1 /*-
2 * Copyright (c) 1998 - 2004 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD: src/sys/dev/ata/ata-chipset.c,v 1.81.2.3 2004/10/10 15:01:47 sos Exp $");
31
32 #include "opt_ata.h"
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/ata.h>
37 #include <sys/bus.h>
38 #include <sys/endian.h>
39 #include <sys/malloc.h>
40 #include <sys/lock.h>
41 #include <sys/mutex.h>
42 #include <sys/sema.h>
43 #include <sys/taskqueue.h>
44 #include <vm/uma.h>
45 #include <machine/stdarg.h>
46 #include <machine/resource.h>
47 #include <machine/bus.h>
48 #include <sys/rman.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/ata/ata-all.h>
52 #include <dev/ata/ata-pci.h>
53
54 /* misc defines */
55 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
56 #define ATAPI_DEVICE(atadev) \
57 ((atadev->unit == ATA_MASTER && \
58 atadev->channel->devices & ATA_ATAPI_MASTER) ||\
59 (atadev->unit == ATA_SLAVE && \
60 atadev->channel->devices & ATA_ATAPI_SLAVE))
61
62 /* local prototypes */
63 static int ata_generic_chipinit(device_t);
64 static void ata_generic_intr(void *);
65 static void ata_generic_setmode(struct ata_device *, int);
66 static int ata_acard_chipinit(device_t);
67 static void ata_acard_intr(void *);
68 static void ata_acard_850_setmode(struct ata_device *, int);
69 static void ata_acard_86X_setmode(struct ata_device *, int);
70 static int ata_ali_chipinit(device_t);
71 static void ata_ali_setmode(struct ata_device *, int);
72 static int ata_amd_chipinit(device_t);
73 static int ata_cyrix_chipinit(device_t);
74 static void ata_cyrix_setmode(struct ata_device *, int);
75 static int ata_cypress_chipinit(device_t);
76 static void ata_cypress_setmode(struct ata_device *, int);
77 static int ata_highpoint_chipinit(device_t);
78 static void ata_highpoint_intr(void *);
79 static void ata_highpoint_setmode(struct ata_device *, int);
80 static int ata_highpoint_check_80pin(struct ata_device *, int);
81 static int ata_intel_chipinit(device_t);
82 static void ata_intel_intr(void *);
83 static void ata_intel_reset(struct ata_channel *);
84 static void ata_intel_old_setmode(struct ata_device *, int);
85 static void ata_intel_new_setmode(struct ata_device *, int);
86 static int ata_national_chipinit(device_t);
87 static void ata_national_setmode(struct ata_device *, int);
88 static int ata_nvidia_chipinit(device_t);
89 static int ata_via_chipinit(device_t);
90 static void ata_via_family_setmode(struct ata_device *, int);
91 static void ata_via_southbridge_fixup(device_t);
92 static int ata_promise_chipinit(device_t);
93 static int ata_promise_mio_allocate(device_t, struct ata_channel *);
94 static void ata_promise_mio_intr(void *);
95 static void ata_promise_sx4_intr(void *);
96 static void ata_promise_mio_dmainit(struct ata_channel *);
97 static void ata_promise_mio_reset(struct ata_channel *ch);
98 static int ata_promise_mio_command(struct ata_device *atadev, u_int8_t command, u_int64_t lba, u_int16_t count, u_int16_t feature);
99 static int ata_promise_sx4_command(struct ata_device *atadev, u_int8_t command, u_int64_t lba, u_int16_t count, u_int16_t feature);
100 static int ata_promise_apkt(u_int8_t *bytep, struct ata_device *atadev, u_int8_t command, u_int64_t lba, u_int16_t count, u_int16_t feature);
101 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt);
102 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr);
103 static void ata_promise_tx2_intr(void *);
104 static void ata_promise_old_intr(void *);
105 static void ata_promise_new_dmainit(struct ata_channel *);
106 static void ata_promise_setmode(struct ata_device *, int);
107 static int ata_serverworks_chipinit(device_t);
108 static void ata_serverworks_setmode(struct ata_device *, int);
109 static int ata_sii_chipinit(device_t);
110 static int ata_sii_allocate(device_t, struct ata_channel *);
111 static void ata_sii_reset(struct ata_channel *);
112 static void ata_sii_intr(void *);
113 static void ata_cmd_intr(void *);
114 static void ata_cmd_old_intr(void *);
115 static void ata_sii_setmode(struct ata_device *, int);
116 static void ata_cmd_setmode(struct ata_device *, int);
117 static int ata_sis_chipinit(device_t);
118 static void ata_sis_setmode(struct ata_device *, int);
119 static int ata_check_80pin(struct ata_device *, int);
120 static struct ata_chip_id *ata_find_chip(device_t, struct ata_chip_id *, int);
121 static struct ata_chip_id *ata_match_chip(device_t, struct ata_chip_id *);
122 static int ata_setup_interrupt(device_t);
123 static int ata_serialize(struct ata_channel *, int);
124 static int ata_mode2idx(int);
125
126 /* generic or unknown ATA chipset init code */
127 int
128 ata_generic_ident(device_t dev)
129 {
130 struct ata_pci_controller *ctlr = device_get_softc(dev);
131
132 device_set_desc(dev, "GENERIC ATA controller");
133 ctlr->chipinit = ata_generic_chipinit;
134 return 0;
135 }
136
137 static int
138 ata_generic_chipinit(device_t dev)
139 {
140 struct ata_pci_controller *ctlr = device_get_softc(dev);
141
142 if (ata_setup_interrupt(dev))
143 return ENXIO;
144 ctlr->setmode = ata_generic_setmode;
145 return 0;
146 }
147
148 static void
149 ata_generic_intr(void *data)
150 {
151 struct ata_pci_controller *ctlr = data;
152 struct ata_channel *ch;
153 int unit;
154
155 /* implement this as a toggle instead to balance load XXX */
156 for (unit = 0; unit < 2; unit++) {
157 if (!(ch = ctlr->interrupt[unit].argument))
158 continue;
159 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
160 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
161
162 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
163 ATA_BMSTAT_INTERRUPT)
164 continue;
165 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
166 DELAY(1);
167 }
168 ctlr->interrupt[unit].function(ch);
169 }
170 }
171
172 static void
173 ata_generic_setmode(struct ata_device *atadev, int mode)
174 {
175 mode = ata_limit_mode(atadev, mode, ATA_UDMA2);
176 mode = ata_check_80pin(atadev, mode);
177 if (!ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
178 atadev->mode = mode;
179 }
180
181 static void
182 ata_sata_setmode(struct ata_device *atadev, int mode)
183 {
184 /*
185 * if we detect that the device isn't a real SATA device we limit
186 * the transfer mode to UDMA5/ATA100.
187 * this works around the problems some devices has with the
188 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133.
189 */
190 if (atadev->param->satacapabilities != 0x0000 &&
191 atadev->param->satacapabilities != 0xffff) {
192 if (!ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
193 ata_limit_mode(atadev, mode, ATA_UDMA6)))
194 atadev->mode = ATA_SA150;
195 }
196 else {
197 mode = ata_limit_mode(atadev, mode, ATA_UDMA5);
198 if (!ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
199 atadev->mode = mode;
200 }
201 }
202
203 /*
204 * Acard chipset support functions
205 */
206 int
207 ata_acard_ident(device_t dev)
208 {
209 struct ata_pci_controller *ctlr = device_get_softc(dev);
210 struct ata_chip_id *idx;
211 static struct ata_chip_id ids[] =
212 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "Acard ATP850" },
213 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "Acard ATP860A" },
214 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "Acard ATP860R" },
215 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "Acard ATP865A" },
216 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "Acard ATP865R" },
217 { 0, 0, 0, 0, 0, 0}};
218 char buffer[64];
219
220 if (!(idx = ata_match_chip(dev, ids)))
221 return ENXIO;
222
223 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
224 device_set_desc_copy(dev, buffer);
225 ctlr->chip = idx;
226 ctlr->chipinit = ata_acard_chipinit;
227 return 0;
228 }
229
230 static int
231 ata_acard_chipinit(device_t dev)
232 {
233 struct ata_pci_controller *ctlr = device_get_softc(dev);
234 int rid = ATA_IRQ_RID;
235
236 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
237 RF_SHAREABLE | RF_ACTIVE))) {
238 device_printf(dev, "unable to map interrupt\n");
239 return ENXIO;
240 }
241 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
242 ata_acard_intr, ctlr, &ctlr->handle))) {
243 device_printf(dev, "unable to setup interrupt\n");
244 return ENXIO;
245 }
246 if (ctlr->chip->cfg1 == ATPOLD) {
247 ctlr->setmode = ata_acard_850_setmode;
248 ctlr->locking = ata_serialize;
249 }
250 else
251 ctlr->setmode = ata_acard_86X_setmode;
252 return 0;
253 }
254
255 static void
256 ata_acard_intr(void *data)
257 {
258 struct ata_pci_controller *ctlr = data;
259 struct ata_channel *ch;
260 int unit;
261
262 /* implement this as a toggle instead to balance load XXX */
263 for (unit = 0; unit < 2; unit++) {
264 if (!(ch = ctlr->interrupt[unit].argument))
265 continue;
266 if (ctlr->chip->cfg1 == ATPOLD && ch->locking(ch, ATA_LF_WHICH) != unit)
267 continue;
268 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
269 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
270
271 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
272 ATA_BMSTAT_INTERRUPT)
273 continue;
274 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
275 DELAY(1);
276 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
277 ATA_IDX_INB(ch, ATA_BMCMD_PORT)&~ATA_BMCMD_START_STOP);
278 DELAY(1);
279 }
280 ctlr->interrupt[unit].function(ch);
281 }
282 }
283
284 static void
285 ata_acard_850_setmode(struct ata_device *atadev, int mode)
286 {
287 device_t parent = device_get_parent(atadev->channel->dev);
288 struct ata_pci_controller *ctlr = device_get_softc(parent);
289 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
290 int error;
291
292 mode = ata_limit_mode(atadev, mode,
293 ATAPI_DEVICE(atadev)?ATA_PIO_MAX:ctlr->chip->max_dma);
294
295 /* XXX missing WDMA0+1 + PIO modes */
296 if (mode >= ATA_WDMA2) {
297 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,mode);
298 if (bootverbose)
299 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
300 (error) ? "FAILURE " : "",
301 ata_mode2str(mode), ctlr->chip->text);
302 if (!error) {
303 u_int8_t reg54 = pci_read_config(parent, 0x54, 1);
304
305 reg54 &= ~(0x03 << (devno << 1));
306 if (mode >= ATA_UDMA0)
307 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1));
308 pci_write_config(parent, 0x54, reg54, 1);
309 pci_write_config(parent, 0x4a, 0xa6, 1);
310 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
311 atadev->mode = mode;
312 return;
313 }
314 }
315 /* we could set PIO mode timings, but we assume the BIOS did that */
316 }
317
318 static void
319 ata_acard_86X_setmode(struct ata_device *atadev, int mode)
320 {
321 device_t parent = device_get_parent(atadev->channel->dev);
322 struct ata_pci_controller *ctlr = device_get_softc(parent);
323 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
324 int error;
325
326
327 mode = ata_limit_mode(atadev, mode,
328 ATAPI_DEVICE(atadev)?ATA_PIO_MAX:ctlr->chip->max_dma);
329
330 mode = ata_check_80pin(atadev, mode);
331
332 /* XXX missing WDMA0+1 + PIO modes */
333 if (mode >= ATA_WDMA2) {
334 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,mode);
335 if (bootverbose)
336 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
337 (error) ? "FAILURE " : "",
338 ata_mode2str(mode), ctlr->chip->text);
339 if (!error) {
340 u_int16_t reg44 = pci_read_config(parent, 0x44, 2);
341
342 reg44 &= ~(0x000f << (devno << 2));
343 if (mode >= ATA_UDMA0)
344 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2));
345 pci_write_config(parent, 0x44, reg44, 2);
346 pci_write_config(parent, 0x4a, 0xa6, 1);
347 pci_write_config(parent, 0x40 + devno, 0x31, 1);
348 atadev->mode = mode;
349 return;
350 }
351 }
352 /* we could set PIO mode timings, but we assume the BIOS did that */
353 }
354
355 /*
356 * Acer Labs Inc (ALI) chipset support functions
357 */
358 int
359 ata_ali_ident(device_t dev)
360 {
361 struct ata_pci_controller *ctlr = device_get_softc(dev);
362 struct ata_chip_id *idx;
363 static struct ata_chip_id ids[] =
364 {{ ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "AcerLabs Aladdin" },
365 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "AcerLabs Aladdin" },
366 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "AcerLabs Aladdin" },
367 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "AcerLabs Aladdin" },
368 { 0, 0, 0, 0, 0, 0}};
369 char buffer[64];
370
371 if (!(idx = ata_match_chip(dev, ids)))
372 return ENXIO;
373
374 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
375 device_set_desc_copy(dev, buffer);
376 ctlr->chip = idx;
377 ctlr->chipinit = ata_ali_chipinit;
378 return 0;
379 }
380
381 static int
382 ata_ali_chipinit(device_t dev)
383 {
384 struct ata_pci_controller *ctlr = device_get_softc(dev);
385
386 if (ata_setup_interrupt(dev))
387 return ENXIO;
388
389 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
390 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
391
392 /* enable cable detection and UDMA support on newer chips */
393 if (ctlr->chip->cfg2 & ALINEW)
394 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1);
395 ctlr->setmode = ata_ali_setmode;
396 return 0;
397 }
398
399 static void
400 ata_ali_setmode(struct ata_device *atadev, int mode)
401 {
402 device_t parent = device_get_parent(atadev->channel->dev);
403 struct ata_pci_controller *ctlr = device_get_softc(parent);
404 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
405 int error;
406
407 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
408
409 if (ctlr->chip->cfg2 & ALINEW) {
410 if (mode > ATA_UDMA2 &&
411 pci_read_config(parent, 0x4a, 1) & (1 << atadev->channel->unit)) {
412 ata_prtdev(atadev,
413 "DMA limited to UDMA33, non-ATA66 cable or device\n");
414 mode = ATA_UDMA2;
415 }
416 }
417 else
418 mode = ata_check_80pin(atadev, mode);
419
420 if (ctlr->chip->cfg2 & ALIOLD) {
421 /* doesn't support ATAPI DMA on write */
422 atadev->channel->flags |= ATA_ATAPI_DMA_RO;
423 if (atadev->channel->devices & ATA_ATAPI_MASTER &&
424 atadev->channel->devices & ATA_ATAPI_SLAVE) {
425 /* doesn't support ATAPI DMA on two ATAPI devices */
426 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n");
427 mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX);
428 }
429 }
430
431 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
432
433 if (bootverbose)
434 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
435 (error) ? "FAILURE " : "",
436 ata_mode2str(mode), ctlr->chip->text);
437 if (!error) {
438 if (mode >= ATA_UDMA0) {
439 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f};
440 u_int32_t word54 = pci_read_config(parent, 0x54, 4);
441
442 word54 &= ~(0x000f000f << (devno << 2));
443 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
444 pci_write_config(parent, 0x54, word54, 4);
445 pci_write_config(parent, 0x58 + (atadev->channel->unit << 2),
446 0x00310001, 4);
447 }
448 else {
449 u_int32_t piotimings[] =
450 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
451 0x00310001, 0x00440001, 0x00330001, 0x00310001};
452
453 pci_write_config(parent, 0x54, pci_read_config(parent, 0x54, 4) &
454 ~(0x0008000f << (devno << 2)), 4);
455 pci_write_config(parent, 0x58 + (atadev->channel->unit << 2),
456 piotimings[ata_mode2idx(mode)], 4);
457 }
458 atadev->mode = mode;
459 }
460 }
461
462 /*
463 * American Micro Devices (AMD) support functions
464 */
465 int
466 ata_amd_ident(device_t dev)
467 {
468 struct ata_pci_controller *ctlr = device_get_softc(dev);
469 struct ata_chip_id *idx;
470 static struct ata_chip_id ids[] =
471 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "AMD 756" },
472 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "AMD 766" },
473 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "AMD 768" },
474 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "AMD 8111" },
475 { 0, 0, 0, 0, 0, 0}};
476 char buffer[64];
477
478 if (!(idx = ata_match_chip(dev, ids)))
479 return ENXIO;
480
481 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
482 device_set_desc_copy(dev, buffer);
483 ctlr->chip = idx;
484 ctlr->chipinit = ata_amd_chipinit;
485 return 0;
486 }
487
488 static int
489 ata_amd_chipinit(device_t dev)
490 {
491 struct ata_pci_controller *ctlr = device_get_softc(dev);
492
493 if (ata_setup_interrupt(dev))
494 return ENXIO;
495
496 /* disable/set prefetch, postwrite */
497 if (ctlr->chip->cfg2 & AMDBUG)
498 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1);
499 else
500 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
501
502 ctlr->setmode = ata_via_family_setmode;
503 return 0;
504 }
505
506 /*
507 * Cyrix chipset support functions
508 */
509 int
510 ata_cyrix_ident(device_t dev)
511 {
512 struct ata_pci_controller *ctlr = device_get_softc(dev);
513
514 if (pci_get_devid(dev) == ATA_CYRIX_5530) {
515 device_set_desc(dev, "Cyrix 5530 ATA33 controller");
516 ctlr->chipinit = ata_cyrix_chipinit;
517 return 0;
518 }
519 return ENXIO;
520 }
521
522 static int
523 ata_cyrix_chipinit(device_t dev)
524 {
525 struct ata_pci_controller *ctlr = device_get_softc(dev);
526
527 if (ata_setup_interrupt(dev))
528 return ENXIO;
529
530 if (ctlr->r_res1)
531 ctlr->setmode = ata_cyrix_setmode;
532 else
533 ctlr->setmode = ata_generic_setmode;
534 return 0;
535 }
536
537 static void
538 ata_cyrix_setmode(struct ata_device *atadev, int mode)
539 {
540 struct ata_channel *ch = atadev->channel;
541 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
542 u_int32_t piotiming[] =
543 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
544 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
545 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
546 int error;
547
548 atadev->channel->dma->alignment = 16;
549 atadev->channel->dma->max_iosize = 126 * DEV_BSIZE;
550
551 mode = ata_limit_mode(atadev, mode, ATA_UDMA2);
552
553 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
554
555 if (bootverbose)
556 ata_prtdev(atadev, "%ssetting %s on Cyrix chip\n",
557 (error) ? "FAILURE " : "", ata_mode2str(mode));
558 if (!error) {
559 if (mode >= ATA_UDMA0) {
560 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
561 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]);
562 }
563 else if (mode >= ATA_WDMA0) {
564 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
565 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]);
566 }
567 else {
568 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
569 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]);
570 }
571 atadev->mode = mode;
572 }
573 }
574
575 /*
576 * Cypress chipset support functions
577 */
578 int
579 ata_cypress_ident(device_t dev)
580 {
581 struct ata_pci_controller *ctlr = device_get_softc(dev);
582
583 /*
584 * the Cypress chip is a mess, it contains two ATA functions, but
585 * both channels are visible on the first one.
586 * simply ignore the second function for now, as the right
587 * solution (ignoring the second channel on the first function)
588 * doesn't work with the crappy ATA interrupt setup on the alpha.
589 */
590 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 &&
591 pci_get_function(dev) == 1 &&
592 pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
593 device_set_desc(dev, "Cypress 82C693 ATA controller");
594 ctlr->chipinit = ata_cypress_chipinit;
595 return 0;
596 }
597 return ENXIO;
598 }
599
600 static int
601 ata_cypress_chipinit(device_t dev)
602 {
603 struct ata_pci_controller *ctlr = device_get_softc(dev);
604
605 if (ata_setup_interrupt(dev))
606 return ENXIO;
607
608 ctlr->setmode = ata_cypress_setmode;
609 return 0;
610 }
611
612 static void
613 ata_cypress_setmode(struct ata_device *atadev, int mode)
614 {
615 device_t parent = device_get_parent(atadev->channel->dev);
616 int error;
617
618 mode = ata_limit_mode(atadev, mode, ATA_WDMA2);
619
620 /* XXX missing WDMA0+1 + PIO modes */
621 if (mode == ATA_WDMA2) {
622 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,mode);
623 if (bootverbose)
624 ata_prtdev(atadev, "%ssetting WDMA2 on Cypress chip\n",
625 error ? "FAILURE " : "");
626 if (!error) {
627 pci_write_config(parent, atadev->channel->unit?0x4e:0x4c,0x2020,2);
628 atadev->mode = mode;
629 return;
630 }
631 }
632 /* we could set PIO mode timings, but we assume the BIOS did that */
633 }
634
635 /*
636 * HighPoint chipset support functions
637 */
638 int
639 ata_highpoint_ident(device_t dev)
640 {
641 struct ata_pci_controller *ctlr = device_get_softc(dev);
642 struct ata_chip_id *idx;
643 static struct ata_chip_id ids[] =
644 {{ ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT372" },
645 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HighPoint HPT370" },
646 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HighPoint HPT368" },
647 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HighPoint HPT366" },
648 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT372" },
649 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT302" },
650 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT371" },
651 { ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HighPoint HPT374" },
652 { 0, 0, 0, 0, 0, 0}};
653 char buffer[64];
654
655 if (!(idx = ata_match_chip(dev, ids)))
656 return ENXIO;
657
658 strcpy(buffer, idx->text);
659 if (idx->cfg1 == HPT374) {
660 if (pci_get_function(dev) == 0)
661 strcat(buffer, " (channel 0+1)");
662 else if (pci_get_function(dev) == 1)
663 strcat(buffer, " (channel 2+3)");
664 }
665 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
666 device_set_desc_copy(dev, buffer);
667 ctlr->chip = idx;
668 ctlr->chipinit = ata_highpoint_chipinit;
669 return 0;
670 }
671
672 static int
673 ata_highpoint_chipinit(device_t dev)
674 {
675 struct ata_pci_controller *ctlr = device_get_softc(dev);
676 int rid = ATA_IRQ_RID;
677
678 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
679 RF_SHAREABLE | RF_ACTIVE))) {
680 device_printf(dev, "unable to map interrupt\n");
681 return ENXIO;
682 }
683 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
684 ata_highpoint_intr, ctlr, &ctlr->handle))) {
685 device_printf(dev, "unable to setup interrupt\n");
686 return ENXIO;
687 }
688
689 if (ctlr->chip->cfg2 == HPTOLD) {
690 /* disable interrupt prediction */
691 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
692 }
693 else {
694 /* disable interrupt prediction */
695 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
696 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
697
698 /* enable interrupts */
699 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
700
701 /* set clocks etc */
702 if (ctlr->chip->cfg1 < HPT372)
703 pci_write_config(dev, 0x5b, 0x22, 1);
704 else
705 pci_write_config(dev, 0x5b,
706 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
707 }
708 ctlr->setmode = ata_highpoint_setmode;
709 return 0;
710 }
711
712 static void
713 ata_highpoint_intr(void *data)
714 {
715 struct ata_pci_controller *ctlr = data;
716 struct ata_channel *ch;
717 int unit;
718
719 /* implement this as a toggle instead to balance load XXX */
720 for (unit = 0; unit < 2; unit++) {
721 if (!(ch = ctlr->interrupt[unit].argument))
722 continue;
723 if (ch->dma) {
724 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
725
726 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
727 ATA_BMSTAT_INTERRUPT)
728 continue;
729 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
730 DELAY(1);
731 }
732 ctlr->interrupt[unit].function(ch);
733 }
734 }
735
736 static void
737 ata_highpoint_setmode(struct ata_device *atadev, int mode)
738 {
739 device_t parent = device_get_parent(atadev->channel->dev);
740 struct ata_pci_controller *ctlr = device_get_softc(parent);
741 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
742 int error;
743 u_int32_t timings33[][4] = {
744 /* HPT366 HPT370 HPT372 HPT374 mode */
745 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
746 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
747 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
748 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
749 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
750 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
751 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
752 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
753 { 0x10c8a731, 0x16514e31, 0x1c82dc62, 0x121882ea }, /* UDMA 0 */
754 { 0x10cba731, 0x164d4e31, 0x1c9adc62, 0x12148254 }, /* UDMA 1 */
755 { 0x10caa731, 0x16494e31, 0x1c91dc62, 0x120c8242 }, /* UDMA 2 */
756 { 0x10cfa731, 0x166d4e31, 0x1c8edc62, 0x128c8242 }, /* UDMA 3 */
757 { 0x10c9a731, 0x16454e31, 0x1c8ddc62, 0x12ac8242 }, /* UDMA 4 */
758 { 0, 0x16454e31, 0x1c6ddc62, 0x12848242 }, /* UDMA 5 */
759 { 0, 0, 0x1c81dc62, 0x12448242 } /* UDMA 6 */
760 };
761
762 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
763
764 if (ctlr->chip->cfg1 == HPT366 && ATAPI_DEVICE(atadev))
765 mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX);
766
767 mode = ata_highpoint_check_80pin(atadev, mode);
768
769 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
770
771 if (bootverbose)
772 ata_prtdev(atadev, "%ssetting %s on HighPoint chip\n",
773 (error) ? "FAILURE " : "", ata_mode2str(mode));
774 if (!error)
775 pci_write_config(parent, 0x40 + (devno << 2),
776 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
777 atadev->mode = mode;
778 }
779
780 static int
781 ata_highpoint_check_80pin(struct ata_device *atadev, int mode)
782 {
783 device_t parent = device_get_parent(atadev->channel->dev);
784 struct ata_pci_controller *ctlr = device_get_softc(parent);
785 u_int8_t reg, val, res;
786
787 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(parent) == 1) {
788 reg = atadev->channel->unit ? 0x57 : 0x53;
789 val = pci_read_config(parent, reg, 1);
790 pci_write_config(parent, reg, val | 0x80, 1);
791 }
792 else {
793 reg = 0x5b;
794 val = pci_read_config(parent, reg, 1);
795 pci_write_config(parent, reg, val & 0xfe, 1);
796 }
797 res = pci_read_config(parent, 0x5a, 1) & (atadev->channel->unit ? 0x1:0x2);
798 pci_write_config(parent, reg, val, 1);
799
800 if (mode > ATA_UDMA2 && res) {
801 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
802 mode = ATA_UDMA2;
803 }
804 return mode;
805 }
806
807 /*
808 * Intel chipset support functions
809 */
810 int
811 ata_intel_ident(device_t dev)
812 {
813 struct ata_pci_controller *ctlr = device_get_softc(dev);
814 struct ata_chip_id *idx;
815 static struct ata_chip_id ids[] =
816 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "Intel PIIX" },
817 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "Intel PIIX3" },
818 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
819 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
820 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
821 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "Intel ICH0" },
822 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "Intel ICH" },
823 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "Intel ICH" },
824 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "Intel ICH2" },
825 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH2" },
826 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "Intel ICH3" },
827 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH3" },
828 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "Intel ICH4" },
829 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH4" },
830 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "Intel ICH5" },
831 { ATA_I82801EB_S1,0, 0, 0x00, ATA_SA150, "Intel ICH5" },
832 { ATA_I82801EB_R1,0, 0, 0x00, ATA_SA150, "Intel ICH5" },
833 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "Intel 6300ESB" },
834 { ATA_I6300ESB_S1,0, 0, 0x00, ATA_SA150, "Intel 6300ESB" },
835 { ATA_I6300ESB_R1,0, 0, 0x00, ATA_SA150, "Intel 6300ESB" },
836 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "Intel ICH6" },
837 { ATA_I82801FB_S1,0, 0, 0x00, ATA_SA150, "Intel ICH6" },
838 { ATA_I82801FB_R1,0, 0, 0x00, ATA_SA150, "Intel ICH6" },
839 { 0, 0, 0, 0, 0, 0}};
840 char buffer[64];
841
842 if (!(idx = ata_match_chip(dev, ids)))
843 return ENXIO;
844
845 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
846 device_set_desc_copy(dev, buffer);
847 ctlr->chip = idx;
848 ctlr->chipinit = ata_intel_chipinit;
849 return 0;
850 }
851
852 static int
853 ata_intel_chipinit(device_t dev)
854 {
855 struct ata_pci_controller *ctlr = device_get_softc(dev);
856 int rid = ATA_IRQ_RID;
857
858 if (!ata_legacy(dev)) {
859 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
860 RF_SHAREABLE | RF_ACTIVE))) {
861 device_printf(dev, "unable to map interrupt\n");
862 return ENXIO;
863 }
864 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
865 ata_intel_intr, ctlr, &ctlr->handle))) {
866 device_printf(dev, "unable to setup interrupt\n");
867 return ENXIO;
868 }
869 }
870
871 if (ctlr->chip->chipid == ATA_I82371FB) {
872 ctlr->setmode = ata_intel_old_setmode;
873 }
874 else if (ctlr->chip->max_dma < ATA_SA150) {
875 ctlr->setmode = ata_intel_new_setmode;
876 }
877 else {
878 pci_write_config(dev, PCIR_COMMAND,
879 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
880 ctlr->reset = ata_intel_reset;
881 ctlr->setmode = ata_sata_setmode;
882 }
883 return 0;
884 }
885
886 static void
887 ata_intel_intr(void *data)
888 {
889 struct ata_pci_controller *ctlr = data;
890 struct ata_channel *ch;
891 int unit;
892
893 /* implement this as a toggle instead to balance load XXX */
894 for (unit = 0; unit < 2; unit++) {
895 if (!(ch = ctlr->interrupt[unit].argument))
896 continue;
897 if (ch->dma) {
898 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
899
900 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
901 ATA_BMSTAT_INTERRUPT)
902 continue;
903 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
904 DELAY(1);
905 }
906 ctlr->interrupt[unit].function(ch);
907 }
908 }
909
910 static void
911 ata_intel_old_setmode(struct ata_device *atadev, int mode)
912 {
913 /* NOT YET */
914 }
915
916 static void
917 ata_intel_reset(struct ata_channel *ch)
918 {
919 device_t parent = device_get_parent(ch->dev);
920 int mask, timeout = 100;
921
922 if (pci_read_config(parent, 0x90, 1) & 0x04)
923 mask = 0x0003;
924 else
925 mask = (0x0001 << ch->unit);
926
927 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2);
928 DELAY(10);
929 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2);
930
931 while (timeout--) {
932 ata_udelay(10000);
933 if ((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) {
934 ata_udelay(10000);
935 return;
936 }
937 }
938 }
939
940 static void
941 ata_intel_new_setmode(struct ata_device *atadev, int mode)
942 {
943 device_t parent = device_get_parent(atadev->channel->dev);
944 struct ata_pci_controller *ctlr = device_get_softc(parent);
945 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
946 u_int32_t reg40 = pci_read_config(parent, 0x40, 4);
947 u_int8_t reg44 = pci_read_config(parent, 0x44, 1);
948 u_int8_t reg48 = pci_read_config(parent, 0x48, 1);
949 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2);
950 u_int16_t reg54 = pci_read_config(parent, 0x54, 2);
951 u_int32_t mask40 = 0, new40 = 0;
952 u_int8_t mask44 = 0, new44 = 0;
953 int error;
954 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
955 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
956
957 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
958
959 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
960 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
961 mode = ATA_UDMA2;
962 }
963
964 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
965
966 if (bootverbose)
967 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
968 (error) ? "FAILURE " : "",
969 ata_mode2str(mode), ctlr->chip->text);
970 if (error)
971 return;
972
973 if (mode >= ATA_UDMA0) {
974 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2);
975 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno<<2))) |
976 (0x01 + !(mode & 0x01)), 2);
977 }
978 else {
979 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2);
980 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))), 2);
981 }
982 reg54 |= 0x0400;
983 if (mode >= ATA_UDMA2)
984 pci_write_config(parent, 0x54, reg54 | (0x1 << devno), 2);
985 else
986 pci_write_config(parent, 0x54, reg54 & ~(0x1 << devno), 2);
987
988 if (mode >= ATA_UDMA5)
989 pci_write_config(parent, 0x54, reg54 | (0x1000 << devno), 2);
990 else
991 pci_write_config(parent, 0x54, reg54 & ~(0x1000 << devno), 2);
992
993 reg40 &= ~0x00ff00ff;
994 reg40 |= 0x40774077;
995
996 if (atadev->unit == ATA_MASTER) {
997 mask40 = 0x3300;
998 new40 = timings[ata_mode2idx(mode)] << 8;
999 }
1000 else {
1001 mask44 = 0x0f;
1002 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
1003 (timings[ata_mode2idx(mode)] & 0x03);
1004 }
1005 if (atadev->channel->unit) {
1006 mask40 <<= 16;
1007 new40 <<= 16;
1008 mask44 <<= 4;
1009 new44 <<= 4;
1010 }
1011 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4);
1012 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1);
1013
1014 atadev->mode = mode;
1015 }
1016
1017 /*
1018 * National chipset support functions
1019 */
1020 int
1021 ata_national_ident(device_t dev)
1022 {
1023 struct ata_pci_controller *ctlr = device_get_softc(dev);
1024
1025 /* this chip is a clone of the Cyrix chip, bugs and all */
1026 if (pci_get_devid(dev) == ATA_SC1100) {
1027 device_set_desc(dev, "National Geode SC1100 ATA33 controller");
1028 ctlr->chipinit = ata_national_chipinit;
1029 return 0;
1030 }
1031 return ENXIO;
1032 }
1033
1034 static device_t nat_host = NULL;
1035
1036 static int
1037 ata_national_chipinit(device_t dev)
1038 {
1039 struct ata_pci_controller *ctlr = device_get_softc(dev);
1040 device_t *children;
1041 int nchildren, i;
1042
1043 if (ata_setup_interrupt(dev))
1044 return ENXIO;
1045
1046 /* locate the ISA part in the southbridge and enable UDMA33 */
1047 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
1048 for (i = 0; i < nchildren; i++) {
1049 if (pci_get_devid(children[i]) == 0x0510100b) {
1050 nat_host = children[i];
1051 break;
1052 }
1053 }
1054 free(children, M_TEMP);
1055 }
1056 ctlr->setmode = ata_national_setmode;
1057 return 0;
1058 }
1059
1060 static void
1061 ata_national_setmode(struct ata_device *atadev, int mode)
1062 {
1063 device_t parent = device_get_parent(atadev->channel->dev);
1064 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
1065 u_int32_t piotiming[] =
1066 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
1067 0x00803020, 0x20102010, 0x00100010,
1068 0x00100010, 0x00100010, 0x00100010 };
1069 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
1070 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
1071 int error;
1072
1073 atadev->channel->dma->alignment = 16;
1074 atadev->channel->dma->max_iosize = 126 * DEV_BSIZE;
1075
1076 mode = ata_limit_mode(atadev, mode, ATA_UDMA2);
1077
1078 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1079
1080 if (bootverbose)
1081 ata_prtdev(atadev, "%s setting %s on National chip\n",
1082 (error) ? "failed" : "success", ata_mode2str(mode));
1083 if (!error) {
1084 if (mode >= ATA_UDMA0) {
1085 pci_write_config(parent, 0x44 + (devno << 3),
1086 udmatiming[mode & ATA_MODE_MASK], 4);
1087 }
1088 else if (mode >= ATA_WDMA0) {
1089 pci_write_config(parent, 0x44 + (devno << 3),
1090 dmatiming[mode & ATA_MODE_MASK], 4);
1091 }
1092 else {
1093 pci_write_config(parent, 0x44 + (devno << 3),
1094 pci_read_config(parent, 0x44 + (devno << 3), 4) |
1095 0x80000000, 4);
1096 }
1097 pci_write_config(parent, 0x40 + (devno << 3),
1098 piotiming[ata_mode2idx(mode)], 4);
1099 atadev->mode = mode;
1100 }
1101 }
1102
1103 /*
1104 * nVidia chipset support functions
1105 */
1106 int
1107 ata_nvidia_ident(device_t dev)
1108 {
1109 struct ata_pci_controller *ctlr = device_get_softc(dev);
1110 struct ata_chip_id *idx;
1111 static struct ata_chip_id ids[] =
1112 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nVidia nForce" },
1113 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce2" },
1114 { ATA_NFORCE2_MCP, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce2 MCP" },
1115 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce3" },
1116 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce3 Pro" },
1117 { ATA_NFORCE3_MCP, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce3 MCP" },
1118 { ATA_NFORCE4, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce4" },
1119 { 0, 0, 0, 0, 0, 0}};
1120 char buffer[64];
1121
1122 if (!(idx = ata_match_chip(dev, ids)))
1123 return ENXIO;
1124
1125 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
1126 device_set_desc_copy(dev, buffer);
1127 ctlr->chip = idx;
1128 ctlr->chipinit = ata_nvidia_chipinit;
1129 return 0;
1130 }
1131
1132 static int
1133 ata_nvidia_chipinit(device_t dev)
1134 {
1135 struct ata_pci_controller *ctlr = device_get_softc(dev);
1136
1137 if (ata_setup_interrupt(dev))
1138 return ENXIO;
1139
1140 /* disable prefetch, postwrite */
1141 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
1142
1143 ctlr->setmode = ata_via_family_setmode;
1144 return 0;
1145 }
1146
1147 /*
1148 * Promise chipset support functions
1149 */
1150 #define ATA_PDC_APKT_OFFSET 0x00000010
1151 #define ATA_PDC_HPKT_OFFSET 0x00000040
1152 #define ATA_PDC_ASG_OFFSET 0x00000080
1153 #define ATA_PDC_LSG_OFFSET 0x000000c0
1154 #define ATA_PDC_HSG_OFFSET 0x00000100
1155 #define ATA_PDC_CHN_OFFSET 0x00000400
1156 #define ATA_PDC_BUF_BASE 0x00400000
1157 #define ATA_PDC_BUF_OFFSET 0x00100000
1158 #define ATA_PDC_MAX_HPKT 8
1159 #define ATA_PDC_WRITE_REG 0x00
1160 #define ATA_PDC_WRITE_CTL 0x0e
1161 #define ATA_PDC_WRITE_END 0x08
1162 #define ATA_PDC_WAIT_NBUSY 0x10
1163 #define ATA_PDC_WAIT_READY 0x18
1164 #define ATA_PDC_1B 0x20
1165 #define ATA_PDC_2B 0x40
1166
1167 struct ata_promise_sx4 {
1168 struct mtx mtx;
1169 u_int32_t array[ATA_PDC_MAX_HPKT];
1170 int head, tail;
1171 int busy;
1172 };
1173
1174 int
1175 ata_promise_ident(device_t dev)
1176 {
1177 struct ata_pci_controller *ctlr = device_get_softc(dev);
1178 struct ata_chip_id *idx;
1179 static struct ata_chip_id ids[] =
1180 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "Promise PDC20246" },
1181 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "Promise PDC20262" },
1182 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "Promise PDC20263" },
1183 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "Promise PDC20265" },
1184 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "Promise PDC20267" },
1185 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "Promise PDC20268" },
1186 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20269" },
1187 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "Promise PDC20270" },
1188 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20271" },
1189 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20275" },
1190 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "Promise PDC20276" },
1191 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20277" },
1192 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20318" },
1193 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20319" },
1194 { ATA_PDC20371, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20371" },
1195 { ATA_PDC20375, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20375" },
1196 { ATA_PDC20376, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20376" },
1197 { ATA_PDC20377, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20377" },
1198 { ATA_PDC20378, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20378" },
1199 { ATA_PDC20379, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20379" },
1200 { ATA_PDC20617, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20617" },
1201 { ATA_PDC20618, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20618" },
1202 { ATA_PDC20619, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20619" },
1203 { ATA_PDC20620, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20620" },
1204 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "Promise PDC20621" },
1205 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "Promise PDC20622" },
1206 { 0, 0, 0, 0, 0, 0}};
1207 char buffer[64];
1208 uintptr_t devid = 0;
1209
1210 if (!(idx = ata_match_chip(dev, ids)))
1211 return ENXIO;
1212
1213 /* if we are on a SuperTrak SX6000 dont attach */
1214 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
1215 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
1216 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
1217 devid == ATA_I960RM)
1218 return ENXIO;
1219
1220 strcpy(buffer, idx->text);
1221
1222 /* if we are on a FastTrak TX4, adjust the interrupt resource */
1223 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
1224 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
1225 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
1226 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) {
1227 static long start = 0, end = 0;
1228
1229 if (pci_get_slot(dev) == 1) {
1230 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
1231 strcat(buffer, " (channel 0+1)");
1232 }
1233 else if (pci_get_slot(dev) == 2 && start && end) {
1234 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
1235 start = end = 0;
1236 strcat(buffer, " (channel 2+3)");
1237 }
1238 else {
1239 start = end = 0;
1240 }
1241 }
1242 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
1243 device_set_desc_copy(dev, buffer);
1244 ctlr->chip = idx;
1245 ctlr->chipinit = ata_promise_chipinit;
1246 return 0;
1247 }
1248
1249 static int
1250 ata_promise_chipinit(device_t dev)
1251 {
1252 struct ata_pci_controller *ctlr = device_get_softc(dev);
1253 int rid = ATA_IRQ_RID;
1254
1255 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1256 RF_SHAREABLE | RF_ACTIVE))) {
1257 device_printf(dev, "unable to map interrupt\n");
1258 return ENXIO;
1259 }
1260
1261 switch (ctlr->chip->cfg1) {
1262 case PRNEW:
1263 /* setup clocks */
1264 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a);
1265
1266 ctlr->dmainit = ata_promise_new_dmainit;
1267 /* FALLTHROUGH */
1268
1269 case PROLD:
1270 /* enable burst mode */
1271 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01);
1272
1273 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1274 ata_promise_old_intr, ctlr, &ctlr->handle))) {
1275 device_printf(dev, "unable to setup interrupt\n");
1276 return ENXIO;
1277 }
1278 break;
1279
1280 case PRTX:
1281 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1282 ata_promise_tx2_intr, ctlr, &ctlr->handle))) {
1283 device_printf(dev, "unable to setup interrupt\n");
1284 return ENXIO;
1285 }
1286 break;
1287
1288 case PRMIO:
1289 // if (ctlr->r_res1)
1290 // bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
1291 ctlr->r_type1 = SYS_RES_MEMORY;
1292 ctlr->r_rid1 = PCIR_BAR(4);
1293 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
1294 &ctlr->r_rid1, RF_ACTIVE)))
1295 return ENXIO;
1296
1297 ctlr->r_type2 = SYS_RES_MEMORY;
1298 ctlr->r_rid2 = PCIR_BAR(3);
1299 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1300 &ctlr->r_rid2, RF_ACTIVE)))
1301 return ENXIO;
1302
1303 ctlr->reset = ata_promise_mio_reset;
1304 ctlr->dmainit = ata_promise_mio_dmainit;
1305 ctlr->allocate = ata_promise_mio_allocate;
1306
1307 if (ctlr->chip->cfg2 & PRDUAL) {
1308 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) +
1309 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2;
1310 }
1311 else if (ctlr->chip->cfg2 & PRSATA) {
1312 ATA_OUTL(ctlr->r_res2, 0x06c, 0x000000ff);
1313 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 3;
1314 }
1315 else
1316 ctlr->channels = 4;
1317
1318 if (ctlr->chip->cfg2 & PRSX4X) {
1319 struct ata_promise_sx4 *hpkt;
1320 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080);
1321
1322 /* print info about cache memory */
1323 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n",
1324 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4,
1325 ((dimm >> 24) & 0xff),
1326 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ?
1327 " ECC enabled" : "" );
1328
1329 ATA_OUTL(ctlr->r_res2, 0x000c000c,
1330 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000));
1331
1332 ctlr->driver = malloc(sizeof(struct ata_promise_sx4),
1333 M_TEMP, M_NOWAIT | M_ZERO);
1334 hpkt = ctlr->driver;
1335 mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF);
1336 hpkt->busy = hpkt->head = hpkt->tail = 0;
1337
1338 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1339 ata_promise_sx4_intr, ctlr, &ctlr->handle))) {
1340 device_printf(dev, "unable to setup interrupt\n");
1341 return ENXIO;
1342 }
1343 }
1344 else {
1345 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1346 ata_promise_mio_intr, ctlr, &ctlr->handle))) {
1347 device_printf(dev, "unable to setup interrupt\n");
1348 return ENXIO;
1349 }
1350 }
1351 break;
1352 }
1353 if (ctlr->chip->max_dma >= ATA_SA150)
1354 ctlr->setmode = ata_sata_setmode;
1355 else
1356 ctlr->setmode = ata_promise_setmode;
1357 return 0;
1358 }
1359
1360 static int
1361 ata_promise_mio_allocate(device_t dev, struct ata_channel *ch)
1362 {
1363 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1364 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0;
1365 int i;
1366
1367 for (i = ATA_DATA; i <= ATA_STATUS; i++) {
1368 ch->r_io[i].res = ctlr->r_res2;
1369 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7);
1370 }
1371 ch->r_io[ATA_ALTSTAT].res = ctlr->r_res2;
1372 ch->r_io[ATA_ALTSTAT].offset = offset + 0x0238 + (ch->unit << 7);
1373 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
1374 ch->flags |= ATA_USE_16BIT;
1375
1376 ata_generic_hw(ch);
1377 if (ctlr->chip->cfg2 & PRSX4X)
1378 ch->hw.command = ata_promise_sx4_command;
1379 else
1380 ch->hw.command = ata_promise_mio_command;
1381 return 0;
1382 }
1383
1384 static void
1385 ata_promise_mio_intr(void *data)
1386 {
1387 struct ata_pci_controller *ctlr = data;
1388 struct ata_channel *ch;
1389 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x00040);
1390 u_int32_t status = 0;
1391 int unit;
1392
1393 if (ctlr->chip->cfg2 & PRSATA) {
1394 status = ATA_INL(ctlr->r_res2, 0x06c);
1395 ATA_OUTL(ctlr->r_res2, 0x06c, status & 0x000000ff);
1396 }
1397
1398 for (unit = 0; unit < ctlr->channels; unit++) {
1399 if (status & (0x00000011 << unit))
1400 if ((ch = ctlr->interrupt[unit].argument) && ch->reset)
1401 ch->reset(ch);
1402 if (vector & (1 << (unit + 1)))
1403 if ((ch = ctlr->interrupt[unit].argument))
1404 ctlr->interrupt[unit].function(ch);
1405 }
1406 }
1407
1408 static void
1409 ata_promise_sx4_intr(void *data)
1410 {
1411 struct ata_pci_controller *ctlr = data;
1412 struct ata_channel *ch;
1413 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480);
1414 int unit;
1415
1416 for (unit = 0; unit < ctlr->channels; unit++) {
1417 if (vector & (1 << (unit + 1)))
1418 if ((ch = ctlr->interrupt[unit].argument))
1419 ctlr->interrupt[unit].function(ch);
1420 if (vector & (1 << (unit + 5)))
1421 if ((ch = ctlr->interrupt[unit].argument))
1422 ata_promise_queue_hpkt(ctlr,
1423 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
1424 ATA_PDC_HPKT_OFFSET));
1425 if (vector & (1 << (unit + 9))) {
1426 ata_promise_next_hpkt(ctlr);
1427 if ((ch = ctlr->interrupt[unit].argument))
1428 ctlr->interrupt[unit].function(ch);
1429 }
1430 if (vector & (1 << (unit + 13))) {
1431 ata_promise_next_hpkt(ctlr);
1432 if ((ch = ctlr->interrupt[unit].argument))
1433 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
1434 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
1435 ATA_PDC_APKT_OFFSET));
1436 }
1437 }
1438 }
1439
1440 static int
1441 ata_promise_mio_dmastart(struct ata_channel *ch)
1442 {
1443 ch->flags |= ATA_DMA_ACTIVE;
1444 return 0;
1445 }
1446
1447 static int
1448 ata_promise_mio_dmastop(struct ata_channel *ch)
1449 {
1450 ch->flags &= ~ATA_DMA_ACTIVE;
1451 /* get status XXX SOS */
1452 return 0;
1453 }
1454
1455 static void
1456 ata_promise_mio_dmainit(struct ata_channel *ch)
1457 {
1458 ata_dmainit(ch);
1459 if (ch->dma) {
1460 ch->dma->start = ata_promise_mio_dmastart;
1461 ch->dma->stop = ata_promise_mio_dmastop;
1462 }
1463 }
1464
1465 static void
1466 ata_promise_mio_reset(struct ata_channel *ch)
1467 {
1468 struct ata_pci_controller *ctlr =
1469 device_get_softc(device_get_parent(ch->dev));
1470
1471 if (ctlr->chip->cfg2 & PRSX4X) {
1472 struct ata_promise_sx4 *hpktp = ctlr->driver;
1473
1474 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1);
1475 DELAY(1000);
1476
1477 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7),
1478 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) &
1479 ~0x00003f9f) | (ch->unit + 1));
1480
1481 mtx_lock(&hpktp->mtx);
1482 ATA_OUTL(ctlr->r_res2, 0xc012c,
1483 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11));
1484 DELAY(10);
1485 ATA_OUTL(ctlr->r_res2, 0xc012c,
1486 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f));
1487 mtx_unlock(&hpktp->mtx);
1488 }
1489 else {
1490 if (ctlr->chip->cfg2 & PRSATA)
1491 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit));
1492
1493 ATA_OUTL(ctlr->r_res2, 0x0048,
1494 ATA_INL(ctlr->r_res2, 0x0048) & ~((1 << 12) << (ch->unit)));
1495 DELAY(10);
1496 ATA_OUTL(ctlr->r_res2, 0x0048,
1497 ATA_INL(ctlr->r_res2, 0x0048) | ((1 << 12) << (ch->unit)));
1498 DELAY(100);
1499
1500 if (ctlr->chip->cfg2 & PRSATA)
1501 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit));
1502
1503 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 0x00000800);
1504 DELAY(1000);
1505
1506 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
1507 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
1508 ~0x00003f9f) | (ch->unit + 1));
1509 }
1510 }
1511
1512 static int
1513 ata_promise_mio_command(struct ata_device *atadev, u_int8_t command,
1514 u_int64_t lba, u_int16_t count, u_int16_t feature)
1515 {
1516 struct ata_pci_controller *ctlr =
1517 device_get_softc(device_get_parent(atadev->channel->dev));
1518 u_int32_t *wordp = (u_int32_t *)atadev->channel->dma->workspace;
1519
1520 ATA_OUTL(ctlr->r_res2, (atadev->channel->unit + 1) << 2, 0x00000001);
1521
1522 switch (command) {
1523 default:
1524 return ata_generic_command(atadev, command, lba, count, feature);
1525
1526 case ATA_READ_DMA:
1527 wordp[0] = htole32(0x04 | ((atadev->channel->unit+1)<<16) | (0x00<<24));
1528 break;
1529
1530 case ATA_WRITE_DMA:
1531 wordp[0] = htole32(0x00 | ((atadev->channel->unit+1)<<16) | (0x00<<24));
1532 break;
1533 }
1534 wordp[1] = htole32(atadev->channel->dma->mdmatab);
1535 wordp[2] = 0;
1536 ata_promise_apkt((u_int8_t*)wordp, atadev, command, lba, count, feature);
1537
1538 ATA_OUTL(ctlr->r_res2, 0x0240 + (atadev->channel->unit << 7),
1539 atadev->channel->dma->wdmatab);
1540 return 0;
1541 }
1542
1543 static int
1544 ata_promise_sx4_command(struct ata_device *atadev, u_int8_t command,
1545 u_int64_t lba, u_int16_t count, u_int16_t feature)
1546 {
1547 struct ata_channel *ch = atadev->channel;
1548 struct ata_dma_prdentry *prd = ch->dma->dmatab;
1549 struct ata_pci_controller *ctlr =
1550 device_get_softc(device_get_parent(ch->dev));
1551 caddr_t window = rman_get_virtual(ctlr->r_res1);
1552 u_int32_t *wordp;
1553 int i, idx, length = 0;
1554
1555 switch (command) {
1556
1557 default:
1558 return -1;
1559
1560 case ATA_ATA_IDENTIFY:
1561 case ATA_READ:
1562 case ATA_READ_MUL:
1563 case ATA_WRITE:
1564 case ATA_WRITE_MUL:
1565 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
1566 return ata_generic_command(atadev, command, lba, count, feature);
1567
1568 case ATA_SETFEATURES:
1569 case ATA_FLUSHCACHE:
1570 case ATA_SLEEP:
1571 case ATA_SET_MULTI:
1572 wordp = (u_int32_t *)
1573 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
1574 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24));
1575 wordp[1] = 0;
1576 wordp[2] = 0;
1577 ata_promise_apkt((u_int8_t *)wordp, atadev, command, lba,count,feature);
1578 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
1579 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
1580 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
1581 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET));
1582 return 0;
1583
1584 case ATA_READ_DMA:
1585 case ATA_WRITE_DMA:
1586 wordp = (u_int32_t *)
1587 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET);
1588 i = idx = 0;
1589 do {
1590 wordp[idx++] = htole32(prd[i].addr);
1591 wordp[idx++] = htole32(prd[i].count & ~ATA_DMA_EOT);
1592 length += (prd[i].count & ~ATA_DMA_EOT);
1593 } while (!(prd[i++].count & ATA_DMA_EOT));
1594 wordp[idx - 1] |= htole32(ATA_DMA_EOT);
1595
1596 wordp = (u_int32_t *)
1597 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET);
1598 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
1599 wordp[1] = htole32((count * DEV_BSIZE) | ATA_DMA_EOT);
1600
1601 wordp = (u_int32_t *)
1602 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET);
1603 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
1604 wordp[1] = htole32((count * DEV_BSIZE) | ATA_DMA_EOT);
1605
1606 wordp = (u_int32_t *)
1607 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET);
1608 if (command == ATA_READ_DMA)
1609 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24));
1610 if (command == ATA_WRITE_DMA)
1611 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24));
1612 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET);
1613 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET);
1614 wordp[3] = 0;
1615
1616 wordp = (u_int32_t *)
1617 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
1618 if (command == ATA_READ_DMA)
1619 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24));
1620 if (command == ATA_WRITE_DMA)
1621 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24));
1622 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET);
1623 wordp[2] = 0;
1624 ata_promise_apkt((u_int8_t *)wordp, atadev, command, lba,count,feature);
1625 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
1626
1627 if (command == ATA_READ_DMA) {
1628 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001);
1629 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001);
1630 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
1631 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET));
1632 }
1633 if (command == ATA_WRITE_DMA) {
1634 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001);
1635 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001);
1636 ata_promise_queue_hpkt(ctlr,
1637 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET));
1638 }
1639 return 0;
1640 }
1641 }
1642
1643 static int
1644 ata_promise_apkt(u_int8_t *bytep, struct ata_device *atadev, u_int8_t command,
1645 u_int64_t lba, u_int16_t count, u_int16_t feature)
1646 {
1647 int i = 12;
1648
1649 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE;
1650 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit;
1651 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL;
1652 bytep[i++] = ATA_A_4BIT;
1653
1654 if ((lba > 268435455 || count > 256) && atadev->param &&
1655 (atadev->param->support.command2 & ATA_SUPPORT_ADDRESS48)) {
1656 atadev->channel->flags |= ATA_48BIT_ACTIVE;
1657 if (command == ATA_READ_DMA)
1658 command = ATA_READ_DMA48;
1659 if (command == ATA_WRITE_DMA)
1660 command = ATA_WRITE_DMA48;
1661 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE;
1662 bytep[i++] = (feature >> 8) & 0xff;
1663 bytep[i++] = feature & 0xff;
1664 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT;
1665 bytep[i++] = (count >> 8) & 0xff;
1666 bytep[i++] = count & 0xff;
1667 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR;
1668 bytep[i++] = (lba >> 24) & 0xff;
1669 bytep[i++] = lba & 0xff;
1670 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
1671 bytep[i++] = (lba >> 32) & 0xff;
1672 bytep[i++] = (lba >> 8) & 0xff;
1673 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
1674 bytep[i++] = (lba >> 40) & 0xff;
1675 bytep[i++] = (lba >> 16) & 0xff;
1676 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
1677 bytep[i++] = ATA_D_LBA | atadev->unit;
1678 }
1679 else {
1680 atadev->channel->flags &= ~ATA_48BIT_ACTIVE;
1681 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE;
1682 bytep[i++] = feature;
1683 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT;
1684 bytep[i++] = count;
1685 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR;
1686 bytep[i++] = lba & 0xff;
1687 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
1688 bytep[i++] = (lba >> 8) & 0xff;
1689 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
1690 bytep[i++] = (lba >> 16) & 0xff;
1691 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
1692 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) |
1693 ATA_D_IBM | atadev->unit | ((lba >> 24) & 0xf);
1694 }
1695 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_CMD;
1696 bytep[i++] = command;
1697 return i;
1698 }
1699
1700 static void
1701 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt)
1702 {
1703 struct ata_promise_sx4 *hpktp = ctlr->driver;
1704
1705 mtx_lock(&hpktp->mtx);
1706 if (hpktp->tail == hpktp->head && !hpktp->busy) {
1707 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt);
1708 hpktp->busy = 1;
1709 }
1710 else
1711 hpktp->array[(hpktp->head++) & (ATA_PDC_MAX_HPKT - 1)] = hpkt;
1712 mtx_unlock(&hpktp->mtx);
1713 }
1714
1715 static void
1716 ata_promise_next_hpkt(struct ata_pci_controller *ctlr)
1717 {
1718 struct ata_promise_sx4 *hpktp = ctlr->driver;
1719
1720 mtx_lock(&hpktp->mtx);
1721 if (hpktp->tail != hpktp->head) {
1722 ATA_OUTL(ctlr->r_res2, 0x000c0100,
1723 hpktp->array[(hpktp->tail++) & (ATA_PDC_MAX_HPKT - 1)]);
1724 }
1725 else
1726 hpktp->busy = 0;
1727 mtx_unlock(&hpktp->mtx);
1728 }
1729
1730 static void
1731 ata_promise_tx2_intr(void *data)
1732 {
1733 struct ata_pci_controller *ctlr = data;
1734 struct ata_channel *ch;
1735 int unit;
1736
1737 /* implement this as a toggle instead to balance load XXX */
1738 for (unit = 0; unit < 2; unit++) {
1739 if (!(ch = ctlr->interrupt[unit].argument))
1740 continue;
1741 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
1742 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
1743 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
1744 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1745
1746 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
1747 ATA_BMSTAT_INTERRUPT)
1748 continue;
1749 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
1750 DELAY(1);
1751 }
1752 ctlr->interrupt[unit].function(ch);
1753 }
1754 }
1755 }
1756
1757 static void
1758 ata_promise_old_intr(void *data)
1759 {
1760 struct ata_pci_controller *ctlr = data;
1761 struct ata_channel *ch;
1762 int unit;
1763
1764 /* implement this as a toggle instead to balance load XXX */
1765 for (unit = 0; unit < 2; unit++) {
1766 if (!(ch = ctlr->interrupt[unit].argument))
1767 continue;
1768 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)){
1769 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
1770 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1771
1772 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
1773 ATA_BMSTAT_INTERRUPT)
1774 continue;
1775 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
1776 DELAY(1);
1777 }
1778 ctlr->interrupt[unit].function(ch);
1779 }
1780 }
1781 }
1782
1783 static int
1784 ata_promise_new_dmastart(struct ata_channel *ch)
1785 {
1786 struct ata_pci_controller *ctlr =
1787 device_get_softc(device_get_parent(ch->dev));
1788
1789 if (ch->flags & ATA_48BIT_ACTIVE) {
1790 ATA_OUTB(ctlr->r_res1, 0x11,
1791 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02));
1792 ATA_OUTL(ctlr->r_res1, 0x20,
1793 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) |
1794 (ch->dma->cur_iosize >> 1));
1795 }
1796 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) |
1797 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1798 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->mdmatab);
1799 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
1800 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) |
1801 ATA_BMCMD_START_STOP);
1802 ch->flags |= ATA_DMA_ACTIVE;
1803 return 0;
1804 }
1805
1806 static int
1807 ata_promise_new_dmastop(struct ata_channel *ch)
1808 {
1809 struct ata_pci_controller *ctlr =
1810 device_get_softc(device_get_parent(ch->dev));
1811 int error;
1812
1813 if (ch->flags & ATA_48BIT_ACTIVE) {
1814 ATA_OUTB(ctlr->r_res1, 0x11,
1815 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02));
1816 ATA_OUTL(ctlr->r_res1, 0x20, 0);
1817 }
1818 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT);
1819 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
1820 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
1821 ch->flags &= ~ATA_DMA_ACTIVE;
1822 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
1823 return error;
1824 }
1825
1826 static void
1827 ata_promise_new_dmainit(struct ata_channel *ch)
1828 {
1829 ata_dmainit(ch);
1830 if (ch->dma) {
1831 ch->dma->start = ata_promise_new_dmastart;
1832 ch->dma->stop = ata_promise_new_dmastop;
1833 }
1834 }
1835
1836 static void
1837 ata_promise_setmode(struct ata_device *atadev, int mode)
1838 {
1839 device_t parent = device_get_parent(atadev->channel->dev);
1840 struct ata_pci_controller *ctlr = device_get_softc(parent);
1841 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
1842 int error;
1843 u_int32_t timings33[][2] = {
1844 /* PROLD PRNEW mode */
1845 { 0x004ff329, 0x004fff2f }, /* PIO 0 */
1846 { 0x004fec25, 0x004ff82a }, /* PIO 1 */
1847 { 0x004fe823, 0x004ff026 }, /* PIO 2 */
1848 { 0x004fe622, 0x004fec24 }, /* PIO 3 */
1849 { 0x004fe421, 0x004fe822 }, /* PIO 4 */
1850 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */
1851 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */
1852 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */
1853 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */
1854 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */
1855 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */
1856 { 0, 0x00424ef6 }, /* UDMA 3 */
1857 { 0, 0x004127f3 }, /* UDMA 4 */
1858 { 0, 0x004127f3 } /* UDMA 5 */
1859 };
1860
1861 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
1862
1863 switch (ctlr->chip->cfg1) {
1864 case PROLD:
1865 case PRNEW:
1866 if (mode > ATA_UDMA2 && (pci_read_config(parent, 0x50, 2) &
1867 (atadev->channel->unit ? 1 << 11 : 1 << 10))) {
1868 ata_prtdev(atadev,
1869 "DMA limited to UDMA33, non-ATA66 cable or device\n");
1870 mode = ATA_UDMA2;
1871 }
1872 if (ATAPI_DEVICE(atadev) && mode > ATA_PIO_MAX)
1873 mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX);
1874 break;
1875
1876 case PRTX:
1877 ATA_IDX_OUTB(atadev->channel, ATA_BMDEVSPEC_0, 0x0b);
1878 if (mode > ATA_UDMA2 &&
1879 ATA_IDX_INB(atadev->channel, ATA_BMDEVSPEC_1) & 0x04) {
1880 ata_prtdev(atadev,
1881 "DMA limited to UDMA33, non-ATA66 cable or device\n");
1882 mode = ATA_UDMA2;
1883 }
1884 break;
1885
1886 case PRMIO:
1887 if (mode > ATA_UDMA2 &&
1888 (ATA_INL(ctlr->r_res2,
1889 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) +
1890 (atadev->channel->unit << 7)) & 0x01000000)) {
1891 ata_prtdev(atadev,
1892 "DMA limited to UDMA33, non-ATA66 cable or device\n");
1893 mode = ATA_UDMA2;
1894 }
1895 break;
1896 }
1897
1898 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1899
1900 if (bootverbose)
1901 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
1902 (error) ? "FAILURE " : "",
1903 ata_mode2str(mode), ctlr->chip->text);
1904 if (!error) {
1905 if (ctlr->chip->cfg1 < PRTX)
1906 pci_write_config(parent, 0x60 + (devno << 2),
1907 timings33[ctlr->chip->cfg1][ata_mode2idx(mode)],4);
1908 atadev->mode = mode;
1909 }
1910 return;
1911 }
1912
1913 /*
1914 * ServerWorks chipset support functions
1915 */
1916 int
1917 ata_serverworks_ident(device_t dev)
1918 {
1919 struct ata_pci_controller *ctlr = device_get_softc(dev);
1920 struct ata_chip_id *idx;
1921 static struct ata_chip_id ids[] =
1922 {{ ATA_ROSB4, 0x00, SWKS33, 0x00, ATA_UDMA2, "ServerWorks ROSB4" },
1923 { ATA_CSB5, 0x92, SWKS100, 0x00, ATA_UDMA5, "ServerWorks CSB5" },
1924 { ATA_CSB5, 0x00, SWKS66, 0x00, ATA_UDMA4, "ServerWorks CSB5" },
1925 { ATA_CSB6, 0x00, SWKS100, 0x00, ATA_UDMA5, "ServerWorks CSB6" },
1926 { ATA_CSB6_1, 0x00, SWKS66, 0x00, ATA_UDMA4, "ServerWorks CSB6" },
1927 { 0, 0, 0, 0, 0, 0}};
1928 char buffer[64];
1929
1930 if (!(idx = ata_match_chip(dev, ids)))
1931 return ENXIO;
1932
1933 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
1934 device_set_desc_copy(dev, buffer);
1935 ctlr->chip = idx;
1936 ctlr->chipinit = ata_serverworks_chipinit;
1937 return 0;
1938 }
1939
1940 static int
1941 ata_serverworks_chipinit(device_t dev)
1942 {
1943 struct ata_pci_controller *ctlr = device_get_softc(dev);
1944
1945 if (ata_setup_interrupt(dev))
1946 return ENXIO;
1947
1948 if (ctlr->chip->cfg1 == SWKS33) {
1949 device_t *children;
1950 int nchildren, i;
1951
1952 /* locate the ISA part in the southbridge and enable UDMA33 */
1953 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
1954 for (i = 0; i < nchildren; i++) {
1955 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
1956 pci_write_config(children[i], 0x64,
1957 (pci_read_config(children[i], 0x64, 4) &
1958 ~0x00002000) | 0x00004000, 4);
1959 break;
1960 }
1961 }
1962 free(children, M_TEMP);
1963 }
1964 }
1965 else {
1966 pci_write_config(dev, 0x5a,
1967 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
1968 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1);
1969 }
1970 ctlr->setmode = ata_serverworks_setmode;
1971 return 0;
1972 }
1973
1974 static void
1975 ata_serverworks_setmode(struct ata_device *atadev, int mode)
1976 {
1977 device_t parent = device_get_parent(atadev->channel->dev);
1978 struct ata_pci_controller *ctlr = device_get_softc(parent);
1979 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
1980 int offset = (devno ^ 0x01) << 3;
1981 int error;
1982 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1983 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1984 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
1985
1986 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
1987
1988 mode = ata_check_80pin(atadev, mode);
1989
1990 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1991
1992 if (bootverbose)
1993 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
1994 (error) ? "FAILURE " : "",
1995 ata_mode2str(mode), ctlr->chip->text);
1996 if (!error) {
1997 if (mode >= ATA_UDMA0) {
1998 pci_write_config(parent, 0x56,
1999 (pci_read_config(parent, 0x56, 2) &
2000 ~(0xf << (devno << 2))) |
2001 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
2002 pci_write_config(parent, 0x54,
2003 pci_read_config(parent, 0x54, 1) |
2004 (0x01 << devno), 1);
2005 pci_write_config(parent, 0x44,
2006 (pci_read_config(parent, 0x44, 4) &
2007 ~(0xff << offset)) |
2008 (dmatimings[2] << offset), 4);
2009 }
2010 else if (mode >= ATA_WDMA0) {
2011 pci_write_config(parent, 0x54,
2012 pci_read_config(parent, 0x54, 1) &
2013 ~(0x01 << devno), 1);
2014 pci_write_config(parent, 0x44,
2015 (pci_read_config(parent, 0x44, 4) &
2016 ~(0xff << offset)) |
2017 (dmatimings[mode & ATA_MODE_MASK] << offset),4);
2018 }
2019 else
2020 pci_write_config(parent, 0x54,
2021 pci_read_config(parent, 0x54, 1) &
2022 ~(0x01 << devno), 1);
2023
2024 pci_write_config(parent, 0x40,
2025 (pci_read_config(parent, 0x40, 4) &
2026 ~(0xff << offset)) |
2027 (piotimings[ata_mode2idx(mode)] << offset), 4);
2028 atadev->mode = mode;
2029 }
2030 }
2031
2032 /*
2033 * Silicon Image (former CMD) chipset support functions
2034 */
2035 int
2036 ata_sii_ident(device_t dev)
2037 {
2038 struct ata_pci_controller *ctlr = device_get_softc(dev);
2039 struct ata_chip_id *idx;
2040 static struct ata_chip_id ids[] =
2041 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" },
2042 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" },
2043 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
2044 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
2045 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" },
2046 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
2047 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
2048 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" },
2049 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" },
2050 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" },
2051 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" },
2052 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" },
2053 { 0, 0, 0, 0, 0, 0}};
2054 char buffer[64];
2055
2056 if (!(idx = ata_match_chip(dev, ids)))
2057 return ENXIO;
2058
2059 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
2060 device_set_desc_copy(dev, buffer);
2061 ctlr->chip = idx;
2062 ctlr->chipinit = ata_sii_chipinit;
2063 return 0;
2064 }
2065
2066 static int
2067 ata_sii_chipinit(device_t dev)
2068 {
2069 struct ata_pci_controller *ctlr = device_get_softc(dev);
2070 int rid = ATA_IRQ_RID;
2071
2072 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2073 RF_SHAREABLE | RF_ACTIVE))) {
2074 device_printf(dev, "unable to map interrupt\n");
2075 return ENXIO;
2076 }
2077
2078 if (ctlr->chip->cfg1 == SIIMEMIO) {
2079 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
2080 ata_sii_intr, ctlr, &ctlr->handle))) {
2081 device_printf(dev, "unable to setup interrupt\n");
2082 return ENXIO;
2083 }
2084
2085 ctlr->r_type2 = SYS_RES_MEMORY;
2086 ctlr->r_rid2 = PCIR_BAR(5);
2087 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
2088 &ctlr->r_rid2, RF_ACTIVE)))
2089 return ENXIO;
2090
2091 if (ctlr->chip->cfg2 & SIISETCLK) {
2092 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
2093 pci_write_config(dev, 0x8a,
2094 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
2095 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
2096 device_printf(dev, "%s could not set ATA133 clock\n",
2097 ctlr->chip->text);
2098 }
2099
2100 /* enable interrupt as BIOS might not */
2101 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
2102
2103 if (ctlr->chip->cfg2 & SII4CH) {
2104 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
2105 ctlr->channels = 4;
2106 }
2107
2108 ctlr->allocate = ata_sii_allocate;
2109 if (ctlr->chip->max_dma >= ATA_SA150) {
2110 ctlr->reset = ata_sii_reset;
2111 ctlr->setmode = ata_sata_setmode;
2112 }
2113 else
2114 ctlr->setmode = ata_sii_setmode;
2115 }
2116 else {
2117 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
2118 ctlr->chip->cfg2 & SIIINTR ?
2119 ata_cmd_intr : ata_cmd_old_intr,
2120 ctlr, &ctlr->handle))) {
2121 device_printf(dev, "unable to setup interrupt\n");
2122 return ENXIO;
2123 }
2124
2125 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
2126 device_printf(dev, "HW has secondary channel disabled\n");
2127 ctlr->channels = 1;
2128 }
2129
2130 /* enable interrupt as BIOS might not */
2131 pci_write_config(dev, 0x71, 0x01, 1);
2132
2133 ctlr->setmode = ata_cmd_setmode;
2134 }
2135 return 0;
2136 }
2137
2138 static int
2139 ata_sii_allocate(device_t dev, struct ata_channel *ch)
2140 {
2141 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2142 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
2143 int i;
2144
2145 for (i = ATA_DATA; i <= ATA_STATUS; i++) {
2146 ch->r_io[i].res = ctlr->r_res2;
2147 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
2148 }
2149 ch->r_io[ATA_ALTSTAT].res = ctlr->r_res2;
2150 ch->r_io[ATA_ALTSTAT].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
2151 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
2152 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
2153 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
2154 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
2155 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
2156 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
2157 ch->r_io[ATA_BMDEVSPEC_0].res = ctlr->r_res2;
2158 ch->r_io[ATA_BMDEVSPEC_0].offset = 0xa1 + (unit01 << 6) + (unit10 << 8);
2159 ch->r_io[ATA_BMDEVSPEC_1].res = ctlr->r_res2;
2160 ch->r_io[ATA_BMDEVSPEC_1].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
2161 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
2162
2163 if (ctlr->chip->max_dma >= ATA_SA150)
2164 ch->flags |= ATA_NO_SLAVE;
2165
2166 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) {
2167 ch->dma->boundary = 16 * DEV_BSIZE;
2168 ch->dma->max_iosize = 15 * DEV_BSIZE;
2169 }
2170
2171 ata_generic_hw(ch);
2172
2173 return 0;
2174 }
2175
2176 static void
2177 ata_sii_reset(struct ata_channel *ch)
2178 {
2179 ATA_IDX_OUTL(ch, ATA_BMDEVSPEC_1, 0x00000001);
2180 DELAY(25000);
2181 ATA_IDX_OUTL(ch, ATA_BMDEVSPEC_1, 0x00000000);
2182 ata_udelay(1000000);
2183 }
2184
2185 static void
2186 ata_sii_intr(void *data)
2187 {
2188 struct ata_pci_controller *ctlr = data;
2189 struct ata_channel *ch;
2190 int unit;
2191
2192 /* implement this as a toggle instead to balance load XXX */
2193 for (unit = 0; unit < ctlr->channels; unit++) {
2194 if (!(ch = ctlr->interrupt[unit].argument))
2195 continue;
2196 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_0) & 0x08) {
2197 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
2198 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
2199
2200 if (!(bmstat & ATA_BMSTAT_INTERRUPT))
2201 continue;
2202 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
2203 DELAY(1);
2204 }
2205 ctlr->interrupt[unit].function(ch);
2206 }
2207 }
2208 }
2209
2210 static void
2211 ata_cmd_intr(void *data)
2212 {
2213 struct ata_pci_controller *ctlr = data;
2214 struct ata_channel *ch;
2215 u_int8_t reg71;
2216 int unit;
2217
2218 /* implement this as a toggle instead to balance load XXX */
2219 for (unit = 0; unit < 2; unit++) {
2220 if (!(ch = ctlr->interrupt[unit].argument))
2221 continue;
2222 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
2223 (ch->unit ? 0x08 : 0x04))) {
2224 pci_write_config(device_get_parent(ch->dev), 0x71,
2225 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
2226 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
2227 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
2228
2229 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
2230 ATA_BMSTAT_INTERRUPT)
2231 continue;
2232 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
2233 DELAY(1);
2234 }
2235 ctlr->interrupt[unit].function(ch);
2236 }
2237 }
2238 }
2239
2240 static void
2241 ata_cmd_old_intr(void *data)
2242 {
2243 struct ata_pci_controller *ctlr = data;
2244 struct ata_channel *ch;
2245 int unit;
2246
2247 /* implement this as a toggle instead to balance load XXX */
2248 for (unit = 0; unit < 2; unit++) {
2249 if (!(ch = ctlr->interrupt[unit].argument))
2250 continue;
2251 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
2252 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
2253
2254 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
2255 ATA_BMSTAT_INTERRUPT)
2256 continue;
2257 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
2258 DELAY(1);
2259 }
2260 ctlr->interrupt[unit].function(ch);
2261 }
2262 }
2263
2264 static void
2265 ata_sii_setmode(struct ata_device *atadev, int mode)
2266 {
2267 device_t parent = device_get_parent(atadev->channel->dev);
2268 struct ata_pci_controller *ctlr = device_get_softc(parent);
2269 int rego = (atadev->channel->unit << 4) + (ATA_DEV(atadev->unit) << 1);
2270 int mreg = atadev->channel->unit ? 0x84 : 0x80;
2271 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2);
2272 int mval = pci_read_config(parent, mreg, 1) & ~mask;
2273 int error;
2274
2275 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
2276
2277 if (ctlr->chip->cfg2 & SIISETCLK) {
2278 if (mode > ATA_UDMA2 && (pci_read_config(parent, 0x79, 1) &
2279 (atadev->channel->unit ? 0x02 : 0x01))) {
2280 ata_prtdev(atadev,
2281 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2282 mode = ATA_UDMA2;
2283 }
2284 }
2285 else
2286 mode = ata_check_80pin(atadev, mode);
2287
2288 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2289
2290 if (bootverbose)
2291 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
2292 (error) ? "FAILURE " : "",
2293 ata_mode2str(mode), ctlr->chip->text);
2294 if (error)
2295 return;
2296
2297 if (mode >= ATA_UDMA0) {
2298 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
2299 u_int8_t ureg = 0xac + rego;
2300
2301 pci_write_config(parent, mreg,
2302 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1);
2303 pci_write_config(parent, ureg,
2304 (pci_read_config(parent, ureg, 1) & ~0x3f) |
2305 udmatimings[mode & ATA_MODE_MASK], 1);
2306
2307 }
2308 else if (mode >= ATA_WDMA0) {
2309 u_int8_t dreg = 0xa8 + rego;
2310 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
2311
2312 pci_write_config(parent, mreg,
2313 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1);
2314 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
2315
2316 }
2317 else {
2318 u_int8_t preg = 0xa4 + rego;
2319 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
2320
2321 pci_write_config(parent, mreg,
2322 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1);
2323 pci_write_config(parent, preg, piotimings[mode & ATA_MODE_MASK], 2);
2324 }
2325 atadev->mode = mode;
2326 }
2327
2328 static void
2329 ata_cmd_setmode(struct ata_device *atadev, int mode)
2330 {
2331 device_t parent = device_get_parent(atadev->channel->dev);
2332 struct ata_pci_controller *ctlr = device_get_softc(parent);
2333 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
2334 int error;
2335
2336 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
2337
2338 mode = ata_check_80pin(atadev, mode);
2339
2340 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2341
2342 if (bootverbose)
2343 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
2344 (error) ? "FAILURE " : "",
2345 ata_mode2str(mode), ctlr->chip->text);
2346 if (!error) {
2347 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
2348 int ureg = atadev->channel->unit ? 0x7b : 0x73;
2349
2350 if (mode >= ATA_UDMA0) {
2351 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
2352 { 0x11, 0x42 }, { 0x25, 0x8a },
2353 { 0x15, 0x4a }, { 0x05, 0x0a } };
2354
2355 u_int8_t umode = pci_read_config(parent, ureg, 1);
2356
2357 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
2358 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)];
2359 pci_write_config(parent, ureg, umode, 1);
2360 }
2361 else if (mode >= ATA_WDMA0) {
2362 int dmatimings[] = { 0x87, 0x32, 0x3f };
2363
2364 pci_write_config(parent, treg, dmatimings[mode & ATA_MODE_MASK], 1);
2365 pci_write_config(parent, ureg,
2366 pci_read_config(parent, ureg, 1) &
2367 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
2368 }
2369 else {
2370 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
2371 pci_write_config(parent, treg,
2372 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
2373 pci_write_config(parent, ureg,
2374 pci_read_config(parent, ureg, 1) &
2375 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
2376 }
2377 atadev->mode = mode;
2378 }
2379 }
2380
2381 /*
2382 * SiS chipset support functions
2383 */
2384 int
2385 ata_sis_ident(device_t dev)
2386 {
2387 struct ata_pci_controller *ctlr = device_get_softc(dev);
2388 struct ata_chip_id *idx;
2389 static struct ata_chip_id ids[] =
2390 {{ ATA_SIS964_S,0x00, SISSATA, 0, ATA_SA150, "SiS 964" }, /* south */
2391 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 964" }, /* south */
2392 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 963" }, /* south */
2393 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 962" }, /* south */
2394
2395 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 745" }, /* 1chip */
2396 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 735" }, /* 1chip */
2397 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 733" }, /* 1chip */
2398 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "SiS 730" }, /* 1chip */
2399
2400 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 635" }, /* 1chip */
2401 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 633" }, /* unknown */
2402 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "SiS 630S"}, /* 1chip */
2403 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "SiS 630" }, /* 1chip */
2404 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "SiS 620" }, /* 1chip */
2405
2406 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "SiS 550" },
2407 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "SiS 540" },
2408 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "SiS 530" },
2409
2410 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "SiS 5513" },
2411 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "SiS 5513" },
2412 { 0, 0, 0, 0, 0, 0 }};
2413 char buffer[64];
2414 int found = 0;
2415
2416 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev))))
2417 return ENXIO;
2418
2419 if (idx->cfg2 && !found) {
2420 u_int8_t reg57 = pci_read_config(dev, 0x57, 1);
2421
2422 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1);
2423 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) {
2424 found = 1;
2425 idx->cfg1 = SIS133NEW;
2426 idx->max_dma = ATA_UDMA6;
2427 sprintf(buffer, "SiS 962/963 %s controller",
2428 ata_mode2str(idx->max_dma));
2429 }
2430 pci_write_config(dev, 0x57, reg57, 1);
2431 }
2432 if (idx->cfg2 && !found) {
2433 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1);
2434
2435 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1);
2436 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) {
2437 struct ata_chip_id id[] =
2438 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }};
2439
2440 found = 1;
2441 if (ata_find_chip(dev, id, pci_get_slot(dev))) {
2442 idx->cfg1 = SIS133OLD;
2443 idx->max_dma = ATA_UDMA6;
2444 }
2445 else {
2446 idx->cfg1 = SIS100NEW;
2447 idx->max_dma = ATA_UDMA5;
2448 }
2449 sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
2450 }
2451 pci_write_config(dev, 0x4a, reg4a, 1);
2452 }
2453 if (!found)
2454 sprintf(buffer,"%s %s controller",idx->text,ata_mode2str(idx->max_dma));
2455
2456 device_set_desc_copy(dev, buffer);
2457 ctlr->chip = idx;
2458 ctlr->chipinit = ata_sis_chipinit;
2459 return 0;
2460 }
2461
2462 static int
2463 ata_sis_chipinit(device_t dev)
2464 {
2465 struct ata_pci_controller *ctlr = device_get_softc(dev);
2466
2467 if (ata_setup_interrupt(dev))
2468 return ENXIO;
2469
2470 switch (ctlr->chip->cfg1) {
2471 case SIS33:
2472 break;
2473 case SIS66:
2474 case SIS100OLD:
2475 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1);
2476 break;
2477 case SIS100NEW:
2478 case SIS133OLD:
2479 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1);
2480 break;
2481 case SIS133NEW:
2482 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2);
2483 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2);
2484 break;
2485 case SISSATA:
2486 pci_write_config(dev, PCIR_COMMAND,
2487 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
2488 ctlr->setmode = ata_sata_setmode;
2489 return 0;
2490 default:
2491 return ENXIO;
2492 }
2493 ctlr->setmode = ata_sis_setmode;
2494 return 0;
2495 }
2496
2497 static void
2498 ata_sis_setmode(struct ata_device *atadev, int mode)
2499 {
2500 device_t parent = device_get_parent(atadev->channel->dev);
2501 struct ata_pci_controller *ctlr = device_get_softc(parent);
2502 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
2503 int error;
2504
2505 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
2506
2507 if (ctlr->chip->cfg1 == SIS133NEW) {
2508 if (mode > ATA_UDMA2 &&
2509 pci_read_config(parent, atadev->channel->unit?0x52:0x50,2)&0x8000){
2510 ata_prtdev(atadev,
2511 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2512 mode = ATA_UDMA2;
2513 }
2514 }
2515 else {
2516 if (mode > ATA_UDMA2 &&
2517 pci_read_config(parent, 0x48, 1)&(atadev->channel->unit?0x20:0x10)){
2518 ata_prtdev(atadev,
2519 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2520 mode = ATA_UDMA2;
2521 }
2522 }
2523
2524 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2525
2526 if (bootverbose)
2527 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
2528 (error) ? "FAILURE " : "",
2529 ata_mode2str(mode), ctlr->chip->text);
2530 if (!error) {
2531 switch (ctlr->chip->cfg1) {
2532 case SIS133NEW: {
2533 u_int32_t timings[] =
2534 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
2535 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
2536 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
2537 u_int32_t reg;
2538
2539 reg = (pci_read_config(parent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
2540 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 4);
2541 break;
2542 }
2543 case SIS133OLD: {
2544 u_int16_t timings[] =
2545 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
2546 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
2547
2548 u_int16_t reg = 0x40 + (devno << 1);
2549
2550 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
2551 break;
2552 }
2553 case SIS100NEW: {
2554 u_int16_t timings[] =
2555 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
2556 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
2557 u_int16_t reg = 0x40 + (devno << 1);
2558
2559 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
2560 break;
2561 }
2562 case SIS100OLD:
2563 case SIS66:
2564 case SIS33: {
2565 u_int16_t timings[] =
2566 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
2567 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
2568 u_int16_t reg = 0x40 + (devno << 1);
2569
2570 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
2571 break;
2572 }
2573 }
2574 atadev->mode = mode;
2575 }
2576 }
2577
2578 /* VIA chipsets */
2579 int
2580 ata_via_ident(device_t dev)
2581 {
2582 struct ata_pci_controller *ctlr = device_get_softc(dev);
2583 struct ata_chip_id *idx;
2584 static struct ata_chip_id ids[] =
2585 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "VIA 82C586B" },
2586 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "VIA 82C586" },
2587 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "VIA 82C596B" },
2588 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "VIA 82C596" },
2589 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "VIA 82C686B"},
2590 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "VIA 82C686A" },
2591 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "VIA 82C686" },
2592 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "VIA 8231" },
2593 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "VIA 8233" },
2594 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "VIA 8233C" },
2595 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8233A" },
2596 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8235" },
2597 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8237" },
2598 { 0, 0, 0, 0, 0, 0 }};
2599 static struct ata_chip_id new_ids[] =
2600 {{ ATA_VIA6410, 0x00, 0x00, 0x00, ATA_UDMA6, "VIA 6410" },
2601 { ATA_VIA6420, 0x00, 0x00, 0x00, ATA_SA150, "VIA 6420" },
2602 { 0, 0, 0, 0, 0, 0 }};
2603 char buffer[64];
2604
2605 if (pci_get_devid(dev) == ATA_VIA82C571) {
2606 if (!(idx = ata_find_chip(dev, ids, -99)))
2607 return ENXIO;
2608 }
2609 else {
2610 if (!(idx = ata_match_chip(dev, new_ids)))
2611 return ENXIO;
2612 }
2613
2614 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
2615 device_set_desc_copy(dev, buffer);
2616 ctlr->chip = idx;
2617 ctlr->chipinit = ata_via_chipinit;
2618 return 0;
2619 }
2620
2621 static int
2622 ata_via_chipinit(device_t dev)
2623 {
2624 struct ata_pci_controller *ctlr = device_get_softc(dev);
2625
2626 if (ata_setup_interrupt(dev))
2627 return ENXIO;
2628
2629 if (ctlr->chip->max_dma >= ATA_SA150) {
2630 pci_write_config(dev, PCIR_COMMAND,
2631 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
2632 ctlr->setmode = ata_sata_setmode;
2633 return 0;
2634 }
2635
2636 /* prepare for ATA-66 on the 82C686a and 82C596b */
2637 if (ctlr->chip->cfg2 & VIACLK)
2638 pci_write_config(dev, 0x50, 0x030b030b, 4);
2639
2640 /* the southbridge might need the data corruption fix */
2641 if (ctlr->chip->cfg2 & VIABUG)
2642 ata_via_southbridge_fixup(dev);
2643
2644 /* set fifo configuration half'n'half */
2645 pci_write_config(dev, 0x43,
2646 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
2647
2648 /* set status register read retry */
2649 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
2650
2651 /* set DMA read & end-of-sector fifo flush */
2652 pci_write_config(dev, 0x46,
2653 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
2654
2655 /* set sector size */
2656 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
2657 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
2658
2659 ctlr->setmode = ata_via_family_setmode;
2660 return 0;
2661 }
2662
2663 static void
2664 ata_via_southbridge_fixup(device_t dev)
2665 {
2666 device_t *children;
2667 int nchildren, i;
2668
2669 if (device_get_children(device_get_parent(dev), &children, &nchildren))
2670 return;
2671
2672 for (i = 0; i < nchildren; i++) {
2673 if (pci_get_devid(children[i]) == ATA_VIA8363 ||
2674 pci_get_devid(children[i]) == ATA_VIA8371 ||
2675 pci_get_devid(children[i]) == ATA_VIA8662 ||
2676 pci_get_devid(children[i]) == ATA_VIA8361) {
2677 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
2678
2679 if ((reg76 & 0xf0) != 0xd0) {
2680 device_printf(dev,
2681 "Correcting VIA config for southbridge data corruption bug\n");
2682 pci_write_config(children[i], 0x75, 0x80, 1);
2683 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
2684 }
2685 break;
2686 }
2687 }
2688 free(children, M_TEMP);
2689 }
2690
2691 /* common code for VIA, AMD & nVidia */
2692 static void
2693 ata_via_family_setmode(struct ata_device *atadev, int mode)
2694 {
2695 device_t parent = device_get_parent(atadev->channel->dev);
2696 struct ata_pci_controller *ctlr = device_get_softc(parent);
2697 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
2698 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
2699 int modes[][7] = {
2700 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
2701 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
2702 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
2703 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
2704 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */
2705 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
2706 int reg = 0x53 - devno;
2707 int error;
2708
2709 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
2710
2711 if (ctlr->chip->cfg2 & AMDCABLE) {
2712 if (mode > ATA_UDMA2 &&
2713 !(pci_read_config(parent, 0x42, 1) & (1 << devno))) {
2714 ata_prtdev(atadev,
2715 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2716 mode = ATA_UDMA2;
2717 }
2718 }
2719 else
2720 mode = ata_check_80pin(atadev, mode);
2721
2722 if (ctlr->chip->cfg2 & NVIDIA)
2723 reg += 0x10;
2724
2725 if (ctlr->chip->cfg1 != VIA133)
2726 pci_write_config(parent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
2727
2728 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2729
2730 if (bootverbose)
2731 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
2732 (error) ? "FAILURE " : "", ata_mode2str(mode),
2733 ctlr->chip->text);
2734 if (!error) {
2735 if (mode >= ATA_UDMA0)
2736 pci_write_config(parent, reg,
2737 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
2738 else
2739 pci_write_config(parent, reg, 0x8b, 1);
2740 atadev->mode = mode;
2741 }
2742 }
2743
2744 /* misc functions */
2745 static struct ata_chip_id *
2746 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot)
2747 {
2748 device_t *children;
2749 int nchildren, i;
2750
2751 if (device_get_children(device_get_parent(dev), &children, &nchildren))
2752 return 0;
2753
2754 while (index->chipid != 0) {
2755 for (i = 0; i < nchildren; i++) {
2756 if (((slot >= 0 && pci_get_slot(children[i]) == slot) ||
2757 (slot < 0 && pci_get_slot(children[i]) <= -slot)) &&
2758 pci_get_devid(children[i]) == index->chipid &&
2759 pci_get_revid(children[i]) >= index->chiprev) {
2760 free(children, M_TEMP);
2761 return index;
2762 }
2763 }
2764 index++;
2765 }
2766 free(children, M_TEMP);
2767 return NULL;
2768 }
2769
2770 static struct ata_chip_id *
2771 ata_match_chip(device_t dev, struct ata_chip_id *index)
2772 {
2773 while (index->chipid != 0) {
2774 if (pci_get_devid(dev) == index->chipid &&
2775 pci_get_revid(dev) >= index->chiprev)
2776 return index;
2777 index++;
2778 }
2779 return NULL;
2780 }
2781
2782 static int
2783 ata_setup_interrupt(device_t dev)
2784 {
2785 struct ata_pci_controller *ctlr = device_get_softc(dev);
2786 int rid = ATA_IRQ_RID;
2787
2788 if (!ata_legacy(dev)) {
2789 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2790 RF_SHAREABLE | RF_ACTIVE))) {
2791 device_printf(dev, "unable to map interrupt\n");
2792 return ENXIO;
2793 }
2794 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
2795 ata_generic_intr, ctlr, &ctlr->handle))) {
2796 device_printf(dev, "unable to setup interrupt\n");
2797 return ENXIO;
2798 }
2799 }
2800 return 0;
2801 }
2802
2803 struct ata_serialize {
2804 struct mtx locked_mtx;
2805 int locked_ch;
2806 int restart_ch;
2807 };
2808
2809 static int
2810 ata_serialize(struct ata_channel *ch, int flags)
2811 {
2812 struct ata_pci_controller *ctlr =
2813 device_get_softc(device_get_parent(ch->dev));
2814 struct ata_serialize *serial;
2815 static int inited = 0;
2816 int res;
2817
2818 if (!inited) {
2819 ctlr->driver = malloc(sizeof(struct ata_serialize),
2820 M_TEMP, M_NOWAIT | M_ZERO);
2821 serial = ctlr->driver;
2822 mtx_init(&serial->locked_mtx, "ATA serialize lock", NULL, MTX_DEF);
2823 serial->locked_ch = -1;
2824 serial->restart_ch = -1;
2825 inited = 1;
2826 }
2827 else
2828 serial = ctlr->driver;
2829
2830 mtx_lock(&serial->locked_mtx);
2831 switch (flags) {
2832 case ATA_LF_LOCK:
2833 if (serial->locked_ch == -1)
2834 serial->locked_ch = ch->unit;
2835 if (serial->locked_ch != ch->unit)
2836 serial->restart_ch = ch->unit;
2837 break;
2838
2839 case ATA_LF_UNLOCK:
2840 if (serial->locked_ch == ch->unit) {
2841 serial->locked_ch = -1;
2842 if (serial->restart_ch != -1) {
2843 if (ctlr->interrupt[serial->restart_ch].argument) {
2844 mtx_unlock(&serial->locked_mtx);
2845 ata_start(ctlr->interrupt[serial->restart_ch].argument);
2846 mtx_lock(&serial->locked_mtx);
2847 }
2848 serial->restart_ch = -1;
2849 }
2850 }
2851 break;
2852
2853 case ATA_LF_WHICH:
2854 break;
2855 }
2856 res = serial->locked_ch;
2857 mtx_unlock(&serial->locked_mtx);
2858 return res;
2859 }
2860
2861 static int
2862 ata_check_80pin(struct ata_device *atadev, int mode)
2863 {
2864 if (mode > ATA_UDMA2 && !(atadev->param->hwres & ATA_CABLE_ID)) {
2865 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
2866 mode = ATA_UDMA2;
2867 }
2868 return mode;
2869 }
2870
2871 static int
2872 ata_mode2idx(int mode)
2873 {
2874 if ((mode & ATA_DMA_MASK) == ATA_UDMA0)
2875 return (mode & ATA_MODE_MASK) + 8;
2876 if ((mode & ATA_DMA_MASK) == ATA_WDMA0)
2877 return (mode & ATA_MODE_MASK) + 5;
2878 return (mode & ATA_MODE_MASK) - ATA_PIO0;
2879 }
Cache object: 7fb66b03f0b8e5ccc91ebbedc7e435f1
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