1 /*-
2 * Copyright (c) 1998 - 2004 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD: src/sys/dev/ata/ata-chipset.c,v 1.81.2.6 2005/03/23 05:14:11 mdodd Exp $");
31
32 #include "opt_ata.h"
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/ata.h>
37 #include <sys/bus.h>
38 #include <sys/endian.h>
39 #include <sys/malloc.h>
40 #include <sys/lock.h>
41 #include <sys/mutex.h>
42 #include <sys/sema.h>
43 #include <sys/taskqueue.h>
44 #include <vm/uma.h>
45 #include <machine/stdarg.h>
46 #include <machine/resource.h>
47 #include <machine/bus.h>
48 #include <sys/rman.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/ata/ata-all.h>
52 #include <dev/ata/ata-pci.h>
53
54 /* misc defines */
55 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
56 #define ATAPI_DEVICE(atadev) \
57 ((atadev->unit == ATA_MASTER && \
58 atadev->channel->devices & ATA_ATAPI_MASTER) ||\
59 (atadev->unit == ATA_SLAVE && \
60 atadev->channel->devices & ATA_ATAPI_SLAVE))
61
62 /* local prototypes */
63 static int ata_generic_chipinit(device_t);
64 static void ata_generic_intr(void *);
65 static void ata_generic_setmode(struct ata_device *, int);
66 static int ata_acard_chipinit(device_t);
67 static void ata_acard_intr(void *);
68 static void ata_acard_850_setmode(struct ata_device *, int);
69 static void ata_acard_86X_setmode(struct ata_device *, int);
70 static int ata_ali_chipinit(device_t);
71 static void ata_ali_setmode(struct ata_device *, int);
72 static int ata_amd_chipinit(device_t);
73 static int ata_cyrix_chipinit(device_t);
74 static void ata_cyrix_setmode(struct ata_device *, int);
75 static int ata_cypress_chipinit(device_t);
76 static void ata_cypress_setmode(struct ata_device *, int);
77 static int ata_highpoint_chipinit(device_t);
78 static void ata_highpoint_intr(void *);
79 static void ata_highpoint_setmode(struct ata_device *, int);
80 static int ata_highpoint_check_80pin(struct ata_device *, int);
81 static int ata_intel_chipinit(device_t);
82 static void ata_intel_intr(void *);
83 static void ata_intel_reset(struct ata_channel *);
84 static void ata_intel_old_setmode(struct ata_device *, int);
85 static void ata_intel_new_setmode(struct ata_device *, int);
86 static int ata_ite_chipinit(device_t);
87 static void ata_ite_setmode(struct ata_device *, int);
88 static int ata_national_chipinit(device_t);
89 static void ata_national_setmode(struct ata_device *, int);
90 static int ata_nvidia_chipinit(device_t);
91 static int ata_via_chipinit(device_t);
92 static void ata_via_family_setmode(struct ata_device *, int);
93 static void ata_via_southbridge_fixup(device_t);
94 static int ata_promise_chipinit(device_t);
95 static int ata_promise_mio_allocate(device_t, struct ata_channel *);
96 static void ata_promise_mio_intr(void *);
97 static void ata_promise_sx4_intr(void *);
98 static void ata_promise_mio_dmainit(struct ata_channel *);
99 static void ata_promise_mio_reset(struct ata_channel *ch);
100 static int ata_promise_mio_command(struct ata_device *atadev, u_int8_t command, u_int64_t lba, u_int16_t count, u_int16_t feature);
101 static int ata_promise_sx4_command(struct ata_device *atadev, u_int8_t command, u_int64_t lba, u_int16_t count, u_int16_t feature);
102 static int ata_promise_apkt(u_int8_t *bytep, struct ata_device *atadev, u_int8_t command, u_int64_t lba, u_int16_t count, u_int16_t feature);
103 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt);
104 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr);
105 static void ata_promise_tx2_intr(void *);
106 static void ata_promise_old_intr(void *);
107 static void ata_promise_new_dmainit(struct ata_channel *);
108 static void ata_promise_setmode(struct ata_device *, int);
109 static int ata_serverworks_chipinit(device_t);
110 static void ata_serverworks_setmode(struct ata_device *, int);
111 static int ata_sii_chipinit(device_t);
112 static int ata_sii_allocate(device_t, struct ata_channel *);
113 static void ata_sii_reset(struct ata_channel *);
114 static void ata_sii_intr(void *);
115 static void ata_cmd_intr(void *);
116 static void ata_cmd_old_intr(void *);
117 static void ata_sii_setmode(struct ata_device *, int);
118 static void ata_cmd_setmode(struct ata_device *, int);
119 static int ata_sis_chipinit(device_t);
120 static void ata_sis_setmode(struct ata_device *, int);
121 static int ata_check_80pin(struct ata_device *, int);
122 static struct ata_chip_id *ata_find_chip(device_t, struct ata_chip_id *, int);
123 static struct ata_chip_id *ata_match_chip(device_t, struct ata_chip_id *);
124 static int ata_setup_interrupt(device_t);
125 static int ata_serialize(struct ata_channel *, int);
126 static int ata_mode2idx(int);
127
128 /* generic or unknown ATA chipset init code */
129 int
130 ata_generic_ident(device_t dev)
131 {
132 struct ata_pci_controller *ctlr = device_get_softc(dev);
133
134 device_set_desc(dev, "GENERIC ATA controller");
135 ctlr->chipinit = ata_generic_chipinit;
136 return 0;
137 }
138
139 static int
140 ata_generic_chipinit(device_t dev)
141 {
142 struct ata_pci_controller *ctlr = device_get_softc(dev);
143
144 if (ata_setup_interrupt(dev))
145 return ENXIO;
146 ctlr->setmode = ata_generic_setmode;
147 return 0;
148 }
149
150 static void
151 ata_generic_intr(void *data)
152 {
153 struct ata_pci_controller *ctlr = data;
154 struct ata_channel *ch;
155 int unit;
156
157 /* implement this as a toggle instead to balance load XXX */
158 for (unit = 0; unit < 2; unit++) {
159 if (!(ch = ctlr->interrupt[unit].argument))
160 continue;
161 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
162 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
163
164 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
165 ATA_BMSTAT_INTERRUPT)
166 continue;
167 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
168 DELAY(1);
169 }
170 ctlr->interrupt[unit].function(ch);
171 }
172 }
173
174 static void
175 ata_generic_setmode(struct ata_device *atadev, int mode)
176 {
177 mode = ata_limit_mode(atadev, mode, ATA_UDMA2);
178 mode = ata_check_80pin(atadev, mode);
179 if (!ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
180 atadev->mode = mode;
181 }
182
183 static void
184 ata_sata_setmode(struct ata_device *atadev, int mode)
185 {
186 /*
187 * if we detect that the device isn't a real SATA device we limit
188 * the transfer mode to UDMA5/ATA100.
189 * this works around the problems some devices has with the
190 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133.
191 */
192 if (atadev->param->satacapabilities != 0x0000 &&
193 atadev->param->satacapabilities != 0xffff) {
194 if (!ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
195 ata_limit_mode(atadev, mode, ATA_UDMA6)))
196 atadev->mode = ATA_SA150;
197 }
198 else {
199 mode = ata_limit_mode(atadev, mode, ATA_UDMA5);
200 if (!ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
201 atadev->mode = mode;
202 }
203 }
204
205 /*
206 * Acard chipset support functions
207 */
208 int
209 ata_acard_ident(device_t dev)
210 {
211 struct ata_pci_controller *ctlr = device_get_softc(dev);
212 struct ata_chip_id *idx;
213 static struct ata_chip_id ids[] =
214 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "Acard ATP850" },
215 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "Acard ATP860A" },
216 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "Acard ATP860R" },
217 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "Acard ATP865A" },
218 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "Acard ATP865R" },
219 { 0, 0, 0, 0, 0, 0}};
220 char buffer[64];
221
222 if (!(idx = ata_match_chip(dev, ids)))
223 return ENXIO;
224
225 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
226 device_set_desc_copy(dev, buffer);
227 ctlr->chip = idx;
228 ctlr->chipinit = ata_acard_chipinit;
229 return 0;
230 }
231
232 static int
233 ata_acard_chipinit(device_t dev)
234 {
235 struct ata_pci_controller *ctlr = device_get_softc(dev);
236 int rid = ATA_IRQ_RID;
237
238 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
239 RF_SHAREABLE | RF_ACTIVE))) {
240 device_printf(dev, "unable to map interrupt\n");
241 return ENXIO;
242 }
243 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
244 ata_acard_intr, ctlr, &ctlr->handle))) {
245 device_printf(dev, "unable to setup interrupt\n");
246 return ENXIO;
247 }
248 if (ctlr->chip->cfg1 == ATPOLD) {
249 ctlr->setmode = ata_acard_850_setmode;
250 ctlr->locking = ata_serialize;
251 }
252 else
253 ctlr->setmode = ata_acard_86X_setmode;
254 return 0;
255 }
256
257 static void
258 ata_acard_intr(void *data)
259 {
260 struct ata_pci_controller *ctlr = data;
261 struct ata_channel *ch;
262 int unit;
263
264 /* implement this as a toggle instead to balance load XXX */
265 for (unit = 0; unit < 2; unit++) {
266 if (!(ch = ctlr->interrupt[unit].argument))
267 continue;
268 if (ctlr->chip->cfg1 == ATPOLD && ch->locking(ch, ATA_LF_WHICH) != unit)
269 continue;
270 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
271 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
272
273 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
274 ATA_BMSTAT_INTERRUPT)
275 continue;
276 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
277 DELAY(1);
278 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
279 ATA_IDX_INB(ch, ATA_BMCMD_PORT)&~ATA_BMCMD_START_STOP);
280 DELAY(1);
281 }
282 ctlr->interrupt[unit].function(ch);
283 }
284 }
285
286 static void
287 ata_acard_850_setmode(struct ata_device *atadev, int mode)
288 {
289 device_t parent = device_get_parent(atadev->channel->dev);
290 struct ata_pci_controller *ctlr = device_get_softc(parent);
291 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
292 int error;
293
294 mode = ata_limit_mode(atadev, mode,
295 ATAPI_DEVICE(atadev)?ATA_PIO_MAX:ctlr->chip->max_dma);
296
297 /* XXX missing WDMA0+1 + PIO modes */
298 if (mode >= ATA_WDMA2) {
299 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,mode);
300 if (bootverbose)
301 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
302 (error) ? "FAILURE " : "",
303 ata_mode2str(mode), ctlr->chip->text);
304 if (!error) {
305 u_int8_t reg54 = pci_read_config(parent, 0x54, 1);
306
307 reg54 &= ~(0x03 << (devno << 1));
308 if (mode >= ATA_UDMA0)
309 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1));
310 pci_write_config(parent, 0x54, reg54, 1);
311 pci_write_config(parent, 0x4a, 0xa6, 1);
312 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
313 atadev->mode = mode;
314 return;
315 }
316 }
317 /* we could set PIO mode timings, but we assume the BIOS did that */
318 }
319
320 static void
321 ata_acard_86X_setmode(struct ata_device *atadev, int mode)
322 {
323 device_t parent = device_get_parent(atadev->channel->dev);
324 struct ata_pci_controller *ctlr = device_get_softc(parent);
325 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
326 int error;
327
328
329 mode = ata_limit_mode(atadev, mode,
330 ATAPI_DEVICE(atadev)?ATA_PIO_MAX:ctlr->chip->max_dma);
331
332 mode = ata_check_80pin(atadev, mode);
333
334 /* XXX missing WDMA0+1 + PIO modes */
335 if (mode >= ATA_WDMA2) {
336 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,mode);
337 if (bootverbose)
338 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
339 (error) ? "FAILURE " : "",
340 ata_mode2str(mode), ctlr->chip->text);
341 if (!error) {
342 u_int16_t reg44 = pci_read_config(parent, 0x44, 2);
343
344 reg44 &= ~(0x000f << (devno << 2));
345 if (mode >= ATA_UDMA0)
346 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2));
347 pci_write_config(parent, 0x44, reg44, 2);
348 pci_write_config(parent, 0x4a, 0xa6, 1);
349 pci_write_config(parent, 0x40 + devno, 0x31, 1);
350 atadev->mode = mode;
351 return;
352 }
353 }
354 /* we could set PIO mode timings, but we assume the BIOS did that */
355 }
356
357 /*
358 * Acer Labs Inc (ALI) chipset support functions
359 */
360 int
361 ata_ali_ident(device_t dev)
362 {
363 struct ata_pci_controller *ctlr = device_get_softc(dev);
364 struct ata_chip_id *idx;
365 static struct ata_chip_id ids[] =
366 {{ ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "AcerLabs Aladdin" },
367 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "AcerLabs Aladdin" },
368 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "AcerLabs Aladdin" },
369 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "AcerLabs Aladdin" },
370 { 0, 0, 0, 0, 0, 0}};
371 char buffer[64];
372
373 if (!(idx = ata_match_chip(dev, ids)))
374 return ENXIO;
375
376 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
377 device_set_desc_copy(dev, buffer);
378 ctlr->chip = idx;
379 ctlr->chipinit = ata_ali_chipinit;
380 return 0;
381 }
382
383 static int
384 ata_ali_chipinit(device_t dev)
385 {
386 struct ata_pci_controller *ctlr = device_get_softc(dev);
387
388 if (ata_setup_interrupt(dev))
389 return ENXIO;
390
391 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
392 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
393
394 /* enable cable detection and UDMA support on newer chips */
395 if (ctlr->chip->cfg2 & ALINEW)
396 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1);
397 ctlr->setmode = ata_ali_setmode;
398 return 0;
399 }
400
401 static void
402 ata_ali_setmode(struct ata_device *atadev, int mode)
403 {
404 device_t parent = device_get_parent(atadev->channel->dev);
405 struct ata_pci_controller *ctlr = device_get_softc(parent);
406 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
407 int error;
408
409 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
410
411 if (ctlr->chip->cfg2 & ALINEW) {
412 if (mode > ATA_UDMA2 &&
413 pci_read_config(parent, 0x4a, 1) & (1 << atadev->channel->unit)) {
414 ata_prtdev(atadev,
415 "DMA limited to UDMA33, non-ATA66 cable or device\n");
416 mode = ATA_UDMA2;
417 }
418 }
419 else
420 mode = ata_check_80pin(atadev, mode);
421
422 if (ctlr->chip->cfg2 & ALIOLD) {
423 /* doesn't support ATAPI DMA on write */
424 atadev->channel->flags |= ATA_ATAPI_DMA_RO;
425 if (atadev->channel->devices & ATA_ATAPI_MASTER &&
426 atadev->channel->devices & ATA_ATAPI_SLAVE) {
427 /* doesn't support ATAPI DMA on two ATAPI devices */
428 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n");
429 mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX);
430 }
431 }
432
433 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
434
435 if (bootverbose)
436 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
437 (error) ? "FAILURE " : "",
438 ata_mode2str(mode), ctlr->chip->text);
439 if (!error) {
440 if (mode >= ATA_UDMA0) {
441 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f};
442 u_int32_t word54 = pci_read_config(parent, 0x54, 4);
443
444 word54 &= ~(0x000f000f << (devno << 2));
445 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
446 pci_write_config(parent, 0x54, word54, 4);
447 pci_write_config(parent, 0x58 + (atadev->channel->unit << 2),
448 0x00310001, 4);
449 }
450 else {
451 u_int32_t piotimings[] =
452 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
453 0x00310001, 0x00440001, 0x00330001, 0x00310001};
454
455 pci_write_config(parent, 0x54, pci_read_config(parent, 0x54, 4) &
456 ~(0x0008000f << (devno << 2)), 4);
457 pci_write_config(parent, 0x58 + (atadev->channel->unit << 2),
458 piotimings[ata_mode2idx(mode)], 4);
459 }
460 atadev->mode = mode;
461 }
462 }
463
464 /*
465 * American Micro Devices (AMD) support functions
466 */
467 int
468 ata_amd_ident(device_t dev)
469 {
470 struct ata_pci_controller *ctlr = device_get_softc(dev);
471 struct ata_chip_id *idx;
472 static struct ata_chip_id ids[] =
473 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "AMD 756" },
474 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "AMD 766" },
475 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "AMD 768" },
476 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "AMD 8111" },
477 { 0, 0, 0, 0, 0, 0}};
478 char buffer[64];
479
480 if (!(idx = ata_match_chip(dev, ids)))
481 return ENXIO;
482
483 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
484 device_set_desc_copy(dev, buffer);
485 ctlr->chip = idx;
486 ctlr->chipinit = ata_amd_chipinit;
487 return 0;
488 }
489
490 static int
491 ata_amd_chipinit(device_t dev)
492 {
493 struct ata_pci_controller *ctlr = device_get_softc(dev);
494
495 if (ata_setup_interrupt(dev))
496 return ENXIO;
497
498 /* disable/set prefetch, postwrite */
499 if (ctlr->chip->cfg2 & AMDBUG)
500 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1);
501 else
502 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
503
504 ctlr->setmode = ata_via_family_setmode;
505 return 0;
506 }
507
508 /*
509 * Cyrix chipset support functions
510 */
511 int
512 ata_cyrix_ident(device_t dev)
513 {
514 struct ata_pci_controller *ctlr = device_get_softc(dev);
515
516 if (pci_get_devid(dev) == ATA_CYRIX_5530) {
517 device_set_desc(dev, "Cyrix 5530 ATA33 controller");
518 ctlr->chipinit = ata_cyrix_chipinit;
519 return 0;
520 }
521 return ENXIO;
522 }
523
524 static int
525 ata_cyrix_chipinit(device_t dev)
526 {
527 struct ata_pci_controller *ctlr = device_get_softc(dev);
528
529 if (ata_setup_interrupt(dev))
530 return ENXIO;
531
532 if (ctlr->r_res1)
533 ctlr->setmode = ata_cyrix_setmode;
534 else
535 ctlr->setmode = ata_generic_setmode;
536 return 0;
537 }
538
539 static void
540 ata_cyrix_setmode(struct ata_device *atadev, int mode)
541 {
542 struct ata_channel *ch = atadev->channel;
543 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
544 u_int32_t piotiming[] =
545 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
546 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
547 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
548 int error;
549
550 atadev->channel->dma->alignment = 16;
551 atadev->channel->dma->max_iosize = 126 * DEV_BSIZE;
552
553 mode = ata_limit_mode(atadev, mode, ATA_UDMA2);
554
555 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
556
557 if (bootverbose)
558 ata_prtdev(atadev, "%ssetting %s on Cyrix chip\n",
559 (error) ? "FAILURE " : "", ata_mode2str(mode));
560 if (!error) {
561 if (mode >= ATA_UDMA0) {
562 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
563 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]);
564 }
565 else if (mode >= ATA_WDMA0) {
566 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
567 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]);
568 }
569 else {
570 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
571 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]);
572 }
573 atadev->mode = mode;
574 }
575 }
576
577 /*
578 * Cypress chipset support functions
579 */
580 int
581 ata_cypress_ident(device_t dev)
582 {
583 struct ata_pci_controller *ctlr = device_get_softc(dev);
584
585 /*
586 * the Cypress chip is a mess, it contains two ATA functions, but
587 * both channels are visible on the first one.
588 * simply ignore the second function for now, as the right
589 * solution (ignoring the second channel on the first function)
590 * doesn't work with the crappy ATA interrupt setup on the alpha.
591 */
592 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 &&
593 pci_get_function(dev) == 1 &&
594 pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
595 device_set_desc(dev, "Cypress 82C693 ATA controller");
596 ctlr->chipinit = ata_cypress_chipinit;
597 return 0;
598 }
599 return ENXIO;
600 }
601
602 static int
603 ata_cypress_chipinit(device_t dev)
604 {
605 struct ata_pci_controller *ctlr = device_get_softc(dev);
606
607 if (ata_setup_interrupt(dev))
608 return ENXIO;
609
610 ctlr->setmode = ata_cypress_setmode;
611 return 0;
612 }
613
614 static void
615 ata_cypress_setmode(struct ata_device *atadev, int mode)
616 {
617 device_t parent = device_get_parent(atadev->channel->dev);
618 int error;
619
620 mode = ata_limit_mode(atadev, mode, ATA_WDMA2);
621
622 /* XXX missing WDMA0+1 + PIO modes */
623 if (mode == ATA_WDMA2) {
624 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,mode);
625 if (bootverbose)
626 ata_prtdev(atadev, "%ssetting WDMA2 on Cypress chip\n",
627 error ? "FAILURE " : "");
628 if (!error) {
629 pci_write_config(parent, atadev->channel->unit?0x4e:0x4c,0x2020,2);
630 atadev->mode = mode;
631 return;
632 }
633 }
634 /* we could set PIO mode timings, but we assume the BIOS did that */
635 }
636
637 /*
638 * HighPoint chipset support functions
639 */
640 int
641 ata_highpoint_ident(device_t dev)
642 {
643 struct ata_pci_controller *ctlr = device_get_softc(dev);
644 struct ata_chip_id *idx;
645 static struct ata_chip_id ids[] =
646 {{ ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT372" },
647 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HighPoint HPT370" },
648 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HighPoint HPT368" },
649 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HighPoint HPT366" },
650 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT372" },
651 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT302" },
652 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT371" },
653 { ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HighPoint HPT374" },
654 { 0, 0, 0, 0, 0, 0}};
655 char buffer[64];
656
657 if (!(idx = ata_match_chip(dev, ids)))
658 return ENXIO;
659
660 strcpy(buffer, idx->text);
661 if (idx->cfg1 == HPT374) {
662 if (pci_get_function(dev) == 0)
663 strcat(buffer, " (channel 0+1)");
664 else if (pci_get_function(dev) == 1)
665 strcat(buffer, " (channel 2+3)");
666 }
667 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
668 device_set_desc_copy(dev, buffer);
669 ctlr->chip = idx;
670 ctlr->chipinit = ata_highpoint_chipinit;
671 return 0;
672 }
673
674 static int
675 ata_highpoint_chipinit(device_t dev)
676 {
677 struct ata_pci_controller *ctlr = device_get_softc(dev);
678 int rid = ATA_IRQ_RID;
679
680 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
681 RF_SHAREABLE | RF_ACTIVE))) {
682 device_printf(dev, "unable to map interrupt\n");
683 return ENXIO;
684 }
685 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
686 ata_highpoint_intr, ctlr, &ctlr->handle))) {
687 device_printf(dev, "unable to setup interrupt\n");
688 return ENXIO;
689 }
690
691 if (ctlr->chip->cfg2 == HPTOLD) {
692 /* disable interrupt prediction */
693 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
694 }
695 else {
696 /* disable interrupt prediction */
697 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
698 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
699
700 /* enable interrupts */
701 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
702
703 /* set clocks etc */
704 if (ctlr->chip->cfg1 < HPT372)
705 pci_write_config(dev, 0x5b, 0x22, 1);
706 else
707 pci_write_config(dev, 0x5b,
708 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
709 }
710 ctlr->setmode = ata_highpoint_setmode;
711 return 0;
712 }
713
714 static void
715 ata_highpoint_intr(void *data)
716 {
717 struct ata_pci_controller *ctlr = data;
718 struct ata_channel *ch;
719 int unit;
720
721 /* implement this as a toggle instead to balance load XXX */
722 for (unit = 0; unit < 2; unit++) {
723 if (!(ch = ctlr->interrupt[unit].argument))
724 continue;
725 if (ch->dma) {
726 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
727
728 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
729 ATA_BMSTAT_INTERRUPT)
730 continue;
731 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
732 DELAY(1);
733 }
734 ctlr->interrupt[unit].function(ch);
735 }
736 }
737
738 static void
739 ata_highpoint_setmode(struct ata_device *atadev, int mode)
740 {
741 device_t parent = device_get_parent(atadev->channel->dev);
742 struct ata_pci_controller *ctlr = device_get_softc(parent);
743 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
744 int error;
745 u_int32_t timings33[][4] = {
746 /* HPT366 HPT370 HPT372 HPT374 mode */
747 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
748 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
749 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
750 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
751 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
752 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
753 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
754 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
755 { 0x10c8a731, 0x16514e31, 0x1c82dc62, 0x121882ea }, /* UDMA 0 */
756 { 0x10cba731, 0x164d4e31, 0x1c9adc62, 0x12148254 }, /* UDMA 1 */
757 { 0x10caa731, 0x16494e31, 0x1c91dc62, 0x120c8242 }, /* UDMA 2 */
758 { 0x10cfa731, 0x166d4e31, 0x1c8edc62, 0x128c8242 }, /* UDMA 3 */
759 { 0x10c9a731, 0x16454e31, 0x1c8ddc62, 0x12ac8242 }, /* UDMA 4 */
760 { 0, 0x16454e31, 0x1c6ddc62, 0x12848242 }, /* UDMA 5 */
761 { 0, 0, 0x1c81dc62, 0x12448242 } /* UDMA 6 */
762 };
763
764 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
765
766 if (ctlr->chip->cfg1 == HPT366 && ATAPI_DEVICE(atadev))
767 mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX);
768
769 mode = ata_highpoint_check_80pin(atadev, mode);
770
771 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
772
773 if (bootverbose)
774 ata_prtdev(atadev, "%ssetting %s on HighPoint chip\n",
775 (error) ? "FAILURE " : "", ata_mode2str(mode));
776 if (!error)
777 pci_write_config(parent, 0x40 + (devno << 2),
778 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
779 atadev->mode = mode;
780 }
781
782 static int
783 ata_highpoint_check_80pin(struct ata_device *atadev, int mode)
784 {
785 device_t parent = device_get_parent(atadev->channel->dev);
786 struct ata_pci_controller *ctlr = device_get_softc(parent);
787 u_int8_t reg, val, res;
788
789 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(parent) == 1) {
790 reg = atadev->channel->unit ? 0x57 : 0x53;
791 val = pci_read_config(parent, reg, 1);
792 pci_write_config(parent, reg, val | 0x80, 1);
793 }
794 else {
795 reg = 0x5b;
796 val = pci_read_config(parent, reg, 1);
797 pci_write_config(parent, reg, val & 0xfe, 1);
798 }
799 res = pci_read_config(parent, 0x5a, 1) & (atadev->channel->unit ? 0x1:0x2);
800 pci_write_config(parent, reg, val, 1);
801
802 if (mode > ATA_UDMA2 && res) {
803 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
804 mode = ATA_UDMA2;
805 }
806 return mode;
807 }
808
809 /*
810 * Intel chipset support functions
811 */
812 int
813 ata_intel_ident(device_t dev)
814 {
815 struct ata_pci_controller *ctlr = device_get_softc(dev);
816 struct ata_chip_id *idx;
817 static struct ata_chip_id ids[] =
818 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "Intel PIIX" },
819 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "Intel PIIX3" },
820 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
821 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
822 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
823 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "Intel ICH0" },
824 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "Intel ICH" },
825 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "Intel ICH" },
826 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "Intel ICH2" },
827 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH2" },
828 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "Intel ICH3" },
829 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH3" },
830 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "Intel ICH4" },
831 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH4" },
832 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "Intel ICH5" },
833 { ATA_I82801EB_S1,0, 0, 0x00, ATA_SA150, "Intel ICH5" },
834 { ATA_I82801EB_R1,0, 0, 0x00, ATA_SA150, "Intel ICH5" },
835 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "Intel 6300ESB" },
836 { ATA_I6300ESB_S1,0, 0, 0x00, ATA_SA150, "Intel 6300ESB" },
837 { ATA_I6300ESB_R1,0, 0, 0x00, ATA_SA150, "Intel 6300ESB" },
838 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "Intel ICH6" },
839 { ATA_I82801FB_S1,0, 0, 0x00, ATA_SA150, "Intel ICH6" },
840 { ATA_I82801FB_R1,0, 0, 0x00, ATA_SA150, "Intel ICH6" },
841 { 0, 0, 0, 0, 0, 0}};
842 char buffer[64];
843
844 if (!(idx = ata_match_chip(dev, ids)))
845 return ENXIO;
846
847 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
848 device_set_desc_copy(dev, buffer);
849 ctlr->chip = idx;
850 ctlr->chipinit = ata_intel_chipinit;
851 return 0;
852 }
853
854 static int
855 ata_intel_chipinit(device_t dev)
856 {
857 struct ata_pci_controller *ctlr = device_get_softc(dev);
858 int rid = ATA_IRQ_RID;
859
860 if (!ata_legacy(dev)) {
861 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
862 RF_SHAREABLE | RF_ACTIVE))) {
863 device_printf(dev, "unable to map interrupt\n");
864 return ENXIO;
865 }
866 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
867 ata_intel_intr, ctlr, &ctlr->handle))) {
868 device_printf(dev, "unable to setup interrupt\n");
869 return ENXIO;
870 }
871 }
872
873 if (ctlr->chip->chipid == ATA_I82371FB) {
874 ctlr->setmode = ata_intel_old_setmode;
875 }
876 else if (ctlr->chip->max_dma < ATA_SA150) {
877 ctlr->setmode = ata_intel_new_setmode;
878 }
879 else {
880 pci_write_config(dev, PCIR_COMMAND,
881 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
882 ctlr->reset = ata_intel_reset;
883 ctlr->setmode = ata_sata_setmode;
884 }
885 return 0;
886 }
887
888 static void
889 ata_intel_intr(void *data)
890 {
891 struct ata_pci_controller *ctlr = data;
892 struct ata_channel *ch;
893 int unit;
894
895 /* implement this as a toggle instead to balance load XXX */
896 for (unit = 0; unit < 2; unit++) {
897 if (!(ch = ctlr->interrupt[unit].argument))
898 continue;
899 if (ch->dma) {
900 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
901
902 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
903 ATA_BMSTAT_INTERRUPT)
904 continue;
905 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
906 DELAY(1);
907 }
908 ctlr->interrupt[unit].function(ch);
909 }
910 }
911
912 static void
913 ata_intel_old_setmode(struct ata_device *atadev, int mode)
914 {
915 /* NOT YET */
916 }
917
918 static void
919 ata_intel_reset(struct ata_channel *ch)
920 {
921 device_t parent = device_get_parent(ch->dev);
922 struct ata_pci_controller *ctlr = device_get_softc(parent);
923 int mask, timeout = 100;
924
925 /* ICH6 has 4 SATA ports as master/slave on 2 channels so deal with pairs */
926 if (ctlr->chip->chipid == ATA_I82801FB_S1 ||
927 ctlr->chip->chipid == ATA_I82801FB_R1) {
928 mask = (0x0005 << ch->unit);
929 }
930 else {
931 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */
932 if (pci_read_config(parent, 0x90, 1) & 0x04)
933 mask = 0x0003;
934 else
935 mask = (0x0001 << ch->unit);
936 }
937 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2);
938 DELAY(10);
939 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2);
940
941 while (timeout--) {
942 ata_udelay(10000);
943 if ((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) {
944 ata_udelay(10000);
945 return;
946 }
947 }
948 }
949
950 static void
951 ata_intel_new_setmode(struct ata_device *atadev, int mode)
952 {
953 device_t parent = device_get_parent(atadev->channel->dev);
954 struct ata_pci_controller *ctlr = device_get_softc(parent);
955 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
956 u_int32_t reg40 = pci_read_config(parent, 0x40, 4);
957 u_int8_t reg44 = pci_read_config(parent, 0x44, 1);
958 u_int8_t reg48 = pci_read_config(parent, 0x48, 1);
959 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2);
960 u_int16_t reg54 = pci_read_config(parent, 0x54, 2);
961 u_int32_t mask40 = 0, new40 = 0;
962 u_int8_t mask44 = 0, new44 = 0;
963 int error;
964 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
965 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
966
967 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
968
969 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
970 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
971 mode = ATA_UDMA2;
972 }
973
974 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
975
976 if (bootverbose)
977 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
978 (error) ? "FAILURE " : "",
979 ata_mode2str(mode), ctlr->chip->text);
980 if (error)
981 return;
982
983 if (mode >= ATA_UDMA0) {
984 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2);
985 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno<<2))) |
986 (0x01 + !(mode & 0x01)), 2);
987 }
988 else {
989 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2);
990 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))), 2);
991 }
992 reg54 |= 0x0400;
993 if (mode >= ATA_UDMA2)
994 pci_write_config(parent, 0x54, reg54 | (0x1 << devno), 2);
995 else
996 pci_write_config(parent, 0x54, reg54 & ~(0x1 << devno), 2);
997
998 if (mode >= ATA_UDMA5)
999 pci_write_config(parent, 0x54, reg54 | (0x1000 << devno), 2);
1000 else
1001 pci_write_config(parent, 0x54, reg54 & ~(0x1000 << devno), 2);
1002
1003 reg40 &= ~0x00ff00ff;
1004 reg40 |= 0x40774077;
1005
1006 if (atadev->unit == ATA_MASTER) {
1007 mask40 = 0x3300;
1008 new40 = timings[ata_mode2idx(mode)] << 8;
1009 }
1010 else {
1011 mask44 = 0x0f;
1012 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
1013 (timings[ata_mode2idx(mode)] & 0x03);
1014 }
1015 if (atadev->channel->unit) {
1016 mask40 <<= 16;
1017 new40 <<= 16;
1018 mask44 <<= 4;
1019 new44 <<= 4;
1020 }
1021 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4);
1022 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1);
1023
1024 atadev->mode = mode;
1025 }
1026
1027 /*
1028 * Integrated Technology Express Inc. (ITE) chipset support functions
1029 */
1030 int
1031 ata_ite_ident(device_t dev)
1032 {
1033 struct ata_pci_controller *ctlr = device_get_softc(dev);
1034
1035 if (pci_get_devid(dev) == ATA_IT8212F) {
1036 device_set_desc(dev, "ITE IT8212F ATA133 controller");
1037 ctlr->chipinit = ata_ite_chipinit;
1038 return 0;
1039 }
1040 return ENXIO;
1041 }
1042
1043 static int
1044 ata_ite_chipinit(device_t dev)
1045 {
1046 struct ata_pci_controller *ctlr = device_get_softc(dev);
1047
1048 if (ata_setup_interrupt(dev))
1049 return ENXIO;
1050
1051 ctlr->setmode = ata_ite_setmode;
1052
1053 /* set PCI mode and 66Mhz reference clock */
1054 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1);
1055
1056 /* set default active & recover timings */
1057 pci_write_config(dev, 0x54, 0x31, 1);
1058 pci_write_config(dev, 0x56, 0x31, 1);
1059 return 0;
1060 }
1061
1062 static void
1063 ata_ite_setmode(struct ata_device *atadev, int mode)
1064 {
1065 device_t parent = device_get_parent(atadev->channel->dev);
1066 struct ata_channel *ch = atadev->channel;
1067 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1068 int error;
1069
1070 /* correct the mode for what the HW supports */
1071 mode = ata_limit_mode(atadev, mode, ATA_UDMA6);
1072
1073 /* check the CBLID bits for 80 conductor cable detection */
1074 if (mode > ATA_UDMA2 && (pci_read_config(parent, 0x40, 2) &
1075 (ch->unit ? (1<<3) : (1<<2)))) {
1076 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
1077 mode = ATA_UDMA2;
1078 }
1079
1080 /* set the wanted mode on the device */
1081 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1082
1083 if (bootverbose)
1084 ata_prtdev(atadev, "%s setting %s on ITE8212F chip\n",
1085 (error) ? "failed" : "success", ata_mode2str(mode));
1086
1087 /* if the device accepted the mode change, setup the HW accordingly */
1088 if (!error) {
1089 if (mode >= ATA_UDMA0) {
1090 u_int8_t udmatiming[] =
1091 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
1092
1093 /* enable UDMA mode */
1094 pci_write_config(parent, 0x50,
1095 pci_read_config(parent, 0x50, 1) &
1096 ~(1 << (devno + 3)), 1);
1097
1098 /* set UDMA timing */
1099 pci_write_config(parent,
1100 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit),
1101 udmatiming[mode & ATA_MODE_MASK], 1);
1102 }
1103 else {
1104 u_int8_t chtiming[] =
1105 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
1106
1107 /* disable UDMA mode */
1108 pci_write_config(parent, 0x50,
1109 pci_read_config(parent, 0x50, 1) |
1110 (1 << (devno + 3)), 1);
1111
1112 /* set active and recover timing (shared between master & slave) */
1113 if (pci_read_config(parent, 0x54 + (ch->unit << 2), 1) <
1114 chtiming[ata_mode2idx(mode)])
1115 pci_write_config(parent, 0x54 + (ch->unit << 2),
1116 chtiming[ata_mode2idx(mode)], 1);
1117 }
1118 atadev->mode = mode;
1119 }
1120 }
1121 /*
1122 * National chipset support functions
1123 */
1124 int
1125 ata_national_ident(device_t dev)
1126 {
1127 struct ata_pci_controller *ctlr = device_get_softc(dev);
1128
1129 /* this chip is a clone of the Cyrix chip, bugs and all */
1130 if (pci_get_devid(dev) == ATA_SC1100) {
1131 device_set_desc(dev, "National Geode SC1100 ATA33 controller");
1132 ctlr->chipinit = ata_national_chipinit;
1133 return 0;
1134 }
1135 return ENXIO;
1136 }
1137
1138 static device_t nat_host = NULL;
1139
1140 static int
1141 ata_national_chipinit(device_t dev)
1142 {
1143 struct ata_pci_controller *ctlr = device_get_softc(dev);
1144 device_t *children;
1145 int nchildren, i;
1146
1147 if (ata_setup_interrupt(dev))
1148 return ENXIO;
1149
1150 /* locate the ISA part in the southbridge and enable UDMA33 */
1151 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
1152 for (i = 0; i < nchildren; i++) {
1153 if (pci_get_devid(children[i]) == 0x0510100b) {
1154 nat_host = children[i];
1155 break;
1156 }
1157 }
1158 free(children, M_TEMP);
1159 }
1160 ctlr->setmode = ata_national_setmode;
1161 return 0;
1162 }
1163
1164 static void
1165 ata_national_setmode(struct ata_device *atadev, int mode)
1166 {
1167 device_t parent = device_get_parent(atadev->channel->dev);
1168 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
1169 u_int32_t piotiming[] =
1170 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
1171 0x00803020, 0x20102010, 0x00100010,
1172 0x00100010, 0x00100010, 0x00100010 };
1173 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
1174 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
1175 int error;
1176
1177 atadev->channel->dma->alignment = 16;
1178 atadev->channel->dma->max_iosize = 126 * DEV_BSIZE;
1179
1180 mode = ata_limit_mode(atadev, mode, ATA_UDMA2);
1181
1182 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1183
1184 if (bootverbose)
1185 ata_prtdev(atadev, "%s setting %s on National chip\n",
1186 (error) ? "failed" : "success", ata_mode2str(mode));
1187 if (!error) {
1188 if (mode >= ATA_UDMA0) {
1189 pci_write_config(parent, 0x44 + (devno << 3),
1190 udmatiming[mode & ATA_MODE_MASK], 4);
1191 }
1192 else if (mode >= ATA_WDMA0) {
1193 pci_write_config(parent, 0x44 + (devno << 3),
1194 dmatiming[mode & ATA_MODE_MASK], 4);
1195 }
1196 else {
1197 pci_write_config(parent, 0x44 + (devno << 3),
1198 pci_read_config(parent, 0x44 + (devno << 3), 4) |
1199 0x80000000, 4);
1200 }
1201 pci_write_config(parent, 0x40 + (devno << 3),
1202 piotiming[ata_mode2idx(mode)], 4);
1203 atadev->mode = mode;
1204 }
1205 }
1206
1207 /*
1208 * nVidia chipset support functions
1209 */
1210 int
1211 ata_nvidia_ident(device_t dev)
1212 {
1213 struct ata_pci_controller *ctlr = device_get_softc(dev);
1214 struct ata_chip_id *idx;
1215 static struct ata_chip_id ids[] =
1216 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nVidia nForce" },
1217 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce2" },
1218 { ATA_NFORCE2_MCP, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce2 MCP" },
1219 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce3" },
1220 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce3 Pro" },
1221 { ATA_NFORCE3_MCP, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce3 MCP" },
1222 { ATA_NFORCE4, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce4" },
1223 { 0, 0, 0, 0, 0, 0}};
1224 char buffer[64];
1225
1226 if (!(idx = ata_match_chip(dev, ids)))
1227 return ENXIO;
1228
1229 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
1230 device_set_desc_copy(dev, buffer);
1231 ctlr->chip = idx;
1232 ctlr->chipinit = ata_nvidia_chipinit;
1233 return 0;
1234 }
1235
1236 static int
1237 ata_nvidia_chipinit(device_t dev)
1238 {
1239 struct ata_pci_controller *ctlr = device_get_softc(dev);
1240
1241 if (ata_setup_interrupt(dev))
1242 return ENXIO;
1243
1244 /* disable prefetch, postwrite */
1245 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
1246
1247 ctlr->setmode = ata_via_family_setmode;
1248 return 0;
1249 }
1250
1251 /*
1252 * Promise chipset support functions
1253 */
1254 #define ATA_PDC_APKT_OFFSET 0x00000010
1255 #define ATA_PDC_HPKT_OFFSET 0x00000040
1256 #define ATA_PDC_ASG_OFFSET 0x00000080
1257 #define ATA_PDC_LSG_OFFSET 0x000000c0
1258 #define ATA_PDC_HSG_OFFSET 0x00000100
1259 #define ATA_PDC_CHN_OFFSET 0x00000400
1260 #define ATA_PDC_BUF_BASE 0x00400000
1261 #define ATA_PDC_BUF_OFFSET 0x00100000
1262 #define ATA_PDC_MAX_HPKT 8
1263 #define ATA_PDC_WRITE_REG 0x00
1264 #define ATA_PDC_WRITE_CTL 0x0e
1265 #define ATA_PDC_WRITE_END 0x08
1266 #define ATA_PDC_WAIT_NBUSY 0x10
1267 #define ATA_PDC_WAIT_READY 0x18
1268 #define ATA_PDC_1B 0x20
1269 #define ATA_PDC_2B 0x40
1270
1271 struct ata_promise_sx4 {
1272 struct mtx mtx;
1273 u_int32_t array[ATA_PDC_MAX_HPKT];
1274 int head, tail;
1275 int busy;
1276 };
1277
1278 int
1279 ata_promise_ident(device_t dev)
1280 {
1281 struct ata_pci_controller *ctlr = device_get_softc(dev);
1282 struct ata_chip_id *idx;
1283 static struct ata_chip_id ids[] =
1284 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "Promise PDC20246" },
1285 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "Promise PDC20262" },
1286 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "Promise PDC20263" },
1287 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "Promise PDC20265" },
1288 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "Promise PDC20267" },
1289 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "Promise PDC20268" },
1290 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20269" },
1291 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "Promise PDC20270" },
1292 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20271" },
1293 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20275" },
1294 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "Promise PDC20276" },
1295 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20277" },
1296 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20318" },
1297 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20319" },
1298 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "Promise PDC20371" },
1299 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "Promise PDC20375" },
1300 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "Promise PDC20376" },
1301 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "Promise PDC20377" },
1302 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "Promise PDC20378" },
1303 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "Promise PDC20379" },
1304 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "Promise PDC20571" },
1305 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "Promise PDC20575" },
1306 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "Promise PDC20579" },
1307 { ATA_PDC20580, 0, PRMIO, PRCMBO2, ATA_SA150, "Promise PDC20580" },
1308 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "Promise PDC20617" },
1309 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "Promise PDC20618" },
1310 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "Promise PDC20619" },
1311 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "Promise PDC20620" },
1312 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "Promise PDC20621" },
1313 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "Promise PDC20622" },
1314 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "Promise PDC40518" },
1315 { 0, 0, 0, 0, 0, 0}};
1316 char buffer[64];
1317 uintptr_t devid = 0;
1318
1319 if (!(idx = ata_match_chip(dev, ids)))
1320 return ENXIO;
1321
1322 /* if we are on a SuperTrak SX6000 dont attach */
1323 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
1324 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
1325 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
1326 devid == ATA_I960RM)
1327 return ENXIO;
1328
1329 strcpy(buffer, idx->text);
1330
1331 /* if we are on a FastTrak TX4, adjust the interrupt resource */
1332 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
1333 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
1334 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
1335 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) {
1336 static long start = 0, end = 0;
1337
1338 if (pci_get_slot(dev) == 1) {
1339 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
1340 strcat(buffer, " (channel 0+1)");
1341 }
1342 else if (pci_get_slot(dev) == 2 && start && end) {
1343 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
1344 start = end = 0;
1345 strcat(buffer, " (channel 2+3)");
1346 }
1347 else {
1348 start = end = 0;
1349 }
1350 }
1351 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
1352 device_set_desc_copy(dev, buffer);
1353 ctlr->chip = idx;
1354 ctlr->chipinit = ata_promise_chipinit;
1355 return 0;
1356 }
1357
1358 static int
1359 ata_promise_chipinit(device_t dev)
1360 {
1361 struct ata_pci_controller *ctlr = device_get_softc(dev);
1362 int rid = ATA_IRQ_RID;
1363
1364 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1365 RF_SHAREABLE | RF_ACTIVE))) {
1366 device_printf(dev, "unable to map interrupt\n");
1367 return ENXIO;
1368 }
1369
1370 if (ctlr->chip->max_dma >= ATA_SA150)
1371 ctlr->setmode = ata_sata_setmode;
1372 else
1373 ctlr->setmode = ata_promise_setmode;
1374
1375 switch (ctlr->chip->cfg1) {
1376 case PRNEW:
1377 /* setup clocks */
1378 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a);
1379
1380 ctlr->dmainit = ata_promise_new_dmainit;
1381 /* FALLTHROUGH */
1382
1383 case PROLD:
1384 /* enable burst mode */
1385 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01);
1386
1387 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1388 ata_promise_old_intr, ctlr, &ctlr->handle))) {
1389 device_printf(dev, "unable to setup interrupt\n");
1390 return ENXIO;
1391 }
1392 break;
1393
1394 case PRTX:
1395 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1396 ata_promise_tx2_intr, ctlr, &ctlr->handle))) {
1397 device_printf(dev, "unable to setup interrupt\n");
1398 return ENXIO;
1399 }
1400 break;
1401
1402 case PRMIO:
1403 // if (ctlr->r_res1)
1404 // bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
1405 ctlr->r_type1 = SYS_RES_MEMORY;
1406 ctlr->r_rid1 = PCIR_BAR(4);
1407 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
1408 &ctlr->r_rid1, RF_ACTIVE)))
1409 return ENXIO;
1410
1411 ctlr->r_type2 = SYS_RES_MEMORY;
1412 ctlr->r_rid2 = PCIR_BAR(3);
1413 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1414 &ctlr->r_rid2, RF_ACTIVE)))
1415 return ENXIO;
1416
1417 ctlr->reset = ata_promise_mio_reset;
1418 ctlr->dmainit = ata_promise_mio_dmainit;
1419 ctlr->allocate = ata_promise_mio_allocate;
1420
1421 switch (ctlr->chip->cfg2) {
1422 case PRPATA:
1423 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) +
1424 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2;
1425 break;
1426
1427 case PRCMBO:
1428 ATA_OUTL(ctlr->r_res2, 0x06c, 0x000000ff);
1429 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 3;
1430 break;
1431
1432 case PRSATA:
1433 ATA_OUTL(ctlr->r_res2, 0x06c, 0x000000ff);
1434 ctlr->channels = 4;
1435 break;
1436
1437 case PRCMBO2:
1438 ATA_OUTL(ctlr->r_res2, 0x060, 0x000000ff);
1439 ctlr->channels = 3;
1440 break;
1441
1442 case PRSATA2:
1443 ATA_OUTL(ctlr->r_res2, 0x060, 0x000000ff);
1444 ctlr->channels = 4;
1445 break;
1446
1447 case PRSX4X: {
1448 struct ata_promise_sx4 *hpkt;
1449 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080);
1450
1451 /* print info about cache memory */
1452 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n",
1453 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4,
1454 ((dimm >> 24) & 0xff),
1455 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ?
1456 " ECC enabled" : "" );
1457
1458 ATA_OUTL(ctlr->r_res2, 0x000c000c,
1459 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000));
1460
1461 ctlr->driver = malloc(sizeof(struct ata_promise_sx4),
1462 M_TEMP, M_NOWAIT | M_ZERO);
1463 hpkt = ctlr->driver;
1464 mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF);
1465 hpkt->busy = hpkt->head = hpkt->tail = 0;
1466
1467 ctlr->channels = 4;
1468
1469 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1470 ata_promise_sx4_intr, ctlr, &ctlr->handle))) {
1471 device_printf(dev, "unable to setup interrupt\n");
1472 return ENXIO;
1473 }
1474 return 0;
1475 }
1476 }
1477
1478 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1479 ata_promise_mio_intr, ctlr, &ctlr->handle))) {
1480 device_printf(dev, "unable to setup interrupt\n");
1481 return ENXIO;
1482 }
1483 return 0;
1484 }
1485 return ENXIO;
1486 }
1487
1488 static int
1489 ata_promise_mio_allocate(device_t dev, struct ata_channel *ch)
1490 {
1491 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1492 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0;
1493 int i;
1494
1495 for (i = ATA_DATA; i <= ATA_STATUS; i++) {
1496 ch->r_io[i].res = ctlr->r_res2;
1497 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7);
1498 }
1499 ch->r_io[ATA_ALTSTAT].res = ctlr->r_res2;
1500 ch->r_io[ATA_ALTSTAT].offset = offset + 0x0238 + (ch->unit << 7);
1501 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
1502 ch->flags |= ATA_USE_16BIT;
1503 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) ||
1504 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2))
1505 ch->flags |= ATA_NO_SLAVE;
1506 ata_generic_hw(ch);
1507 if (ctlr->chip->cfg2 & PRSX4X)
1508 ch->hw.command = ata_promise_sx4_command;
1509 else
1510 ch->hw.command = ata_promise_mio_command;
1511 return 0;
1512 }
1513
1514 static void
1515 ata_promise_mio_intr(void *data)
1516 {
1517 struct ata_pci_controller *ctlr = data;
1518 struct ata_channel *ch;
1519 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x00040);
1520 u_int32_t status = 0;
1521 int unit;
1522
1523 if (ctlr->chip->cfg2 & (PRSATA | PRCMBO)) {
1524 status = ATA_INL(ctlr->r_res2, 0x06c);
1525 ATA_OUTL(ctlr->r_res2, 0x06c, status & 0x000000ff);
1526 }
1527 if (ctlr->chip->cfg2 & (PRSATA2 | PRCMBO2)) {
1528 ATA_OUTL(ctlr->r_res2, 0x040, vector & 0x0000ffff);
1529 status = ATA_INL(ctlr->r_res2, 0x060);
1530 ATA_OUTL(ctlr->r_res2, 0x060, status & 0x000000ff);
1531 }
1532 for (unit = 0; unit < ctlr->channels; unit++) {
1533 if (status & (0x00000011 << unit))
1534 if ((ch = ctlr->interrupt[unit].argument))
1535 ata_promise_mio_reset(ch);
1536 if (vector & (1 << (unit + 1)))
1537 if ((ch = ctlr->interrupt[unit].argument))
1538 ctlr->interrupt[unit].function(ch);
1539 }
1540 }
1541
1542 static void
1543 ata_promise_sx4_intr(void *data)
1544 {
1545 struct ata_pci_controller *ctlr = data;
1546 struct ata_channel *ch;
1547 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480);
1548 int unit;
1549
1550 for (unit = 0; unit < ctlr->channels; unit++) {
1551 if (vector & (1 << (unit + 1)))
1552 if ((ch = ctlr->interrupt[unit].argument))
1553 ctlr->interrupt[unit].function(ch);
1554 if (vector & (1 << (unit + 5)))
1555 if ((ch = ctlr->interrupt[unit].argument))
1556 ata_promise_queue_hpkt(ctlr,
1557 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
1558 ATA_PDC_HPKT_OFFSET));
1559 if (vector & (1 << (unit + 9))) {
1560 ata_promise_next_hpkt(ctlr);
1561 if ((ch = ctlr->interrupt[unit].argument))
1562 ctlr->interrupt[unit].function(ch);
1563 }
1564 if (vector & (1 << (unit + 13))) {
1565 ata_promise_next_hpkt(ctlr);
1566 if ((ch = ctlr->interrupt[unit].argument))
1567 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
1568 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
1569 ATA_PDC_APKT_OFFSET));
1570 }
1571 }
1572 }
1573
1574 static int
1575 ata_promise_mio_dmastart(struct ata_channel *ch)
1576 {
1577 ch->flags |= ATA_DMA_ACTIVE;
1578 return 0;
1579 }
1580
1581 static int
1582 ata_promise_mio_dmastop(struct ata_channel *ch)
1583 {
1584 ch->flags &= ~ATA_DMA_ACTIVE;
1585 /* get status XXX SOS */
1586 return 0;
1587 }
1588
1589 static void
1590 ata_promise_mio_dmainit(struct ata_channel *ch)
1591 {
1592 ata_dmainit(ch);
1593 if (ch->dma) {
1594 ch->dma->start = ata_promise_mio_dmastart;
1595 ch->dma->stop = ata_promise_mio_dmastop;
1596 }
1597 }
1598
1599 static void
1600 ata_promise_mio_reset(struct ata_channel *ch)
1601 {
1602 struct ata_pci_controller *ctlr =
1603 device_get_softc(device_get_parent(ch->dev));
1604
1605 switch (ctlr->chip->cfg2) {
1606 case PRSX4X: {
1607 struct ata_promise_sx4 *hpktp = ctlr->driver;
1608
1609 /* softreset channel ATA module */
1610 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1);
1611 DELAY(1000);
1612 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7),
1613 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) &
1614 ~0x00003f9f) | (ch->unit + 1));
1615
1616 /* softreset HOST module */
1617 mtx_lock(&hpktp->mtx);
1618 ATA_OUTL(ctlr->r_res2, 0xc012c,
1619 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11));
1620 DELAY(10);
1621 ATA_OUTL(ctlr->r_res2, 0xc012c,
1622 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f));
1623 mtx_unlock(&hpktp->mtx);
1624 }
1625 break;
1626
1627 case PRCMBO:
1628 case PRCMBO2:
1629 /* softreset channel ATA module */
1630 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
1631 ata_udelay(10000);
1632 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
1633 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
1634 ~0x00003f9f) | (ch->unit + 1));
1635 break;
1636
1637 case PRSATA: {
1638 u_int32_t status = 0;
1639 int timeout;
1640
1641 /* mask plug/unplug intr */
1642 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit));
1643
1644 /* softreset channels ATA module */
1645 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
1646 ata_udelay(10000);
1647 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
1648 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
1649 ~0x00003f9f) | (ch->unit + 1));
1650
1651 /* enable PHY XXX SOS */
1652 /* wait up to 1 sec for "connect well" */
1653 for (timeout = 0; timeout > 1000000 ; timeout += 100) {
1654 status = ATA_INL(ctlr->r_res2, 0x400 + (ch->unit << 8));
1655
1656 if ((status & 0x313) == 0x112)
1657 break;
1658 ata_udelay(10000);
1659 }
1660 if (timeout >= 1000000)
1661 device_printf(ch->dev, "connect status=%08x\n", status);
1662
1663 /* reset and enable plug/unplug intr */
1664 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit));
1665 }
1666 break;
1667
1668 case PRSATA2: {
1669 u_int32_t status = 0;
1670 int timeout;
1671
1672 /* set portmultiplier port */
1673 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f);
1674
1675 /* mask plug/unplug intr */
1676 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit));
1677
1678 /* softreset channels ATA module */
1679 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
1680 ata_udelay(10000);
1681 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
1682 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
1683 ~0x00003f9f) | (ch->unit + 1));
1684
1685 /* enable PHY XXX SOS */
1686 /* set PHY mode to "improved" */
1687 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8),
1688 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) &
1689 ~0x00000003) | 0x00000001);
1690
1691 /* wait up to 1 sec for "connect well" */
1692 for (timeout = 0; timeout > 1000000 ; timeout += 100) {
1693 status = ATA_INL(ctlr->r_res2, 0x400 + (ch->unit << 8));
1694
1695 if ((status & 0x737) == 0x113 || (status & 0x727) == 0x123)
1696 break;
1697 ata_udelay(10000);
1698 }
1699 if (timeout >= 1000000)
1700 device_printf(ch->dev, "connect status=%08x\n", status);
1701
1702 /* reset and enable plug/unplug intr */
1703 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit));
1704
1705 /* set portmultiplier port */
1706 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00);
1707 }
1708 break;
1709 }
1710 }
1711
1712 static int
1713 ata_promise_mio_command(struct ata_device *atadev, u_int8_t command,
1714 u_int64_t lba, u_int16_t count, u_int16_t feature)
1715 {
1716 struct ata_pci_controller *ctlr =
1717 device_get_softc(device_get_parent(atadev->channel->dev));
1718 u_int32_t *wordp = (u_int32_t *)atadev->channel->dma->workspace;
1719
1720 ATA_OUTL(ctlr->r_res2, (atadev->channel->unit + 1) << 2, 0x00000001);
1721
1722 switch (command) {
1723 default:
1724 return ata_generic_command(atadev, command, lba, count, feature);
1725
1726 case ATA_READ_DMA:
1727 wordp[0] = htole32(0x04 | ((atadev->channel->unit+1)<<16) | (0x00<<24));
1728 break;
1729
1730 case ATA_WRITE_DMA:
1731 wordp[0] = htole32(0x00 | ((atadev->channel->unit+1)<<16) | (0x00<<24));
1732 break;
1733 }
1734 wordp[1] = htole32(atadev->channel->dma->mdmatab);
1735 wordp[2] = 0;
1736 ata_promise_apkt((u_int8_t*)wordp, atadev, command, lba, count, feature);
1737
1738 ATA_OUTL(ctlr->r_res2, 0x0240 + (atadev->channel->unit << 7),
1739 atadev->channel->dma->wdmatab);
1740 return 0;
1741 }
1742
1743 static int
1744 ata_promise_sx4_command(struct ata_device *atadev, u_int8_t command,
1745 u_int64_t lba, u_int16_t count, u_int16_t feature)
1746 {
1747 struct ata_channel *ch = atadev->channel;
1748 struct ata_dma_prdentry *prd = ch->dma->dmatab;
1749 struct ata_pci_controller *ctlr =
1750 device_get_softc(device_get_parent(ch->dev));
1751 caddr_t window = rman_get_virtual(ctlr->r_res1);
1752 u_int32_t *wordp;
1753 int i, idx, length = 0;
1754
1755 switch (command) {
1756
1757 default:
1758 return -1;
1759
1760 case ATA_ATA_IDENTIFY:
1761 case ATA_READ:
1762 case ATA_READ_MUL:
1763 case ATA_WRITE:
1764 case ATA_WRITE_MUL:
1765 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
1766 return ata_generic_command(atadev, command, lba, count, feature);
1767
1768 case ATA_SETFEATURES:
1769 case ATA_FLUSHCACHE:
1770 case ATA_SLEEP:
1771 case ATA_SET_MULTI:
1772 wordp = (u_int32_t *)
1773 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
1774 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24));
1775 wordp[1] = 0;
1776 wordp[2] = 0;
1777 ata_promise_apkt((u_int8_t *)wordp, atadev, command, lba,count,feature);
1778 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
1779 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
1780 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
1781 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET));
1782 return 0;
1783
1784 case ATA_READ_DMA:
1785 case ATA_WRITE_DMA:
1786 wordp = (u_int32_t *)
1787 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET);
1788 i = idx = 0;
1789 do {
1790 wordp[idx++] = htole32(prd[i].addr);
1791 wordp[idx++] = htole32(prd[i].count & ~ATA_DMA_EOT);
1792 length += (prd[i].count & ~ATA_DMA_EOT);
1793 } while (!(prd[i++].count & ATA_DMA_EOT));
1794 wordp[idx - 1] |= htole32(ATA_DMA_EOT);
1795
1796 wordp = (u_int32_t *)
1797 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET);
1798 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
1799 wordp[1] = htole32((count * DEV_BSIZE) | ATA_DMA_EOT);
1800
1801 wordp = (u_int32_t *)
1802 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET);
1803 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
1804 wordp[1] = htole32((count * DEV_BSIZE) | ATA_DMA_EOT);
1805
1806 wordp = (u_int32_t *)
1807 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET);
1808 if (command == ATA_READ_DMA)
1809 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24));
1810 if (command == ATA_WRITE_DMA)
1811 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24));
1812 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET);
1813 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET);
1814 wordp[3] = 0;
1815
1816 wordp = (u_int32_t *)
1817 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
1818 if (command == ATA_READ_DMA)
1819 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24));
1820 if (command == ATA_WRITE_DMA)
1821 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24));
1822 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET);
1823 wordp[2] = 0;
1824 ata_promise_apkt((u_int8_t *)wordp, atadev, command, lba,count,feature);
1825 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
1826
1827 if (command == ATA_READ_DMA) {
1828 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001);
1829 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001);
1830 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
1831 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET));
1832 }
1833 if (command == ATA_WRITE_DMA) {
1834 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001);
1835 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001);
1836 ata_promise_queue_hpkt(ctlr,
1837 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET));
1838 }
1839 return 0;
1840 }
1841 }
1842
1843 static int
1844 ata_promise_apkt(u_int8_t *bytep, struct ata_device *atadev, u_int8_t command,
1845 u_int64_t lba, u_int16_t count, u_int16_t feature)
1846 {
1847 int i = 12;
1848
1849 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE;
1850 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit;
1851 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL;
1852 bytep[i++] = ATA_A_4BIT;
1853
1854 if ((lba >= ATA_MAX_28BIT_LBA || count > 256) && atadev->param &&
1855 (atadev->param->support.command2 & ATA_SUPPORT_ADDRESS48)) {
1856 atadev->channel->flags |= ATA_48BIT_ACTIVE;
1857 if (command == ATA_READ_DMA)
1858 command = ATA_READ_DMA48;
1859 if (command == ATA_WRITE_DMA)
1860 command = ATA_WRITE_DMA48;
1861 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE;
1862 bytep[i++] = (feature >> 8) & 0xff;
1863 bytep[i++] = feature & 0xff;
1864 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT;
1865 bytep[i++] = (count >> 8) & 0xff;
1866 bytep[i++] = count & 0xff;
1867 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR;
1868 bytep[i++] = (lba >> 24) & 0xff;
1869 bytep[i++] = lba & 0xff;
1870 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
1871 bytep[i++] = (lba >> 32) & 0xff;
1872 bytep[i++] = (lba >> 8) & 0xff;
1873 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
1874 bytep[i++] = (lba >> 40) & 0xff;
1875 bytep[i++] = (lba >> 16) & 0xff;
1876 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
1877 bytep[i++] = ATA_D_LBA | atadev->unit;
1878 }
1879 else {
1880 atadev->channel->flags &= ~ATA_48BIT_ACTIVE;
1881 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE;
1882 bytep[i++] = feature;
1883 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT;
1884 bytep[i++] = count;
1885 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR;
1886 bytep[i++] = lba & 0xff;
1887 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
1888 bytep[i++] = (lba >> 8) & 0xff;
1889 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
1890 bytep[i++] = (lba >> 16) & 0xff;
1891 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
1892 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) |
1893 ATA_D_IBM | atadev->unit | ((lba >> 24) & 0xf);
1894 }
1895 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_CMD;
1896 bytep[i++] = command;
1897 return i;
1898 }
1899
1900 static void
1901 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt)
1902 {
1903 struct ata_promise_sx4 *hpktp = ctlr->driver;
1904
1905 mtx_lock(&hpktp->mtx);
1906 if (hpktp->tail == hpktp->head && !hpktp->busy) {
1907 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt);
1908 hpktp->busy = 1;
1909 }
1910 else
1911 hpktp->array[(hpktp->head++) & (ATA_PDC_MAX_HPKT - 1)] = hpkt;
1912 mtx_unlock(&hpktp->mtx);
1913 }
1914
1915 static void
1916 ata_promise_next_hpkt(struct ata_pci_controller *ctlr)
1917 {
1918 struct ata_promise_sx4 *hpktp = ctlr->driver;
1919
1920 mtx_lock(&hpktp->mtx);
1921 if (hpktp->tail != hpktp->head) {
1922 ATA_OUTL(ctlr->r_res2, 0x000c0100,
1923 hpktp->array[(hpktp->tail++) & (ATA_PDC_MAX_HPKT - 1)]);
1924 }
1925 else
1926 hpktp->busy = 0;
1927 mtx_unlock(&hpktp->mtx);
1928 }
1929
1930 static void
1931 ata_promise_tx2_intr(void *data)
1932 {
1933 struct ata_pci_controller *ctlr = data;
1934 struct ata_channel *ch;
1935 int unit;
1936
1937 /* implement this as a toggle instead to balance load XXX */
1938 for (unit = 0; unit < 2; unit++) {
1939 if (!(ch = ctlr->interrupt[unit].argument))
1940 continue;
1941 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
1942 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
1943 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
1944 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1945
1946 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
1947 ATA_BMSTAT_INTERRUPT)
1948 continue;
1949 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
1950 DELAY(1);
1951 }
1952 ctlr->interrupt[unit].function(ch);
1953 }
1954 }
1955 }
1956
1957 static void
1958 ata_promise_old_intr(void *data)
1959 {
1960 struct ata_pci_controller *ctlr = data;
1961 struct ata_channel *ch;
1962 int unit;
1963
1964 /* implement this as a toggle instead to balance load XXX */
1965 for (unit = 0; unit < 2; unit++) {
1966 if (!(ch = ctlr->interrupt[unit].argument))
1967 continue;
1968 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)){
1969 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
1970 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1971
1972 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
1973 ATA_BMSTAT_INTERRUPT)
1974 continue;
1975 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
1976 DELAY(1);
1977 }
1978 ctlr->interrupt[unit].function(ch);
1979 }
1980 }
1981 }
1982
1983 static int
1984 ata_promise_new_dmastart(struct ata_channel *ch)
1985 {
1986 struct ata_pci_controller *ctlr =
1987 device_get_softc(device_get_parent(ch->dev));
1988
1989 if (ch->flags & ATA_48BIT_ACTIVE) {
1990 ATA_OUTB(ctlr->r_res1, 0x11,
1991 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02));
1992 ATA_OUTL(ctlr->r_res1, 0x20,
1993 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) |
1994 (ch->dma->cur_iosize >> 1));
1995 }
1996 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) |
1997 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1998 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->mdmatab);
1999 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
2000 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) |
2001 ATA_BMCMD_START_STOP);
2002 ch->flags |= ATA_DMA_ACTIVE;
2003 return 0;
2004 }
2005
2006 static int
2007 ata_promise_new_dmastop(struct ata_channel *ch)
2008 {
2009 struct ata_pci_controller *ctlr =
2010 device_get_softc(device_get_parent(ch->dev));
2011 int error;
2012
2013 if (ch->flags & ATA_48BIT_ACTIVE) {
2014 ATA_OUTB(ctlr->r_res1, 0x11,
2015 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02));
2016 ATA_OUTL(ctlr->r_res1, 0x20, 0);
2017 }
2018 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT);
2019 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
2020 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
2021 ch->flags &= ~ATA_DMA_ACTIVE;
2022 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
2023 return error;
2024 }
2025
2026 static void
2027 ata_promise_new_dmainit(struct ata_channel *ch)
2028 {
2029 ata_dmainit(ch);
2030 if (ch->dma) {
2031 ch->dma->start = ata_promise_new_dmastart;
2032 ch->dma->stop = ata_promise_new_dmastop;
2033 }
2034 }
2035
2036 static void
2037 ata_promise_setmode(struct ata_device *atadev, int mode)
2038 {
2039 device_t parent = device_get_parent(atadev->channel->dev);
2040 struct ata_pci_controller *ctlr = device_get_softc(parent);
2041 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
2042 int error;
2043 u_int32_t timings33[][2] = {
2044 /* PROLD PRNEW mode */
2045 { 0x004ff329, 0x004fff2f }, /* PIO 0 */
2046 { 0x004fec25, 0x004ff82a }, /* PIO 1 */
2047 { 0x004fe823, 0x004ff026 }, /* PIO 2 */
2048 { 0x004fe622, 0x004fec24 }, /* PIO 3 */
2049 { 0x004fe421, 0x004fe822 }, /* PIO 4 */
2050 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */
2051 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */
2052 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */
2053 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */
2054 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */
2055 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */
2056 { 0, 0x00424ef6 }, /* UDMA 3 */
2057 { 0, 0x004127f3 }, /* UDMA 4 */
2058 { 0, 0x004127f3 } /* UDMA 5 */
2059 };
2060
2061 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
2062
2063 switch (ctlr->chip->cfg1) {
2064 case PROLD:
2065 case PRNEW:
2066 if (mode > ATA_UDMA2 && (pci_read_config(parent, 0x50, 2) &
2067 (atadev->channel->unit ? 1 << 11 : 1 << 10))) {
2068 ata_prtdev(atadev,
2069 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2070 mode = ATA_UDMA2;
2071 }
2072 if (ATAPI_DEVICE(atadev) && mode > ATA_PIO_MAX)
2073 mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX);
2074 break;
2075
2076 case PRTX:
2077 ATA_IDX_OUTB(atadev->channel, ATA_BMDEVSPEC_0, 0x0b);
2078 if (mode > ATA_UDMA2 &&
2079 ATA_IDX_INB(atadev->channel, ATA_BMDEVSPEC_1) & 0x04) {
2080 ata_prtdev(atadev,
2081 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2082 mode = ATA_UDMA2;
2083 }
2084 break;
2085
2086 case PRMIO:
2087 if (mode > ATA_UDMA2 &&
2088 (ATA_INL(ctlr->r_res2,
2089 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) +
2090 (atadev->channel->unit << 7)) & 0x01000000)) {
2091 ata_prtdev(atadev,
2092 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2093 mode = ATA_UDMA2;
2094 }
2095 break;
2096 }
2097
2098 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2099
2100 if (bootverbose)
2101 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
2102 (error) ? "FAILURE " : "",
2103 ata_mode2str(mode), ctlr->chip->text);
2104 if (!error) {
2105 if (ctlr->chip->cfg1 < PRTX)
2106 pci_write_config(parent, 0x60 + (devno << 2),
2107 timings33[ctlr->chip->cfg1][ata_mode2idx(mode)],4);
2108 atadev->mode = mode;
2109 }
2110 return;
2111 }
2112
2113 /*
2114 * ServerWorks chipset support functions
2115 */
2116 int
2117 ata_serverworks_ident(device_t dev)
2118 {
2119 struct ata_pci_controller *ctlr = device_get_softc(dev);
2120 struct ata_chip_id *idx;
2121 static struct ata_chip_id ids[] =
2122 {{ ATA_ROSB4, 0x00, SWKS33, 0x00, ATA_UDMA2, "ServerWorks ROSB4" },
2123 { ATA_CSB5, 0x92, SWKS100, 0x00, ATA_UDMA5, "ServerWorks CSB5" },
2124 { ATA_CSB5, 0x00, SWKS66, 0x00, ATA_UDMA4, "ServerWorks CSB5" },
2125 { ATA_CSB6, 0x00, SWKS100, 0x00, ATA_UDMA5, "ServerWorks CSB6" },
2126 { ATA_CSB6_1, 0x00, SWKS66, 0x00, ATA_UDMA4, "ServerWorks CSB6" },
2127 { 0, 0, 0, 0, 0, 0}};
2128 char buffer[64];
2129
2130 if (!(idx = ata_match_chip(dev, ids)))
2131 return ENXIO;
2132
2133 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
2134 device_set_desc_copy(dev, buffer);
2135 ctlr->chip = idx;
2136 ctlr->chipinit = ata_serverworks_chipinit;
2137 return 0;
2138 }
2139
2140 static int
2141 ata_serverworks_chipinit(device_t dev)
2142 {
2143 struct ata_pci_controller *ctlr = device_get_softc(dev);
2144
2145 if (ata_setup_interrupt(dev))
2146 return ENXIO;
2147
2148 if (ctlr->chip->cfg1 == SWKS33) {
2149 device_t *children;
2150 int nchildren, i;
2151
2152 /* locate the ISA part in the southbridge and enable UDMA33 */
2153 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
2154 for (i = 0; i < nchildren; i++) {
2155 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
2156 pci_write_config(children[i], 0x64,
2157 (pci_read_config(children[i], 0x64, 4) &
2158 ~0x00002000) | 0x00004000, 4);
2159 break;
2160 }
2161 }
2162 free(children, M_TEMP);
2163 }
2164 }
2165 else {
2166 pci_write_config(dev, 0x5a,
2167 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
2168 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1);
2169 }
2170 ctlr->setmode = ata_serverworks_setmode;
2171 return 0;
2172 }
2173
2174 static void
2175 ata_serverworks_setmode(struct ata_device *atadev, int mode)
2176 {
2177 device_t parent = device_get_parent(atadev->channel->dev);
2178 struct ata_pci_controller *ctlr = device_get_softc(parent);
2179 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
2180 int offset = (devno ^ 0x01) << 3;
2181 int error;
2182 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
2183 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
2184 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
2185
2186 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
2187
2188 mode = ata_check_80pin(atadev, mode);
2189
2190 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2191
2192 if (bootverbose)
2193 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
2194 (error) ? "FAILURE " : "",
2195 ata_mode2str(mode), ctlr->chip->text);
2196 if (!error) {
2197 if (mode >= ATA_UDMA0) {
2198 pci_write_config(parent, 0x56,
2199 (pci_read_config(parent, 0x56, 2) &
2200 ~(0xf << (devno << 2))) |
2201 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
2202 pci_write_config(parent, 0x54,
2203 pci_read_config(parent, 0x54, 1) |
2204 (0x01 << devno), 1);
2205 pci_write_config(parent, 0x44,
2206 (pci_read_config(parent, 0x44, 4) &
2207 ~(0xff << offset)) |
2208 (dmatimings[2] << offset), 4);
2209 }
2210 else if (mode >= ATA_WDMA0) {
2211 pci_write_config(parent, 0x54,
2212 pci_read_config(parent, 0x54, 1) &
2213 ~(0x01 << devno), 1);
2214 pci_write_config(parent, 0x44,
2215 (pci_read_config(parent, 0x44, 4) &
2216 ~(0xff << offset)) |
2217 (dmatimings[mode & ATA_MODE_MASK] << offset),4);
2218 }
2219 else
2220 pci_write_config(parent, 0x54,
2221 pci_read_config(parent, 0x54, 1) &
2222 ~(0x01 << devno), 1);
2223
2224 pci_write_config(parent, 0x40,
2225 (pci_read_config(parent, 0x40, 4) &
2226 ~(0xff << offset)) |
2227 (piotimings[ata_mode2idx(mode)] << offset), 4);
2228 atadev->mode = mode;
2229 }
2230 }
2231
2232 /*
2233 * Silicon Image (former CMD) chipset support functions
2234 */
2235 int
2236 ata_sii_ident(device_t dev)
2237 {
2238 struct ata_pci_controller *ctlr = device_get_softc(dev);
2239 struct ata_chip_id *idx;
2240 static struct ata_chip_id ids[] =
2241 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" },
2242 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" },
2243 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
2244 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
2245 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" },
2246 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
2247 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
2248 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" },
2249 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" },
2250 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" },
2251 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" },
2252 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" },
2253 { 0, 0, 0, 0, 0, 0}};
2254 char buffer[64];
2255
2256 if (!(idx = ata_match_chip(dev, ids)))
2257 return ENXIO;
2258
2259 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
2260 device_set_desc_copy(dev, buffer);
2261 ctlr->chip = idx;
2262 ctlr->chipinit = ata_sii_chipinit;
2263 return 0;
2264 }
2265
2266 static int
2267 ata_sii_chipinit(device_t dev)
2268 {
2269 struct ata_pci_controller *ctlr = device_get_softc(dev);
2270 int rid = ATA_IRQ_RID;
2271
2272 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2273 RF_SHAREABLE | RF_ACTIVE))) {
2274 device_printf(dev, "unable to map interrupt\n");
2275 return ENXIO;
2276 }
2277
2278 if (ctlr->chip->cfg1 == SIIMEMIO) {
2279 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
2280 ata_sii_intr, ctlr, &ctlr->handle))) {
2281 device_printf(dev, "unable to setup interrupt\n");
2282 return ENXIO;
2283 }
2284
2285 ctlr->r_type2 = SYS_RES_MEMORY;
2286 ctlr->r_rid2 = PCIR_BAR(5);
2287 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
2288 &ctlr->r_rid2, RF_ACTIVE)))
2289 return ENXIO;
2290
2291 if (ctlr->chip->cfg2 & SIISETCLK) {
2292 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
2293 pci_write_config(dev, 0x8a,
2294 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
2295 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
2296 device_printf(dev, "%s could not set ATA133 clock\n",
2297 ctlr->chip->text);
2298 }
2299
2300 /* enable interrupt as BIOS might not */
2301 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
2302
2303 if (ctlr->chip->cfg2 & SII4CH) {
2304 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
2305 ctlr->channels = 4;
2306 }
2307
2308 ctlr->allocate = ata_sii_allocate;
2309 if (ctlr->chip->max_dma >= ATA_SA150) {
2310 ctlr->reset = ata_sii_reset;
2311 ctlr->setmode = ata_sata_setmode;
2312 }
2313 else
2314 ctlr->setmode = ata_sii_setmode;
2315 }
2316 else {
2317 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
2318 ctlr->chip->cfg2 & SIIINTR ?
2319 ata_cmd_intr : ata_cmd_old_intr,
2320 ctlr, &ctlr->handle))) {
2321 device_printf(dev, "unable to setup interrupt\n");
2322 return ENXIO;
2323 }
2324
2325 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
2326 device_printf(dev, "HW has secondary channel disabled\n");
2327 ctlr->channels = 1;
2328 }
2329
2330 /* enable interrupt as BIOS might not */
2331 pci_write_config(dev, 0x71, 0x01, 1);
2332
2333 ctlr->setmode = ata_cmd_setmode;
2334 }
2335 return 0;
2336 }
2337
2338 static int
2339 ata_sii_allocate(device_t dev, struct ata_channel *ch)
2340 {
2341 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2342 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
2343 int i;
2344
2345 for (i = ATA_DATA; i <= ATA_STATUS; i++) {
2346 ch->r_io[i].res = ctlr->r_res2;
2347 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
2348 }
2349 ch->r_io[ATA_ALTSTAT].res = ctlr->r_res2;
2350 ch->r_io[ATA_ALTSTAT].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
2351 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
2352 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
2353 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
2354 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
2355 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
2356 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
2357 ch->r_io[ATA_BMDEVSPEC_0].res = ctlr->r_res2;
2358 ch->r_io[ATA_BMDEVSPEC_0].offset = 0xa1 + (unit01 << 6) + (unit10 << 8);
2359 ch->r_io[ATA_BMDEVSPEC_1].res = ctlr->r_res2;
2360 ch->r_io[ATA_BMDEVSPEC_1].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
2361 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
2362
2363 if (ctlr->chip->max_dma >= ATA_SA150)
2364 ch->flags |= ATA_NO_SLAVE;
2365
2366 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) {
2367 ch->dma->boundary = 16 * DEV_BSIZE;
2368 ch->dma->max_iosize = 15 * DEV_BSIZE;
2369 }
2370
2371 ata_generic_hw(ch);
2372
2373 return 0;
2374 }
2375
2376 static void
2377 ata_sii_reset(struct ata_channel *ch)
2378 {
2379 ATA_IDX_OUTL(ch, ATA_BMDEVSPEC_1, 0x00000001);
2380 DELAY(25000);
2381 ATA_IDX_OUTL(ch, ATA_BMDEVSPEC_1, 0x00000000);
2382 ata_udelay(1000000);
2383 }
2384
2385 static void
2386 ata_sii_intr(void *data)
2387 {
2388 struct ata_pci_controller *ctlr = data;
2389 struct ata_channel *ch;
2390 int unit;
2391
2392 /* implement this as a toggle instead to balance load XXX */
2393 for (unit = 0; unit < ctlr->channels; unit++) {
2394 if (!(ch = ctlr->interrupt[unit].argument))
2395 continue;
2396 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_0) & 0x08) {
2397 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
2398 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
2399
2400 if (!(bmstat & ATA_BMSTAT_INTERRUPT))
2401 continue;
2402 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
2403 DELAY(1);
2404 }
2405 ctlr->interrupt[unit].function(ch);
2406 }
2407 }
2408 }
2409
2410 static void
2411 ata_cmd_intr(void *data)
2412 {
2413 struct ata_pci_controller *ctlr = data;
2414 struct ata_channel *ch;
2415 u_int8_t reg71;
2416 int unit;
2417
2418 /* implement this as a toggle instead to balance load XXX */
2419 for (unit = 0; unit < 2; unit++) {
2420 if (!(ch = ctlr->interrupt[unit].argument))
2421 continue;
2422 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
2423 (ch->unit ? 0x08 : 0x04))) {
2424 pci_write_config(device_get_parent(ch->dev), 0x71,
2425 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
2426 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
2427 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
2428
2429 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
2430 ATA_BMSTAT_INTERRUPT)
2431 continue;
2432 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
2433 DELAY(1);
2434 }
2435 ctlr->interrupt[unit].function(ch);
2436 }
2437 }
2438 }
2439
2440 static void
2441 ata_cmd_old_intr(void *data)
2442 {
2443 struct ata_pci_controller *ctlr = data;
2444 struct ata_channel *ch;
2445 int unit;
2446
2447 /* implement this as a toggle instead to balance load XXX */
2448 for (unit = 0; unit < 2; unit++) {
2449 if (!(ch = ctlr->interrupt[unit].argument))
2450 continue;
2451 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
2452 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
2453
2454 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
2455 ATA_BMSTAT_INTERRUPT)
2456 continue;
2457 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
2458 DELAY(1);
2459 }
2460 ctlr->interrupt[unit].function(ch);
2461 }
2462 }
2463
2464 static void
2465 ata_sii_setmode(struct ata_device *atadev, int mode)
2466 {
2467 device_t parent = device_get_parent(atadev->channel->dev);
2468 struct ata_pci_controller *ctlr = device_get_softc(parent);
2469 int rego = (atadev->channel->unit << 4) + (ATA_DEV(atadev->unit) << 1);
2470 int mreg = atadev->channel->unit ? 0x84 : 0x80;
2471 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2);
2472 int mval = pci_read_config(parent, mreg, 1) & ~mask;
2473 int error;
2474
2475 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
2476
2477 if (ctlr->chip->cfg2 & SIISETCLK) {
2478 if (mode > ATA_UDMA2 && (pci_read_config(parent, 0x79, 1) &
2479 (atadev->channel->unit ? 0x02 : 0x01))) {
2480 ata_prtdev(atadev,
2481 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2482 mode = ATA_UDMA2;
2483 }
2484 }
2485 else
2486 mode = ata_check_80pin(atadev, mode);
2487
2488 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2489
2490 if (bootverbose)
2491 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
2492 (error) ? "FAILURE " : "",
2493 ata_mode2str(mode), ctlr->chip->text);
2494 if (error)
2495 return;
2496
2497 if (mode >= ATA_UDMA0) {
2498 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
2499 u_int8_t ureg = 0xac + rego;
2500
2501 pci_write_config(parent, mreg,
2502 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1);
2503 pci_write_config(parent, ureg,
2504 (pci_read_config(parent, ureg, 1) & ~0x3f) |
2505 udmatimings[mode & ATA_MODE_MASK], 1);
2506
2507 }
2508 else if (mode >= ATA_WDMA0) {
2509 u_int8_t dreg = 0xa8 + rego;
2510 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
2511
2512 pci_write_config(parent, mreg,
2513 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1);
2514 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
2515
2516 }
2517 else {
2518 u_int8_t preg = 0xa4 + rego;
2519 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
2520
2521 pci_write_config(parent, mreg,
2522 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1);
2523 pci_write_config(parent, preg, piotimings[mode & ATA_MODE_MASK], 2);
2524 }
2525 atadev->mode = mode;
2526 }
2527
2528 static void
2529 ata_cmd_setmode(struct ata_device *atadev, int mode)
2530 {
2531 device_t parent = device_get_parent(atadev->channel->dev);
2532 struct ata_pci_controller *ctlr = device_get_softc(parent);
2533 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
2534 int error;
2535
2536 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
2537
2538 mode = ata_check_80pin(atadev, mode);
2539
2540 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2541
2542 if (bootverbose)
2543 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
2544 (error) ? "FAILURE " : "",
2545 ata_mode2str(mode), ctlr->chip->text);
2546 if (!error) {
2547 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
2548 int ureg = atadev->channel->unit ? 0x7b : 0x73;
2549
2550 if (mode >= ATA_UDMA0) {
2551 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
2552 { 0x11, 0x42 }, { 0x25, 0x8a },
2553 { 0x15, 0x4a }, { 0x05, 0x0a } };
2554
2555 u_int8_t umode = pci_read_config(parent, ureg, 1);
2556
2557 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
2558 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)];
2559 pci_write_config(parent, ureg, umode, 1);
2560 }
2561 else if (mode >= ATA_WDMA0) {
2562 int dmatimings[] = { 0x87, 0x32, 0x3f };
2563
2564 pci_write_config(parent, treg, dmatimings[mode & ATA_MODE_MASK], 1);
2565 pci_write_config(parent, ureg,
2566 pci_read_config(parent, ureg, 1) &
2567 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
2568 }
2569 else {
2570 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
2571 pci_write_config(parent, treg,
2572 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
2573 pci_write_config(parent, ureg,
2574 pci_read_config(parent, ureg, 1) &
2575 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
2576 }
2577 atadev->mode = mode;
2578 }
2579 }
2580
2581 /*
2582 * SiS chipset support functions
2583 */
2584 int
2585 ata_sis_ident(device_t dev)
2586 {
2587 struct ata_pci_controller *ctlr = device_get_softc(dev);
2588 struct ata_chip_id *idx;
2589 static struct ata_chip_id ids[] =
2590 {{ ATA_SIS964_S,0x00, SISSATA, 0, ATA_SA150, "SiS 964" }, /* south */
2591 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 964" }, /* south */
2592 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 963" }, /* south */
2593 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 962" }, /* south */
2594
2595 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 745" }, /* 1chip */
2596 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 735" }, /* 1chip */
2597 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 733" }, /* 1chip */
2598 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "SiS 730" }, /* 1chip */
2599
2600 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 635" }, /* 1chip */
2601 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 633" }, /* unknown */
2602 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "SiS 630S"}, /* 1chip */
2603 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "SiS 630" }, /* 1chip */
2604 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "SiS 620" }, /* 1chip */
2605
2606 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "SiS 550" },
2607 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "SiS 540" },
2608 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "SiS 530" },
2609
2610 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "SiS 5513" },
2611 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "SiS 5513" },
2612 { 0, 0, 0, 0, 0, 0 }};
2613 char buffer[64];
2614 int found = 0;
2615
2616 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev))))
2617 return ENXIO;
2618
2619 if (idx->cfg2 && !found) {
2620 u_int8_t reg57 = pci_read_config(dev, 0x57, 1);
2621
2622 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1);
2623 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) {
2624 found = 1;
2625 idx->cfg1 = SIS133NEW;
2626 idx->max_dma = ATA_UDMA6;
2627 sprintf(buffer, "SiS 962/963 %s controller",
2628 ata_mode2str(idx->max_dma));
2629 }
2630 pci_write_config(dev, 0x57, reg57, 1);
2631 }
2632 if (idx->cfg2 && !found) {
2633 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1);
2634
2635 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1);
2636 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) {
2637 struct ata_chip_id id[] =
2638 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }};
2639
2640 found = 1;
2641 if (ata_find_chip(dev, id, pci_get_slot(dev))) {
2642 idx->cfg1 = SIS133OLD;
2643 idx->max_dma = ATA_UDMA6;
2644 }
2645 else {
2646 idx->cfg1 = SIS100NEW;
2647 idx->max_dma = ATA_UDMA5;
2648 }
2649 sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
2650 }
2651 pci_write_config(dev, 0x4a, reg4a, 1);
2652 }
2653 if (!found)
2654 sprintf(buffer,"%s %s controller",idx->text,ata_mode2str(idx->max_dma));
2655
2656 device_set_desc_copy(dev, buffer);
2657 ctlr->chip = idx;
2658 ctlr->chipinit = ata_sis_chipinit;
2659 return 0;
2660 }
2661
2662 static int
2663 ata_sis_chipinit(device_t dev)
2664 {
2665 struct ata_pci_controller *ctlr = device_get_softc(dev);
2666
2667 if (ata_setup_interrupt(dev))
2668 return ENXIO;
2669
2670 switch (ctlr->chip->cfg1) {
2671 case SIS33:
2672 break;
2673 case SIS66:
2674 case SIS100OLD:
2675 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1);
2676 break;
2677 case SIS100NEW:
2678 case SIS133OLD:
2679 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1);
2680 break;
2681 case SIS133NEW:
2682 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2);
2683 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2);
2684 break;
2685 case SISSATA:
2686 pci_write_config(dev, PCIR_COMMAND,
2687 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
2688 ctlr->setmode = ata_sata_setmode;
2689 return 0;
2690 default:
2691 return ENXIO;
2692 }
2693 ctlr->setmode = ata_sis_setmode;
2694 return 0;
2695 }
2696
2697 static void
2698 ata_sis_setmode(struct ata_device *atadev, int mode)
2699 {
2700 device_t parent = device_get_parent(atadev->channel->dev);
2701 struct ata_pci_controller *ctlr = device_get_softc(parent);
2702 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
2703 int error;
2704
2705 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
2706
2707 if (ctlr->chip->cfg1 == SIS133NEW) {
2708 if (mode > ATA_UDMA2 &&
2709 pci_read_config(parent, atadev->channel->unit?0x52:0x50,2)&0x8000){
2710 ata_prtdev(atadev,
2711 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2712 mode = ATA_UDMA2;
2713 }
2714 }
2715 else {
2716 if (mode > ATA_UDMA2 &&
2717 pci_read_config(parent, 0x48, 1)&(atadev->channel->unit?0x20:0x10)){
2718 ata_prtdev(atadev,
2719 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2720 mode = ATA_UDMA2;
2721 }
2722 }
2723
2724 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2725
2726 if (bootverbose)
2727 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
2728 (error) ? "FAILURE " : "",
2729 ata_mode2str(mode), ctlr->chip->text);
2730 if (!error) {
2731 switch (ctlr->chip->cfg1) {
2732 case SIS133NEW: {
2733 u_int32_t timings[] =
2734 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
2735 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
2736 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
2737 u_int32_t reg;
2738
2739 reg = (pci_read_config(parent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
2740 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 4);
2741 break;
2742 }
2743 case SIS133OLD: {
2744 u_int16_t timings[] =
2745 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
2746 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
2747
2748 u_int16_t reg = 0x40 + (devno << 1);
2749
2750 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
2751 break;
2752 }
2753 case SIS100NEW: {
2754 u_int16_t timings[] =
2755 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
2756 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
2757 u_int16_t reg = 0x40 + (devno << 1);
2758
2759 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
2760 break;
2761 }
2762 case SIS100OLD:
2763 case SIS66:
2764 case SIS33: {
2765 u_int16_t timings[] =
2766 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
2767 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
2768 u_int16_t reg = 0x40 + (devno << 1);
2769
2770 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
2771 break;
2772 }
2773 }
2774 atadev->mode = mode;
2775 }
2776 }
2777
2778 /* VIA chipsets */
2779 int
2780 ata_via_ident(device_t dev)
2781 {
2782 struct ata_pci_controller *ctlr = device_get_softc(dev);
2783 struct ata_chip_id *idx;
2784 static struct ata_chip_id ids[] =
2785 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "VIA 82C586B" },
2786 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "VIA 82C586" },
2787 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "VIA 82C596B" },
2788 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "VIA 82C596" },
2789 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "VIA 82C686B"},
2790 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "VIA 82C686A" },
2791 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "VIA 82C686" },
2792 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "VIA 8231" },
2793 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "VIA 8233" },
2794 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "VIA 8233C" },
2795 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8233A" },
2796 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8235" },
2797 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8237" },
2798 { 0, 0, 0, 0, 0, 0 }};
2799 static struct ata_chip_id new_ids[] =
2800 {{ ATA_VIA6410, 0x00, 0x00, 0x00, ATA_UDMA6, "VIA 6410" },
2801 { ATA_VIA6420, 0x00, 0x00, 0x00, ATA_SA150, "VIA 6420" },
2802 { 0, 0, 0, 0, 0, 0 }};
2803 char buffer[64];
2804
2805 if (pci_get_devid(dev) == ATA_VIA82C571) {
2806 if (!(idx = ata_find_chip(dev, ids, -99)))
2807 return ENXIO;
2808 }
2809 else {
2810 if (!(idx = ata_match_chip(dev, new_ids)))
2811 return ENXIO;
2812 }
2813
2814 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
2815 device_set_desc_copy(dev, buffer);
2816 ctlr->chip = idx;
2817 ctlr->chipinit = ata_via_chipinit;
2818 return 0;
2819 }
2820
2821 static int
2822 ata_via_chipinit(device_t dev)
2823 {
2824 struct ata_pci_controller *ctlr = device_get_softc(dev);
2825
2826 if (ata_setup_interrupt(dev))
2827 return ENXIO;
2828
2829 if (ctlr->chip->max_dma >= ATA_SA150) {
2830 pci_write_config(dev, PCIR_COMMAND,
2831 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
2832 ctlr->setmode = ata_sata_setmode;
2833 return 0;
2834 }
2835
2836 /* prepare for ATA-66 on the 82C686a and 82C596b */
2837 if (ctlr->chip->cfg2 & VIACLK)
2838 pci_write_config(dev, 0x50, 0x030b030b, 4);
2839
2840 /* the southbridge might need the data corruption fix */
2841 if (ctlr->chip->cfg2 & VIABUG)
2842 ata_via_southbridge_fixup(dev);
2843
2844 /* set fifo configuration half'n'half */
2845 pci_write_config(dev, 0x43,
2846 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
2847
2848 /* set status register read retry */
2849 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
2850
2851 /* set DMA read & end-of-sector fifo flush */
2852 pci_write_config(dev, 0x46,
2853 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
2854
2855 /* set sector size */
2856 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
2857 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
2858
2859 ctlr->setmode = ata_via_family_setmode;
2860 return 0;
2861 }
2862
2863 static void
2864 ata_via_southbridge_fixup(device_t dev)
2865 {
2866 device_t *children;
2867 int nchildren, i;
2868
2869 if (device_get_children(device_get_parent(dev), &children, &nchildren))
2870 return;
2871
2872 for (i = 0; i < nchildren; i++) {
2873 if (pci_get_devid(children[i]) == ATA_VIA8363 ||
2874 pci_get_devid(children[i]) == ATA_VIA8371 ||
2875 pci_get_devid(children[i]) == ATA_VIA8662 ||
2876 pci_get_devid(children[i]) == ATA_VIA8361) {
2877 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
2878
2879 if ((reg76 & 0xf0) != 0xd0) {
2880 device_printf(dev,
2881 "Correcting VIA config for southbridge data corruption bug\n");
2882 pci_write_config(children[i], 0x75, 0x80, 1);
2883 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
2884 }
2885 break;
2886 }
2887 }
2888 free(children, M_TEMP);
2889 }
2890
2891 /* common code for VIA, AMD & nVidia */
2892 static void
2893 ata_via_family_setmode(struct ata_device *atadev, int mode)
2894 {
2895 device_t parent = device_get_parent(atadev->channel->dev);
2896 struct ata_pci_controller *ctlr = device_get_softc(parent);
2897 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
2898 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
2899 int modes[][7] = {
2900 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
2901 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
2902 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
2903 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
2904 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */
2905 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
2906 int reg = 0x53 - devno;
2907 int error;
2908
2909 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
2910
2911 if (ctlr->chip->cfg2 & AMDCABLE) {
2912 if (mode > ATA_UDMA2 &&
2913 !(pci_read_config(parent, 0x42, 1) & (1 << devno))) {
2914 ata_prtdev(atadev,
2915 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2916 mode = ATA_UDMA2;
2917 }
2918 }
2919 else
2920 mode = ata_check_80pin(atadev, mode);
2921
2922 if (ctlr->chip->cfg2 & NVIDIA)
2923 reg += 0x10;
2924
2925 if (ctlr->chip->cfg1 != VIA133)
2926 pci_write_config(parent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
2927
2928 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2929
2930 if (bootverbose)
2931 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
2932 (error) ? "FAILURE " : "", ata_mode2str(mode),
2933 ctlr->chip->text);
2934 if (!error) {
2935 if (mode >= ATA_UDMA0)
2936 pci_write_config(parent, reg,
2937 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
2938 else
2939 pci_write_config(parent, reg, 0x8b, 1);
2940 atadev->mode = mode;
2941 }
2942 }
2943
2944 /* misc functions */
2945 static struct ata_chip_id *
2946 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot)
2947 {
2948 device_t *children;
2949 int nchildren, i;
2950
2951 if (device_get_children(device_get_parent(dev), &children, &nchildren))
2952 return 0;
2953
2954 while (index->chipid != 0) {
2955 for (i = 0; i < nchildren; i++) {
2956 if (((slot >= 0 && pci_get_slot(children[i]) == slot) ||
2957 (slot < 0 && pci_get_slot(children[i]) <= -slot)) &&
2958 pci_get_devid(children[i]) == index->chipid &&
2959 pci_get_revid(children[i]) >= index->chiprev) {
2960 free(children, M_TEMP);
2961 return index;
2962 }
2963 }
2964 index++;
2965 }
2966 free(children, M_TEMP);
2967 return NULL;
2968 }
2969
2970 static struct ata_chip_id *
2971 ata_match_chip(device_t dev, struct ata_chip_id *index)
2972 {
2973 while (index->chipid != 0) {
2974 if (pci_get_devid(dev) == index->chipid &&
2975 pci_get_revid(dev) >= index->chiprev)
2976 return index;
2977 index++;
2978 }
2979 return NULL;
2980 }
2981
2982 static int
2983 ata_setup_interrupt(device_t dev)
2984 {
2985 struct ata_pci_controller *ctlr = device_get_softc(dev);
2986 int rid = ATA_IRQ_RID;
2987
2988 if (!ata_legacy(dev)) {
2989 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2990 RF_SHAREABLE | RF_ACTIVE))) {
2991 device_printf(dev, "unable to map interrupt\n");
2992 return ENXIO;
2993 }
2994 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
2995 ata_generic_intr, ctlr, &ctlr->handle))) {
2996 device_printf(dev, "unable to setup interrupt\n");
2997 return ENXIO;
2998 }
2999 }
3000 return 0;
3001 }
3002
3003 struct ata_serialize {
3004 struct mtx locked_mtx;
3005 int locked_ch;
3006 int restart_ch;
3007 };
3008
3009 static int
3010 ata_serialize(struct ata_channel *ch, int flags)
3011 {
3012 struct ata_pci_controller *ctlr =
3013 device_get_softc(device_get_parent(ch->dev));
3014 struct ata_serialize *serial;
3015 static int inited = 0;
3016 int res;
3017
3018 if (!inited) {
3019 ctlr->driver = malloc(sizeof(struct ata_serialize),
3020 M_TEMP, M_NOWAIT | M_ZERO);
3021 serial = ctlr->driver;
3022 mtx_init(&serial->locked_mtx, "ATA serialize lock", NULL, MTX_DEF);
3023 serial->locked_ch = -1;
3024 serial->restart_ch = -1;
3025 inited = 1;
3026 }
3027 else
3028 serial = ctlr->driver;
3029
3030 mtx_lock(&serial->locked_mtx);
3031 switch (flags) {
3032 case ATA_LF_LOCK:
3033 if (serial->locked_ch == -1)
3034 serial->locked_ch = ch->unit;
3035 if (serial->locked_ch != ch->unit)
3036 serial->restart_ch = ch->unit;
3037 break;
3038
3039 case ATA_LF_UNLOCK:
3040 if (serial->locked_ch == ch->unit) {
3041 serial->locked_ch = -1;
3042 if (serial->restart_ch != -1) {
3043 if (ctlr->interrupt[serial->restart_ch].argument) {
3044 mtx_unlock(&serial->locked_mtx);
3045 ata_start(ctlr->interrupt[serial->restart_ch].argument);
3046 mtx_lock(&serial->locked_mtx);
3047 }
3048 serial->restart_ch = -1;
3049 }
3050 }
3051 break;
3052
3053 case ATA_LF_WHICH:
3054 break;
3055 }
3056 res = serial->locked_ch;
3057 mtx_unlock(&serial->locked_mtx);
3058 return res;
3059 }
3060
3061 static int
3062 ata_check_80pin(struct ata_device *atadev, int mode)
3063 {
3064 if (mode > ATA_UDMA2 && !(atadev->param->hwres & ATA_CABLE_ID)) {
3065 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
3066 mode = ATA_UDMA2;
3067 }
3068 return mode;
3069 }
3070
3071 static int
3072 ata_mode2idx(int mode)
3073 {
3074 if ((mode & ATA_DMA_MASK) == ATA_UDMA0)
3075 return (mode & ATA_MODE_MASK) + 8;
3076 if ((mode & ATA_DMA_MASK) == ATA_WDMA0)
3077 return (mode & ATA_MODE_MASK) + 5;
3078 return (mode & ATA_MODE_MASK) - ATA_PIO0;
3079 }
Cache object: 9f8a8cc5d55dec043b955cb226bdce3e
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