1 /*-
2 * Copyright (c) 1998 - 2005 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD: src/sys/dev/ata/ata-chipset.c,v 1.126.2.4.2.1 2005/10/14 09:34:50 scottl Exp $");
31
32 #include "opt_ata.h"
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/ata.h>
37 #include <sys/bus.h>
38 #include <sys/endian.h>
39 #include <sys/malloc.h>
40 #include <sys/lock.h>
41 #include <sys/mutex.h>
42 #include <sys/sema.h>
43 #include <sys/taskqueue.h>
44 #include <vm/uma.h>
45 #include <machine/stdarg.h>
46 #include <machine/resource.h>
47 #include <machine/bus.h>
48 #include <sys/rman.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/ata/ata-all.h>
52 #include <dev/ata/ata-pci.h>
53 #include <ata_if.h>
54
55 /* local prototypes */
56 static int ata_generic_chipinit(device_t dev);
57 static void ata_generic_intr(void *data);
58 static void ata_generic_setmode(device_t dev, int mode);
59 static void ata_sata_setmode(device_t dev, int mode);
60 static int ata_sata_connect(struct ata_channel *ch);
61 static void ata_sata_phy_enable(struct ata_channel *ch);
62 static void ata_sata_phy_event(void *context, int dummy);
63 static int ata_ahci_allocate(device_t dev);
64 static int ata_ahci_setup_fis(u_int8_t *fis, struct ata_request *request);
65 static int ata_ahci_begin_transaction(struct ata_request *request);
66 static int ata_ahci_end_transaction(struct ata_request *request);
67 static void ata_ahci_intr(void *data);
68 static void ata_ahci_reset(device_t dev);
69 static void ata_ahci_dmainit(device_t dev);
70 static int ata_acard_chipinit(device_t dev);
71 static void ata_acard_intr(void *data);
72 static void ata_acard_850_setmode(device_t dev, int mode);
73 static void ata_acard_86X_setmode(device_t dev, int mode);
74 static int ata_ali_chipinit(device_t dev);
75 static int ata_ali_allocate(device_t dev);
76 static int ata_ali_sata_allocate(device_t dev);
77 static void ata_ali_reset(device_t dev);
78 static void ata_ali_setmode(device_t dev, int mode);
79 static int ata_amd_chipinit(device_t dev);
80 static int ata_ati_chipinit(device_t dev);
81 static void ata_ati_setmode(device_t dev, int mode);
82 static int ata_cyrix_chipinit(device_t dev);
83 static void ata_cyrix_setmode(device_t dev, int mode);
84 static int ata_cypress_chipinit(device_t dev);
85 static void ata_cypress_setmode(device_t dev, int mode);
86 static int ata_highpoint_chipinit(device_t dev);
87 static void ata_highpoint_intr(void *data);
88 static void ata_highpoint_setmode(device_t dev, int mode);
89 static int ata_highpoint_check_80pin(device_t dev, int mode);
90 static int ata_intel_chipinit(device_t dev);
91 static int ata_intel_31244_allocate(device_t dev);
92 static void ata_intel_31244_intr(void *data);
93 static void ata_intel_31244_reset(device_t dev);
94 static int ata_intel_31244_command(struct ata_request *request);
95 static void ata_intel_intr(void *data);
96 static void ata_intel_reset(device_t dev);
97 static void ata_intel_old_setmode(device_t dev, int mode);
98 static void ata_intel_new_setmode(device_t dev, int mode);
99 static int ata_ite_chipinit(device_t dev);
100 static void ata_ite_setmode(device_t dev, int mode);
101 static int ata_national_chipinit(device_t dev);
102 static void ata_national_setmode(device_t dev, int mode);
103 static int ata_nvidia_chipinit(device_t dev);
104 static int ata_nvidia_allocate(device_t dev);
105 static void ata_nvidia_intr(void *data);
106 static void ata_nvidia_reset(device_t dev);
107 static int ata_promise_chipinit(device_t dev);
108 static int ata_promise_mio_allocate(device_t dev);
109 static void ata_promise_mio_intr(void *data);
110 static void ata_promise_sx4_intr(void *data);
111 static void ata_promise_mio_dmainit(device_t dev);
112 static void ata_promise_mio_reset(device_t dev);
113 static int ata_promise_mio_command(struct ata_request *request);
114 static int ata_promise_sx4_command(struct ata_request *request);
115 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request);
116 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt);
117 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr);
118 static void ata_promise_tx2_intr(void *data);
119 static void ata_promise_old_intr(void *data);
120 static int ata_promise_new_dmastart(device_t dev);
121 static int ata_promise_new_dmastop(device_t dev);
122 static void ata_promise_new_dmareset(device_t dev);
123 static void ata_promise_new_dmainit(device_t dev);
124 static void ata_promise_setmode(device_t dev, int mode);
125 static int ata_serverworks_chipinit(device_t dev);
126 static void ata_serverworks_setmode(device_t dev, int mode);
127 static int ata_sii_chipinit(device_t dev);
128 static int ata_sii_allocate(device_t dev);
129 static void ata_sii_intr(void *data);
130 static void ata_cmd_intr(void *data);
131 static void ata_cmd_old_intr(void *data);
132 static void ata_sii_reset(device_t dev);
133 static void ata_sii_setmode(device_t dev, int mode);
134 static void ata_cmd_setmode(device_t dev, int mode);
135 static int ata_sis_chipinit(device_t dev);
136 static int ata_sis_allocate(device_t dev);
137 static void ata_sis_reset(device_t dev);
138 static void ata_sis_setmode(device_t dev, int mode);
139 static int ata_via_chipinit(device_t dev);
140 static int ata_via_allocate(device_t dev);
141 static void ata_via_reset(device_t dev);
142 static void ata_via_southbridge_fixup(device_t dev);
143 static void ata_via_family_setmode(device_t dev, int mode);
144 static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot);
145 static int ata_setup_interrupt(device_t dev);
146 static int ata_serialize(device_t dev, int flags);
147 static void ata_print_cable(device_t dev, u_int8_t *who);
148 static int ata_atapi(device_t dev);
149 static int ata_check_80pin(device_t dev, int mode);
150 static int ata_mode2idx(int mode);
151
152
153 /* generic or unknown ATA chipset support functions */
154 int
155 ata_generic_ident(device_t dev)
156 {
157 struct ata_pci_controller *ctlr = device_get_softc(dev);
158
159 device_set_desc(dev, "GENERIC ATA controller");
160 ctlr->chipinit = ata_generic_chipinit;
161 return 0;
162 }
163
164 static int
165 ata_generic_chipinit(device_t dev)
166 {
167 struct ata_pci_controller *ctlr = device_get_softc(dev);
168
169 if (ata_setup_interrupt(dev))
170 return ENXIO;
171 ctlr->setmode = ata_generic_setmode;
172 return 0;
173 }
174
175 static void
176 ata_generic_intr(void *data)
177 {
178 struct ata_pci_controller *ctlr = data;
179 struct ata_channel *ch;
180 int unit;
181
182 for (unit = 0; unit < ctlr->channels; unit++) {
183 if (!(ch = ctlr->interrupt[unit].argument))
184 continue;
185 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
186 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
187
188 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
189 ATA_BMSTAT_INTERRUPT)
190 continue;
191 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
192 DELAY(1);
193 }
194 ctlr->interrupt[unit].function(ch);
195 }
196 }
197
198 static void
199 ata_generic_setmode(device_t dev, int mode)
200 {
201 struct ata_device *atadev = device_get_softc(dev);
202
203 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
204 mode = ata_check_80pin(dev, mode);
205 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
206 atadev->mode = mode;
207 }
208
209
210 /* SATA support functions */
211 static void
212 ata_sata_setmode(device_t dev, int mode)
213 {
214 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
215 struct ata_device *atadev = device_get_softc(dev);
216
217 /*
218 * if we detect that the device isn't a real SATA device we limit
219 * the transfer mode to UDMA5/ATA100.
220 * this works around the problems some devices has with the
221 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133.
222 */
223 if (atadev->param.satacapabilities != 0x0000 &&
224 atadev->param.satacapabilities != 0xffff) {
225 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
226 ata_limit_mode(dev, mode, ATA_UDMA6)))
227 atadev->mode = ctlr->chip->max_dma;
228 }
229 else {
230 mode = ata_limit_mode(dev, mode, ATA_UDMA5);
231 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
232 atadev->mode = mode;
233 }
234 }
235
236 static int
237 ata_sata_connect(struct ata_channel *ch)
238 {
239 u_int32_t status;
240 int timeout;
241
242 /* wait up to 1 second for "connect well" */
243 for (timeout = 0; timeout < 100 ; timeout++) {
244 status = ATA_IDX_INL(ch, ATA_SSTATUS);
245 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 ||
246 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)
247 break;
248 ata_udelay(10000);
249 }
250 if (timeout >= 100) {
251 if (bootverbose)
252 device_printf(ch->dev, "SATA connect status=%08x\n", status);
253 return 0;
254 }
255
256 /* clear SATA error register */
257 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
258
259 /* find out what type device we got poll for spec'd 31 seconds */
260 /* XXX SOS 10 secs for now as I have little patience */
261 ch->devices = 0;
262 for (timeout = 0; timeout < 1000; timeout++) {
263 if (ATA_IDX_INB(ch, ATA_STATUS) & ATA_S_BUSY)
264 DELAY(10000);
265 else
266 break;
267 }
268 if (bootverbose)
269 device_printf(ch->dev, "SATA connect ready time=%dms\n", timeout * 10);
270 if (timeout < 1000) {
271 if ((ATA_IDX_INB(ch, ATA_CYL_LSB) == ATAPI_MAGIC_LSB) &&
272 (ATA_IDX_INB(ch, ATA_CYL_MSB) == ATAPI_MAGIC_MSB))
273 ch->devices = ATA_ATAPI_MASTER;
274 else
275 ch->devices = ATA_ATA_MASTER;
276 }
277 if (bootverbose)
278 device_printf(ch->dev, "sata_connect devices=0x%b\n",
279 ch->devices, "\2\3ATAPI_MASTER\1ATA_MASTER");
280 return 1;
281 }
282
283 static void
284 ata_sata_phy_enable(struct ata_channel *ch)
285 {
286 int loop, retry;
287
288 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) {
289 ata_sata_connect(ch);
290 return;
291 }
292
293 for (retry = 0; retry < 10; retry++) {
294 for (loop = 0; loop < 10; loop++) {
295 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET);
296 ata_udelay(100);
297 if ((ATA_IDX_INL(ch, ATA_SCONTROL) &
298 ATA_SC_DET_MASK) == ATA_SC_DET_RESET)
299 break;
300 }
301 ata_udelay(5000);
302 for (loop = 0; loop < 10; loop++) {
303 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_IDLE);
304 ata_udelay(100);
305 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 0) {
306 ata_sata_connect(ch);
307 return;
308 }
309 }
310 }
311 }
312
313 static void
314 ata_sata_phy_event(void *context, int dummy)
315 {
316 struct ata_connect_task *tp = (struct ata_connect_task *)context;
317 struct ata_channel *ch = device_get_softc(tp->dev);
318 device_t *children;
319 int nchildren, i;
320
321 mtx_lock(&Giant); /* newbus suckage it needs Giant */
322 if (tp->action == ATA_C_ATTACH) {
323 device_printf(tp->dev, "CONNECTED\n");
324 ata_sata_connect(ch);
325 ata_identify(tp->dev);
326 }
327 if (tp->action == ATA_C_DETACH) {
328 if (!device_get_children(tp->dev, &children, &nchildren)) {
329 for (i = 0; i < nchildren; i++)
330 if (children[i])
331 device_delete_child(tp->dev, children[i]);
332 free(children, M_TEMP);
333 }
334 mtx_lock(&ch->state_mtx);
335 ch->state = ATA_IDLE;
336 mtx_unlock(&ch->state_mtx);
337 device_printf(tp->dev, "DISCONNECTED\n");
338 }
339 mtx_unlock(&Giant); /* suckage code dealt with, release Giant */
340 free(tp, M_ATA);
341 }
342
343
344 /*
345 * AHCI v1.0 compliant SATA chipset support functions
346 */
347 struct ata_ahci_dma_prd {
348 u_int64_t dba;
349 u_int32_t reserved;
350 u_int32_t dbc; /* 0 based */
351 #define ATA_AHCI_PRD_MASK 0x003fffff /* max 4MB */
352 #define ATA_AHCI_PRD_IPC (1<<31)
353 } __packed;
354
355 struct ata_ahci_cmd_tab {
356 u_int8_t cfis[64];
357 u_int8_t acmd[32];
358 u_int8_t reserved[32];
359 struct ata_ahci_dma_prd prd_tab[16];
360 } __packed;
361
362 struct ata_ahci_cmd_list {
363 u_int16_t cmd_flags;
364 u_int16_t prd_length; /* PRD entries */
365 u_int32_t bytecount;
366 u_int64_t cmd_table_phys; /* 128byte aligned */
367 } __packed;
368
369
370 static int
371 ata_ahci_allocate(device_t dev)
372 {
373 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
374 struct ata_channel *ch = device_get_softc(dev);
375 int offset = (ch->unit << 7);
376
377 /* XXX SOS this is a hack to satisfy various legacy cruft */
378 ch->r_io[ATA_CYL_LSB].res = ctlr->r_res2;
379 ch->r_io[ATA_CYL_LSB].offset = ATA_AHCI_P_SIG + 1 + offset;
380 ch->r_io[ATA_CYL_MSB].res = ctlr->r_res2;
381 ch->r_io[ATA_CYL_MSB].offset = ATA_AHCI_P_SIG + 3 + offset;
382 ch->r_io[ATA_STATUS].res = ctlr->r_res2;
383 ch->r_io[ATA_STATUS].offset = ATA_AHCI_P_TFD + offset;
384 ch->r_io[ATA_ALTSTAT].res = ctlr->r_res2;
385 ch->r_io[ATA_ALTSTAT].offset = ATA_AHCI_P_TFD + offset;
386
387 /* set the SATA resources */
388 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
389 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset;
390 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
391 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset;
392 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
393 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset;
394 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
395 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset;
396
397 ch->hw.begin_transaction = ata_ahci_begin_transaction;
398 ch->hw.end_transaction = ata_ahci_end_transaction;
399 ch->hw.command = NULL; /* not used here */
400
401 /* setup the work areas */
402 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset,
403 ch->dma->work_bus + ATA_AHCI_CL_OFFSET);
404 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, 0x00000000);
405
406 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset,
407 ch->dma->work_bus + ATA_AHCI_FB_OFFSET);
408 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, 0x00000000);
409
410 /* enable wanted port interrupts */
411 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
412 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
413 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
414 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP |
415 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS |
416 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR));
417
418 /* start operations on this channel */
419 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
420 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
421 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
422 return 0;
423 }
424
425 static int
426 ata_ahci_setup_fis(u_int8_t *fis, struct ata_request *request)
427 {
428 struct ata_device *atadev = device_get_softc(request->dev);
429 int idx = 0;
430
431 /* XXX SOS add ATAPI commands support later */
432 ata_modify_if_48bit(request);
433
434 fis[idx++] = 0x27; /* host to device */
435 fis[idx++] = 0x80; /* command FIS (note PM goes here) */
436 fis[idx++] = request->u.ata.command;
437 fis[idx++] = request->u.ata.feature;
438
439 fis[idx++] = request->u.ata.lba;
440 fis[idx++] = request->u.ata.lba >> 8;
441 fis[idx++] = request->u.ata.lba >> 16;
442 fis[idx] = ATA_D_LBA | atadev->unit;
443 if (atadev->flags & ATA_D_48BIT_ACTIVE)
444 idx++;
445 else
446 fis[idx++] |= (request->u.ata.lba >> 24 & 0x0f);
447
448 fis[idx++] = request->u.ata.lba >> 24;
449 fis[idx++] = request->u.ata.lba >> 32;
450 fis[idx++] = request->u.ata.lba >> 40;
451 fis[idx++] = request->u.ata.feature >> 8;
452
453 fis[idx++] = request->u.ata.count;
454 fis[idx++] = request->u.ata.count >> 8;
455 fis[idx++] = 0x00;
456 fis[idx++] = ATA_A_4BIT;
457
458 fis[idx++] = 0x00;
459 fis[idx++] = 0x00;
460 fis[idx++] = 0x00;
461 fis[idx++] = 0x00;
462 return idx;
463 }
464
465 /* must be called with ATA channel locked and state_mtx held */
466 static int
467 ata_ahci_begin_transaction(struct ata_request *request)
468 {
469 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
470 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
471 struct ata_ahci_cmd_tab *ctp;
472 struct ata_ahci_cmd_list *clp;
473 int fis_size, entries;
474 int tag = 0;
475
476 /* get a piece of the workspace for this request */
477 ctp = (struct ata_ahci_cmd_tab *)
478 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag));
479
480 /* setup the FIS for this request */ /* XXX SOS ATAPI missing still */
481 if (!(fis_size = ata_ahci_setup_fis(&ctp->cfis[0], request))) {
482 device_printf(request->dev, "setting up SATA FIS failed\n");
483 request->result = EIO;
484 return ATA_OP_FINISHED;
485 }
486
487 /* if request moves data setup and load SG list */
488 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
489 if (ch->dma->load(ch->dev, request->data, request->bytecount,
490 request->flags & ATA_R_READ,
491 ctp->prd_tab, &entries)) {
492 device_printf(request->dev, "setting up DMA failed\n");
493 request->result = EIO;
494 return ATA_OP_FINISHED;
495 }
496 }
497
498 /* setup the command list entry */
499 clp = (struct ata_ahci_cmd_list *)
500 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
501
502 clp->prd_length = entries;
503 clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) |
504 (request->flags & ATA_R_ATAPI ? (1<<5) : 0) |
505 (fis_size / sizeof(u_int32_t));
506 clp->bytecount = 0;
507 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET +
508 (ATA_AHCI_CT_SIZE * tag));
509
510 /* clear eventual ACTIVE bit */
511 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag));
512
513 /* issue the command */
514 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + (ch->unit << 7), (1 << tag));
515
516 /* start the timeout */
517 callout_reset(&request->callout, request->timeout * hz,
518 (timeout_t*)ata_timeout, request);
519 return ATA_OP_CONTINUES;
520 }
521
522 /* must be called with ATA channel locked and state_mtx held */
523 static int
524 ata_ahci_end_transaction(struct ata_request *request)
525 {
526 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
527 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
528 struct ata_ahci_cmd_list *clp;
529 u_int32_t tf_data;
530 int tag = 0;
531
532 /* kill the timeout */
533 callout_stop(&request->callout);
534
535 /* get status */
536 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit << 7));
537 request->status = tf_data;
538
539 /* if error status get details */
540 if (request->status & ATA_S_ERROR)
541 request->error = tf_data >> 8;
542
543 /* record how much data we actually moved */
544 clp = (struct ata_ahci_cmd_list *)
545 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
546 request->donecount = clp->bytecount;
547
548 /* release SG list etc */
549 ch->dma->unload(ch->dev);
550
551 return ATA_OP_FINISHED;
552 }
553
554 static void
555 ata_ahci_intr(void *data)
556 {
557 struct ata_pci_controller *ctlr = data;
558 struct ata_channel *ch;
559 u_int32_t port, status, error, issued;
560 int unit;
561 int tag = 0;
562
563 port = ATA_INL(ctlr->r_res2, ATA_AHCI_IS);
564
565 for (unit = 0; unit < ctlr->channels; unit++) {
566 if (port & (1 << unit)) {
567 if ((ch = ctlr->interrupt[unit].argument)) {
568 struct ata_connect_task *tp;
569 int offset = (ch->unit << 7);
570
571 error = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SERR + offset);
572 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_SERR + offset, error);
573 status = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset);
574 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, status);
575 issued = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset);
576
577 /* do we have cold connect surprise */
578 if (status & ATA_AHCI_P_IX_CPD) {
579 printf("ata_ahci_intr status=%08x error=%08x issued=%08x\n",
580 status, error, issued);
581 }
582
583 /* check for and handle connect events */
584 if ((status & ATA_AHCI_P_IX_PC) &&
585 (tp = (struct ata_connect_task *)
586 malloc(sizeof(struct ata_connect_task),
587 M_ATA, M_NOWAIT | M_ZERO))) {
588
589 device_printf(ch->dev, "CONNECT requested\n");
590 tp->action = ATA_C_ATTACH;
591 tp->dev = ch->dev;
592 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
593 taskqueue_enqueue(taskqueue_thread, &tp->task);
594 }
595
596 /* check for and handle disconnect events */
597 if (((status & (ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC)) ==
598 ATA_AHCI_P_IX_PRC) &&
599 (tp = (struct ata_connect_task *)
600 malloc(sizeof(struct ata_connect_task),
601 M_ATA, M_NOWAIT | M_ZERO))) {
602
603 device_printf(ch->dev, "DISCONNECT requested\n");
604 tp->action = ATA_C_DETACH;
605 tp->dev = ch->dev;
606 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
607 taskqueue_enqueue(taskqueue_thread, &tp->task);
608 }
609
610 /* any drive action to take care of ? */
611 if (!(issued & (1<<tag)))
612 ctlr->interrupt[unit].function(ch);
613 }
614 }
615 }
616 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, port);
617 }
618
619 static void
620 ata_ahci_reset(device_t dev)
621 {
622 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
623 struct ata_channel *ch = device_get_softc(dev);
624 u_int32_t cmd;
625 int offset = (ch->unit << 7);
626
627 /* kill off all activity on this channel */
628 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
629 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
630 cmd & ~(ATA_AHCI_P_CMD_CR | ATA_AHCI_P_CMD_FR |
631 ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
632
633 DELAY(500000); /* XXX SOS this is not entirely wrong */
634
635 /* spin up device */
636 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, ATA_AHCI_P_CMD_SUD);
637
638 ata_sata_phy_enable(ch);
639
640 /* clear any interrupts pending on this channel */
641 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
642 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
643
644 /* start operations on this channel */
645 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
646 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
647 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
648 }
649
650 static void
651 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
652 {
653 struct ata_dmasetprd_args *args = xsc;
654 struct ata_ahci_dma_prd *prd = args->dmatab;
655 int i;
656
657 if (!(args->error = error)) {
658 for (i = 0; i < nsegs; i++) {
659 prd[i].dba = htole64(segs[i].ds_addr);
660 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK);
661 }
662 }
663 args->nsegs = nsegs;
664 }
665
666 static void
667 ata_ahci_dmainit(device_t dev)
668 {
669 struct ata_channel *ch = device_get_softc(dev);
670
671 ata_dmainit(dev);
672 if (ch->dma) {
673 /* note start and stop are not used here */
674 ch->dma->setprd = ata_ahci_dmasetprd;
675 ch->dma->max_iosize = 8192 * DEV_BSIZE;
676 }
677 }
678
679
680 /*
681 * Acard chipset support functions
682 */
683 int
684 ata_acard_ident(device_t dev)
685 {
686 struct ata_pci_controller *ctlr = device_get_softc(dev);
687 struct ata_chip_id *idx;
688 static struct ata_chip_id ids[] =
689 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "Acard ATP850" },
690 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "Acard ATP860A" },
691 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "Acard ATP860R" },
692 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "Acard ATP865A" },
693 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "Acard ATP865R" },
694 { 0, 0, 0, 0, 0, 0}};
695 char buffer[64];
696
697 if (!(idx = ata_match_chip(dev, ids)))
698 return ENXIO;
699
700 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
701 device_set_desc_copy(dev, buffer);
702 ctlr->chip = idx;
703 ctlr->chipinit = ata_acard_chipinit;
704 return 0;
705 }
706
707 static int
708 ata_acard_chipinit(device_t dev)
709 {
710 struct ata_pci_controller *ctlr = device_get_softc(dev);
711 int rid = ATA_IRQ_RID;
712
713 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
714 RF_SHAREABLE | RF_ACTIVE))) {
715 device_printf(dev, "unable to map interrupt\n");
716 return ENXIO;
717 }
718 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
719 ata_acard_intr, ctlr, &ctlr->handle))) {
720 device_printf(dev, "unable to setup interrupt\n");
721 return ENXIO;
722 }
723 if (ctlr->chip->cfg1 == ATPOLD) {
724 ctlr->setmode = ata_acard_850_setmode;
725 ctlr->locking = ata_serialize;
726 }
727 else
728 ctlr->setmode = ata_acard_86X_setmode;
729 return 0;
730 }
731
732 static void
733 ata_acard_intr(void *data)
734 {
735 struct ata_pci_controller *ctlr = data;
736 struct ata_channel *ch;
737 int unit;
738
739 for (unit = 0; unit < ctlr->channels; unit++) {
740 if (!(ch = ctlr->interrupt[unit].argument))
741 continue;
742 if (ctlr->chip->cfg1 == ATPOLD &&
743 ATA_LOCKING(ch->dev, ATA_LF_WHICH) != unit)
744 continue;
745 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
746 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
747
748 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
749 ATA_BMSTAT_INTERRUPT)
750 continue;
751 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
752 DELAY(1);
753 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
754 ATA_IDX_INB(ch, ATA_BMCMD_PORT)&~ATA_BMCMD_START_STOP);
755 DELAY(1);
756 }
757 ctlr->interrupt[unit].function(ch);
758 }
759 }
760
761 static void
762 ata_acard_850_setmode(device_t dev, int mode)
763 {
764 device_t gparent = GRANDPARENT(dev);
765 struct ata_pci_controller *ctlr = device_get_softc(gparent);
766 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
767 struct ata_device *atadev = device_get_softc(dev);
768 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
769 int error;
770
771 mode = ata_limit_mode(dev, mode,
772 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
773
774 /* XXX SOS missing WDMA0+1 + PIO modes */
775 if (mode >= ATA_WDMA2) {
776 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
777 if (bootverbose)
778 device_printf(dev, "%ssetting %s on %s chip\n",
779 (error) ? "FAILURE " : "",
780 ata_mode2str(mode), ctlr->chip->text);
781 if (!error) {
782 u_int8_t reg54 = pci_read_config(gparent, 0x54, 1);
783
784 reg54 &= ~(0x03 << (devno << 1));
785 if (mode >= ATA_UDMA0)
786 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1));
787 pci_write_config(gparent, 0x54, reg54, 1);
788 pci_write_config(gparent, 0x4a, 0xa6, 1);
789 pci_write_config(gparent, 0x40 + (devno << 1), 0x0301, 2);
790 atadev->mode = mode;
791 return;
792 }
793 }
794 /* we could set PIO mode timings, but we assume the BIOS did that */
795 }
796
797 static void
798 ata_acard_86X_setmode(device_t dev, int mode)
799 {
800 device_t gparent = GRANDPARENT(dev);
801 struct ata_pci_controller *ctlr = device_get_softc(gparent);
802 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
803 struct ata_device *atadev = device_get_softc(dev);
804 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
805 int error;
806
807
808 mode = ata_limit_mode(dev, mode,
809 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
810
811 mode = ata_check_80pin(dev, mode);
812
813 /* XXX SOS missing WDMA0+1 + PIO modes */
814 if (mode >= ATA_WDMA2) {
815 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
816 if (bootverbose)
817 device_printf(dev, "%ssetting %s on %s chip\n",
818 (error) ? "FAILURE " : "",
819 ata_mode2str(mode), ctlr->chip->text);
820 if (!error) {
821 u_int16_t reg44 = pci_read_config(gparent, 0x44, 2);
822
823 reg44 &= ~(0x000f << (devno << 2));
824 if (mode >= ATA_UDMA0)
825 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2));
826 pci_write_config(gparent, 0x44, reg44, 2);
827 pci_write_config(gparent, 0x4a, 0xa6, 1);
828 pci_write_config(gparent, 0x40 + devno, 0x31, 1);
829 atadev->mode = mode;
830 return;
831 }
832 }
833 /* we could set PIO mode timings, but we assume the BIOS did that */
834 }
835
836
837 /*
838 * Acer Labs Inc (ALI) chipset support functions
839 */
840 int
841 ata_ali_ident(device_t dev)
842 {
843 struct ata_pci_controller *ctlr = device_get_softc(dev);
844 struct ata_chip_id *idx;
845 static struct ata_chip_id ids[] =
846 {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "AcerLabs M5289" },
847 { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "AcerLabs M5287" },
848 { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "AcerLabs M5281" },
849 { ATA_ALI_5229, 0xc5, 0, ALINEW, ATA_UDMA6, "AcerLabs M5229" },
850 { ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "AcerLabs M5229" },
851 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "AcerLabs M5229" },
852 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "AcerLabs M5229" },
853 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "AcerLabs M5229" },
854 { 0, 0, 0, 0, 0, 0}};
855 char buffer[64];
856
857 if (!(idx = ata_match_chip(dev, ids)))
858 return ENXIO;
859
860 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
861 device_set_desc_copy(dev, buffer);
862 ctlr->chip = idx;
863 ctlr->chipinit = ata_ali_chipinit;
864 return 0;
865 }
866
867 static int
868 ata_ali_chipinit(device_t dev)
869 {
870 struct ata_pci_controller *ctlr = device_get_softc(dev);
871
872 if (ata_setup_interrupt(dev))
873 return ENXIO;
874
875 switch (ctlr->chip->cfg2) {
876 case ALISATA:
877 pci_write_config(dev, PCIR_COMMAND,
878 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
879 ctlr->channels = ctlr->chip->cfg1;
880 ctlr->allocate = ata_ali_sata_allocate;
881 ctlr->setmode = ata_sata_setmode;
882 break;
883
884 case ALINEW:
885 /* use device interrupt as byte count end */
886 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
887
888 /* enable cable detection and UDMA support on newer chips */
889 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1);
890
891 /* enable ATAPI UDMA mode */
892 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1);
893
894 /* only chips with revision > 0xc4 can do 48bit DMA */
895 if (ctlr->chip->chiprev <= 0xc4)
896 device_printf(dev,
897 "using PIO transfers above 137GB as workaround for "
898 "48bit DMA access bug, expect reduced performance\n");
899 ctlr->reset = ata_ali_reset;
900 ctlr->allocate = ata_ali_allocate;
901 ctlr->setmode = ata_ali_setmode;
902 break;
903
904 case ALIOLD:
905 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
906 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
907 ctlr->setmode = ata_ali_setmode;
908 break;
909 }
910 return 0;
911 }
912
913 static int
914 ata_ali_allocate(device_t dev)
915 {
916 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
917 struct ata_channel *ch = device_get_softc(dev);
918
919 /* setup the usual register normal pci style */
920 if (ata_pci_allocate(dev))
921 return ENXIO;
922
923 /* older chips can't do 48bit DMA transfers */
924 if (ctlr->chip->chiprev <= 0xc4)
925 ch->flags |= ATA_NO_48BIT_DMA;
926
927 return 0;
928 }
929
930 static int
931 ata_ali_sata_allocate(device_t dev)
932 {
933 device_t parent = device_get_parent(dev);
934 struct ata_pci_controller *ctlr = device_get_softc(parent);
935 struct ata_channel *ch = device_get_softc(dev);
936 struct resource *io = NULL, *ctlio = NULL;
937 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
938 int i, rid;
939
940 rid = PCIR_BAR(0) + (unit01 ? 8 : 0);
941 io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
942 if (!io)
943 return ENXIO;
944
945 rid = PCIR_BAR(1) + (unit01 ? 8 : 0);
946 ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
947 if (!ctlio) {
948 bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io);
949 return ENXIO;
950 }
951
952 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
953 ch->r_io[i].res = io;
954 ch->r_io[i].offset = i + (unit10 ? 8 : 0);
955 }
956 ch->r_io[ATA_CONTROL].res = ctlio;
957 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0);
958 ch->r_io[ATA_IDX_ADDR].res = io;
959 ata_default_registers(dev);
960 if (ctlr->r_res1) {
961 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
962 ch->r_io[i].res = ctlr->r_res1;
963 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
964 }
965 }
966 ch->flags |= ATA_NO_SLAVE;
967
968 /* XXX SOS PHY handling awkward in ALI chip not supported yet */
969 ata_generic_hw(dev);
970 return 0;
971 }
972
973 static void
974 ata_ali_reset(device_t dev)
975 {
976 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
977 struct ata_channel *ch = device_get_softc(dev);
978 device_t *children;
979 int nchildren, i;
980
981 ata_generic_reset(dev);
982
983 /*
984 * workaround for datacorruption bug found on at least SUN Blade-100
985 * find the ISA function on the southbridge and disable then enable
986 * the ATA channel tristate buffer
987 */
988 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) {
989 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) {
990 for (i = 0; i < nchildren; i++) {
991 if (pci_get_devid(children[i]) == ATA_ALI_1533) {
992 pci_write_config(children[i], 0x58,
993 pci_read_config(children[i], 0x58, 1) &
994 ~(0x04 << ch->unit), 1);
995 pci_write_config(children[i], 0x58,
996 pci_read_config(children[i], 0x58, 1) |
997 (0x04 << ch->unit), 1);
998 break;
999 }
1000 }
1001 free(children, M_TEMP);
1002 }
1003 }
1004 }
1005
1006 static void
1007 ata_ali_setmode(device_t dev, int mode)
1008 {
1009 device_t gparent = GRANDPARENT(dev);
1010 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1011 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1012 struct ata_device *atadev = device_get_softc(dev);
1013 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1014 int error;
1015
1016 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1017
1018 if (ctlr->chip->cfg2 & ALINEW) {
1019 if (mode > ATA_UDMA2 &&
1020 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) {
1021 ata_print_cable(dev, "controller");
1022 mode = ATA_UDMA2;
1023 }
1024 }
1025 else
1026 mode = ata_check_80pin(dev, mode);
1027
1028 if (ctlr->chip->cfg2 & ALIOLD) {
1029 /* doesn't support ATAPI DMA on write */
1030 ch->flags |= ATA_ATAPI_DMA_RO;
1031 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) {
1032 /* doesn't support ATAPI DMA on two ATAPI devices */
1033 device_printf(dev, "two atapi devices on this channel, no DMA\n");
1034 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1035 }
1036 }
1037
1038 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1039
1040 if (bootverbose)
1041 device_printf(dev, "%ssetting %s on %s chip\n",
1042 (error) ? "FAILURE " : "",
1043 ata_mode2str(mode), ctlr->chip->text);
1044 if (!error) {
1045 if (mode >= ATA_UDMA0) {
1046 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d};
1047 u_int32_t word54 = pci_read_config(gparent, 0x54, 4);
1048
1049 word54 &= ~(0x000f000f << (devno << 2));
1050 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
1051 pci_write_config(gparent, 0x54, word54, 4);
1052 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1053 0x00310001, 4);
1054 }
1055 else {
1056 u_int32_t piotimings[] =
1057 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
1058 0x00310001, 0x00440001, 0x00330001, 0x00310001};
1059
1060 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) &
1061 ~(0x0008000f << (devno << 2)), 4);
1062 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1063 piotimings[ata_mode2idx(mode)], 4);
1064 }
1065 atadev->mode = mode;
1066 }
1067 }
1068
1069
1070 /*
1071 * American Micro Devices (AMD) chipset support functions
1072 */
1073 int
1074 ata_amd_ident(device_t dev)
1075 {
1076 struct ata_pci_controller *ctlr = device_get_softc(dev);
1077 struct ata_chip_id *idx;
1078 static struct ata_chip_id ids[] =
1079 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "AMD 756" },
1080 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "AMD 766" },
1081 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "AMD 768" },
1082 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "AMD 8111" },
1083 { 0, 0, 0, 0, 0, 0}};
1084 char buffer[64];
1085
1086 if (!(idx = ata_match_chip(dev, ids)))
1087 return ENXIO;
1088
1089 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
1090 device_set_desc_copy(dev, buffer);
1091 ctlr->chip = idx;
1092 ctlr->chipinit = ata_amd_chipinit;
1093 return 0;
1094 }
1095
1096 static int
1097 ata_amd_chipinit(device_t dev)
1098 {
1099 struct ata_pci_controller *ctlr = device_get_softc(dev);
1100
1101 if (ata_setup_interrupt(dev))
1102 return ENXIO;
1103
1104 /* disable/set prefetch, postwrite */
1105 if (ctlr->chip->cfg2 & AMDBUG)
1106 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1);
1107 else
1108 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
1109
1110 ctlr->setmode = ata_via_family_setmode;
1111 return 0;
1112 }
1113
1114
1115 /*
1116 * ATI chipset support functions
1117 */
1118 int
1119 ata_ati_ident(device_t dev)
1120 {
1121 struct ata_pci_controller *ctlr = device_get_softc(dev);
1122 struct ata_chip_id *idx;
1123 static struct ata_chip_id ids[] =
1124 {{ ATA_ATI_IXP200, 0x00, 0, 0, ATA_UDMA5, "ATI IXP200" },
1125 { ATA_ATI_IXP300, 0x00, 0, 0, ATA_UDMA6, "ATI IXP300" },
1126 { ATA_ATI_IXP400, 0x00, 0, 0, ATA_UDMA6, "ATI IXP400" },
1127 { ATA_ATI_IXP300_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "ATI IXP300" },
1128 { ATA_ATI_IXP400_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "ATI IXP400" },
1129 { ATA_ATI_IXP400_S2, 0x00, SIIMEMIO, 0, ATA_SA150, "ATI IXP400" },
1130 { 0, 0, 0, 0, 0, 0}};
1131 char buffer[64];
1132
1133 if (!(idx = ata_match_chip(dev, ids)))
1134 return ENXIO;
1135
1136 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
1137 device_set_desc_copy(dev, buffer);
1138 ctlr->chip = idx;
1139
1140 /* the ATI SATA controller is actually a SiI 3112 controller*/
1141 if (ctlr->chip->cfg1 & SIIMEMIO)
1142 ctlr->chipinit = ata_sii_chipinit;
1143 else
1144 ctlr->chipinit = ata_ati_chipinit;
1145 return 0;
1146 }
1147
1148 static int
1149 ata_ati_chipinit(device_t dev)
1150 {
1151 struct ata_pci_controller *ctlr = device_get_softc(dev);
1152
1153 if (ata_setup_interrupt(dev))
1154 return ENXIO;
1155
1156 ctlr->setmode = ata_ati_setmode;
1157 return 0;
1158 }
1159
1160 static void
1161 ata_ati_setmode(device_t dev, int mode)
1162 {
1163 device_t gparent = GRANDPARENT(dev);
1164 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1165 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1166 struct ata_device *atadev = device_get_softc(dev);
1167 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1168 int offset = (devno ^ 0x01) << 3;
1169 int error;
1170 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1171 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1172 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
1173
1174 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1175
1176 mode = ata_check_80pin(dev, mode);
1177
1178 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1179
1180 if (bootverbose)
1181 device_printf(dev, "%ssetting %s on %s chip\n",
1182 (error) ? "FAILURE " : "",
1183 ata_mode2str(mode), ctlr->chip->text);
1184 if (!error) {
1185 if (mode >= ATA_UDMA0) {
1186 pci_write_config(gparent, 0x56,
1187 (pci_read_config(gparent, 0x56, 2) &
1188 ~(0xf << (devno << 2))) |
1189 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
1190 pci_write_config(gparent, 0x54,
1191 pci_read_config(gparent, 0x54, 1) |
1192 (0x01 << devno), 1);
1193 pci_write_config(gparent, 0x44,
1194 (pci_read_config(gparent, 0x44, 4) &
1195 ~(0xff << offset)) |
1196 (dmatimings[2] << offset), 4);
1197 }
1198 else if (mode >= ATA_WDMA0) {
1199 pci_write_config(gparent, 0x54,
1200 pci_read_config(gparent, 0x54, 1) &
1201 ~(0x01 << devno), 1);
1202 pci_write_config(gparent, 0x44,
1203 (pci_read_config(gparent, 0x44, 4) &
1204 ~(0xff << offset)) |
1205 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
1206 }
1207 else
1208 pci_write_config(gparent, 0x54,
1209 pci_read_config(gparent, 0x54, 1) &
1210 ~(0x01 << devno), 1);
1211
1212 pci_write_config(gparent, 0x4a,
1213 (pci_read_config(gparent, 0x4a, 2) &
1214 ~(0xf << (devno << 2))) |
1215 (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2);
1216 pci_write_config(gparent, 0x40,
1217 (pci_read_config(gparent, 0x40, 4) &
1218 ~(0xff << offset)) |
1219 (piotimings[ata_mode2idx(mode)] << offset), 4);
1220 atadev->mode = mode;
1221 }
1222 }
1223
1224 /*
1225 * Cyrix chipset support functions
1226 */
1227 int
1228 ata_cyrix_ident(device_t dev)
1229 {
1230 struct ata_pci_controller *ctlr = device_get_softc(dev);
1231
1232 if (pci_get_devid(dev) == ATA_CYRIX_5530) {
1233 device_set_desc(dev, "Cyrix 5530 ATA33 controller");
1234 ctlr->chipinit = ata_cyrix_chipinit;
1235 return 0;
1236 }
1237 return ENXIO;
1238 }
1239
1240 static int
1241 ata_cyrix_chipinit(device_t dev)
1242 {
1243 struct ata_pci_controller *ctlr = device_get_softc(dev);
1244
1245 if (ata_setup_interrupt(dev))
1246 return ENXIO;
1247
1248 if (ctlr->r_res1)
1249 ctlr->setmode = ata_cyrix_setmode;
1250 else
1251 ctlr->setmode = ata_generic_setmode;
1252 return 0;
1253 }
1254
1255 static void
1256 ata_cyrix_setmode(device_t dev, int mode)
1257 {
1258 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1259 struct ata_device *atadev = device_get_softc(dev);
1260 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1261 u_int32_t piotiming[] =
1262 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
1263 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
1264 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
1265 int error;
1266
1267 ch->dma->alignment = 16;
1268 ch->dma->max_iosize = 126 * DEV_BSIZE;
1269
1270 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
1271
1272 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1273
1274 if (bootverbose)
1275 device_printf(dev, "%ssetting %s on Cyrix chip\n",
1276 (error) ? "FAILURE " : "", ata_mode2str(mode));
1277 if (!error) {
1278 if (mode >= ATA_UDMA0) {
1279 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1280 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]);
1281 }
1282 else if (mode >= ATA_WDMA0) {
1283 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1284 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]);
1285 }
1286 else {
1287 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1288 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]);
1289 }
1290 atadev->mode = mode;
1291 }
1292 }
1293
1294
1295 /*
1296 * Cypress chipset support functions
1297 */
1298 int
1299 ata_cypress_ident(device_t dev)
1300 {
1301 struct ata_pci_controller *ctlr = device_get_softc(dev);
1302
1303 /*
1304 * the Cypress chip is a mess, it contains two ATA functions, but
1305 * both channels are visible on the first one.
1306 * simply ignore the second function for now, as the right
1307 * solution (ignoring the second channel on the first function)
1308 * doesn't work with the crappy ATA interrupt setup on the alpha.
1309 */
1310 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 &&
1311 pci_get_function(dev) == 1 &&
1312 pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
1313 device_set_desc(dev, "Cypress 82C693 ATA controller");
1314 ctlr->chipinit = ata_cypress_chipinit;
1315 return 0;
1316 }
1317 return ENXIO;
1318 }
1319
1320 static int
1321 ata_cypress_chipinit(device_t dev)
1322 {
1323 struct ata_pci_controller *ctlr = device_get_softc(dev);
1324
1325 if (ata_setup_interrupt(dev))
1326 return ENXIO;
1327
1328 ctlr->setmode = ata_cypress_setmode;
1329 return 0;
1330 }
1331
1332 static void
1333 ata_cypress_setmode(device_t dev, int mode)
1334 {
1335 device_t gparent = GRANDPARENT(dev);
1336 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1337 struct ata_device *atadev = device_get_softc(dev);
1338 int error;
1339
1340 mode = ata_limit_mode(dev, mode, ATA_WDMA2);
1341
1342 /* XXX SOS missing WDMA0+1 + PIO modes */
1343 if (mode == ATA_WDMA2) {
1344 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1345 if (bootverbose)
1346 device_printf(dev, "%ssetting WDMA2 on Cypress chip\n",
1347 error ? "FAILURE " : "");
1348 if (!error) {
1349 pci_write_config(gparent, ch->unit ? 0x4e : 0x4c, 0x2020, 2);
1350 atadev->mode = mode;
1351 return;
1352 }
1353 }
1354 /* we could set PIO mode timings, but we assume the BIOS did that */
1355 }
1356
1357
1358 /*
1359 * HighPoint chipset support functions
1360 */
1361 int
1362 ata_highpoint_ident(device_t dev)
1363 {
1364 struct ata_pci_controller *ctlr = device_get_softc(dev);
1365 struct ata_chip_id *idx;
1366 static struct ata_chip_id ids[] =
1367 {{ ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HighPoint HPT374" },
1368 { ATA_HPT372, 0x02, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT372N" },
1369 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT372" },
1370 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT371" },
1371 { ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT372" },
1372 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HighPoint HPT370" },
1373 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HighPoint HPT368" },
1374 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HighPoint HPT366" },
1375 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT302" },
1376 { 0, 0, 0, 0, 0, 0}};
1377 char buffer[64];
1378
1379 if (!(idx = ata_match_chip(dev, ids)))
1380 return ENXIO;
1381
1382 strcpy(buffer, idx->text);
1383 if (idx->cfg1 == HPT374) {
1384 if (pci_get_function(dev) == 0)
1385 strcat(buffer, " (channel 0+1)");
1386 else if (pci_get_function(dev) == 1)
1387 strcat(buffer, " (channel 2+3)");
1388 }
1389 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
1390 device_set_desc_copy(dev, buffer);
1391 ctlr->chip = idx;
1392 ctlr->chipinit = ata_highpoint_chipinit;
1393 return 0;
1394 }
1395
1396 static int
1397 ata_highpoint_chipinit(device_t dev)
1398 {
1399 struct ata_pci_controller *ctlr = device_get_softc(dev);
1400 int rid = ATA_IRQ_RID;
1401
1402 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1403 RF_SHAREABLE | RF_ACTIVE))) {
1404 device_printf(dev, "unable to map interrupt\n");
1405 return ENXIO;
1406 }
1407 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1408 ata_highpoint_intr, ctlr, &ctlr->handle))) {
1409 device_printf(dev, "unable to setup interrupt\n");
1410 return ENXIO;
1411 }
1412
1413 if (ctlr->chip->cfg2 == HPTOLD) {
1414 /* disable interrupt prediction */
1415 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
1416 }
1417 else {
1418 /* disable interrupt prediction */
1419 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
1420 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
1421
1422 /* enable interrupts */
1423 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
1424
1425 /* set clocks etc */
1426 if (ctlr->chip->cfg1 < HPT372)
1427 pci_write_config(dev, 0x5b, 0x22, 1);
1428 else
1429 pci_write_config(dev, 0x5b,
1430 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
1431 }
1432 ctlr->setmode = ata_highpoint_setmode;
1433 return 0;
1434 }
1435
1436 static void
1437 ata_highpoint_intr(void *data)
1438 {
1439 struct ata_pci_controller *ctlr = data;
1440 struct ata_channel *ch;
1441 int unit;
1442
1443 for (unit = 0; unit < ctlr->channels; unit++) {
1444 if (!(ch = ctlr->interrupt[unit].argument))
1445 continue;
1446 if (ch->dma) {
1447 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1448
1449 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
1450 ATA_BMSTAT_INTERRUPT)
1451 continue;
1452 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
1453 DELAY(1);
1454 }
1455 ctlr->interrupt[unit].function(ch);
1456 }
1457 }
1458
1459 static void
1460 ata_highpoint_setmode(device_t dev, int mode)
1461 {
1462 device_t gparent = GRANDPARENT(dev);
1463 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1464 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1465 struct ata_device *atadev = device_get_softc(dev);
1466 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1467 int error;
1468 u_int32_t timings33[][4] = {
1469 /* HPT366 HPT370 HPT372 HPT374 mode */
1470 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
1471 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
1472 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
1473 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
1474 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
1475 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
1476 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
1477 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
1478 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */
1479 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */
1480 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */
1481 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */
1482 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */
1483 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */
1484 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */
1485 };
1486
1487 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1488
1489 if (ctlr->chip->cfg1 == HPT366 && ata_atapi(dev))
1490 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1491
1492 mode = ata_highpoint_check_80pin(dev, mode);
1493
1494 /*
1495 * most if not all HPT chips cant really handle that the device is
1496 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to
1497 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance
1498 */
1499 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
1500 ata_limit_mode(dev, mode, ATA_UDMA5));
1501 if (bootverbose)
1502 device_printf(dev, "%ssetting %s on HighPoint chip\n",
1503 (error) ? "FAILURE " : "", ata_mode2str(mode));
1504 if (!error)
1505 pci_write_config(gparent, 0x40 + (devno << 2),
1506 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
1507 atadev->mode = mode;
1508 }
1509
1510 static int
1511 ata_highpoint_check_80pin(device_t dev, int mode)
1512 {
1513 device_t gparent = GRANDPARENT(dev);
1514 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1515 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1516 u_int8_t reg, val, res;
1517
1518 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(gparent) == 1) {
1519 reg = ch->unit ? 0x57 : 0x53;
1520 val = pci_read_config(gparent, reg, 1);
1521 pci_write_config(gparent, reg, val | 0x80, 1);
1522 }
1523 else {
1524 reg = 0x5b;
1525 val = pci_read_config(gparent, reg, 1);
1526 pci_write_config(gparent, reg, val & 0xfe, 1);
1527 }
1528 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2);
1529 pci_write_config(gparent, reg, val, 1);
1530
1531 if (mode > ATA_UDMA2 && res) {
1532 ata_print_cable(dev, "controller");
1533 mode = ATA_UDMA2;
1534 }
1535 return mode;
1536 }
1537
1538
1539 /*
1540 * Intel chipset support functions
1541 */
1542 int
1543 ata_intel_ident(device_t dev)
1544 {
1545 struct ata_pci_controller *ctlr = device_get_softc(dev);
1546 struct ata_chip_id *idx;
1547 static struct ata_chip_id ids[] =
1548 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "Intel PIIX" },
1549 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "Intel PIIX3" },
1550 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
1551 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
1552 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
1553 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "Intel ICH0" },
1554 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "Intel ICH" },
1555 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "Intel ICH" },
1556 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "Intel ICH2" },
1557 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH2" },
1558 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "Intel ICH3" },
1559 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH3" },
1560 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "Intel ICH4" },
1561 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH4" },
1562 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "Intel ICH5" },
1563 { ATA_I82801EB_S1, 0, 0, 0x00, ATA_SA150, "Intel ICH5" },
1564 { ATA_I82801EB_R1, 0, 0, 0x00, ATA_SA150, "Intel ICH5" },
1565 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "Intel 6300ESB" },
1566 { ATA_I6300ESB_S1, 0, 0, 0x00, ATA_SA150, "Intel 6300ESB" },
1567 { ATA_I6300ESB_R1, 0, 0, 0x00, ATA_SA150, "Intel 6300ESB" },
1568 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "Intel ICH6" },
1569 { ATA_I82801FB_S1, 0, 0, 0x00, ATA_SA150, "Intel ICH6" },
1570 { ATA_I82801FB_R1, 0, 0, 0x00, ATA_SA150, "Intel ICH6" },
1571 { ATA_I82801FB_M, 0, 0, 0x00, ATA_SA150, "Intel ICH6" },
1572 { ATA_I82801GB, 0, 0, 0x00, ATA_UDMA5, "Intel ICH7" },
1573 { ATA_I82801GB_S1, 0, 0, 0x00, ATA_SA150, "Intel ICH7" },
1574 { ATA_I82801GB_R1, 0, 0, 0x00, ATA_SA150, "Intel ICH7" },
1575 { ATA_I82801GB_M, 0, 0, 0x00, ATA_SA150, "Intel ICH7" },
1576 { ATA_I82801GB_AH, 0, 0, 0x00, ATA_SA150, "Intel ICH7" },
1577 { ATA_I31244, 0, 0, 0x00, ATA_SA150, "Intel 31244" },
1578 { 0, 0, 0, 0, 0, 0}};
1579 char buffer[64];
1580
1581 if (!(idx = ata_match_chip(dev, ids)))
1582 return ENXIO;
1583
1584 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
1585 device_set_desc_copy(dev, buffer);
1586 ctlr->chip = idx;
1587 ctlr->chipinit = ata_intel_chipinit;
1588 return 0;
1589 }
1590
1591 static int
1592 ata_intel_chipinit(device_t dev)
1593 {
1594 struct ata_pci_controller *ctlr = device_get_softc(dev);
1595 int rid = ATA_IRQ_RID;
1596
1597 if (!ata_legacy(dev)) {
1598 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1599 RF_SHAREABLE | RF_ACTIVE))) {
1600 device_printf(dev, "unable to map interrupt\n");
1601 return ENXIO;
1602 }
1603 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1604 ata_intel_intr, ctlr, &ctlr->handle))) {
1605 device_printf(dev, "unable to setup interrupt\n");
1606 return ENXIO;
1607 }
1608 }
1609
1610 /* good old PIIX needs special treatment (not implemented) */
1611 if (ctlr->chip->chipid == ATA_I82371FB) {
1612 ctlr->setmode = ata_intel_old_setmode;
1613 }
1614
1615 /* the intel 31244 needs special care if in DPA mode */
1616 else if (ctlr->chip->chipid == ATA_I31244) {
1617 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) {
1618 ctlr->r_type2 = SYS_RES_MEMORY;
1619 ctlr->r_rid2 = PCIR_BAR(0);
1620 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1621 &ctlr->r_rid2,
1622 RF_ACTIVE)))
1623 return ENXIO;
1624
1625 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
1626 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1627 ata_intel_31244_intr, ctlr, &ctlr->handle)) {
1628 device_printf(dev, "unable to setup interrupt\n");
1629 return ENXIO;
1630 }
1631 ctlr->channels = 4;
1632 ctlr->reset = ata_intel_31244_reset;
1633 ctlr->allocate = ata_intel_31244_allocate;
1634 }
1635 ctlr->setmode = ata_sata_setmode;
1636 }
1637
1638 /* non SATA intel chips goes here */
1639 else if (ctlr->chip->max_dma < ATA_SA150) {
1640 ctlr->setmode = ata_intel_new_setmode;
1641 }
1642
1643 /* SATA parts can be either compat or AHCI */
1644 else {
1645 /* if we have BAR(5) as a memory resource we should use AHCI mode */
1646 ctlr->r_type2 = SYS_RES_MEMORY;
1647 ctlr->r_rid2 = PCIR_BAR(5);
1648 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1649 &ctlr->r_rid2, RF_ACTIVE))) {
1650 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
1651 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1652 ata_ahci_intr, ctlr, &ctlr->handle)) {
1653 device_printf(dev, "unable to setup interrupt\n");
1654 return ENXIO;
1655 }
1656
1657 /* force all ports active "the legacy way" */
1658 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f,2);
1659
1660 /* enable AHCI mode */
1661 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
1662
1663 /* get the number of HW channels */
1664 ctlr->channels = (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) &
1665 ATA_AHCI_NPMASK) + 1;
1666
1667 /* enable AHCI interrupts */
1668 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
1669 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE);
1670
1671 ctlr->reset = ata_ahci_reset;
1672 ctlr->dmainit = ata_ahci_dmainit;
1673 ctlr->allocate = ata_ahci_allocate;
1674 }
1675 else {
1676 ctlr->reset = ata_intel_reset;
1677 }
1678 ctlr->setmode = ata_sata_setmode;
1679 pci_write_config(dev, PCIR_COMMAND,
1680 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
1681 }
1682 return 0;
1683 }
1684
1685 static int
1686 ata_intel_31244_allocate(device_t dev)
1687 {
1688 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1689 struct ata_channel *ch = device_get_softc(dev);
1690 int i;
1691 int ch_offset;
1692
1693 ch_offset = 0x200 + ch->unit * 0x200;
1694
1695 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
1696 ch->r_io[i].res = ctlr->r_res2;
1697 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
1698 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06;
1699 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
1700 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
1701 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
1702 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
1703 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
1704 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d;
1705 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04;
1706 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c;
1707 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28;
1708 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29;
1709 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100;
1710 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104;
1711 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108;
1712 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70;
1713 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72;
1714 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74;
1715
1716 ch->flags |= ATA_NO_SLAVE;
1717 ata_generic_hw(dev);
1718 ch->hw.command = ata_intel_31244_command;
1719
1720 /* enable PHY state change interrupt */
1721 ATA_OUTL(ctlr->r_res2, 0x4,
1722 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3)));
1723 return 0;
1724 }
1725
1726 static void
1727 ata_intel_31244_intr(void *data)
1728 {
1729 struct ata_pci_controller *ctlr = data;
1730 struct ata_channel *ch;
1731 int unit;
1732
1733 for (unit = 0; unit < ctlr->channels; unit++) {
1734 if (!(ch = ctlr->interrupt[unit].argument))
1735 continue;
1736
1737 /* check for PHY related interrupts on SATA capable HW */
1738 if (ctlr->chip->max_dma >= ATA_SA150) {
1739 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS);
1740 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR);
1741 struct ata_connect_task *tp;
1742
1743 if (error) {
1744 /* clear error bits/interrupt */
1745 ATA_IDX_OUTL(ch, ATA_SERROR, error);
1746
1747 /* if we have a connection event deal with it */
1748 if ((error & ATA_SE_PHY_CHANGED) &&
1749 (tp = (struct ata_connect_task *)
1750 malloc(sizeof(struct ata_connect_task),
1751 M_ATA, M_NOWAIT | M_ZERO))) {
1752
1753 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) {
1754 device_printf(ch->dev, "CONNECT requested\n");
1755 tp->action = ATA_C_ATTACH;
1756 }
1757 else {
1758 device_printf(ch->dev, "DISCONNECT requested\n");
1759 tp->action = ATA_C_DETACH;
1760 }
1761 tp->dev = ch->dev;
1762 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
1763 taskqueue_enqueue(taskqueue_thread, &tp->task);
1764 }
1765 }
1766 }
1767
1768 /* any drive action to take care of ? */
1769 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
1770 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1771
1772 if (!(bmstat & ATA_BMSTAT_INTERRUPT))
1773 continue;
1774 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
1775 DELAY(1);
1776 }
1777 ctlr->interrupt[unit].function(ch);
1778 }
1779 }
1780
1781 static void
1782 ata_intel_31244_reset(device_t dev)
1783 {
1784 struct ata_channel *ch = device_get_softc(dev);
1785
1786 ata_sata_phy_enable(ch);
1787 }
1788
1789 static int
1790 ata_intel_31244_command(struct ata_request *request)
1791 {
1792 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
1793 struct ata_device *atadev = device_get_softc(request->dev);
1794 u_int64_t lba;
1795
1796 if (!(atadev->flags & ATA_D_48BIT_ACTIVE))
1797 return (ata_generic_command(request));
1798
1799 lba = request->u.ata.lba;
1800 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit);
1801 /* enable interrupt */
1802 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
1803 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
1804 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
1805 ATA_IDX_OUTW(ch, ATA_SECTOR, ((lba >> 16) & 0xff00) | (lba & 0x00ff));
1806 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((lba >> 24) & 0xff00) |
1807 ((lba >> 8) & 0x00ff));
1808 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((lba >> 32) & 0xff00) |
1809 ((lba >> 16) & 0x00ff));
1810
1811 /* issue command to controller */
1812 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command);
1813
1814 return 0;
1815 }
1816
1817 static void
1818 ata_intel_intr(void *data)
1819 {
1820 struct ata_pci_controller *ctlr = data;
1821 struct ata_channel *ch;
1822 int unit;
1823
1824 for (unit = 0; unit < ctlr->channels; unit++) {
1825 if (!(ch = ctlr->interrupt[unit].argument))
1826 continue;
1827 if (ch->dma) {
1828 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1829
1830 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
1831 ATA_BMSTAT_INTERRUPT)
1832 continue;
1833 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
1834 DELAY(1);
1835 }
1836 ctlr->interrupt[unit].function(ch);
1837 }
1838 }
1839
1840 static void
1841 ata_intel_reset(device_t dev)
1842 {
1843 device_t parent = device_get_parent(dev);
1844 struct ata_pci_controller *ctlr = device_get_softc(parent);
1845 struct ata_channel *ch = device_get_softc(dev);
1846 int mask, timeout;
1847
1848 /* ICH6 has 4 SATA ports as master/slave on 2 channels so deal with pairs */
1849 if (ctlr->chip->chipid == ATA_I82801FB_S1 ||
1850 ctlr->chip->chipid == ATA_I82801FB_R1 ||
1851 ctlr->chip->chipid == ATA_I82801FB_M) {
1852 mask = (0x0005 << ch->unit);
1853 }
1854 else {
1855 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */
1856 if (pci_read_config(parent, 0x90, 1) & 0x04)
1857 mask = 0x0003;
1858 else {
1859 mask = (0x0001 << ch->unit);
1860 /* XXX SOS should be in intel_allocate when we grow it */
1861 ch->flags |= ATA_NO_SLAVE;
1862 }
1863 }
1864 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2);
1865 DELAY(10);
1866 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2);
1867
1868 /* wait up to 1 sec for "connect well" */
1869 for (timeout = 0; timeout < 100 ; timeout++) {
1870 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) &&
1871 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff))
1872 break;
1873 ata_udelay(10000);
1874 }
1875 ata_generic_reset(dev);
1876 }
1877
1878 static void
1879 ata_intel_old_setmode(device_t dev, int mode)
1880 {
1881 /* NOT YET */
1882 }
1883
1884 static void
1885 ata_intel_new_setmode(device_t dev, int mode)
1886 {
1887 device_t gparent = GRANDPARENT(dev);
1888 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1889 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1890 struct ata_device *atadev = device_get_softc(dev);
1891 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1892 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4);
1893 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1);
1894 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1);
1895 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2);
1896 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2);
1897 u_int32_t mask40 = 0, new40 = 0;
1898 u_int8_t mask44 = 0, new44 = 0;
1899 int error;
1900 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
1901 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
1902
1903 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1904
1905 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
1906 ata_print_cable(dev, "controller");
1907 mode = ATA_UDMA2;
1908 }
1909
1910 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1911
1912 if (bootverbose)
1913 device_printf(dev, "%ssetting %s on %s chip\n",
1914 (error) ? "FAILURE " : "",
1915 ata_mode2str(mode), ctlr->chip->text);
1916 if (error)
1917 return;
1918
1919 if (mode >= ATA_UDMA0) {
1920 pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2);
1921 pci_write_config(gparent, 0x4a,
1922 (reg4a & ~(0x3 << (devno << 2))) |
1923 ((0x01 + !(mode & 0x01)) << (devno << 2)), 2);
1924 }
1925 else {
1926 pci_write_config(gparent, 0x48, reg48 & ~(0x0001 << devno), 2);
1927 pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))), 2);
1928 }
1929 reg54 |= 0x0400;
1930 if (mode >= ATA_UDMA2)
1931 pci_write_config(gparent, 0x54, reg54 | (0x1 << devno), 2);
1932 else
1933 pci_write_config(gparent, 0x54, reg54 & ~(0x1 << devno), 2);
1934
1935 if (mode >= ATA_UDMA5)
1936 pci_write_config(gparent, 0x54, reg54 | (0x1000 << devno), 2);
1937 else
1938 pci_write_config(gparent, 0x54, reg54 & ~(0x1000 << devno), 2);
1939
1940 reg40 &= ~0x00ff00ff;
1941 reg40 |= 0x40774077;
1942
1943 if (atadev->unit == ATA_MASTER) {
1944 mask40 = 0x3300;
1945 new40 = timings[ata_mode2idx(mode)] << 8;
1946 }
1947 else {
1948 mask44 = 0x0f;
1949 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
1950 (timings[ata_mode2idx(mode)] & 0x03);
1951 }
1952 if (ch->unit) {
1953 mask40 <<= 16;
1954 new40 <<= 16;
1955 mask44 <<= 4;
1956 new44 <<= 4;
1957 }
1958 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4);
1959 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1);
1960
1961 atadev->mode = mode;
1962 }
1963
1964
1965 /*
1966 * Integrated Technology Express Inc. (ITE) chipset support functions
1967 */
1968 int
1969 ata_ite_ident(device_t dev)
1970 {
1971 struct ata_pci_controller *ctlr = device_get_softc(dev);
1972 struct ata_chip_id *idx;
1973 static struct ata_chip_id ids[] =
1974 {{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "ITE IT8212F" },
1975 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "ITE IT8211F" },
1976 { 0, 0, 0, 0, 0, 0}};
1977 char buffer[64];
1978
1979 if (!(idx = ata_match_chip(dev, ids)))
1980 return ENXIO;
1981
1982 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
1983 device_set_desc_copy(dev, buffer);
1984 ctlr->chip = idx;
1985 ctlr->chipinit = ata_ite_chipinit;
1986 return 0;
1987 }
1988
1989 static int
1990 ata_ite_chipinit(device_t dev)
1991 {
1992 struct ata_pci_controller *ctlr = device_get_softc(dev);
1993
1994 if (ata_setup_interrupt(dev))
1995 return ENXIO;
1996
1997 ctlr->setmode = ata_ite_setmode;
1998
1999 /* set PCI mode and 66Mhz reference clock */
2000 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1);
2001
2002 /* set default active & recover timings */
2003 pci_write_config(dev, 0x54, 0x31, 1);
2004 pci_write_config(dev, 0x56, 0x31, 1);
2005 return 0;
2006 }
2007
2008 static void
2009 ata_ite_setmode(device_t dev, int mode)
2010 {
2011 device_t gparent = GRANDPARENT(dev);
2012 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2013 struct ata_device *atadev = device_get_softc(dev);
2014 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2015 int error;
2016
2017 /* correct the mode for what the HW supports */
2018 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2019
2020 /* check the CBLID bits for 80 conductor cable detection */
2021 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) &
2022 (ch->unit ? (1<<3) : (1<<2)))) {
2023 ata_print_cable(dev, "controller");
2024 mode = ATA_UDMA2;
2025 }
2026
2027 /* set the wanted mode on the device */
2028 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2029
2030 if (bootverbose)
2031 device_printf(dev, "%s setting %s on ITE8212F chip\n",
2032 (error) ? "failed" : "success", ata_mode2str(mode));
2033
2034 /* if the device accepted the mode change, setup the HW accordingly */
2035 if (!error) {
2036 if (mode >= ATA_UDMA0) {
2037 u_int8_t udmatiming[] =
2038 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
2039
2040 /* enable UDMA mode */
2041 pci_write_config(gparent, 0x50,
2042 pci_read_config(gparent, 0x50, 1) &
2043 ~(1 << (devno + 3)), 1);
2044
2045 /* set UDMA timing */
2046 pci_write_config(gparent,
2047 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit),
2048 udmatiming[mode & ATA_MODE_MASK], 1);
2049 }
2050 else {
2051 u_int8_t chtiming[] =
2052 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
2053
2054 /* disable UDMA mode */
2055 pci_write_config(gparent, 0x50,
2056 pci_read_config(gparent, 0x50, 1) |
2057 (1 << (devno + 3)), 1);
2058
2059 /* set active and recover timing (shared between master & slave) */
2060 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) <
2061 chtiming[ata_mode2idx(mode)])
2062 pci_write_config(gparent, 0x54 + (ch->unit << 2),
2063 chtiming[ata_mode2idx(mode)], 1);
2064 }
2065 atadev->mode = mode;
2066 }
2067 }
2068
2069
2070 /*
2071 * National chipset support functions
2072 */
2073 int
2074 ata_national_ident(device_t dev)
2075 {
2076 struct ata_pci_controller *ctlr = device_get_softc(dev);
2077
2078 /* this chip is a clone of the Cyrix chip, bugs and all */
2079 if (pci_get_devid(dev) == ATA_SC1100) {
2080 device_set_desc(dev, "National Geode SC1100 ATA33 controller");
2081 ctlr->chipinit = ata_national_chipinit;
2082 return 0;
2083 }
2084 return ENXIO;
2085 }
2086
2087 static device_t nat_host = NULL;
2088
2089 static int
2090 ata_national_chipinit(device_t dev)
2091 {
2092 struct ata_pci_controller *ctlr = device_get_softc(dev);
2093 device_t *children;
2094 int nchildren, i;
2095
2096 if (ata_setup_interrupt(dev))
2097 return ENXIO;
2098
2099 /* locate the ISA part in the southbridge and enable UDMA33 */
2100 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
2101 for (i = 0; i < nchildren; i++) {
2102 if (pci_get_devid(children[i]) == 0x0510100b) {
2103 nat_host = children[i];
2104 break;
2105 }
2106 }
2107 free(children, M_TEMP);
2108 }
2109 ctlr->setmode = ata_national_setmode;
2110 return 0;
2111 }
2112
2113 static void
2114 ata_national_setmode(device_t dev, int mode)
2115 {
2116 device_t gparent = GRANDPARENT(dev);
2117 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2118 struct ata_device *atadev = device_get_softc(dev);
2119 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2120 u_int32_t piotiming[] =
2121 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
2122 0x00803020, 0x20102010, 0x00100010,
2123 0x00100010, 0x00100010, 0x00100010 };
2124 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
2125 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
2126 int error;
2127
2128 ch->dma->alignment = 16;
2129 ch->dma->max_iosize = 126 * DEV_BSIZE;
2130
2131 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
2132
2133 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2134
2135 if (bootverbose)
2136 device_printf(dev, "%s setting %s on National chip\n",
2137 (error) ? "failed" : "success", ata_mode2str(mode));
2138 if (!error) {
2139 if (mode >= ATA_UDMA0) {
2140 pci_write_config(gparent, 0x44 + (devno << 3),
2141 udmatiming[mode & ATA_MODE_MASK], 4);
2142 }
2143 else if (mode >= ATA_WDMA0) {
2144 pci_write_config(gparent, 0x44 + (devno << 3),
2145 dmatiming[mode & ATA_MODE_MASK], 4);
2146 }
2147 else {
2148 pci_write_config(gparent, 0x44 + (devno << 3),
2149 pci_read_config(gparent, 0x44 + (devno << 3), 4) |
2150 0x80000000, 4);
2151 }
2152 pci_write_config(gparent, 0x40 + (devno << 3),
2153 piotiming[ata_mode2idx(mode)], 4);
2154 atadev->mode = mode;
2155 }
2156 }
2157
2158
2159 /*
2160 * nVidia chipset support functions
2161 */
2162 int
2163 ata_nvidia_ident(device_t dev)
2164 {
2165 struct ata_pci_controller *ctlr = device_get_softc(dev);
2166 struct ata_chip_id *idx;
2167 static struct ata_chip_id ids[] =
2168 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nVidia nForce" },
2169 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce2" },
2170 { ATA_NFORCE2_MCP, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce2 MCP" },
2171 { ATA_NFORCE2_MCP_S1, 0, 0, 0, ATA_SA150, "nVidia nForce2 MCP" },
2172 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce3" },
2173 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce3 Pro" },
2174 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nVidia nForce3 Pro" },
2175 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nVidia nForce3 Pro" },
2176 { ATA_NFORCE3_MCP, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce3 MCP" },
2177 { ATA_NFORCE3_MCP_S1, 0, 0, NV4OFF, ATA_SA150, "nVidia nForce3 MCP" },
2178 { ATA_NFORCE3_MCP_S2, 0, 0, NV4OFF, ATA_SA150, "nVidia nForce3 MCP" },
2179 { ATA_NFORCE4, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce4" },
2180 { ATA_NFORCE4_S1, 0, 0, NV4OFF, ATA_SA150, "nVidia nForce4" },
2181 { ATA_NFORCE4_S2, 0, 0, NV4OFF, ATA_SA150, "nVidia nForce4" },
2182 { 0, 0, 0, 0, 0, 0}};
2183 char buffer[64];
2184
2185 if (!(idx = ata_match_chip(dev, ids)))
2186 return ENXIO;
2187
2188 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
2189 device_set_desc_copy(dev, buffer);
2190 ctlr->chip = idx;
2191 ctlr->chipinit = ata_nvidia_chipinit;
2192 return 0;
2193 }
2194
2195 static int
2196 ata_nvidia_chipinit(device_t dev)
2197 {
2198 struct ata_pci_controller *ctlr = device_get_softc(dev);
2199
2200 if (ata_setup_interrupt(dev))
2201 return ENXIO;
2202
2203 if (ctlr->chip->max_dma >= ATA_SA150) {
2204 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1)
2205 ctlr->r_type2 = SYS_RES_IOPORT;
2206 else
2207 ctlr->r_type2 = SYS_RES_MEMORY;
2208 ctlr->r_rid2 = PCIR_BAR(5);
2209 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
2210 &ctlr->r_rid2, RF_ACTIVE))) {
2211 int offset = ctlr->chip->cfg2 & NV4OFF ? 0x0440 : 0x0010;
2212
2213 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
2214 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
2215 ata_nvidia_intr, ctlr, &ctlr->handle)) {
2216 device_printf(dev, "unable to setup interrupt\n");
2217 return ENXIO;
2218 }
2219
2220 /* enable control access */
2221 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1);
2222
2223 /* clear interrupt status */
2224 ATA_OUTB(ctlr->r_res2, offset, 0xff);
2225
2226 /* enable device and PHY state change interrupts */
2227 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd);
2228
2229 /* enable PCI interrupt */
2230 pci_write_config(dev, PCIR_COMMAND,
2231 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
2232
2233 ctlr->allocate = ata_nvidia_allocate;
2234 ctlr->reset = ata_nvidia_reset;
2235 }
2236 ctlr->setmode = ata_sata_setmode;
2237 }
2238 else {
2239 /* disable prefetch, postwrite */
2240 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
2241 ctlr->setmode = ata_via_family_setmode;
2242 }
2243 return 0;
2244 }
2245
2246 static int
2247 ata_nvidia_allocate(device_t dev)
2248 {
2249 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2250 struct ata_channel *ch = device_get_softc(dev);
2251
2252 /* setup the usual register normal pci style */
2253 if (ata_pci_allocate(dev))
2254 return ENXIO;
2255
2256 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
2257 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6);
2258 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
2259 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6);
2260 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
2261 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6);
2262 ch->flags |= ATA_NO_SLAVE;
2263
2264 return 0;
2265 }
2266
2267 static void
2268 ata_nvidia_intr(void *data)
2269 {
2270 struct ata_pci_controller *ctlr = data;
2271 struct ata_channel *ch;
2272 int offset = ctlr->chip->cfg2 & NV4OFF ? 0x0440 : 0x0010;
2273 u_int8_t status;
2274 int unit;
2275
2276 /* get interrupt status */
2277 status = ATA_INB(ctlr->r_res2, offset);
2278
2279 /* clear interrupt status */
2280 ATA_OUTB(ctlr->r_res2, offset, 0xff);
2281
2282 for (unit = 0; unit < ctlr->channels; unit++) {
2283 if ((ch = ctlr->interrupt[unit].argument)) {
2284 struct ata_connect_task *tp;
2285 int maskshift = ch->unit << 2;
2286
2287 /* clear error status */
2288 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2289
2290 /* check for and handle connect events */
2291 if (((status & (0x0c << maskshift)) == (0x04 << maskshift)) &&
2292 (tp = (struct ata_connect_task *)
2293 malloc(sizeof(struct ata_connect_task),
2294 M_ATA, M_NOWAIT | M_ZERO))) {
2295
2296 device_printf(ch->dev, "CONNECT requested\n");
2297 tp->action = ATA_C_ATTACH;
2298 tp->dev = ch->dev;
2299 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
2300 taskqueue_enqueue(taskqueue_thread, &tp->task);
2301 }
2302
2303 /* check for and handle disconnect events */
2304 if ((status & (0x08 << maskshift)) &&
2305 (tp = (struct ata_connect_task *)
2306 malloc(sizeof(struct ata_connect_task),
2307 M_ATA, M_NOWAIT | M_ZERO))) {
2308
2309 device_printf(ch->dev, "DISCONNECT requested\n");
2310 tp->action = ATA_C_DETACH;
2311 tp->dev = ch->dev;
2312 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
2313 taskqueue_enqueue(taskqueue_thread, &tp->task);
2314 }
2315
2316 /* any drive action to take care of ? */
2317 if (status & (0x01 << maskshift)) {
2318 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
2319 int bmstat =
2320 ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
2321
2322 if (!(bmstat & ATA_BMSTAT_INTERRUPT))
2323 continue;
2324 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat&~ATA_BMSTAT_ERROR);
2325 DELAY(1);
2326 }
2327 ctlr->interrupt[unit].function(ch);
2328 }
2329 }
2330 }
2331 }
2332
2333 static void
2334 ata_nvidia_reset(device_t dev)
2335 {
2336 struct ata_channel *ch = device_get_softc(dev);
2337
2338 ata_sata_phy_enable(ch);
2339 }
2340
2341
2342 /*
2343 * Promise chipset support functions
2344 */
2345 #define ATA_PDC_APKT_OFFSET 0x00000010
2346 #define ATA_PDC_HPKT_OFFSET 0x00000040
2347 #define ATA_PDC_ASG_OFFSET 0x00000080
2348 #define ATA_PDC_LSG_OFFSET 0x000000c0
2349 #define ATA_PDC_HSG_OFFSET 0x00000100
2350 #define ATA_PDC_CHN_OFFSET 0x00000400
2351 #define ATA_PDC_BUF_BASE 0x00400000
2352 #define ATA_PDC_BUF_OFFSET 0x00100000
2353 #define ATA_PDC_MAX_HPKT 8
2354 #define ATA_PDC_WRITE_REG 0x00
2355 #define ATA_PDC_WRITE_CTL 0x0e
2356 #define ATA_PDC_WRITE_END 0x08
2357 #define ATA_PDC_WAIT_NBUSY 0x10
2358 #define ATA_PDC_WAIT_READY 0x18
2359 #define ATA_PDC_1B 0x20
2360 #define ATA_PDC_2B 0x40
2361
2362 struct host_packet {
2363 u_int32_t addr;
2364 TAILQ_ENTRY(host_packet) chain;
2365 };
2366
2367 struct ata_promise_sx4 {
2368 struct mtx mtx;
2369 TAILQ_HEAD(, host_packet) queue;
2370 int busy;
2371 };
2372
2373 int
2374 ata_promise_ident(device_t dev)
2375 {
2376 struct ata_pci_controller *ctlr = device_get_softc(dev);
2377 struct ata_chip_id *idx;
2378 static struct ata_chip_id ids[] =
2379 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "Promise PDC20246" },
2380 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "Promise PDC20262" },
2381 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "Promise PDC20263" },
2382 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "Promise PDC20265" },
2383 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "Promise PDC20267" },
2384 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "Promise PDC20268" },
2385 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20269" },
2386 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "Promise PDC20270" },
2387 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20271" },
2388 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20275" },
2389 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "Promise PDC20276" },
2390 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20277" },
2391 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20318" },
2392 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20319" },
2393 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "Promise PDC20371" },
2394 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "Promise PDC20375" },
2395 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "Promise PDC20376" },
2396 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "Promise PDC20377" },
2397 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "Promise PDC20378" },
2398 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "Promise PDC20379" },
2399 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "Promise PDC20571" },
2400 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "Promise PDC20575" },
2401 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "Promise PDC20579" },
2402 { ATA_PDC20580, 0, PRMIO, PRCMBO2, ATA_SA150, "Promise PDC20580" },
2403 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "Promise PDC20617" },
2404 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "Promise PDC20618" },
2405 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "Promise PDC20619" },
2406 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "Promise PDC20620" },
2407 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "Promise PDC20621" },
2408 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "Promise PDC20622" },
2409 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "Promise PDC40518" },
2410 { ATA_PDC40519, 0, PRMIO, PRSATA2, ATA_SA150, "Promise PDC40519" },
2411 { ATA_PDC40718, 0, PRMIO, PRSATA2, ATA_SA300, "Promise PDC40718" },
2412 { ATA_PDC40719, 0, PRMIO, PRSATA2, ATA_SA300, "Promise PDC40719" },
2413 { 0, 0, 0, 0, 0, 0}};
2414 char buffer[64];
2415 uintptr_t devid = 0;
2416
2417 if (!(idx = ata_match_chip(dev, ids)))
2418 return ENXIO;
2419
2420 /* if we are on a SuperTrak SX6000 dont attach */
2421 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
2422 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
2423 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
2424 devid == ATA_I960RM)
2425 return ENXIO;
2426
2427 strcpy(buffer, idx->text);
2428
2429 /* if we are on a FastTrak TX4, adjust the interrupt resource */
2430 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
2431 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
2432 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
2433 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) {
2434 static long start = 0, end = 0;
2435
2436 if (pci_get_slot(dev) == 1) {
2437 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
2438 strcat(buffer, " (channel 0+1)");
2439 }
2440 else if (pci_get_slot(dev) == 2 && start && end) {
2441 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
2442 start = end = 0;
2443 strcat(buffer, " (channel 2+3)");
2444 }
2445 else {
2446 start = end = 0;
2447 }
2448 }
2449 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
2450 device_set_desc_copy(dev, buffer);
2451 ctlr->chip = idx;
2452 ctlr->chipinit = ata_promise_chipinit;
2453 return 0;
2454 }
2455
2456 static int
2457 ata_promise_chipinit(device_t dev)
2458 {
2459 struct ata_pci_controller *ctlr = device_get_softc(dev);
2460 int rid = ATA_IRQ_RID;
2461
2462 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2463 RF_SHAREABLE | RF_ACTIVE))) {
2464 device_printf(dev, "unable to map interrupt\n");
2465 return ENXIO;
2466 }
2467
2468 if (ctlr->chip->max_dma >= ATA_SA150)
2469 ctlr->setmode = ata_sata_setmode;
2470 else
2471 ctlr->setmode = ata_promise_setmode;
2472
2473 switch (ctlr->chip->cfg1) {
2474 case PRNEW:
2475 /* setup clocks */
2476 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a);
2477
2478 ctlr->dmainit = ata_promise_new_dmainit;
2479 /* FALLTHROUGH */
2480
2481 case PROLD:
2482 /* enable burst mode */
2483 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01);
2484
2485 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
2486 ata_promise_old_intr, ctlr, &ctlr->handle))) {
2487 device_printf(dev, "unable to setup interrupt\n");
2488 return ENXIO;
2489 }
2490 break;
2491
2492 case PRTX:
2493 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
2494 ata_promise_tx2_intr, ctlr, &ctlr->handle))) {
2495 device_printf(dev, "unable to setup interrupt\n");
2496 return ENXIO;
2497 }
2498 break;
2499
2500 case PRMIO:
2501 // if (ctlr->r_res1)
2502 // bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
2503 ctlr->r_type1 = SYS_RES_MEMORY;
2504 ctlr->r_rid1 = PCIR_BAR(4);
2505 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
2506 &ctlr->r_rid1, RF_ACTIVE)))
2507 return ENXIO;
2508
2509 ctlr->r_type2 = SYS_RES_MEMORY;
2510 ctlr->r_rid2 = PCIR_BAR(3);
2511 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
2512 &ctlr->r_rid2, RF_ACTIVE))){
2513 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
2514 return ENXIO;
2515 }
2516 ctlr->reset = ata_promise_mio_reset;
2517 ctlr->dmainit = ata_promise_mio_dmainit;
2518 ctlr->allocate = ata_promise_mio_allocate;
2519
2520 if (ctlr->chip->cfg2 == PRSX4X) {
2521 struct ata_promise_sx4 *hpkt;
2522 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080);
2523
2524 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
2525 ata_promise_sx4_intr, ctlr, &ctlr->handle))) {
2526 device_printf(dev, "unable to setup interrupt\n");
2527 /* XXX SOS release resources */
2528 return ENXIO;
2529 }
2530
2531 /* print info about cache memory */
2532 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n",
2533 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4,
2534 ((dimm >> 24) & 0xff),
2535 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ?
2536 " ECC enabled" : "" );
2537
2538 /* adjust cache memory parameters */
2539 ATA_OUTL(ctlr->r_res2, 0x000c000c,
2540 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000));
2541
2542 /* setup host packet controls */
2543 hpkt = malloc(sizeof(struct ata_promise_sx4),
2544 M_TEMP, M_NOWAIT | M_ZERO);
2545 mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF);
2546 TAILQ_INIT(&hpkt->queue);
2547 hpkt->busy = 0; //hpkt->head = hpkt->tail = 0;
2548 device_set_ivars(dev, hpkt);
2549 ctlr->channels = 4;
2550 return 0;
2551 }
2552
2553 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
2554 ata_promise_mio_intr, ctlr, &ctlr->handle))) {
2555 device_printf(dev, "unable to setup interrupt\n");
2556 /* XXX SOS release resources */
2557 return ENXIO;
2558 }
2559
2560 switch (ctlr->chip->cfg2) {
2561 case PRPATA:
2562 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) +
2563 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2;
2564 break;
2565
2566 case PRCMBO:
2567 ATA_OUTL(ctlr->r_res2, 0x06c, 0x000000ff);
2568 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 3;
2569 break;
2570
2571 case PRSATA:
2572 ATA_OUTL(ctlr->r_res2, 0x06c, 0x000000ff);
2573 ctlr->channels = 4;
2574 break;
2575
2576 case PRCMBO2:
2577 ATA_OUTL(ctlr->r_res2, 0x060, 0x000000ff);
2578 ctlr->channels = 3;
2579 break;
2580
2581 case PRSATA2:
2582 ATA_OUTL(ctlr->r_res2, 0x060, 0x000000ff);
2583 ctlr->channels = 4;
2584 break;
2585
2586 default:
2587 /* XXX SOS release resources */
2588 return ENXIO;
2589 }
2590 default:
2591 /* XXX SOS release resources */
2592 return ENXIO;
2593 }
2594 return 0;
2595 }
2596
2597 static int
2598 ata_promise_mio_allocate(device_t dev)
2599 {
2600 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2601 struct ata_channel *ch = device_get_softc(dev);
2602 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0;
2603 int i;
2604
2605 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
2606 ch->r_io[i].res = ctlr->r_res2;
2607 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7);
2608 }
2609 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
2610 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7);
2611 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
2612 ata_default_registers(dev);
2613 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) ||
2614 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2)) {
2615 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
2616 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8);
2617 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
2618 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8);
2619 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
2620 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8);
2621 ch->flags |= ATA_NO_SLAVE;
2622 }
2623 ch->flags |= ATA_USE_16BIT;
2624
2625 ata_generic_hw(dev);
2626 if (offset)
2627 ch->hw.command = ata_promise_sx4_command;
2628 else
2629 ch->hw.command = ata_promise_mio_command;
2630 return 0;
2631 }
2632
2633 static void
2634 ata_promise_mio_intr(void *data)
2635 {
2636 struct ata_pci_controller *ctlr = data;
2637 struct ata_channel *ch;
2638 u_int32_t vector = 0, status = 0;
2639 int unit;
2640
2641 switch (ctlr->chip->cfg2) {
2642 case PRSATA:
2643 case PRCMBO:
2644 /* read and acknowledge interrupt(s) */
2645 vector = ATA_INL(ctlr->r_res2, 0x040);
2646
2647 /* read and clear interface status */
2648 status = ATA_INL(ctlr->r_res2, 0x06c);
2649 ATA_OUTL(ctlr->r_res2, 0x06c, status & 0x000000ff);
2650 break;
2651
2652 case PRSATA2:
2653 case PRCMBO2:
2654 /* read and acknowledge interrupt(s) */
2655 vector = ATA_INL(ctlr->r_res2, 0x040);
2656 ATA_OUTL(ctlr->r_res2, 0x040, vector & 0x0000ffff);
2657
2658 /* read and clear interface status */
2659 status = ATA_INL(ctlr->r_res2, 0x060);
2660 ATA_OUTL(ctlr->r_res2, 0x060, status & 0x000000ff);
2661 break;
2662 }
2663
2664 for (unit = 0; unit < ctlr->channels; unit++) {
2665
2666 if ((ch = ctlr->interrupt[unit].argument)) {
2667 struct ata_connect_task *tp;
2668
2669 /* check for and handle disconnect events */
2670 if ((status & (0x00000001 << unit)) &&
2671 (tp = (struct ata_connect_task *)
2672 malloc(sizeof(struct ata_connect_task),
2673 M_ATA, M_NOWAIT | M_ZERO))) {
2674
2675 if (bootverbose)
2676 device_printf(ch->dev, "DISCONNECT requested\n");
2677 tp->action = ATA_C_DETACH;
2678 tp->dev = ch->dev;
2679 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
2680 taskqueue_enqueue(taskqueue_thread, &tp->task);
2681 }
2682
2683 /* check for and handle connect events */
2684 if ((status & (0x00000010 << unit)) &&
2685 (tp = (struct ata_connect_task *)
2686 malloc(sizeof(struct ata_connect_task),
2687 M_ATA, M_NOWAIT | M_ZERO))) {
2688
2689 if (bootverbose)
2690 device_printf(ch->dev, "CONNECT requested\n");
2691 tp->action = ATA_C_ATTACH;
2692 tp->dev = ch->dev;
2693 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
2694 taskqueue_enqueue(taskqueue_thread, &tp->task);
2695 }
2696
2697 /* active interrupt(s) need to call the interrupt handler */
2698 if (vector & (1 << (unit + 1)))
2699 if ((ch = ctlr->interrupt[unit].argument))
2700 ctlr->interrupt[unit].function(ch);
2701 }
2702 }
2703 }
2704
2705 static void
2706 ata_promise_sx4_intr(void *data)
2707 {
2708 struct ata_pci_controller *ctlr = data;
2709 struct ata_channel *ch;
2710 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480);
2711 int unit;
2712
2713 for (unit = 0; unit < ctlr->channels; unit++) {
2714 if (vector & (1 << (unit + 1)))
2715 if ((ch = ctlr->interrupt[unit].argument))
2716 ctlr->interrupt[unit].function(ch);
2717 if (vector & (1 << (unit + 5)))
2718 if ((ch = ctlr->interrupt[unit].argument))
2719 ata_promise_queue_hpkt(ctlr,
2720 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
2721 ATA_PDC_HPKT_OFFSET));
2722 if (vector & (1 << (unit + 9))) {
2723 ata_promise_next_hpkt(ctlr);
2724 if ((ch = ctlr->interrupt[unit].argument))
2725 ctlr->interrupt[unit].function(ch);
2726 }
2727 if (vector & (1 << (unit + 13))) {
2728 ata_promise_next_hpkt(ctlr);
2729 if ((ch = ctlr->interrupt[unit].argument))
2730 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
2731 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
2732 ATA_PDC_APKT_OFFSET));
2733 }
2734 }
2735 }
2736
2737 static void
2738 ata_promise_mio_dmainit(device_t dev)
2739 {
2740 struct ata_channel *ch = device_get_softc(dev);
2741
2742 ata_dmainit(dev);
2743 if (ch->dma) {
2744 /* note start and stop are not used here */
2745 }
2746 }
2747
2748 static void
2749 ata_promise_mio_reset(device_t dev)
2750 {
2751 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2752 struct ata_channel *ch = device_get_softc(dev);
2753 struct ata_promise_sx4 *hpktp;
2754
2755 switch (ctlr->chip->cfg2) {
2756 case PRSX4X:
2757
2758 /* softreset channel ATA module */
2759 hpktp = device_get_ivars(ctlr->dev);
2760 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1);
2761 ata_udelay(1000);
2762 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7),
2763 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) &
2764 ~0x00003f9f) | (ch->unit + 1));
2765
2766 /* softreset HOST module */ /* XXX SOS what about other outstandings */
2767 mtx_lock(&hpktp->mtx);
2768 ATA_OUTL(ctlr->r_res2, 0xc012c,
2769 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11));
2770 DELAY(10);
2771 ATA_OUTL(ctlr->r_res2, 0xc012c,
2772 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f));
2773 hpktp->busy = 0;
2774 mtx_unlock(&hpktp->mtx);
2775 ata_generic_reset(dev);
2776 break;
2777
2778 case PRCMBO:
2779 case PRSATA:
2780 if ((ctlr->chip->cfg2 == PRSATA) ||
2781 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
2782
2783 /* mask plug/unplug intr */
2784 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit));
2785 }
2786
2787 /* softreset channels ATA module */
2788 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
2789 ata_udelay(10000);
2790 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
2791 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
2792 ~0x00003f9f) | (ch->unit + 1));
2793
2794 if ((ctlr->chip->cfg2 == PRSATA) ||
2795 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
2796
2797 ata_sata_phy_enable(ch);
2798
2799 /* reset and enable plug/unplug intr */
2800 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit));
2801 }
2802 else
2803 ata_generic_reset(dev);
2804 break;
2805
2806 case PRCMBO2:
2807 case PRSATA2:
2808 if ((ctlr->chip->cfg2 == PRSATA2) ||
2809 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
2810 /* set portmultiplier port */
2811 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f);
2812
2813 /* mask plug/unplug intr */
2814 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit));
2815 }
2816
2817 /* softreset channels ATA module */
2818 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
2819 ata_udelay(10000);
2820 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
2821 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
2822 ~0x00003f9f) | (ch->unit + 1));
2823
2824 if ((ctlr->chip->cfg2 == PRSATA2) ||
2825 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
2826
2827 /* set PHY mode to "improved" */
2828 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8),
2829 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) &
2830 ~0x00000003) | 0x00000001);
2831
2832 ata_sata_phy_enable(ch);
2833
2834 /* reset and enable plug/unplug intr */
2835 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit));
2836
2837 /* set portmultiplier port */
2838 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00);
2839 }
2840 else
2841 ata_generic_reset(dev);
2842 break;
2843
2844 }
2845 }
2846
2847 static int
2848 ata_promise_mio_command(struct ata_request *request)
2849 {
2850 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2851 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2852 u_int32_t *wordp = (u_int32_t *)ch->dma->work;
2853
2854 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001);
2855
2856 /* XXX SOS add ATAPI commands support later */
2857 switch (request->u.ata.command) {
2858 default:
2859 return ata_generic_command(request);
2860
2861 case ATA_READ_DMA:
2862 case ATA_READ_DMA48:
2863 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24));
2864 break;
2865
2866 case ATA_WRITE_DMA:
2867 case ATA_WRITE_DMA48:
2868 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24));
2869 break;
2870 }
2871 wordp[1] = htole32(ch->dma->sg_bus);
2872 wordp[2] = 0;
2873 ata_promise_apkt((u_int8_t*)wordp, request);
2874
2875 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma->work_bus);
2876 return 0;
2877 }
2878
2879 static int
2880 ata_promise_sx4_command(struct ata_request *request)
2881 {
2882 device_t gparent = GRANDPARENT(request->dev);
2883 struct ata_pci_controller *ctlr = device_get_softc(gparent);
2884 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2885 struct ata_dma_prdentry *prd = ch->dma->sg;
2886 caddr_t window = rman_get_virtual(ctlr->r_res1);
2887 u_int32_t *wordp;
2888 int i, idx, length = 0;
2889
2890 /* XXX SOS add ATAPI commands support later */
2891 switch (request->u.ata.command) {
2892
2893 default:
2894 return -1;
2895
2896 case ATA_ATA_IDENTIFY:
2897 case ATA_READ:
2898 case ATA_READ48:
2899 case ATA_READ_MUL:
2900 case ATA_READ_MUL48:
2901 case ATA_WRITE:
2902 case ATA_WRITE48:
2903 case ATA_WRITE_MUL:
2904 case ATA_WRITE_MUL48:
2905 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
2906 return ata_generic_command(request);
2907
2908 case ATA_SETFEATURES:
2909 case ATA_FLUSHCACHE:
2910 case ATA_FLUSHCACHE48:
2911 case ATA_SLEEP:
2912 case ATA_SET_MULTI:
2913 wordp = (u_int32_t *)
2914 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
2915 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24));
2916 wordp[1] = 0;
2917 wordp[2] = 0;
2918 ata_promise_apkt((u_int8_t *)wordp, request);
2919 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
2920 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
2921 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
2922 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET));
2923 return 0;
2924
2925 case ATA_READ_DMA:
2926 case ATA_READ_DMA48:
2927 case ATA_WRITE_DMA:
2928 case ATA_WRITE_DMA48:
2929 wordp = (u_int32_t *)
2930 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET);
2931 i = idx = 0;
2932 do {
2933 wordp[idx++] = prd[i].addr;
2934 wordp[idx++] = prd[i].count;
2935 length += (prd[i].count & ~ATA_DMA_EOT);
2936 } while (!(prd[i++].count & ATA_DMA_EOT));
2937
2938 wordp = (u_int32_t *)
2939 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET);
2940 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
2941 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
2942
2943 wordp = (u_int32_t *)
2944 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET);
2945 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
2946 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
2947
2948 wordp = (u_int32_t *)
2949 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET);
2950 if (request->flags & ATA_R_READ)
2951 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24));
2952 if (request->flags & ATA_R_WRITE)
2953 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24));
2954 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET);
2955 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET);
2956 wordp[3] = 0;
2957
2958 wordp = (u_int32_t *)
2959 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
2960 if (request->flags & ATA_R_READ)
2961 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24));
2962 if (request->flags & ATA_R_WRITE)
2963 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24));
2964 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET);
2965 wordp[2] = 0;
2966 ata_promise_apkt((u_int8_t *)wordp, request);
2967 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
2968
2969 if (request->flags & ATA_R_READ) {
2970 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001);
2971 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001);
2972 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
2973 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET));
2974 }
2975 if (request->flags & ATA_R_WRITE) {
2976 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001);
2977 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001);
2978 ata_promise_queue_hpkt(ctlr,
2979 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET));
2980 }
2981 return 0;
2982 }
2983 }
2984
2985 static int
2986 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request)
2987 {
2988 struct ata_device *atadev = device_get_softc(request->dev);
2989 int i = 12;
2990
2991 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE;
2992 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit;
2993 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL;
2994 bytep[i++] = ATA_A_4BIT;
2995
2996 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
2997 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE;
2998 bytep[i++] = request->u.ata.feature >> 8;
2999 bytep[i++] = request->u.ata.feature;
3000 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT;
3001 bytep[i++] = request->u.ata.count >> 8;
3002 bytep[i++] = request->u.ata.count;
3003 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR;
3004 bytep[i++] = request->u.ata.lba >> 24;
3005 bytep[i++] = request->u.ata.lba;
3006 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
3007 bytep[i++] = request->u.ata.lba >> 32;
3008 bytep[i++] = request->u.ata.lba >> 8;
3009 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
3010 bytep[i++] = request->u.ata.lba >> 40;
3011 bytep[i++] = request->u.ata.lba >> 16;
3012 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
3013 bytep[i++] = ATA_D_LBA | atadev->unit;
3014 }
3015 else {
3016 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE;
3017 bytep[i++] = request->u.ata.feature;
3018 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT;
3019 bytep[i++] = request->u.ata.count;
3020 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR;
3021 bytep[i++] = request->u.ata.lba;
3022 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
3023 bytep[i++] = request->u.ata.lba >> 8;
3024 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
3025 bytep[i++] = request->u.ata.lba >> 16;
3026 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
3027 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) |
3028 ATA_D_IBM | atadev->unit | ((request->u.ata.lba >> 24)&0xf);
3029 }
3030 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND;
3031 bytep[i++] = request->u.ata.command;
3032 return i;
3033 }
3034
3035 static void
3036 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt)
3037 {
3038 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
3039
3040 mtx_lock(&hpktp->mtx);
3041 if (hpktp->busy) {
3042 struct host_packet *hp =
3043 malloc(sizeof(struct host_packet), M_TEMP, M_NOWAIT | M_ZERO);
3044 hp->addr = hpkt;
3045 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain);
3046 }
3047 else {
3048 hpktp->busy = 1;
3049 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt);
3050 }
3051 mtx_unlock(&hpktp->mtx);
3052 }
3053
3054 static void
3055 ata_promise_next_hpkt(struct ata_pci_controller *ctlr)
3056 {
3057 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
3058 struct host_packet *hp;
3059
3060 mtx_lock(&hpktp->mtx);
3061 if ((hp = TAILQ_FIRST(&hpktp->queue))) {
3062 TAILQ_REMOVE(&hpktp->queue, hp, chain);
3063 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr);
3064 free(hp, M_TEMP);
3065 }
3066 else
3067 hpktp->busy = 0;
3068 mtx_unlock(&hpktp->mtx);
3069 }
3070
3071 static void
3072 ata_promise_tx2_intr(void *data)
3073 {
3074 struct ata_pci_controller *ctlr = data;
3075 struct ata_channel *ch;
3076 int unit;
3077
3078 for (unit = 0; unit < ctlr->channels; unit++) {
3079 if (!(ch = ctlr->interrupt[unit].argument))
3080 continue;
3081 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3082 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
3083 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
3084 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
3085
3086 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
3087 ATA_BMSTAT_INTERRUPT)
3088 continue;
3089 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
3090 DELAY(1);
3091 }
3092 ctlr->interrupt[unit].function(ch);
3093 }
3094 }
3095 }
3096
3097 static void
3098 ata_promise_old_intr(void *data)
3099 {
3100 struct ata_pci_controller *ctlr = data;
3101 struct ata_channel *ch;
3102 int unit;
3103
3104 for (unit = 0; unit < ctlr->channels; unit++) {
3105 if (!(ch = ctlr->interrupt[unit].argument))
3106 continue;
3107 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)){
3108 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
3109 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
3110
3111 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
3112 ATA_BMSTAT_INTERRUPT)
3113 continue;
3114 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
3115 DELAY(1);
3116 }
3117 ctlr->interrupt[unit].function(ch);
3118 }
3119 }
3120 }
3121
3122 static int
3123 ata_promise_new_dmastart(device_t dev)
3124 {
3125 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3126 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3127 struct ata_device *atadev = device_get_softc(dev);
3128
3129 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3130 ATA_OUTB(ctlr->r_res1, 0x11,
3131 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02));
3132 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20,
3133 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) |
3134 (ch->dma->cur_iosize >> 1));
3135 }
3136 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) |
3137 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
3138 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus);
3139 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3140 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) |
3141 ATA_BMCMD_START_STOP);
3142 ch->flags |= ATA_DMA_ACTIVE;
3143 return 0;
3144 }
3145
3146 static int
3147 ata_promise_new_dmastop(device_t dev)
3148 {
3149 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3150 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3151 struct ata_device *atadev = device_get_softc(dev);
3152 int error;
3153
3154 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3155 ATA_OUTB(ctlr->r_res1, 0x11,
3156 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02));
3157 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0);
3158 }
3159 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT);
3160 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3161 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3162 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3163 ch->flags &= ~ATA_DMA_ACTIVE;
3164 return error;
3165 }
3166
3167 static void
3168 ata_promise_new_dmareset(device_t dev)
3169 {
3170 struct ata_channel *ch = device_get_softc(dev);
3171
3172 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3173 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3174 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3175 ch->flags &= ~ATA_DMA_ACTIVE;
3176 }
3177
3178 static void
3179 ata_promise_new_dmainit(device_t dev)
3180 {
3181 struct ata_channel *ch = device_get_softc(dev);
3182
3183 ata_dmainit(dev);
3184 if (ch->dma) {
3185 ch->dma->start = ata_promise_new_dmastart;
3186 ch->dma->stop = ata_promise_new_dmastop;
3187 ch->dma->reset = ata_promise_new_dmareset;
3188 }
3189 }
3190
3191 static void
3192 ata_promise_setmode(device_t dev, int mode)
3193 {
3194 device_t gparent = GRANDPARENT(dev);
3195 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3196 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3197 struct ata_device *atadev = device_get_softc(dev);
3198 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
3199 int error;
3200 u_int32_t timings33[][2] = {
3201 /* PROLD PRNEW mode */
3202 { 0x004ff329, 0x004fff2f }, /* PIO 0 */
3203 { 0x004fec25, 0x004ff82a }, /* PIO 1 */
3204 { 0x004fe823, 0x004ff026 }, /* PIO 2 */
3205 { 0x004fe622, 0x004fec24 }, /* PIO 3 */
3206 { 0x004fe421, 0x004fe822 }, /* PIO 4 */
3207 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */
3208 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */
3209 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */
3210 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */
3211 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */
3212 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */
3213 { 0, 0x00424ef6 }, /* UDMA 3 */
3214 { 0, 0x004127f3 }, /* UDMA 4 */
3215 { 0, 0x004127f3 } /* UDMA 5 */
3216 };
3217
3218 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
3219
3220 switch (ctlr->chip->cfg1) {
3221 case PROLD:
3222 case PRNEW:
3223 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) &
3224 (ch->unit ? 1 << 11 : 1 << 10))) {
3225 ata_print_cable(dev, "controller");
3226 mode = ATA_UDMA2;
3227 }
3228 if (ata_atapi(dev) && mode > ATA_PIO_MAX)
3229 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
3230 break;
3231
3232 case PRTX:
3233 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3234 if (mode > ATA_UDMA2 &&
3235 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) {
3236 ata_print_cable(dev, "controller");
3237 mode = ATA_UDMA2;
3238 }
3239 break;
3240
3241 case PRMIO:
3242 if (mode > ATA_UDMA2 &&
3243 (ATA_INL(ctlr->r_res2,
3244 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) +
3245 (ch->unit << 7)) & 0x01000000)) {
3246 ata_print_cable(dev, "controller");
3247 mode = ATA_UDMA2;
3248 }
3249 break;
3250 }
3251
3252 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3253
3254 if (bootverbose)
3255 device_printf(dev, "%ssetting %s on %s chip\n",
3256 (error) ? "FAILURE " : "",
3257 ata_mode2str(mode), ctlr->chip->text);
3258 if (!error) {
3259 if (ctlr->chip->cfg1 < PRTX)
3260 pci_write_config(gparent, 0x60 + (devno << 2),
3261 timings33[ctlr->chip->cfg1][ata_mode2idx(mode)],4);
3262 atadev->mode = mode;
3263 }
3264 return;
3265 }
3266
3267
3268 /*
3269 * ServerWorks chipset support functions
3270 */
3271 int
3272 ata_serverworks_ident(device_t dev)
3273 {
3274 struct ata_pci_controller *ctlr = device_get_softc(dev);
3275 struct ata_chip_id *idx;
3276 static struct ata_chip_id ids[] =
3277 {{ ATA_ROSB4, 0x00, SWKS33, 0x00, ATA_UDMA2, "ServerWorks ROSB4" },
3278 { ATA_CSB5, 0x92, SWKS100, 0x00, ATA_UDMA5, "ServerWorks CSB5" },
3279 { ATA_CSB5, 0x00, SWKS66, 0x00, ATA_UDMA4, "ServerWorks CSB5" },
3280 { ATA_CSB6, 0x00, SWKS100, 0x00, ATA_UDMA5, "ServerWorks CSB6" },
3281 { ATA_CSB6_1, 0x00, SWKS66, 0x00, ATA_UDMA4, "ServerWorks CSB6" },
3282 { 0, 0, 0, 0, 0, 0}};
3283 char buffer[64];
3284
3285 if (!(idx = ata_match_chip(dev, ids)))
3286 return ENXIO;
3287
3288 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
3289 device_set_desc_copy(dev, buffer);
3290 ctlr->chip = idx;
3291 ctlr->chipinit = ata_serverworks_chipinit;
3292 return 0;
3293 }
3294
3295 static int
3296 ata_serverworks_chipinit(device_t dev)
3297 {
3298 struct ata_pci_controller *ctlr = device_get_softc(dev);
3299
3300 if (ata_setup_interrupt(dev))
3301 return ENXIO;
3302
3303 if (ctlr->chip->cfg1 == SWKS33) {
3304 device_t *children;
3305 int nchildren, i;
3306
3307 /* locate the ISA part in the southbridge and enable UDMA33 */
3308 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
3309 for (i = 0; i < nchildren; i++) {
3310 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
3311 pci_write_config(children[i], 0x64,
3312 (pci_read_config(children[i], 0x64, 4) &
3313 ~0x00002000) | 0x00004000, 4);
3314 break;
3315 }
3316 }
3317 free(children, M_TEMP);
3318 }
3319 }
3320 else {
3321 pci_write_config(dev, 0x5a,
3322 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
3323 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1);
3324 }
3325 ctlr->setmode = ata_serverworks_setmode;
3326 return 0;
3327 }
3328
3329 static void
3330 ata_serverworks_setmode(device_t dev, int mode)
3331 {
3332 device_t gparent = GRANDPARENT(dev);
3333 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3334 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3335 struct ata_device *atadev = device_get_softc(dev);
3336 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
3337 int offset = (devno ^ 0x01) << 3;
3338 int error;
3339 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
3340 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
3341 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
3342
3343 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
3344
3345 mode = ata_check_80pin(dev, mode);
3346
3347 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3348
3349 if (bootverbose)
3350 device_printf(dev, "%ssetting %s on %s chip\n",
3351 (error) ? "FAILURE " : "",
3352 ata_mode2str(mode), ctlr->chip->text);
3353 if (!error) {
3354 if (mode >= ATA_UDMA0) {
3355 pci_write_config(gparent, 0x56,
3356 (pci_read_config(gparent, 0x56, 2) &
3357 ~(0xf << (devno << 2))) |
3358 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
3359 pci_write_config(gparent, 0x54,
3360 pci_read_config(gparent, 0x54, 1) |
3361 (0x01 << devno), 1);
3362 pci_write_config(gparent, 0x44,
3363 (pci_read_config(gparent, 0x44, 4) &
3364 ~(0xff << offset)) |
3365 (dmatimings[2] << offset), 4);
3366 }
3367 else if (mode >= ATA_WDMA0) {
3368 pci_write_config(gparent, 0x54,
3369 pci_read_config(gparent, 0x54, 1) &
3370 ~(0x01 << devno), 1);
3371 pci_write_config(gparent, 0x44,
3372 (pci_read_config(gparent, 0x44, 4) &
3373 ~(0xff << offset)) |
3374 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
3375 }
3376 else
3377 pci_write_config(gparent, 0x54,
3378 pci_read_config(gparent, 0x54, 1) &
3379 ~(0x01 << devno), 1);
3380
3381 pci_write_config(gparent, 0x40,
3382 (pci_read_config(gparent, 0x40, 4) &
3383 ~(0xff << offset)) |
3384 (piotimings[ata_mode2idx(mode)] << offset), 4);
3385 atadev->mode = mode;
3386 }
3387 }
3388
3389
3390 /*
3391 * Silicon Image Inc. (SiI) (former CMD) chipset support functions
3392 */
3393 int
3394 ata_sii_ident(device_t dev)
3395 {
3396 struct ata_pci_controller *ctlr = device_get_softc(dev);
3397 struct ata_chip_id *idx;
3398 static struct ata_chip_id ids[] =
3399 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" },
3400 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" },
3401 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
3402 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
3403 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" },
3404 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
3405 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
3406 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" },
3407 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" },
3408 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" },
3409 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" },
3410 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" },
3411 { 0, 0, 0, 0, 0, 0}};
3412 char buffer[64];
3413
3414 if (!(idx = ata_match_chip(dev, ids)))
3415 return ENXIO;
3416
3417 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
3418 device_set_desc_copy(dev, buffer);
3419 ctlr->chip = idx;
3420 ctlr->chipinit = ata_sii_chipinit;
3421 return 0;
3422 }
3423
3424 static int
3425 ata_sii_chipinit(device_t dev)
3426 {
3427 struct ata_pci_controller *ctlr = device_get_softc(dev);
3428 int rid = ATA_IRQ_RID;
3429
3430 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3431 RF_SHAREABLE | RF_ACTIVE))) {
3432 device_printf(dev, "unable to map interrupt\n");
3433 return ENXIO;
3434 }
3435
3436 if (ctlr->chip->cfg1 == SIIMEMIO) {
3437 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
3438 ata_sii_intr, ctlr, &ctlr->handle))) {
3439 device_printf(dev, "unable to setup interrupt\n");
3440 return ENXIO;
3441 }
3442
3443 ctlr->r_type2 = SYS_RES_MEMORY;
3444 ctlr->r_rid2 = PCIR_BAR(5);
3445 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3446 &ctlr->r_rid2, RF_ACTIVE)))
3447 return ENXIO;
3448
3449 if (ctlr->chip->cfg2 & SIISETCLK) {
3450 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
3451 pci_write_config(dev, 0x8a,
3452 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
3453 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
3454 device_printf(dev, "%s could not set ATA133 clock\n",
3455 ctlr->chip->text);
3456 }
3457
3458 /* if we have 4 channels enable the second set */
3459 if (ctlr->chip->cfg2 & SII4CH) {
3460 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
3461 ctlr->channels = 4;
3462 }
3463
3464 /* enable PCI interrupt as BIOS might not */
3465 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
3466
3467 /* dont block interrupts from any channel */
3468 pci_write_config(dev, 0x48,
3469 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
3470
3471 ctlr->allocate = ata_sii_allocate;
3472 if (ctlr->chip->max_dma >= ATA_SA150) {
3473 ctlr->reset = ata_sii_reset;
3474 ctlr->setmode = ata_sata_setmode;
3475 }
3476 else
3477 ctlr->setmode = ata_sii_setmode;
3478 }
3479 else {
3480 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
3481 ctlr->chip->cfg2 & SIIINTR ?
3482 ata_cmd_intr : ata_cmd_old_intr,
3483 ctlr, &ctlr->handle))) {
3484 device_printf(dev, "unable to setup interrupt\n");
3485 return ENXIO;
3486 }
3487
3488 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
3489 device_printf(dev, "HW has secondary channel disabled\n");
3490 ctlr->channels = 1;
3491 }
3492
3493 /* enable interrupt as BIOS might not */
3494 pci_write_config(dev, 0x71, 0x01, 1);
3495
3496 ctlr->setmode = ata_cmd_setmode;
3497 }
3498 return 0;
3499 }
3500
3501 static int
3502 ata_sii_allocate(device_t dev)
3503 {
3504 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3505 struct ata_channel *ch = device_get_softc(dev);
3506 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
3507 int i;
3508
3509 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
3510 ch->r_io[i].res = ctlr->r_res2;
3511 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
3512 }
3513 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
3514 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
3515 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
3516 ata_default_registers(dev);
3517 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
3518 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
3519 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
3520 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
3521 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
3522 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
3523 ch->r_io[ATA_BMDEVSPEC_0].res = ctlr->r_res2;
3524 ch->r_io[ATA_BMDEVSPEC_0].offset = 0xa1 + (unit01 << 6) + (unit10 << 8);
3525
3526 if (ctlr->chip->max_dma >= ATA_SA150) {
3527 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3528 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
3529 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3530 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
3531 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3532 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
3533 ch->flags |= ATA_NO_SLAVE;
3534
3535 /* enable PHY state change interrupt */
3536 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
3537 }
3538
3539 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) {
3540 /* work around errata in early chips */
3541 ch->dma->boundary = 16 * DEV_BSIZE;
3542 ch->dma->segsize = 15 * DEV_BSIZE;
3543 }
3544
3545 ata_generic_hw(dev);
3546 return 0;
3547 }
3548
3549 static void
3550 ata_sii_intr(void *data)
3551 {
3552 struct ata_pci_controller *ctlr = data;
3553 struct ata_channel *ch;
3554 int unit;
3555
3556 for (unit = 0; unit < ctlr->channels; unit++) {
3557 if (!(ch = ctlr->interrupt[unit].argument))
3558 continue;
3559
3560 /* check for PHY related interrupts on SATA capable HW */
3561 if (ctlr->chip->max_dma >= ATA_SA150) {
3562 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS);
3563 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR);
3564 struct ata_connect_task *tp;
3565
3566 if (error) {
3567 /* clear error bits/interrupt */
3568 ATA_IDX_OUTL(ch, ATA_SERROR, error);
3569
3570 /* if we have a connection event deal with it */
3571 if ((error & ATA_SE_PHY_CHANGED) &&
3572 (tp = (struct ata_connect_task *)
3573 malloc(sizeof(struct ata_connect_task),
3574 M_ATA, M_NOWAIT | M_ZERO))) {
3575
3576 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) {
3577 device_printf(ch->dev, "CONNECT requested\n");
3578 tp->action = ATA_C_ATTACH;
3579 }
3580 else {
3581 device_printf(ch->dev, "DISCONNECT requested\n");
3582 tp->action = ATA_C_DETACH;
3583 }
3584 tp->dev = ch->dev;
3585 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3586 taskqueue_enqueue(taskqueue_thread, &tp->task);
3587 }
3588 }
3589 }
3590
3591 /* any drive action to take care of ? */
3592 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_0) & 0x08) {
3593 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
3594 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
3595
3596 if (!(bmstat & ATA_BMSTAT_INTERRUPT))
3597 continue;
3598 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
3599 DELAY(1);
3600 }
3601 ctlr->interrupt[unit].function(ch);
3602 }
3603
3604 }
3605 }
3606
3607 static void
3608 ata_cmd_intr(void *data)
3609 {
3610 struct ata_pci_controller *ctlr = data;
3611 struct ata_channel *ch;
3612 u_int8_t reg71;
3613 int unit;
3614
3615 for (unit = 0; unit < ctlr->channels; unit++) {
3616 if (!(ch = ctlr->interrupt[unit].argument))
3617 continue;
3618 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
3619 (ch->unit ? 0x08 : 0x04))) {
3620 pci_write_config(device_get_parent(ch->dev), 0x71,
3621 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
3622 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
3623 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
3624
3625 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
3626 ATA_BMSTAT_INTERRUPT)
3627 continue;
3628 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
3629 DELAY(1);
3630 }
3631 ctlr->interrupt[unit].function(ch);
3632 }
3633 }
3634 }
3635
3636 static void
3637 ata_cmd_old_intr(void *data)
3638 {
3639 struct ata_pci_controller *ctlr = data;
3640 struct ata_channel *ch;
3641 int unit;
3642
3643 for (unit = 0; unit < ctlr->channels; unit++) {
3644 if (!(ch = ctlr->interrupt[unit].argument))
3645 continue;
3646 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
3647 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
3648
3649 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
3650 ATA_BMSTAT_INTERRUPT)
3651 continue;
3652 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
3653 DELAY(1);
3654 }
3655 ctlr->interrupt[unit].function(ch);
3656 }
3657 }
3658
3659 static void
3660 ata_sii_reset(device_t dev)
3661 {
3662 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3663 struct ata_channel *ch = device_get_softc(dev);
3664 int offset = ((ch->unit & 1) << 7) + ((ch->unit & 2) << 8);
3665
3666 /* disable PHY state change interrupt */
3667 ATA_OUTL(ctlr->r_res2, 0x148 + offset, ~(1 << 16));
3668
3669 /* reset controller part for this channel */
3670 ATA_OUTL(ctlr->r_res2, 0x48,
3671 ATA_INL(ctlr->r_res2, 0x48) | (0xc0 >> ch->unit));
3672 DELAY(1000);
3673 ATA_OUTL(ctlr->r_res2, 0x48,
3674 ATA_INL(ctlr->r_res2, 0x48) & ~(0xc0 >> ch->unit));
3675
3676 ata_sata_phy_enable(ch);
3677
3678 /* enable PHY state change interrupt */
3679 ATA_OUTL(ctlr->r_res2, 0x148 + offset, (1 << 16));
3680 }
3681
3682 static void
3683 ata_sii_setmode(device_t dev, int mode)
3684 {
3685 device_t gparent = GRANDPARENT(dev);
3686 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3687 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3688 struct ata_device *atadev = device_get_softc(dev);
3689 int rego = (ch->unit << 4) + (ATA_DEV(atadev->unit) << 1);
3690 int mreg = ch->unit ? 0x84 : 0x80;
3691 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2);
3692 int mval = pci_read_config(gparent, mreg, 1) & ~mask;
3693 int error;
3694
3695 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
3696
3697 if (ctlr->chip->cfg2 & SIISETCLK) {
3698 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) &
3699 (ch->unit ? 0x02 : 0x01))) {
3700 ata_print_cable(dev, "controller");
3701 mode = ATA_UDMA2;
3702 }
3703 }
3704 else
3705 mode = ata_check_80pin(dev, mode);
3706
3707 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3708
3709 if (bootverbose)
3710 device_printf(dev, "%ssetting %s on %s chip\n",
3711 (error) ? "FAILURE " : "",
3712 ata_mode2str(mode), ctlr->chip->text);
3713 if (error)
3714 return;
3715
3716 if (mode >= ATA_UDMA0) {
3717 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
3718 u_int8_t ureg = 0xac + rego;
3719
3720 pci_write_config(gparent, mreg,
3721 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1);
3722 pci_write_config(gparent, ureg,
3723 (pci_read_config(gparent, ureg, 1) & ~0x3f) |
3724 udmatimings[mode & ATA_MODE_MASK], 1);
3725
3726 }
3727 else if (mode >= ATA_WDMA0) {
3728 u_int8_t dreg = 0xa8 + rego;
3729 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
3730
3731 pci_write_config(gparent, mreg,
3732 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1);
3733 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
3734
3735 }
3736 else {
3737 u_int8_t preg = 0xa4 + rego;
3738 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
3739
3740 pci_write_config(gparent, mreg,
3741 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1);
3742 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2);
3743 }
3744 atadev->mode = mode;
3745 }
3746
3747 static void
3748 ata_cmd_setmode(device_t dev, int mode)
3749 {
3750 device_t gparent = GRANDPARENT(dev);
3751 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3752 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3753 struct ata_device *atadev = device_get_softc(dev);
3754 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
3755 int error;
3756
3757 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
3758
3759 mode = ata_check_80pin(dev, mode);
3760
3761 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3762
3763 if (bootverbose)
3764 device_printf(dev, "%ssetting %s on %s chip\n",
3765 (error) ? "FAILURE " : "",
3766 ata_mode2str(mode), ctlr->chip->text);
3767 if (!error) {
3768 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
3769 int ureg = ch->unit ? 0x7b : 0x73;
3770
3771 if (mode >= ATA_UDMA0) {
3772 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
3773 { 0x11, 0x42 }, { 0x25, 0x8a },
3774 { 0x15, 0x4a }, { 0x05, 0x0a } };
3775
3776 u_int8_t umode = pci_read_config(gparent, ureg, 1);
3777
3778 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
3779 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)];
3780 pci_write_config(gparent, ureg, umode, 1);
3781 }
3782 else if (mode >= ATA_WDMA0) {
3783 int dmatimings[] = { 0x87, 0x32, 0x3f };
3784
3785 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1);
3786 pci_write_config(gparent, ureg,
3787 pci_read_config(gparent, ureg, 1) &
3788 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
3789 }
3790 else {
3791 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
3792 pci_write_config(gparent, treg,
3793 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
3794 pci_write_config(gparent, ureg,
3795 pci_read_config(gparent, ureg, 1) &
3796 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
3797 }
3798 atadev->mode = mode;
3799 }
3800 }
3801
3802
3803 /*
3804 * Silicon Integrated Systems Corp. (SiS) chipset support functions
3805 */
3806 int
3807 ata_sis_ident(device_t dev)
3808 {
3809 struct ata_pci_controller *ctlr = device_get_softc(dev);
3810 struct ata_chip_id *idx;
3811 static struct ata_chip_id ids[] =
3812 {{ ATA_SIS182, 0x00, SISSATA, 0, ATA_SA150, "SiS 182" }, /* south */
3813 { ATA_SIS181, 0x00, SISSATA, 0, ATA_SA150, "SiS 181" }, /* south */
3814 { ATA_SIS180, 0x00, SISSATA, 0, ATA_SA150, "SiS 180" }, /* south */
3815 { ATA_SIS965, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 965" }, /* south */
3816 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 964" }, /* south */
3817 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 963" }, /* south */
3818 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 962" }, /* south */
3819
3820 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 745" }, /* 1chip */
3821 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 735" }, /* 1chip */
3822 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 733" }, /* 1chip */
3823 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "SiS 730" }, /* 1chip */
3824
3825 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 635" }, /* 1chip */
3826 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 633" }, /* unknown */
3827 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "SiS 630S"}, /* 1chip */
3828 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "SiS 630" }, /* 1chip */
3829 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "SiS 620" }, /* 1chip */
3830
3831 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "SiS 550" },
3832 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "SiS 540" },
3833 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "SiS 530" },
3834
3835 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "SiS 5513" },
3836 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "SiS 5513" },
3837 { 0, 0, 0, 0, 0, 0 }};
3838 char buffer[64];
3839 int found = 0;
3840
3841 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev))))
3842 return ENXIO;
3843
3844 if (idx->cfg2 && !found) {
3845 u_int8_t reg57 = pci_read_config(dev, 0x57, 1);
3846
3847 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1);
3848 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) {
3849 found = 1;
3850 idx->cfg1 = SIS133NEW;
3851 idx->max_dma = ATA_UDMA6;
3852 sprintf(buffer, "SiS 962/963 %s controller",
3853 ata_mode2str(idx->max_dma));
3854 }
3855 pci_write_config(dev, 0x57, reg57, 1);
3856 }
3857 if (idx->cfg2 && !found) {
3858 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1);
3859
3860 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1);
3861 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) {
3862 struct ata_chip_id id[] =
3863 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }};
3864
3865 found = 1;
3866 if (ata_find_chip(dev, id, pci_get_slot(dev))) {
3867 idx->cfg1 = SIS133OLD;
3868 idx->max_dma = ATA_UDMA6;
3869 }
3870 else {
3871 idx->cfg1 = SIS100NEW;
3872 idx->max_dma = ATA_UDMA5;
3873 }
3874 sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
3875 }
3876 pci_write_config(dev, 0x4a, reg4a, 1);
3877 }
3878 if (!found)
3879 sprintf(buffer,"%s %s controller",idx->text,ata_mode2str(idx->max_dma));
3880
3881 device_set_desc_copy(dev, buffer);
3882 ctlr->chip = idx;
3883 ctlr->chipinit = ata_sis_chipinit;
3884 return 0;
3885 }
3886
3887 static int
3888 ata_sis_chipinit(device_t dev)
3889 {
3890 struct ata_pci_controller *ctlr = device_get_softc(dev);
3891
3892 if (ata_setup_interrupt(dev))
3893 return ENXIO;
3894
3895 switch (ctlr->chip->cfg1) {
3896 case SIS33:
3897 break;
3898 case SIS66:
3899 case SIS100OLD:
3900 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1);
3901 break;
3902 case SIS100NEW:
3903 case SIS133OLD:
3904 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1);
3905 break;
3906 case SIS133NEW:
3907 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2);
3908 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2);
3909 break;
3910 case SISSATA:
3911 ctlr->r_type2 = SYS_RES_IOPORT;
3912 ctlr->r_rid2 = PCIR_BAR(5);
3913 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3914 &ctlr->r_rid2, RF_ACTIVE))) {
3915 pci_write_config(dev, PCIR_COMMAND,
3916 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
3917 ctlr->allocate = ata_sis_allocate;
3918 ctlr->reset = ata_sis_reset;
3919 }
3920 ctlr->setmode = ata_sata_setmode;
3921 return 0;
3922 default:
3923 return ENXIO;
3924 }
3925 ctlr->setmode = ata_sis_setmode;
3926 return 0;
3927 }
3928
3929 static int
3930 ata_sis_allocate(device_t dev)
3931 {
3932 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3933 struct ata_channel *ch = device_get_softc(dev);
3934
3935 /* setup the usual register normal pci style */
3936 if (ata_pci_allocate(dev))
3937 return ENXIO;
3938
3939 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3940 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 4);
3941 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3942 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 4);
3943 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3944 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 4);
3945 ch->flags |= ATA_NO_SLAVE;
3946
3947 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */
3948 /* XXX SOS unknown how to enable PHY state change interrupt */
3949 return 0;
3950 }
3951
3952 static void
3953 ata_sis_reset(device_t dev)
3954 {
3955 struct ata_channel *ch = device_get_softc(dev);
3956
3957 ata_sata_phy_enable(ch);
3958 }
3959
3960
3961 static void
3962 ata_sis_setmode(device_t dev, int mode)
3963 {
3964 device_t gparent = GRANDPARENT(dev);
3965 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3966 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3967 struct ata_device *atadev = device_get_softc(dev);
3968 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
3969 int error;
3970
3971 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
3972
3973 if (ctlr->chip->cfg1 == SIS133NEW) {
3974 if (mode > ATA_UDMA2 &&
3975 pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) {
3976 ata_print_cable(dev, "controller");
3977 mode = ATA_UDMA2;
3978 }
3979 }
3980 else {
3981 if (mode > ATA_UDMA2 &&
3982 pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) {
3983 ata_print_cable(dev, "controller");
3984 mode = ATA_UDMA2;
3985 }
3986 }
3987
3988 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3989
3990 if (bootverbose)
3991 device_printf(dev, "%ssetting %s on %s chip\n",
3992 (error) ? "FAILURE " : "",
3993 ata_mode2str(mode), ctlr->chip->text);
3994 if (!error) {
3995 switch (ctlr->chip->cfg1) {
3996 case SIS133NEW: {
3997 u_int32_t timings[] =
3998 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
3999 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
4000 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
4001 u_int32_t reg;
4002
4003 reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
4004 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4);
4005 break;
4006 }
4007 case SIS133OLD: {
4008 u_int16_t timings[] =
4009 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
4010 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
4011
4012 u_int16_t reg = 0x40 + (devno << 1);
4013
4014 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
4015 break;
4016 }
4017 case SIS100NEW: {
4018 u_int16_t timings[] =
4019 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
4020 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
4021 u_int16_t reg = 0x40 + (devno << 1);
4022
4023 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
4024 break;
4025 }
4026 case SIS100OLD:
4027 case SIS66:
4028 case SIS33: {
4029 u_int16_t timings[] =
4030 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
4031 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
4032 u_int16_t reg = 0x40 + (devno << 1);
4033
4034 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
4035 break;
4036 }
4037 }
4038 atadev->mode = mode;
4039 }
4040 }
4041
4042
4043 /* VIA Technologies Inc. chipset support functions */
4044 int
4045 ata_via_ident(device_t dev)
4046 {
4047 struct ata_pci_controller *ctlr = device_get_softc(dev);
4048 struct ata_chip_id *idx;
4049 static struct ata_chip_id ids[] =
4050 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "VIA 82C586B" },
4051 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "VIA 82C586" },
4052 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "VIA 82C596B" },
4053 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "VIA 82C596" },
4054 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "VIA 82C686B"},
4055 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "VIA 82C686A" },
4056 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "VIA 82C686" },
4057 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "VIA 8231" },
4058 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "VIA 8233" },
4059 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "VIA 8233C" },
4060 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8233A" },
4061 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8235" },
4062 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8237" },
4063 { 0, 0, 0, 0, 0, 0 }};
4064 static struct ata_chip_id new_ids[] =
4065 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "VIA 6410" },
4066 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "VIA 6420" },
4067 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "VIA 6421" },
4068 { 0, 0, 0, 0, 0, 0 }};
4069 char buffer[64];
4070
4071 if (pci_get_devid(dev) == ATA_VIA82C571) {
4072 if (!(idx = ata_find_chip(dev, ids, -99)))
4073 return ENXIO;
4074 }
4075 else {
4076 if (!(idx = ata_match_chip(dev, new_ids)))
4077 return ENXIO;
4078 }
4079
4080 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
4081 device_set_desc_copy(dev, buffer);
4082 ctlr->chip = idx;
4083 ctlr->chipinit = ata_via_chipinit;
4084 return 0;
4085 }
4086
4087 static int
4088 ata_via_chipinit(device_t dev)
4089 {
4090 struct ata_pci_controller *ctlr = device_get_softc(dev);
4091
4092 if (ata_setup_interrupt(dev))
4093 return ENXIO;
4094
4095 if (ctlr->chip->max_dma >= ATA_SA150) {
4096 ctlr->r_type2 = SYS_RES_IOPORT;
4097 ctlr->r_rid2 = PCIR_BAR(5);
4098 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4099 &ctlr->r_rid2, RF_ACTIVE))) {
4100 pci_write_config(dev, PCIR_COMMAND,
4101 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
4102 ctlr->allocate = ata_via_allocate;
4103 ctlr->reset = ata_via_reset;
4104 }
4105 ctlr->setmode = ata_sata_setmode;
4106 return 0;
4107 }
4108
4109 /* prepare for ATA-66 on the 82C686a and 82C596b */
4110 if (ctlr->chip->cfg2 & VIACLK)
4111 pci_write_config(dev, 0x50, 0x030b030b, 4);
4112
4113 /* the southbridge might need the data corruption fix */
4114 if (ctlr->chip->cfg2 & VIABUG)
4115 ata_via_southbridge_fixup(dev);
4116
4117 /* set fifo configuration half'n'half */
4118 pci_write_config(dev, 0x43,
4119 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
4120
4121 /* set status register read retry */
4122 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
4123
4124 /* set DMA read & end-of-sector fifo flush */
4125 pci_write_config(dev, 0x46,
4126 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
4127
4128 /* set sector size */
4129 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
4130 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
4131
4132 ctlr->setmode = ata_via_family_setmode;
4133 return 0;
4134 }
4135
4136 static int
4137 ata_via_allocate(device_t dev)
4138 {
4139 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4140 struct ata_channel *ch = device_get_softc(dev);
4141
4142 /* newer SATA chips has resources in one BAR for each channel */
4143 if (ctlr->chip->cfg2 & VIABAR) {
4144 struct resource *r_io;
4145 int i, rid;
4146
4147 rid = PCIR_BAR(ch->unit);
4148 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev),
4149 SYS_RES_IOPORT,
4150 &rid, RF_ACTIVE)))
4151 return ENXIO;
4152
4153 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
4154 ch->r_io[i].res = r_io;
4155 ch->r_io[i].offset = i;
4156 }
4157 ch->r_io[ATA_CONTROL].res = r_io;
4158 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE;
4159 ch->r_io[ATA_IDX_ADDR].res = r_io;
4160 ata_default_registers(dev);
4161 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
4162 ch->r_io[i].res = ctlr->r_res1;
4163 ch->r_io[i].offset = i - ATA_BMCMD_PORT;
4164 }
4165 ata_generic_hw(dev);
4166 }
4167 else {
4168 if (ata_pci_allocate(dev))
4169 return ENXIO;
4170 }
4171
4172 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4173 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1);
4174 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4175 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1);
4176 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4177 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1);
4178 ch->flags |= ATA_NO_SLAVE;
4179
4180 /* XXX SOS PHY hotplug handling missing in VIA chip ?? */
4181 /* XXX SOS unknown how to enable PHY state change interrupt */
4182 return 0;
4183 }
4184
4185 static void
4186 ata_via_reset(device_t dev)
4187 {
4188 struct ata_channel *ch = device_get_softc(dev);
4189
4190 ata_sata_phy_enable(ch);
4191 }
4192
4193 static void
4194 ata_via_southbridge_fixup(device_t dev)
4195 {
4196 device_t *children;
4197 int nchildren, i;
4198
4199 if (device_get_children(device_get_parent(dev), &children, &nchildren))
4200 return;
4201
4202 for (i = 0; i < nchildren; i++) {
4203 if (pci_get_devid(children[i]) == ATA_VIA8363 ||
4204 pci_get_devid(children[i]) == ATA_VIA8371 ||
4205 pci_get_devid(children[i]) == ATA_VIA8662 ||
4206 pci_get_devid(children[i]) == ATA_VIA8361) {
4207 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
4208
4209 if ((reg76 & 0xf0) != 0xd0) {
4210 device_printf(dev,
4211 "Correcting VIA config for southbridge data corruption bug\n");
4212 pci_write_config(children[i], 0x75, 0x80, 1);
4213 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
4214 }
4215 break;
4216 }
4217 }
4218 free(children, M_TEMP);
4219 }
4220
4221
4222 /* common code for VIA, AMD & nVidia */
4223 static void
4224 ata_via_family_setmode(device_t dev, int mode)
4225 {
4226 device_t gparent = GRANDPARENT(dev);
4227 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4228 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4229 struct ata_device *atadev = device_get_softc(dev);
4230 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
4231 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
4232 int modes[][7] = {
4233 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
4234 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
4235 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
4236 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
4237 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */
4238 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4239 int reg = 0x53 - devno;
4240 int error;
4241
4242 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4243
4244 if (ctlr->chip->cfg2 & AMDCABLE) {
4245 if (mode > ATA_UDMA2 &&
4246 !(pci_read_config(gparent, 0x42, 1) & (1 << devno))) {
4247 ata_print_cable(dev, "controller");
4248 mode = ATA_UDMA2;
4249 }
4250 }
4251 else
4252 mode = ata_check_80pin(dev, mode);
4253
4254 if (ctlr->chip->cfg2 & NVIDIA)
4255 reg += 0x10;
4256
4257 if (ctlr->chip->cfg1 != VIA133)
4258 pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
4259
4260 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4261
4262 if (bootverbose)
4263 device_printf(dev, "%ssetting %s on %s chip\n",
4264 (error) ? "FAILURE " : "", ata_mode2str(mode),
4265 ctlr->chip->text);
4266 if (!error) {
4267 if (mode >= ATA_UDMA0)
4268 pci_write_config(gparent, reg,
4269 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
4270 else
4271 pci_write_config(gparent, reg, 0x8b, 1);
4272 atadev->mode = mode;
4273 }
4274 }
4275
4276
4277 /* misc functions */
4278 struct ata_chip_id *
4279 ata_match_chip(device_t dev, struct ata_chip_id *index)
4280 {
4281 while (index->chipid != 0) {
4282 if (pci_get_devid(dev) == index->chipid &&
4283 pci_get_revid(dev) >= index->chiprev)
4284 return index;
4285 index++;
4286 }
4287 return NULL;
4288 }
4289
4290 static struct ata_chip_id *
4291 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot)
4292 {
4293 device_t *children;
4294 int nchildren, i;
4295
4296 if (device_get_children(device_get_parent(dev), &children, &nchildren))
4297 return 0;
4298
4299 while (index->chipid != 0) {
4300 for (i = 0; i < nchildren; i++) {
4301 if (((slot >= 0 && pci_get_slot(children[i]) == slot) ||
4302 (slot < 0 && pci_get_slot(children[i]) <= -slot)) &&
4303 pci_get_devid(children[i]) == index->chipid &&
4304 pci_get_revid(children[i]) >= index->chiprev) {
4305 free(children, M_TEMP);
4306 return index;
4307 }
4308 }
4309 index++;
4310 }
4311 free(children, M_TEMP);
4312 return NULL;
4313 }
4314
4315 static int
4316 ata_setup_interrupt(device_t dev)
4317 {
4318 struct ata_pci_controller *ctlr = device_get_softc(dev);
4319 int rid = ATA_IRQ_RID;
4320
4321 if (!ata_legacy(dev)) {
4322 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
4323 RF_SHAREABLE | RF_ACTIVE))) {
4324 device_printf(dev, "unable to map interrupt\n");
4325 return ENXIO;
4326 }
4327 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
4328 ata_generic_intr, ctlr, &ctlr->handle))) {
4329 device_printf(dev, "unable to setup interrupt\n");
4330 return ENXIO;
4331 }
4332 }
4333 return 0;
4334 }
4335
4336 struct ata_serialize {
4337 struct mtx locked_mtx;
4338 int locked_ch;
4339 int restart_ch;
4340 };
4341
4342 static int
4343 ata_serialize(device_t dev, int flags)
4344 {
4345 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4346 struct ata_channel *ch = device_get_softc(dev);
4347 struct ata_serialize *serial;
4348 static int inited = 0;
4349 int res;
4350
4351 if (!inited) {
4352 serial = malloc(sizeof(struct ata_serialize),
4353 M_TEMP, M_NOWAIT | M_ZERO);
4354 mtx_init(&serial->locked_mtx, "ATA serialize lock", NULL, MTX_DEF);
4355 serial->locked_ch = -1;
4356 serial->restart_ch = -1;
4357 device_set_ivars(ctlr->dev, serial);
4358 inited = 1;
4359 }
4360 else
4361 serial = device_get_ivars(ctlr->dev);
4362
4363 mtx_lock(&serial->locked_mtx);
4364 switch (flags) {
4365 case ATA_LF_LOCK:
4366 if (serial->locked_ch == -1)
4367 serial->locked_ch = ch->unit;
4368 if (serial->locked_ch != ch->unit)
4369 serial->restart_ch = ch->unit;
4370 break;
4371
4372 case ATA_LF_UNLOCK:
4373 if (serial->locked_ch == ch->unit) {
4374 serial->locked_ch = -1;
4375 if (serial->restart_ch != -1) {
4376 if ((ch = ctlr->interrupt[serial->restart_ch].argument)) {
4377 serial->restart_ch = -1;
4378 mtx_unlock(&serial->locked_mtx);
4379 ata_start(ch->dev);
4380 return -1;
4381 }
4382 }
4383 }
4384 break;
4385
4386 case ATA_LF_WHICH:
4387 break;
4388 }
4389 res = serial->locked_ch;
4390 mtx_unlock(&serial->locked_mtx);
4391 return res;
4392 }
4393
4394 static void
4395 ata_print_cable(device_t dev, u_int8_t *who)
4396 {
4397 device_printf(dev,
4398 "DMA limited to UDMA33, %s found non-ATA66 cable\n", who);
4399 }
4400
4401 static int
4402 ata_atapi(device_t dev)
4403 {
4404 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4405 struct ata_device *atadev = device_get_softc(dev);
4406
4407 return ((atadev->unit == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) ||
4408 (atadev->unit == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE));
4409 }
4410
4411 static int
4412 ata_check_80pin(device_t dev, int mode)
4413 {
4414 struct ata_device *atadev = device_get_softc(dev);
4415
4416 if (mode > ATA_UDMA2 && !(atadev->param.hwres & ATA_CABLE_ID)) {
4417 ata_print_cable(dev, "device");
4418 mode = ATA_UDMA2;
4419 }
4420 return mode;
4421 }
4422
4423 static int
4424 ata_mode2idx(int mode)
4425 {
4426 if ((mode & ATA_DMA_MASK) == ATA_UDMA0)
4427 return (mode & ATA_MODE_MASK) + 8;
4428 if ((mode & ATA_DMA_MASK) == ATA_WDMA0)
4429 return (mode & ATA_MODE_MASK) + 5;
4430 return (mode & ATA_MODE_MASK) - ATA_PIO0;
4431 }
Cache object: 51e21e67118772549570c92edcea99d3
|