1 /*-
2 * Copyright (c) 1998 - 2006 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: src/sys/dev/ata/ata-chipset.c,v 1.126.2.11 2006/03/16 21:28:51 sos Exp $");
29
30 #include "opt_ata.h"
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/ata.h>
35 #include <sys/bus.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <sys/sema.h>
41 #include <sys/taskqueue.h>
42 #include <vm/uma.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
46 #include <sys/rman.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49 #include <dev/ata/ata-all.h>
50 #include <dev/ata/ata-pci.h>
51 #include <ata_if.h>
52
53 /* local prototypes */
54 /* ata-chipset.c */
55 static int ata_generic_chipinit(device_t dev);
56 static void ata_generic_intr(void *data);
57 static void ata_generic_setmode(device_t dev, int mode);
58 static void ata_sata_phy_enable(struct ata_channel *ch);
59 static void ata_sata_phy_event(void *context, int dummy);
60 static int ata_sata_connect(struct ata_channel *ch);
61 static void ata_sata_setmode(device_t dev, int mode);
62 static int ata_ahci_allocate(device_t dev);
63 static int ata_ahci_status(device_t dev);
64 static int ata_ahci_begin_transaction(struct ata_request *request);
65 static int ata_ahci_end_transaction(struct ata_request *request);
66 static void ata_ahci_reset(device_t dev);
67 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
68 static void ata_ahci_dmainit(device_t dev);
69 static int ata_ahci_setup_fis(u_int8_t *fis, struct ata_request *request);
70 static int ata_acard_chipinit(device_t dev);
71 static int ata_acard_allocate(device_t dev);
72 static int ata_acard_status(device_t dev);
73 static void ata_acard_850_setmode(device_t dev, int mode);
74 static void ata_acard_86X_setmode(device_t dev, int mode);
75 static int ata_ali_chipinit(device_t dev);
76 static int ata_ali_allocate(device_t dev);
77 static int ata_ali_sata_allocate(device_t dev);
78 static void ata_ali_reset(device_t dev);
79 static void ata_ali_setmode(device_t dev, int mode);
80 static int ata_amd_chipinit(device_t dev);
81 static int ata_ati_chipinit(device_t dev);
82 static void ata_ati_setmode(device_t dev, int mode);
83 static int ata_cyrix_chipinit(device_t dev);
84 static void ata_cyrix_setmode(device_t dev, int mode);
85 static int ata_cypress_chipinit(device_t dev);
86 static void ata_cypress_setmode(device_t dev, int mode);
87 static int ata_highpoint_chipinit(device_t dev);
88 static int ata_highpoint_allocate(device_t dev);
89 static void ata_highpoint_setmode(device_t dev, int mode);
90 static int ata_highpoint_check_80pin(device_t dev, int mode);
91 static int ata_intel_chipinit(device_t dev);
92 static int ata_intel_allocate(device_t dev);
93 static void ata_intel_reset(device_t dev);
94 static void ata_intel_old_setmode(device_t dev, int mode);
95 static void ata_intel_new_setmode(device_t dev, int mode);
96 static int ata_intel_31244_allocate(device_t dev);
97 static int ata_intel_31244_status(device_t dev);
98 static int ata_intel_31244_command(struct ata_request *request);
99 static void ata_intel_31244_reset(device_t dev);
100 static int ata_ite_chipinit(device_t dev);
101 static void ata_ite_setmode(device_t dev, int mode);
102 static int ata_jmicron_chipinit(device_t dev);
103 static int ata_jmicron_allocate(device_t dev);
104 static void ata_jmicron_reset(device_t dev);
105 static void ata_jmicron_dmainit(device_t dev);
106 static void ata_jmicron_setmode(device_t dev, int mode);
107 static int ata_marvell_chipinit(device_t dev);
108 static int ata_marvell_allocate(device_t dev);
109 static int ata_marvell_status(device_t dev);
110 static int ata_marvell_begin_transaction(struct ata_request *request);
111 static int ata_marvell_end_transaction(struct ata_request *request);
112 static void ata_marvell_reset(device_t dev);
113 static void ata_marvell_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
114 static void ata_marvell_dmainit(device_t dev);
115 static int ata_national_chipinit(device_t dev);
116 static void ata_national_setmode(device_t dev, int mode);
117 static int ata_nvidia_chipinit(device_t dev);
118 static int ata_nvidia_allocate(device_t dev);
119 static int ata_nvidia_status(device_t dev);
120 static void ata_nvidia_reset(device_t dev);
121 static int ata_promise_chipinit(device_t dev);
122 static int ata_promise_allocate(device_t dev);
123 static int ata_promise_status(device_t dev);
124 static int ata_promise_dmastart(device_t dev);
125 static int ata_promise_dmastop(device_t dev);
126 static void ata_promise_dmareset(device_t dev);
127 static void ata_promise_dmainit(device_t dev);
128 static void ata_promise_setmode(device_t dev, int mode);
129 static int ata_promise_tx2_allocate(device_t dev);
130 static int ata_promise_tx2_status(device_t dev);
131 static int ata_promise_mio_allocate(device_t dev);
132 static void ata_promise_mio_intr(void *data);
133 static int ata_promise_mio_status(device_t dev);
134 static int ata_promise_mio_command(struct ata_request *request);
135 static void ata_promise_mio_reset(device_t dev);
136 static void ata_promise_mio_dmainit(device_t dev);
137 static void ata_promise_mio_setmode(device_t dev, int mode);
138 static void ata_promise_sx4_intr(void *data);
139 static int ata_promise_sx4_command(struct ata_request *request);
140 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request);
141 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt);
142 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr);
143 static int ata_serverworks_chipinit(device_t dev);
144 static void ata_serverworks_setmode(device_t dev, int mode);
145 static int ata_sii_chipinit(device_t dev);
146 static int ata_cmd_allocate(device_t dev);
147 static int ata_cmd_status(device_t dev);
148 static void ata_cmd_setmode(device_t dev, int mode);
149 static int ata_sii_allocate(device_t dev);
150 static int ata_sii_status(device_t dev);
151 static void ata_sii_reset(device_t dev);
152 static void ata_sii_setmode(device_t dev, int mode);
153 static int ata_sis_chipinit(device_t dev);
154 static int ata_sis_allocate(device_t dev);
155 static void ata_sis_reset(device_t dev);
156 static void ata_sis_setmode(device_t dev, int mode);
157 static int ata_via_chipinit(device_t dev);
158 static int ata_via_allocate(device_t dev);
159 static void ata_via_reset(device_t dev);
160 static void ata_via_southbridge_fixup(device_t dev);
161 static void ata_via_family_setmode(device_t dev, int mode);
162 static struct ata_chip_id *ata_match_chip(device_t dev, struct ata_chip_id *index);
163 static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot);
164 static int ata_setup_interrupt(device_t dev);
165 static int ata_serialize(device_t dev, int flags);
166 static void ata_print_cable(device_t dev, u_int8_t *who);
167 static int ata_atapi(device_t dev);
168 static int ata_check_80pin(device_t dev, int mode);
169 static int ata_mode2idx(int mode);
170
171
172 /*
173 * generic ATA support functions
174 */
175 int
176 ata_generic_ident(device_t dev)
177 {
178 struct ata_pci_controller *ctlr = device_get_softc(dev);
179
180 device_set_desc(dev, "GENERIC ATA controller");
181 ctlr->chipinit = ata_generic_chipinit;
182 return 0;
183 }
184
185 static int
186 ata_generic_chipinit(device_t dev)
187 {
188 struct ata_pci_controller *ctlr = device_get_softc(dev);
189
190 if (ata_setup_interrupt(dev))
191 return ENXIO;
192 ctlr->setmode = ata_generic_setmode;
193 return 0;
194 }
195
196 static void
197 ata_generic_intr(void *data)
198 {
199 struct ata_pci_controller *ctlr = data;
200 struct ata_channel *ch;
201 int unit;
202
203 for (unit = 0; unit < ctlr->channels; unit++) {
204 if ((ch = ctlr->interrupt[unit].argument))
205 ctlr->interrupt[unit].function(ch);
206 }
207 }
208
209 static void
210 ata_generic_setmode(device_t dev, int mode)
211 {
212 struct ata_device *atadev = device_get_softc(dev);
213
214 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
215 mode = ata_check_80pin(dev, mode);
216 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
217 atadev->mode = mode;
218 }
219
220
221 /*
222 * SATA support functions
223 */
224 static void
225 ata_sata_phy_enable(struct ata_channel *ch)
226 {
227 int loop, retry;
228
229 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) {
230 ata_sata_connect(ch);
231 return;
232 }
233
234 for (retry = 0; retry < 10; retry++) {
235 for (loop = 0; loop < 10; loop++) {
236 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET);
237 ata_udelay(100);
238 if ((ATA_IDX_INL(ch, ATA_SCONTROL) &
239 ATA_SC_DET_MASK) == ATA_SC_DET_RESET)
240 break;
241 }
242 ata_udelay(5000);
243 for (loop = 0; loop < 10; loop++) {
244 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_IDLE |
245 ATA_SC_IPM_DIS_PARTIAL |
246 ATA_SC_IPM_DIS_SLUMBER);
247 ata_udelay(100);
248 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 0) {
249 ata_sata_connect(ch);
250 return;
251 }
252 }
253 }
254 }
255
256 static void
257 ata_sata_phy_event(void *context, int dummy)
258 {
259 struct ata_connect_task *tp = (struct ata_connect_task *)context;
260 struct ata_channel *ch = device_get_softc(tp->dev);
261 device_t *children;
262 int nchildren, i;
263
264 mtx_lock(&Giant); /* newbus suckage it needs Giant */
265 if (tp->action == ATA_C_ATTACH) {
266 if (bootverbose)
267 device_printf(tp->dev, "CONNECTED\n");
268 ata_sata_connect(ch);
269 ata_identify(tp->dev);
270 }
271 if (tp->action == ATA_C_DETACH) {
272 if (!device_get_children(tp->dev, &children, &nchildren)) {
273 for (i = 0; i < nchildren; i++)
274 if (children[i])
275 device_delete_child(tp->dev, children[i]);
276 free(children, M_TEMP);
277 }
278 mtx_lock(&ch->state_mtx);
279 ch->state = ATA_IDLE;
280 mtx_unlock(&ch->state_mtx);
281 if (bootverbose)
282 device_printf(tp->dev, "DISCONNECTED\n");
283 }
284 mtx_unlock(&Giant); /* suckage code dealt with, release Giant */
285 free(tp, M_ATA);
286 }
287
288 static int
289 ata_sata_connect(struct ata_channel *ch)
290 {
291 u_int32_t status;
292 int timeout;
293
294 /* wait up to 1 second for "connect well" */
295 for (timeout = 0; timeout < 100 ; timeout++) {
296 status = ATA_IDX_INL(ch, ATA_SSTATUS);
297 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 ||
298 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)
299 break;
300 ata_udelay(10000);
301 }
302 if (timeout >= 100) {
303 if (bootverbose)
304 device_printf(ch->dev, "SATA connect status=%08x\n", status);
305 return 0;
306 }
307
308 /* clear SATA error register */
309 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
310
311 /* find out what type device we got poll for spec'd 31 seconds */
312 /* XXX SOS 10 secs for now as I have little patience */
313 ch->devices = 0;
314 for (timeout = 0; timeout < 1000; timeout++) {
315 if (ATA_IDX_INB(ch, ATA_STATUS) & ATA_S_BUSY)
316 DELAY(10000);
317 else
318 break;
319 }
320 if (bootverbose)
321 device_printf(ch->dev, "SATA connect ready time=%dms\n", timeout * 10);
322 if (timeout < 1000) {
323 if ((ATA_IDX_INB(ch, ATA_CYL_LSB) == ATAPI_MAGIC_LSB) &&
324 (ATA_IDX_INB(ch, ATA_CYL_MSB) == ATAPI_MAGIC_MSB))
325 ch->devices = ATA_ATAPI_MASTER;
326 else
327 ch->devices = ATA_ATA_MASTER;
328 }
329 if (bootverbose)
330 device_printf(ch->dev, "sata_connect devices=0x%b\n",
331 ch->devices, "\2\3ATAPI_MASTER\1ATA_MASTER");
332 return 1;
333 }
334
335 static void
336 ata_sata_setmode(device_t dev, int mode)
337 {
338 struct ata_device *atadev = device_get_softc(dev);
339
340 /*
341 * if we detect that the device isn't a real SATA device we limit
342 * the transfer mode to UDMA5/ATA100.
343 * this works around the problems some devices has with the
344 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133.
345 */
346 if (atadev->param.satacapabilities != 0x0000 &&
347 atadev->param.satacapabilities != 0xffff) {
348 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
349
350 /* on some drives we need to set the transfer mode */
351 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
352 ata_limit_mode(dev, mode, ATA_UDMA6));
353
354 /* query SATA STATUS for the speed */
355 if (ch->r_io[ATA_SSTATUS].res &&
356 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) ==
357 ATA_SS_CONWELL_GEN2))
358 atadev->mode = ATA_SA300;
359 else
360 atadev->mode = ATA_SA150;
361 }
362 else {
363 mode = ata_limit_mode(dev, mode, ATA_UDMA5);
364 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
365 atadev->mode = mode;
366 }
367 }
368
369
370 /*
371 * AHCI v1.0 compliant SATA chipset support functions
372 */
373 struct ata_ahci_dma_prd {
374 u_int64_t dba;
375 u_int32_t reserved;
376 u_int32_t dbc; /* 0 based */
377 #define ATA_AHCI_PRD_MASK 0x003fffff /* max 4MB */
378 #define ATA_AHCI_PRD_IPC (1<<31)
379 } __packed;
380
381 struct ata_ahci_cmd_tab {
382 u_int8_t cfis[64];
383 u_int8_t acmd[32];
384 u_int8_t reserved[32];
385 struct ata_ahci_dma_prd prd_tab[16];
386 } __packed;
387
388 struct ata_ahci_cmd_list {
389 u_int16_t cmd_flags;
390 u_int16_t prd_length; /* PRD entries */
391 u_int32_t bytecount;
392 u_int64_t cmd_table_phys; /* 128byte aligned */
393 } __packed;
394
395
396 static int
397 ata_ahci_allocate(device_t dev)
398 {
399 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
400 struct ata_channel *ch = device_get_softc(dev);
401 int offset = (ch->unit << 7);
402
403 /* setup legacy cruft we need */
404 ch->r_io[ATA_CYL_LSB].res = ctlr->r_res2;
405 ch->r_io[ATA_CYL_LSB].offset = ATA_AHCI_P_SIG + 1 + offset;
406 ch->r_io[ATA_CYL_MSB].res = ctlr->r_res2;
407 ch->r_io[ATA_CYL_MSB].offset = ATA_AHCI_P_SIG + 3 + offset;
408 ch->r_io[ATA_STATUS].res = ctlr->r_res2;
409 ch->r_io[ATA_STATUS].offset = ATA_AHCI_P_TFD + offset;
410 ch->r_io[ATA_ALTSTAT].res = ctlr->r_res2;
411 ch->r_io[ATA_ALTSTAT].offset = ATA_AHCI_P_TFD + offset;
412
413 /* set the SATA resources */
414 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
415 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset;
416 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
417 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset;
418 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
419 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset;
420 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
421 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset;
422
423 ch->hw.status = ata_ahci_status;
424 ch->hw.begin_transaction = ata_ahci_begin_transaction;
425 ch->hw.end_transaction = ata_ahci_end_transaction;
426 ch->hw.command = NULL; /* not used here */
427
428 /* setup the work areas */
429 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset,
430 ch->dma->work_bus + ATA_AHCI_CL_OFFSET);
431 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, 0x00000000);
432
433 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset,
434 ch->dma->work_bus + ATA_AHCI_FB_OFFSET);
435 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, 0x00000000);
436
437 /* enable wanted port interrupts */
438 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
439 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
440 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
441 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP |
442 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS |
443 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR));
444
445 /* start operations on this channel */
446 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
447 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
448 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
449 return 0;
450 }
451
452 static int
453 ata_ahci_status(device_t dev)
454 {
455 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
456 struct ata_channel *ch = device_get_softc(dev);
457 struct ata_connect_task *tp;
458 u_int32_t action, istatus, sstatus, error, issued;
459 int offset = (ch->unit << 7);
460 int tag = 0;
461
462 if ((action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS)) & (1 << ch->unit)) {
463 istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset);
464 issued = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset);
465 sstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SSTS + offset);
466 error = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SERR + offset);
467
468 /* clear interrupt(s) */
469 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action);
470 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus);
471 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_SERR + offset, error);
472
473 /* do we have cold connect surprise */
474 if (istatus & ATA_AHCI_P_IX_CPD) {
475 printf("ata_ahci_intr status=%08x sstatus=%08x error=%08x\n",
476 istatus, sstatus, error);
477 }
478
479 /* check for and handle connect events */
480 if ((istatus & ATA_AHCI_P_IX_PC) &&
481 (tp = (struct ata_connect_task *)
482 malloc(sizeof(struct ata_connect_task),
483 M_ATA, M_NOWAIT | M_ZERO))) {
484
485 if (bootverbose)
486 device_printf(ch->dev, "CONNECT requested\n");
487 tp->action = ATA_C_ATTACH;
488 tp->dev = ch->dev;
489 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
490 taskqueue_enqueue(taskqueue_thread, &tp->task);
491 }
492
493 /* check for and handle disconnect events */
494 else if ((istatus & ATA_AHCI_P_IX_PRC) &&
495 !((sstatus & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 ||
496 (sstatus & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2) &&
497 (tp = (struct ata_connect_task *)
498 malloc(sizeof(struct ata_connect_task),
499 M_ATA, M_NOWAIT | M_ZERO))) {
500
501 if (bootverbose)
502 device_printf(ch->dev, "DISCONNECT requested\n");
503 tp->action = ATA_C_DETACH;
504 tp->dev = ch->dev;
505 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
506 taskqueue_enqueue(taskqueue_thread, &tp->task);
507 }
508
509 /* do we have any device action ? */
510 if (!(issued & (1 << tag)))
511 return 1;
512 }
513 return 0;
514 }
515
516 /* must be called with ATA channel locked and state_mtx held */
517 static int
518 ata_ahci_begin_transaction(struct ata_request *request)
519 {
520 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
521 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
522 struct ata_ahci_cmd_tab *ctp;
523 struct ata_ahci_cmd_list *clp;
524 int fis_size, entries;
525 int tag = 0;
526
527 /* get a piece of the workspace for this request */
528 ctp = (struct ata_ahci_cmd_tab *)
529 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag));
530
531 /* setup the FIS for this request */ /* XXX SOS ATAPI missing still */
532 if (!(fis_size = ata_ahci_setup_fis(&ctp->cfis[0], request))) {
533 device_printf(request->dev, "setting up SATA FIS failed\n");
534 request->result = EIO;
535 return ATA_OP_FINISHED;
536 }
537
538 /* if request moves data setup and load SG list */
539 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
540 if (ch->dma->load(ch->dev, request->data, request->bytecount,
541 request->flags & ATA_R_READ,
542 ctp->prd_tab, &entries)) {
543 device_printf(request->dev, "setting up DMA failed\n");
544 request->result = EIO;
545 return ATA_OP_FINISHED;
546 }
547 }
548
549 /* setup the command list entry */
550 clp = (struct ata_ahci_cmd_list *)
551 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
552
553 clp->prd_length = entries;
554 clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) |
555 (request->flags & ATA_R_ATAPI ? (1<<5) : 0) |
556 (fis_size / sizeof(u_int32_t));
557 clp->bytecount = 0;
558 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET +
559 (ATA_AHCI_CT_SIZE * tag));
560
561 /* clear eventual ACTIVE bit */
562 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag));
563
564 /* issue the command */
565 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + (ch->unit << 7), (1 << tag));
566
567 /* start the timeout */
568 callout_reset(&request->callout, request->timeout * hz,
569 (timeout_t*)ata_timeout, request);
570 return ATA_OP_CONTINUES;
571 }
572
573 /* must be called with ATA channel locked and state_mtx held */
574 static int
575 ata_ahci_end_transaction(struct ata_request *request)
576 {
577 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
578 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
579 struct ata_ahci_cmd_list *clp;
580 u_int32_t tf_data;
581 int tag = 0;
582
583 /* kill the timeout */
584 callout_stop(&request->callout);
585
586 /* get status */
587 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit << 7));
588 request->status = tf_data;
589
590 /* if error status get details */
591 if (request->status & ATA_S_ERROR)
592 request->error = tf_data >> 8;
593
594 /* record how much data we actually moved */
595 clp = (struct ata_ahci_cmd_list *)
596 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
597 request->donecount = clp->bytecount;
598
599 /* release SG list etc */
600 ch->dma->unload(ch->dev);
601
602 return ATA_OP_FINISHED;
603 }
604
605 static void
606 ata_ahci_reset(device_t dev)
607 {
608 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
609 struct ata_channel *ch = device_get_softc(dev);
610 u_int32_t cmd;
611 int offset = (ch->unit << 7);
612
613 /* kill off all activity on this channel */
614 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
615 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
616 cmd & ~(ATA_AHCI_P_CMD_CR | ATA_AHCI_P_CMD_FR |
617 ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
618
619 DELAY(500000); /* XXX SOS this is not entirely wrong */
620
621 /* spin up device */
622 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, ATA_AHCI_P_CMD_SUD);
623
624 ata_sata_phy_enable(ch);
625
626 /* clear any interrupts pending on this channel */
627 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
628 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
629
630 /* start operations on this channel */
631 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
632 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
633 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
634 }
635
636 static void
637 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
638 {
639 struct ata_dmasetprd_args *args = xsc;
640 struct ata_ahci_dma_prd *prd = args->dmatab;
641 int i;
642
643 if (!(args->error = error)) {
644 for (i = 0; i < nsegs; i++) {
645 prd[i].dba = htole64(segs[i].ds_addr);
646 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK);
647 }
648 }
649 args->nsegs = nsegs;
650 }
651
652 static void
653 ata_ahci_dmainit(device_t dev)
654 {
655 struct ata_channel *ch = device_get_softc(dev);
656
657 ata_dmainit(dev);
658 if (ch->dma) {
659 /* note start and stop are not used here */
660 ch->dma->setprd = ata_ahci_dmasetprd;
661 ch->dma->max_iosize = 8192 * DEV_BSIZE;
662 }
663 }
664
665 static int
666 ata_ahci_setup_fis(u_int8_t *fis, struct ata_request *request)
667 {
668 struct ata_device *atadev = device_get_softc(request->dev);
669 int idx = 0;
670
671 /* XXX SOS add ATAPI commands support later */
672 ata_modify_if_48bit(request);
673
674 fis[idx++] = 0x27; /* host to device */
675 fis[idx++] = 0x80; /* command FIS (note PM goes here) */
676 fis[idx++] = request->u.ata.command;
677 fis[idx++] = request->u.ata.feature;
678
679 fis[idx++] = request->u.ata.lba;
680 fis[idx++] = request->u.ata.lba >> 8;
681 fis[idx++] = request->u.ata.lba >> 16;
682 fis[idx] = ATA_D_LBA | atadev->unit;
683 if (atadev->flags & ATA_D_48BIT_ACTIVE)
684 idx++;
685 else
686 fis[idx++] |= (request->u.ata.lba >> 24 & 0x0f);
687
688 fis[idx++] = request->u.ata.lba >> 24;
689 fis[idx++] = request->u.ata.lba >> 32;
690 fis[idx++] = request->u.ata.lba >> 40;
691 fis[idx++] = request->u.ata.feature >> 8;
692
693 fis[idx++] = request->u.ata.count;
694 fis[idx++] = request->u.ata.count >> 8;
695 fis[idx++] = 0x00;
696 fis[idx++] = ATA_A_4BIT;
697
698 fis[idx++] = 0x00;
699 fis[idx++] = 0x00;
700 fis[idx++] = 0x00;
701 fis[idx++] = 0x00;
702 return idx;
703 }
704
705
706 /*
707 * Acard chipset support functions
708 */
709 int
710 ata_acard_ident(device_t dev)
711 {
712 struct ata_pci_controller *ctlr = device_get_softc(dev);
713 struct ata_chip_id *idx;
714 static struct ata_chip_id ids[] =
715 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "ATP850" },
716 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "ATP860A" },
717 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "ATP860R" },
718 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "ATP865A" },
719 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "ATP865R" },
720 { 0, 0, 0, 0, 0, 0}};
721 char buffer[64];
722
723 if (!(idx = ata_match_chip(dev, ids)))
724 return ENXIO;
725
726 sprintf(buffer, "Acard %s %s controller",
727 idx->text, ata_mode2str(idx->max_dma));
728 device_set_desc_copy(dev, buffer);
729 ctlr->chip = idx;
730 ctlr->chipinit = ata_acard_chipinit;
731 return 0;
732 }
733
734 static int
735 ata_acard_chipinit(device_t dev)
736 {
737 struct ata_pci_controller *ctlr = device_get_softc(dev);
738
739 if (ata_setup_interrupt(dev))
740 return ENXIO;
741
742 ctlr->allocate = ata_acard_allocate;
743 if (ctlr->chip->cfg1 == ATPOLD) {
744 ctlr->setmode = ata_acard_850_setmode;
745 ctlr->locking = ata_serialize;
746 }
747 else
748 ctlr->setmode = ata_acard_86X_setmode;
749 return 0;
750 }
751
752 static int
753 ata_acard_allocate(device_t dev)
754 {
755 struct ata_channel *ch = device_get_softc(dev);
756
757 /* setup the usual register normal pci style */
758 if (ata_pci_allocate(dev))
759 return ENXIO;
760
761 ch->hw.status = ata_acard_status;
762 return 0;
763 }
764
765 static int
766 ata_acard_status(device_t dev)
767 {
768 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
769 struct ata_channel *ch = device_get_softc(dev);
770
771 if (ctlr->chip->cfg1 == ATPOLD &&
772 ATA_LOCKING(ch->dev, ATA_LF_WHICH) != ch->unit)
773 return 0;
774 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
775 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
776
777 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
778 ATA_BMSTAT_INTERRUPT)
779 return 0;
780 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
781 DELAY(1);
782 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
783 ATA_IDX_INB(ch, ATA_BMCMD_PORT)&~ATA_BMCMD_START_STOP);
784 DELAY(1);
785 }
786 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
787 DELAY(100);
788 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
789 return 0;
790 }
791 return 1;
792 }
793
794 static void
795 ata_acard_850_setmode(device_t dev, int mode)
796 {
797 device_t gparent = GRANDPARENT(dev);
798 struct ata_pci_controller *ctlr = device_get_softc(gparent);
799 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
800 struct ata_device *atadev = device_get_softc(dev);
801 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
802 int error;
803
804 mode = ata_limit_mode(dev, mode,
805 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
806
807 /* XXX SOS missing WDMA0+1 + PIO modes */
808 if (mode >= ATA_WDMA2) {
809 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
810 if (bootverbose)
811 device_printf(dev, "%ssetting %s on %s chip\n",
812 (error) ? "FAILURE " : "",
813 ata_mode2str(mode), ctlr->chip->text);
814 if (!error) {
815 u_int8_t reg54 = pci_read_config(gparent, 0x54, 1);
816
817 reg54 &= ~(0x03 << (devno << 1));
818 if (mode >= ATA_UDMA0)
819 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1));
820 pci_write_config(gparent, 0x54, reg54, 1);
821 pci_write_config(gparent, 0x4a, 0xa6, 1);
822 pci_write_config(gparent, 0x40 + (devno << 1), 0x0301, 2);
823 atadev->mode = mode;
824 return;
825 }
826 }
827 /* we could set PIO mode timings, but we assume the BIOS did that */
828 }
829
830 static void
831 ata_acard_86X_setmode(device_t dev, int mode)
832 {
833 device_t gparent = GRANDPARENT(dev);
834 struct ata_pci_controller *ctlr = device_get_softc(gparent);
835 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
836 struct ata_device *atadev = device_get_softc(dev);
837 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
838 int error;
839
840
841 mode = ata_limit_mode(dev, mode,
842 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
843
844 mode = ata_check_80pin(dev, mode);
845
846 /* XXX SOS missing WDMA0+1 + PIO modes */
847 if (mode >= ATA_WDMA2) {
848 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
849 if (bootverbose)
850 device_printf(dev, "%ssetting %s on %s chip\n",
851 (error) ? "FAILURE " : "",
852 ata_mode2str(mode), ctlr->chip->text);
853 if (!error) {
854 u_int16_t reg44 = pci_read_config(gparent, 0x44, 2);
855
856 reg44 &= ~(0x000f << (devno << 2));
857 if (mode >= ATA_UDMA0)
858 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2));
859 pci_write_config(gparent, 0x44, reg44, 2);
860 pci_write_config(gparent, 0x4a, 0xa6, 1);
861 pci_write_config(gparent, 0x40 + devno, 0x31, 1);
862 atadev->mode = mode;
863 return;
864 }
865 }
866 /* we could set PIO mode timings, but we assume the BIOS did that */
867 }
868
869
870 /*
871 * Acer Labs Inc (ALI) chipset support functions
872 */
873 int
874 ata_ali_ident(device_t dev)
875 {
876 struct ata_pci_controller *ctlr = device_get_softc(dev);
877 struct ata_chip_id *idx;
878 static struct ata_chip_id ids[] =
879 {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" },
880 { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "M5287" },
881 { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "M5281" },
882 { ATA_ALI_5229, 0xc5, 0, ALINEW, ATA_UDMA6, "M5229" },
883 { ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "M5229" },
884 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "M5229" },
885 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "M5229" },
886 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "M5229" },
887 { 0, 0, 0, 0, 0, 0}};
888 char buffer[64];
889
890 if (!(idx = ata_match_chip(dev, ids)))
891 return ENXIO;
892
893 sprintf(buffer, "AcerLabs %s %s controller",
894 idx->text, ata_mode2str(idx->max_dma));
895 device_set_desc_copy(dev, buffer);
896 ctlr->chip = idx;
897 ctlr->chipinit = ata_ali_chipinit;
898 return 0;
899 }
900
901 static int
902 ata_ali_chipinit(device_t dev)
903 {
904 struct ata_pci_controller *ctlr = device_get_softc(dev);
905
906 if (ata_setup_interrupt(dev))
907 return ENXIO;
908
909 switch (ctlr->chip->cfg2) {
910 case ALISATA:
911 ctlr->channels = ctlr->chip->cfg1;
912 ctlr->allocate = ata_ali_sata_allocate;
913 ctlr->setmode = ata_sata_setmode;
914
915 /* enable PCI interrupt */
916 pci_write_config(dev, PCIR_COMMAND,
917 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
918 break;
919
920 case ALINEW:
921 /* use device interrupt as byte count end */
922 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
923
924 /* enable cable detection and UDMA support on newer chips */
925 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1);
926
927 /* enable ATAPI UDMA mode */
928 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1);
929
930 /* only chips with revision > 0xc4 can do 48bit DMA */
931 if (ctlr->chip->chiprev <= 0xc4)
932 device_printf(dev,
933 "using PIO transfers above 137GB as workaround for "
934 "48bit DMA access bug, expect reduced performance\n");
935 ctlr->allocate = ata_ali_allocate;
936 ctlr->reset = ata_ali_reset;
937 ctlr->setmode = ata_ali_setmode;
938 break;
939
940 case ALIOLD:
941 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
942 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
943 ctlr->setmode = ata_ali_setmode;
944 break;
945 }
946 return 0;
947 }
948
949 static int
950 ata_ali_allocate(device_t dev)
951 {
952 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
953 struct ata_channel *ch = device_get_softc(dev);
954
955 /* setup the usual register normal pci style */
956 if (ata_pci_allocate(dev))
957 return ENXIO;
958
959 /* older chips can't do 48bit DMA transfers */
960 if (ctlr->chip->chiprev <= 0xc4)
961 ch->flags |= ATA_NO_48BIT_DMA;
962
963 return 0;
964 }
965
966 static int
967 ata_ali_sata_allocate(device_t dev)
968 {
969 device_t parent = device_get_parent(dev);
970 struct ata_pci_controller *ctlr = device_get_softc(parent);
971 struct ata_channel *ch = device_get_softc(dev);
972 struct resource *io = NULL, *ctlio = NULL;
973 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
974 int i, rid;
975
976 rid = PCIR_BAR(0) + (unit01 ? 8 : 0);
977 io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
978 if (!io)
979 return ENXIO;
980
981 rid = PCIR_BAR(1) + (unit01 ? 8 : 0);
982 ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
983 if (!ctlio) {
984 bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io);
985 return ENXIO;
986 }
987
988 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
989 ch->r_io[i].res = io;
990 ch->r_io[i].offset = i + (unit10 ? 8 : 0);
991 }
992 ch->r_io[ATA_CONTROL].res = ctlio;
993 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0);
994 ch->r_io[ATA_IDX_ADDR].res = io;
995 ata_default_registers(dev);
996 if (ctlr->r_res1) {
997 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
998 ch->r_io[i].res = ctlr->r_res1;
999 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
1000 }
1001 }
1002 ch->flags |= ATA_NO_SLAVE;
1003
1004 /* XXX SOS PHY handling awkward in ALI chip not supported yet */
1005 ata_pci_hw(dev);
1006 return 0;
1007 }
1008
1009 static void
1010 ata_ali_reset(device_t dev)
1011 {
1012 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1013 struct ata_channel *ch = device_get_softc(dev);
1014 device_t *children;
1015 int nchildren, i;
1016
1017 ata_generic_reset(dev);
1018
1019 /*
1020 * workaround for datacorruption bug found on at least SUN Blade-100
1021 * find the ISA function on the southbridge and disable then enable
1022 * the ATA channel tristate buffer
1023 */
1024 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) {
1025 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) {
1026 for (i = 0; i < nchildren; i++) {
1027 if (pci_get_devid(children[i]) == ATA_ALI_1533) {
1028 pci_write_config(children[i], 0x58,
1029 pci_read_config(children[i], 0x58, 1) &
1030 ~(0x04 << ch->unit), 1);
1031 pci_write_config(children[i], 0x58,
1032 pci_read_config(children[i], 0x58, 1) |
1033 (0x04 << ch->unit), 1);
1034 break;
1035 }
1036 }
1037 free(children, M_TEMP);
1038 }
1039 }
1040 }
1041
1042 static void
1043 ata_ali_setmode(device_t dev, int mode)
1044 {
1045 device_t gparent = GRANDPARENT(dev);
1046 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1047 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1048 struct ata_device *atadev = device_get_softc(dev);
1049 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1050 int error;
1051
1052 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1053
1054 if (ctlr->chip->cfg2 & ALINEW) {
1055 if (mode > ATA_UDMA2 &&
1056 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) {
1057 ata_print_cable(dev, "controller");
1058 mode = ATA_UDMA2;
1059 }
1060 }
1061 else
1062 mode = ata_check_80pin(dev, mode);
1063
1064 if (ctlr->chip->cfg2 & ALIOLD) {
1065 /* doesn't support ATAPI DMA on write */
1066 ch->flags |= ATA_ATAPI_DMA_RO;
1067 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) {
1068 /* doesn't support ATAPI DMA on two ATAPI devices */
1069 device_printf(dev, "two atapi devices on this channel, no DMA\n");
1070 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1071 }
1072 }
1073
1074 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1075
1076 if (bootverbose)
1077 device_printf(dev, "%ssetting %s on %s chip\n",
1078 (error) ? "FAILURE " : "",
1079 ata_mode2str(mode), ctlr->chip->text);
1080 if (!error) {
1081 if (mode >= ATA_UDMA0) {
1082 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d};
1083 u_int32_t word54 = pci_read_config(gparent, 0x54, 4);
1084
1085 word54 &= ~(0x000f000f << (devno << 2));
1086 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
1087 pci_write_config(gparent, 0x54, word54, 4);
1088 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1089 0x00310001, 4);
1090 }
1091 else {
1092 u_int32_t piotimings[] =
1093 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
1094 0x00310001, 0x00440001, 0x00330001, 0x00310001};
1095
1096 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) &
1097 ~(0x0008000f << (devno << 2)), 4);
1098 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1099 piotimings[ata_mode2idx(mode)], 4);
1100 }
1101 atadev->mode = mode;
1102 }
1103 }
1104
1105
1106 /*
1107 * American Micro Devices (AMD) chipset support functions
1108 */
1109 int
1110 ata_amd_ident(device_t dev)
1111 {
1112 struct ata_pci_controller *ctlr = device_get_softc(dev);
1113 struct ata_chip_id *idx;
1114 static struct ata_chip_id ids[] =
1115 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "756" },
1116 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "766" },
1117 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "768" },
1118 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "8111" },
1119 { 0, 0, 0, 0, 0, 0}};
1120 char buffer[64];
1121
1122 if (!(idx = ata_match_chip(dev, ids)))
1123 return ENXIO;
1124
1125 sprintf(buffer, "AMD %s %s controller",
1126 idx->text, ata_mode2str(idx->max_dma));
1127 device_set_desc_copy(dev, buffer);
1128 ctlr->chip = idx;
1129 ctlr->chipinit = ata_amd_chipinit;
1130 return 0;
1131 }
1132
1133 static int
1134 ata_amd_chipinit(device_t dev)
1135 {
1136 struct ata_pci_controller *ctlr = device_get_softc(dev);
1137
1138 if (ata_setup_interrupt(dev))
1139 return ENXIO;
1140
1141 /* disable/set prefetch, postwrite */
1142 if (ctlr->chip->cfg2 & AMDBUG)
1143 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1);
1144 else
1145 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
1146
1147 ctlr->setmode = ata_via_family_setmode;
1148 return 0;
1149 }
1150
1151
1152 /*
1153 * ATI chipset support functions
1154 */
1155 int
1156 ata_ati_ident(device_t dev)
1157 {
1158 struct ata_pci_controller *ctlr = device_get_softc(dev);
1159 struct ata_chip_id *idx;
1160 static struct ata_chip_id ids[] =
1161 {{ ATA_ATI_IXP200, 0x00, 0, 0, ATA_UDMA5, "IXP200" },
1162 { ATA_ATI_IXP300, 0x00, 0, 0, ATA_UDMA6, "IXP300" },
1163 { ATA_ATI_IXP400, 0x00, 0, 0, ATA_UDMA6, "IXP400" },
1164 { ATA_ATI_IXP300_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP300" },
1165 { ATA_ATI_IXP400_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" },
1166 { ATA_ATI_IXP400_S2, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" },
1167 { 0, 0, 0, 0, 0, 0}};
1168 char buffer[64];
1169
1170 if (!(idx = ata_match_chip(dev, ids)))
1171 return ENXIO;
1172
1173 sprintf(buffer, "ATI %s %s controller",
1174 idx->text, ata_mode2str(idx->max_dma));
1175 device_set_desc_copy(dev, buffer);
1176 ctlr->chip = idx;
1177
1178 /* the ATI SATA controller is actually a SiI 3112 controller*/
1179 if (ctlr->chip->cfg1 & SIIMEMIO)
1180 ctlr->chipinit = ata_sii_chipinit;
1181 else
1182 ctlr->chipinit = ata_ati_chipinit;
1183 return 0;
1184 }
1185
1186 static int
1187 ata_ati_chipinit(device_t dev)
1188 {
1189 struct ata_pci_controller *ctlr = device_get_softc(dev);
1190
1191 if (ata_setup_interrupt(dev))
1192 return ENXIO;
1193
1194 ctlr->setmode = ata_ati_setmode;
1195 return 0;
1196 }
1197
1198 static void
1199 ata_ati_setmode(device_t dev, int mode)
1200 {
1201 device_t gparent = GRANDPARENT(dev);
1202 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1203 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1204 struct ata_device *atadev = device_get_softc(dev);
1205 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1206 int offset = (devno ^ 0x01) << 3;
1207 int error;
1208 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1209 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1210 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
1211
1212 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1213
1214 mode = ata_check_80pin(dev, mode);
1215
1216 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1217
1218 if (bootverbose)
1219 device_printf(dev, "%ssetting %s on %s chip\n",
1220 (error) ? "FAILURE " : "",
1221 ata_mode2str(mode), ctlr->chip->text);
1222 if (!error) {
1223 if (mode >= ATA_UDMA0) {
1224 pci_write_config(gparent, 0x56,
1225 (pci_read_config(gparent, 0x56, 2) &
1226 ~(0xf << (devno << 2))) |
1227 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
1228 pci_write_config(gparent, 0x54,
1229 pci_read_config(gparent, 0x54, 1) |
1230 (0x01 << devno), 1);
1231 pci_write_config(gparent, 0x44,
1232 (pci_read_config(gparent, 0x44, 4) &
1233 ~(0xff << offset)) |
1234 (dmatimings[2] << offset), 4);
1235 }
1236 else if (mode >= ATA_WDMA0) {
1237 pci_write_config(gparent, 0x54,
1238 pci_read_config(gparent, 0x54, 1) &
1239 ~(0x01 << devno), 1);
1240 pci_write_config(gparent, 0x44,
1241 (pci_read_config(gparent, 0x44, 4) &
1242 ~(0xff << offset)) |
1243 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
1244 }
1245 else
1246 pci_write_config(gparent, 0x54,
1247 pci_read_config(gparent, 0x54, 1) &
1248 ~(0x01 << devno), 1);
1249
1250 pci_write_config(gparent, 0x4a,
1251 (pci_read_config(gparent, 0x4a, 2) &
1252 ~(0xf << (devno << 2))) |
1253 (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2);
1254 pci_write_config(gparent, 0x40,
1255 (pci_read_config(gparent, 0x40, 4) &
1256 ~(0xff << offset)) |
1257 (piotimings[ata_mode2idx(mode)] << offset), 4);
1258 atadev->mode = mode;
1259 }
1260 }
1261
1262 /*
1263 * Cyrix chipset support functions
1264 */
1265 int
1266 ata_cyrix_ident(device_t dev)
1267 {
1268 struct ata_pci_controller *ctlr = device_get_softc(dev);
1269
1270 if (pci_get_devid(dev) == ATA_CYRIX_5530) {
1271 device_set_desc(dev, "Cyrix 5530 ATA33 controller");
1272 ctlr->chipinit = ata_cyrix_chipinit;
1273 return 0;
1274 }
1275 return ENXIO;
1276 }
1277
1278 static int
1279 ata_cyrix_chipinit(device_t dev)
1280 {
1281 struct ata_pci_controller *ctlr = device_get_softc(dev);
1282
1283 if (ata_setup_interrupt(dev))
1284 return ENXIO;
1285
1286 if (ctlr->r_res1)
1287 ctlr->setmode = ata_cyrix_setmode;
1288 else
1289 ctlr->setmode = ata_generic_setmode;
1290 return 0;
1291 }
1292
1293 static void
1294 ata_cyrix_setmode(device_t dev, int mode)
1295 {
1296 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1297 struct ata_device *atadev = device_get_softc(dev);
1298 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1299 u_int32_t piotiming[] =
1300 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
1301 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
1302 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
1303 int error;
1304
1305 ch->dma->alignment = 16;
1306 ch->dma->max_iosize = 126 * DEV_BSIZE;
1307
1308 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
1309
1310 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1311
1312 if (bootverbose)
1313 device_printf(dev, "%ssetting %s on Cyrix chip\n",
1314 (error) ? "FAILURE " : "", ata_mode2str(mode));
1315 if (!error) {
1316 if (mode >= ATA_UDMA0) {
1317 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1318 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]);
1319 }
1320 else if (mode >= ATA_WDMA0) {
1321 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1322 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]);
1323 }
1324 else {
1325 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1326 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]);
1327 }
1328 atadev->mode = mode;
1329 }
1330 }
1331
1332
1333 /*
1334 * Cypress chipset support functions
1335 */
1336 int
1337 ata_cypress_ident(device_t dev)
1338 {
1339 struct ata_pci_controller *ctlr = device_get_softc(dev);
1340
1341 /*
1342 * the Cypress chip is a mess, it contains two ATA functions, but
1343 * both channels are visible on the first one.
1344 * simply ignore the second function for now, as the right
1345 * solution (ignoring the second channel on the first function)
1346 * doesn't work with the crappy ATA interrupt setup on the alpha.
1347 */
1348 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 &&
1349 pci_get_function(dev) == 1 &&
1350 pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
1351 device_set_desc(dev, "Cypress 82C693 ATA controller");
1352 ctlr->chipinit = ata_cypress_chipinit;
1353 return 0;
1354 }
1355 return ENXIO;
1356 }
1357
1358 static int
1359 ata_cypress_chipinit(device_t dev)
1360 {
1361 struct ata_pci_controller *ctlr = device_get_softc(dev);
1362
1363 if (ata_setup_interrupt(dev))
1364 return ENXIO;
1365
1366 ctlr->setmode = ata_cypress_setmode;
1367 return 0;
1368 }
1369
1370 static void
1371 ata_cypress_setmode(device_t dev, int mode)
1372 {
1373 device_t gparent = GRANDPARENT(dev);
1374 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1375 struct ata_device *atadev = device_get_softc(dev);
1376 int error;
1377
1378 mode = ata_limit_mode(dev, mode, ATA_WDMA2);
1379
1380 /* XXX SOS missing WDMA0+1 + PIO modes */
1381 if (mode == ATA_WDMA2) {
1382 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1383 if (bootverbose)
1384 device_printf(dev, "%ssetting WDMA2 on Cypress chip\n",
1385 error ? "FAILURE " : "");
1386 if (!error) {
1387 pci_write_config(gparent, ch->unit ? 0x4e : 0x4c, 0x2020, 2);
1388 atadev->mode = mode;
1389 return;
1390 }
1391 }
1392 /* we could set PIO mode timings, but we assume the BIOS did that */
1393 }
1394
1395
1396 /*
1397 * HighPoint chipset support functions
1398 */
1399 int
1400 ata_highpoint_ident(device_t dev)
1401 {
1402 struct ata_pci_controller *ctlr = device_get_softc(dev);
1403 struct ata_chip_id *idx;
1404 static struct ata_chip_id ids[] =
1405 {{ ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HPT374" },
1406 { ATA_HPT372, 0x02, HPT372, 0x00, ATA_UDMA6, "HPT372N" },
1407 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1408 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT371" },
1409 { ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1410 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HPT370" },
1411 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HPT368" },
1412 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HPT366" },
1413 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT302" },
1414 { 0, 0, 0, 0, 0, 0}};
1415 char buffer[64];
1416
1417 if (!(idx = ata_match_chip(dev, ids)))
1418 return ENXIO;
1419
1420 strcpy(buffer, idx->text);
1421 if (idx->cfg1 == HPT374) {
1422 if (pci_get_function(dev) == 0)
1423 strcat(buffer, " (channel 0+1)");
1424 else if (pci_get_function(dev) == 1)
1425 strcat(buffer, " (channel 2+3)");
1426 }
1427 sprintf(buffer, "HighPoint %s %s controller",
1428 buffer, ata_mode2str(idx->max_dma));
1429 device_set_desc_copy(dev, buffer);
1430 ctlr->chip = idx;
1431 ctlr->chipinit = ata_highpoint_chipinit;
1432 return 0;
1433 }
1434
1435 static int
1436 ata_highpoint_chipinit(device_t dev)
1437 {
1438 struct ata_pci_controller *ctlr = device_get_softc(dev);
1439
1440 if (ata_setup_interrupt(dev))
1441 return ENXIO;
1442
1443 if (ctlr->chip->cfg2 == HPTOLD) {
1444 /* disable interrupt prediction */
1445 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
1446 }
1447 else {
1448 /* disable interrupt prediction */
1449 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
1450 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
1451
1452 /* enable interrupts */
1453 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
1454
1455 /* set clocks etc */
1456 if (ctlr->chip->cfg1 < HPT372)
1457 pci_write_config(dev, 0x5b, 0x22, 1);
1458 else
1459 pci_write_config(dev, 0x5b,
1460 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
1461 }
1462 ctlr->allocate = ata_highpoint_allocate;
1463 ctlr->setmode = ata_highpoint_setmode;
1464 return 0;
1465 }
1466
1467 static int
1468 ata_highpoint_allocate(device_t dev)
1469 {
1470 struct ata_channel *ch = device_get_softc(dev);
1471
1472 /* setup the usual register normal pci style */
1473 if (ata_pci_allocate(dev))
1474 return ENXIO;
1475
1476 ch->flags |= ATA_ALWAYS_DMASTAT;
1477 return 0;
1478 }
1479
1480 static void
1481 ata_highpoint_setmode(device_t dev, int mode)
1482 {
1483 device_t gparent = GRANDPARENT(dev);
1484 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1485 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1486 struct ata_device *atadev = device_get_softc(dev);
1487 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1488 int error;
1489 u_int32_t timings33[][4] = {
1490 /* HPT366 HPT370 HPT372 HPT374 mode */
1491 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
1492 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
1493 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
1494 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
1495 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
1496 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
1497 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
1498 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
1499 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */
1500 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */
1501 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */
1502 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */
1503 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */
1504 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */
1505 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */
1506 };
1507
1508 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1509
1510 if (ctlr->chip->cfg1 == HPT366 && ata_atapi(dev))
1511 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1512
1513 mode = ata_highpoint_check_80pin(dev, mode);
1514
1515 /*
1516 * most if not all HPT chips cant really handle that the device is
1517 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to
1518 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance
1519 */
1520 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
1521 ata_limit_mode(dev, mode, ATA_UDMA5));
1522 if (bootverbose)
1523 device_printf(dev, "%ssetting %s on HighPoint chip\n",
1524 (error) ? "FAILURE " : "", ata_mode2str(mode));
1525 if (!error)
1526 pci_write_config(gparent, 0x40 + (devno << 2),
1527 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
1528 atadev->mode = mode;
1529 }
1530
1531 static int
1532 ata_highpoint_check_80pin(device_t dev, int mode)
1533 {
1534 device_t gparent = GRANDPARENT(dev);
1535 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1536 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1537 u_int8_t reg, val, res;
1538
1539 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(gparent) == 1) {
1540 reg = ch->unit ? 0x57 : 0x53;
1541 val = pci_read_config(gparent, reg, 1);
1542 pci_write_config(gparent, reg, val | 0x80, 1);
1543 }
1544 else {
1545 reg = 0x5b;
1546 val = pci_read_config(gparent, reg, 1);
1547 pci_write_config(gparent, reg, val & 0xfe, 1);
1548 }
1549 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2);
1550 pci_write_config(gparent, reg, val, 1);
1551
1552 if (mode > ATA_UDMA2 && res) {
1553 ata_print_cable(dev, "controller");
1554 mode = ATA_UDMA2;
1555 }
1556 return mode;
1557 }
1558
1559
1560 /*
1561 * Intel chipset support functions
1562 */
1563 int
1564 ata_intel_ident(device_t dev)
1565 {
1566 struct ata_pci_controller *ctlr = device_get_softc(dev);
1567 struct ata_chip_id *idx;
1568 static struct ata_chip_id ids[] =
1569 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "PIIX" },
1570 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "PIIX3" },
1571 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1572 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1573 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1574 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "ICH0" },
1575 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "ICH" },
1576 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "ICH" },
1577 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "ICH2" },
1578 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "ICH2" },
1579 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "ICH3" },
1580 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "ICH3" },
1581 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "ICH4" },
1582 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "ICH4" },
1583 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "ICH5" },
1584 { ATA_I82801EB_S1, 0, 0, 0x00, ATA_SA150, "ICH5" },
1585 { ATA_I82801EB_R1, 0, 0, 0x00, ATA_SA150, "ICH5" },
1586 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "6300ESB" },
1587 { ATA_I6300ESB_S1, 0, 0, 0x00, ATA_SA150, "6300ESB" },
1588 { ATA_I6300ESB_R1, 0, 0, 0x00, ATA_SA150, "6300ESB" },
1589 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "ICH6" },
1590 { ATA_I82801FB_S1, 0, AHCI, 0x00, ATA_SA150, "ICH6" },
1591 { ATA_I82801FB_R1, 0, AHCI, 0x00, ATA_SA150, "ICH6" },
1592 { ATA_I82801FB_M, 0, AHCI, 0x00, ATA_SA150, "ICH6" },
1593 { ATA_I82801GB, 0, 0, 0x00, ATA_UDMA5, "ICH7" },
1594 { ATA_I82801GB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1595 { ATA_I82801GB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1596 { ATA_I82801GB_M, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1597 { ATA_I82801GB_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1598 { ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" },
1599 { 0, 0, 0, 0, 0, 0}};
1600 char buffer[64];
1601
1602 if (!(idx = ata_match_chip(dev, ids)))
1603 return ENXIO;
1604
1605 sprintf(buffer, "Intel %s %s controller",
1606 idx->text, ata_mode2str(idx->max_dma));
1607 device_set_desc_copy(dev, buffer);
1608 ctlr->chip = idx;
1609 ctlr->chipinit = ata_intel_chipinit;
1610 return 0;
1611 }
1612
1613 static int
1614 ata_intel_chipinit(device_t dev)
1615 {
1616 struct ata_pci_controller *ctlr = device_get_softc(dev);
1617
1618 if (ata_setup_interrupt(dev))
1619 return ENXIO;
1620
1621 /* good old PIIX needs special treatment (not implemented) */
1622 if (ctlr->chip->chipid == ATA_I82371FB) {
1623 ctlr->setmode = ata_intel_old_setmode;
1624 }
1625
1626 /* the intel 31244 needs special care if in DPA mode */
1627 else if (ctlr->chip->chipid == ATA_I31244) {
1628 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) {
1629 ctlr->r_type2 = SYS_RES_MEMORY;
1630 ctlr->r_rid2 = PCIR_BAR(0);
1631 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1632 &ctlr->r_rid2,
1633 RF_ACTIVE)))
1634 return ENXIO;
1635 ctlr->channels = 4;
1636 ctlr->allocate = ata_intel_31244_allocate;
1637 ctlr->reset = ata_intel_31244_reset;
1638 }
1639 ctlr->setmode = ata_sata_setmode;
1640 }
1641
1642 /* non SATA intel chips goes here */
1643 else if (ctlr->chip->max_dma < ATA_SA150) {
1644 ctlr->allocate = ata_intel_allocate;
1645 ctlr->setmode = ata_intel_new_setmode;
1646 }
1647
1648 /* SATA parts can be either compat or AHCI */
1649 else {
1650 /* force all ports active "the legacy way" */
1651 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f,2);
1652
1653 ctlr->allocate = ata_intel_allocate;
1654 ctlr->reset = ata_intel_reset;
1655
1656 /* if we have AHCI capability and BAR(5) as a memory resource */
1657 if (ctlr->chip->cfg1 == AHCI) {
1658 ctlr->r_type2 = SYS_RES_MEMORY;
1659 ctlr->r_rid2 = PCIR_BAR(5);
1660 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1661 &ctlr->r_rid2,
1662 RF_ACTIVE))) {
1663 /* is AHCI or RAID mode enabled in BIOS ? */
1664 if (pci_read_config(dev, 0x90, 1) & 0xc0) {
1665
1666 /* reset AHCI controller */
1667 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
1668 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_HR);
1669 DELAY(1000000);
1670 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) {
1671 bus_release_resource(dev, ctlr->r_type2,
1672 ctlr->r_rid2, ctlr->r_res2);
1673 device_printf(dev, "AHCI controller reset failure\n");
1674 return ENXIO;
1675 }
1676
1677 /* enable AHCI mode */
1678 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
1679
1680 /* get the number of HW channels */
1681 ctlr->channels = (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) &
1682 ATA_AHCI_NPMASK) + 1;
1683
1684 /* enable AHCI interrupts */
1685 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
1686 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) |
1687 ATA_AHCI_GHC_IE);
1688 ctlr->allocate = ata_ahci_allocate;
1689 ctlr->reset = ata_ahci_reset;
1690 ctlr->dmainit = ata_ahci_dmainit;
1691 }
1692 }
1693 }
1694 ctlr->setmode = ata_sata_setmode;
1695
1696 /* enable PCI interrupt */
1697 pci_write_config(dev, PCIR_COMMAND,
1698 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
1699 }
1700 return 0;
1701 }
1702
1703 static int
1704 ata_intel_allocate(device_t dev)
1705 {
1706 struct ata_channel *ch = device_get_softc(dev);
1707
1708 /* setup the usual register normal pci style */
1709 if (ata_pci_allocate(dev))
1710 return ENXIO;
1711
1712 ch->flags |= ATA_ALWAYS_DMASTAT;
1713 return 0;
1714 }
1715
1716 static void
1717 ata_intel_reset(device_t dev)
1718 {
1719 device_t parent = device_get_parent(dev);
1720 struct ata_pci_controller *ctlr = device_get_softc(parent);
1721 struct ata_channel *ch = device_get_softc(dev);
1722 int mask, timeout;
1723
1724 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */
1725 if (ctlr->chip->cfg1) {
1726 mask = (0x0005 << ch->unit);
1727 }
1728 else {
1729 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */
1730 if (pci_read_config(parent, 0x90, 1) & 0x04)
1731 mask = 0x0003;
1732 else {
1733 mask = (0x0001 << ch->unit);
1734 /* XXX SOS should be in intel_allocate if we grow it */
1735 ch->flags |= ATA_NO_SLAVE;
1736 }
1737 }
1738 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2);
1739 DELAY(10);
1740 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2);
1741
1742 /* wait up to 1 sec for "connect well" */
1743 for (timeout = 0; timeout < 100 ; timeout++) {
1744 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) &&
1745 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff))
1746 break;
1747 ata_udelay(10000);
1748 }
1749 ata_generic_reset(dev);
1750 }
1751
1752 static void
1753 ata_intel_old_setmode(device_t dev, int mode)
1754 {
1755 /* NOT YET */
1756 }
1757
1758 static void
1759 ata_intel_new_setmode(device_t dev, int mode)
1760 {
1761 device_t gparent = GRANDPARENT(dev);
1762 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1763 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1764 struct ata_device *atadev = device_get_softc(dev);
1765 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1766 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4);
1767 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1);
1768 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1);
1769 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2);
1770 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2);
1771 u_int32_t mask40 = 0, new40 = 0;
1772 u_int8_t mask44 = 0, new44 = 0;
1773 int error;
1774 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
1775 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
1776
1777 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1778
1779 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
1780 ata_print_cable(dev, "controller");
1781 mode = ATA_UDMA2;
1782 }
1783
1784 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1785
1786 if (bootverbose)
1787 device_printf(dev, "%ssetting %s on %s chip\n",
1788 (error) ? "FAILURE " : "",
1789 ata_mode2str(mode), ctlr->chip->text);
1790 if (error)
1791 return;
1792
1793 if (mode >= ATA_UDMA0) {
1794 pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2);
1795 pci_write_config(gparent, 0x4a,
1796 (reg4a & ~(0x3 << (devno << 2))) |
1797 ((0x01 + !(mode & 0x01)) << (devno << 2)), 2);
1798 }
1799 else {
1800 pci_write_config(gparent, 0x48, reg48 & ~(0x0001 << devno), 2);
1801 pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))), 2);
1802 }
1803 reg54 |= 0x0400;
1804 if (mode >= ATA_UDMA2)
1805 pci_write_config(gparent, 0x54, reg54 | (0x1 << devno), 2);
1806 else
1807 pci_write_config(gparent, 0x54, reg54 & ~(0x1 << devno), 2);
1808
1809 if (mode >= ATA_UDMA5)
1810 pci_write_config(gparent, 0x54, reg54 | (0x1000 << devno), 2);
1811 else
1812 pci_write_config(gparent, 0x54, reg54 & ~(0x1000 << devno), 2);
1813
1814 reg40 &= ~0x00ff00ff;
1815 reg40 |= 0x40774077;
1816
1817 if (atadev->unit == ATA_MASTER) {
1818 mask40 = 0x3300;
1819 new40 = timings[ata_mode2idx(mode)] << 8;
1820 }
1821 else {
1822 mask44 = 0x0f;
1823 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
1824 (timings[ata_mode2idx(mode)] & 0x03);
1825 }
1826 if (ch->unit) {
1827 mask40 <<= 16;
1828 new40 <<= 16;
1829 mask44 <<= 4;
1830 new44 <<= 4;
1831 }
1832 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4);
1833 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1);
1834
1835 atadev->mode = mode;
1836 }
1837
1838 static int
1839 ata_intel_31244_allocate(device_t dev)
1840 {
1841 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1842 struct ata_channel *ch = device_get_softc(dev);
1843 int i;
1844 int ch_offset;
1845
1846 ch_offset = 0x200 + ch->unit * 0x200;
1847
1848 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
1849 ch->r_io[i].res = ctlr->r_res2;
1850 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
1851 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06;
1852 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
1853 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
1854 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
1855 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
1856 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
1857 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d;
1858 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04;
1859 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c;
1860 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28;
1861 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29;
1862 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100;
1863 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104;
1864 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108;
1865 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70;
1866 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72;
1867 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74;
1868
1869 ch->flags |= ATA_NO_SLAVE;
1870 ata_pci_hw(dev);
1871 ch->hw.status = ata_intel_31244_status;
1872 ch->hw.command = ata_intel_31244_command;
1873
1874 /* enable PHY state change interrupt */
1875 ATA_OUTL(ctlr->r_res2, 0x4,
1876 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3)));
1877 return 0;
1878 }
1879
1880 static int
1881 ata_intel_31244_status(device_t dev)
1882 {
1883 struct ata_channel *ch = device_get_softc(dev);
1884 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS);
1885 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR);
1886 struct ata_connect_task *tp;
1887
1888 /* check for PHY related interrupts on SATA capable HW */
1889 if (error) {
1890 /* clear error bits/interrupt */
1891 ATA_IDX_OUTL(ch, ATA_SERROR, error);
1892
1893 /* if we have a connection event deal with it */
1894 if ((error & ATA_SE_PHY_CHANGED) &&
1895 (tp = (struct ata_connect_task *)
1896 malloc(sizeof(struct ata_connect_task),
1897 M_ATA, M_NOWAIT | M_ZERO))) {
1898
1899 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) {
1900 if (bootverbose)
1901 device_printf(ch->dev, "CONNECT requested\n");
1902 tp->action = ATA_C_ATTACH;
1903 }
1904 else {
1905 if (bootverbose)
1906 device_printf(ch->dev, "DISCONNECT requested\n");
1907 tp->action = ATA_C_DETACH;
1908 }
1909 tp->dev = ch->dev;
1910 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
1911 taskqueue_enqueue(taskqueue_thread, &tp->task);
1912 }
1913 }
1914
1915 /* any drive action to take care of ? */
1916 return ata_pci_status(dev);
1917 }
1918
1919 static int
1920 ata_intel_31244_command(struct ata_request *request)
1921 {
1922 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
1923 struct ata_device *atadev = device_get_softc(request->dev);
1924 u_int64_t lba;
1925
1926 if (!(atadev->flags & ATA_D_48BIT_ACTIVE))
1927 return (ata_generic_command(request));
1928
1929 lba = request->u.ata.lba;
1930 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit);
1931 /* enable interrupt */
1932 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
1933 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
1934 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
1935 ATA_IDX_OUTW(ch, ATA_SECTOR, ((lba >> 16) & 0xff00) | (lba & 0x00ff));
1936 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((lba >> 24) & 0xff00) |
1937 ((lba >> 8) & 0x00ff));
1938 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((lba >> 32) & 0xff00) |
1939 ((lba >> 16) & 0x00ff));
1940
1941 /* issue command to controller */
1942 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command);
1943
1944 return 0;
1945 }
1946
1947 static void
1948 ata_intel_31244_reset(device_t dev)
1949 {
1950 struct ata_channel *ch = device_get_softc(dev);
1951
1952 ata_sata_phy_enable(ch);
1953 }
1954
1955
1956 /*
1957 * Integrated Technology Express Inc. (ITE) chipset support functions
1958 */
1959 int
1960 ata_ite_ident(device_t dev)
1961 {
1962 struct ata_pci_controller *ctlr = device_get_softc(dev);
1963 struct ata_chip_id *idx;
1964 static struct ata_chip_id ids[] =
1965 {{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" },
1966 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" },
1967 { 0, 0, 0, 0, 0, 0}};
1968 char buffer[64];
1969
1970 if (!(idx = ata_match_chip(dev, ids)))
1971 return ENXIO;
1972
1973 sprintf(buffer, "ITE %s %s controller",
1974 idx->text, ata_mode2str(idx->max_dma));
1975 device_set_desc_copy(dev, buffer);
1976 ctlr->chip = idx;
1977 ctlr->chipinit = ata_ite_chipinit;
1978 return 0;
1979 }
1980
1981 static int
1982 ata_ite_chipinit(device_t dev)
1983 {
1984 struct ata_pci_controller *ctlr = device_get_softc(dev);
1985
1986 if (ata_setup_interrupt(dev))
1987 return ENXIO;
1988
1989 ctlr->setmode = ata_ite_setmode;
1990
1991 /* set PCI mode and 66Mhz reference clock */
1992 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1);
1993
1994 /* set default active & recover timings */
1995 pci_write_config(dev, 0x54, 0x31, 1);
1996 pci_write_config(dev, 0x56, 0x31, 1);
1997 return 0;
1998 }
1999
2000 static void
2001 ata_ite_setmode(device_t dev, int mode)
2002 {
2003 device_t gparent = GRANDPARENT(dev);
2004 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2005 struct ata_device *atadev = device_get_softc(dev);
2006 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2007 int error;
2008
2009 /* correct the mode for what the HW supports */
2010 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2011
2012 /* check the CBLID bits for 80 conductor cable detection */
2013 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) &
2014 (ch->unit ? (1<<3) : (1<<2)))) {
2015 ata_print_cable(dev, "controller");
2016 mode = ATA_UDMA2;
2017 }
2018
2019 /* set the wanted mode on the device */
2020 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2021
2022 if (bootverbose)
2023 device_printf(dev, "%s setting %s on ITE8212F chip\n",
2024 (error) ? "failed" : "success", ata_mode2str(mode));
2025
2026 /* if the device accepted the mode change, setup the HW accordingly */
2027 if (!error) {
2028 if (mode >= ATA_UDMA0) {
2029 u_int8_t udmatiming[] =
2030 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
2031
2032 /* enable UDMA mode */
2033 pci_write_config(gparent, 0x50,
2034 pci_read_config(gparent, 0x50, 1) &
2035 ~(1 << (devno + 3)), 1);
2036
2037 /* set UDMA timing */
2038 pci_write_config(gparent,
2039 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit),
2040 udmatiming[mode & ATA_MODE_MASK], 1);
2041 }
2042 else {
2043 u_int8_t chtiming[] =
2044 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
2045
2046 /* disable UDMA mode */
2047 pci_write_config(gparent, 0x50,
2048 pci_read_config(gparent, 0x50, 1) |
2049 (1 << (devno + 3)), 1);
2050
2051 /* set active and recover timing (shared between master & slave) */
2052 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) <
2053 chtiming[ata_mode2idx(mode)])
2054 pci_write_config(gparent, 0x54 + (ch->unit << 2),
2055 chtiming[ata_mode2idx(mode)], 1);
2056 }
2057 atadev->mode = mode;
2058 }
2059 }
2060
2061
2062 /*
2063 * JMicron chipset support functions
2064 */
2065 int
2066 ata_jmicron_ident(device_t dev)
2067 {
2068 struct ata_pci_controller *ctlr = device_get_softc(dev);
2069 struct ata_chip_id *idx;
2070 static struct ata_chip_id ids[] =
2071 {{ ATA_JMB360, 0, 1, 0, ATA_SA300, "JMB360" },
2072 { ATA_JMB361, 0, 1, 1, ATA_SA300, "JMB361" },
2073 { ATA_JMB363, 0, 2, 1, ATA_SA300, "JMB363" },
2074 { ATA_JMB365, 0, 1, 2, ATA_SA300, "JMB365" },
2075 { ATA_JMB366, 0, 2, 2, ATA_SA300, "JMB366" },
2076 { 0, 0, 0, 0, 0, 0}};
2077 char buffer[64];
2078
2079 if (!(idx = ata_match_chip(dev, ids)))
2080 return ENXIO;
2081
2082 sprintf(buffer, "JMicron %s %s controller",
2083 idx->text, ata_mode2str(idx->max_dma));
2084 device_set_desc_copy(dev, buffer);
2085 ctlr->chip = idx;
2086 ctlr->chipinit = ata_jmicron_chipinit;
2087 return 0;
2088 }
2089
2090 static int
2091 ata_jmicron_chipinit(device_t dev)
2092 {
2093 struct ata_pci_controller *ctlr = device_get_softc(dev);
2094
2095 if (ata_setup_interrupt(dev))
2096 return ENXIO;
2097
2098 /* set controller configuration to a setup we support */
2099 pci_write_config(dev, 0x40, 0x80c0a131, 4);
2100 pci_write_config(dev, 0x80, 0x01200000, 4);
2101
2102 ctlr->allocate = ata_jmicron_allocate;
2103 ctlr->reset = ata_jmicron_reset;
2104 ctlr->dmainit = ata_jmicron_dmainit;
2105 ctlr->setmode = ata_jmicron_setmode;
2106
2107 ctlr->r_type2 = SYS_RES_MEMORY;
2108 ctlr->r_rid2 = PCIR_BAR(5);
2109 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
2110 &ctlr->r_rid2, RF_ACTIVE))) {
2111 /* reset AHCI controller */
2112 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
2113 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_HR);
2114 DELAY(1000000);
2115 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) {
2116 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2,ctlr->r_res2);
2117 device_printf(dev, "AHCI controller reset failure\n");
2118 return ENXIO;
2119 }
2120
2121 /* enable AHCI mode */
2122 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
2123 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_AE);
2124
2125 /* clear interrupts */
2126 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS));
2127
2128 /* enable AHCI interrupts */
2129 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
2130 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE);
2131
2132 /* enable PCI interrupt */
2133 pci_write_config(dev, PCIR_COMMAND,
2134 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
2135 }
2136
2137 /* set the number of HW channels */
2138 ctlr->channels = ctlr->chip->cfg1 + ctlr->chip->cfg2;
2139 return 0;
2140 }
2141
2142 static int
2143 ata_jmicron_allocate(device_t dev)
2144 {
2145 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2146 struct ata_channel *ch = device_get_softc(dev);
2147 int error;
2148
2149 if (ch->unit >= ctlr->chip->cfg1) {
2150 ch->unit -= ctlr->chip->cfg1;
2151 error = ata_pci_allocate(dev);
2152 ch->unit += ctlr->chip->cfg1;
2153 }
2154 else
2155 error = ata_ahci_allocate(dev);
2156 return error;
2157 }
2158
2159 static void
2160 ata_jmicron_reset(device_t dev)
2161 {
2162 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2163 struct ata_channel *ch = device_get_softc(dev);
2164
2165 if (ch->unit >= ctlr->chip->cfg1)
2166 ata_generic_reset(dev);
2167 else
2168 ata_ahci_reset(dev);
2169 }
2170
2171 static void
2172 ata_jmicron_dmainit(device_t dev)
2173 {
2174 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2175 struct ata_channel *ch = device_get_softc(dev);
2176
2177 if (ch->unit >= ctlr->chip->cfg1)
2178 ata_pci_dmainit(dev);
2179 else
2180 ata_ahci_dmainit(dev);
2181 }
2182
2183 static void
2184 ata_jmicron_setmode(device_t dev, int mode)
2185 {
2186 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
2187 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2188
2189 if (ch->unit >= ctlr->chip->cfg1) {
2190 struct ata_device *atadev = device_get_softc(dev);
2191
2192 /* check for 80pin cable present */
2193 if (pci_read_config(dev, 0x40, 1) & 0x08)
2194 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
2195 else
2196 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2197
2198 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2199 atadev->mode = mode;
2200 }
2201 else
2202 ata_sata_setmode(dev, mode);
2203 }
2204
2205
2206 /*
2207 * Marvell chipset support functions
2208 */
2209 #define ATA_MV_HOST_BASE(ch) \
2210 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000)
2211 #define ATA_MV_EDMA_BASE(ch) \
2212 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000)
2213
2214 struct ata_marvell_response {
2215 u_int16_t tag;
2216 u_int8_t edma_status;
2217 u_int8_t dev_status;
2218 u_int32_t timestamp;
2219 };
2220
2221 struct ata_marvell_dma_prdentry {
2222 u_int32_t addrlo;
2223 u_int32_t count;
2224 u_int32_t addrhi;
2225 u_int32_t reserved;
2226 };
2227
2228 int
2229 ata_marvell_ident(device_t dev)
2230 {
2231 struct ata_pci_controller *ctlr = device_get_softc(dev);
2232 struct ata_chip_id *idx;
2233 static struct ata_chip_id ids[] =
2234 {{ ATA_M88SX5040, 0, 4, MV5XXX, ATA_SA150, "88SX5040" },
2235 { ATA_M88SX5041, 0, 4, MV5XXX, ATA_SA150, "88SX5041" },
2236 { ATA_M88SX5080, 0, 8, MV5XXX, ATA_SA150, "88SX5080" },
2237 { ATA_M88SX5081, 0, 8, MV5XXX, ATA_SA150, "88SX5081" },
2238 { ATA_M88SX6041, 0, 4, MV6XXX, ATA_SA300, "88SX6041" },
2239 { ATA_M88SX6081, 0, 8, MV6XXX, ATA_SA300, "88SX6081" },
2240 { 0, 0, 0, 0, 0, 0}};
2241 char buffer[64];
2242
2243 if (!(idx = ata_match_chip(dev, ids)))
2244 return ENXIO;
2245
2246 sprintf(buffer, "Marvell %s %s controller",
2247 idx->text, ata_mode2str(idx->max_dma));
2248 device_set_desc_copy(dev, buffer);
2249 ctlr->chip = idx;
2250 ctlr->chipinit = ata_marvell_chipinit;
2251 return 0;
2252 }
2253
2254 static int
2255 ata_marvell_chipinit(device_t dev)
2256 {
2257 struct ata_pci_controller *ctlr = device_get_softc(dev);
2258
2259 if (ata_setup_interrupt(dev))
2260 return ENXIO;
2261
2262 ctlr->r_type1 = SYS_RES_MEMORY;
2263 ctlr->r_rid1 = PCIR_BAR(0);
2264 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
2265 &ctlr->r_rid1, RF_ACTIVE)))
2266 return ENXIO;
2267
2268 /* mask all host controller interrupts */
2269 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000);
2270
2271 /* mask all PCI interrupts */
2272 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000);
2273
2274 ctlr->allocate = ata_marvell_allocate;
2275 ctlr->reset = ata_marvell_reset;
2276 ctlr->dmainit = ata_marvell_dmainit;
2277 ctlr->setmode = ata_sata_setmode;
2278 ctlr->channels = ctlr->chip->cfg1;
2279
2280 /* clear host controller interrupts */
2281 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000);
2282 if (ctlr->chip->cfg1 > 4)
2283 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000);
2284
2285 /* clear PCI interrupts */
2286 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000);
2287
2288 /* unmask PCI interrupts we want */
2289 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff);
2290
2291 /* unmask host controller interrupts we want */
2292 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ |
2293 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25));
2294
2295 /* enable PCI interrupt */
2296 pci_write_config(dev, PCIR_COMMAND,
2297 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
2298 return 0;
2299 }
2300
2301 static int
2302 ata_marvell_allocate(device_t dev)
2303 {
2304 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2305 struct ata_channel *ch = device_get_softc(dev);
2306 bus_addr_t wordp = ch->dma->work_bus;
2307 int i;
2308
2309 /* set legacy ATA resources */
2310 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
2311 ch->r_io[i].res = ctlr->r_res1;
2312 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch);
2313 }
2314 ch->r_io[ATA_CONTROL].res = ctlr->r_res1;
2315 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch);
2316 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1;
2317 ata_default_registers(dev);
2318
2319 /* set SATA resources */
2320 switch (ctlr->chip->cfg2) {
2321 case MV5XXX:
2322 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2323 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch);
2324 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2325 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch);
2326 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2327 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch);
2328 break;
2329 case MV6XXX:
2330 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2331 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch);
2332 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2333 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch);
2334 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2335 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch);
2336 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1;
2337 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch);
2338 break;
2339 }
2340
2341 ch->flags |= ATA_NO_SLAVE;
2342 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */
2343 ata_generic_hw(dev);
2344 ch->hw.begin_transaction = ata_marvell_begin_transaction;
2345 ch->hw.end_transaction = ata_marvell_end_transaction;
2346 ch->hw.status = ata_marvell_status;
2347
2348 /* disable the EDMA machinery */
2349 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2350 DELAY(100000); /* SOS should poll for disabled */
2351
2352 /* set configuration to non-queued 128b read transfers stop on error */
2353 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13));
2354
2355 /* request queue base high */
2356 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), (wordp >> 16) >> 16);
2357
2358 /* request queue in ptr */
2359 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), wordp & 0xffffffff);
2360
2361 /* request queue out ptr */
2362 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0);
2363
2364 /* response queue base high */
2365 wordp += 1024;
2366 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), (wordp >> 16) >> 16);
2367
2368 /* response queue in ptr */
2369 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0);
2370
2371 /* response queue out ptr */
2372 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), wordp & 0xffffffff);
2373
2374 /* clear SATA error register */
2375 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2376
2377 /* clear any outstanding error interrupts */
2378 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2379
2380 /* unmask all error interrupts */
2381 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
2382
2383 /* enable EDMA machinery */
2384 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2385 return 0;
2386 }
2387
2388 static int
2389 ata_marvell_status(device_t dev)
2390 {
2391 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2392 struct ata_channel *ch = device_get_softc(dev);
2393 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60);
2394 int shift = (ch->unit << 1) + (ch->unit > 3);
2395
2396 /* do we have any errors flagged ? */
2397 if (cause & (1 << shift)) {
2398 struct ata_connect_task *tp;
2399 u_int32_t error =
2400 ATA_INL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch));
2401
2402 /* check for and handle disconnect events */
2403 if ((error & 0x00000008) &&
2404 (tp = (struct ata_connect_task *)
2405 malloc(sizeof(struct ata_connect_task),
2406 M_ATA, M_NOWAIT | M_ZERO))) {
2407
2408 if (bootverbose)
2409 device_printf(ch->dev, "DISCONNECT requested\n");
2410 tp->action = ATA_C_DETACH;
2411 tp->dev = ch->dev;
2412 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
2413 taskqueue_enqueue(taskqueue_thread, &tp->task);
2414 }
2415
2416 /* check for and handle connect events */
2417 if ((error & 0x00000010) &&
2418 (tp = (struct ata_connect_task *)
2419 malloc(sizeof(struct ata_connect_task),
2420 M_ATA, M_NOWAIT | M_ZERO))) {
2421
2422 if (bootverbose)
2423 device_printf(ch->dev, "CONNECT requested\n");
2424 tp->action = ATA_C_ATTACH;
2425 tp->dev = ch->dev;
2426 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
2427 taskqueue_enqueue(taskqueue_thread, &tp->task);
2428 }
2429
2430 /* clear SATA error register */
2431 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2432
2433 /* clear any outstanding error interrupts */
2434 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2435 }
2436
2437 /* do we have any device action ? */
2438 return (cause & (2 << shift));
2439 }
2440
2441 /* must be called with ATA channel locked and state_mtx held */
2442 static int
2443 ata_marvell_begin_transaction(struct ata_request *request)
2444 {
2445 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2446 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2447 u_int32_t req_in;
2448 u_int8_t *bytep;
2449 u_int16_t *wordp;
2450 u_int32_t *quadp;
2451 int i, tag = 0x07;
2452 int dummy, error, slot;
2453
2454 /* only DMA R/W goes through the EMDA machine */
2455 if (request->u.ata.command != ATA_READ_DMA &&
2456 request->u.ata.command != ATA_WRITE_DMA) {
2457
2458 /* disable the EDMA machinery */
2459 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)
2460 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2461 return ata_begin_transaction(request);
2462 }
2463
2464 /* check for 48 bit access and convert if needed */
2465 ata_modify_if_48bit(request);
2466
2467 /* check sanity, setup SG list and DMA engine */
2468 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
2469 request->flags & ATA_R_READ, ch->dma->sg,
2470 &dummy))) {
2471 device_printf(request->dev, "setting up DMA failed\n");
2472 request->result = error;
2473 return ATA_OP_FINISHED;
2474 }
2475
2476 /* get next free request queue slot */
2477 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch));
2478 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f;
2479 bytep = (u_int8_t *)(ch->dma->work);
2480 bytep += (slot << 5);
2481 wordp = (u_int16_t *)bytep;
2482 quadp = (u_int32_t *)bytep;
2483
2484 /* fill in this request */
2485 quadp[0] = (long)ch->dma->sg_bus & 0xffffffff;
2486 quadp[1] = (ch->dma->sg_bus & 0xffffffff00000000) >> 32;
2487 wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1);
2488
2489 i = 10;
2490 bytep[i++] = (request->u.ata.count >> 8) & 0xff;
2491 bytep[i++] = 0x10 | ATA_COUNT;
2492 bytep[i++] = request->u.ata.count & 0xff;
2493 bytep[i++] = 0x10 | ATA_COUNT;
2494
2495 bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
2496 bytep[i++] = 0x10 | ATA_SECTOR;
2497 bytep[i++] = request->u.ata.lba & 0xff;
2498 bytep[i++] = 0x10 | ATA_SECTOR;
2499
2500 bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
2501 bytep[i++] = 0x10 | ATA_CYL_LSB;
2502 bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
2503 bytep[i++] = 0x10 | ATA_CYL_LSB;
2504
2505 bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
2506 bytep[i++] = 0x10 | ATA_CYL_MSB;
2507 bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
2508 bytep[i++] = 0x10 | ATA_CYL_MSB;
2509
2510 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf);
2511 bytep[i++] = 0x10 | ATA_DRIVE;
2512
2513 bytep[i++] = request->u.ata.command;
2514 bytep[i++] = 0x90 | ATA_COMMAND;
2515
2516 /* enable EDMA machinery if needed */
2517 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) {
2518 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2519 while (!(ATA_INL(ctlr->r_res1,
2520 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
2521 DELAY(10);
2522 }
2523
2524 /* tell EDMA it has a new request */
2525 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f;
2526 req_in &= 0xfffffc00;
2527 req_in += (slot << 5);
2528 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in);
2529
2530 return ATA_OP_CONTINUES;
2531 }
2532
2533 /* must be called with ATA channel locked and state_mtx held */
2534 static int
2535 ata_marvell_end_transaction(struct ata_request *request)
2536 {
2537 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2538 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2539 int offset = (ch->unit > 3 ? 0x30014 : 0x20014);
2540 u_int32_t icr = ATA_INL(ctlr->r_res1, offset);
2541 int res;
2542
2543 /* EDMA interrupt */
2544 if ((icr & (0x0001 << (ch->unit & 3)))) {
2545 struct ata_marvell_response *response;
2546 u_int32_t rsp_in, rsp_out;
2547 int slot;
2548
2549 /* unload SG list */
2550 ch->dma->unload(ch->dev);
2551
2552 /* stop timeout */
2553 callout_stop(&request->callout);
2554
2555 /* get response ptr's */
2556 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch));
2557 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch));
2558 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f;
2559 rsp_out &= 0xffffff00;
2560 rsp_out += (slot << 3);
2561 response = (struct ata_marvell_response *)
2562 (int8_t *)(ch->dma->work) + 1024 + (slot << 3);
2563
2564 /* record status for this request */
2565 request->status = response->dev_status;
2566 request->error = 0;
2567
2568 /* ack response */
2569 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out);
2570
2571 /* update progress */
2572 if (!(request->status & ATA_S_ERROR) &&
2573 !(request->flags & ATA_R_TIMEOUT))
2574 request->donecount = request->bytecount;
2575 res = ATA_OP_FINISHED;
2576 }
2577
2578 /* legacy ATA interrupt */
2579 else {
2580 res = ata_end_transaction(request);
2581 }
2582
2583 /* ack interrupt */
2584 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3))));
2585 return res;
2586 }
2587
2588 static void
2589 ata_marvell_reset(device_t dev)
2590 {
2591 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2592 struct ata_channel *ch = device_get_softc(dev);
2593
2594 /* disable the EDMA machinery */
2595 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2596 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
2597 DELAY(10);
2598
2599 /* clear SATA error register */
2600 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2601
2602 /* clear any outstanding error interrupts */
2603 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2604
2605 /* unmask all error interrupts */
2606 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
2607
2608 /* enable channel and test for devices */
2609 ata_sata_phy_enable(ch);
2610
2611 /* enable EDMA machinery */
2612 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2613 }
2614
2615 static void
2616 ata_marvell_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
2617 {
2618 struct ata_dmasetprd_args *args = xsc;
2619 struct ata_marvell_dma_prdentry *prd = args->dmatab;
2620 int i;
2621
2622 if ((args->error = error))
2623 return;
2624
2625 for (i = 0; i < nsegs; i++) {
2626 prd[i].addrlo = htole32(segs[i].ds_addr);
2627 prd[i].addrhi = 0;
2628 prd[i].count = htole32(segs[i].ds_len);
2629 }
2630 prd[i - 1].count |= htole32(ATA_DMA_EOT);
2631 }
2632
2633 static void
2634 ata_marvell_dmainit(device_t dev)
2635 {
2636 struct ata_channel *ch = device_get_softc(dev);
2637
2638 ata_dmainit(dev);
2639 if (ch->dma) {
2640 /* note start and stop are not used here */
2641 ch->dma->setprd = ata_marvell_dmasetprd;
2642 }
2643 }
2644
2645
2646 /*
2647 * National chipset support functions
2648 */
2649 int
2650 ata_national_ident(device_t dev)
2651 {
2652 struct ata_pci_controller *ctlr = device_get_softc(dev);
2653
2654 /* this chip is a clone of the Cyrix chip, bugs and all */
2655 if (pci_get_devid(dev) == ATA_SC1100) {
2656 device_set_desc(dev, "National Geode SC1100 ATA33 controller");
2657 ctlr->chipinit = ata_national_chipinit;
2658 return 0;
2659 }
2660 return ENXIO;
2661 }
2662
2663 static int
2664 ata_national_chipinit(device_t dev)
2665 {
2666 struct ata_pci_controller *ctlr = device_get_softc(dev);
2667
2668 if (ata_setup_interrupt(dev))
2669 return ENXIO;
2670
2671 ctlr->setmode = ata_national_setmode;
2672 return 0;
2673 }
2674
2675 static void
2676 ata_national_setmode(device_t dev, int mode)
2677 {
2678 device_t gparent = GRANDPARENT(dev);
2679 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2680 struct ata_device *atadev = device_get_softc(dev);
2681 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2682 u_int32_t piotiming[] =
2683 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
2684 0x00803020, 0x20102010, 0x00100010,
2685 0x00100010, 0x00100010, 0x00100010 };
2686 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
2687 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
2688 int error;
2689
2690 ch->dma->alignment = 16;
2691 ch->dma->max_iosize = 126 * DEV_BSIZE;
2692
2693 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
2694
2695 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2696
2697 if (bootverbose)
2698 device_printf(dev, "%s setting %s on National chip\n",
2699 (error) ? "failed" : "success", ata_mode2str(mode));
2700 if (!error) {
2701 if (mode >= ATA_UDMA0) {
2702 pci_write_config(gparent, 0x44 + (devno << 3),
2703 udmatiming[mode & ATA_MODE_MASK], 4);
2704 }
2705 else if (mode >= ATA_WDMA0) {
2706 pci_write_config(gparent, 0x44 + (devno << 3),
2707 dmatiming[mode & ATA_MODE_MASK], 4);
2708 }
2709 else {
2710 pci_write_config(gparent, 0x44 + (devno << 3),
2711 pci_read_config(gparent, 0x44 + (devno << 3), 4) |
2712 0x80000000, 4);
2713 }
2714 pci_write_config(gparent, 0x40 + (devno << 3),
2715 piotiming[ata_mode2idx(mode)], 4);
2716 atadev->mode = mode;
2717 }
2718 }
2719
2720
2721 /*
2722 * nVidia chipset support functions
2723 */
2724 int
2725 ata_nvidia_ident(device_t dev)
2726 {
2727 struct ata_pci_controller *ctlr = device_get_softc(dev);
2728 struct ata_chip_id *idx;
2729 static struct ata_chip_id ids[] =
2730 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nForce" },
2731 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2" },
2732 { ATA_NFORCE2_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2 Pro" },
2733 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" },
2734 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3" },
2735 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3 Pro" },
2736 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
2737 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
2738 { ATA_NFORCE_MCP04, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP" },
2739 { ATA_NFORCE_MCP04_S1, 0, 0, NV4OFF, ATA_SA150, "nForce MCP" },
2740 { ATA_NFORCE_MCP04_S2, 0, 0, NV4OFF, ATA_SA150, "nForce MCP" },
2741 { ATA_NFORCE_CK804, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce CK804" },
2742 { ATA_NFORCE_CK804_S1, 0, 0, NV4OFF, ATA_SA300, "nForce CK804" },
2743 { ATA_NFORCE_CK804_S2, 0, 0, NV4OFF, ATA_SA300, "nForce CK804" },
2744 { ATA_NFORCE_MCP51, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP51" },
2745 { ATA_NFORCE_MCP51_S1, 0, 0, NV4OFF, ATA_SA300, "nForce MCP51" },
2746 { ATA_NFORCE_MCP51_S2, 0, 0, NV4OFF, ATA_SA300, "nForce MCP51" },
2747 { ATA_NFORCE_MCP55, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP55" },
2748 { ATA_NFORCE_MCP55_S1, 0, 0, NV4OFF, ATA_SA300, "nForce MCP55" },
2749 { ATA_NFORCE_MCP55_S2, 0, 0, NV4OFF, ATA_SA300, "nForce MCP55" },
2750 { 0, 0, 0, 0, 0, 0}} ;
2751 char buffer[64] ;
2752
2753 if (!(idx = ata_match_chip(dev, ids)))
2754 return ENXIO;
2755
2756 sprintf(buffer, "nVidia %s %s controller",
2757 idx->text, ata_mode2str(idx->max_dma));
2758 device_set_desc_copy(dev, buffer);
2759 ctlr->chip = idx;
2760 ctlr->chipinit = ata_nvidia_chipinit;
2761 return 0;
2762 }
2763
2764 static int
2765 ata_nvidia_chipinit(device_t dev)
2766 {
2767 struct ata_pci_controller *ctlr = device_get_softc(dev);
2768
2769 if (ata_setup_interrupt(dev))
2770 return ENXIO;
2771
2772 if (ctlr->chip->max_dma >= ATA_SA150) {
2773 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1)
2774 ctlr->r_type2 = SYS_RES_IOPORT;
2775 else
2776 ctlr->r_type2 = SYS_RES_MEMORY;
2777 ctlr->r_rid2 = PCIR_BAR(5);
2778 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
2779 &ctlr->r_rid2, RF_ACTIVE))) {
2780 int offset = ctlr->chip->cfg2 & NV4OFF ? 0x0440 : 0x0010;
2781
2782 ctlr->allocate = ata_nvidia_allocate;
2783 ctlr->reset = ata_nvidia_reset;
2784
2785 /* enable control access */
2786 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1);
2787
2788 /* clear interrupt status */
2789 ATA_OUTB(ctlr->r_res2, offset, 0xff);
2790
2791 /* enable device and PHY state change interrupts */
2792 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd);
2793
2794 /* enable PCI interrupt */
2795 pci_write_config(dev, PCIR_COMMAND,
2796 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
2797
2798 }
2799 ctlr->setmode = ata_sata_setmode;
2800 }
2801 else {
2802 /* disable prefetch, postwrite */
2803 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
2804 ctlr->setmode = ata_via_family_setmode;
2805 }
2806 return 0;
2807 }
2808
2809 static int
2810 ata_nvidia_allocate(device_t dev)
2811 {
2812 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2813 struct ata_channel *ch = device_get_softc(dev);
2814
2815 /* setup the usual register normal pci style */
2816 if (ata_pci_allocate(dev))
2817 return ENXIO;
2818
2819 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
2820 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6);
2821 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
2822 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6);
2823 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
2824 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6);
2825
2826 ch->hw.status = ata_nvidia_status;
2827 ch->flags |= ATA_NO_SLAVE;
2828
2829 return 0;
2830 }
2831
2832 static int
2833 ata_nvidia_status(device_t dev)
2834 {
2835 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2836 struct ata_channel *ch = device_get_softc(dev);
2837 int offset = ctlr->chip->cfg2 & NV4OFF ? 0x0440 : 0x0010;
2838 struct ata_connect_task *tp;
2839 int shift = ch->unit << 2;
2840 u_int8_t status;
2841
2842 /* get interrupt status */
2843 status = ATA_INB(ctlr->r_res2, offset);
2844
2845 /* check for and handle connect events */
2846 if (((status & (0x0c << shift)) == (0x04 << shift)) &&
2847 (tp = (struct ata_connect_task *)
2848 malloc(sizeof(struct ata_connect_task),
2849 M_ATA, M_NOWAIT | M_ZERO))) {
2850
2851 if (bootverbose)
2852 device_printf(ch->dev, "CONNECT requested\n");
2853 tp->action = ATA_C_ATTACH;
2854 tp->dev = ch->dev;
2855 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
2856 taskqueue_enqueue(taskqueue_thread, &tp->task);
2857 }
2858
2859 /* check for and handle disconnect events */
2860 if ((status & (0x08 << shift)) &&
2861 (tp = (struct ata_connect_task *)
2862 malloc(sizeof(struct ata_connect_task),
2863 M_ATA, M_NOWAIT | M_ZERO))) {
2864
2865 if (bootverbose)
2866 device_printf(ch->dev, "DISCONNECT requested\n");
2867 tp->action = ATA_C_DETACH;
2868 tp->dev = ch->dev;
2869 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
2870 taskqueue_enqueue(taskqueue_thread, &tp->task);
2871 }
2872
2873 /* clear interrupt status */
2874 ATA_OUTB(ctlr->r_res2, offset, (0x0f << shift));
2875
2876 /* do we have any device action ? */
2877 return (status & (0x01 << shift));
2878 }
2879
2880 static void
2881 ata_nvidia_reset(device_t dev)
2882 {
2883 struct ata_channel *ch = device_get_softc(dev);
2884
2885 ata_sata_phy_enable(ch);
2886 }
2887
2888
2889 /*
2890 * Promise chipset support functions
2891 */
2892 #define ATA_PDC_APKT_OFFSET 0x00000010
2893 #define ATA_PDC_HPKT_OFFSET 0x00000040
2894 #define ATA_PDC_ASG_OFFSET 0x00000080
2895 #define ATA_PDC_LSG_OFFSET 0x000000c0
2896 #define ATA_PDC_HSG_OFFSET 0x00000100
2897 #define ATA_PDC_CHN_OFFSET 0x00000400
2898 #define ATA_PDC_BUF_BASE 0x00400000
2899 #define ATA_PDC_BUF_OFFSET 0x00100000
2900 #define ATA_PDC_MAX_HPKT 8
2901 #define ATA_PDC_WRITE_REG 0x00
2902 #define ATA_PDC_WRITE_CTL 0x0e
2903 #define ATA_PDC_WRITE_END 0x08
2904 #define ATA_PDC_WAIT_NBUSY 0x10
2905 #define ATA_PDC_WAIT_READY 0x18
2906 #define ATA_PDC_1B 0x20
2907 #define ATA_PDC_2B 0x40
2908
2909 struct host_packet {
2910 u_int32_t addr;
2911 TAILQ_ENTRY(host_packet) chain;
2912 };
2913
2914 struct ata_promise_sx4 {
2915 struct mtx mtx;
2916 TAILQ_HEAD(, host_packet) queue;
2917 int busy;
2918 };
2919
2920 int
2921 ata_promise_ident(device_t dev)
2922 {
2923 struct ata_pci_controller *ctlr = device_get_softc(dev);
2924 struct ata_chip_id *idx;
2925 static struct ata_chip_id ids[] =
2926 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "PDC20246" },
2927 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20262" },
2928 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20263" },
2929 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20265" },
2930 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20267" },
2931 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20268" },
2932 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "PDC20269" },
2933 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20270" },
2934 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "PDC20271" },
2935 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "PDC20275" },
2936 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "PDC20276" },
2937 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "PDC20277" },
2938 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "PDC20318" },
2939 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "PDC20319" },
2940 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20371" },
2941 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20375" },
2942 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20376" },
2943 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20377" },
2944 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20378" },
2945 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20379" },
2946 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" },
2947 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" },
2948 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" },
2949 { ATA_PDC20771, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" },
2950 { ATA_PDC40775, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" },
2951 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20617" },
2952 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20618" },
2953 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20619" },
2954 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20620" },
2955 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "PDC20621" },
2956 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "PDC20622" },
2957 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40518" },
2958 { ATA_PDC40519, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40519" },
2959 { ATA_PDC40718, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40718" },
2960 { ATA_PDC40719, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40719" },
2961 { ATA_PDC40779, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40779" },
2962 { 0, 0, 0, 0, 0, 0}};
2963 char buffer[64];
2964 uintptr_t devid = 0;
2965
2966 if (!(idx = ata_match_chip(dev, ids)))
2967 return ENXIO;
2968
2969 /* if we are on a SuperTrak SX6000 dont attach */
2970 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
2971 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
2972 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
2973 devid == ATA_I960RM)
2974 return ENXIO;
2975
2976 strcpy(buffer, "Promise ");
2977 strcat(buffer, idx->text);
2978
2979 /* if we are on a FastTrak TX4, adjust the interrupt resource */
2980 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
2981 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
2982 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
2983 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) {
2984 static long start = 0, end = 0;
2985
2986 if (pci_get_slot(dev) == 1) {
2987 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
2988 strcat(buffer, " (channel 0+1)");
2989 }
2990 else if (pci_get_slot(dev) == 2 && start && end) {
2991 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
2992 start = end = 0;
2993 strcat(buffer, " (channel 2+3)");
2994 }
2995 else {
2996 start = end = 0;
2997 }
2998 }
2999 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
3000 device_set_desc_copy(dev, buffer);
3001 ctlr->chip = idx;
3002 ctlr->chipinit = ata_promise_chipinit;
3003 return 0;
3004 }
3005
3006 static int
3007 ata_promise_chipinit(device_t dev)
3008 {
3009 struct ata_pci_controller *ctlr = device_get_softc(dev);
3010 int fake_reg, stat_reg;
3011
3012 if (ata_setup_interrupt(dev))
3013 return ENXIO;
3014
3015 switch (ctlr->chip->cfg1) {
3016 case PRNEW:
3017 /* setup clocks */
3018 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a);
3019
3020 ctlr->dmainit = ata_promise_dmainit;
3021 /* FALLTHROUGH */
3022
3023 case PROLD:
3024 /* enable burst mode */
3025 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01);
3026 ctlr->allocate = ata_promise_allocate;
3027 ctlr->setmode = ata_promise_setmode;
3028 return 0;
3029
3030 case PRTX:
3031 ctlr->allocate = ata_promise_tx2_allocate;
3032 ctlr->setmode = ata_promise_setmode;
3033 return 0;
3034
3035 case PRMIO:
3036 ctlr->r_type1 = SYS_RES_MEMORY;
3037 ctlr->r_rid1 = PCIR_BAR(4);
3038 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
3039 &ctlr->r_rid1, RF_ACTIVE)))
3040 goto failnfree;
3041
3042 ctlr->r_type2 = SYS_RES_MEMORY;
3043 ctlr->r_rid2 = PCIR_BAR(3);
3044 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3045 &ctlr->r_rid2, RF_ACTIVE)))
3046 goto failnfree;
3047
3048 if (ctlr->chip->cfg2 == PRSX4X) {
3049 struct ata_promise_sx4 *hpkt;
3050 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080);
3051
3052 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3053 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
3054 ata_promise_sx4_intr, ctlr, &ctlr->handle)) {
3055 device_printf(dev, "unable to setup interrupt\n");
3056 goto failnfree;
3057 }
3058
3059 /* print info about cache memory */
3060 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n",
3061 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4,
3062 ((dimm >> 24) & 0xff),
3063 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ?
3064 " ECC enabled" : "" );
3065
3066 /* adjust cache memory parameters */
3067 ATA_OUTL(ctlr->r_res2, 0x000c000c,
3068 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000));
3069
3070 /* setup host packet controls */
3071 hpkt = malloc(sizeof(struct ata_promise_sx4),
3072 M_TEMP, M_NOWAIT | M_ZERO);
3073 mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF);
3074 TAILQ_INIT(&hpkt->queue);
3075 hpkt->busy = 0;
3076 device_set_ivars(dev, hpkt);
3077 ctlr->allocate = ata_promise_mio_allocate;
3078 ctlr->reset = ata_promise_mio_reset;
3079 ctlr->dmainit = ata_promise_mio_dmainit;
3080 ctlr->setmode = ata_promise_setmode;
3081 ctlr->channels = 4;
3082 return 0;
3083 }
3084
3085 /* mio type controllers need an interrupt intercept */
3086 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3087 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
3088 ata_promise_mio_intr, ctlr, &ctlr->handle)) {
3089 device_printf(dev, "unable to setup interrupt\n");
3090 goto failnfree;
3091 }
3092
3093 switch (ctlr->chip->cfg2) {
3094 case PRPATA:
3095 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) +
3096 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2;
3097 goto sata150;
3098 case PRCMBO:
3099 ctlr->channels = 3;
3100 goto sata150;
3101 case PRSATA:
3102 ctlr->channels = 4;
3103 sata150:
3104 fake_reg = 0x60;
3105 stat_reg = 0x6c;
3106 break;
3107
3108 case PRCMBO2:
3109 ctlr->channels = 3;
3110 goto sataii;
3111 case PRSATA2:
3112 default:
3113 ctlr->channels = 4;
3114 sataii:
3115 fake_reg = 0x54;
3116 stat_reg = 0x60;
3117 break;
3118 }
3119
3120 /* prime fake interrupt register */
3121 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3122
3123 /* clear SATA status */
3124 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff);
3125
3126 ctlr->allocate = ata_promise_mio_allocate;
3127 ctlr->reset = ata_promise_mio_reset;
3128 ctlr->dmainit = ata_promise_mio_dmainit;
3129 ctlr->setmode = ata_promise_mio_setmode;
3130
3131 return 0;
3132 }
3133
3134 failnfree:
3135 if (ctlr->r_res2)
3136 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
3137 if (ctlr->r_res1)
3138 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1);
3139 return ENXIO;
3140 }
3141
3142 static int
3143 ata_promise_allocate(device_t dev)
3144 {
3145 struct ata_channel *ch = device_get_softc(dev);
3146
3147 if (ata_pci_allocate(dev))
3148 return ENXIO;
3149
3150 ch->hw.status = ata_promise_status;
3151 return 0;
3152 }
3153
3154 static int
3155 ata_promise_status(device_t dev)
3156 {
3157 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3158 struct ata_channel *ch = device_get_softc(dev);
3159
3160 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) {
3161 return ata_pci_status(dev);
3162 }
3163 return 0;
3164 }
3165
3166 static int
3167 ata_promise_dmastart(device_t dev)
3168 {
3169 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3170 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3171 struct ata_device *atadev = device_get_softc(dev);
3172
3173 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3174 ATA_OUTB(ctlr->r_res1, 0x11,
3175 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02));
3176 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20,
3177 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) |
3178 (ch->dma->cur_iosize >> 1));
3179 }
3180 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) |
3181 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
3182 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus);
3183 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3184 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) |
3185 ATA_BMCMD_START_STOP);
3186 ch->flags |= ATA_DMA_ACTIVE;
3187 return 0;
3188 }
3189
3190 static int
3191 ata_promise_dmastop(device_t dev)
3192 {
3193 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3194 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3195 struct ata_device *atadev = device_get_softc(dev);
3196 int error;
3197
3198 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3199 ATA_OUTB(ctlr->r_res1, 0x11,
3200 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02));
3201 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0);
3202 }
3203 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT);
3204 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3205 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3206 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3207 ch->flags &= ~ATA_DMA_ACTIVE;
3208 return error;
3209 }
3210
3211 static void
3212 ata_promise_dmareset(device_t dev)
3213 {
3214 struct ata_channel *ch = device_get_softc(dev);
3215
3216 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3217 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3218 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3219 ch->flags &= ~ATA_DMA_ACTIVE;
3220 }
3221
3222 static void
3223 ata_promise_dmainit(device_t dev)
3224 {
3225 struct ata_channel *ch = device_get_softc(dev);
3226
3227 ata_dmainit(dev);
3228 if (ch->dma) {
3229 ch->dma->start = ata_promise_dmastart;
3230 ch->dma->stop = ata_promise_dmastop;
3231 ch->dma->reset = ata_promise_dmareset;
3232 }
3233 }
3234
3235 static void
3236 ata_promise_setmode(device_t dev, int mode)
3237 {
3238 device_t gparent = GRANDPARENT(dev);
3239 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3240 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3241 struct ata_device *atadev = device_get_softc(dev);
3242 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
3243 int error;
3244 u_int32_t timings[][2] = {
3245 /* PROLD PRNEW mode */
3246 { 0x004ff329, 0x004fff2f }, /* PIO 0 */
3247 { 0x004fec25, 0x004ff82a }, /* PIO 1 */
3248 { 0x004fe823, 0x004ff026 }, /* PIO 2 */
3249 { 0x004fe622, 0x004fec24 }, /* PIO 3 */
3250 { 0x004fe421, 0x004fe822 }, /* PIO 4 */
3251 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */
3252 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */
3253 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */
3254 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */
3255 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */
3256 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */
3257 { 0, 0x00424ef6 }, /* UDMA 3 */
3258 { 0, 0x004127f3 }, /* UDMA 4 */
3259 { 0, 0x004127f3 } /* UDMA 5 */
3260 };
3261
3262 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
3263
3264 switch (ctlr->chip->cfg1) {
3265 case PROLD:
3266 case PRNEW:
3267 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) &
3268 (ch->unit ? 1 << 11 : 1 << 10))) {
3269 ata_print_cable(dev, "controller");
3270 mode = ATA_UDMA2;
3271 }
3272 if (ata_atapi(dev) && mode > ATA_PIO_MAX)
3273 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
3274 break;
3275
3276 case PRTX:
3277 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3278 if (mode > ATA_UDMA2 &&
3279 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) {
3280 ata_print_cable(dev, "controller");
3281 mode = ATA_UDMA2;
3282 }
3283 break;
3284
3285 case PRMIO:
3286 if (mode > ATA_UDMA2 &&
3287 (ATA_INL(ctlr->r_res2,
3288 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) +
3289 (ch->unit << 7)) & 0x01000000)) {
3290 ata_print_cable(dev, "controller");
3291 mode = ATA_UDMA2;
3292 }
3293 break;
3294 }
3295
3296 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3297
3298 if (bootverbose)
3299 device_printf(dev, "%ssetting %s on %s chip\n",
3300 (error) ? "FAILURE " : "",
3301 ata_mode2str(mode), ctlr->chip->text);
3302 if (!error) {
3303 if (ctlr->chip->cfg1 < PRTX)
3304 pci_write_config(gparent, 0x60 + (devno << 2),
3305 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
3306 atadev->mode = mode;
3307 }
3308 return;
3309 }
3310
3311 static int
3312 ata_promise_tx2_allocate(device_t dev)
3313 {
3314 struct ata_channel *ch = device_get_softc(dev);
3315
3316 if (ata_pci_allocate(dev))
3317 return ENXIO;
3318
3319 ch->hw.status = ata_promise_tx2_status;
3320 return 0;
3321 }
3322
3323 static int
3324 ata_promise_tx2_status(device_t dev)
3325 {
3326 struct ata_channel *ch = device_get_softc(dev);
3327
3328 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3329 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
3330 return ata_pci_status(dev);
3331 }
3332 return 0;
3333 }
3334
3335 static int
3336 ata_promise_mio_allocate(device_t dev)
3337 {
3338 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3339 struct ata_channel *ch = device_get_softc(dev);
3340 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0;
3341 int i;
3342
3343 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
3344 ch->r_io[i].res = ctlr->r_res2;
3345 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7);
3346 }
3347 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
3348 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7);
3349 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
3350 ata_default_registers(dev);
3351 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) ||
3352 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2)) {
3353 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3354 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8);
3355 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3356 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8);
3357 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3358 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8);
3359 ch->flags |= ATA_NO_SLAVE;
3360 }
3361 ch->flags |= ATA_USE_16BIT;
3362
3363 ata_generic_hw(dev);
3364 if (ctlr->chip->cfg2 & PRSX4X) {
3365 ch->hw.command = ata_promise_sx4_command;
3366 }
3367 else {
3368 ch->hw.command = ata_promise_mio_command;
3369 ch->hw.status = ata_promise_mio_status;
3370 }
3371 return 0;
3372 }
3373
3374 static void
3375 ata_promise_mio_intr(void *data)
3376 {
3377 struct ata_pci_controller *ctlr = data;
3378 struct ata_channel *ch;
3379 u_int32_t vector;
3380 int unit, fake_reg;
3381
3382 switch (ctlr->chip->cfg2) {
3383 case PRPATA:
3384 case PRCMBO:
3385 case PRSATA:
3386 fake_reg = 0x60;
3387 break;
3388 case PRCMBO2:
3389 case PRSATA2:
3390 default:
3391 fake_reg = 0x54;
3392 break;
3393 }
3394
3395 /*
3396 * since reading interrupt status register on early "mio" chips
3397 * clears the status bits we cannot read it for each channel later on
3398 * in the generic interrupt routine.
3399 * store the bits in an unused register in the chip so we can read
3400 * it from there safely to get around this "feature".
3401 */
3402 vector = ATA_INL(ctlr->r_res2, 0x040);
3403 ATA_OUTL(ctlr->r_res2, 0x040, vector);
3404 ATA_OUTL(ctlr->r_res2, fake_reg, vector);
3405
3406 for (unit = 0; unit < ctlr->channels; unit++) {
3407 if ((ch = ctlr->interrupt[unit].argument))
3408 ctlr->interrupt[unit].function(ch);
3409 }
3410
3411 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3412 }
3413
3414 static int
3415 ata_promise_mio_status(device_t dev)
3416 {
3417 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3418 struct ata_channel *ch = device_get_softc(dev);
3419 struct ata_connect_task *tp;
3420 u_int32_t fake_reg, stat_reg, vector, status;
3421
3422 switch (ctlr->chip->cfg2) {
3423 case PRPATA:
3424 case PRCMBO:
3425 case PRSATA:
3426 fake_reg = 0x60;
3427 stat_reg = 0x6c;
3428 break;
3429 case PRCMBO2:
3430 case PRSATA2:
3431 default:
3432 fake_reg = 0x54;
3433 stat_reg = 0x60;
3434 break;
3435 }
3436
3437 /* read and acknowledge interrupt */
3438 vector = ATA_INL(ctlr->r_res2, fake_reg);
3439
3440 /* read and clear interface status */
3441 status = ATA_INL(ctlr->r_res2, stat_reg);
3442 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit));
3443
3444 /* check for and handle disconnect events */
3445 if ((status & (0x00000001 << ch->unit)) &&
3446 (tp = (struct ata_connect_task *)
3447 malloc(sizeof(struct ata_connect_task),
3448 M_ATA, M_NOWAIT | M_ZERO))) {
3449
3450 if (bootverbose)
3451 device_printf(ch->dev, "DISCONNECT requested\n");
3452 tp->action = ATA_C_DETACH;
3453 tp->dev = ch->dev;
3454 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3455 taskqueue_enqueue(taskqueue_thread, &tp->task);
3456 }
3457
3458 /* check for and handle connect events */
3459 if ((status & (0x00000010 << ch->unit)) &&
3460 (tp = (struct ata_connect_task *)
3461 malloc(sizeof(struct ata_connect_task),
3462 M_ATA, M_NOWAIT | M_ZERO))) {
3463
3464 if (bootverbose)
3465 device_printf(ch->dev, "CONNECT requested\n");
3466 tp->action = ATA_C_ATTACH;
3467 tp->dev = ch->dev;
3468 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3469 taskqueue_enqueue(taskqueue_thread, &tp->task);
3470 }
3471
3472 /* do we have any device action ? */
3473 return (vector & (1 << (ch->unit + 1)));
3474 }
3475
3476 static int
3477 ata_promise_mio_command(struct ata_request *request)
3478 {
3479 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
3480 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
3481 u_int32_t *wordp = (u_int32_t *)ch->dma->work;
3482
3483 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001);
3484
3485 /* XXX SOS add ATAPI commands support later */
3486 switch (request->u.ata.command) {
3487 default:
3488 return ata_generic_command(request);
3489
3490 case ATA_READ_DMA:
3491 case ATA_READ_DMA48:
3492 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24));
3493 break;
3494
3495 case ATA_WRITE_DMA:
3496 case ATA_WRITE_DMA48:
3497 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24));
3498 break;
3499 }
3500 wordp[1] = htole32(ch->dma->sg_bus);
3501 wordp[2] = 0;
3502 ata_promise_apkt((u_int8_t*)wordp, request);
3503
3504 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma->work_bus);
3505 return 0;
3506 }
3507
3508 static void
3509 ata_promise_mio_reset(device_t dev)
3510 {
3511 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3512 struct ata_channel *ch = device_get_softc(dev);
3513 struct ata_promise_sx4 *hpktp;
3514
3515 switch (ctlr->chip->cfg2) {
3516 case PRSX4X:
3517
3518 /* softreset channel ATA module */
3519 hpktp = device_get_ivars(ctlr->dev);
3520 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1);
3521 ata_udelay(1000);
3522 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7),
3523 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) &
3524 ~0x00003f9f) | (ch->unit + 1));
3525
3526 /* softreset HOST module */ /* XXX SOS what about other outstandings */
3527 mtx_lock(&hpktp->mtx);
3528 ATA_OUTL(ctlr->r_res2, 0xc012c,
3529 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11));
3530 DELAY(10);
3531 ATA_OUTL(ctlr->r_res2, 0xc012c,
3532 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f));
3533 hpktp->busy = 0;
3534 mtx_unlock(&hpktp->mtx);
3535 ata_generic_reset(dev);
3536 break;
3537
3538 case PRPATA:
3539 case PRCMBO:
3540 case PRSATA:
3541 if ((ctlr->chip->cfg2 == PRSATA) ||
3542 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
3543
3544 /* mask plug/unplug intr */
3545 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit));
3546 }
3547
3548 /* softreset channels ATA module */
3549 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
3550 ata_udelay(10000);
3551 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
3552 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
3553 ~0x00003f9f) | (ch->unit + 1));
3554
3555 if ((ctlr->chip->cfg2 == PRSATA) ||
3556 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
3557
3558 ata_sata_phy_enable(ch);
3559
3560 /* reset and enable plug/unplug intr */
3561 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit));
3562 }
3563 else
3564 ata_generic_reset(dev);
3565 break;
3566
3567 case PRCMBO2:
3568 case PRSATA2:
3569 if ((ctlr->chip->cfg2 == PRSATA2) ||
3570 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
3571 /* set portmultiplier port */
3572 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f);
3573
3574 /* mask plug/unplug intr */
3575 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit));
3576 }
3577
3578 /* softreset channels ATA module */
3579 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
3580 ata_udelay(10000);
3581 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
3582 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
3583 ~0x00003f9f) | (ch->unit + 1));
3584
3585 if ((ctlr->chip->cfg2 == PRSATA2) ||
3586 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
3587
3588 /* set PHY mode to "improved" */
3589 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8),
3590 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) &
3591 ~0x00000003) | 0x00000001);
3592
3593 ata_sata_phy_enable(ch);
3594
3595 /* reset and enable plug/unplug intr */
3596 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit));
3597
3598 /* set portmultiplier port */
3599 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00);
3600 }
3601 else
3602 ata_generic_reset(dev);
3603 break;
3604
3605 }
3606 }
3607
3608 static void
3609 ata_promise_mio_dmainit(device_t dev)
3610 {
3611 /* note start and stop are not used here */
3612 ata_dmainit(dev);
3613 }
3614
3615 static void
3616 ata_promise_mio_setmode(device_t dev, int mode)
3617 {
3618 device_t gparent = GRANDPARENT(dev);
3619 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3620 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3621
3622 if ( (ctlr->chip->cfg2 == PRSATA) ||
3623 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2)) ||
3624 (ctlr->chip->cfg2 == PRSATA2) ||
3625 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2)))
3626 ata_sata_setmode(dev, mode);
3627 else
3628 ata_promise_setmode(dev, mode);
3629 }
3630
3631 static void
3632 ata_promise_sx4_intr(void *data)
3633 {
3634 struct ata_pci_controller *ctlr = data;
3635 struct ata_channel *ch;
3636 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480);
3637 int unit;
3638
3639 for (unit = 0; unit < ctlr->channels; unit++) {
3640 if (vector & (1 << (unit + 1)))
3641 if ((ch = ctlr->interrupt[unit].argument))
3642 ctlr->interrupt[unit].function(ch);
3643 if (vector & (1 << (unit + 5)))
3644 if ((ch = ctlr->interrupt[unit].argument))
3645 ata_promise_queue_hpkt(ctlr,
3646 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
3647 ATA_PDC_HPKT_OFFSET));
3648 if (vector & (1 << (unit + 9))) {
3649 ata_promise_next_hpkt(ctlr);
3650 if ((ch = ctlr->interrupt[unit].argument))
3651 ctlr->interrupt[unit].function(ch);
3652 }
3653 if (vector & (1 << (unit + 13))) {
3654 ata_promise_next_hpkt(ctlr);
3655 if ((ch = ctlr->interrupt[unit].argument))
3656 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
3657 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
3658 ATA_PDC_APKT_OFFSET));
3659 }
3660 }
3661 }
3662
3663 static int
3664 ata_promise_sx4_command(struct ata_request *request)
3665 {
3666 device_t gparent = GRANDPARENT(request->dev);
3667 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3668 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
3669 struct ata_dma_prdentry *prd = ch->dma->sg;
3670 caddr_t window = rman_get_virtual(ctlr->r_res1);
3671 u_int32_t *wordp;
3672 int i, idx, length = 0;
3673
3674 /* XXX SOS add ATAPI commands support later */
3675 switch (request->u.ata.command) {
3676
3677 default:
3678 return -1;
3679
3680 case ATA_ATA_IDENTIFY:
3681 case ATA_READ:
3682 case ATA_READ48:
3683 case ATA_READ_MUL:
3684 case ATA_READ_MUL48:
3685 case ATA_WRITE:
3686 case ATA_WRITE48:
3687 case ATA_WRITE_MUL:
3688 case ATA_WRITE_MUL48:
3689 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
3690 return ata_generic_command(request);
3691
3692 case ATA_SETFEATURES:
3693 case ATA_FLUSHCACHE:
3694 case ATA_FLUSHCACHE48:
3695 case ATA_SLEEP:
3696 case ATA_SET_MULTI:
3697 wordp = (u_int32_t *)
3698 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
3699 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24));
3700 wordp[1] = 0;
3701 wordp[2] = 0;
3702 ata_promise_apkt((u_int8_t *)wordp, request);
3703 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
3704 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
3705 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
3706 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET));
3707 return 0;
3708
3709 case ATA_READ_DMA:
3710 case ATA_READ_DMA48:
3711 case ATA_WRITE_DMA:
3712 case ATA_WRITE_DMA48:
3713 wordp = (u_int32_t *)
3714 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET);
3715 i = idx = 0;
3716 do {
3717 wordp[idx++] = prd[i].addr;
3718 wordp[idx++] = prd[i].count;
3719 length += (prd[i].count & ~ATA_DMA_EOT);
3720 } while (!(prd[i++].count & ATA_DMA_EOT));
3721
3722 wordp = (u_int32_t *)
3723 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET);
3724 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
3725 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
3726
3727 wordp = (u_int32_t *)
3728 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET);
3729 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
3730 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
3731
3732 wordp = (u_int32_t *)
3733 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET);
3734 if (request->flags & ATA_R_READ)
3735 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24));
3736 if (request->flags & ATA_R_WRITE)
3737 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24));
3738 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET);
3739 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET);
3740 wordp[3] = 0;
3741
3742 wordp = (u_int32_t *)
3743 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
3744 if (request->flags & ATA_R_READ)
3745 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24));
3746 if (request->flags & ATA_R_WRITE)
3747 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24));
3748 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET);
3749 wordp[2] = 0;
3750 ata_promise_apkt((u_int8_t *)wordp, request);
3751 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
3752
3753 if (request->flags & ATA_R_READ) {
3754 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001);
3755 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001);
3756 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
3757 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET));
3758 }
3759 if (request->flags & ATA_R_WRITE) {
3760 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001);
3761 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001);
3762 ata_promise_queue_hpkt(ctlr,
3763 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET));
3764 }
3765 return 0;
3766 }
3767 }
3768
3769 static int
3770 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request)
3771 {
3772 struct ata_device *atadev = device_get_softc(request->dev);
3773 int i = 12;
3774
3775 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE;
3776 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit;
3777 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL;
3778 bytep[i++] = ATA_A_4BIT;
3779
3780 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3781 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE;
3782 bytep[i++] = request->u.ata.feature >> 8;
3783 bytep[i++] = request->u.ata.feature;
3784 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT;
3785 bytep[i++] = request->u.ata.count >> 8;
3786 bytep[i++] = request->u.ata.count;
3787 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR;
3788 bytep[i++] = request->u.ata.lba >> 24;
3789 bytep[i++] = request->u.ata.lba;
3790 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
3791 bytep[i++] = request->u.ata.lba >> 32;
3792 bytep[i++] = request->u.ata.lba >> 8;
3793 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
3794 bytep[i++] = request->u.ata.lba >> 40;
3795 bytep[i++] = request->u.ata.lba >> 16;
3796 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
3797 bytep[i++] = ATA_D_LBA | atadev->unit;
3798 }
3799 else {
3800 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE;
3801 bytep[i++] = request->u.ata.feature;
3802 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT;
3803 bytep[i++] = request->u.ata.count;
3804 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR;
3805 bytep[i++] = request->u.ata.lba;
3806 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
3807 bytep[i++] = request->u.ata.lba >> 8;
3808 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
3809 bytep[i++] = request->u.ata.lba >> 16;
3810 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
3811 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) |
3812 ATA_D_IBM | atadev->unit | ((request->u.ata.lba >> 24)&0xf);
3813 }
3814 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND;
3815 bytep[i++] = request->u.ata.command;
3816 return i;
3817 }
3818
3819 static void
3820 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt)
3821 {
3822 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
3823
3824 mtx_lock(&hpktp->mtx);
3825 if (hpktp->busy) {
3826 struct host_packet *hp =
3827 malloc(sizeof(struct host_packet), M_TEMP, M_NOWAIT | M_ZERO);
3828 hp->addr = hpkt;
3829 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain);
3830 }
3831 else {
3832 hpktp->busy = 1;
3833 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt);
3834 }
3835 mtx_unlock(&hpktp->mtx);
3836 }
3837
3838 static void
3839 ata_promise_next_hpkt(struct ata_pci_controller *ctlr)
3840 {
3841 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
3842 struct host_packet *hp;
3843
3844 mtx_lock(&hpktp->mtx);
3845 if ((hp = TAILQ_FIRST(&hpktp->queue))) {
3846 TAILQ_REMOVE(&hpktp->queue, hp, chain);
3847 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr);
3848 free(hp, M_TEMP);
3849 }
3850 else
3851 hpktp->busy = 0;
3852 mtx_unlock(&hpktp->mtx);
3853 }
3854
3855
3856 /*
3857 * ServerWorks chipset support functions
3858 */
3859 int
3860 ata_serverworks_ident(device_t dev)
3861 {
3862 struct ata_pci_controller *ctlr = device_get_softc(dev);
3863 struct ata_chip_id *idx;
3864 static struct ata_chip_id ids[] =
3865 {{ ATA_ROSB4, 0x00, SWKS33, 0x00, ATA_UDMA2, "ROSB4" },
3866 { ATA_CSB5, 0x92, SWKS100, 0x00, ATA_UDMA5, "CSB5" },
3867 { ATA_CSB5, 0x00, SWKS66, 0x00, ATA_UDMA4, "CSB5" },
3868 { ATA_CSB6, 0x00, SWKS100, 0x00, ATA_UDMA5, "CSB6" },
3869 { ATA_CSB6_1, 0x00, SWKS66, 0x00, ATA_UDMA4, "CSB6" },
3870 { 0, 0, 0, 0, 0, 0}};
3871 char buffer[64];
3872
3873 if (!(idx = ata_match_chip(dev, ids)))
3874 return ENXIO;
3875
3876 sprintf(buffer, "ServerWorks %s %s controller",
3877 idx->text, ata_mode2str(idx->max_dma));
3878 device_set_desc_copy(dev, buffer);
3879 ctlr->chip = idx;
3880 ctlr->chipinit = ata_serverworks_chipinit;
3881 return 0;
3882 }
3883
3884 static int
3885 ata_serverworks_chipinit(device_t dev)
3886 {
3887 struct ata_pci_controller *ctlr = device_get_softc(dev);
3888
3889 if (ata_setup_interrupt(dev))
3890 return ENXIO;
3891
3892 if (ctlr->chip->cfg1 == SWKS33) {
3893 device_t *children;
3894 int nchildren, i;
3895
3896 /* locate the ISA part in the southbridge and enable UDMA33 */
3897 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
3898 for (i = 0; i < nchildren; i++) {
3899 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
3900 pci_write_config(children[i], 0x64,
3901 (pci_read_config(children[i], 0x64, 4) &
3902 ~0x00002000) | 0x00004000, 4);
3903 break;
3904 }
3905 }
3906 free(children, M_TEMP);
3907 }
3908 }
3909 else {
3910 pci_write_config(dev, 0x5a,
3911 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
3912 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1);
3913 }
3914 ctlr->setmode = ata_serverworks_setmode;
3915 return 0;
3916 }
3917
3918 static void
3919 ata_serverworks_setmode(device_t dev, int mode)
3920 {
3921 device_t gparent = GRANDPARENT(dev);
3922 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3923 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3924 struct ata_device *atadev = device_get_softc(dev);
3925 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
3926 int offset = (devno ^ 0x01) << 3;
3927 int error;
3928 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
3929 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
3930 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
3931
3932 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
3933
3934 mode = ata_check_80pin(dev, mode);
3935
3936 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3937
3938 if (bootverbose)
3939 device_printf(dev, "%ssetting %s on %s chip\n",
3940 (error) ? "FAILURE " : "",
3941 ata_mode2str(mode), ctlr->chip->text);
3942 if (!error) {
3943 if (mode >= ATA_UDMA0) {
3944 pci_write_config(gparent, 0x56,
3945 (pci_read_config(gparent, 0x56, 2) &
3946 ~(0xf << (devno << 2))) |
3947 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
3948 pci_write_config(gparent, 0x54,
3949 pci_read_config(gparent, 0x54, 1) |
3950 (0x01 << devno), 1);
3951 pci_write_config(gparent, 0x44,
3952 (pci_read_config(gparent, 0x44, 4) &
3953 ~(0xff << offset)) |
3954 (dmatimings[2] << offset), 4);
3955 }
3956 else if (mode >= ATA_WDMA0) {
3957 pci_write_config(gparent, 0x54,
3958 pci_read_config(gparent, 0x54, 1) &
3959 ~(0x01 << devno), 1);
3960 pci_write_config(gparent, 0x44,
3961 (pci_read_config(gparent, 0x44, 4) &
3962 ~(0xff << offset)) |
3963 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
3964 }
3965 else
3966 pci_write_config(gparent, 0x54,
3967 pci_read_config(gparent, 0x54, 1) &
3968 ~(0x01 << devno), 1);
3969
3970 pci_write_config(gparent, 0x40,
3971 (pci_read_config(gparent, 0x40, 4) &
3972 ~(0xff << offset)) |
3973 (piotimings[ata_mode2idx(mode)] << offset), 4);
3974 atadev->mode = mode;
3975 }
3976 }
3977
3978
3979 /*
3980 * Silicon Image Inc. (SiI) (former CMD) chipset support functions
3981 */
3982 int
3983 ata_sii_ident(device_t dev)
3984 {
3985 struct ata_pci_controller *ctlr = device_get_softc(dev);
3986 struct ata_chip_id *idx;
3987 static struct ata_chip_id ids[] =
3988 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" },
3989 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" },
3990 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
3991 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
3992 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" },
3993 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
3994 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
3995 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" },
3996 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" },
3997 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" },
3998 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" },
3999 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" },
4000 { 0, 0, 0, 0, 0, 0}};
4001 char buffer[64];
4002
4003 if (!(idx = ata_match_chip(dev, ids)))
4004 return ENXIO;
4005
4006 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
4007 device_set_desc_copy(dev, buffer);
4008 ctlr->chip = idx;
4009 ctlr->chipinit = ata_sii_chipinit;
4010 return 0;
4011 }
4012
4013 static int
4014 ata_sii_chipinit(device_t dev)
4015 {
4016 struct ata_pci_controller *ctlr = device_get_softc(dev);
4017
4018 if (ata_setup_interrupt(dev))
4019 return ENXIO;
4020
4021 if (ctlr->chip->cfg1 == SIIMEMIO) {
4022 ctlr->r_type2 = SYS_RES_MEMORY;
4023 ctlr->r_rid2 = PCIR_BAR(5);
4024 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4025 &ctlr->r_rid2, RF_ACTIVE)))
4026 return ENXIO;
4027
4028 if (ctlr->chip->cfg2 & SIISETCLK) {
4029 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4030 pci_write_config(dev, 0x8a,
4031 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
4032 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4033 device_printf(dev, "%s could not set ATA133 clock\n",
4034 ctlr->chip->text);
4035 }
4036
4037 /* if we have 4 channels enable the second set */
4038 if (ctlr->chip->cfg2 & SII4CH) {
4039 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
4040 ctlr->channels = 4;
4041 }
4042
4043 /* enable PCI interrupt as BIOS might not */
4044 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
4045
4046 /* dont block interrupts from any channel */
4047 pci_write_config(dev, 0x48,
4048 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
4049
4050 ctlr->allocate = ata_sii_allocate;
4051 if (ctlr->chip->max_dma >= ATA_SA150) {
4052 ctlr->reset = ata_sii_reset;
4053 ctlr->setmode = ata_sata_setmode;
4054 }
4055 else
4056 ctlr->setmode = ata_sii_setmode;
4057 }
4058 else {
4059 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
4060 device_printf(dev, "HW has secondary channel disabled\n");
4061 ctlr->channels = 1;
4062 }
4063
4064 /* enable interrupt as BIOS might not */
4065 pci_write_config(dev, 0x71, 0x01, 1);
4066
4067 ctlr->allocate = ata_cmd_allocate;
4068 ctlr->setmode = ata_cmd_setmode;
4069 }
4070 return 0;
4071 }
4072
4073 static int
4074 ata_cmd_allocate(device_t dev)
4075 {
4076 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4077 struct ata_channel *ch = device_get_softc(dev);
4078
4079 /* setup the usual register normal pci style */
4080 if (ata_pci_allocate(dev))
4081 return ENXIO;
4082
4083 if (ctlr->chip->cfg2 & SIIINTR)
4084 ch->hw.status = ata_cmd_status;
4085
4086 return 0;
4087 }
4088
4089 static int
4090 ata_cmd_status(device_t dev)
4091 {
4092 struct ata_channel *ch = device_get_softc(dev);
4093 u_int8_t reg71;
4094
4095 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
4096 (ch->unit ? 0x08 : 0x04))) {
4097 pci_write_config(device_get_parent(ch->dev), 0x71,
4098 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
4099 return ata_pci_status(dev);
4100 }
4101 return 0;
4102 }
4103
4104 static void
4105 ata_cmd_setmode(device_t dev, int mode)
4106 {
4107 device_t gparent = GRANDPARENT(dev);
4108 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4109 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4110 struct ata_device *atadev = device_get_softc(dev);
4111 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4112 int error;
4113
4114 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4115
4116 mode = ata_check_80pin(dev, mode);
4117
4118 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4119
4120 if (bootverbose)
4121 device_printf(dev, "%ssetting %s on %s chip\n",
4122 (error) ? "FAILURE " : "",
4123 ata_mode2str(mode), ctlr->chip->text);
4124 if (!error) {
4125 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
4126 int ureg = ch->unit ? 0x7b : 0x73;
4127
4128 if (mode >= ATA_UDMA0) {
4129 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
4130 { 0x11, 0x42 }, { 0x25, 0x8a },
4131 { 0x15, 0x4a }, { 0x05, 0x0a } };
4132
4133 u_int8_t umode = pci_read_config(gparent, ureg, 1);
4134
4135 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
4136 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)];
4137 pci_write_config(gparent, ureg, umode, 1);
4138 }
4139 else if (mode >= ATA_WDMA0) {
4140 int dmatimings[] = { 0x87, 0x32, 0x3f };
4141
4142 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1);
4143 pci_write_config(gparent, ureg,
4144 pci_read_config(gparent, ureg, 1) &
4145 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4146 }
4147 else {
4148 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
4149 pci_write_config(gparent, treg,
4150 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
4151 pci_write_config(gparent, ureg,
4152 pci_read_config(gparent, ureg, 1) &
4153 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4154 }
4155 atadev->mode = mode;
4156 }
4157 }
4158
4159 static int
4160 ata_sii_allocate(device_t dev)
4161 {
4162 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4163 struct ata_channel *ch = device_get_softc(dev);
4164 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
4165 int i;
4166
4167 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
4168 ch->r_io[i].res = ctlr->r_res2;
4169 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
4170 }
4171 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
4172 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
4173 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
4174 ata_default_registers(dev);
4175 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
4176 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
4177 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
4178 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
4179 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
4180 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
4181 ch->r_io[ATA_BMDEVSPEC_0].res = ctlr->r_res2;
4182 ch->r_io[ATA_BMDEVSPEC_0].offset = 0xa1 + (unit01 << 6) + (unit10 << 8);
4183
4184 if (ctlr->chip->max_dma >= ATA_SA150) {
4185 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4186 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
4187 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4188 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
4189 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4190 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
4191 ch->flags |= ATA_NO_SLAVE;
4192
4193 /* enable PHY state change interrupt */
4194 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
4195 }
4196
4197 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) {
4198 /* work around errata in early chips */
4199 ch->dma->boundary = 16 * DEV_BSIZE;
4200 ch->dma->segsize = 15 * DEV_BSIZE;
4201 }
4202
4203 ata_pci_hw(dev);
4204 ch->hw.status = ata_sii_status;
4205 return 0;
4206 }
4207
4208 static int
4209 ata_sii_status(device_t dev)
4210 {
4211 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4212 struct ata_channel *ch = device_get_softc(dev);
4213
4214 /* check for PHY related interrupts on SATA capable HW */
4215 if (ctlr->chip->max_dma >= ATA_SA150) {
4216 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS);
4217 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR);
4218 struct ata_connect_task *tp;
4219
4220 if (error) {
4221 /* clear error bits/interrupt */
4222 ATA_IDX_OUTL(ch, ATA_SERROR, error);
4223
4224 /* if we have a connection event deal with it */
4225 if ((error & ATA_SE_PHY_CHANGED) &&
4226 (tp = (struct ata_connect_task *)
4227 malloc(sizeof(struct ata_connect_task),
4228 M_ATA, M_NOWAIT | M_ZERO))) {
4229
4230 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) {
4231 if (bootverbose)
4232 device_printf(ch->dev, "CONNECT requested\n");
4233 tp->action = ATA_C_ATTACH;
4234 }
4235 else {
4236 if (bootverbose)
4237 device_printf(ch->dev, "DISCONNECT requested\n");
4238 tp->action = ATA_C_DETACH;
4239 }
4240 tp->dev = ch->dev;
4241 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
4242 taskqueue_enqueue(taskqueue_thread, &tp->task);
4243 }
4244 }
4245 }
4246
4247 /* any drive action to take care of ? */
4248 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_0) & 0x08)
4249 return ata_pci_status(dev);
4250 else
4251 return 0;
4252 }
4253
4254 static void
4255 ata_sii_reset(device_t dev)
4256 {
4257 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4258 struct ata_channel *ch = device_get_softc(dev);
4259 int offset = ((ch->unit & 1) << 7) + ((ch->unit & 2) << 8);
4260
4261 /* disable PHY state change interrupt */
4262 ATA_OUTL(ctlr->r_res2, 0x148 + offset, ~(1 << 16));
4263
4264 /* reset controller part for this channel */
4265 ATA_OUTL(ctlr->r_res2, 0x48,
4266 ATA_INL(ctlr->r_res2, 0x48) | (0xc0 >> ch->unit));
4267 DELAY(1000);
4268 ATA_OUTL(ctlr->r_res2, 0x48,
4269 ATA_INL(ctlr->r_res2, 0x48) & ~(0xc0 >> ch->unit));
4270
4271 ata_sata_phy_enable(ch);
4272
4273 /* enable PHY state change interrupt */
4274 ATA_OUTL(ctlr->r_res2, 0x148 + offset, (1 << 16));
4275 }
4276
4277 static void
4278 ata_sii_setmode(device_t dev, int mode)
4279 {
4280 device_t gparent = GRANDPARENT(dev);
4281 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4282 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4283 struct ata_device *atadev = device_get_softc(dev);
4284 int rego = (ch->unit << 4) + (ATA_DEV(atadev->unit) << 1);
4285 int mreg = ch->unit ? 0x84 : 0x80;
4286 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2);
4287 int mval = pci_read_config(gparent, mreg, 1) & ~mask;
4288 int error;
4289
4290 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4291
4292 if (ctlr->chip->cfg2 & SIISETCLK) {
4293 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) &
4294 (ch->unit ? 0x02 : 0x01))) {
4295 ata_print_cable(dev, "controller");
4296 mode = ATA_UDMA2;
4297 }
4298 }
4299 else
4300 mode = ata_check_80pin(dev, mode);
4301
4302 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4303
4304 if (bootverbose)
4305 device_printf(dev, "%ssetting %s on %s chip\n",
4306 (error) ? "FAILURE " : "",
4307 ata_mode2str(mode), ctlr->chip->text);
4308 if (error)
4309 return;
4310
4311 if (mode >= ATA_UDMA0) {
4312 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
4313 u_int8_t ureg = 0xac + rego;
4314
4315 pci_write_config(gparent, mreg,
4316 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1);
4317 pci_write_config(gparent, ureg,
4318 (pci_read_config(gparent, ureg, 1) & ~0x3f) |
4319 udmatimings[mode & ATA_MODE_MASK], 1);
4320
4321 }
4322 else if (mode >= ATA_WDMA0) {
4323 u_int8_t dreg = 0xa8 + rego;
4324 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
4325
4326 pci_write_config(gparent, mreg,
4327 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1);
4328 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
4329
4330 }
4331 else {
4332 u_int8_t preg = 0xa4 + rego;
4333 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
4334
4335 pci_write_config(gparent, mreg,
4336 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1);
4337 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2);
4338 }
4339 atadev->mode = mode;
4340 }
4341
4342
4343 /*
4344 * Silicon Integrated Systems Corp. (SiS) chipset support functions
4345 */
4346 int
4347 ata_sis_ident(device_t dev)
4348 {
4349 struct ata_pci_controller *ctlr = device_get_softc(dev);
4350 struct ata_chip_id *idx;
4351 static struct ata_chip_id ids[] =
4352 {{ ATA_SIS182, 0x00, SISSATA, 0, ATA_SA150, "182" }, /* south */
4353 { ATA_SIS181, 0x00, SISSATA, 0, ATA_SA150, "181" }, /* south */
4354 { ATA_SIS180, 0x00, SISSATA, 0, ATA_SA150, "180" }, /* south */
4355 { ATA_SIS965, 0x00, SIS133NEW, 0, ATA_UDMA6, "965" }, /* south */
4356 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "964" }, /* south */
4357 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "963" }, /* south */
4358 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "962" }, /* south */
4359
4360 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */
4361 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */
4362 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */
4363 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */
4364
4365 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */
4366 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "633" }, /* unknown */
4367 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */
4368 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "630" }, /* 1chip */
4369 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "620" }, /* 1chip */
4370
4371 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "550" },
4372 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "540" },
4373 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "530" },
4374
4375 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "5513" },
4376 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "5513" },
4377 { 0, 0, 0, 0, 0, 0 }};
4378 char buffer[64];
4379 int found = 0;
4380
4381 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev))))
4382 return ENXIO;
4383
4384 if (idx->cfg2 && !found) {
4385 u_int8_t reg57 = pci_read_config(dev, 0x57, 1);
4386
4387 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1);
4388 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) {
4389 found = 1;
4390 idx->cfg1 = SIS133NEW;
4391 idx->max_dma = ATA_UDMA6;
4392 sprintf(buffer, "SiS 962/963 %s controller",
4393 ata_mode2str(idx->max_dma));
4394 }
4395 pci_write_config(dev, 0x57, reg57, 1);
4396 }
4397 if (idx->cfg2 && !found) {
4398 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1);
4399
4400 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1);
4401 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) {
4402 struct ata_chip_id id[] =
4403 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }};
4404
4405 found = 1;
4406 if (ata_find_chip(dev, id, pci_get_slot(dev))) {
4407 idx->cfg1 = SIS133OLD;
4408 idx->max_dma = ATA_UDMA6;
4409 }
4410 else {
4411 idx->cfg1 = SIS100NEW;
4412 idx->max_dma = ATA_UDMA5;
4413 }
4414 sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
4415 }
4416 pci_write_config(dev, 0x4a, reg4a, 1);
4417 }
4418 if (!found)
4419 sprintf(buffer,"SiS %s %s controller",
4420 idx->text, ata_mode2str(idx->max_dma));
4421
4422 device_set_desc_copy(dev, buffer);
4423 ctlr->chip = idx;
4424 ctlr->chipinit = ata_sis_chipinit;
4425 return 0;
4426 }
4427
4428 static int
4429 ata_sis_chipinit(device_t dev)
4430 {
4431 struct ata_pci_controller *ctlr = device_get_softc(dev);
4432
4433 if (ata_setup_interrupt(dev))
4434 return ENXIO;
4435
4436 switch (ctlr->chip->cfg1) {
4437 case SIS33:
4438 break;
4439 case SIS66:
4440 case SIS100OLD:
4441 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1);
4442 break;
4443 case SIS100NEW:
4444 case SIS133OLD:
4445 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1);
4446 break;
4447 case SIS133NEW:
4448 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2);
4449 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2);
4450 break;
4451 case SISSATA:
4452 ctlr->r_type2 = SYS_RES_IOPORT;
4453 ctlr->r_rid2 = PCIR_BAR(5);
4454 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4455 &ctlr->r_rid2, RF_ACTIVE))) {
4456 ctlr->allocate = ata_sis_allocate;
4457 ctlr->reset = ata_sis_reset;
4458
4459 /* enable PCI interrupt */
4460 pci_write_config(dev, PCIR_COMMAND,
4461 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
4462 }
4463 ctlr->setmode = ata_sata_setmode;
4464 return 0;
4465 default:
4466 return ENXIO;
4467 }
4468 ctlr->setmode = ata_sis_setmode;
4469 return 0;
4470 }
4471
4472 static int
4473 ata_sis_allocate(device_t dev)
4474 {
4475 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4476 struct ata_channel *ch = device_get_softc(dev);
4477 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6);
4478
4479 /* setup the usual register normal pci style */
4480 if (ata_pci_allocate(dev))
4481 return ENXIO;
4482
4483 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4484 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset;
4485 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4486 ch->r_io[ATA_SERROR].offset = 0x04 + offset;
4487 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4488 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset;
4489 ch->flags |= ATA_NO_SLAVE;
4490
4491 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */
4492 /* XXX SOS unknown how to enable PHY state change interrupt */
4493 return 0;
4494 }
4495
4496 static void
4497 ata_sis_reset(device_t dev)
4498 {
4499 struct ata_channel *ch = device_get_softc(dev);
4500
4501 ata_sata_phy_enable(ch);
4502 }
4503
4504
4505 static void
4506 ata_sis_setmode(device_t dev, int mode)
4507 {
4508 device_t gparent = GRANDPARENT(dev);
4509 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4510 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4511 struct ata_device *atadev = device_get_softc(dev);
4512 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4513 int error;
4514
4515 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4516
4517 if (ctlr->chip->cfg1 == SIS133NEW) {
4518 if (mode > ATA_UDMA2 &&
4519 pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) {
4520 ata_print_cable(dev, "controller");
4521 mode = ATA_UDMA2;
4522 }
4523 }
4524 else {
4525 if (mode > ATA_UDMA2 &&
4526 pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) {
4527 ata_print_cable(dev, "controller");
4528 mode = ATA_UDMA2;
4529 }
4530 }
4531
4532 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4533
4534 if (bootverbose)
4535 device_printf(dev, "%ssetting %s on %s chip\n",
4536 (error) ? "FAILURE " : "",
4537 ata_mode2str(mode), ctlr->chip->text);
4538 if (!error) {
4539 switch (ctlr->chip->cfg1) {
4540 case SIS133NEW: {
4541 u_int32_t timings[] =
4542 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
4543 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
4544 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
4545 u_int32_t reg;
4546
4547 reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
4548 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4);
4549 break;
4550 }
4551 case SIS133OLD: {
4552 u_int16_t timings[] =
4553 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
4554 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
4555
4556 u_int16_t reg = 0x40 + (devno << 1);
4557
4558 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
4559 break;
4560 }
4561 case SIS100NEW: {
4562 u_int16_t timings[] =
4563 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
4564 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
4565 u_int16_t reg = 0x40 + (devno << 1);
4566
4567 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
4568 break;
4569 }
4570 case SIS100OLD:
4571 case SIS66:
4572 case SIS33: {
4573 u_int16_t timings[] =
4574 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
4575 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
4576 u_int16_t reg = 0x40 + (devno << 1);
4577
4578 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
4579 break;
4580 }
4581 }
4582 atadev->mode = mode;
4583 }
4584 }
4585
4586
4587 /* VIA Technologies Inc. chipset support functions */
4588 int
4589 ata_via_ident(device_t dev)
4590 {
4591 struct ata_pci_controller *ctlr = device_get_softc(dev);
4592 struct ata_chip_id *idx;
4593 static struct ata_chip_id ids[] =
4594 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" },
4595 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" },
4596 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" },
4597 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" },
4598 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"},
4599 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" },
4600 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" },
4601 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" },
4602 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" },
4603 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" },
4604 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" },
4605 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" },
4606 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
4607 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" },
4608 { 0, 0, 0, 0, 0, 0 }};
4609 static struct ata_chip_id new_ids[] =
4610 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" },
4611 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" },
4612 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" },
4613 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA150, "8251" },
4614 { 0, 0, 0, 0, 0, 0 }};
4615 char buffer[64];
4616
4617 if (pci_get_devid(dev) == ATA_VIA82C571) {
4618 if (!(idx = ata_find_chip(dev, ids, -99)))
4619 return ENXIO;
4620 }
4621 else {
4622 if (!(idx = ata_match_chip(dev, new_ids)))
4623 return ENXIO;
4624 }
4625
4626 sprintf(buffer, "VIA %s %s controller",
4627 idx->text, ata_mode2str(idx->max_dma));
4628 device_set_desc_copy(dev, buffer);
4629 ctlr->chip = idx;
4630 ctlr->chipinit = ata_via_chipinit;
4631 return 0;
4632 }
4633
4634 static int
4635 ata_via_chipinit(device_t dev)
4636 {
4637 struct ata_pci_controller *ctlr = device_get_softc(dev);
4638
4639 if (ata_setup_interrupt(dev))
4640 return ENXIO;
4641
4642 if (ctlr->chip->max_dma >= ATA_SA150) {
4643 ctlr->r_type2 = SYS_RES_IOPORT;
4644 ctlr->r_rid2 = PCIR_BAR(5);
4645 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4646 &ctlr->r_rid2, RF_ACTIVE))) {
4647 ctlr->allocate = ata_via_allocate;
4648 ctlr->reset = ata_via_reset;
4649
4650 /* enable PCI interrupt */
4651 pci_write_config(dev, PCIR_COMMAND,
4652 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
4653 }
4654 ctlr->setmode = ata_sata_setmode;
4655 return 0;
4656 }
4657
4658 /* prepare for ATA-66 on the 82C686a and 82C596b */
4659 if (ctlr->chip->cfg2 & VIACLK)
4660 pci_write_config(dev, 0x50, 0x030b030b, 4);
4661
4662 /* the southbridge might need the data corruption fix */
4663 if (ctlr->chip->cfg2 & VIABUG)
4664 ata_via_southbridge_fixup(dev);
4665
4666 /* set fifo configuration half'n'half */
4667 pci_write_config(dev, 0x43,
4668 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
4669
4670 /* set status register read retry */
4671 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
4672
4673 /* set DMA read & end-of-sector fifo flush */
4674 pci_write_config(dev, 0x46,
4675 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
4676
4677 /* set sector size */
4678 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
4679 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
4680
4681 ctlr->setmode = ata_via_family_setmode;
4682 return 0;
4683 }
4684
4685 static int
4686 ata_via_allocate(device_t dev)
4687 {
4688 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4689 struct ata_channel *ch = device_get_softc(dev);
4690
4691 /* newer SATA chips has resources in one BAR for each channel */
4692 if (ctlr->chip->cfg2 & VIABAR) {
4693 struct resource *r_io;
4694 int i, rid;
4695
4696 rid = PCIR_BAR(ch->unit);
4697 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev),
4698 SYS_RES_IOPORT,
4699 &rid, RF_ACTIVE)))
4700 return ENXIO;
4701
4702 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
4703 ch->r_io[i].res = r_io;
4704 ch->r_io[i].offset = i;
4705 }
4706 ch->r_io[ATA_CONTROL].res = r_io;
4707 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE;
4708 ch->r_io[ATA_IDX_ADDR].res = r_io;
4709 ata_default_registers(dev);
4710 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
4711 ch->r_io[i].res = ctlr->r_res1;
4712 ch->r_io[i].offset = i - ATA_BMCMD_PORT;
4713 }
4714 ata_pci_hw(dev);
4715 }
4716 else {
4717 /* setup the usual register normal pci style */
4718 if (ata_pci_allocate(dev))
4719 return ENXIO;
4720 }
4721
4722 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4723 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1);
4724 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4725 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1);
4726 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4727 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1);
4728 ch->flags |= ATA_NO_SLAVE;
4729
4730 /* XXX SOS PHY hotplug handling missing in VIA chip ?? */
4731 /* XXX SOS unknown how to enable PHY state change interrupt */
4732 return 0;
4733 }
4734
4735 static void
4736 ata_via_reset(device_t dev)
4737 {
4738 struct ata_channel *ch = device_get_softc(dev);
4739
4740 ata_sata_phy_enable(ch);
4741 }
4742
4743 static void
4744 ata_via_southbridge_fixup(device_t dev)
4745 {
4746 device_t *children;
4747 int nchildren, i;
4748
4749 if (device_get_children(device_get_parent(dev), &children, &nchildren))
4750 return;
4751
4752 for (i = 0; i < nchildren; i++) {
4753 if (pci_get_devid(children[i]) == ATA_VIA8363 ||
4754 pci_get_devid(children[i]) == ATA_VIA8371 ||
4755 pci_get_devid(children[i]) == ATA_VIA8662 ||
4756 pci_get_devid(children[i]) == ATA_VIA8361) {
4757 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
4758
4759 if ((reg76 & 0xf0) != 0xd0) {
4760 device_printf(dev,
4761 "Correcting VIA config for southbridge data corruption bug\n");
4762 pci_write_config(children[i], 0x75, 0x80, 1);
4763 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
4764 }
4765 break;
4766 }
4767 }
4768 free(children, M_TEMP);
4769 }
4770
4771
4772 /* common code for VIA, AMD & nVidia */
4773 static void
4774 ata_via_family_setmode(device_t dev, int mode)
4775 {
4776 device_t gparent = GRANDPARENT(dev);
4777 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4778 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4779 struct ata_device *atadev = device_get_softc(dev);
4780 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
4781 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
4782 int modes[][7] = {
4783 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
4784 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
4785 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
4786 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
4787 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */
4788 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4789 int reg = 0x53 - devno;
4790 int error;
4791
4792 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4793
4794 if (ctlr->chip->cfg2 & AMDCABLE) {
4795 if (mode > ATA_UDMA2 &&
4796 !(pci_read_config(gparent, 0x42, 1) & (1 << devno))) {
4797 ata_print_cable(dev, "controller");
4798 mode = ATA_UDMA2;
4799 }
4800 }
4801 else
4802 mode = ata_check_80pin(dev, mode);
4803
4804 if (ctlr->chip->cfg2 & NVIDIA)
4805 reg += 0x10;
4806
4807 if (ctlr->chip->cfg1 != VIA133)
4808 pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
4809
4810 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4811
4812 if (bootverbose)
4813 device_printf(dev, "%ssetting %s on %s chip\n",
4814 (error) ? "FAILURE " : "", ata_mode2str(mode),
4815 ctlr->chip->text);
4816 if (!error) {
4817 if (mode >= ATA_UDMA0)
4818 pci_write_config(gparent, reg,
4819 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
4820 else
4821 pci_write_config(gparent, reg, 0x8b, 1);
4822 atadev->mode = mode;
4823 }
4824 }
4825
4826
4827 /* misc functions */
4828 static struct ata_chip_id *
4829 ata_match_chip(device_t dev, struct ata_chip_id *index)
4830 {
4831 while (index->chipid != 0) {
4832 if (pci_get_devid(dev) == index->chipid &&
4833 pci_get_revid(dev) >= index->chiprev)
4834 return index;
4835 index++;
4836 }
4837 return NULL;
4838 }
4839
4840 static struct ata_chip_id *
4841 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot)
4842 {
4843 device_t *children;
4844 int nchildren, i;
4845
4846 if (device_get_children(device_get_parent(dev), &children, &nchildren))
4847 return 0;
4848
4849 while (index->chipid != 0) {
4850 for (i = 0; i < nchildren; i++) {
4851 if (((slot >= 0 && pci_get_slot(children[i]) == slot) ||
4852 (slot < 0 && pci_get_slot(children[i]) <= -slot)) &&
4853 pci_get_devid(children[i]) == index->chipid &&
4854 pci_get_revid(children[i]) >= index->chiprev) {
4855 free(children, M_TEMP);
4856 return index;
4857 }
4858 }
4859 index++;
4860 }
4861 free(children, M_TEMP);
4862 return NULL;
4863 }
4864
4865 static int
4866 ata_setup_interrupt(device_t dev)
4867 {
4868 struct ata_pci_controller *ctlr = device_get_softc(dev);
4869 int rid = ATA_IRQ_RID;
4870
4871 if (!ata_legacy(dev)) {
4872 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
4873 RF_SHAREABLE | RF_ACTIVE))) {
4874 device_printf(dev, "unable to map interrupt\n");
4875 return ENXIO;
4876 }
4877 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
4878 ata_generic_intr, ctlr, &ctlr->handle))) {
4879 device_printf(dev, "unable to setup interrupt\n");
4880 return ENXIO;
4881 }
4882 }
4883 return 0;
4884 }
4885
4886 struct ata_serialize {
4887 struct mtx locked_mtx;
4888 int locked_ch;
4889 int restart_ch;
4890 };
4891
4892 static int
4893 ata_serialize(device_t dev, int flags)
4894 {
4895 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4896 struct ata_channel *ch = device_get_softc(dev);
4897 struct ata_serialize *serial;
4898 static int inited = 0;
4899 int res;
4900
4901 if (!inited) {
4902 serial = malloc(sizeof(struct ata_serialize),
4903 M_TEMP, M_NOWAIT | M_ZERO);
4904 mtx_init(&serial->locked_mtx, "ATA serialize lock", NULL, MTX_DEF);
4905 serial->locked_ch = -1;
4906 serial->restart_ch = -1;
4907 device_set_ivars(ctlr->dev, serial);
4908 inited = 1;
4909 }
4910 else
4911 serial = device_get_ivars(ctlr->dev);
4912
4913 mtx_lock(&serial->locked_mtx);
4914 switch (flags) {
4915 case ATA_LF_LOCK:
4916 if (serial->locked_ch == -1)
4917 serial->locked_ch = ch->unit;
4918 if (serial->locked_ch != ch->unit)
4919 serial->restart_ch = ch->unit;
4920 break;
4921
4922 case ATA_LF_UNLOCK:
4923 if (serial->locked_ch == ch->unit) {
4924 serial->locked_ch = -1;
4925 if (serial->restart_ch != -1) {
4926 if ((ch = ctlr->interrupt[serial->restart_ch].argument)) {
4927 serial->restart_ch = -1;
4928 mtx_unlock(&serial->locked_mtx);
4929 ata_start(ch->dev);
4930 return -1;
4931 }
4932 }
4933 }
4934 break;
4935
4936 case ATA_LF_WHICH:
4937 break;
4938 }
4939 res = serial->locked_ch;
4940 mtx_unlock(&serial->locked_mtx);
4941 return res;
4942 }
4943
4944 static void
4945 ata_print_cable(device_t dev, u_int8_t *who)
4946 {
4947 device_printf(dev,
4948 "DMA limited to UDMA33, %s found non-ATA66 cable\n", who);
4949 }
4950
4951 static int
4952 ata_atapi(device_t dev)
4953 {
4954 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4955 struct ata_device *atadev = device_get_softc(dev);
4956
4957 return ((atadev->unit == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) ||
4958 (atadev->unit == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE));
4959 }
4960
4961 static int
4962 ata_check_80pin(device_t dev, int mode)
4963 {
4964 struct ata_device *atadev = device_get_softc(dev);
4965
4966 if (mode > ATA_UDMA2 && !(atadev->param.hwres & ATA_CABLE_ID)) {
4967 ata_print_cable(dev, "device");
4968 mode = ATA_UDMA2;
4969 }
4970 return mode;
4971 }
4972
4973 static int
4974 ata_mode2idx(int mode)
4975 {
4976 if ((mode & ATA_DMA_MASK) == ATA_UDMA0)
4977 return (mode & ATA_MODE_MASK) + 8;
4978 if ((mode & ATA_DMA_MASK) == ATA_WDMA0)
4979 return (mode & ATA_MODE_MASK) + 5;
4980 return (mode & ATA_MODE_MASK) - ATA_PIO0;
4981 }
Cache object: 46810499ffaba82a451e828a74d1ab5b
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