1 /*-
2 * Copyright (c) 1998 - 2006 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: src/sys/dev/ata/ata-chipset.c,v 1.126.2.15 2006/10/09 16:01:35 sos Exp $");
29
30 #include "opt_ata.h"
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/ata.h>
35 #include <sys/bus.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <sys/sema.h>
41 #include <sys/taskqueue.h>
42 #include <vm/uma.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
46 #include <sys/rman.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49 #include <dev/ata/ata-all.h>
50 #include <dev/ata/ata-pci.h>
51 #include <ata_if.h>
52
53 /* local prototypes */
54 /* ata-chipset.c */
55 static int ata_generic_chipinit(device_t dev);
56 static void ata_generic_intr(void *data);
57 static void ata_generic_setmode(device_t dev, int mode);
58 static void ata_sata_phy_enable(struct ata_channel *ch);
59 static void ata_sata_phy_event(void *context, int dummy);
60 static int ata_sata_connect(struct ata_channel *ch);
61 static void ata_sata_setmode(device_t dev, int mode);
62 static int ata_ahci_chipinit(device_t dev);
63 static int ata_ahci_allocate(device_t dev);
64 static int ata_ahci_status(device_t dev);
65 static int ata_ahci_begin_transaction(struct ata_request *request);
66 static int ata_ahci_end_transaction(struct ata_request *request);
67 static void ata_ahci_reset(device_t dev);
68 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
69 static void ata_ahci_dmainit(device_t dev);
70 static int ata_ahci_setup_fis(u_int8_t *fis, struct ata_request *request);
71 static int ata_acard_chipinit(device_t dev);
72 static int ata_acard_allocate(device_t dev);
73 static int ata_acard_status(device_t dev);
74 static void ata_acard_850_setmode(device_t dev, int mode);
75 static void ata_acard_86X_setmode(device_t dev, int mode);
76 static int ata_ali_chipinit(device_t dev);
77 static int ata_ali_allocate(device_t dev);
78 static int ata_ali_sata_allocate(device_t dev);
79 static void ata_ali_reset(device_t dev);
80 static void ata_ali_setmode(device_t dev, int mode);
81 static int ata_amd_chipinit(device_t dev);
82 static int ata_ati_chipinit(device_t dev);
83 static void ata_ati_setmode(device_t dev, int mode);
84 static int ata_cyrix_chipinit(device_t dev);
85 static void ata_cyrix_setmode(device_t dev, int mode);
86 static int ata_cypress_chipinit(device_t dev);
87 static void ata_cypress_setmode(device_t dev, int mode);
88 static int ata_highpoint_chipinit(device_t dev);
89 static int ata_highpoint_allocate(device_t dev);
90 static void ata_highpoint_setmode(device_t dev, int mode);
91 static int ata_highpoint_check_80pin(device_t dev, int mode);
92 static int ata_intel_chipinit(device_t dev);
93 static int ata_intel_allocate(device_t dev);
94 static void ata_intel_reset(device_t dev);
95 static void ata_intel_old_setmode(device_t dev, int mode);
96 static void ata_intel_new_setmode(device_t dev, int mode);
97 static int ata_intel_31244_allocate(device_t dev);
98 static int ata_intel_31244_status(device_t dev);
99 static int ata_intel_31244_command(struct ata_request *request);
100 static void ata_intel_31244_reset(device_t dev);
101 static int ata_ite_chipinit(device_t dev);
102 static void ata_ite_setmode(device_t dev, int mode);
103 static int ata_jmicron_chipinit(device_t dev);
104 static int ata_jmicron_allocate(device_t dev);
105 static void ata_jmicron_reset(device_t dev);
106 static void ata_jmicron_dmainit(device_t dev);
107 static void ata_jmicron_setmode(device_t dev, int mode);
108 static int ata_marvell_chipinit(device_t dev);
109 static int ata_marvell_allocate(device_t dev);
110 static int ata_marvell_status(device_t dev);
111 static int ata_marvell_begin_transaction(struct ata_request *request);
112 static int ata_marvell_end_transaction(struct ata_request *request);
113 static void ata_marvell_reset(device_t dev);
114 static void ata_marvell_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
115 static void ata_marvell_dmainit(device_t dev);
116 static int ata_national_chipinit(device_t dev);
117 static void ata_national_setmode(device_t dev, int mode);
118 static int ata_nvidia_chipinit(device_t dev);
119 static int ata_nvidia_allocate(device_t dev);
120 static int ata_nvidia_status(device_t dev);
121 static void ata_nvidia_reset(device_t dev);
122 static int ata_promise_chipinit(device_t dev);
123 static int ata_promise_allocate(device_t dev);
124 static int ata_promise_status(device_t dev);
125 static int ata_promise_dmastart(device_t dev);
126 static int ata_promise_dmastop(device_t dev);
127 static void ata_promise_dmareset(device_t dev);
128 static void ata_promise_dmainit(device_t dev);
129 static void ata_promise_setmode(device_t dev, int mode);
130 static int ata_promise_tx2_allocate(device_t dev);
131 static int ata_promise_tx2_status(device_t dev);
132 static int ata_promise_mio_allocate(device_t dev);
133 static void ata_promise_mio_intr(void *data);
134 static int ata_promise_mio_status(device_t dev);
135 static int ata_promise_mio_command(struct ata_request *request);
136 static void ata_promise_mio_reset(device_t dev);
137 static void ata_promise_mio_dmainit(device_t dev);
138 static void ata_promise_mio_setmode(device_t dev, int mode);
139 static void ata_promise_sx4_intr(void *data);
140 static int ata_promise_sx4_command(struct ata_request *request);
141 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request);
142 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt);
143 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr);
144 static int ata_serverworks_chipinit(device_t dev);
145 static int ata_serverworks_allocate(device_t dev);
146 static void ata_serverworks_setmode(device_t dev, int mode);
147 static int ata_sii_chipinit(device_t dev);
148 static int ata_cmd_allocate(device_t dev);
149 static int ata_cmd_status(device_t dev);
150 static void ata_cmd_setmode(device_t dev, int mode);
151 static int ata_sii_allocate(device_t dev);
152 static int ata_sii_status(device_t dev);
153 static void ata_sii_reset(device_t dev);
154 static void ata_sii_setmode(device_t dev, int mode);
155 static int ata_sis_chipinit(device_t dev);
156 static int ata_sis_allocate(device_t dev);
157 static void ata_sis_reset(device_t dev);
158 static void ata_sis_setmode(device_t dev, int mode);
159 static int ata_via_chipinit(device_t dev);
160 static int ata_via_allocate(device_t dev);
161 static void ata_via_reset(device_t dev);
162 static void ata_via_southbridge_fixup(device_t dev);
163 static void ata_via_family_setmode(device_t dev, int mode);
164 static struct ata_chip_id *ata_match_chip(device_t dev, struct ata_chip_id *index);
165 static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot);
166 static int ata_setup_interrupt(device_t dev);
167 static int ata_serialize(device_t dev, int flags);
168 static void ata_print_cable(device_t dev, u_int8_t *who);
169 static int ata_atapi(device_t dev);
170 static int ata_check_80pin(device_t dev, int mode);
171 static int ata_mode2idx(int mode);
172
173
174 /*
175 * generic ATA support functions
176 */
177 int
178 ata_generic_ident(device_t dev)
179 {
180 struct ata_pci_controller *ctlr = device_get_softc(dev);
181
182 device_set_desc(dev, "GENERIC ATA controller");
183 ctlr->chipinit = ata_generic_chipinit;
184 return 0;
185 }
186
187 static int
188 ata_generic_chipinit(device_t dev)
189 {
190 struct ata_pci_controller *ctlr = device_get_softc(dev);
191
192 if (ata_setup_interrupt(dev))
193 return ENXIO;
194 ctlr->setmode = ata_generic_setmode;
195 return 0;
196 }
197
198 static void
199 ata_generic_intr(void *data)
200 {
201 struct ata_pci_controller *ctlr = data;
202 struct ata_channel *ch;
203 int unit;
204
205 for (unit = 0; unit < ctlr->channels; unit++) {
206 if ((ch = ctlr->interrupt[unit].argument))
207 ctlr->interrupt[unit].function(ch);
208 }
209 }
210
211 static void
212 ata_generic_setmode(device_t dev, int mode)
213 {
214 struct ata_device *atadev = device_get_softc(dev);
215
216 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
217 mode = ata_check_80pin(dev, mode);
218 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
219 atadev->mode = mode;
220 }
221
222
223 /*
224 * SATA support functions
225 */
226 static void
227 ata_sata_phy_enable(struct ata_channel *ch)
228 {
229 int loop, retry;
230
231 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) {
232 ata_sata_connect(ch);
233 return;
234 }
235
236 for (retry = 0; retry < 10; retry++) {
237 for (loop = 0; loop < 10; loop++) {
238 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET);
239 ata_udelay(100);
240 if ((ATA_IDX_INL(ch, ATA_SCONTROL) &
241 ATA_SC_DET_MASK) == ATA_SC_DET_RESET)
242 break;
243 }
244 ata_udelay(5000);
245 for (loop = 0; loop < 10; loop++) {
246 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_IDLE |
247 ATA_SC_IPM_DIS_PARTIAL |
248 ATA_SC_IPM_DIS_SLUMBER);
249 ata_udelay(100);
250 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 0) {
251 ata_sata_connect(ch);
252 return;
253 }
254 }
255 }
256 }
257
258 static void
259 ata_sata_phy_event(void *context, int dummy)
260 {
261 struct ata_connect_task *tp = (struct ata_connect_task *)context;
262 struct ata_channel *ch = device_get_softc(tp->dev);
263 device_t *children;
264 int nchildren, i;
265
266 mtx_lock(&Giant); /* newbus suckage it needs Giant */
267 if (tp->action == ATA_C_ATTACH) {
268 if (bootverbose)
269 device_printf(tp->dev, "CONNECTED\n");
270 ata_sata_connect(ch);
271 ata_identify(tp->dev);
272 }
273 if (tp->action == ATA_C_DETACH) {
274 if (!device_get_children(tp->dev, &children, &nchildren)) {
275 for (i = 0; i < nchildren; i++)
276 if (children[i])
277 device_delete_child(tp->dev, children[i]);
278 free(children, M_TEMP);
279 }
280 mtx_lock(&ch->state_mtx);
281 ch->state = ATA_IDLE;
282 mtx_unlock(&ch->state_mtx);
283 if (bootverbose)
284 device_printf(tp->dev, "DISCONNECTED\n");
285 }
286 mtx_unlock(&Giant); /* suckage code dealt with, release Giant */
287 free(tp, M_ATA);
288 }
289
290 static int
291 ata_sata_connect(struct ata_channel *ch)
292 {
293 u_int32_t status;
294 int timeout;
295
296 /* wait up to 1 second for "connect well" */
297 for (timeout = 0; timeout < 100 ; timeout++) {
298 status = ATA_IDX_INL(ch, ATA_SSTATUS);
299 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 ||
300 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)
301 break;
302 ata_udelay(10000);
303 }
304 if (timeout >= 100) {
305 if (bootverbose)
306 device_printf(ch->dev, "SATA connect status=%08x\n", status);
307 return 0;
308 }
309
310 /* clear SATA error register */
311 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
312
313 /* find out what type device we got poll for spec'd 31 seconds */
314 /* XXX SOS 10 secs for now as I have little patience */
315 ch->devices = 0;
316 for (timeout = 0; timeout < 1000; timeout++) {
317 if (ATA_IDX_INB(ch, ATA_STATUS) & ATA_S_BUSY)
318 DELAY(10000);
319 else
320 break;
321 }
322 if (bootverbose)
323 device_printf(ch->dev, "SATA connect ready time=%dms\n", timeout * 10);
324 if (timeout < 1000) {
325 if ((ATA_IDX_INB(ch, ATA_CYL_LSB) == ATAPI_MAGIC_LSB) &&
326 (ATA_IDX_INB(ch, ATA_CYL_MSB) == ATAPI_MAGIC_MSB))
327 ch->devices = ATA_ATAPI_MASTER;
328 else
329 ch->devices = ATA_ATA_MASTER;
330 }
331 if (bootverbose)
332 device_printf(ch->dev, "sata_connect devices=0x%b\n",
333 ch->devices, "\2\3ATAPI_MASTER\1ATA_MASTER");
334 return 1;
335 }
336
337 static void
338 ata_sata_setmode(device_t dev, int mode)
339 {
340 struct ata_device *atadev = device_get_softc(dev);
341
342 /*
343 * if we detect that the device isn't a real SATA device we limit
344 * the transfer mode to UDMA5/ATA100.
345 * this works around the problems some devices has with the
346 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133.
347 */
348 if (atadev->param.satacapabilities != 0x0000 &&
349 atadev->param.satacapabilities != 0xffff) {
350 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
351
352 /* on some drives we need to set the transfer mode */
353 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
354 ata_limit_mode(dev, mode, ATA_UDMA6));
355
356 /* query SATA STATUS for the speed */
357 if (ch->r_io[ATA_SSTATUS].res &&
358 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) ==
359 ATA_SS_CONWELL_GEN2))
360 atadev->mode = ATA_SA300;
361 else
362 atadev->mode = ATA_SA150;
363 }
364 else {
365 mode = ata_limit_mode(dev, mode, ATA_UDMA5);
366 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
367 atadev->mode = mode;
368 }
369 }
370
371
372 /*
373 * AHCI v1.0 compliant SATA chipset support functions
374 */
375 struct ata_ahci_dma_prd {
376 u_int64_t dba;
377 u_int32_t reserved;
378 u_int32_t dbc; /* 0 based */
379 #define ATA_AHCI_PRD_MASK 0x003fffff /* max 4MB */
380 #define ATA_AHCI_PRD_IPC (1<<31)
381 } __packed;
382
383 struct ata_ahci_cmd_tab {
384 u_int8_t cfis[64];
385 u_int8_t acmd[32];
386 u_int8_t reserved[32];
387 struct ata_ahci_dma_prd prd_tab[16];
388 } __packed;
389
390 struct ata_ahci_cmd_list {
391 u_int16_t cmd_flags;
392 u_int16_t prd_length; /* PRD entries */
393 u_int32_t bytecount;
394 u_int64_t cmd_table_phys; /* 128byte aligned */
395 } __packed;
396
397
398 static int
399 ata_ahci_chipinit(device_t dev)
400 {
401 struct ata_pci_controller *ctlr = device_get_softc(dev);
402 u_int32_t version;
403
404 /* reset AHCI controller */
405 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
406 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_HR);
407 DELAY(1000000);
408 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) {
409 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
410 device_printf(dev, "AHCI controller reset failure\n");
411 return ENXIO;
412 }
413
414 /* enable AHCI mode */
415 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
416 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_AE);
417
418 /* get the number of HW channels */
419 ctlr->channels = (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK)+1;
420
421 /* clear interrupts */
422 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS));
423
424 /* enable AHCI interrupts */
425 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
426 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE);
427
428 ctlr->reset = ata_ahci_reset;
429 ctlr->dmainit = ata_ahci_dmainit;
430 ctlr->allocate = ata_ahci_allocate;
431 ctlr->setmode = ata_sata_setmode;
432
433 /* enable PCI interrupt */
434 pci_write_config(dev, PCIR_COMMAND,
435 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
436
437 /* announce we support the HW */
438 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS);
439 device_printf(dev,
440 "AHCI Version %x%x.%x%x controller with %d ports detected\n",
441 (version >> 24) & 0xff, (version >> 16) & 0xff,
442 (version >> 8) & 0xff, version & 0xff, ctlr->channels);
443 return 0;
444 }
445
446 static int
447 ata_ahci_allocate(device_t dev)
448 {
449 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
450 struct ata_channel *ch = device_get_softc(dev);
451 int offset = (ch->unit << 7);
452
453 /* setup legacy cruft we need */
454 ch->r_io[ATA_CYL_LSB].res = ctlr->r_res2;
455 ch->r_io[ATA_CYL_LSB].offset = ATA_AHCI_P_SIG + 1 + offset;
456 ch->r_io[ATA_CYL_MSB].res = ctlr->r_res2;
457 ch->r_io[ATA_CYL_MSB].offset = ATA_AHCI_P_SIG + 3 + offset;
458 ch->r_io[ATA_STATUS].res = ctlr->r_res2;
459 ch->r_io[ATA_STATUS].offset = ATA_AHCI_P_TFD + offset;
460 ch->r_io[ATA_ALTSTAT].res = ctlr->r_res2;
461 ch->r_io[ATA_ALTSTAT].offset = ATA_AHCI_P_TFD + offset;
462
463 /* set the SATA resources */
464 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
465 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset;
466 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
467 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset;
468 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
469 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset;
470 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
471 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset;
472
473 ch->hw.status = ata_ahci_status;
474 ch->hw.begin_transaction = ata_ahci_begin_transaction;
475 ch->hw.end_transaction = ata_ahci_end_transaction;
476 ch->hw.command = NULL; /* not used here */
477
478 /* setup the work areas */
479 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset,
480 ch->dma->work_bus + ATA_AHCI_CL_OFFSET);
481 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, 0x00000000);
482
483 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset,
484 ch->dma->work_bus + ATA_AHCI_FB_OFFSET);
485 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, 0x00000000);
486
487 /* enable wanted port interrupts */
488 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
489 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
490 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
491 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP |
492 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS |
493 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR));
494
495 /* start operations on this channel */
496 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
497 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
498 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
499 return 0;
500 }
501
502 static int
503 ata_ahci_status(device_t dev)
504 {
505 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
506 struct ata_channel *ch = device_get_softc(dev);
507 struct ata_connect_task *tp;
508 u_int32_t action, istatus, sstatus, error, issued;
509 int offset = (ch->unit << 7);
510 int tag = 0;
511
512 action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS);
513 if (action & (1 << ch->unit)) {
514 istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset);
515 issued = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset);
516 sstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SSTS + offset);
517 error = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SERR + offset);
518
519 /* clear interrupt(s) */
520 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action);
521 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus);
522 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_SERR + offset, error);
523
524 /* do we have cold connect surprise */
525 if (istatus & ATA_AHCI_P_IX_CPD) {
526 printf("ata_ahci_status status=%08x sstatus=%08x error=%08x\n",
527 istatus, sstatus, error);
528 }
529
530 /* check for and handle connect events */
531 if ((istatus & ATA_AHCI_P_IX_PC) &&
532 (tp = (struct ata_connect_task *)
533 malloc(sizeof(struct ata_connect_task),
534 M_ATA, M_NOWAIT | M_ZERO))) {
535
536 if (bootverbose)
537 device_printf(ch->dev, "CONNECT requested\n");
538 tp->action = ATA_C_ATTACH;
539 tp->dev = ch->dev;
540 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
541 taskqueue_enqueue(taskqueue_thread, &tp->task);
542 }
543
544 /* check for and handle disconnect events */
545 else if ((istatus & ATA_AHCI_P_IX_PRC) &&
546 !((sstatus & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 ||
547 (sstatus & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2) &&
548 (tp = (struct ata_connect_task *)
549 malloc(sizeof(struct ata_connect_task),
550 M_ATA, M_NOWAIT | M_ZERO))) {
551
552 if (bootverbose)
553 device_printf(ch->dev, "DISCONNECT requested\n");
554 tp->action = ATA_C_DETACH;
555 tp->dev = ch->dev;
556 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
557 taskqueue_enqueue(taskqueue_thread, &tp->task);
558 }
559
560 /* do we have any device action ? */
561 if (!(issued & (1 << tag)))
562 return 1;
563 }
564 return 0;
565 }
566
567 /* must be called with ATA channel locked and state_mtx held */
568 static int
569 ata_ahci_begin_transaction(struct ata_request *request)
570 {
571 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
572 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
573 struct ata_ahci_cmd_tab *ctp;
574 struct ata_ahci_cmd_list *clp;
575 int tag = 0, entries = 0;
576 int fis_size;
577
578 /* get a piece of the workspace for this request */
579 ctp = (struct ata_ahci_cmd_tab *)
580 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag));
581
582 /* setup the FIS for this request */ /* XXX SOS ATAPI missing still */
583 if (!(fis_size = ata_ahci_setup_fis(&ctp->cfis[0], request))) {
584 device_printf(request->dev, "setting up SATA FIS failed\n");
585 request->result = EIO;
586 return ATA_OP_FINISHED;
587 }
588
589 /* if request moves data setup and load SG list */
590 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
591 if (ch->dma->load(ch->dev, request->data, request->bytecount,
592 request->flags & ATA_R_READ,
593 ctp->prd_tab, &entries)) {
594 device_printf(request->dev, "setting up DMA failed\n");
595 request->result = EIO;
596 return ATA_OP_FINISHED;
597 }
598 }
599
600 /* setup the command list entry */
601 clp = (struct ata_ahci_cmd_list *)
602 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
603
604 clp->prd_length = entries;
605 clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) |
606 (request->flags & ATA_R_ATAPI ? (1<<5) : 0) |
607 (fis_size / sizeof(u_int32_t));
608 clp->bytecount = 0;
609 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET +
610 (ATA_AHCI_CT_SIZE * tag));
611
612 /* clear eventual ACTIVE bit */
613 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag));
614
615 /* issue the command */
616 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + (ch->unit << 7), (1 << tag));
617
618 /* start the timeout */
619 callout_reset(&request->callout, request->timeout * hz,
620 (timeout_t*)ata_timeout, request);
621 return ATA_OP_CONTINUES;
622 }
623
624 /* must be called with ATA channel locked and state_mtx held */
625 static int
626 ata_ahci_end_transaction(struct ata_request *request)
627 {
628 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
629 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
630 struct ata_ahci_cmd_list *clp;
631 u_int32_t tf_data;
632 int tag = 0;
633
634 /* kill the timeout */
635 callout_stop(&request->callout);
636
637 /* get status */
638 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit << 7));
639 request->status = tf_data;
640
641 /* if error status get details */
642 if (request->status & ATA_S_ERROR)
643 request->error = tf_data >> 8;
644
645 /* record how much data we actually moved */
646 clp = (struct ata_ahci_cmd_list *)
647 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
648 request->donecount = clp->bytecount;
649
650 /* release SG list etc */
651 ch->dma->unload(ch->dev);
652
653 return ATA_OP_FINISHED;
654 }
655
656 static void
657 ata_ahci_reset(device_t dev)
658 {
659 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
660 struct ata_channel *ch = device_get_softc(dev);
661 u_int32_t cmd;
662 int timeout, offset = (ch->unit << 7);
663
664 /* kill off all activity on this channel */
665 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
666 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
667 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
668
669 /* XXX SOS this is not entirely wrong */
670 timeout = 0;
671 do {
672 DELAY(1000);
673 if (timeout++ > 500)
674 device_printf(dev, "stopping AHCI engine failed\n");
675 break;
676 }
677 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
678
679 /* issue Command List Override if supported */
680 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) {
681 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
682 cmd |= ATA_AHCI_P_CMD_CLO;
683 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd);
684 timeout = 0;
685 do {
686 DELAY(1000);
687 if (timeout++ > 500)
688 device_printf(dev, "executing CLO failed\n");
689 break;
690 }
691 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO);
692 }
693
694 /* spin up device */
695 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, ATA_AHCI_P_CMD_SUD);
696
697 ata_sata_phy_enable(ch);
698
699 /* clear any interrupts pending on this channel */
700 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
701 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
702
703 /* start operations on this channel */
704 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
705 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
706 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
707 }
708
709 static void
710 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
711 {
712 struct ata_dmasetprd_args *args = xsc;
713 struct ata_ahci_dma_prd *prd = args->dmatab;
714 int i;
715
716 if (!(args->error = error)) {
717 for (i = 0; i < nsegs; i++) {
718 prd[i].dba = htole64(segs[i].ds_addr);
719 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK);
720 }
721 }
722 args->nsegs = nsegs;
723 }
724
725 static void
726 ata_ahci_dmainit(device_t dev)
727 {
728 struct ata_channel *ch = device_get_softc(dev);
729
730 ata_dmainit(dev);
731 if (ch->dma) {
732 /* note start and stop are not used here */
733 ch->dma->setprd = ata_ahci_dmasetprd;
734 ch->dma->max_iosize = 8192 * DEV_BSIZE;
735 }
736 }
737
738 static int
739 ata_ahci_setup_fis(u_int8_t *fis, struct ata_request *request)
740 {
741 struct ata_device *atadev = device_get_softc(request->dev);
742 int idx = 0;
743
744 /* XXX SOS add ATAPI commands support later */
745 ata_modify_if_48bit(request);
746
747 fis[idx++] = 0x27; /* host to device */
748 fis[idx++] = 0x80; /* command FIS (note PM goes here) */
749 fis[idx++] = request->u.ata.command;
750 fis[idx++] = request->u.ata.feature;
751
752 fis[idx++] = request->u.ata.lba;
753 fis[idx++] = request->u.ata.lba >> 8;
754 fis[idx++] = request->u.ata.lba >> 16;
755 fis[idx] = ATA_D_LBA | atadev->unit;
756 if (atadev->flags & ATA_D_48BIT_ACTIVE)
757 idx++;
758 else
759 fis[idx++] |= (request->u.ata.lba >> 24 & 0x0f);
760
761 fis[idx++] = request->u.ata.lba >> 24;
762 fis[idx++] = request->u.ata.lba >> 32;
763 fis[idx++] = request->u.ata.lba >> 40;
764 fis[idx++] = request->u.ata.feature >> 8;
765
766 fis[idx++] = request->u.ata.count;
767 fis[idx++] = request->u.ata.count >> 8;
768 fis[idx++] = 0x00;
769 fis[idx++] = ATA_A_4BIT;
770
771 fis[idx++] = 0x00;
772 fis[idx++] = 0x00;
773 fis[idx++] = 0x00;
774 fis[idx++] = 0x00;
775 return idx;
776 }
777
778
779 /*
780 * Acard chipset support functions
781 */
782 int
783 ata_acard_ident(device_t dev)
784 {
785 struct ata_pci_controller *ctlr = device_get_softc(dev);
786 struct ata_chip_id *idx;
787 static struct ata_chip_id ids[] =
788 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "ATP850" },
789 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "ATP860A" },
790 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "ATP860R" },
791 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "ATP865A" },
792 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "ATP865R" },
793 { 0, 0, 0, 0, 0, 0}};
794 char buffer[64];
795
796 if (!(idx = ata_match_chip(dev, ids)))
797 return ENXIO;
798
799 sprintf(buffer, "Acard %s %s controller",
800 idx->text, ata_mode2str(idx->max_dma));
801 device_set_desc_copy(dev, buffer);
802 ctlr->chip = idx;
803 ctlr->chipinit = ata_acard_chipinit;
804 return 0;
805 }
806
807 static int
808 ata_acard_chipinit(device_t dev)
809 {
810 struct ata_pci_controller *ctlr = device_get_softc(dev);
811
812 if (ata_setup_interrupt(dev))
813 return ENXIO;
814
815 ctlr->allocate = ata_acard_allocate;
816 if (ctlr->chip->cfg1 == ATPOLD) {
817 ctlr->setmode = ata_acard_850_setmode;
818 ctlr->locking = ata_serialize;
819 }
820 else
821 ctlr->setmode = ata_acard_86X_setmode;
822 return 0;
823 }
824
825 static int
826 ata_acard_allocate(device_t dev)
827 {
828 struct ata_channel *ch = device_get_softc(dev);
829
830 /* setup the usual register normal pci style */
831 if (ata_pci_allocate(dev))
832 return ENXIO;
833
834 ch->hw.status = ata_acard_status;
835 return 0;
836 }
837
838 static int
839 ata_acard_status(device_t dev)
840 {
841 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
842 struct ata_channel *ch = device_get_softc(dev);
843
844 if (ctlr->chip->cfg1 == ATPOLD &&
845 ATA_LOCKING(ch->dev, ATA_LF_WHICH) != ch->unit)
846 return 0;
847 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
848 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
849
850 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
851 ATA_BMSTAT_INTERRUPT)
852 return 0;
853 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
854 DELAY(1);
855 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
856 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
857 DELAY(1);
858 }
859 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
860 DELAY(100);
861 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
862 return 0;
863 }
864 return 1;
865 }
866
867 static void
868 ata_acard_850_setmode(device_t dev, int mode)
869 {
870 device_t gparent = GRANDPARENT(dev);
871 struct ata_pci_controller *ctlr = device_get_softc(gparent);
872 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
873 struct ata_device *atadev = device_get_softc(dev);
874 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
875 int error;
876
877 mode = ata_limit_mode(dev, mode,
878 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
879
880 /* XXX SOS missing WDMA0+1 + PIO modes */
881 if (mode >= ATA_WDMA2) {
882 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
883 if (bootverbose)
884 device_printf(dev, "%ssetting %s on %s chip\n",
885 (error) ? "FAILURE " : "",
886 ata_mode2str(mode), ctlr->chip->text);
887 if (!error) {
888 u_int8_t reg54 = pci_read_config(gparent, 0x54, 1);
889
890 reg54 &= ~(0x03 << (devno << 1));
891 if (mode >= ATA_UDMA0)
892 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1));
893 pci_write_config(gparent, 0x54, reg54, 1);
894 pci_write_config(gparent, 0x4a, 0xa6, 1);
895 pci_write_config(gparent, 0x40 + (devno << 1), 0x0301, 2);
896 atadev->mode = mode;
897 return;
898 }
899 }
900 /* we could set PIO mode timings, but we assume the BIOS did that */
901 }
902
903 static void
904 ata_acard_86X_setmode(device_t dev, int mode)
905 {
906 device_t gparent = GRANDPARENT(dev);
907 struct ata_pci_controller *ctlr = device_get_softc(gparent);
908 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
909 struct ata_device *atadev = device_get_softc(dev);
910 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
911 int error;
912
913
914 mode = ata_limit_mode(dev, mode,
915 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
916
917 mode = ata_check_80pin(dev, mode);
918
919 /* XXX SOS missing WDMA0+1 + PIO modes */
920 if (mode >= ATA_WDMA2) {
921 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
922 if (bootverbose)
923 device_printf(dev, "%ssetting %s on %s chip\n",
924 (error) ? "FAILURE " : "",
925 ata_mode2str(mode), ctlr->chip->text);
926 if (!error) {
927 u_int16_t reg44 = pci_read_config(gparent, 0x44, 2);
928
929 reg44 &= ~(0x000f << (devno << 2));
930 if (mode >= ATA_UDMA0)
931 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2));
932 pci_write_config(gparent, 0x44, reg44, 2);
933 pci_write_config(gparent, 0x4a, 0xa6, 1);
934 pci_write_config(gparent, 0x40 + devno, 0x31, 1);
935 atadev->mode = mode;
936 return;
937 }
938 }
939 /* we could set PIO mode timings, but we assume the BIOS did that */
940 }
941
942
943 /*
944 * Acer Labs Inc (ALI) chipset support functions
945 */
946 int
947 ata_ali_ident(device_t dev)
948 {
949 struct ata_pci_controller *ctlr = device_get_softc(dev);
950 struct ata_chip_id *idx;
951 static struct ata_chip_id ids[] =
952 {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" },
953 { ATA_ALI_5288, 0x00, 4, ALISATA, ATA_SA300, "M5288" },
954 { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "M5287" },
955 { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "M5281" },
956 { ATA_ALI_5229, 0xc5, 0, ALINEW, ATA_UDMA6, "M5229" },
957 { ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "M5229" },
958 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "M5229" },
959 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "M5229" },
960 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "M5229" },
961 { 0, 0, 0, 0, 0, 0}};
962 char buffer[64];
963
964 if (!(idx = ata_match_chip(dev, ids)))
965 return ENXIO;
966
967 sprintf(buffer, "AcerLabs %s %s controller",
968 idx->text, ata_mode2str(idx->max_dma));
969 device_set_desc_copy(dev, buffer);
970 ctlr->chip = idx;
971 ctlr->chipinit = ata_ali_chipinit;
972 return 0;
973 }
974
975 static int
976 ata_ali_chipinit(device_t dev)
977 {
978 struct ata_pci_controller *ctlr = device_get_softc(dev);
979
980 if (ata_setup_interrupt(dev))
981 return ENXIO;
982
983 switch (ctlr->chip->cfg2) {
984 case ALISATA:
985 ctlr->channels = ctlr->chip->cfg1;
986 ctlr->allocate = ata_ali_sata_allocate;
987 ctlr->setmode = ata_sata_setmode;
988
989 /* if we have a memory resource we can likely do AHCI */
990 ctlr->r_type2 = SYS_RES_MEMORY;
991 ctlr->r_rid2 = PCIR_BAR(5);
992 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
993 &ctlr->r_rid2, RF_ACTIVE)))
994 return ata_ahci_chipinit(dev);
995
996 /* enable PCI interrupt */
997 pci_write_config(dev, PCIR_COMMAND,
998 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
999 break;
1000
1001 case ALINEW:
1002 /* use device interrupt as byte count end */
1003 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
1004
1005 /* enable cable detection and UDMA support on newer chips */
1006 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1);
1007
1008 /* enable ATAPI UDMA mode */
1009 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1);
1010
1011 /* only chips with revision > 0xc4 can do 48bit DMA */
1012 if (ctlr->chip->chiprev <= 0xc4)
1013 device_printf(dev,
1014 "using PIO transfers above 137GB as workaround for "
1015 "48bit DMA access bug, expect reduced performance\n");
1016 ctlr->allocate = ata_ali_allocate;
1017 ctlr->reset = ata_ali_reset;
1018 ctlr->setmode = ata_ali_setmode;
1019 break;
1020
1021 case ALIOLD:
1022 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
1023 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
1024 ctlr->setmode = ata_ali_setmode;
1025 break;
1026 }
1027 return 0;
1028 }
1029
1030 static int
1031 ata_ali_allocate(device_t dev)
1032 {
1033 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1034 struct ata_channel *ch = device_get_softc(dev);
1035
1036 /* setup the usual register normal pci style */
1037 if (ata_pci_allocate(dev))
1038 return ENXIO;
1039
1040 /* older chips can't do 48bit DMA transfers */
1041 if (ctlr->chip->chiprev <= 0xc4)
1042 ch->flags |= ATA_NO_48BIT_DMA;
1043
1044 return 0;
1045 }
1046
1047 static int
1048 ata_ali_sata_allocate(device_t dev)
1049 {
1050 device_t parent = device_get_parent(dev);
1051 struct ata_pci_controller *ctlr = device_get_softc(parent);
1052 struct ata_channel *ch = device_get_softc(dev);
1053 struct resource *io = NULL, *ctlio = NULL;
1054 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
1055 int i, rid;
1056
1057 rid = PCIR_BAR(0) + (unit01 ? 8 : 0);
1058 io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1059 if (!io)
1060 return ENXIO;
1061
1062 rid = PCIR_BAR(1) + (unit01 ? 8 : 0);
1063 ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1064 if (!ctlio) {
1065 bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io);
1066 return ENXIO;
1067 }
1068
1069 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
1070 ch->r_io[i].res = io;
1071 ch->r_io[i].offset = i + (unit10 ? 8 : 0);
1072 }
1073 ch->r_io[ATA_CONTROL].res = ctlio;
1074 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0);
1075 ch->r_io[ATA_IDX_ADDR].res = io;
1076 ata_default_registers(dev);
1077 if (ctlr->r_res1) {
1078 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
1079 ch->r_io[i].res = ctlr->r_res1;
1080 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
1081 }
1082 }
1083 ch->flags |= ATA_NO_SLAVE;
1084
1085 /* XXX SOS PHY handling awkward in ALI chip not supported yet */
1086 ata_pci_hw(dev);
1087 return 0;
1088 }
1089
1090 static void
1091 ata_ali_reset(device_t dev)
1092 {
1093 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1094 struct ata_channel *ch = device_get_softc(dev);
1095 device_t *children;
1096 int nchildren, i;
1097
1098 ata_generic_reset(dev);
1099
1100 /*
1101 * workaround for datacorruption bug found on at least SUN Blade-100
1102 * find the ISA function on the southbridge and disable then enable
1103 * the ATA channel tristate buffer
1104 */
1105 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) {
1106 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) {
1107 for (i = 0; i < nchildren; i++) {
1108 if (pci_get_devid(children[i]) == ATA_ALI_1533) {
1109 pci_write_config(children[i], 0x58,
1110 pci_read_config(children[i], 0x58, 1) &
1111 ~(0x04 << ch->unit), 1);
1112 pci_write_config(children[i], 0x58,
1113 pci_read_config(children[i], 0x58, 1) |
1114 (0x04 << ch->unit), 1);
1115 break;
1116 }
1117 }
1118 free(children, M_TEMP);
1119 }
1120 }
1121 }
1122
1123 static void
1124 ata_ali_setmode(device_t dev, int mode)
1125 {
1126 device_t gparent = GRANDPARENT(dev);
1127 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1128 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1129 struct ata_device *atadev = device_get_softc(dev);
1130 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1131 int error;
1132
1133 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1134
1135 if (ctlr->chip->cfg2 & ALINEW) {
1136 if (mode > ATA_UDMA2 &&
1137 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) {
1138 ata_print_cable(dev, "controller");
1139 mode = ATA_UDMA2;
1140 }
1141 }
1142 else
1143 mode = ata_check_80pin(dev, mode);
1144
1145 if (ctlr->chip->cfg2 & ALIOLD) {
1146 /* doesn't support ATAPI DMA on write */
1147 ch->flags |= ATA_ATAPI_DMA_RO;
1148 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) {
1149 /* doesn't support ATAPI DMA on two ATAPI devices */
1150 device_printf(dev, "two atapi devices on this channel, no DMA\n");
1151 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1152 }
1153 }
1154
1155 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1156
1157 if (bootverbose)
1158 device_printf(dev, "%ssetting %s on %s chip\n",
1159 (error) ? "FAILURE " : "",
1160 ata_mode2str(mode), ctlr->chip->text);
1161 if (!error) {
1162 if (mode >= ATA_UDMA0) {
1163 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d};
1164 u_int32_t word54 = pci_read_config(gparent, 0x54, 4);
1165
1166 word54 &= ~(0x000f000f << (devno << 2));
1167 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
1168 pci_write_config(gparent, 0x54, word54, 4);
1169 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1170 0x00310001, 4);
1171 }
1172 else {
1173 u_int32_t piotimings[] =
1174 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
1175 0x00310001, 0x00440001, 0x00330001, 0x00310001};
1176
1177 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) &
1178 ~(0x0008000f << (devno << 2)), 4);
1179 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1180 piotimings[ata_mode2idx(mode)], 4);
1181 }
1182 atadev->mode = mode;
1183 }
1184 }
1185
1186
1187 /*
1188 * American Micro Devices (AMD) chipset support functions
1189 */
1190 int
1191 ata_amd_ident(device_t dev)
1192 {
1193 struct ata_pci_controller *ctlr = device_get_softc(dev);
1194 struct ata_chip_id *idx;
1195 static struct ata_chip_id ids[] =
1196 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "756" },
1197 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "766" },
1198 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "768" },
1199 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "8111" },
1200 { 0, 0, 0, 0, 0, 0}};
1201 char buffer[64];
1202
1203 if (!(idx = ata_match_chip(dev, ids)))
1204 return ENXIO;
1205
1206 sprintf(buffer, "AMD %s %s controller",
1207 idx->text, ata_mode2str(idx->max_dma));
1208 device_set_desc_copy(dev, buffer);
1209 ctlr->chip = idx;
1210 ctlr->chipinit = ata_amd_chipinit;
1211 return 0;
1212 }
1213
1214 static int
1215 ata_amd_chipinit(device_t dev)
1216 {
1217 struct ata_pci_controller *ctlr = device_get_softc(dev);
1218
1219 if (ata_setup_interrupt(dev))
1220 return ENXIO;
1221
1222 /* disable/set prefetch, postwrite */
1223 if (ctlr->chip->cfg2 & AMDBUG)
1224 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1);
1225 else
1226 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
1227
1228 ctlr->setmode = ata_via_family_setmode;
1229 return 0;
1230 }
1231
1232
1233 /*
1234 * ATI chipset support functions
1235 */
1236 int
1237 ata_ati_ident(device_t dev)
1238 {
1239 struct ata_pci_controller *ctlr = device_get_softc(dev);
1240 struct ata_chip_id *idx;
1241 static struct ata_chip_id ids[] =
1242 {{ ATA_ATI_IXP200, 0x00, 0, 0, ATA_UDMA5, "IXP200" },
1243 { ATA_ATI_IXP300, 0x00, 0, 0, ATA_UDMA6, "IXP300" },
1244 { ATA_ATI_IXP400, 0x00, 0, 0, ATA_UDMA6, "IXP400" },
1245 { ATA_ATI_IXP300_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP300" },
1246 { ATA_ATI_IXP400_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" },
1247 { ATA_ATI_IXP400_S2, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" },
1248 { 0, 0, 0, 0, 0, 0}};
1249 char buffer[64];
1250
1251 if (!(idx = ata_match_chip(dev, ids)))
1252 return ENXIO;
1253
1254 sprintf(buffer, "ATI %s %s controller",
1255 idx->text, ata_mode2str(idx->max_dma));
1256 device_set_desc_copy(dev, buffer);
1257 ctlr->chip = idx;
1258
1259 /* the ATI SATA controller is actually a SiI 3112 controller*/
1260 if (ctlr->chip->cfg1 & SIIMEMIO)
1261 ctlr->chipinit = ata_sii_chipinit;
1262 else
1263 ctlr->chipinit = ata_ati_chipinit;
1264 return 0;
1265 }
1266
1267 static int
1268 ata_ati_chipinit(device_t dev)
1269 {
1270 struct ata_pci_controller *ctlr = device_get_softc(dev);
1271
1272 if (ata_setup_interrupt(dev))
1273 return ENXIO;
1274
1275 ctlr->setmode = ata_ati_setmode;
1276 return 0;
1277 }
1278
1279 static void
1280 ata_ati_setmode(device_t dev, int mode)
1281 {
1282 device_t gparent = GRANDPARENT(dev);
1283 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1284 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1285 struct ata_device *atadev = device_get_softc(dev);
1286 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1287 int offset = (devno ^ 0x01) << 3;
1288 int error;
1289 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1290 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1291 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
1292
1293 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1294
1295 mode = ata_check_80pin(dev, mode);
1296
1297 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1298
1299 if (bootverbose)
1300 device_printf(dev, "%ssetting %s on %s chip\n",
1301 (error) ? "FAILURE " : "",
1302 ata_mode2str(mode), ctlr->chip->text);
1303 if (!error) {
1304 if (mode >= ATA_UDMA0) {
1305 pci_write_config(gparent, 0x56,
1306 (pci_read_config(gparent, 0x56, 2) &
1307 ~(0xf << (devno << 2))) |
1308 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
1309 pci_write_config(gparent, 0x54,
1310 pci_read_config(gparent, 0x54, 1) |
1311 (0x01 << devno), 1);
1312 pci_write_config(gparent, 0x44,
1313 (pci_read_config(gparent, 0x44, 4) &
1314 ~(0xff << offset)) |
1315 (dmatimings[2] << offset), 4);
1316 }
1317 else if (mode >= ATA_WDMA0) {
1318 pci_write_config(gparent, 0x54,
1319 pci_read_config(gparent, 0x54, 1) &
1320 ~(0x01 << devno), 1);
1321 pci_write_config(gparent, 0x44,
1322 (pci_read_config(gparent, 0x44, 4) &
1323 ~(0xff << offset)) |
1324 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
1325 }
1326 else
1327 pci_write_config(gparent, 0x54,
1328 pci_read_config(gparent, 0x54, 1) &
1329 ~(0x01 << devno), 1);
1330
1331 pci_write_config(gparent, 0x4a,
1332 (pci_read_config(gparent, 0x4a, 2) &
1333 ~(0xf << (devno << 2))) |
1334 (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2);
1335 pci_write_config(gparent, 0x40,
1336 (pci_read_config(gparent, 0x40, 4) &
1337 ~(0xff << offset)) |
1338 (piotimings[ata_mode2idx(mode)] << offset), 4);
1339 atadev->mode = mode;
1340 }
1341 }
1342
1343 /*
1344 * Cyrix chipset support functions
1345 */
1346 int
1347 ata_cyrix_ident(device_t dev)
1348 {
1349 struct ata_pci_controller *ctlr = device_get_softc(dev);
1350
1351 if (pci_get_devid(dev) == ATA_CYRIX_5530) {
1352 device_set_desc(dev, "Cyrix 5530 ATA33 controller");
1353 ctlr->chipinit = ata_cyrix_chipinit;
1354 return 0;
1355 }
1356 return ENXIO;
1357 }
1358
1359 static int
1360 ata_cyrix_chipinit(device_t dev)
1361 {
1362 struct ata_pci_controller *ctlr = device_get_softc(dev);
1363
1364 if (ata_setup_interrupt(dev))
1365 return ENXIO;
1366
1367 if (ctlr->r_res1)
1368 ctlr->setmode = ata_cyrix_setmode;
1369 else
1370 ctlr->setmode = ata_generic_setmode;
1371 return 0;
1372 }
1373
1374 static void
1375 ata_cyrix_setmode(device_t dev, int mode)
1376 {
1377 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1378 struct ata_device *atadev = device_get_softc(dev);
1379 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1380 u_int32_t piotiming[] =
1381 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
1382 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
1383 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
1384 int error;
1385
1386 ch->dma->alignment = 16;
1387 ch->dma->max_iosize = 126 * DEV_BSIZE;
1388
1389 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
1390
1391 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1392
1393 if (bootverbose)
1394 device_printf(dev, "%ssetting %s on Cyrix chip\n",
1395 (error) ? "FAILURE " : "", ata_mode2str(mode));
1396 if (!error) {
1397 if (mode >= ATA_UDMA0) {
1398 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1399 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]);
1400 }
1401 else if (mode >= ATA_WDMA0) {
1402 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1403 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]);
1404 }
1405 else {
1406 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1407 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]);
1408 }
1409 atadev->mode = mode;
1410 }
1411 }
1412
1413
1414 /*
1415 * Cypress chipset support functions
1416 */
1417 int
1418 ata_cypress_ident(device_t dev)
1419 {
1420 struct ata_pci_controller *ctlr = device_get_softc(dev);
1421
1422 /*
1423 * the Cypress chip is a mess, it contains two ATA functions, but
1424 * both channels are visible on the first one.
1425 * simply ignore the second function for now, as the right
1426 * solution (ignoring the second channel on the first function)
1427 * doesn't work with the crappy ATA interrupt setup on the alpha.
1428 */
1429 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 &&
1430 pci_get_function(dev) == 1 &&
1431 pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
1432 device_set_desc(dev, "Cypress 82C693 ATA controller");
1433 ctlr->chipinit = ata_cypress_chipinit;
1434 return 0;
1435 }
1436 return ENXIO;
1437 }
1438
1439 static int
1440 ata_cypress_chipinit(device_t dev)
1441 {
1442 struct ata_pci_controller *ctlr = device_get_softc(dev);
1443
1444 if (ata_setup_interrupt(dev))
1445 return ENXIO;
1446
1447 ctlr->setmode = ata_cypress_setmode;
1448 return 0;
1449 }
1450
1451 static void
1452 ata_cypress_setmode(device_t dev, int mode)
1453 {
1454 device_t gparent = GRANDPARENT(dev);
1455 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1456 struct ata_device *atadev = device_get_softc(dev);
1457 int error;
1458
1459 mode = ata_limit_mode(dev, mode, ATA_WDMA2);
1460
1461 /* XXX SOS missing WDMA0+1 + PIO modes */
1462 if (mode == ATA_WDMA2) {
1463 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1464 if (bootverbose)
1465 device_printf(dev, "%ssetting WDMA2 on Cypress chip\n",
1466 error ? "FAILURE " : "");
1467 if (!error) {
1468 pci_write_config(gparent, ch->unit ? 0x4e : 0x4c, 0x2020, 2);
1469 atadev->mode = mode;
1470 return;
1471 }
1472 }
1473 /* we could set PIO mode timings, but we assume the BIOS did that */
1474 }
1475
1476
1477 /*
1478 * HighPoint chipset support functions
1479 */
1480 int
1481 ata_highpoint_ident(device_t dev)
1482 {
1483 struct ata_pci_controller *ctlr = device_get_softc(dev);
1484 struct ata_chip_id *idx;
1485 static struct ata_chip_id ids[] =
1486 {{ ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HPT374" },
1487 { ATA_HPT372, 0x02, HPT372, 0x00, ATA_UDMA6, "HPT372N" },
1488 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1489 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT371" },
1490 { ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1491 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HPT370" },
1492 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HPT368" },
1493 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HPT366" },
1494 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT302" },
1495 { 0, 0, 0, 0, 0, 0}};
1496 char buffer[64];
1497
1498 if (!(idx = ata_match_chip(dev, ids)))
1499 return ENXIO;
1500
1501 strcpy(buffer, "HighPoint ");
1502 strcat(buffer, idx->text);
1503 if (idx->cfg1 == HPT374) {
1504 if (pci_get_function(dev) == 0)
1505 strcat(buffer, " (channel 0+1)");
1506 if (pci_get_function(dev) == 1)
1507 strcat(buffer, " (channel 2+3)");
1508 }
1509 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
1510 device_set_desc_copy(dev, buffer);
1511 ctlr->chip = idx;
1512 ctlr->chipinit = ata_highpoint_chipinit;
1513 return 0;
1514 }
1515
1516 static int
1517 ata_highpoint_chipinit(device_t dev)
1518 {
1519 struct ata_pci_controller *ctlr = device_get_softc(dev);
1520
1521 if (ata_setup_interrupt(dev))
1522 return ENXIO;
1523
1524 if (ctlr->chip->cfg2 == HPTOLD) {
1525 /* disable interrupt prediction */
1526 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
1527 }
1528 else {
1529 /* disable interrupt prediction */
1530 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
1531 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
1532
1533 /* enable interrupts */
1534 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
1535
1536 /* set clocks etc */
1537 if (ctlr->chip->cfg1 < HPT372)
1538 pci_write_config(dev, 0x5b, 0x22, 1);
1539 else
1540 pci_write_config(dev, 0x5b,
1541 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
1542 }
1543 ctlr->allocate = ata_highpoint_allocate;
1544 ctlr->setmode = ata_highpoint_setmode;
1545 return 0;
1546 }
1547
1548 static int
1549 ata_highpoint_allocate(device_t dev)
1550 {
1551 struct ata_channel *ch = device_get_softc(dev);
1552
1553 /* setup the usual register normal pci style */
1554 if (ata_pci_allocate(dev))
1555 return ENXIO;
1556
1557 ch->flags |= ATA_ALWAYS_DMASTAT;
1558 return 0;
1559 }
1560
1561 static void
1562 ata_highpoint_setmode(device_t dev, int mode)
1563 {
1564 device_t gparent = GRANDPARENT(dev);
1565 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1566 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1567 struct ata_device *atadev = device_get_softc(dev);
1568 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1569 int error;
1570 u_int32_t timings33[][4] = {
1571 /* HPT366 HPT370 HPT372 HPT374 mode */
1572 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
1573 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
1574 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
1575 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
1576 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
1577 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
1578 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
1579 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
1580 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */
1581 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */
1582 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */
1583 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */
1584 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */
1585 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */
1586 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */
1587 };
1588
1589 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1590
1591 if (ctlr->chip->cfg1 == HPT366 && ata_atapi(dev))
1592 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1593
1594 mode = ata_highpoint_check_80pin(dev, mode);
1595
1596 /*
1597 * most if not all HPT chips cant really handle that the device is
1598 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to
1599 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance
1600 */
1601 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
1602 ata_limit_mode(dev, mode, ATA_UDMA5));
1603 if (bootverbose)
1604 device_printf(dev, "%ssetting %s on HighPoint chip\n",
1605 (error) ? "FAILURE " : "", ata_mode2str(mode));
1606 if (!error)
1607 pci_write_config(gparent, 0x40 + (devno << 2),
1608 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
1609 atadev->mode = mode;
1610 }
1611
1612 static int
1613 ata_highpoint_check_80pin(device_t dev, int mode)
1614 {
1615 device_t gparent = GRANDPARENT(dev);
1616 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1617 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1618 u_int8_t reg, val, res;
1619
1620 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(gparent) == 1) {
1621 reg = ch->unit ? 0x57 : 0x53;
1622 val = pci_read_config(gparent, reg, 1);
1623 pci_write_config(gparent, reg, val | 0x80, 1);
1624 }
1625 else {
1626 reg = 0x5b;
1627 val = pci_read_config(gparent, reg, 1);
1628 pci_write_config(gparent, reg, val & 0xfe, 1);
1629 }
1630 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2);
1631 pci_write_config(gparent, reg, val, 1);
1632
1633 if (mode > ATA_UDMA2 && res) {
1634 ata_print_cable(dev, "controller");
1635 mode = ATA_UDMA2;
1636 }
1637 return mode;
1638 }
1639
1640
1641 /*
1642 * Intel chipset support functions
1643 */
1644 int
1645 ata_intel_ident(device_t dev)
1646 {
1647 struct ata_pci_controller *ctlr = device_get_softc(dev);
1648 struct ata_chip_id *idx;
1649 static struct ata_chip_id ids[] =
1650 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "PIIX" },
1651 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "PIIX3" },
1652 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1653 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1654 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1655 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "ICH0" },
1656 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "ICH" },
1657 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "ICH" },
1658 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "ICH2" },
1659 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "ICH2" },
1660 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "ICH3" },
1661 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "ICH3" },
1662 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "ICH4" },
1663 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "ICH4" },
1664 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "ICH5" },
1665 { ATA_I82801EB_S1, 0, 0, 0x00, ATA_SA150, "ICH5" },
1666 { ATA_I82801EB_R1, 0, 0, 0x00, ATA_SA150, "ICH5" },
1667 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "6300ESB" },
1668 { ATA_I6300ESB_S1, 0, 0, 0x00, ATA_SA150, "6300ESB" },
1669 { ATA_I6300ESB_R1, 0, 0, 0x00, ATA_SA150, "6300ESB" },
1670 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "ICH6" },
1671 { ATA_I82801FB_S1, 0, AHCI, 0x00, ATA_SA150, "ICH6" },
1672 { ATA_I82801FB_R1, 0, AHCI, 0x00, ATA_SA150, "ICH6" },
1673 { ATA_I82801FBM, 0, AHCI, 0x00, ATA_SA150, "ICH6M" },
1674 { ATA_I82801GB, 0, 0, 0x00, ATA_UDMA5, "ICH7" },
1675 { ATA_I82801GB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1676 { ATA_I82801GB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1677 { ATA_I82801GB_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1678 { ATA_I82801GBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1679 { ATA_I82801GBM_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1680 { ATA_I82801GBM_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1681 { ATA_I63XXESB2, 0, 0, 0x00, ATA_UDMA5, "63XXESB2" },
1682 { ATA_I63XXESB2_S1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1683 { ATA_I63XXESB2_S2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1684 { ATA_I63XXESB2_R1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1685 { ATA_I63XXESB2_R2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1686 { ATA_I82801HB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1687 { ATA_I82801HB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1688 { ATA_I82801HB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1689 { ATA_I82801HB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1690 { ATA_I82801HB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1691 { ATA_I82801HBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8M" },
1692 { ATA_I82801HBM_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8M" },
1693 { ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" },
1694 { 0, 0, 0, 0, 0, 0}};
1695 char buffer[64];
1696
1697 if (!(idx = ata_match_chip(dev, ids)))
1698 return ENXIO;
1699
1700 sprintf(buffer, "Intel %s %s controller",
1701 idx->text, ata_mode2str(idx->max_dma));
1702 device_set_desc_copy(dev, buffer);
1703 ctlr->chip = idx;
1704 ctlr->chipinit = ata_intel_chipinit;
1705 return 0;
1706 }
1707
1708 static int
1709 ata_intel_chipinit(device_t dev)
1710 {
1711 struct ata_pci_controller *ctlr = device_get_softc(dev);
1712
1713 if (ata_setup_interrupt(dev))
1714 return ENXIO;
1715
1716 /* good old PIIX needs special treatment (not implemented) */
1717 if (ctlr->chip->chipid == ATA_I82371FB) {
1718 ctlr->setmode = ata_intel_old_setmode;
1719 }
1720
1721 /* the intel 31244 needs special care if in DPA mode */
1722 else if (ctlr->chip->chipid == ATA_I31244) {
1723 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) {
1724 ctlr->r_type2 = SYS_RES_MEMORY;
1725 ctlr->r_rid2 = PCIR_BAR(0);
1726 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1727 &ctlr->r_rid2,
1728 RF_ACTIVE)))
1729 return ENXIO;
1730 ctlr->channels = 4;
1731 ctlr->allocate = ata_intel_31244_allocate;
1732 ctlr->reset = ata_intel_31244_reset;
1733 }
1734 ctlr->setmode = ata_sata_setmode;
1735 }
1736
1737 /* non SATA intel chips goes here */
1738 else if (ctlr->chip->max_dma < ATA_SA150) {
1739 ctlr->allocate = ata_intel_allocate;
1740 ctlr->setmode = ata_intel_new_setmode;
1741 }
1742
1743 /* SATA parts can be either compat or AHCI */
1744 else {
1745 /* force all ports active "the legacy way" */
1746 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f,2);
1747
1748 ctlr->allocate = ata_intel_allocate;
1749 ctlr->reset = ata_intel_reset;
1750
1751 /*
1752 * if we have AHCI capability and BAR(5) as a memory resource
1753 * and AHCI or RAID mode enabled in BIOS we go for AHCI mode
1754 */
1755 if ((ctlr->chip->cfg1 == AHCI) &&
1756 (pci_read_config(dev, 0x90, 1) & 0xc0)) {
1757 ctlr->r_type2 = SYS_RES_MEMORY;
1758 ctlr->r_rid2 = PCIR_BAR(5);
1759 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1760 &ctlr->r_rid2,
1761 RF_ACTIVE)))
1762 return ata_ahci_chipinit(dev);
1763 }
1764 ctlr->setmode = ata_sata_setmode;
1765
1766 /* enable PCI interrupt */
1767 pci_write_config(dev, PCIR_COMMAND,
1768 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
1769 }
1770 return 0;
1771 }
1772
1773 static int
1774 ata_intel_allocate(device_t dev)
1775 {
1776 struct ata_channel *ch = device_get_softc(dev);
1777
1778 /* setup the usual register normal pci style */
1779 if (ata_pci_allocate(dev))
1780 return ENXIO;
1781
1782 ch->flags |= ATA_ALWAYS_DMASTAT;
1783 return 0;
1784 }
1785
1786 static void
1787 ata_intel_reset(device_t dev)
1788 {
1789 device_t parent = device_get_parent(dev);
1790 struct ata_pci_controller *ctlr = device_get_softc(parent);
1791 struct ata_channel *ch = device_get_softc(dev);
1792 int mask, timeout;
1793
1794 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */
1795 if (ctlr->chip->cfg1) {
1796 mask = (0x0005 << ch->unit);
1797 }
1798 else {
1799 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */
1800 if (pci_read_config(parent, 0x90, 1) & 0x04)
1801 mask = 0x0003;
1802 else {
1803 mask = (0x0001 << ch->unit);
1804 /* XXX SOS should be in intel_allocate if we grow it */
1805 ch->flags |= ATA_NO_SLAVE;
1806 }
1807 }
1808 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2);
1809 DELAY(10);
1810 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2);
1811
1812 /* wait up to 1 sec for "connect well" */
1813 for (timeout = 0; timeout < 100 ; timeout++) {
1814 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) &&
1815 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff))
1816 break;
1817 ata_udelay(10000);
1818 }
1819 ata_generic_reset(dev);
1820 }
1821
1822 static void
1823 ata_intel_old_setmode(device_t dev, int mode)
1824 {
1825 /* NOT YET */
1826 }
1827
1828 static void
1829 ata_intel_new_setmode(device_t dev, int mode)
1830 {
1831 device_t gparent = GRANDPARENT(dev);
1832 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1833 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1834 struct ata_device *atadev = device_get_softc(dev);
1835 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1836 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4);
1837 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1);
1838 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1);
1839 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2);
1840 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2);
1841 u_int32_t mask40 = 0, new40 = 0;
1842 u_int8_t mask44 = 0, new44 = 0;
1843 int error;
1844 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
1845 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
1846
1847 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1848
1849 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
1850 ata_print_cable(dev, "controller");
1851 mode = ATA_UDMA2;
1852 }
1853
1854 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1855
1856 if (bootverbose)
1857 device_printf(dev, "%ssetting %s on %s chip\n",
1858 (error) ? "FAILURE " : "",
1859 ata_mode2str(mode), ctlr->chip->text);
1860 if (error)
1861 return;
1862
1863 if (mode >= ATA_UDMA0) {
1864 pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2);
1865 pci_write_config(gparent, 0x4a,
1866 (reg4a & ~(0x3 << (devno << 2))) |
1867 ((0x01 + !(mode & 0x01)) << (devno << 2)), 2);
1868 }
1869 else {
1870 pci_write_config(gparent, 0x48, reg48 & ~(0x0001 << devno), 2);
1871 pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))), 2);
1872 }
1873 reg54 |= 0x0400;
1874 if (mode >= ATA_UDMA2)
1875 pci_write_config(gparent, 0x54, reg54 | (0x1 << devno), 2);
1876 else
1877 pci_write_config(gparent, 0x54, reg54 & ~(0x1 << devno), 2);
1878
1879 if (mode >= ATA_UDMA5)
1880 pci_write_config(gparent, 0x54, reg54 | (0x1000 << devno), 2);
1881 else
1882 pci_write_config(gparent, 0x54, reg54 & ~(0x1000 << devno), 2);
1883
1884 reg40 &= ~0x00ff00ff;
1885 reg40 |= 0x40774077;
1886
1887 if (atadev->unit == ATA_MASTER) {
1888 mask40 = 0x3300;
1889 new40 = timings[ata_mode2idx(mode)] << 8;
1890 }
1891 else {
1892 mask44 = 0x0f;
1893 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
1894 (timings[ata_mode2idx(mode)] & 0x03);
1895 }
1896 if (ch->unit) {
1897 mask40 <<= 16;
1898 new40 <<= 16;
1899 mask44 <<= 4;
1900 new44 <<= 4;
1901 }
1902 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4);
1903 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1);
1904
1905 atadev->mode = mode;
1906 }
1907
1908 static int
1909 ata_intel_31244_allocate(device_t dev)
1910 {
1911 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1912 struct ata_channel *ch = device_get_softc(dev);
1913 int i;
1914 int ch_offset;
1915
1916 ch_offset = 0x200 + ch->unit * 0x200;
1917
1918 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
1919 ch->r_io[i].res = ctlr->r_res2;
1920
1921 /* setup ATA registers */
1922 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
1923 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06;
1924 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
1925 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
1926 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
1927 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
1928 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
1929 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d;
1930 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04;
1931 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c;
1932 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28;
1933 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29;
1934
1935 /* setup DMA registers */
1936 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100;
1937 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104;
1938 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108;
1939
1940 /* setup SATA registers */
1941 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70;
1942 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72;
1943 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74;
1944
1945 ch->flags |= ATA_NO_SLAVE;
1946 ata_pci_hw(dev);
1947 ch->hw.status = ata_intel_31244_status;
1948 ch->hw.command = ata_intel_31244_command;
1949
1950 /* enable PHY state change interrupt */
1951 ATA_OUTL(ctlr->r_res2, 0x4,
1952 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3)));
1953 return 0;
1954 }
1955
1956 static int
1957 ata_intel_31244_status(device_t dev)
1958 {
1959 struct ata_channel *ch = device_get_softc(dev);
1960 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS);
1961 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR);
1962 struct ata_connect_task *tp;
1963
1964 /* check for PHY related interrupts on SATA capable HW */
1965 if (error) {
1966 /* clear error bits/interrupt */
1967 ATA_IDX_OUTL(ch, ATA_SERROR, error);
1968
1969 /* if we have a connection event deal with it */
1970 if ((error & ATA_SE_PHY_CHANGED) &&
1971 (tp = (struct ata_connect_task *)
1972 malloc(sizeof(struct ata_connect_task),
1973 M_ATA, M_NOWAIT | M_ZERO))) {
1974
1975 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) {
1976 if (bootverbose)
1977 device_printf(ch->dev, "CONNECT requested\n");
1978 tp->action = ATA_C_ATTACH;
1979 }
1980 else {
1981 if (bootverbose)
1982 device_printf(ch->dev, "DISCONNECT requested\n");
1983 tp->action = ATA_C_DETACH;
1984 }
1985 tp->dev = ch->dev;
1986 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
1987 taskqueue_enqueue(taskqueue_thread, &tp->task);
1988 }
1989 }
1990
1991 /* any drive action to take care of ? */
1992 return ata_pci_status(dev);
1993 }
1994
1995 static int
1996 ata_intel_31244_command(struct ata_request *request)
1997 {
1998 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
1999 struct ata_device *atadev = device_get_softc(request->dev);
2000 u_int64_t lba;
2001
2002 if (!(atadev->flags & ATA_D_48BIT_ACTIVE))
2003 return (ata_generic_command(request));
2004
2005 lba = request->u.ata.lba;
2006 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit);
2007 /* enable interrupt */
2008 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
2009 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
2010 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
2011 ATA_IDX_OUTW(ch, ATA_SECTOR, ((lba >> 16) & 0xff00) | (lba & 0x00ff));
2012 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((lba >> 24) & 0xff00) |
2013 ((lba >> 8) & 0x00ff));
2014 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((lba >> 32) & 0xff00) |
2015 ((lba >> 16) & 0x00ff));
2016
2017 /* issue command to controller */
2018 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command);
2019
2020 return 0;
2021 }
2022
2023 static void
2024 ata_intel_31244_reset(device_t dev)
2025 {
2026 struct ata_channel *ch = device_get_softc(dev);
2027
2028 ata_sata_phy_enable(ch);
2029 }
2030
2031
2032 /*
2033 * Integrated Technology Express Inc. (ITE) chipset support functions
2034 */
2035 int
2036 ata_ite_ident(device_t dev)
2037 {
2038 struct ata_pci_controller *ctlr = device_get_softc(dev);
2039 struct ata_chip_id *idx;
2040 static struct ata_chip_id ids[] =
2041 {{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" },
2042 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" },
2043 { 0, 0, 0, 0, 0, 0}};
2044 char buffer[64];
2045
2046 if (!(idx = ata_match_chip(dev, ids)))
2047 return ENXIO;
2048
2049 sprintf(buffer, "ITE %s %s controller",
2050 idx->text, ata_mode2str(idx->max_dma));
2051 device_set_desc_copy(dev, buffer);
2052 ctlr->chip = idx;
2053 ctlr->chipinit = ata_ite_chipinit;
2054 return 0;
2055 }
2056
2057 static int
2058 ata_ite_chipinit(device_t dev)
2059 {
2060 struct ata_pci_controller *ctlr = device_get_softc(dev);
2061
2062 if (ata_setup_interrupt(dev))
2063 return ENXIO;
2064
2065 ctlr->setmode = ata_ite_setmode;
2066
2067 /* set PCI mode and 66Mhz reference clock */
2068 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1);
2069
2070 /* set default active & recover timings */
2071 pci_write_config(dev, 0x54, 0x31, 1);
2072 pci_write_config(dev, 0x56, 0x31, 1);
2073 return 0;
2074 }
2075
2076 static void
2077 ata_ite_setmode(device_t dev, int mode)
2078 {
2079 device_t gparent = GRANDPARENT(dev);
2080 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2081 struct ata_device *atadev = device_get_softc(dev);
2082 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2083 int error;
2084
2085 /* correct the mode for what the HW supports */
2086 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2087
2088 /* check the CBLID bits for 80 conductor cable detection */
2089 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) &
2090 (ch->unit ? (1<<3) : (1<<2)))) {
2091 ata_print_cable(dev, "controller");
2092 mode = ATA_UDMA2;
2093 }
2094
2095 /* set the wanted mode on the device */
2096 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2097
2098 if (bootverbose)
2099 device_printf(dev, "%s setting %s on ITE8212F chip\n",
2100 (error) ? "failed" : "success", ata_mode2str(mode));
2101
2102 /* if the device accepted the mode change, setup the HW accordingly */
2103 if (!error) {
2104 if (mode >= ATA_UDMA0) {
2105 u_int8_t udmatiming[] =
2106 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
2107
2108 /* enable UDMA mode */
2109 pci_write_config(gparent, 0x50,
2110 pci_read_config(gparent, 0x50, 1) &
2111 ~(1 << (devno + 3)), 1);
2112
2113 /* set UDMA timing */
2114 pci_write_config(gparent,
2115 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit),
2116 udmatiming[mode & ATA_MODE_MASK], 1);
2117 }
2118 else {
2119 u_int8_t chtiming[] =
2120 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
2121
2122 /* disable UDMA mode */
2123 pci_write_config(gparent, 0x50,
2124 pci_read_config(gparent, 0x50, 1) |
2125 (1 << (devno + 3)), 1);
2126
2127 /* set active and recover timing (shared between master & slave) */
2128 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) <
2129 chtiming[ata_mode2idx(mode)])
2130 pci_write_config(gparent, 0x54 + (ch->unit << 2),
2131 chtiming[ata_mode2idx(mode)], 1);
2132 }
2133 atadev->mode = mode;
2134 }
2135 }
2136
2137
2138 /*
2139 * JMicron chipset support functions
2140 */
2141 int
2142 ata_jmicron_ident(device_t dev)
2143 {
2144 struct ata_pci_controller *ctlr = device_get_softc(dev);
2145 struct ata_chip_id *idx;
2146 static struct ata_chip_id ids[] =
2147 {{ ATA_JMB360, 0, 1, 0, ATA_SA300, "JMB360" },
2148 { ATA_JMB361, 0, 1, 1, ATA_SA300, "JMB361" },
2149 { ATA_JMB363, 0, 2, 1, ATA_SA300, "JMB363" },
2150 { ATA_JMB365, 0, 1, 2, ATA_SA300, "JMB365" },
2151 { ATA_JMB366, 0, 2, 2, ATA_SA300, "JMB366" },
2152 { 0, 0, 0, 0, 0, 0}};
2153 char buffer[64];
2154
2155 if (!(idx = ata_match_chip(dev, ids)))
2156 return ENXIO;
2157
2158 if ((pci_read_config(dev, 0xdf, 1) & 0x40) &&
2159 (pci_get_function(dev) == (pci_read_config(dev, 0x40, 1) & 0x02 >> 1)))
2160 sprintf(buffer, "JMicron %s %s controller",
2161 idx->text, ata_mode2str(ATA_UDMA6));
2162 else
2163 sprintf(buffer, "JMicron %s %s controller",
2164 idx->text, ata_mode2str(idx->max_dma));
2165 device_set_desc_copy(dev, buffer);
2166 ctlr->chip = idx;
2167 ctlr->chipinit = ata_jmicron_chipinit;
2168 return 0;
2169 }
2170
2171 static int
2172 ata_jmicron_chipinit(device_t dev)
2173 {
2174 struct ata_pci_controller *ctlr = device_get_softc(dev);
2175 int error;
2176
2177 if (ata_setup_interrupt(dev))
2178 return ENXIO;
2179
2180 /* do we have multiple PCI functions ? */
2181 if (pci_read_config(dev, 0xdf, 1) & 0x40) {
2182 /* if we have a memory BAR(5) we are on the AHCI part */
2183 ctlr->r_type2 = SYS_RES_MEMORY;
2184 ctlr->r_rid2 = PCIR_BAR(5);
2185 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
2186 &ctlr->r_rid2, RF_ACTIVE)))
2187 return ata_ahci_chipinit(dev);
2188
2189 /* otherwise we are on the PATA part */
2190 ctlr->allocate = ata_pci_allocate;
2191 ctlr->reset = ata_generic_reset;
2192 ctlr->dmainit = ata_pci_dmainit;
2193 ctlr->setmode = ata_jmicron_setmode;
2194 ctlr->channels = ctlr->chip->cfg2;
2195 }
2196 else {
2197 /* set controller configuration to a combined setup we support */
2198 pci_write_config(dev, 0x40, 0x80c0a131, 4);
2199 pci_write_config(dev, 0x80, 0x01200000, 4);
2200
2201 ctlr->r_type2 = SYS_RES_MEMORY;
2202 ctlr->r_rid2 = PCIR_BAR(5);
2203 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
2204 &ctlr->r_rid2, RF_ACTIVE))){
2205 if ((error = ata_ahci_chipinit(dev)))
2206 return error;
2207 }
2208
2209 ctlr->allocate = ata_jmicron_allocate;
2210 ctlr->reset = ata_jmicron_reset;
2211 ctlr->dmainit = ata_jmicron_dmainit;
2212 ctlr->setmode = ata_jmicron_setmode;
2213
2214 /* set the number of HW channels */
2215 ctlr->channels = ctlr->chip->cfg1 + ctlr->chip->cfg2;
2216 }
2217 return 0;
2218 }
2219
2220 static int
2221 ata_jmicron_allocate(device_t dev)
2222 {
2223 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2224 struct ata_channel *ch = device_get_softc(dev);
2225 int error;
2226
2227 if (ch->unit >= ctlr->chip->cfg1) {
2228 ch->unit -= ctlr->chip->cfg1;
2229 error = ata_pci_allocate(dev);
2230 ch->unit += ctlr->chip->cfg1;
2231 }
2232 else
2233 error = ata_ahci_allocate(dev);
2234 return error;
2235 }
2236
2237 static void
2238 ata_jmicron_reset(device_t dev)
2239 {
2240 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2241 struct ata_channel *ch = device_get_softc(dev);
2242
2243 if (ch->unit >= ctlr->chip->cfg1)
2244 ata_generic_reset(dev);
2245 else
2246 ata_ahci_reset(dev);
2247 }
2248
2249 static void
2250 ata_jmicron_dmainit(device_t dev)
2251 {
2252 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2253 struct ata_channel *ch = device_get_softc(dev);
2254
2255 if (ch->unit >= ctlr->chip->cfg1)
2256 ata_pci_dmainit(dev);
2257 else
2258 ata_ahci_dmainit(dev);
2259 }
2260
2261 static void
2262 ata_jmicron_setmode(device_t dev, int mode)
2263 {
2264 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
2265 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2266
2267 if (pci_read_config(dev, 0xdf, 1) & 0x40 || ch->unit >= ctlr->chip->cfg1) {
2268 struct ata_device *atadev = device_get_softc(dev);
2269
2270 /* check for 80pin cable present */
2271 if (pci_read_config(dev, 0x40, 1) & 0x08)
2272 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
2273 else
2274 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2275
2276 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2277 atadev->mode = mode;
2278 }
2279 else
2280 ata_sata_setmode(dev, mode);
2281 }
2282
2283
2284 /*
2285 * Marvell chipset support functions
2286 */
2287 #define ATA_MV_HOST_BASE(ch) \
2288 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000)
2289 #define ATA_MV_EDMA_BASE(ch) \
2290 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000)
2291
2292 struct ata_marvell_response {
2293 u_int16_t tag;
2294 u_int8_t edma_status;
2295 u_int8_t dev_status;
2296 u_int32_t timestamp;
2297 };
2298
2299 struct ata_marvell_dma_prdentry {
2300 u_int32_t addrlo;
2301 u_int32_t count;
2302 u_int32_t addrhi;
2303 u_int32_t reserved;
2304 };
2305
2306 int
2307 ata_marvell_ident(device_t dev)
2308 {
2309 struct ata_pci_controller *ctlr = device_get_softc(dev);
2310 struct ata_chip_id *idx;
2311 static struct ata_chip_id ids[] =
2312 {{ ATA_M88SX5040, 0, 4, MV5XXX, ATA_SA150, "88SX5040" },
2313 { ATA_M88SX5041, 0, 4, MV5XXX, ATA_SA150, "88SX5041" },
2314 { ATA_M88SX5080, 0, 8, MV5XXX, ATA_SA150, "88SX5080" },
2315 { ATA_M88SX5081, 0, 8, MV5XXX, ATA_SA150, "88SX5081" },
2316 { ATA_M88SX6041, 0, 4, MV6XXX, ATA_SA300, "88SX6041" },
2317 { ATA_M88SX6081, 0, 8, MV6XXX, ATA_SA300, "88SX6081" },
2318 { 0, 0, 0, 0, 0, 0}};
2319 char buffer[64];
2320
2321 if (!(idx = ata_match_chip(dev, ids)))
2322 return ENXIO;
2323
2324 sprintf(buffer, "Marvell %s %s controller",
2325 idx->text, ata_mode2str(idx->max_dma));
2326 device_set_desc_copy(dev, buffer);
2327 ctlr->chip = idx;
2328 ctlr->chipinit = ata_marvell_chipinit;
2329 return 0;
2330 }
2331
2332 static int
2333 ata_marvell_chipinit(device_t dev)
2334 {
2335 struct ata_pci_controller *ctlr = device_get_softc(dev);
2336
2337 if (ata_setup_interrupt(dev))
2338 return ENXIO;
2339
2340 ctlr->r_type1 = SYS_RES_MEMORY;
2341 ctlr->r_rid1 = PCIR_BAR(0);
2342 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
2343 &ctlr->r_rid1, RF_ACTIVE)))
2344 return ENXIO;
2345
2346 /* mask all host controller interrupts */
2347 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000);
2348
2349 /* mask all PCI interrupts */
2350 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000);
2351
2352 ctlr->allocate = ata_marvell_allocate;
2353 ctlr->reset = ata_marvell_reset;
2354 ctlr->dmainit = ata_marvell_dmainit;
2355 ctlr->setmode = ata_sata_setmode;
2356 ctlr->channels = ctlr->chip->cfg1;
2357
2358 /* clear host controller interrupts */
2359 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000);
2360 if (ctlr->chip->cfg1 > 4)
2361 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000);
2362
2363 /* clear PCI interrupts */
2364 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000);
2365
2366 /* unmask PCI interrupts we want */
2367 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff);
2368
2369 /* unmask host controller interrupts we want */
2370 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ |
2371 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25));
2372
2373 /* enable PCI interrupt */
2374 pci_write_config(dev, PCIR_COMMAND,
2375 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
2376 return 0;
2377 }
2378
2379 static int
2380 ata_marvell_allocate(device_t dev)
2381 {
2382 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2383 struct ata_channel *ch = device_get_softc(dev);
2384 bus_addr_t work = ch->dma->work_bus;
2385 int i;
2386
2387 /* clear work area */
2388 bzero(ch->dma->work, 1024+256);
2389
2390 /* set legacy ATA resources */
2391 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
2392 ch->r_io[i].res = ctlr->r_res1;
2393 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch);
2394 }
2395 ch->r_io[ATA_CONTROL].res = ctlr->r_res1;
2396 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch);
2397 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1;
2398 ata_default_registers(dev);
2399
2400 /* set SATA resources */
2401 switch (ctlr->chip->cfg2) {
2402 case MV5XXX:
2403 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2404 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch);
2405 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2406 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch);
2407 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2408 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch);
2409 break;
2410 case MV6XXX:
2411 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2412 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch);
2413 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2414 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch);
2415 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2416 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch);
2417 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1;
2418 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch);
2419 break;
2420 }
2421
2422 ch->flags |= ATA_NO_SLAVE;
2423 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */
2424 ata_generic_hw(dev);
2425 ch->hw.begin_transaction = ata_marvell_begin_transaction;
2426 ch->hw.end_transaction = ata_marvell_end_transaction;
2427 ch->hw.status = ata_marvell_status;
2428
2429 /* disable the EDMA machinery */
2430 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2431 DELAY(100000); /* SOS should poll for disabled */
2432
2433 /* set configuration to non-queued 128b read transfers stop on error */
2434 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13));
2435
2436 /* request queue base high */
2437 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), (work >> 16) >> 16);
2438
2439 /* request queue in ptr */
2440 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
2441
2442 /* request queue out ptr */
2443 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0);
2444
2445 /* response queue base high */
2446 work += 1024;
2447 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), (work >> 16) >> 16);
2448
2449 /* response queue in ptr */
2450 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0);
2451
2452 /* response queue out ptr */
2453 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
2454
2455 /* clear SATA error register */
2456 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2457
2458 /* clear any outstanding error interrupts */
2459 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2460
2461 /* unmask all error interrupts */
2462 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
2463
2464 /* enable EDMA machinery */
2465 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2466 return 0;
2467 }
2468
2469 static int
2470 ata_marvell_status(device_t dev)
2471 {
2472 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2473 struct ata_channel *ch = device_get_softc(dev);
2474 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60);
2475 int shift = (ch->unit << 1) + (ch->unit > 3);
2476
2477 /* do we have any errors flagged ? */
2478 if (cause & (1 << shift)) {
2479 struct ata_connect_task *tp;
2480 u_int32_t error =
2481 ATA_INL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch));
2482
2483 /* check for and handle disconnect events */
2484 if ((error & 0x00000008) &&
2485 (tp = (struct ata_connect_task *)
2486 malloc(sizeof(struct ata_connect_task),
2487 M_ATA, M_NOWAIT | M_ZERO))) {
2488
2489 if (bootverbose)
2490 device_printf(ch->dev, "DISCONNECT requested\n");
2491 tp->action = ATA_C_DETACH;
2492 tp->dev = ch->dev;
2493 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
2494 taskqueue_enqueue(taskqueue_thread, &tp->task);
2495 }
2496
2497 /* check for and handle connect events */
2498 if ((error & 0x00000010) &&
2499 (tp = (struct ata_connect_task *)
2500 malloc(sizeof(struct ata_connect_task),
2501 M_ATA, M_NOWAIT | M_ZERO))) {
2502
2503 if (bootverbose)
2504 device_printf(ch->dev, "CONNECT requested\n");
2505 tp->action = ATA_C_ATTACH;
2506 tp->dev = ch->dev;
2507 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
2508 taskqueue_enqueue(taskqueue_thread, &tp->task);
2509 }
2510
2511 /* clear SATA error register */
2512 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2513
2514 /* clear any outstanding error interrupts */
2515 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2516 }
2517
2518 /* do we have any device action ? */
2519 return (cause & (2 << shift));
2520 }
2521
2522 /* must be called with ATA channel locked and state_mtx held */
2523 static int
2524 ata_marvell_begin_transaction(struct ata_request *request)
2525 {
2526 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2527 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2528 u_int32_t req_in;
2529 u_int8_t *bytep;
2530 u_int16_t *wordp;
2531 u_int32_t *quadp;
2532 int i, tag = 0x07;
2533 int dummy, error, slot;
2534
2535 /* only DMA R/W goes through the EMDA machine */
2536 if (request->u.ata.command != ATA_READ_DMA &&
2537 request->u.ata.command != ATA_WRITE_DMA) {
2538
2539 /* disable the EDMA machinery */
2540 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)
2541 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2542 return ata_begin_transaction(request);
2543 }
2544
2545 /* check for 48 bit access and convert if needed */
2546 ata_modify_if_48bit(request);
2547
2548 /* check sanity, setup SG list and DMA engine */
2549 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
2550 request->flags & ATA_R_READ, ch->dma->sg,
2551 &dummy))) {
2552 device_printf(request->dev, "setting up DMA failed\n");
2553 request->result = error;
2554 return ATA_OP_FINISHED;
2555 }
2556
2557 /* get next free request queue slot */
2558 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch));
2559 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f;
2560 bytep = (u_int8_t *)(ch->dma->work);
2561 bytep += (slot << 5);
2562 wordp = (u_int16_t *)bytep;
2563 quadp = (u_int32_t *)bytep;
2564
2565 /* fill in this request */
2566 quadp[0] = (long)ch->dma->sg_bus & 0xffffffff;
2567 quadp[1] = (ch->dma->sg_bus & 0xffffffff00000000ull) >> 32;
2568 wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1);
2569
2570 i = 10;
2571 bytep[i++] = (request->u.ata.count >> 8) & 0xff;
2572 bytep[i++] = 0x10 | ATA_COUNT;
2573 bytep[i++] = request->u.ata.count & 0xff;
2574 bytep[i++] = 0x10 | ATA_COUNT;
2575
2576 bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
2577 bytep[i++] = 0x10 | ATA_SECTOR;
2578 bytep[i++] = request->u.ata.lba & 0xff;
2579 bytep[i++] = 0x10 | ATA_SECTOR;
2580
2581 bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
2582 bytep[i++] = 0x10 | ATA_CYL_LSB;
2583 bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
2584 bytep[i++] = 0x10 | ATA_CYL_LSB;
2585
2586 bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
2587 bytep[i++] = 0x10 | ATA_CYL_MSB;
2588 bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
2589 bytep[i++] = 0x10 | ATA_CYL_MSB;
2590
2591 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf);
2592 bytep[i++] = 0x10 | ATA_DRIVE;
2593
2594 bytep[i++] = request->u.ata.command;
2595 bytep[i++] = 0x90 | ATA_COMMAND;
2596
2597 /* enable EDMA machinery if needed */
2598 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) {
2599 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2600 while (!(ATA_INL(ctlr->r_res1,
2601 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
2602 DELAY(10);
2603 }
2604
2605 /* tell EDMA it has a new request */
2606 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f;
2607 req_in &= 0xfffffc00;
2608 req_in += (slot << 5);
2609 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in);
2610
2611 return ATA_OP_CONTINUES;
2612 }
2613
2614 /* must be called with ATA channel locked and state_mtx held */
2615 static int
2616 ata_marvell_end_transaction(struct ata_request *request)
2617 {
2618 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2619 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2620 int offset = (ch->unit > 3 ? 0x30014 : 0x20014);
2621 u_int32_t icr = ATA_INL(ctlr->r_res1, offset);
2622 int res;
2623
2624 /* EDMA interrupt */
2625 if ((icr & (0x0001 << (ch->unit & 3)))) {
2626 struct ata_marvell_response *response;
2627 u_int32_t rsp_in, rsp_out;
2628 int slot;
2629
2630 /* unload SG list */
2631 ch->dma->unload(ch->dev);
2632
2633 /* stop timeout */
2634 callout_stop(&request->callout);
2635
2636 /* get response ptr's */
2637 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch));
2638 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch));
2639 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f;
2640 rsp_out &= 0xffffff00;
2641 rsp_out += (slot << 3);
2642 response = (struct ata_marvell_response *)
2643 (ch->dma->work + 1024 + (slot << 3));
2644
2645 /* record status for this request */
2646 request->status = response->dev_status;
2647 request->error = 0;
2648
2649 /* ack response */
2650 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out);
2651
2652 /* update progress */
2653 if (!(request->status & ATA_S_ERROR) &&
2654 !(request->flags & ATA_R_TIMEOUT))
2655 request->donecount = request->bytecount;
2656 res = ATA_OP_FINISHED;
2657 }
2658
2659 /* legacy ATA interrupt */
2660 else {
2661 res = ata_end_transaction(request);
2662 }
2663
2664 /* ack interrupt */
2665 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3))));
2666 return res;
2667 }
2668
2669 static void
2670 ata_marvell_reset(device_t dev)
2671 {
2672 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2673 struct ata_channel *ch = device_get_softc(dev);
2674
2675 /* disable the EDMA machinery */
2676 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2677 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
2678 DELAY(10);
2679
2680 /* clear SATA error register */
2681 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2682
2683 /* clear any outstanding error interrupts */
2684 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2685
2686 /* unmask all error interrupts */
2687 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
2688
2689 /* enable channel and test for devices */
2690 ata_sata_phy_enable(ch);
2691
2692 /* enable EDMA machinery */
2693 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2694 }
2695
2696 static void
2697 ata_marvell_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
2698 {
2699 struct ata_dmasetprd_args *args = xsc;
2700 struct ata_marvell_dma_prdentry *prd = args->dmatab;
2701 int i;
2702
2703 if ((args->error = error))
2704 return;
2705
2706 for (i = 0; i < nsegs; i++) {
2707 prd[i].addrlo = htole32(segs[i].ds_addr);
2708 prd[i].addrhi = 0;
2709 prd[i].count = htole32(segs[i].ds_len);
2710 }
2711 prd[i - 1].count |= htole32(ATA_DMA_EOT);
2712 }
2713
2714 static void
2715 ata_marvell_dmainit(device_t dev)
2716 {
2717 struct ata_channel *ch = device_get_softc(dev);
2718
2719 ata_dmainit(dev);
2720 if (ch->dma) {
2721 /* note start and stop are not used here */
2722 ch->dma->setprd = ata_marvell_dmasetprd;
2723 }
2724 }
2725
2726
2727 /*
2728 * National chipset support functions
2729 */
2730 int
2731 ata_national_ident(device_t dev)
2732 {
2733 struct ata_pci_controller *ctlr = device_get_softc(dev);
2734
2735 /* this chip is a clone of the Cyrix chip, bugs and all */
2736 if (pci_get_devid(dev) == ATA_SC1100) {
2737 device_set_desc(dev, "National Geode SC1100 ATA33 controller");
2738 ctlr->chipinit = ata_national_chipinit;
2739 return 0;
2740 }
2741 return ENXIO;
2742 }
2743
2744 static int
2745 ata_national_chipinit(device_t dev)
2746 {
2747 struct ata_pci_controller *ctlr = device_get_softc(dev);
2748
2749 if (ata_setup_interrupt(dev))
2750 return ENXIO;
2751
2752 ctlr->setmode = ata_national_setmode;
2753 return 0;
2754 }
2755
2756 static void
2757 ata_national_setmode(device_t dev, int mode)
2758 {
2759 device_t gparent = GRANDPARENT(dev);
2760 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2761 struct ata_device *atadev = device_get_softc(dev);
2762 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2763 u_int32_t piotiming[] =
2764 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
2765 0x00803020, 0x20102010, 0x00100010,
2766 0x00100010, 0x00100010, 0x00100010 };
2767 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
2768 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
2769 int error;
2770
2771 ch->dma->alignment = 16;
2772 ch->dma->max_iosize = 126 * DEV_BSIZE;
2773
2774 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
2775
2776 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2777
2778 if (bootverbose)
2779 device_printf(dev, "%s setting %s on National chip\n",
2780 (error) ? "failed" : "success", ata_mode2str(mode));
2781 if (!error) {
2782 if (mode >= ATA_UDMA0) {
2783 pci_write_config(gparent, 0x44 + (devno << 3),
2784 udmatiming[mode & ATA_MODE_MASK], 4);
2785 }
2786 else if (mode >= ATA_WDMA0) {
2787 pci_write_config(gparent, 0x44 + (devno << 3),
2788 dmatiming[mode & ATA_MODE_MASK], 4);
2789 }
2790 else {
2791 pci_write_config(gparent, 0x44 + (devno << 3),
2792 pci_read_config(gparent, 0x44 + (devno << 3), 4) |
2793 0x80000000, 4);
2794 }
2795 pci_write_config(gparent, 0x40 + (devno << 3),
2796 piotiming[ata_mode2idx(mode)], 4);
2797 atadev->mode = mode;
2798 }
2799 }
2800
2801
2802 /*
2803 * nVidia chipset support functions
2804 */
2805 int
2806 ata_nvidia_ident(device_t dev)
2807 {
2808 struct ata_pci_controller *ctlr = device_get_softc(dev);
2809 struct ata_chip_id *idx;
2810 static struct ata_chip_id ids[] =
2811 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nForce" },
2812 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2" },
2813 { ATA_NFORCE2_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2 Pro" },
2814 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" },
2815 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3" },
2816 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3 Pro" },
2817 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
2818 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
2819 { ATA_NFORCE_MCP04, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP" },
2820 { ATA_NFORCE_MCP04_S1, 0, 0, NV4, ATA_SA150, "nForce MCP" },
2821 { ATA_NFORCE_MCP04_S2, 0, 0, NV4, ATA_SA150, "nForce MCP" },
2822 { ATA_NFORCE_CK804, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce CK804" },
2823 { ATA_NFORCE_CK804_S1, 0, 0, NV4, ATA_SA300, "nForce CK804" },
2824 { ATA_NFORCE_CK804_S2, 0, 0, NV4, ATA_SA300, "nForce CK804" },
2825 { ATA_NFORCE_MCP51, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP51" },
2826 { ATA_NFORCE_MCP51_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
2827 { ATA_NFORCE_MCP51_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
2828 { ATA_NFORCE_MCP55, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP55" },
2829 { ATA_NFORCE_MCP55_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
2830 { ATA_NFORCE_MCP55_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
2831 { 0, 0, 0, 0, 0, 0}} ;
2832 char buffer[64] ;
2833
2834 if (!(idx = ata_match_chip(dev, ids)))
2835 return ENXIO;
2836
2837 sprintf(buffer, "nVidia %s %s controller",
2838 idx->text, ata_mode2str(idx->max_dma));
2839 device_set_desc_copy(dev, buffer);
2840 ctlr->chip = idx;
2841 ctlr->chipinit = ata_nvidia_chipinit;
2842 return 0;
2843 }
2844
2845 static int
2846 ata_nvidia_chipinit(device_t dev)
2847 {
2848 struct ata_pci_controller *ctlr = device_get_softc(dev);
2849
2850 if (ata_setup_interrupt(dev))
2851 return ENXIO;
2852
2853 if (ctlr->chip->max_dma >= ATA_SA150) {
2854 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1)
2855 ctlr->r_type2 = SYS_RES_IOPORT;
2856 else
2857 ctlr->r_type2 = SYS_RES_MEMORY;
2858 ctlr->r_rid2 = PCIR_BAR(5);
2859 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
2860 &ctlr->r_rid2, RF_ACTIVE))) {
2861 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
2862
2863 ctlr->allocate = ata_nvidia_allocate;
2864 ctlr->reset = ata_nvidia_reset;
2865
2866 /* enable control access */
2867 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1);
2868
2869 if (ctlr->chip->cfg2 & NVQ) {
2870 /* clear interrupt status */
2871 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff);
2872
2873 /* enable device and PHY state change interrupts */
2874 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d);
2875
2876 /* disable NCQ support */
2877 ATA_OUTL(ctlr->r_res2, 0x0400,
2878 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9);
2879 }
2880 else {
2881 /* clear interrupt status */
2882 ATA_OUTB(ctlr->r_res2, offset, 0xff);
2883
2884 /* enable device and PHY state change interrupts */
2885 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd);
2886 }
2887
2888 /* enable PCI interrupt */
2889 pci_write_config(dev, PCIR_COMMAND,
2890 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
2891
2892 }
2893 ctlr->setmode = ata_sata_setmode;
2894 }
2895 else {
2896 /* disable prefetch, postwrite */
2897 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
2898 ctlr->setmode = ata_via_family_setmode;
2899 }
2900 return 0;
2901 }
2902
2903 static int
2904 ata_nvidia_allocate(device_t dev)
2905 {
2906 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2907 struct ata_channel *ch = device_get_softc(dev);
2908
2909 /* setup the usual register normal pci style */
2910 if (ata_pci_allocate(dev))
2911 return ENXIO;
2912
2913 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
2914 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6);
2915 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
2916 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6);
2917 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
2918 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6);
2919
2920 ch->hw.status = ata_nvidia_status;
2921 ch->flags |= ATA_NO_SLAVE;
2922
2923 return 0;
2924 }
2925
2926 static int
2927 ata_nvidia_status(device_t dev)
2928 {
2929 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2930 struct ata_channel *ch = device_get_softc(dev);
2931 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
2932 struct ata_connect_task *tp;
2933 int shift = ch->unit << (ctlr->chip->cfg2 & NVQ ? 4 : 2);
2934 u_int32_t status;
2935
2936 /* get and clear interrupt status */
2937 if (ctlr->chip->cfg2 & NVQ) {
2938 status = ATA_INL(ctlr->r_res2, offset);
2939 ATA_OUTL(ctlr->r_res2, offset, (0x0f << shift) | 0x00f000f0);
2940 }
2941 else {
2942 status = ATA_INB(ctlr->r_res2, offset);
2943 ATA_OUTB(ctlr->r_res2, offset, (0x0f << shift));
2944 }
2945
2946 /* check for and handle connect events */
2947 if (((status & (0x0c << shift)) == (0x04 << shift)) &&
2948 (tp = (struct ata_connect_task *)
2949 malloc(sizeof(struct ata_connect_task),
2950 M_ATA, M_NOWAIT | M_ZERO))) {
2951
2952 if (bootverbose)
2953 device_printf(ch->dev, "CONNECT requested\n");
2954 tp->action = ATA_C_ATTACH;
2955 tp->dev = ch->dev;
2956 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
2957 taskqueue_enqueue(taskqueue_thread, &tp->task);
2958 }
2959
2960 /* check for and handle disconnect events */
2961 if ((status & (0x08 << shift)) &&
2962 !((status & (0x04 << shift) && ATA_IDX_INL(ch, ATA_SSTATUS))) &&
2963 (tp = (struct ata_connect_task *)
2964 malloc(sizeof(struct ata_connect_task),
2965 M_ATA, M_NOWAIT | M_ZERO))) {
2966
2967 if (bootverbose)
2968 device_printf(ch->dev, "DISCONNECT requested\n");
2969 tp->action = ATA_C_DETACH;
2970 tp->dev = ch->dev;
2971 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
2972 taskqueue_enqueue(taskqueue_thread, &tp->task);
2973 }
2974
2975 /* do we have any device action ? */
2976 return (status & (0x01 << shift));
2977 }
2978
2979 static void
2980 ata_nvidia_reset(device_t dev)
2981 {
2982 struct ata_channel *ch = device_get_softc(dev);
2983
2984 ata_sata_phy_enable(ch);
2985 }
2986
2987
2988 /*
2989 * Promise chipset support functions
2990 */
2991 #define ATA_PDC_APKT_OFFSET 0x00000010
2992 #define ATA_PDC_HPKT_OFFSET 0x00000040
2993 #define ATA_PDC_ASG_OFFSET 0x00000080
2994 #define ATA_PDC_LSG_OFFSET 0x000000c0
2995 #define ATA_PDC_HSG_OFFSET 0x00000100
2996 #define ATA_PDC_CHN_OFFSET 0x00000400
2997 #define ATA_PDC_BUF_BASE 0x00400000
2998 #define ATA_PDC_BUF_OFFSET 0x00100000
2999 #define ATA_PDC_MAX_HPKT 8
3000 #define ATA_PDC_WRITE_REG 0x00
3001 #define ATA_PDC_WRITE_CTL 0x0e
3002 #define ATA_PDC_WRITE_END 0x08
3003 #define ATA_PDC_WAIT_NBUSY 0x10
3004 #define ATA_PDC_WAIT_READY 0x18
3005 #define ATA_PDC_1B 0x20
3006 #define ATA_PDC_2B 0x40
3007
3008 struct host_packet {
3009 u_int32_t addr;
3010 TAILQ_ENTRY(host_packet) chain;
3011 };
3012
3013 struct ata_promise_sx4 {
3014 struct mtx mtx;
3015 TAILQ_HEAD(, host_packet) queue;
3016 int busy;
3017 };
3018
3019 int
3020 ata_promise_ident(device_t dev)
3021 {
3022 struct ata_pci_controller *ctlr = device_get_softc(dev);
3023 struct ata_chip_id *idx;
3024 static struct ata_chip_id ids[] =
3025 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "PDC20246" },
3026 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20262" },
3027 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20263" },
3028 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20265" },
3029 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20267" },
3030 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20268" },
3031 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "PDC20269" },
3032 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20270" },
3033 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "PDC20271" },
3034 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "PDC20275" },
3035 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "PDC20276" },
3036 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "PDC20277" },
3037 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "PDC20318" },
3038 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "PDC20319" },
3039 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20371" },
3040 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20375" },
3041 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20376" },
3042 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20377" },
3043 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20378" },
3044 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20379" },
3045 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" },
3046 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" },
3047 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" },
3048 { ATA_PDC20771, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" },
3049 { ATA_PDC40775, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" },
3050 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20617" },
3051 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20618" },
3052 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20619" },
3053 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20620" },
3054 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "PDC20621" },
3055 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "PDC20622" },
3056 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40518" },
3057 { ATA_PDC40519, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40519" },
3058 { ATA_PDC40718, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40718" },
3059 { ATA_PDC40719, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40719" },
3060 { ATA_PDC40779, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40779" },
3061 { 0, 0, 0, 0, 0, 0}};
3062 char buffer[64];
3063 uintptr_t devid = 0;
3064
3065 if (!(idx = ata_match_chip(dev, ids)))
3066 return ENXIO;
3067
3068 /* if we are on a SuperTrak SX6000 dont attach */
3069 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
3070 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
3071 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
3072 devid == ATA_I960RM)
3073 return ENXIO;
3074
3075 strcpy(buffer, "Promise ");
3076 strcat(buffer, idx->text);
3077
3078 /* if we are on a FastTrak TX4, adjust the interrupt resource */
3079 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
3080 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
3081 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
3082 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) {
3083 static long start = 0, end = 0;
3084
3085 if (pci_get_slot(dev) == 1) {
3086 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
3087 strcat(buffer, " (channel 0+1)");
3088 }
3089 else if (pci_get_slot(dev) == 2 && start && end) {
3090 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
3091 strcat(buffer, " (channel 2+3)");
3092 }
3093 else {
3094 start = end = 0;
3095 }
3096 }
3097 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
3098 device_set_desc_copy(dev, buffer);
3099 ctlr->chip = idx;
3100 ctlr->chipinit = ata_promise_chipinit;
3101 return 0;
3102 }
3103
3104 static int
3105 ata_promise_chipinit(device_t dev)
3106 {
3107 struct ata_pci_controller *ctlr = device_get_softc(dev);
3108 int fake_reg, stat_reg;
3109
3110 if (ata_setup_interrupt(dev))
3111 return ENXIO;
3112
3113 switch (ctlr->chip->cfg1) {
3114 case PRNEW:
3115 /* setup clocks */
3116 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a);
3117
3118 ctlr->dmainit = ata_promise_dmainit;
3119 /* FALLTHROUGH */
3120
3121 case PROLD:
3122 /* enable burst mode */
3123 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01);
3124 ctlr->allocate = ata_promise_allocate;
3125 ctlr->setmode = ata_promise_setmode;
3126 return 0;
3127
3128 case PRTX:
3129 ctlr->allocate = ata_promise_tx2_allocate;
3130 ctlr->setmode = ata_promise_setmode;
3131 return 0;
3132
3133 case PRMIO:
3134 ctlr->r_type1 = SYS_RES_MEMORY;
3135 ctlr->r_rid1 = PCIR_BAR(4);
3136 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
3137 &ctlr->r_rid1, RF_ACTIVE)))
3138 goto failnfree;
3139
3140 ctlr->r_type2 = SYS_RES_MEMORY;
3141 ctlr->r_rid2 = PCIR_BAR(3);
3142 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3143 &ctlr->r_rid2, RF_ACTIVE)))
3144 goto failnfree;
3145
3146 if (ctlr->chip->cfg2 == PRSX4X) {
3147 struct ata_promise_sx4 *hpkt;
3148 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080);
3149
3150 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3151 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
3152 ata_promise_sx4_intr, ctlr, &ctlr->handle)) {
3153 device_printf(dev, "unable to setup interrupt\n");
3154 goto failnfree;
3155 }
3156
3157 /* print info about cache memory */
3158 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n",
3159 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4,
3160 ((dimm >> 24) & 0xff),
3161 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ?
3162 " ECC enabled" : "" );
3163
3164 /* adjust cache memory parameters */
3165 ATA_OUTL(ctlr->r_res2, 0x000c000c,
3166 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000));
3167
3168 /* setup host packet controls */
3169 hpkt = malloc(sizeof(struct ata_promise_sx4),
3170 M_TEMP, M_NOWAIT | M_ZERO);
3171 mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF);
3172 TAILQ_INIT(&hpkt->queue);
3173 hpkt->busy = 0;
3174 device_set_ivars(dev, hpkt);
3175 ctlr->allocate = ata_promise_mio_allocate;
3176 ctlr->reset = ata_promise_mio_reset;
3177 ctlr->dmainit = ata_promise_mio_dmainit;
3178 ctlr->setmode = ata_promise_setmode;
3179 ctlr->channels = 4;
3180 return 0;
3181 }
3182
3183 /* mio type controllers need an interrupt intercept */
3184 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3185 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
3186 ata_promise_mio_intr, ctlr, &ctlr->handle)) {
3187 device_printf(dev, "unable to setup interrupt\n");
3188 goto failnfree;
3189 }
3190
3191 switch (ctlr->chip->cfg2) {
3192 case PRPATA:
3193 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) +
3194 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2;
3195 goto sata150;
3196 case PRCMBO:
3197 ctlr->channels = 3;
3198 goto sata150;
3199 case PRSATA:
3200 ctlr->channels = 4;
3201 sata150:
3202 fake_reg = 0x60;
3203 stat_reg = 0x6c;
3204 break;
3205
3206 case PRCMBO2:
3207 ctlr->channels = 3;
3208 goto sataii;
3209 case PRSATA2:
3210 default:
3211 ctlr->channels = 4;
3212 sataii:
3213 fake_reg = 0x54;
3214 stat_reg = 0x60;
3215 break;
3216 }
3217
3218 /* prime fake interrupt register */
3219 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3220
3221 /* clear SATA status */
3222 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff);
3223
3224 ctlr->allocate = ata_promise_mio_allocate;
3225 ctlr->reset = ata_promise_mio_reset;
3226 ctlr->dmainit = ata_promise_mio_dmainit;
3227 ctlr->setmode = ata_promise_mio_setmode;
3228
3229 return 0;
3230 }
3231
3232 failnfree:
3233 if (ctlr->r_res2)
3234 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
3235 if (ctlr->r_res1)
3236 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1);
3237 return ENXIO;
3238 }
3239
3240 static int
3241 ata_promise_allocate(device_t dev)
3242 {
3243 struct ata_channel *ch = device_get_softc(dev);
3244
3245 if (ata_pci_allocate(dev))
3246 return ENXIO;
3247
3248 ch->hw.status = ata_promise_status;
3249 return 0;
3250 }
3251
3252 static int
3253 ata_promise_status(device_t dev)
3254 {
3255 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3256 struct ata_channel *ch = device_get_softc(dev);
3257
3258 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) {
3259 return ata_pci_status(dev);
3260 }
3261 return 0;
3262 }
3263
3264 static int
3265 ata_promise_dmastart(device_t dev)
3266 {
3267 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3268 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3269 struct ata_device *atadev = device_get_softc(dev);
3270
3271 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3272 ATA_OUTB(ctlr->r_res1, 0x11,
3273 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02));
3274 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20,
3275 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) |
3276 (ch->dma->cur_iosize >> 1));
3277 }
3278 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) |
3279 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
3280 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus);
3281 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3282 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) |
3283 ATA_BMCMD_START_STOP);
3284 ch->flags |= ATA_DMA_ACTIVE;
3285 return 0;
3286 }
3287
3288 static int
3289 ata_promise_dmastop(device_t dev)
3290 {
3291 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3292 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3293 struct ata_device *atadev = device_get_softc(dev);
3294 int error;
3295
3296 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3297 ATA_OUTB(ctlr->r_res1, 0x11,
3298 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02));
3299 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0);
3300 }
3301 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT);
3302 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3303 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3304 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3305 ch->flags &= ~ATA_DMA_ACTIVE;
3306 return error;
3307 }
3308
3309 static void
3310 ata_promise_dmareset(device_t dev)
3311 {
3312 struct ata_channel *ch = device_get_softc(dev);
3313
3314 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3315 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3316 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3317 ch->flags &= ~ATA_DMA_ACTIVE;
3318 }
3319
3320 static void
3321 ata_promise_dmainit(device_t dev)
3322 {
3323 struct ata_channel *ch = device_get_softc(dev);
3324
3325 ata_dmainit(dev);
3326 if (ch->dma) {
3327 ch->dma->start = ata_promise_dmastart;
3328 ch->dma->stop = ata_promise_dmastop;
3329 ch->dma->reset = ata_promise_dmareset;
3330 }
3331 }
3332
3333 static void
3334 ata_promise_setmode(device_t dev, int mode)
3335 {
3336 device_t gparent = GRANDPARENT(dev);
3337 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3338 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3339 struct ata_device *atadev = device_get_softc(dev);
3340 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
3341 int error;
3342 u_int32_t timings[][2] = {
3343 /* PROLD PRNEW mode */
3344 { 0x004ff329, 0x004fff2f }, /* PIO 0 */
3345 { 0x004fec25, 0x004ff82a }, /* PIO 1 */
3346 { 0x004fe823, 0x004ff026 }, /* PIO 2 */
3347 { 0x004fe622, 0x004fec24 }, /* PIO 3 */
3348 { 0x004fe421, 0x004fe822 }, /* PIO 4 */
3349 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */
3350 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */
3351 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */
3352 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */
3353 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */
3354 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */
3355 { 0, 0x00424ef6 }, /* UDMA 3 */
3356 { 0, 0x004127f3 }, /* UDMA 4 */
3357 { 0, 0x004127f3 } /* UDMA 5 */
3358 };
3359
3360 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
3361
3362 switch (ctlr->chip->cfg1) {
3363 case PROLD:
3364 case PRNEW:
3365 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) &
3366 (ch->unit ? 1 << 11 : 1 << 10))) {
3367 ata_print_cable(dev, "controller");
3368 mode = ATA_UDMA2;
3369 }
3370 if (ata_atapi(dev) && mode > ATA_PIO_MAX)
3371 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
3372 break;
3373
3374 case PRTX:
3375 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3376 if (mode > ATA_UDMA2 &&
3377 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) {
3378 ata_print_cable(dev, "controller");
3379 mode = ATA_UDMA2;
3380 }
3381 break;
3382
3383 case PRMIO:
3384 if (mode > ATA_UDMA2 &&
3385 (ATA_INL(ctlr->r_res2,
3386 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) +
3387 (ch->unit << 7)) & 0x01000000)) {
3388 ata_print_cable(dev, "controller");
3389 mode = ATA_UDMA2;
3390 }
3391 break;
3392 }
3393
3394 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3395
3396 if (bootverbose)
3397 device_printf(dev, "%ssetting %s on %s chip\n",
3398 (error) ? "FAILURE " : "",
3399 ata_mode2str(mode), ctlr->chip->text);
3400 if (!error) {
3401 if (ctlr->chip->cfg1 < PRTX)
3402 pci_write_config(gparent, 0x60 + (devno << 2),
3403 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
3404 atadev->mode = mode;
3405 }
3406 return;
3407 }
3408
3409 static int
3410 ata_promise_tx2_allocate(device_t dev)
3411 {
3412 struct ata_channel *ch = device_get_softc(dev);
3413
3414 if (ata_pci_allocate(dev))
3415 return ENXIO;
3416
3417 ch->hw.status = ata_promise_tx2_status;
3418 return 0;
3419 }
3420
3421 static int
3422 ata_promise_tx2_status(device_t dev)
3423 {
3424 struct ata_channel *ch = device_get_softc(dev);
3425
3426 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3427 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
3428 return ata_pci_status(dev);
3429 }
3430 return 0;
3431 }
3432
3433 static int
3434 ata_promise_mio_allocate(device_t dev)
3435 {
3436 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3437 struct ata_channel *ch = device_get_softc(dev);
3438 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0;
3439 int i;
3440
3441 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
3442 ch->r_io[i].res = ctlr->r_res2;
3443 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7);
3444 }
3445 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
3446 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7);
3447 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
3448 ata_default_registers(dev);
3449 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) ||
3450 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2)) {
3451 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3452 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8);
3453 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3454 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8);
3455 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3456 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8);
3457 ch->flags |= ATA_NO_SLAVE;
3458 }
3459 ch->flags |= ATA_USE_16BIT;
3460
3461 ata_generic_hw(dev);
3462 if (ctlr->chip->cfg2 & PRSX4X) {
3463 ch->hw.command = ata_promise_sx4_command;
3464 }
3465 else {
3466 ch->hw.command = ata_promise_mio_command;
3467 ch->hw.status = ata_promise_mio_status;
3468 }
3469 return 0;
3470 }
3471
3472 static void
3473 ata_promise_mio_intr(void *data)
3474 {
3475 struct ata_pci_controller *ctlr = data;
3476 struct ata_channel *ch;
3477 u_int32_t vector;
3478 int unit, fake_reg;
3479
3480 switch (ctlr->chip->cfg2) {
3481 case PRPATA:
3482 case PRCMBO:
3483 case PRSATA:
3484 fake_reg = 0x60;
3485 break;
3486 case PRCMBO2:
3487 case PRSATA2:
3488 default:
3489 fake_reg = 0x54;
3490 break;
3491 }
3492
3493 /*
3494 * since reading interrupt status register on early "mio" chips
3495 * clears the status bits we cannot read it for each channel later on
3496 * in the generic interrupt routine.
3497 * store the bits in an unused register in the chip so we can read
3498 * it from there safely to get around this "feature".
3499 */
3500 vector = ATA_INL(ctlr->r_res2, 0x040);
3501 ATA_OUTL(ctlr->r_res2, 0x040, vector);
3502 ATA_OUTL(ctlr->r_res2, fake_reg, vector);
3503
3504 for (unit = 0; unit < ctlr->channels; unit++) {
3505 if ((ch = ctlr->interrupt[unit].argument))
3506 ctlr->interrupt[unit].function(ch);
3507 }
3508
3509 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3510 }
3511
3512 static int
3513 ata_promise_mio_status(device_t dev)
3514 {
3515 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3516 struct ata_channel *ch = device_get_softc(dev);
3517 struct ata_connect_task *tp;
3518 u_int32_t fake_reg, stat_reg, vector, status;
3519
3520 switch (ctlr->chip->cfg2) {
3521 case PRPATA:
3522 case PRCMBO:
3523 case PRSATA:
3524 fake_reg = 0x60;
3525 stat_reg = 0x6c;
3526 break;
3527 case PRCMBO2:
3528 case PRSATA2:
3529 default:
3530 fake_reg = 0x54;
3531 stat_reg = 0x60;
3532 break;
3533 }
3534
3535 /* read and acknowledge interrupt */
3536 vector = ATA_INL(ctlr->r_res2, fake_reg);
3537
3538 /* read and clear interface status */
3539 status = ATA_INL(ctlr->r_res2, stat_reg);
3540 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit));
3541
3542 /* check for and handle disconnect events */
3543 if ((status & (0x00000001 << ch->unit)) &&
3544 (tp = (struct ata_connect_task *)
3545 malloc(sizeof(struct ata_connect_task),
3546 M_ATA, M_NOWAIT | M_ZERO))) {
3547
3548 if (bootverbose)
3549 device_printf(ch->dev, "DISCONNECT requested\n");
3550 tp->action = ATA_C_DETACH;
3551 tp->dev = ch->dev;
3552 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3553 taskqueue_enqueue(taskqueue_thread, &tp->task);
3554 }
3555
3556 /* check for and handle connect events */
3557 if ((status & (0x00000010 << ch->unit)) &&
3558 (tp = (struct ata_connect_task *)
3559 malloc(sizeof(struct ata_connect_task),
3560 M_ATA, M_NOWAIT | M_ZERO))) {
3561
3562 if (bootverbose)
3563 device_printf(ch->dev, "CONNECT requested\n");
3564 tp->action = ATA_C_ATTACH;
3565 tp->dev = ch->dev;
3566 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3567 taskqueue_enqueue(taskqueue_thread, &tp->task);
3568 }
3569
3570 /* do we have any device action ? */
3571 return (vector & (1 << (ch->unit + 1)));
3572 }
3573
3574 static int
3575 ata_promise_mio_command(struct ata_request *request)
3576 {
3577 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
3578 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
3579 u_int32_t *wordp = (u_int32_t *)ch->dma->work;
3580
3581 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001);
3582
3583 /* XXX SOS add ATAPI commands support later */
3584 switch (request->u.ata.command) {
3585 default:
3586 return ata_generic_command(request);
3587
3588 case ATA_READ_DMA:
3589 case ATA_READ_DMA48:
3590 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24));
3591 break;
3592
3593 case ATA_WRITE_DMA:
3594 case ATA_WRITE_DMA48:
3595 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24));
3596 break;
3597 }
3598 wordp[1] = htole32(ch->dma->sg_bus);
3599 wordp[2] = 0;
3600 ata_promise_apkt((u_int8_t*)wordp, request);
3601
3602 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma->work_bus);
3603 return 0;
3604 }
3605
3606 static void
3607 ata_promise_mio_reset(device_t dev)
3608 {
3609 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3610 struct ata_channel *ch = device_get_softc(dev);
3611 struct ata_promise_sx4 *hpktp;
3612
3613 switch (ctlr->chip->cfg2) {
3614 case PRSX4X:
3615
3616 /* softreset channel ATA module */
3617 hpktp = device_get_ivars(ctlr->dev);
3618 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1);
3619 ata_udelay(1000);
3620 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7),
3621 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) &
3622 ~0x00003f9f) | (ch->unit + 1));
3623
3624 /* softreset HOST module */ /* XXX SOS what about other outstandings */
3625 mtx_lock(&hpktp->mtx);
3626 ATA_OUTL(ctlr->r_res2, 0xc012c,
3627 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11));
3628 DELAY(10);
3629 ATA_OUTL(ctlr->r_res2, 0xc012c,
3630 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f));
3631 hpktp->busy = 0;
3632 mtx_unlock(&hpktp->mtx);
3633 ata_generic_reset(dev);
3634 break;
3635
3636 case PRPATA:
3637 case PRCMBO:
3638 case PRSATA:
3639 if ((ctlr->chip->cfg2 == PRSATA) ||
3640 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
3641
3642 /* mask plug/unplug intr */
3643 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit));
3644 }
3645
3646 /* softreset channels ATA module */
3647 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
3648 ata_udelay(10000);
3649 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
3650 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
3651 ~0x00003f9f) | (ch->unit + 1));
3652
3653 if ((ctlr->chip->cfg2 == PRSATA) ||
3654 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
3655
3656 ata_sata_phy_enable(ch);
3657
3658 /* reset and enable plug/unplug intr */
3659 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit));
3660 }
3661 else
3662 ata_generic_reset(dev);
3663 break;
3664
3665 case PRCMBO2:
3666 case PRSATA2:
3667 if ((ctlr->chip->cfg2 == PRSATA2) ||
3668 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
3669 /* set portmultiplier port */
3670 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f);
3671
3672 /* mask plug/unplug intr */
3673 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit));
3674 }
3675
3676 /* softreset channels ATA module */
3677 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
3678 ata_udelay(10000);
3679 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
3680 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
3681 ~0x00003f9f) | (ch->unit + 1));
3682
3683 if ((ctlr->chip->cfg2 == PRSATA2) ||
3684 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
3685
3686 /* set PHY mode to "improved" */
3687 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8),
3688 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) &
3689 ~0x00000003) | 0x00000001);
3690
3691 ata_sata_phy_enable(ch);
3692
3693 /* reset and enable plug/unplug intr */
3694 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit));
3695
3696 /* set portmultiplier port */
3697 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00);
3698 }
3699 else
3700 ata_generic_reset(dev);
3701 break;
3702
3703 }
3704 }
3705
3706 static void
3707 ata_promise_mio_dmainit(device_t dev)
3708 {
3709 /* note start and stop are not used here */
3710 ata_dmainit(dev);
3711 }
3712
3713 static void
3714 ata_promise_mio_setmode(device_t dev, int mode)
3715 {
3716 device_t gparent = GRANDPARENT(dev);
3717 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3718 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3719
3720 if ( (ctlr->chip->cfg2 == PRSATA) ||
3721 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2)) ||
3722 (ctlr->chip->cfg2 == PRSATA2) ||
3723 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2)))
3724 ata_sata_setmode(dev, mode);
3725 else
3726 ata_promise_setmode(dev, mode);
3727 }
3728
3729 static void
3730 ata_promise_sx4_intr(void *data)
3731 {
3732 struct ata_pci_controller *ctlr = data;
3733 struct ata_channel *ch;
3734 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480);
3735 int unit;
3736
3737 for (unit = 0; unit < ctlr->channels; unit++) {
3738 if (vector & (1 << (unit + 1)))
3739 if ((ch = ctlr->interrupt[unit].argument))
3740 ctlr->interrupt[unit].function(ch);
3741 if (vector & (1 << (unit + 5)))
3742 if ((ch = ctlr->interrupt[unit].argument))
3743 ata_promise_queue_hpkt(ctlr,
3744 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
3745 ATA_PDC_HPKT_OFFSET));
3746 if (vector & (1 << (unit + 9))) {
3747 ata_promise_next_hpkt(ctlr);
3748 if ((ch = ctlr->interrupt[unit].argument))
3749 ctlr->interrupt[unit].function(ch);
3750 }
3751 if (vector & (1 << (unit + 13))) {
3752 ata_promise_next_hpkt(ctlr);
3753 if ((ch = ctlr->interrupt[unit].argument))
3754 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
3755 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
3756 ATA_PDC_APKT_OFFSET));
3757 }
3758 }
3759 }
3760
3761 static int
3762 ata_promise_sx4_command(struct ata_request *request)
3763 {
3764 device_t gparent = GRANDPARENT(request->dev);
3765 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3766 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
3767 struct ata_dma_prdentry *prd = ch->dma->sg;
3768 caddr_t window = rman_get_virtual(ctlr->r_res1);
3769 u_int32_t *wordp;
3770 int i, idx, length = 0;
3771
3772 /* XXX SOS add ATAPI commands support later */
3773 switch (request->u.ata.command) {
3774
3775 default:
3776 return -1;
3777
3778 case ATA_ATA_IDENTIFY:
3779 case ATA_READ:
3780 case ATA_READ48:
3781 case ATA_READ_MUL:
3782 case ATA_READ_MUL48:
3783 case ATA_WRITE:
3784 case ATA_WRITE48:
3785 case ATA_WRITE_MUL:
3786 case ATA_WRITE_MUL48:
3787 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
3788 return ata_generic_command(request);
3789
3790 case ATA_SETFEATURES:
3791 case ATA_FLUSHCACHE:
3792 case ATA_FLUSHCACHE48:
3793 case ATA_SLEEP:
3794 case ATA_SET_MULTI:
3795 wordp = (u_int32_t *)
3796 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
3797 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24));
3798 wordp[1] = 0;
3799 wordp[2] = 0;
3800 ata_promise_apkt((u_int8_t *)wordp, request);
3801 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
3802 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
3803 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
3804 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET));
3805 return 0;
3806
3807 case ATA_READ_DMA:
3808 case ATA_READ_DMA48:
3809 case ATA_WRITE_DMA:
3810 case ATA_WRITE_DMA48:
3811 wordp = (u_int32_t *)
3812 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET);
3813 i = idx = 0;
3814 do {
3815 wordp[idx++] = prd[i].addr;
3816 wordp[idx++] = prd[i].count;
3817 length += (prd[i].count & ~ATA_DMA_EOT);
3818 } while (!(prd[i++].count & ATA_DMA_EOT));
3819
3820 wordp = (u_int32_t *)
3821 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET);
3822 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
3823 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
3824
3825 wordp = (u_int32_t *)
3826 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET);
3827 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
3828 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
3829
3830 wordp = (u_int32_t *)
3831 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET);
3832 if (request->flags & ATA_R_READ)
3833 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24));
3834 if (request->flags & ATA_R_WRITE)
3835 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24));
3836 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET);
3837 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET);
3838 wordp[3] = 0;
3839
3840 wordp = (u_int32_t *)
3841 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
3842 if (request->flags & ATA_R_READ)
3843 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24));
3844 if (request->flags & ATA_R_WRITE)
3845 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24));
3846 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET);
3847 wordp[2] = 0;
3848 ata_promise_apkt((u_int8_t *)wordp, request);
3849 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
3850
3851 if (request->flags & ATA_R_READ) {
3852 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001);
3853 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001);
3854 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
3855 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET));
3856 }
3857 if (request->flags & ATA_R_WRITE) {
3858 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001);
3859 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001);
3860 ata_promise_queue_hpkt(ctlr,
3861 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET));
3862 }
3863 return 0;
3864 }
3865 }
3866
3867 static int
3868 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request)
3869 {
3870 struct ata_device *atadev = device_get_softc(request->dev);
3871 int i = 12;
3872
3873 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE;
3874 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit;
3875 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL;
3876 bytep[i++] = ATA_A_4BIT;
3877
3878 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3879 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE;
3880 bytep[i++] = request->u.ata.feature >> 8;
3881 bytep[i++] = request->u.ata.feature;
3882 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT;
3883 bytep[i++] = request->u.ata.count >> 8;
3884 bytep[i++] = request->u.ata.count;
3885 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR;
3886 bytep[i++] = request->u.ata.lba >> 24;
3887 bytep[i++] = request->u.ata.lba;
3888 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
3889 bytep[i++] = request->u.ata.lba >> 32;
3890 bytep[i++] = request->u.ata.lba >> 8;
3891 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
3892 bytep[i++] = request->u.ata.lba >> 40;
3893 bytep[i++] = request->u.ata.lba >> 16;
3894 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
3895 bytep[i++] = ATA_D_LBA | atadev->unit;
3896 }
3897 else {
3898 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE;
3899 bytep[i++] = request->u.ata.feature;
3900 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT;
3901 bytep[i++] = request->u.ata.count;
3902 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR;
3903 bytep[i++] = request->u.ata.lba;
3904 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
3905 bytep[i++] = request->u.ata.lba >> 8;
3906 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
3907 bytep[i++] = request->u.ata.lba >> 16;
3908 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
3909 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) |
3910 ATA_D_IBM | atadev->unit | ((request->u.ata.lba >> 24)&0xf);
3911 }
3912 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND;
3913 bytep[i++] = request->u.ata.command;
3914 return i;
3915 }
3916
3917 static void
3918 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt)
3919 {
3920 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
3921
3922 mtx_lock(&hpktp->mtx);
3923 if (hpktp->busy) {
3924 struct host_packet *hp =
3925 malloc(sizeof(struct host_packet), M_TEMP, M_NOWAIT | M_ZERO);
3926 hp->addr = hpkt;
3927 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain);
3928 }
3929 else {
3930 hpktp->busy = 1;
3931 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt);
3932 }
3933 mtx_unlock(&hpktp->mtx);
3934 }
3935
3936 static void
3937 ata_promise_next_hpkt(struct ata_pci_controller *ctlr)
3938 {
3939 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
3940 struct host_packet *hp;
3941
3942 mtx_lock(&hpktp->mtx);
3943 if ((hp = TAILQ_FIRST(&hpktp->queue))) {
3944 TAILQ_REMOVE(&hpktp->queue, hp, chain);
3945 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr);
3946 free(hp, M_TEMP);
3947 }
3948 else
3949 hpktp->busy = 0;
3950 mtx_unlock(&hpktp->mtx);
3951 }
3952
3953
3954 /*
3955 * ServerWorks chipset support functions
3956 */
3957 int
3958 ata_serverworks_ident(device_t dev)
3959 {
3960 struct ata_pci_controller *ctlr = device_get_softc(dev);
3961 struct ata_chip_id *idx;
3962 static struct ata_chip_id ids[] =
3963 {{ ATA_ROSB4, 0x00, SWKS33, 0, ATA_UDMA2, "ROSB4" },
3964 { ATA_CSB5, 0x92, SWKS100, 0, ATA_UDMA5, "CSB5" },
3965 { ATA_CSB5, 0x00, SWKS66, 0, ATA_UDMA4, "CSB5" },
3966 { ATA_CSB6, 0x00, SWKS100, 0, ATA_UDMA5, "CSB6" },
3967 { ATA_CSB6_1, 0x00, SWKS66, 0, ATA_UDMA4, "CSB6" },
3968 { ATA_HT1000, 0x00, SWKS100, 0, ATA_UDMA5, "HT1000" },
3969 { ATA_HT1000_S1, 0x00, SWKS100, 4, ATA_SA150, "HT1000" },
3970 { ATA_HT1000_S2, 0x00, SWKSMIO, 4, ATA_SA150, "HT1000" },
3971 { ATA_K2, 0x00, SWKSMIO, 4, ATA_SA150, "K2" },
3972 { ATA_FRODO4, 0x00, SWKSMIO, 4, ATA_SA150, "Frodo4" },
3973 { ATA_FRODO8, 0x00, SWKSMIO, 8, ATA_SA150, "Frodo8" },
3974 { 0, 0, 0, 0, 0, 0}};
3975 char buffer[64];
3976
3977 if (!(idx = ata_match_chip(dev, ids)))
3978 return ENXIO;
3979
3980 sprintf(buffer, "ServerWorks %s %s controller",
3981 idx->text, ata_mode2str(idx->max_dma));
3982 device_set_desc_copy(dev, buffer);
3983 ctlr->chip = idx;
3984 ctlr->chipinit = ata_serverworks_chipinit;
3985 return 0;
3986 }
3987
3988 static int
3989 ata_serverworks_chipinit(device_t dev)
3990 {
3991 struct ata_pci_controller *ctlr = device_get_softc(dev);
3992
3993 if (ata_setup_interrupt(dev))
3994 return ENXIO;
3995
3996 if (ctlr->chip->cfg1 == SWKSMIO) {
3997 ctlr->r_type2 = SYS_RES_MEMORY;
3998 ctlr->r_rid2 = PCIR_BAR(5);
3999 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4000 &ctlr->r_rid2, RF_ACTIVE)))
4001 return ENXIO;
4002
4003 ctlr->channels = ctlr->chip->cfg2;
4004 ctlr->allocate = ata_serverworks_allocate;
4005 ctlr->setmode = ata_sata_setmode;
4006 return 0;
4007 }
4008 else if (ctlr->chip->cfg1 == SWKS33) {
4009 device_t *children;
4010 int nchildren, i;
4011
4012 /* locate the ISA part in the southbridge and enable UDMA33 */
4013 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
4014 for (i = 0; i < nchildren; i++) {
4015 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
4016 pci_write_config(children[i], 0x64,
4017 (pci_read_config(children[i], 0x64, 4) &
4018 ~0x00002000) | 0x00004000, 4);
4019 break;
4020 }
4021 }
4022 free(children, M_TEMP);
4023 }
4024 }
4025 else {
4026 pci_write_config(dev, 0x5a,
4027 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
4028 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1);
4029 }
4030 ctlr->setmode = ata_serverworks_setmode;
4031 return 0;
4032 }
4033
4034 static int
4035 ata_serverworks_allocate(device_t dev)
4036 {
4037 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4038 struct ata_channel *ch = device_get_softc(dev);
4039 int ch_offset;
4040 int i;
4041
4042 ch_offset = ch->unit * 0x100;
4043
4044 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
4045 ch->r_io[i].res = ctlr->r_res2;
4046
4047 /* setup ATA registers */
4048 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
4049 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04;
4050 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
4051 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
4052 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
4053 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
4054 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
4055 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c;
4056 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20;
4057 ata_default_registers(dev);
4058
4059 /* setup DMA registers */
4060 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30;
4061 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32;
4062 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34;
4063
4064 /* setup SATA registers */
4065 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40;
4066 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44;
4067 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48;
4068
4069 ch->flags |= ATA_NO_SLAVE;
4070 ata_pci_hw(dev);
4071 return 0;
4072 }
4073
4074 static void
4075 ata_serverworks_setmode(device_t dev, int mode)
4076 {
4077 device_t gparent = GRANDPARENT(dev);
4078 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4079 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4080 struct ata_device *atadev = device_get_softc(dev);
4081 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4082 int offset = (devno ^ 0x01) << 3;
4083 int error;
4084 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
4085 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
4086 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
4087
4088 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4089
4090 mode = ata_check_80pin(dev, mode);
4091
4092 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4093
4094 if (bootverbose)
4095 device_printf(dev, "%ssetting %s on %s chip\n",
4096 (error) ? "FAILURE " : "",
4097 ata_mode2str(mode), ctlr->chip->text);
4098 if (!error) {
4099 if (mode >= ATA_UDMA0) {
4100 pci_write_config(gparent, 0x56,
4101 (pci_read_config(gparent, 0x56, 2) &
4102 ~(0xf << (devno << 2))) |
4103 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
4104 pci_write_config(gparent, 0x54,
4105 pci_read_config(gparent, 0x54, 1) |
4106 (0x01 << devno), 1);
4107 pci_write_config(gparent, 0x44,
4108 (pci_read_config(gparent, 0x44, 4) &
4109 ~(0xff << offset)) |
4110 (dmatimings[2] << offset), 4);
4111 }
4112 else if (mode >= ATA_WDMA0) {
4113 pci_write_config(gparent, 0x54,
4114 pci_read_config(gparent, 0x54, 1) &
4115 ~(0x01 << devno), 1);
4116 pci_write_config(gparent, 0x44,
4117 (pci_read_config(gparent, 0x44, 4) &
4118 ~(0xff << offset)) |
4119 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
4120 }
4121 else
4122 pci_write_config(gparent, 0x54,
4123 pci_read_config(gparent, 0x54, 1) &
4124 ~(0x01 << devno), 1);
4125
4126 pci_write_config(gparent, 0x40,
4127 (pci_read_config(gparent, 0x40, 4) &
4128 ~(0xff << offset)) |
4129 (piotimings[ata_mode2idx(mode)] << offset), 4);
4130 atadev->mode = mode;
4131 }
4132 }
4133
4134
4135 /*
4136 * Silicon Image Inc. (SiI) (former CMD) chipset support functions
4137 */
4138 int
4139 ata_sii_ident(device_t dev)
4140 {
4141 struct ata_pci_controller *ctlr = device_get_softc(dev);
4142 struct ata_chip_id *idx;
4143 static struct ata_chip_id ids[] =
4144 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" },
4145 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" },
4146 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
4147 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
4148 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" },
4149 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
4150 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
4151 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" },
4152 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" },
4153 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" },
4154 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" },
4155 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" },
4156 { 0, 0, 0, 0, 0, 0}};
4157 char buffer[64];
4158
4159 if (!(idx = ata_match_chip(dev, ids)))
4160 return ENXIO;
4161
4162 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
4163 device_set_desc_copy(dev, buffer);
4164 ctlr->chip = idx;
4165 ctlr->chipinit = ata_sii_chipinit;
4166 return 0;
4167 }
4168
4169 static int
4170 ata_sii_chipinit(device_t dev)
4171 {
4172 struct ata_pci_controller *ctlr = device_get_softc(dev);
4173
4174 if (ata_setup_interrupt(dev))
4175 return ENXIO;
4176
4177 if (ctlr->chip->cfg1 == SIIMEMIO) {
4178 ctlr->r_type2 = SYS_RES_MEMORY;
4179 ctlr->r_rid2 = PCIR_BAR(5);
4180 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4181 &ctlr->r_rid2, RF_ACTIVE)))
4182 return ENXIO;
4183
4184 if (ctlr->chip->cfg2 & SIISETCLK) {
4185 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4186 pci_write_config(dev, 0x8a,
4187 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
4188 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4189 device_printf(dev, "%s could not set ATA133 clock\n",
4190 ctlr->chip->text);
4191 }
4192
4193 /* if we have 4 channels enable the second set */
4194 if (ctlr->chip->cfg2 & SII4CH) {
4195 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
4196 ctlr->channels = 4;
4197 }
4198
4199 /* enable PCI interrupt as BIOS might not */
4200 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
4201
4202 /* dont block interrupts from any channel */
4203 pci_write_config(dev, 0x48,
4204 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
4205
4206 ctlr->allocate = ata_sii_allocate;
4207 if (ctlr->chip->max_dma >= ATA_SA150) {
4208 ctlr->reset = ata_sii_reset;
4209 ctlr->setmode = ata_sata_setmode;
4210 }
4211 else
4212 ctlr->setmode = ata_sii_setmode;
4213 }
4214 else {
4215 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
4216 device_printf(dev, "HW has secondary channel disabled\n");
4217 ctlr->channels = 1;
4218 }
4219
4220 /* enable interrupt as BIOS might not */
4221 pci_write_config(dev, 0x71, 0x01, 1);
4222
4223 ctlr->allocate = ata_cmd_allocate;
4224 ctlr->setmode = ata_cmd_setmode;
4225 }
4226 return 0;
4227 }
4228
4229 static int
4230 ata_cmd_allocate(device_t dev)
4231 {
4232 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4233 struct ata_channel *ch = device_get_softc(dev);
4234
4235 /* setup the usual register normal pci style */
4236 if (ata_pci_allocate(dev))
4237 return ENXIO;
4238
4239 if (ctlr->chip->cfg2 & SIIINTR)
4240 ch->hw.status = ata_cmd_status;
4241
4242 return 0;
4243 }
4244
4245 static int
4246 ata_cmd_status(device_t dev)
4247 {
4248 struct ata_channel *ch = device_get_softc(dev);
4249 u_int8_t reg71;
4250
4251 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
4252 (ch->unit ? 0x08 : 0x04))) {
4253 pci_write_config(device_get_parent(ch->dev), 0x71,
4254 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
4255 return ata_pci_status(dev);
4256 }
4257 return 0;
4258 }
4259
4260 static void
4261 ata_cmd_setmode(device_t dev, int mode)
4262 {
4263 device_t gparent = GRANDPARENT(dev);
4264 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4265 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4266 struct ata_device *atadev = device_get_softc(dev);
4267 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4268 int error;
4269
4270 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4271
4272 mode = ata_check_80pin(dev, mode);
4273
4274 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4275
4276 if (bootverbose)
4277 device_printf(dev, "%ssetting %s on %s chip\n",
4278 (error) ? "FAILURE " : "",
4279 ata_mode2str(mode), ctlr->chip->text);
4280 if (!error) {
4281 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
4282 int ureg = ch->unit ? 0x7b : 0x73;
4283
4284 if (mode >= ATA_UDMA0) {
4285 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
4286 { 0x11, 0x42 }, { 0x25, 0x8a },
4287 { 0x15, 0x4a }, { 0x05, 0x0a } };
4288
4289 u_int8_t umode = pci_read_config(gparent, ureg, 1);
4290
4291 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
4292 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)];
4293 pci_write_config(gparent, ureg, umode, 1);
4294 }
4295 else if (mode >= ATA_WDMA0) {
4296 int dmatimings[] = { 0x87, 0x32, 0x3f };
4297
4298 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1);
4299 pci_write_config(gparent, ureg,
4300 pci_read_config(gparent, ureg, 1) &
4301 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4302 }
4303 else {
4304 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
4305 pci_write_config(gparent, treg,
4306 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
4307 pci_write_config(gparent, ureg,
4308 pci_read_config(gparent, ureg, 1) &
4309 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4310 }
4311 atadev->mode = mode;
4312 }
4313 }
4314
4315 static int
4316 ata_sii_allocate(device_t dev)
4317 {
4318 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4319 struct ata_channel *ch = device_get_softc(dev);
4320 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
4321 int i;
4322
4323 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
4324 ch->r_io[i].res = ctlr->r_res2;
4325 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
4326 }
4327 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
4328 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
4329 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
4330 ata_default_registers(dev);
4331
4332 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
4333 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
4334 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
4335 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
4336 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
4337 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
4338 ch->r_io[ATA_BMDEVSPEC_0].res = ctlr->r_res2;
4339 ch->r_io[ATA_BMDEVSPEC_0].offset = 0xa1 + (unit01 << 6) + (unit10 << 8);
4340
4341 if (ctlr->chip->max_dma >= ATA_SA150) {
4342 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4343 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
4344 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4345 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
4346 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4347 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
4348 ch->flags |= ATA_NO_SLAVE;
4349
4350 /* enable PHY state change interrupt */
4351 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
4352 }
4353
4354 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) {
4355 /* work around errata in early chips */
4356 ch->dma->boundary = 16 * DEV_BSIZE;
4357 ch->dma->segsize = 15 * DEV_BSIZE;
4358 }
4359
4360 ata_pci_hw(dev);
4361 ch->hw.status = ata_sii_status;
4362 return 0;
4363 }
4364
4365 static int
4366 ata_sii_status(device_t dev)
4367 {
4368 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4369 struct ata_channel *ch = device_get_softc(dev);
4370
4371 /* check for PHY related interrupts on SATA capable HW */
4372 if (ctlr->chip->max_dma >= ATA_SA150) {
4373 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS);
4374 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR);
4375 struct ata_connect_task *tp;
4376
4377 if (error) {
4378 /* clear error bits/interrupt */
4379 ATA_IDX_OUTL(ch, ATA_SERROR, error);
4380
4381 /* if we have a connection event deal with it */
4382 if ((error & ATA_SE_PHY_CHANGED) &&
4383 (tp = (struct ata_connect_task *)
4384 malloc(sizeof(struct ata_connect_task),
4385 M_ATA, M_NOWAIT | M_ZERO))) {
4386
4387 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) {
4388 if (bootverbose)
4389 device_printf(ch->dev, "CONNECT requested\n");
4390 tp->action = ATA_C_ATTACH;
4391 }
4392 else {
4393 if (bootverbose)
4394 device_printf(ch->dev, "DISCONNECT requested\n");
4395 tp->action = ATA_C_DETACH;
4396 }
4397 tp->dev = ch->dev;
4398 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
4399 taskqueue_enqueue(taskqueue_thread, &tp->task);
4400 }
4401 }
4402 }
4403
4404 /* any drive action to take care of ? */
4405 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_0) & 0x08)
4406 return ata_pci_status(dev);
4407 else
4408 return 0;
4409 }
4410
4411 static void
4412 ata_sii_reset(device_t dev)
4413 {
4414 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4415 struct ata_channel *ch = device_get_softc(dev);
4416 int offset = ((ch->unit & 1) << 7) + ((ch->unit & 2) << 8);
4417
4418 /* disable PHY state change interrupt */
4419 ATA_OUTL(ctlr->r_res2, 0x148 + offset, ~(1 << 16));
4420
4421 /* reset controller part for this channel */
4422 ATA_OUTL(ctlr->r_res2, 0x48,
4423 ATA_INL(ctlr->r_res2, 0x48) | (0xc0 >> ch->unit));
4424 DELAY(1000);
4425 ATA_OUTL(ctlr->r_res2, 0x48,
4426 ATA_INL(ctlr->r_res2, 0x48) & ~(0xc0 >> ch->unit));
4427
4428 ata_sata_phy_enable(ch);
4429
4430 /* enable PHY state change interrupt */
4431 ATA_OUTL(ctlr->r_res2, 0x148 + offset, (1 << 16));
4432 }
4433
4434 static void
4435 ata_sii_setmode(device_t dev, int mode)
4436 {
4437 device_t gparent = GRANDPARENT(dev);
4438 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4439 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4440 struct ata_device *atadev = device_get_softc(dev);
4441 int rego = (ch->unit << 4) + (ATA_DEV(atadev->unit) << 1);
4442 int mreg = ch->unit ? 0x84 : 0x80;
4443 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2);
4444 int mval = pci_read_config(gparent, mreg, 1) & ~mask;
4445 int error;
4446
4447 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4448
4449 if (ctlr->chip->cfg2 & SIISETCLK) {
4450 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) &
4451 (ch->unit ? 0x02 : 0x01))) {
4452 ata_print_cable(dev, "controller");
4453 mode = ATA_UDMA2;
4454 }
4455 }
4456 else
4457 mode = ata_check_80pin(dev, mode);
4458
4459 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4460
4461 if (bootverbose)
4462 device_printf(dev, "%ssetting %s on %s chip\n",
4463 (error) ? "FAILURE " : "",
4464 ata_mode2str(mode), ctlr->chip->text);
4465 if (error)
4466 return;
4467
4468 if (mode >= ATA_UDMA0) {
4469 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
4470 u_int8_t ureg = 0xac + rego;
4471
4472 pci_write_config(gparent, mreg,
4473 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1);
4474 pci_write_config(gparent, ureg,
4475 (pci_read_config(gparent, ureg, 1) & ~0x3f) |
4476 udmatimings[mode & ATA_MODE_MASK], 1);
4477
4478 }
4479 else if (mode >= ATA_WDMA0) {
4480 u_int8_t dreg = 0xa8 + rego;
4481 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
4482
4483 pci_write_config(gparent, mreg,
4484 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1);
4485 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
4486
4487 }
4488 else {
4489 u_int8_t preg = 0xa4 + rego;
4490 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
4491
4492 pci_write_config(gparent, mreg,
4493 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1);
4494 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2);
4495 }
4496 atadev->mode = mode;
4497 }
4498
4499
4500 /*
4501 * Silicon Integrated Systems Corp. (SiS) chipset support functions
4502 */
4503 int
4504 ata_sis_ident(device_t dev)
4505 {
4506 struct ata_pci_controller *ctlr = device_get_softc(dev);
4507 struct ata_chip_id *idx;
4508 static struct ata_chip_id ids[] =
4509 {{ ATA_SIS182, 0x00, SISSATA, 0, ATA_SA150, "182" }, /* south */
4510 { ATA_SIS181, 0x00, SISSATA, 0, ATA_SA150, "181" }, /* south */
4511 { ATA_SIS180, 0x00, SISSATA, 0, ATA_SA150, "180" }, /* south */
4512 { ATA_SIS965, 0x00, SIS133NEW, 0, ATA_UDMA6, "965" }, /* south */
4513 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "964" }, /* south */
4514 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "963" }, /* south */
4515 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "962" }, /* south */
4516
4517 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */
4518 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */
4519 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */
4520 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */
4521
4522 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */
4523 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "633" }, /* unknown */
4524 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */
4525 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "630" }, /* 1chip */
4526 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "620" }, /* 1chip */
4527
4528 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "550" },
4529 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "540" },
4530 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "530" },
4531
4532 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "5513" },
4533 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "5513" },
4534 { 0, 0, 0, 0, 0, 0 }};
4535 char buffer[64];
4536 int found = 0;
4537
4538 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev))))
4539 return ENXIO;
4540
4541 if (idx->cfg2 && !found) {
4542 u_int8_t reg57 = pci_read_config(dev, 0x57, 1);
4543
4544 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1);
4545 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) {
4546 found = 1;
4547 idx->cfg1 = SIS133NEW;
4548 idx->max_dma = ATA_UDMA6;
4549 sprintf(buffer, "SiS 962/963 %s controller",
4550 ata_mode2str(idx->max_dma));
4551 }
4552 pci_write_config(dev, 0x57, reg57, 1);
4553 }
4554 if (idx->cfg2 && !found) {
4555 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1);
4556
4557 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1);
4558 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) {
4559 struct ata_chip_id id[] =
4560 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }};
4561
4562 found = 1;
4563 if (ata_find_chip(dev, id, pci_get_slot(dev))) {
4564 idx->cfg1 = SIS133OLD;
4565 idx->max_dma = ATA_UDMA6;
4566 }
4567 else {
4568 idx->cfg1 = SIS100NEW;
4569 idx->max_dma = ATA_UDMA5;
4570 }
4571 sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
4572 }
4573 pci_write_config(dev, 0x4a, reg4a, 1);
4574 }
4575 if (!found)
4576 sprintf(buffer,"SiS %s %s controller",
4577 idx->text, ata_mode2str(idx->max_dma));
4578
4579 device_set_desc_copy(dev, buffer);
4580 ctlr->chip = idx;
4581 ctlr->chipinit = ata_sis_chipinit;
4582 return 0;
4583 }
4584
4585 static int
4586 ata_sis_chipinit(device_t dev)
4587 {
4588 struct ata_pci_controller *ctlr = device_get_softc(dev);
4589
4590 if (ata_setup_interrupt(dev))
4591 return ENXIO;
4592
4593 switch (ctlr->chip->cfg1) {
4594 case SIS33:
4595 break;
4596 case SIS66:
4597 case SIS100OLD:
4598 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1);
4599 break;
4600 case SIS100NEW:
4601 case SIS133OLD:
4602 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1);
4603 break;
4604 case SIS133NEW:
4605 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2);
4606 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2);
4607 break;
4608 case SISSATA:
4609 ctlr->r_type2 = SYS_RES_IOPORT;
4610 ctlr->r_rid2 = PCIR_BAR(5);
4611 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4612 &ctlr->r_rid2, RF_ACTIVE))) {
4613 ctlr->allocate = ata_sis_allocate;
4614 ctlr->reset = ata_sis_reset;
4615
4616 /* enable PCI interrupt */
4617 pci_write_config(dev, PCIR_COMMAND,
4618 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
4619 }
4620 ctlr->setmode = ata_sata_setmode;
4621 return 0;
4622 default:
4623 return ENXIO;
4624 }
4625 ctlr->setmode = ata_sis_setmode;
4626 return 0;
4627 }
4628
4629 static int
4630 ata_sis_allocate(device_t dev)
4631 {
4632 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4633 struct ata_channel *ch = device_get_softc(dev);
4634 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6);
4635
4636 /* setup the usual register normal pci style */
4637 if (ata_pci_allocate(dev))
4638 return ENXIO;
4639
4640 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4641 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset;
4642 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4643 ch->r_io[ATA_SERROR].offset = 0x04 + offset;
4644 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4645 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset;
4646 ch->flags |= ATA_NO_SLAVE;
4647
4648 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */
4649 /* XXX SOS unknown how to enable PHY state change interrupt */
4650 return 0;
4651 }
4652
4653 static void
4654 ata_sis_reset(device_t dev)
4655 {
4656 struct ata_channel *ch = device_get_softc(dev);
4657
4658 ata_sata_phy_enable(ch);
4659 }
4660
4661
4662 static void
4663 ata_sis_setmode(device_t dev, int mode)
4664 {
4665 device_t gparent = GRANDPARENT(dev);
4666 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4667 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4668 struct ata_device *atadev = device_get_softc(dev);
4669 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4670 int error;
4671
4672 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4673
4674 if (ctlr->chip->cfg1 == SIS133NEW) {
4675 if (mode > ATA_UDMA2 &&
4676 pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) {
4677 ata_print_cable(dev, "controller");
4678 mode = ATA_UDMA2;
4679 }
4680 }
4681 else {
4682 if (mode > ATA_UDMA2 &&
4683 pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) {
4684 ata_print_cable(dev, "controller");
4685 mode = ATA_UDMA2;
4686 }
4687 }
4688
4689 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4690
4691 if (bootverbose)
4692 device_printf(dev, "%ssetting %s on %s chip\n",
4693 (error) ? "FAILURE " : "",
4694 ata_mode2str(mode), ctlr->chip->text);
4695 if (!error) {
4696 switch (ctlr->chip->cfg1) {
4697 case SIS133NEW: {
4698 u_int32_t timings[] =
4699 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
4700 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
4701 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
4702 u_int32_t reg;
4703
4704 reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
4705 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4);
4706 break;
4707 }
4708 case SIS133OLD: {
4709 u_int16_t timings[] =
4710 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
4711 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
4712
4713 u_int16_t reg = 0x40 + (devno << 1);
4714
4715 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
4716 break;
4717 }
4718 case SIS100NEW: {
4719 u_int16_t timings[] =
4720 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
4721 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
4722 u_int16_t reg = 0x40 + (devno << 1);
4723
4724 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
4725 break;
4726 }
4727 case SIS100OLD:
4728 case SIS66:
4729 case SIS33: {
4730 u_int16_t timings[] =
4731 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
4732 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
4733 u_int16_t reg = 0x40 + (devno << 1);
4734
4735 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
4736 break;
4737 }
4738 }
4739 atadev->mode = mode;
4740 }
4741 }
4742
4743
4744 /* VIA Technologies Inc. chipset support functions */
4745 int
4746 ata_via_ident(device_t dev)
4747 {
4748 struct ata_pci_controller *ctlr = device_get_softc(dev);
4749 struct ata_chip_id *idx;
4750 static struct ata_chip_id ids[] =
4751 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" },
4752 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" },
4753 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" },
4754 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" },
4755 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"},
4756 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" },
4757 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" },
4758 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" },
4759 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" },
4760 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" },
4761 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" },
4762 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" },
4763 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
4764 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" },
4765 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" },
4766 { 0, 0, 0, 0, 0, 0 }};
4767 static struct ata_chip_id new_ids[] =
4768 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" },
4769 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" },
4770 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" },
4771 { ATA_VIA8237A, 0x00, 0, 0x00, ATA_SA150, "8237A" },
4772 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" },
4773 { 0, 0, 0, 0, 0, 0 }};
4774 char buffer[64];
4775
4776 if (pci_get_devid(dev) == ATA_VIA82C571) {
4777 if (!(idx = ata_find_chip(dev, ids, -99)))
4778 return ENXIO;
4779 }
4780 else {
4781 if (!(idx = ata_match_chip(dev, new_ids)))
4782 return ENXIO;
4783 }
4784
4785 sprintf(buffer, "VIA %s %s controller",
4786 idx->text, ata_mode2str(idx->max_dma));
4787 device_set_desc_copy(dev, buffer);
4788 ctlr->chip = idx;
4789 ctlr->chipinit = ata_via_chipinit;
4790 return 0;
4791 }
4792
4793 static int
4794 ata_via_chipinit(device_t dev)
4795 {
4796 struct ata_pci_controller *ctlr = device_get_softc(dev);
4797
4798 if (ata_setup_interrupt(dev))
4799 return ENXIO;
4800
4801 if (ctlr->chip->max_dma >= ATA_SA150) {
4802 if (ctlr->chip->cfg2 == VIAAHCI) {
4803 ctlr->r_type2 = SYS_RES_MEMORY;
4804 ctlr->r_rid2 = PCIR_BAR(5);
4805 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4806 &ctlr->r_rid2,
4807 RF_ACTIVE))) {
4808 return ata_ahci_chipinit(dev);
4809 }
4810 }
4811 ctlr->r_type2 = SYS_RES_IOPORT;
4812 ctlr->r_rid2 = PCIR_BAR(5);
4813 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4814 &ctlr->r_rid2, RF_ACTIVE))) {
4815 ctlr->allocate = ata_via_allocate;
4816 ctlr->reset = ata_via_reset;
4817
4818 /* enable PCI interrupt */
4819 pci_write_config(dev, PCIR_COMMAND,
4820 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
4821 }
4822 ctlr->setmode = ata_sata_setmode;
4823 return 0;
4824 }
4825
4826 /* prepare for ATA-66 on the 82C686a and 82C596b */
4827 if (ctlr->chip->cfg2 & VIACLK)
4828 pci_write_config(dev, 0x50, 0x030b030b, 4);
4829
4830 /* the southbridge might need the data corruption fix */
4831 if (ctlr->chip->cfg2 & VIABUG)
4832 ata_via_southbridge_fixup(dev);
4833
4834 /* set fifo configuration half'n'half */
4835 pci_write_config(dev, 0x43,
4836 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
4837
4838 /* set status register read retry */
4839 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
4840
4841 /* set DMA read & end-of-sector fifo flush */
4842 pci_write_config(dev, 0x46,
4843 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
4844
4845 /* set sector size */
4846 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
4847 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
4848
4849 ctlr->setmode = ata_via_family_setmode;
4850 return 0;
4851 }
4852
4853 static int
4854 ata_via_allocate(device_t dev)
4855 {
4856 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4857 struct ata_channel *ch = device_get_softc(dev);
4858
4859 /* newer SATA chips has resources in one BAR for each channel */
4860 if (ctlr->chip->cfg2 & VIABAR) {
4861 struct resource *r_io;
4862 int i, rid;
4863
4864 rid = PCIR_BAR(ch->unit);
4865 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev),
4866 SYS_RES_IOPORT,
4867 &rid, RF_ACTIVE)))
4868 return ENXIO;
4869
4870 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
4871 ch->r_io[i].res = r_io;
4872 ch->r_io[i].offset = i;
4873 }
4874 ch->r_io[ATA_CONTROL].res = r_io;
4875 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE;
4876 ch->r_io[ATA_IDX_ADDR].res = r_io;
4877 ata_default_registers(dev);
4878 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
4879 ch->r_io[i].res = ctlr->r_res1;
4880 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
4881 }
4882 ata_pci_hw(dev);
4883 }
4884 else {
4885 /* setup the usual register normal pci style */
4886 if (ata_pci_allocate(dev))
4887 return ENXIO;
4888 }
4889
4890 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4891 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1);
4892 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4893 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1);
4894 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4895 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1);
4896 ch->flags |= ATA_NO_SLAVE;
4897
4898 /* XXX SOS PHY hotplug handling missing in VIA chip ?? */
4899 /* XXX SOS unknown how to enable PHY state change interrupt */
4900 return 0;
4901 }
4902
4903 static void
4904 ata_via_reset(device_t dev)
4905 {
4906 struct ata_channel *ch = device_get_softc(dev);
4907
4908 ata_sata_phy_enable(ch);
4909 }
4910
4911 static void
4912 ata_via_southbridge_fixup(device_t dev)
4913 {
4914 device_t *children;
4915 int nchildren, i;
4916
4917 if (device_get_children(device_get_parent(dev), &children, &nchildren))
4918 return;
4919
4920 for (i = 0; i < nchildren; i++) {
4921 if (pci_get_devid(children[i]) == ATA_VIA8363 ||
4922 pci_get_devid(children[i]) == ATA_VIA8371 ||
4923 pci_get_devid(children[i]) == ATA_VIA8662 ||
4924 pci_get_devid(children[i]) == ATA_VIA8361) {
4925 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
4926
4927 if ((reg76 & 0xf0) != 0xd0) {
4928 device_printf(dev,
4929 "Correcting VIA config for southbridge data corruption bug\n");
4930 pci_write_config(children[i], 0x75, 0x80, 1);
4931 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
4932 }
4933 break;
4934 }
4935 }
4936 free(children, M_TEMP);
4937 }
4938
4939
4940 /* common code for VIA, AMD & nVidia */
4941 static void
4942 ata_via_family_setmode(device_t dev, int mode)
4943 {
4944 device_t gparent = GRANDPARENT(dev);
4945 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4946 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4947 struct ata_device *atadev = device_get_softc(dev);
4948 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
4949 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
4950 int modes[][7] = {
4951 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
4952 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
4953 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
4954 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
4955 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */
4956 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4957 int reg = 0x53 - devno;
4958 int error;
4959
4960 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4961
4962 if (ctlr->chip->cfg2 & AMDCABLE) {
4963 if (mode > ATA_UDMA2 &&
4964 !(pci_read_config(gparent, 0x42, 1) & (1 << devno))) {
4965 ata_print_cable(dev, "controller");
4966 mode = ATA_UDMA2;
4967 }
4968 }
4969 else
4970 mode = ata_check_80pin(dev, mode);
4971
4972 if (ctlr->chip->cfg2 & NVIDIA)
4973 reg += 0x10;
4974
4975 if (ctlr->chip->cfg1 != VIA133)
4976 pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
4977
4978 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4979
4980 if (bootverbose)
4981 device_printf(dev, "%ssetting %s on %s chip\n",
4982 (error) ? "FAILURE " : "", ata_mode2str(mode),
4983 ctlr->chip->text);
4984 if (!error) {
4985 if (mode >= ATA_UDMA0)
4986 pci_write_config(gparent, reg,
4987 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
4988 else
4989 pci_write_config(gparent, reg, 0x8b, 1);
4990 atadev->mode = mode;
4991 }
4992 }
4993
4994
4995 /* misc functions */
4996 static struct ata_chip_id *
4997 ata_match_chip(device_t dev, struct ata_chip_id *index)
4998 {
4999 while (index->chipid != 0) {
5000 if (pci_get_devid(dev) == index->chipid &&
5001 pci_get_revid(dev) >= index->chiprev)
5002 return index;
5003 index++;
5004 }
5005 return NULL;
5006 }
5007
5008 static struct ata_chip_id *
5009 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot)
5010 {
5011 device_t *children;
5012 int nchildren, i;
5013
5014 if (device_get_children(device_get_parent(dev), &children, &nchildren))
5015 return 0;
5016
5017 while (index->chipid != 0) {
5018 for (i = 0; i < nchildren; i++) {
5019 if (((slot >= 0 && pci_get_slot(children[i]) == slot) ||
5020 (slot < 0 && pci_get_slot(children[i]) <= -slot)) &&
5021 pci_get_devid(children[i]) == index->chipid &&
5022 pci_get_revid(children[i]) >= index->chiprev) {
5023 free(children, M_TEMP);
5024 return index;
5025 }
5026 }
5027 index++;
5028 }
5029 free(children, M_TEMP);
5030 return NULL;
5031 }
5032
5033 static int
5034 ata_setup_interrupt(device_t dev)
5035 {
5036 struct ata_pci_controller *ctlr = device_get_softc(dev);
5037 int rid = ATA_IRQ_RID;
5038
5039 if (!ata_legacy(dev)) {
5040 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
5041 RF_SHAREABLE | RF_ACTIVE))) {
5042 device_printf(dev, "unable to map interrupt\n");
5043 return ENXIO;
5044 }
5045 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
5046 ata_generic_intr, ctlr, &ctlr->handle))) {
5047 device_printf(dev, "unable to setup interrupt\n");
5048 return ENXIO;
5049 }
5050 }
5051 return 0;
5052 }
5053
5054 struct ata_serialize {
5055 struct mtx locked_mtx;
5056 int locked_ch;
5057 int restart_ch;
5058 };
5059
5060 static int
5061 ata_serialize(device_t dev, int flags)
5062 {
5063 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5064 struct ata_channel *ch = device_get_softc(dev);
5065 struct ata_serialize *serial;
5066 static int inited = 0;
5067 int res;
5068
5069 if (!inited) {
5070 serial = malloc(sizeof(struct ata_serialize),
5071 M_TEMP, M_NOWAIT | M_ZERO);
5072 mtx_init(&serial->locked_mtx, "ATA serialize lock", NULL, MTX_DEF);
5073 serial->locked_ch = -1;
5074 serial->restart_ch = -1;
5075 device_set_ivars(ctlr->dev, serial);
5076 inited = 1;
5077 }
5078 else
5079 serial = device_get_ivars(ctlr->dev);
5080
5081 mtx_lock(&serial->locked_mtx);
5082 switch (flags) {
5083 case ATA_LF_LOCK:
5084 if (serial->locked_ch == -1)
5085 serial->locked_ch = ch->unit;
5086 if (serial->locked_ch != ch->unit)
5087 serial->restart_ch = ch->unit;
5088 break;
5089
5090 case ATA_LF_UNLOCK:
5091 if (serial->locked_ch == ch->unit) {
5092 serial->locked_ch = -1;
5093 if (serial->restart_ch != -1) {
5094 if ((ch = ctlr->interrupt[serial->restart_ch].argument)) {
5095 serial->restart_ch = -1;
5096 mtx_unlock(&serial->locked_mtx);
5097 ata_start(ch->dev);
5098 return -1;
5099 }
5100 }
5101 }
5102 break;
5103
5104 case ATA_LF_WHICH:
5105 break;
5106 }
5107 res = serial->locked_ch;
5108 mtx_unlock(&serial->locked_mtx);
5109 return res;
5110 }
5111
5112 static void
5113 ata_print_cable(device_t dev, u_int8_t *who)
5114 {
5115 device_printf(dev,
5116 "DMA limited to UDMA33, %s found non-ATA66 cable\n", who);
5117 }
5118
5119 static int
5120 ata_atapi(device_t dev)
5121 {
5122 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5123 struct ata_device *atadev = device_get_softc(dev);
5124
5125 return ((atadev->unit == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) ||
5126 (atadev->unit == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE));
5127 }
5128
5129 static int
5130 ata_check_80pin(device_t dev, int mode)
5131 {
5132 struct ata_device *atadev = device_get_softc(dev);
5133
5134 if (mode > ATA_UDMA2 && !(atadev->param.hwres & ATA_CABLE_ID)) {
5135 ata_print_cable(dev, "device");
5136 mode = ATA_UDMA2;
5137 }
5138 return mode;
5139 }
5140
5141 static int
5142 ata_mode2idx(int mode)
5143 {
5144 if ((mode & ATA_DMA_MASK) == ATA_UDMA0)
5145 return (mode & ATA_MODE_MASK) + 8;
5146 if ((mode & ATA_DMA_MASK) == ATA_WDMA0)
5147 return (mode & ATA_MODE_MASK) + 5;
5148 return (mode & ATA_MODE_MASK) - ATA_PIO0;
5149 }
Cache object: da531a10a8975fddb6bbd1a42a5fd8b5
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