1 /*-
2 * Copyright (c) 1998 - 2007 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: src/sys/dev/ata/ata-chipset.c,v 1.126.2.23.2.2 2007/12/09 19:27:19 delphij Exp $");
29
30 #include "opt_ata.h"
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/ata.h>
35 #include <sys/bus.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <sys/sema.h>
41 #include <sys/taskqueue.h>
42 #include <vm/uma.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
46 #include <sys/rman.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49 #include <dev/ata/ata-all.h>
50 #include <dev/ata/ata-pci.h>
51 #include <ata_if.h>
52
53 /* local prototypes */
54 /* ata-chipset.c */
55 static int ata_generic_chipinit(device_t dev);
56 static void ata_generic_intr(void *data);
57 static void ata_generic_setmode(device_t dev, int mode);
58 static void ata_sata_phy_check_events(device_t dev);
59 static void ata_sata_phy_event(void *context, int dummy);
60 static int ata_sata_phy_reset(device_t dev);
61 static int ata_sata_connect(struct ata_channel *ch);
62 static void ata_sata_setmode(device_t dev, int mode);
63 static int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis);
64 static int ata_ahci_chipinit(device_t dev);
65 static int ata_ahci_allocate(device_t dev);
66 static int ata_ahci_status(device_t dev);
67 static int ata_ahci_begin_transaction(struct ata_request *request);
68 static int ata_ahci_end_transaction(struct ata_request *request);
69 static void ata_ahci_reset(device_t dev);
70 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
71 static void ata_ahci_dmainit(device_t dev);
72 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request);
73 static int ata_acard_chipinit(device_t dev);
74 static int ata_acard_allocate(device_t dev);
75 static int ata_acard_status(device_t dev);
76 static void ata_acard_850_setmode(device_t dev, int mode);
77 static void ata_acard_86X_setmode(device_t dev, int mode);
78 static int ata_ali_chipinit(device_t dev);
79 static int ata_ali_allocate(device_t dev);
80 static int ata_ali_sata_allocate(device_t dev);
81 static void ata_ali_reset(device_t dev);
82 static void ata_ali_setmode(device_t dev, int mode);
83 static int ata_amd_chipinit(device_t dev);
84 static int ata_ati_chipinit(device_t dev);
85 static void ata_ati_setmode(device_t dev, int mode);
86 static int ata_cyrix_chipinit(device_t dev);
87 static void ata_cyrix_setmode(device_t dev, int mode);
88 static int ata_cypress_chipinit(device_t dev);
89 static void ata_cypress_setmode(device_t dev, int mode);
90 static int ata_highpoint_chipinit(device_t dev);
91 static int ata_highpoint_allocate(device_t dev);
92 static void ata_highpoint_setmode(device_t dev, int mode);
93 static int ata_highpoint_check_80pin(device_t dev, int mode);
94 static int ata_intel_chipinit(device_t dev);
95 static int ata_intel_allocate(device_t dev);
96 static void ata_intel_reset(device_t dev);
97 static void ata_intel_old_setmode(device_t dev, int mode);
98 static void ata_intel_new_setmode(device_t dev, int mode);
99 static void ata_intel_sata_setmode(device_t dev, int mode);
100 static int ata_intel_31244_allocate(device_t dev);
101 static int ata_intel_31244_status(device_t dev);
102 static int ata_intel_31244_command(struct ata_request *request);
103 static void ata_intel_31244_reset(device_t dev);
104 static int ata_ite_chipinit(device_t dev);
105 static void ata_ite_setmode(device_t dev, int mode);
106 static int ata_jmicron_chipinit(device_t dev);
107 static int ata_jmicron_allocate(device_t dev);
108 static void ata_jmicron_reset(device_t dev);
109 static void ata_jmicron_dmainit(device_t dev);
110 static void ata_jmicron_setmode(device_t dev, int mode);
111 static int ata_marvell_pata_chipinit(device_t dev);
112 static int ata_marvell_pata_allocate(device_t dev);
113 static void ata_marvell_pata_setmode(device_t dev, int mode);
114 static int ata_marvell_edma_chipinit(device_t dev);
115 static int ata_marvell_edma_allocate(device_t dev);
116 static int ata_marvell_edma_status(device_t dev);
117 static int ata_marvell_edma_begin_transaction(struct ata_request *request);
118 static int ata_marvell_edma_end_transaction(struct ata_request *request);
119 static void ata_marvell_edma_reset(device_t dev);
120 static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
121 static void ata_marvell_edma_dmainit(device_t dev);
122 static int ata_national_chipinit(device_t dev);
123 static void ata_national_setmode(device_t dev, int mode);
124 static int ata_netcell_chipinit(device_t dev);
125 static int ata_netcell_allocate(device_t dev);
126 static int ata_nvidia_chipinit(device_t dev);
127 static int ata_nvidia_allocate(device_t dev);
128 static int ata_nvidia_status(device_t dev);
129 static void ata_nvidia_reset(device_t dev);
130 static int ata_promise_chipinit(device_t dev);
131 static int ata_promise_allocate(device_t dev);
132 static int ata_promise_status(device_t dev);
133 static int ata_promise_dmastart(device_t dev);
134 static int ata_promise_dmastop(device_t dev);
135 static void ata_promise_dmareset(device_t dev);
136 static void ata_promise_dmainit(device_t dev);
137 static void ata_promise_setmode(device_t dev, int mode);
138 static int ata_promise_tx2_allocate(device_t dev);
139 static int ata_promise_tx2_status(device_t dev);
140 static int ata_promise_mio_allocate(device_t dev);
141 static void ata_promise_mio_intr(void *data);
142 static int ata_promise_mio_status(device_t dev);
143 static int ata_promise_mio_command(struct ata_request *request);
144 static void ata_promise_mio_reset(device_t dev);
145 static void ata_promise_mio_dmainit(device_t dev);
146 static void ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
147 static void ata_promise_mio_setmode(device_t dev, int mode);
148 static void ata_promise_sx4_intr(void *data);
149 static int ata_promise_sx4_command(struct ata_request *request);
150 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request);
151 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt);
152 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr);
153 static int ata_serverworks_chipinit(device_t dev);
154 static int ata_serverworks_allocate(device_t dev);
155 static void ata_serverworks_setmode(device_t dev, int mode);
156 static int ata_sii_chipinit(device_t dev);
157 static int ata_cmd_allocate(device_t dev);
158 static int ata_cmd_status(device_t dev);
159 static void ata_cmd_setmode(device_t dev, int mode);
160 static int ata_sii_allocate(device_t dev);
161 static int ata_sii_status(device_t dev);
162 static void ata_sii_reset(device_t dev);
163 static void ata_sii_setmode(device_t dev, int mode);
164 static int ata_siiprb_allocate(device_t dev);
165 static int ata_siiprb_status(device_t dev);
166 static int ata_siiprb_begin_transaction(struct ata_request *request);
167 static int ata_siiprb_end_transaction(struct ata_request *request);
168 static void ata_siiprb_reset(device_t dev);
169 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
170 static void ata_siiprb_dmainit(device_t dev);
171 static int ata_sis_chipinit(device_t dev);
172 static int ata_sis_allocate(device_t dev);
173 static void ata_sis_reset(device_t dev);
174 static void ata_sis_setmode(device_t dev, int mode);
175 static int ata_via_chipinit(device_t dev);
176 static int ata_via_allocate(device_t dev);
177 static void ata_via_reset(device_t dev);
178 static void ata_via_setmode(device_t dev, int mode);
179 static void ata_via_southbridge_fixup(device_t dev);
180 static void ata_via_family_setmode(device_t dev, int mode);
181 static void ata_set_desc(device_t dev);
182 static struct ata_chip_id *ata_match_chip(device_t dev, struct ata_chip_id *index);
183 static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot);
184 static int ata_setup_interrupt(device_t dev);
185 static int ata_serialize(device_t dev, int flags);
186 static void ata_print_cable(device_t dev, u_int8_t *who);
187 static int ata_atapi(device_t dev);
188 static int ata_check_80pin(device_t dev, int mode);
189 static int ata_mode2idx(int mode);
190
191
192 /*
193 * generic ATA support functions
194 */
195 int
196 ata_generic_ident(device_t dev)
197 {
198 struct ata_pci_controller *ctlr = device_get_softc(dev);
199 char buffer[64];
200
201 sprintf(buffer, "%s ATA controller", ata_pcivendor2str(dev));
202 device_set_desc_copy(dev, buffer);
203 ctlr->chipinit = ata_generic_chipinit;
204 return 0;
205 }
206
207 static int
208 ata_generic_chipinit(device_t dev)
209 {
210 struct ata_pci_controller *ctlr = device_get_softc(dev);
211
212 if (ata_setup_interrupt(dev))
213 return ENXIO;
214 ctlr->setmode = ata_generic_setmode;
215 return 0;
216 }
217
218 static void
219 ata_generic_intr(void *data)
220 {
221 struct ata_pci_controller *ctlr = data;
222 struct ata_channel *ch;
223 int unit;
224
225 for (unit = 0; unit < ctlr->channels; unit++) {
226 if ((ch = ctlr->interrupt[unit].argument))
227 ctlr->interrupt[unit].function(ch);
228 }
229 }
230
231 static void
232 ata_generic_setmode(device_t dev, int mode)
233 {
234 struct ata_device *atadev = device_get_softc(dev);
235
236 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
237 mode = ata_check_80pin(dev, mode);
238 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
239 atadev->mode = mode;
240 }
241
242
243 /*
244 * SATA support functions
245 */
246 static void
247 ata_sata_phy_check_events(device_t dev)
248 {
249 struct ata_channel *ch = device_get_softc(dev);
250 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR);
251
252 /* clear error bits/interrupt */
253 ATA_IDX_OUTL(ch, ATA_SERROR, error);
254
255 /* do we have any events flagged ? */
256 if (error) {
257 struct ata_connect_task *tp;
258 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS);
259
260 /* if we have a connection event deal with it */
261 if ((error & ATA_SE_PHY_CHANGED) &&
262 (tp = (struct ata_connect_task *)
263 malloc(sizeof(struct ata_connect_task),
264 M_ATA, M_NOWAIT | M_ZERO))) {
265
266 if (((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) ||
267 ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)) {
268 if (bootverbose)
269 device_printf(ch->dev, "CONNECT requested\n");
270 tp->action = ATA_C_ATTACH;
271 }
272 else {
273 if (bootverbose)
274 device_printf(ch->dev, "DISCONNECT requested\n");
275 tp->action = ATA_C_DETACH;
276 }
277 tp->dev = ch->dev;
278 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
279 taskqueue_enqueue(taskqueue_thread, &tp->task);
280 }
281 }
282 }
283
284 static void
285 ata_sata_phy_event(void *context, int dummy)
286 {
287 struct ata_connect_task *tp = (struct ata_connect_task *)context;
288 struct ata_channel *ch = device_get_softc(tp->dev);
289 device_t *children;
290 int nchildren, i;
291
292 mtx_lock(&Giant); /* newbus suckage it needs Giant */
293 if (tp->action == ATA_C_ATTACH) {
294 if (bootverbose)
295 device_printf(tp->dev, "CONNECTED\n");
296 ATA_RESET(tp->dev);
297 ata_identify(tp->dev);
298 }
299 if (tp->action == ATA_C_DETACH) {
300 if (!device_get_children(tp->dev, &children, &nchildren)) {
301 for (i = 0; i < nchildren; i++)
302 if (children[i])
303 device_delete_child(tp->dev, children[i]);
304 free(children, M_TEMP);
305 }
306 mtx_lock(&ch->state_mtx);
307 ch->state = ATA_IDLE;
308 mtx_unlock(&ch->state_mtx);
309 if (bootverbose)
310 device_printf(tp->dev, "DISCONNECTED\n");
311 }
312 mtx_unlock(&Giant); /* suckage code dealt with, release Giant */
313 free(tp, M_ATA);
314 }
315
316 static int
317 ata_sata_phy_reset(device_t dev)
318 {
319 struct ata_channel *ch = device_get_softc(dev);
320 int loop, retry;
321
322 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE)
323 return ata_sata_connect(ch);
324
325 for (retry = 0; retry < 10; retry++) {
326 for (loop = 0; loop < 10; loop++) {
327 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET);
328 ata_udelay(100);
329 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) ==
330 ATA_SC_DET_RESET)
331 break;
332 }
333 ata_udelay(5000);
334 for (loop = 0; loop < 10; loop++) {
335 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_IDLE |
336 ATA_SC_IPM_DIS_PARTIAL |
337 ATA_SC_IPM_DIS_SLUMBER);
338 ata_udelay(100);
339 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 0)
340 return ata_sata_connect(ch);
341 }
342 }
343 return 0;
344 }
345
346 static int
347 ata_sata_connect(struct ata_channel *ch)
348 {
349 u_int32_t status;
350 int timeout;
351
352 /* wait up to 1 second for "connect well" */
353 for (timeout = 0; timeout < 100 ; timeout++) {
354 status = ATA_IDX_INL(ch, ATA_SSTATUS);
355 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 ||
356 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)
357 break;
358 ata_udelay(10000);
359 }
360 if (timeout >= 100) {
361 if (bootverbose)
362 device_printf(ch->dev, "SATA connect status=%08x\n", status);
363 return 0;
364 }
365 if (bootverbose)
366 device_printf(ch->dev, "SATA connect time=%dms\n", timeout * 10);
367
368 /* clear SATA error register */
369 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
370
371 return 1;
372 }
373
374 static void
375 ata_sata_setmode(device_t dev, int mode)
376 {
377 struct ata_device *atadev = device_get_softc(dev);
378
379 /*
380 * if we detect that the device isn't a real SATA device we limit
381 * the transfer mode to UDMA5/ATA100.
382 * this works around the problems some devices has with the
383 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133.
384 */
385 if (atadev->param.satacapabilities != 0x0000 &&
386 atadev->param.satacapabilities != 0xffff) {
387 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
388
389 /* on some drives we need to set the transfer mode */
390 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
391 ata_limit_mode(dev, mode, ATA_UDMA6));
392
393 /* query SATA STATUS for the speed */
394 if (ch->r_io[ATA_SSTATUS].res &&
395 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) ==
396 ATA_SS_CONWELL_GEN2))
397 atadev->mode = ATA_SA300;
398 else
399 atadev->mode = ATA_SA150;
400 }
401 else {
402 mode = ata_limit_mode(dev, mode, ATA_UDMA5);
403 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
404 atadev->mode = mode;
405 }
406 }
407
408 static int
409 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis)
410 {
411 struct ata_device *atadev = device_get_softc(request->dev);
412
413 if (request->flags & ATA_R_ATAPI) {
414 fis[0] = 0x27; /* host to device */
415 fis[1] = 0x80; /* command FIS (note PM goes here) */
416 fis[2] = ATA_PACKET_CMD;
417 if (request->flags & (ATA_R_READ | ATA_R_WRITE))
418 fis[3] = ATA_F_DMA;
419 else {
420 fis[5] = request->transfersize;
421 fis[6] = request->transfersize >> 8;
422 }
423 fis[7] = ATA_D_LBA | atadev->unit;
424 fis[15] = ATA_A_4BIT;
425 return 20;
426 }
427 else {
428 ata_modify_if_48bit(request);
429 fis[0] = 0x27; /* host to device */
430 fis[1] = 0x80; /* command FIS (note PM goes here) */
431 fis[2] = request->u.ata.command;
432 fis[3] = request->u.ata.feature;
433 fis[4] = request->u.ata.lba;
434 fis[5] = request->u.ata.lba >> 8;
435 fis[6] = request->u.ata.lba >> 16;
436 fis[7] = ATA_D_LBA | atadev->unit;
437 if (!(atadev->flags & ATA_D_48BIT_ACTIVE))
438 fis[7] |= (request->u.ata.lba >> 24 & 0x0f);
439 fis[8] = request->u.ata.lba >> 24;
440 fis[9] = request->u.ata.lba >> 32;
441 fis[10] = request->u.ata.lba >> 40;
442 fis[11] = request->u.ata.feature >> 8;
443 fis[12] = request->u.ata.count;
444 fis[13] = request->u.ata.count >> 8;
445 fis[15] = ATA_A_4BIT;
446 return 20;
447 }
448 return 0;
449 }
450
451
452 /*
453 * AHCI v1.x compliant SATA chipset support functions
454 */
455 int
456 ata_ahci_ident(device_t dev)
457 {
458 struct ata_pci_controller *ctlr = device_get_softc(dev);
459 char buffer[64];
460
461 /* is this PCI device flagged as an AHCI compliant chip ? */
462 if (pci_read_config(dev, PCIR_PROGIF, 1) != 0x01)
463 return ENXIO;
464
465 if (bootverbose)
466 sprintf(buffer, "%s (ID=%08x) AHCI controller",
467 ata_pcivendor2str(dev), pci_get_devid(dev));
468 else
469 sprintf(buffer, "%s AHCI controller", ata_pcivendor2str(dev));
470 device_set_desc_copy(dev, buffer);
471 ctlr->chipinit = ata_ahci_chipinit;
472 return 0;
473 }
474
475 static int
476 ata_ahci_chipinit(device_t dev)
477 {
478 struct ata_pci_controller *ctlr = device_get_softc(dev);
479 u_int32_t version;
480
481 /* if we have a memory BAR(5) we are likely on an AHCI part */
482 ctlr->r_type2 = SYS_RES_MEMORY;
483 ctlr->r_rid2 = PCIR_BAR(5);
484 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
485 &ctlr->r_rid2, RF_ACTIVE)))
486 return ENXIO;
487
488 /* setup interrupt delivery if not done allready by a vendor driver */
489 if (!ctlr->r_irq) {
490 if (ata_setup_interrupt(dev))
491 return ENXIO;
492 }
493 else
494 device_printf(dev, "AHCI called from vendor specific driver\n");
495
496 /* enable AHCI mode */
497 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
498
499 /* reset AHCI controller */
500 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_HR);
501 DELAY(1000000);
502 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) {
503 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
504 device_printf(dev, "AHCI controller reset failure\n");
505 return ENXIO;
506 }
507
508 /* reenable AHCI mode */
509 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
510
511 /* get the number of HW channels */
512 ctlr->channels =
513 MAX(flsl(ATA_INL(ctlr->r_res2, ATA_AHCI_PI)),
514 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
515
516 /* clear interrupts */
517 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS));
518
519 /* enable AHCI interrupts */
520 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
521 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE);
522
523 ctlr->reset = ata_ahci_reset;
524 ctlr->dmainit = ata_ahci_dmainit;
525 ctlr->allocate = ata_ahci_allocate;
526 ctlr->setmode = ata_sata_setmode;
527
528 /* enable PCI interrupt */
529 pci_write_config(dev, PCIR_COMMAND,
530 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
531
532 /* announce we support the HW */
533 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS);
534 device_printf(dev,
535 "AHCI Version %x%x.%x%x controller with %d ports detected\n",
536 (version >> 24) & 0xff, (version >> 16) & 0xff,
537 (version >> 8) & 0xff, version & 0xff,
538 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
539 return 0;
540 }
541
542 static int
543 ata_ahci_allocate(device_t dev)
544 {
545 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
546 struct ata_channel *ch = device_get_softc(dev);
547 u_int64_t work;
548 int offset = ch->unit << 7;
549
550 /* set the SATA resources */
551 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
552 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset;
553 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
554 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset;
555 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
556 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset;
557 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
558 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset;
559
560 ch->hw.status = ata_ahci_status;
561 ch->hw.begin_transaction = ata_ahci_begin_transaction;
562 ch->hw.end_transaction = ata_ahci_end_transaction;
563 ch->hw.command = NULL; /* not used here */
564
565 /* setup work areas */
566 work = ch->dma->work_bus + ATA_AHCI_CL_OFFSET;
567 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff);
568 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32);
569
570 work = ch->dma->work_bus + ATA_AHCI_FB_OFFSET;
571 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff);
572 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32);
573
574 /* enable wanted port interrupts */
575 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
576 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
577 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
578 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP |
579 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS |
580 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR));
581
582 /* start operations on this channel */
583 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
584 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
585 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
586 return 0;
587 }
588
589 static int
590 ata_ahci_status(device_t dev)
591 {
592 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
593 struct ata_channel *ch = device_get_softc(dev);
594 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS);
595 int offset = ch->unit << 7;
596 int tag = 0;
597
598 if (action & (1 << ch->unit)) {
599 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset);
600 u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset);
601
602 /* clear interrupt(s) */
603 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action & (1 << ch->unit));
604 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus);
605
606 /* do we have any PHY events ? */
607 /* XXX SOS check istatus phy bits */
608 ata_sata_phy_check_events(dev);
609
610 /* do we have a potentially hanging engine to take care of? */
611 if ((istatus & 0x78400050) && (cstatus & (1 << tag))) {
612
613 u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
614 int timeout = 0;
615
616 /* kill off all activity on this channel */
617 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
618 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
619
620 /* XXX SOS this is not entirely wrong */
621 do {
622 DELAY(1000);
623 if (timeout++ > 500) {
624 device_printf(dev, "stopping AHCI engine failed\n");
625 break;
626 }
627 } while (ATA_INL(ctlr->r_res2,
628 ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
629
630 /* start operations on this channel */
631 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
632 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
633
634 return 1;
635 }
636 else
637 return (!(cstatus & (1 << tag)));
638 }
639 return 0;
640 }
641
642 /* must be called with ATA channel locked and state_mtx held */
643 static int
644 ata_ahci_begin_transaction(struct ata_request *request)
645 {
646 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
647 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
648 struct ata_ahci_cmd_tab *ctp;
649 struct ata_ahci_cmd_list *clp;
650 int offset = ch->unit << 7;
651 int tag = 0, entries = 0;
652 int fis_size;
653
654 /* get a piece of the workspace for this request */
655 ctp = (struct ata_ahci_cmd_tab *)
656 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag));
657
658 /* setup the FIS for this request */
659 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) {
660 device_printf(request->dev, "setting up SATA FIS failed\n");
661 request->result = EIO;
662 return ATA_OP_FINISHED;
663 }
664
665 /* if request moves data setup and load SG list */
666 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
667 if (ch->dma->load(ch->dev, request->data, request->bytecount,
668 request->flags & ATA_R_READ,
669 ctp->prd_tab, &entries)) {
670 device_printf(request->dev, "setting up DMA failed\n");
671 request->result = EIO;
672 return ATA_OP_FINISHED;
673 }
674 }
675
676 /* setup the command list entry */
677 clp = (struct ata_ahci_cmd_list *)
678 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
679
680 clp->prd_length = entries;
681 clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) |
682 (request->flags & ATA_R_ATAPI ? ((1<<5) | (1<<7)) : 0) |
683 (fis_size / sizeof(u_int32_t));
684 clp->bytecount = 0;
685 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET +
686 (ATA_AHCI_CT_SIZE * tag));
687
688 /* clear eventual ACTIVE bit */
689 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag));
690
691 /* set command type bit */
692 if (request->flags & ATA_R_ATAPI)
693 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
694 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) |
695 ATA_AHCI_P_CMD_ATAPI);
696 else
697 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
698 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) &
699 ~ATA_AHCI_P_CMD_ATAPI);
700
701 /* issue command to controller */
702 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << tag));
703
704 if (!(request->flags & ATA_R_ATAPI)) {
705 /* device reset doesn't interrupt */
706 if (request->u.ata.command == ATA_DEVICE_RESET) {
707 u_int32_t tf_data;
708 int timeout = 1000000;
709
710 do {
711 DELAY(10);
712 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7));
713 } while ((tf_data & ATA_S_BUSY) && timeout--);
714 if (bootverbose)
715 device_printf(ch->dev, "device_reset timeout=%dus\n",
716 (1000000-timeout)*10);
717 request->status = tf_data;
718 if (request->status & ATA_S_ERROR)
719 request->error = tf_data >> 8;
720 return ATA_OP_FINISHED;
721 }
722 }
723
724 /* start the timeout */
725 callout_reset(&request->callout, request->timeout * hz,
726 (timeout_t*)ata_timeout, request);
727 return ATA_OP_CONTINUES;
728 }
729
730 /* must be called with ATA channel locked and state_mtx held */
731 static int
732 ata_ahci_end_transaction(struct ata_request *request)
733 {
734 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
735 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
736 struct ata_ahci_cmd_list *clp;
737 u_int32_t tf_data;
738 int offset = ch->unit << 7;
739 int tag = 0;
740
741 /* kill the timeout */
742 callout_stop(&request->callout);
743
744 /* get status */
745 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset);
746 request->status = tf_data;
747
748 /* if error status get details */
749 if (request->status & ATA_S_ERROR)
750 request->error = tf_data >> 8;
751
752 /* record how much data we actually moved */
753 clp = (struct ata_ahci_cmd_list *)
754 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
755 request->donecount = clp->bytecount;
756
757 /* release SG list etc */
758 ch->dma->unload(ch->dev);
759
760 return ATA_OP_FINISHED;
761 }
762
763 static void
764 ata_ahci_reset(device_t dev)
765 {
766 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
767 struct ata_channel *ch = device_get_softc(dev);
768 u_int32_t cmd, signature;
769 int offset = ch->unit << 7;
770 int timeout;
771
772 if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) {
773 device_printf(dev, "port not implemented\n");
774 return;
775 }
776 ch->devices = 0;
777
778 /* kill off all activity on this channel */
779 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
780 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
781 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
782
783 /* XXX SOS this is not entirely wrong */
784 timeout = 0;
785 do {
786 DELAY(1000);
787 if (timeout++ > 500) {
788 device_printf(dev, "stopping AHCI engine failed\n");
789 break;
790 }
791 }
792 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
793
794 /* issue Command List Override if supported */
795 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) {
796 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
797 cmd |= ATA_AHCI_P_CMD_CLO;
798 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd);
799 timeout = 0;
800 do {
801 DELAY(1000);
802 if (timeout++ > 500) {
803 device_printf(dev, "executing CLO failed\n");
804 break;
805 }
806 }
807 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO);
808 }
809
810 /* reset PHY and decide what is present */
811 if (ata_sata_phy_reset(dev)) {
812
813 /* clear any interrupts pending on this channel */
814 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
815 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
816
817 /* clear SATA error register */
818 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
819
820 /* start operations on this channel */
821 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
822 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
823 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
824
825 signature = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset);
826 if (bootverbose)
827 device_printf(dev, "SIGNATURE: %08x\n", signature);
828 switch (signature) {
829 case 0x00000101:
830 ch->devices = ATA_ATA_MASTER;
831 break;
832 case 0x96690101:
833 ch->devices = ATA_PORTMULTIPLIER;
834 device_printf(ch->dev, "Portmultipliers not supported yet\n");
835 ch->devices = 0;
836 break;
837 case 0xeb140101:
838 ch->devices = ATA_ATAPI_MASTER;
839 break;
840 default: /* SOS XXX */
841 if (bootverbose)
842 device_printf(ch->dev, "No signature, asuming disk device\n");
843 ch->devices = ATA_ATA_MASTER;
844 }
845 }
846 if (bootverbose)
847 device_printf(dev, "ahci_reset devices=0x%b\n", ch->devices,
848 "\2\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
849 }
850
851 static void
852 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
853 {
854 struct ata_dmasetprd_args *args = xsc;
855 struct ata_ahci_dma_prd *prd = args->dmatab;
856 int i;
857
858 if (!(args->error = error)) {
859 for (i = 0; i < nsegs; i++) {
860 prd[i].dba = htole64(segs[i].ds_addr);
861 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK);
862 }
863 }
864 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
865 args->nsegs = nsegs;
866 }
867
868 static void
869 ata_ahci_dmainit(device_t dev)
870 {
871 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
872 struct ata_channel *ch = device_get_softc(dev);
873
874 ata_dmainit(dev);
875 if (ch->dma) {
876 /* note start and stop are not used here */
877 ch->dma->setprd = ata_ahci_dmasetprd;
878 ch->dma->max_iosize = 8192 * DEV_BSIZE;
879 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT)
880 ch->dma->max_address = BUS_SPACE_MAXADDR;
881 }
882 }
883
884 static int
885 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request)
886 {
887 bzero(ctp->cfis, 64);
888 if (request->flags & ATA_R_ATAPI) {
889 bzero(ctp->acmd, 32);
890 bcopy(request->u.atapi.ccb, ctp->acmd, 16);
891 }
892 return ata_request2fis_h2d(request, &ctp->cfis[0]);
893 }
894
895
896 /*
897 * Acard chipset support functions
898 */
899 int
900 ata_acard_ident(device_t dev)
901 {
902 struct ata_pci_controller *ctlr = device_get_softc(dev);
903 static struct ata_chip_id ids[] =
904 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "ATP850" },
905 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "ATP860A" },
906 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "ATP860R" },
907 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "ATP865A" },
908 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "ATP865R" },
909 { 0, 0, 0, 0, 0, 0}};
910
911 if (!(ctlr->chip = ata_match_chip(dev, ids)))
912 return ENXIO;
913
914 ata_set_desc(dev);
915 ctlr->chipinit = ata_acard_chipinit;
916 return 0;
917 }
918
919 static int
920 ata_acard_chipinit(device_t dev)
921 {
922 struct ata_pci_controller *ctlr = device_get_softc(dev);
923
924 if (ata_setup_interrupt(dev))
925 return ENXIO;
926
927 ctlr->allocate = ata_acard_allocate;
928 if (ctlr->chip->cfg1 == ATPOLD) {
929 ctlr->setmode = ata_acard_850_setmode;
930 ctlr->locking = ata_serialize;
931 }
932 else
933 ctlr->setmode = ata_acard_86X_setmode;
934 return 0;
935 }
936
937 static int
938 ata_acard_allocate(device_t dev)
939 {
940 struct ata_channel *ch = device_get_softc(dev);
941
942 /* setup the usual register normal pci style */
943 if (ata_pci_allocate(dev))
944 return ENXIO;
945
946 ch->hw.status = ata_acard_status;
947 return 0;
948 }
949
950 static int
951 ata_acard_status(device_t dev)
952 {
953 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
954 struct ata_channel *ch = device_get_softc(dev);
955
956 if (ctlr->chip->cfg1 == ATPOLD &&
957 ATA_LOCKING(ch->dev, ATA_LF_WHICH) != ch->unit)
958 return 0;
959 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
960 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
961
962 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
963 ATA_BMSTAT_INTERRUPT)
964 return 0;
965 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
966 DELAY(1);
967 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
968 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
969 DELAY(1);
970 }
971 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
972 DELAY(100);
973 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
974 return 0;
975 }
976 return 1;
977 }
978
979 static void
980 ata_acard_850_setmode(device_t dev, int mode)
981 {
982 device_t gparent = GRANDPARENT(dev);
983 struct ata_pci_controller *ctlr = device_get_softc(gparent);
984 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
985 struct ata_device *atadev = device_get_softc(dev);
986 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
987 int error;
988
989 mode = ata_limit_mode(dev, mode,
990 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
991
992 /* XXX SOS missing WDMA0+1 + PIO modes */
993 if (mode >= ATA_WDMA2) {
994 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
995 if (bootverbose)
996 device_printf(dev, "%ssetting %s on %s chip\n",
997 (error) ? "FAILURE " : "",
998 ata_mode2str(mode), ctlr->chip->text);
999 if (!error) {
1000 u_int8_t reg54 = pci_read_config(gparent, 0x54, 1);
1001
1002 reg54 &= ~(0x03 << (devno << 1));
1003 if (mode >= ATA_UDMA0)
1004 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1));
1005 pci_write_config(gparent, 0x54, reg54, 1);
1006 pci_write_config(gparent, 0x4a, 0xa6, 1);
1007 pci_write_config(gparent, 0x40 + (devno << 1), 0x0301, 2);
1008 atadev->mode = mode;
1009 return;
1010 }
1011 }
1012 /* we could set PIO mode timings, but we assume the BIOS did that */
1013 }
1014
1015 static void
1016 ata_acard_86X_setmode(device_t dev, int mode)
1017 {
1018 device_t gparent = GRANDPARENT(dev);
1019 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1020 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1021 struct ata_device *atadev = device_get_softc(dev);
1022 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1023 int error;
1024
1025
1026 mode = ata_limit_mode(dev, mode,
1027 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
1028
1029 mode = ata_check_80pin(dev, mode);
1030
1031 /* XXX SOS missing WDMA0+1 + PIO modes */
1032 if (mode >= ATA_WDMA2) {
1033 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1034 if (bootverbose)
1035 device_printf(dev, "%ssetting %s on %s chip\n",
1036 (error) ? "FAILURE " : "",
1037 ata_mode2str(mode), ctlr->chip->text);
1038 if (!error) {
1039 u_int16_t reg44 = pci_read_config(gparent, 0x44, 2);
1040
1041 reg44 &= ~(0x000f << (devno << 2));
1042 if (mode >= ATA_UDMA0)
1043 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2));
1044 pci_write_config(gparent, 0x44, reg44, 2);
1045 pci_write_config(gparent, 0x4a, 0xa6, 1);
1046 pci_write_config(gparent, 0x40 + devno, 0x31, 1);
1047 atadev->mode = mode;
1048 return;
1049 }
1050 }
1051 /* we could set PIO mode timings, but we assume the BIOS did that */
1052 }
1053
1054
1055 /*
1056 * Acer Labs Inc (ALI) chipset support functions
1057 */
1058 int
1059 ata_ali_ident(device_t dev)
1060 {
1061 struct ata_pci_controller *ctlr = device_get_softc(dev);
1062 static struct ata_chip_id ids[] =
1063 {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" },
1064 { ATA_ALI_5288, 0x00, 4, ALISATA, ATA_SA300, "M5288" },
1065 { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "M5287" },
1066 { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "M5281" },
1067 { ATA_ALI_5229, 0xc5, 0, ALINEW, ATA_UDMA6, "M5229" },
1068 { ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "M5229" },
1069 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "M5229" },
1070 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "M5229" },
1071 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "M5229" },
1072 { 0, 0, 0, 0, 0, 0}};
1073
1074 if (!(ctlr->chip = ata_match_chip(dev, ids)))
1075 return ENXIO;
1076
1077 ata_set_desc(dev);
1078 ctlr->chipinit = ata_ali_chipinit;
1079 return 0;
1080 }
1081
1082 static int
1083 ata_ali_chipinit(device_t dev)
1084 {
1085 struct ata_pci_controller *ctlr = device_get_softc(dev);
1086
1087 if (ata_setup_interrupt(dev))
1088 return ENXIO;
1089
1090 switch (ctlr->chip->cfg2) {
1091 case ALISATA:
1092 ctlr->channels = ctlr->chip->cfg1;
1093 ctlr->allocate = ata_ali_sata_allocate;
1094 ctlr->setmode = ata_sata_setmode;
1095
1096 /* AHCI mode is correctly supported only on the ALi 5288. */
1097 if ((ctlr->chip->chipid == ATA_ALI_5288) &&
1098 (ata_ahci_chipinit(dev) != ENXIO))
1099 return 0;
1100
1101 /* enable PCI interrupt */
1102 pci_write_config(dev, PCIR_COMMAND,
1103 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
1104 break;
1105
1106 case ALINEW:
1107 /* use device interrupt as byte count end */
1108 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
1109
1110 /* enable cable detection and UDMA support on newer chips */
1111 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1);
1112
1113 /* enable ATAPI UDMA mode */
1114 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1);
1115
1116 /* only chips with revision > 0xc4 can do 48bit DMA */
1117 if (ctlr->chip->chiprev <= 0xc4)
1118 device_printf(dev,
1119 "using PIO transfers above 137GB as workaround for "
1120 "48bit DMA access bug, expect reduced performance\n");
1121 ctlr->allocate = ata_ali_allocate;
1122 ctlr->reset = ata_ali_reset;
1123 ctlr->setmode = ata_ali_setmode;
1124 break;
1125
1126 case ALIOLD:
1127 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
1128 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
1129 ctlr->setmode = ata_ali_setmode;
1130 break;
1131 }
1132 return 0;
1133 }
1134
1135 static int
1136 ata_ali_allocate(device_t dev)
1137 {
1138 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1139 struct ata_channel *ch = device_get_softc(dev);
1140
1141 /* setup the usual register normal pci style */
1142 if (ata_pci_allocate(dev))
1143 return ENXIO;
1144
1145 /* older chips can't do 48bit DMA transfers */
1146 if (ctlr->chip->chiprev <= 0xc4)
1147 ch->flags |= ATA_NO_48BIT_DMA;
1148
1149 return 0;
1150 }
1151
1152 static int
1153 ata_ali_sata_allocate(device_t dev)
1154 {
1155 device_t parent = device_get_parent(dev);
1156 struct ata_pci_controller *ctlr = device_get_softc(parent);
1157 struct ata_channel *ch = device_get_softc(dev);
1158 struct resource *io = NULL, *ctlio = NULL;
1159 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
1160 int i, rid;
1161
1162 rid = PCIR_BAR(0) + (unit01 ? 8 : 0);
1163 io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1164 if (!io)
1165 return ENXIO;
1166
1167 rid = PCIR_BAR(1) + (unit01 ? 8 : 0);
1168 ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1169 if (!ctlio) {
1170 bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io);
1171 return ENXIO;
1172 }
1173
1174 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
1175 ch->r_io[i].res = io;
1176 ch->r_io[i].offset = i + (unit10 ? 8 : 0);
1177 }
1178 ch->r_io[ATA_CONTROL].res = ctlio;
1179 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0);
1180 ch->r_io[ATA_IDX_ADDR].res = io;
1181 ata_default_registers(dev);
1182 if (ctlr->r_res1) {
1183 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
1184 ch->r_io[i].res = ctlr->r_res1;
1185 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
1186 }
1187 }
1188 ch->flags |= ATA_NO_SLAVE;
1189
1190 /* XXX SOS PHY handling awkward in ALI chip not supported yet */
1191 ata_pci_hw(dev);
1192 return 0;
1193 }
1194
1195 static void
1196 ata_ali_reset(device_t dev)
1197 {
1198 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1199 struct ata_channel *ch = device_get_softc(dev);
1200 device_t *children;
1201 int nchildren, i;
1202
1203 ata_generic_reset(dev);
1204
1205 /*
1206 * workaround for datacorruption bug found on at least SUN Blade-100
1207 * find the ISA function on the southbridge and disable then enable
1208 * the ATA channel tristate buffer
1209 */
1210 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) {
1211 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) {
1212 for (i = 0; i < nchildren; i++) {
1213 if (pci_get_devid(children[i]) == ATA_ALI_1533) {
1214 pci_write_config(children[i], 0x58,
1215 pci_read_config(children[i], 0x58, 1) &
1216 ~(0x04 << ch->unit), 1);
1217 pci_write_config(children[i], 0x58,
1218 pci_read_config(children[i], 0x58, 1) |
1219 (0x04 << ch->unit), 1);
1220 break;
1221 }
1222 }
1223 free(children, M_TEMP);
1224 }
1225 }
1226 }
1227
1228 static void
1229 ata_ali_setmode(device_t dev, int mode)
1230 {
1231 device_t gparent = GRANDPARENT(dev);
1232 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1233 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1234 struct ata_device *atadev = device_get_softc(dev);
1235 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1236 int error;
1237
1238 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1239
1240 if (ctlr->chip->cfg2 & ALINEW) {
1241 if (mode > ATA_UDMA2 &&
1242 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) {
1243 ata_print_cable(dev, "controller");
1244 mode = ATA_UDMA2;
1245 }
1246 }
1247 else
1248 mode = ata_check_80pin(dev, mode);
1249
1250 if (ctlr->chip->cfg2 & ALIOLD) {
1251 /* doesn't support ATAPI DMA on write */
1252 ch->flags |= ATA_ATAPI_DMA_RO;
1253 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) {
1254 /* doesn't support ATAPI DMA on two ATAPI devices */
1255 device_printf(dev, "two atapi devices on this channel, no DMA\n");
1256 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1257 }
1258 }
1259
1260 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1261
1262 if (bootverbose)
1263 device_printf(dev, "%ssetting %s on %s chip\n",
1264 (error) ? "FAILURE " : "",
1265 ata_mode2str(mode), ctlr->chip->text);
1266 if (!error) {
1267 if (mode >= ATA_UDMA0) {
1268 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d};
1269 u_int32_t word54 = pci_read_config(gparent, 0x54, 4);
1270
1271 word54 &= ~(0x000f000f << (devno << 2));
1272 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
1273 pci_write_config(gparent, 0x54, word54, 4);
1274 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1275 0x00310001, 4);
1276 }
1277 else {
1278 u_int32_t piotimings[] =
1279 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
1280 0x00310001, 0x00440001, 0x00330001, 0x00310001};
1281
1282 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) &
1283 ~(0x0008000f << (devno << 2)), 4);
1284 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1285 piotimings[ata_mode2idx(mode)], 4);
1286 }
1287 atadev->mode = mode;
1288 }
1289 }
1290
1291
1292 /*
1293 * American Micro Devices (AMD) chipset support functions
1294 */
1295 int
1296 ata_amd_ident(device_t dev)
1297 {
1298 struct ata_pci_controller *ctlr = device_get_softc(dev);
1299 static struct ata_chip_id ids[] =
1300 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "756" },
1301 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "766" },
1302 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "768" },
1303 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "8111" },
1304 { ATA_AMD5536, 0x00, AMDNVIDIA, 0x00, ATA_UDMA5, "CS5536" },
1305 { 0, 0, 0, 0, 0, 0}};
1306
1307 if (!(ctlr->chip = ata_match_chip(dev, ids)))
1308 return ENXIO;
1309
1310 ata_set_desc(dev);
1311 ctlr->chipinit = ata_amd_chipinit;
1312 return 0;
1313 }
1314
1315 static int
1316 ata_amd_chipinit(device_t dev)
1317 {
1318 struct ata_pci_controller *ctlr = device_get_softc(dev);
1319
1320 if (ata_setup_interrupt(dev))
1321 return ENXIO;
1322
1323 /* disable/set prefetch, postwrite */
1324 if (ctlr->chip->cfg2 & AMDBUG)
1325 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1);
1326 else
1327 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
1328
1329 ctlr->setmode = ata_via_family_setmode;
1330 return 0;
1331 }
1332
1333
1334 /*
1335 * ATI chipset support functions
1336 */
1337 int
1338 ata_ati_ident(device_t dev)
1339 {
1340 struct ata_pci_controller *ctlr = device_get_softc(dev);
1341 static struct ata_chip_id ids[] =
1342 {{ ATA_ATI_IXP200, 0x00, 0, 0, ATA_UDMA5, "IXP200" },
1343 { ATA_ATI_IXP300, 0x00, 0, 0, ATA_UDMA6, "IXP300" },
1344 { ATA_ATI_IXP300_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP300" },
1345 { ATA_ATI_IXP400, 0x00, 0, 0, ATA_UDMA6, "IXP400" },
1346 { ATA_ATI_IXP400_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" },
1347 { ATA_ATI_IXP400_S2, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" },
1348 { ATA_ATI_IXP600, 0x00, 0, 0, ATA_UDMA6, "IXP600" },
1349 { ATA_ATI_IXP700, 0x00, 0, 0, ATA_UDMA6, "IXP700" },
1350 { 0, 0, 0, 0, 0, 0}};
1351
1352 if (!(ctlr->chip = ata_match_chip(dev, ids)))
1353 return ENXIO;
1354
1355 ata_set_desc(dev);
1356
1357 /* the ATI SATA controller is actually a SiI 3112 controller*/
1358 if (ctlr->chip->cfg1 & SIIMEMIO)
1359 ctlr->chipinit = ata_sii_chipinit;
1360 else
1361 ctlr->chipinit = ata_ati_chipinit;
1362 return 0;
1363 }
1364
1365 static int
1366 ata_ati_chipinit(device_t dev)
1367 {
1368 struct ata_pci_controller *ctlr = device_get_softc(dev);
1369
1370 if (ata_setup_interrupt(dev))
1371 return ENXIO;
1372
1373 /* IXP600 & IXP700 only have 1 PATA channel */
1374 if ((ctlr->chip->chipid == ATA_ATI_IXP600) ||
1375 (ctlr->chip->chipid == ATA_ATI_IXP700))
1376 ctlr->channels = 1;
1377
1378 ctlr->setmode = ata_ati_setmode;
1379 return 0;
1380 }
1381
1382 static void
1383 ata_ati_setmode(device_t dev, int mode)
1384 {
1385 device_t gparent = GRANDPARENT(dev);
1386 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1387 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1388 struct ata_device *atadev = device_get_softc(dev);
1389 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1390 int offset = (devno ^ 0x01) << 3;
1391 int error;
1392 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1393 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1394 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
1395
1396 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1397
1398 mode = ata_check_80pin(dev, mode);
1399
1400 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1401
1402 if (bootverbose)
1403 device_printf(dev, "%ssetting %s on %s chip\n",
1404 (error) ? "FAILURE " : "",
1405 ata_mode2str(mode), ctlr->chip->text);
1406 if (!error) {
1407 if (mode >= ATA_UDMA0) {
1408 pci_write_config(gparent, 0x56,
1409 (pci_read_config(gparent, 0x56, 2) &
1410 ~(0xf << (devno << 2))) |
1411 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
1412 pci_write_config(gparent, 0x54,
1413 pci_read_config(gparent, 0x54, 1) |
1414 (0x01 << devno), 1);
1415 pci_write_config(gparent, 0x44,
1416 (pci_read_config(gparent, 0x44, 4) &
1417 ~(0xff << offset)) |
1418 (dmatimings[2] << offset), 4);
1419 }
1420 else if (mode >= ATA_WDMA0) {
1421 pci_write_config(gparent, 0x54,
1422 pci_read_config(gparent, 0x54, 1) &
1423 ~(0x01 << devno), 1);
1424 pci_write_config(gparent, 0x44,
1425 (pci_read_config(gparent, 0x44, 4) &
1426 ~(0xff << offset)) |
1427 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
1428 }
1429 else
1430 pci_write_config(gparent, 0x54,
1431 pci_read_config(gparent, 0x54, 1) &
1432 ~(0x01 << devno), 1);
1433
1434 pci_write_config(gparent, 0x4a,
1435 (pci_read_config(gparent, 0x4a, 2) &
1436 ~(0xf << (devno << 2))) |
1437 (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2);
1438 pci_write_config(gparent, 0x40,
1439 (pci_read_config(gparent, 0x40, 4) &
1440 ~(0xff << offset)) |
1441 (piotimings[ata_mode2idx(mode)] << offset), 4);
1442 atadev->mode = mode;
1443 }
1444 }
1445
1446
1447 /*
1448 * Cyrix chipset support functions
1449 */
1450 int
1451 ata_cyrix_ident(device_t dev)
1452 {
1453 struct ata_pci_controller *ctlr = device_get_softc(dev);
1454
1455 if (pci_get_devid(dev) == ATA_CYRIX_5530) {
1456 device_set_desc(dev, "Cyrix 5530 ATA33 controller");
1457 ctlr->chipinit = ata_cyrix_chipinit;
1458 return 0;
1459 }
1460 return ENXIO;
1461 }
1462
1463 static int
1464 ata_cyrix_chipinit(device_t dev)
1465 {
1466 struct ata_pci_controller *ctlr = device_get_softc(dev);
1467
1468 if (ata_setup_interrupt(dev))
1469 return ENXIO;
1470
1471 if (ctlr->r_res1)
1472 ctlr->setmode = ata_cyrix_setmode;
1473 else
1474 ctlr->setmode = ata_generic_setmode;
1475 return 0;
1476 }
1477
1478 static void
1479 ata_cyrix_setmode(device_t dev, int mode)
1480 {
1481 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1482 struct ata_device *atadev = device_get_softc(dev);
1483 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1484 u_int32_t piotiming[] =
1485 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
1486 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
1487 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
1488 int error;
1489
1490 ch->dma->alignment = 16;
1491 ch->dma->max_iosize = 126 * DEV_BSIZE;
1492
1493 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
1494
1495 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1496
1497 if (bootverbose)
1498 device_printf(dev, "%ssetting %s on Cyrix chip\n",
1499 (error) ? "FAILURE " : "", ata_mode2str(mode));
1500 if (!error) {
1501 if (mode >= ATA_UDMA0) {
1502 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1503 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]);
1504 }
1505 else if (mode >= ATA_WDMA0) {
1506 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1507 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]);
1508 }
1509 else {
1510 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1511 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]);
1512 }
1513 atadev->mode = mode;
1514 }
1515 }
1516
1517
1518 /*
1519 * Cypress chipset support functions
1520 */
1521 int
1522 ata_cypress_ident(device_t dev)
1523 {
1524 struct ata_pci_controller *ctlr = device_get_softc(dev);
1525
1526 /*
1527 * the Cypress chip is a mess, it contains two ATA functions, but
1528 * both channels are visible on the first one.
1529 * simply ignore the second function for now, as the right
1530 * solution (ignoring the second channel on the first function)
1531 * doesn't work with the crappy ATA interrupt setup on the alpha.
1532 */
1533 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 &&
1534 pci_get_function(dev) == 1 &&
1535 pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
1536 device_set_desc(dev, "Cypress 82C693 ATA controller");
1537 ctlr->chipinit = ata_cypress_chipinit;
1538 return 0;
1539 }
1540 return ENXIO;
1541 }
1542
1543 static int
1544 ata_cypress_chipinit(device_t dev)
1545 {
1546 struct ata_pci_controller *ctlr = device_get_softc(dev);
1547
1548 if (ata_setup_interrupt(dev))
1549 return ENXIO;
1550
1551 ctlr->setmode = ata_cypress_setmode;
1552 return 0;
1553 }
1554
1555 static void
1556 ata_cypress_setmode(device_t dev, int mode)
1557 {
1558 device_t gparent = GRANDPARENT(dev);
1559 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1560 struct ata_device *atadev = device_get_softc(dev);
1561 int error;
1562
1563 mode = ata_limit_mode(dev, mode, ATA_WDMA2);
1564
1565 /* XXX SOS missing WDMA0+1 + PIO modes */
1566 if (mode == ATA_WDMA2) {
1567 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1568 if (bootverbose)
1569 device_printf(dev, "%ssetting WDMA2 on Cypress chip\n",
1570 error ? "FAILURE " : "");
1571 if (!error) {
1572 pci_write_config(gparent, ch->unit ? 0x4e : 0x4c, 0x2020, 2);
1573 atadev->mode = mode;
1574 return;
1575 }
1576 }
1577 /* we could set PIO mode timings, but we assume the BIOS did that */
1578 }
1579
1580
1581 /*
1582 * HighPoint chipset support functions
1583 */
1584 int
1585 ata_highpoint_ident(device_t dev)
1586 {
1587 struct ata_pci_controller *ctlr = device_get_softc(dev);
1588 struct ata_chip_id *idx;
1589 static struct ata_chip_id ids[] =
1590 {{ ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HPT374" },
1591 { ATA_HPT372, 0x02, HPT372, 0x00, ATA_UDMA6, "HPT372N" },
1592 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1593 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT371" },
1594 { ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1595 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HPT370" },
1596 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HPT368" },
1597 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HPT366" },
1598 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT302" },
1599 { 0, 0, 0, 0, 0, 0}};
1600 char buffer[64];
1601
1602 if (!(idx = ata_match_chip(dev, ids)))
1603 return ENXIO;
1604
1605 strcpy(buffer, "HighPoint ");
1606 strcat(buffer, idx->text);
1607 if (idx->cfg1 == HPT374) {
1608 if (pci_get_function(dev) == 0)
1609 strcat(buffer, " (channel 0+1)");
1610 if (pci_get_function(dev) == 1)
1611 strcat(buffer, " (channel 2+3)");
1612 }
1613 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
1614 device_set_desc_copy(dev, buffer);
1615 ctlr->chip = idx;
1616 ctlr->chipinit = ata_highpoint_chipinit;
1617 return 0;
1618 }
1619
1620 static int
1621 ata_highpoint_chipinit(device_t dev)
1622 {
1623 struct ata_pci_controller *ctlr = device_get_softc(dev);
1624
1625 if (ata_setup_interrupt(dev))
1626 return ENXIO;
1627
1628 if (ctlr->chip->cfg2 == HPTOLD) {
1629 /* disable interrupt prediction */
1630 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
1631 }
1632 else {
1633 /* disable interrupt prediction */
1634 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
1635 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
1636
1637 /* enable interrupts */
1638 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
1639
1640 /* set clocks etc */
1641 if (ctlr->chip->cfg1 < HPT372)
1642 pci_write_config(dev, 0x5b, 0x22, 1);
1643 else
1644 pci_write_config(dev, 0x5b,
1645 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
1646 }
1647 ctlr->allocate = ata_highpoint_allocate;
1648 ctlr->setmode = ata_highpoint_setmode;
1649 return 0;
1650 }
1651
1652 static int
1653 ata_highpoint_allocate(device_t dev)
1654 {
1655 struct ata_channel *ch = device_get_softc(dev);
1656
1657 /* setup the usual register normal pci style */
1658 if (ata_pci_allocate(dev))
1659 return ENXIO;
1660
1661 ch->flags |= ATA_ALWAYS_DMASTAT;
1662 return 0;
1663 }
1664
1665 static void
1666 ata_highpoint_setmode(device_t dev, int mode)
1667 {
1668 device_t gparent = GRANDPARENT(dev);
1669 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1670 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1671 struct ata_device *atadev = device_get_softc(dev);
1672 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1673 int error;
1674 u_int32_t timings33[][4] = {
1675 /* HPT366 HPT370 HPT372 HPT374 mode */
1676 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
1677 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
1678 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
1679 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
1680 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
1681 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
1682 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
1683 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
1684 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */
1685 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */
1686 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */
1687 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */
1688 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */
1689 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */
1690 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */
1691 };
1692
1693 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1694
1695 if (ctlr->chip->cfg1 == HPT366 && ata_atapi(dev))
1696 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1697
1698 mode = ata_highpoint_check_80pin(dev, mode);
1699
1700 /*
1701 * most if not all HPT chips cant really handle that the device is
1702 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to
1703 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance
1704 */
1705 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
1706 ata_limit_mode(dev, mode, ATA_UDMA5));
1707 if (bootverbose)
1708 device_printf(dev, "%ssetting %s on HighPoint chip\n",
1709 (error) ? "FAILURE " : "", ata_mode2str(mode));
1710 if (!error)
1711 pci_write_config(gparent, 0x40 + (devno << 2),
1712 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
1713 atadev->mode = mode;
1714 }
1715
1716 static int
1717 ata_highpoint_check_80pin(device_t dev, int mode)
1718 {
1719 device_t gparent = GRANDPARENT(dev);
1720 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1721 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1722 u_int8_t reg, val, res;
1723
1724 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(gparent) == 1) {
1725 reg = ch->unit ? 0x57 : 0x53;
1726 val = pci_read_config(gparent, reg, 1);
1727 pci_write_config(gparent, reg, val | 0x80, 1);
1728 }
1729 else {
1730 reg = 0x5b;
1731 val = pci_read_config(gparent, reg, 1);
1732 pci_write_config(gparent, reg, val & 0xfe, 1);
1733 }
1734 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2);
1735 pci_write_config(gparent, reg, val, 1);
1736
1737 if (mode > ATA_UDMA2 && res) {
1738 ata_print_cable(dev, "controller");
1739 mode = ATA_UDMA2;
1740 }
1741 return mode;
1742 }
1743
1744
1745 /*
1746 * Intel chipset support functions
1747 */
1748 int
1749 ata_intel_ident(device_t dev)
1750 {
1751 struct ata_pci_controller *ctlr = device_get_softc(dev);
1752 static struct ata_chip_id ids[] =
1753 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "PIIX" },
1754 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "PIIX3" },
1755 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1756 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1757 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1758 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "ICH0" },
1759 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "ICH" },
1760 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "ICH" },
1761 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "ICH2" },
1762 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "ICH2" },
1763 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "ICH3" },
1764 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "ICH3" },
1765 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "ICH4" },
1766 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "ICH4" },
1767 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "ICH5" },
1768 { ATA_I82801EB_S1, 0, 0, 0x00, ATA_SA150, "ICH5" },
1769 { ATA_I82801EB_R1, 0, 0, 0x00, ATA_SA150, "ICH5" },
1770 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "6300ESB" },
1771 { ATA_I6300ESB_S1, 0, 0, 0x00, ATA_SA150, "6300ESB" },
1772 { ATA_I6300ESB_R1, 0, 0, 0x00, ATA_SA150, "6300ESB" },
1773 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "ICH6" },
1774 { ATA_I82801FB_S1, 0, AHCI, 0x00, ATA_SA150, "ICH6" },
1775 { ATA_I82801FB_R1, 0, AHCI, 0x00, ATA_SA150, "ICH6" },
1776 { ATA_I82801FBM, 0, AHCI, 0x00, ATA_SA150, "ICH6M" },
1777 { ATA_I82801GB, 0, 0, 0x00, ATA_UDMA5, "ICH7" },
1778 { ATA_I82801GB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1779 { ATA_I82801GB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1780 { ATA_I82801GB_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1781 { ATA_I82801GBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1782 { ATA_I82801GBM_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1783 { ATA_I82801GBM_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1784 { ATA_I63XXESB2, 0, 0, 0x00, ATA_UDMA5, "63XXESB2" },
1785 { ATA_I63XXESB2_S1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1786 { ATA_I63XXESB2_S2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1787 { ATA_I63XXESB2_R1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1788 { ATA_I63XXESB2_R2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1789 { ATA_I82801HB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1790 { ATA_I82801HB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1791 { ATA_I82801HB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1792 { ATA_I82801HB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1793 { ATA_I82801HB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1794 { ATA_I82801HBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8M" },
1795 { ATA_I82801HBM_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8M" },
1796 { ATA_I82801IB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1797 { ATA_I82801IB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1798 { ATA_I82801IB_AH2, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1799 { ATA_I82801IB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1800 { ATA_I82801IB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1801 { ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" },
1802 { 0, 0, 0, 0, 0, 0}};
1803
1804 if (!(ctlr->chip = ata_match_chip(dev, ids)))
1805 return ENXIO;
1806
1807 ata_set_desc(dev);
1808 ctlr->chipinit = ata_intel_chipinit;
1809 return 0;
1810 }
1811
1812 static int
1813 ata_intel_chipinit(device_t dev)
1814 {
1815 struct ata_pci_controller *ctlr = device_get_softc(dev);
1816
1817 if (ata_setup_interrupt(dev))
1818 return ENXIO;
1819
1820 /* good old PIIX needs special treatment (not implemented) */
1821 if (ctlr->chip->chipid == ATA_I82371FB) {
1822 ctlr->setmode = ata_intel_old_setmode;
1823 }
1824
1825 /* the intel 31244 needs special care if in DPA mode */
1826 else if (ctlr->chip->chipid == ATA_I31244) {
1827 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) {
1828 ctlr->r_type2 = SYS_RES_MEMORY;
1829 ctlr->r_rid2 = PCIR_BAR(0);
1830 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1831 &ctlr->r_rid2,
1832 RF_ACTIVE)))
1833 return ENXIO;
1834 ctlr->channels = 4;
1835 ctlr->allocate = ata_intel_31244_allocate;
1836 ctlr->reset = ata_intel_31244_reset;
1837 }
1838 ctlr->setmode = ata_sata_setmode;
1839 }
1840
1841 /* non SATA intel chips goes here */
1842 else if (ctlr->chip->max_dma < ATA_SA150) {
1843 ctlr->allocate = ata_intel_allocate;
1844 ctlr->setmode = ata_intel_new_setmode;
1845 }
1846
1847 /* SATA parts can be either compat or AHCI */
1848 else {
1849 /* force all ports active "the legacy way" */
1850 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2);
1851
1852 ctlr->allocate = ata_intel_allocate;
1853 ctlr->reset = ata_intel_reset;
1854
1855 /*
1856 * if we have AHCI capability and AHCI or RAID mode enabled
1857 * in BIOS we try for AHCI mode
1858 */
1859 if ((ctlr->chip->cfg1 == AHCI) &&
1860 (pci_read_config(dev, 0x90, 1) & 0xc0) &&
1861 (ata_ahci_chipinit(dev) != ENXIO))
1862 return 0;
1863
1864 /* if BAR(5) is IO it should point to SATA interface registers */
1865 ctlr->r_type2 = SYS_RES_IOPORT;
1866 ctlr->r_rid2 = PCIR_BAR(5);
1867 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1868 &ctlr->r_rid2, RF_ACTIVE)))
1869 ctlr->setmode = ata_intel_sata_setmode;
1870 else
1871 ctlr->setmode = ata_sata_setmode;
1872
1873 /* enable PCI interrupt */
1874 pci_write_config(dev, PCIR_COMMAND,
1875 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
1876 }
1877 return 0;
1878 }
1879
1880 static int
1881 ata_intel_allocate(device_t dev)
1882 {
1883 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1884 struct ata_channel *ch = device_get_softc(dev);
1885
1886 /* setup the usual register normal pci style */
1887 if (ata_pci_allocate(dev))
1888 return ENXIO;
1889
1890 /* if r_res2 is valid it points to SATA interface registers */
1891 if (ctlr->r_res2) {
1892 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
1893 ch->r_io[ATA_IDX_ADDR].offset = 0x00;
1894 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2;
1895 ch->r_io[ATA_IDX_DATA].offset = 0x04;
1896 }
1897
1898 ch->flags |= ATA_ALWAYS_DMASTAT;
1899 return 0;
1900 }
1901
1902 static void
1903 ata_intel_reset(device_t dev)
1904 {
1905 device_t parent = device_get_parent(dev);
1906 struct ata_pci_controller *ctlr = device_get_softc(parent);
1907 struct ata_channel *ch = device_get_softc(dev);
1908 int mask, timeout;
1909
1910 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */
1911 if (ctlr->chip->cfg1) {
1912 mask = (0x0005 << ch->unit);
1913 }
1914 else {
1915 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */
1916 if (pci_read_config(parent, 0x90, 1) & 0x04)
1917 mask = 0x0003;
1918 else {
1919 mask = (0x0001 << ch->unit);
1920 /* XXX SOS should be in intel_allocate if we grow it */
1921 ch->flags |= ATA_NO_SLAVE;
1922 }
1923 }
1924 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2);
1925 DELAY(10);
1926 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2);
1927
1928 /* wait up to 1 sec for "connect well" */
1929 for (timeout = 0; timeout < 100 ; timeout++) {
1930 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) &&
1931 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff))
1932 break;
1933 ata_udelay(10000);
1934 }
1935 ata_generic_reset(dev);
1936 }
1937
1938 static void
1939 ata_intel_old_setmode(device_t dev, int mode)
1940 {
1941 /* NOT YET */
1942 }
1943
1944 static void
1945 ata_intel_new_setmode(device_t dev, int mode)
1946 {
1947 device_t gparent = GRANDPARENT(dev);
1948 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1949 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1950 struct ata_device *atadev = device_get_softc(dev);
1951 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1952 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4);
1953 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1);
1954 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1);
1955 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2);
1956 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2);
1957 u_int32_t mask40 = 0, new40 = 0;
1958 u_int8_t mask44 = 0, new44 = 0;
1959 int error;
1960 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
1961 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
1962
1963 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1964
1965 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
1966 ata_print_cable(dev, "controller");
1967 mode = ATA_UDMA2;
1968 }
1969
1970 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1971
1972 if (bootverbose)
1973 device_printf(dev, "%ssetting %s on %s chip\n",
1974 (error) ? "FAILURE " : "",
1975 ata_mode2str(mode), ctlr->chip->text);
1976 if (error)
1977 return;
1978
1979 if (mode >= ATA_UDMA0) {
1980 pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2);
1981 pci_write_config(gparent, 0x4a,
1982 (reg4a & ~(0x3 << (devno << 2))) |
1983 ((0x01 + !(mode & 0x01)) << (devno << 2)), 2);
1984 }
1985 else {
1986 pci_write_config(gparent, 0x48, reg48 & ~(0x0001 << devno), 2);
1987 pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))), 2);
1988 }
1989 reg54 |= 0x0400;
1990 if (mode >= ATA_UDMA2)
1991 pci_write_config(gparent, 0x54, reg54 | (0x1 << devno), 2);
1992 else
1993 pci_write_config(gparent, 0x54, reg54 & ~(0x1 << devno), 2);
1994
1995 if (mode >= ATA_UDMA5)
1996 pci_write_config(gparent, 0x54, reg54 | (0x1000 << devno), 2);
1997 else
1998 pci_write_config(gparent, 0x54, reg54 & ~(0x1000 << devno), 2);
1999
2000 reg40 &= ~0x00ff00ff;
2001 reg40 |= 0x40774077;
2002
2003 if (atadev->unit == ATA_MASTER) {
2004 mask40 = 0x3300;
2005 new40 = timings[ata_mode2idx(mode)] << 8;
2006 }
2007 else {
2008 mask44 = 0x0f;
2009 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
2010 (timings[ata_mode2idx(mode)] & 0x03);
2011 }
2012 if (ch->unit) {
2013 mask40 <<= 16;
2014 new40 <<= 16;
2015 mask44 <<= 4;
2016 new44 <<= 4;
2017 }
2018 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4);
2019 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1);
2020
2021 atadev->mode = mode;
2022 }
2023
2024 static void
2025 ata_intel_sata_setmode(device_t dev, int mode)
2026 {
2027 struct ata_device *atadev = device_get_softc(dev);
2028
2029 if (atadev->param.satacapabilities != 0x0000 &&
2030 atadev->param.satacapabilities != 0xffff) {
2031
2032 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2033 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2034
2035 /* on some drives we need to set the transfer mode */
2036 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
2037 ata_limit_mode(dev, mode, ATA_UDMA6));
2038
2039 /* set ATA_SSTATUS register offset */
2040 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, devno * 0x100);
2041
2042 /* query SATA STATUS for the speed */
2043 if ((ATA_IDX_INL(ch, ATA_IDX_DATA) & ATA_SS_CONWELL_MASK) ==
2044 ATA_SS_CONWELL_GEN2)
2045 atadev->mode = ATA_SA300;
2046 else
2047 atadev->mode = ATA_SA150;
2048 }
2049 else {
2050 mode = ata_limit_mode(dev, mode, ATA_UDMA5);
2051 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2052 atadev->mode = mode;
2053 }
2054 }
2055
2056 static int
2057 ata_intel_31244_allocate(device_t dev)
2058 {
2059 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2060 struct ata_channel *ch = device_get_softc(dev);
2061 int i;
2062 int ch_offset;
2063
2064 ch_offset = 0x200 + ch->unit * 0x200;
2065
2066 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
2067 ch->r_io[i].res = ctlr->r_res2;
2068
2069 /* setup ATA registers */
2070 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
2071 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06;
2072 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
2073 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
2074 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
2075 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
2076 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
2077 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d;
2078 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04;
2079 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c;
2080 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28;
2081 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29;
2082
2083 /* setup DMA registers */
2084 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100;
2085 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104;
2086 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108;
2087
2088 /* setup SATA registers */
2089 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70;
2090 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72;
2091 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74;
2092
2093 ch->flags |= ATA_NO_SLAVE;
2094 ata_pci_hw(dev);
2095 ch->hw.status = ata_intel_31244_status;
2096 ch->hw.command = ata_intel_31244_command;
2097
2098 /* enable PHY state change interrupt */
2099 ATA_OUTL(ctlr->r_res2, 0x4,
2100 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3)));
2101 return 0;
2102 }
2103
2104 static int
2105 ata_intel_31244_status(device_t dev)
2106 {
2107 /* do we have any PHY events ? */
2108 ata_sata_phy_check_events(dev);
2109
2110 /* any drive action to take care of ? */
2111 return ata_pci_status(dev);
2112 }
2113
2114 static int
2115 ata_intel_31244_command(struct ata_request *request)
2116 {
2117 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2118 struct ata_device *atadev = device_get_softc(request->dev);
2119 u_int64_t lba;
2120
2121 if (!(atadev->flags & ATA_D_48BIT_ACTIVE))
2122 return (ata_generic_command(request));
2123
2124 lba = request->u.ata.lba;
2125 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit);
2126 /* enable interrupt */
2127 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
2128 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
2129 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
2130 ATA_IDX_OUTW(ch, ATA_SECTOR, ((lba >> 16) & 0xff00) | (lba & 0x00ff));
2131 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((lba >> 24) & 0xff00) |
2132 ((lba >> 8) & 0x00ff));
2133 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((lba >> 32) & 0xff00) |
2134 ((lba >> 16) & 0x00ff));
2135
2136 /* issue command to controller */
2137 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command);
2138
2139 return 0;
2140 }
2141
2142 static void
2143 ata_intel_31244_reset(device_t dev)
2144 {
2145 if (ata_sata_phy_reset(dev))
2146 ata_generic_reset(dev);
2147 }
2148
2149
2150 /*
2151 * Integrated Technology Express Inc. (ITE) chipset support functions
2152 */
2153 int
2154 ata_ite_ident(device_t dev)
2155 {
2156 struct ata_pci_controller *ctlr = device_get_softc(dev);
2157 static struct ata_chip_id ids[] =
2158 {{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" },
2159 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" },
2160 { 0, 0, 0, 0, 0, 0}};
2161
2162 if (!(ctlr->chip = ata_match_chip(dev, ids)))
2163 return ENXIO;
2164
2165 ata_set_desc(dev);
2166 ctlr->chipinit = ata_ite_chipinit;
2167 return 0;
2168 }
2169
2170 static int
2171 ata_ite_chipinit(device_t dev)
2172 {
2173 struct ata_pci_controller *ctlr = device_get_softc(dev);
2174
2175 if (ata_setup_interrupt(dev))
2176 return ENXIO;
2177
2178 ctlr->setmode = ata_ite_setmode;
2179
2180 /* set PCI mode and 66Mhz reference clock */
2181 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1);
2182
2183 /* set default active & recover timings */
2184 pci_write_config(dev, 0x54, 0x31, 1);
2185 pci_write_config(dev, 0x56, 0x31, 1);
2186 return 0;
2187 }
2188
2189 static void
2190 ata_ite_setmode(device_t dev, int mode)
2191 {
2192 device_t gparent = GRANDPARENT(dev);
2193 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2194 struct ata_device *atadev = device_get_softc(dev);
2195 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2196 int error;
2197
2198 /* correct the mode for what the HW supports */
2199 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2200
2201 /* check the CBLID bits for 80 conductor cable detection */
2202 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) &
2203 (ch->unit ? (1<<3) : (1<<2)))) {
2204 ata_print_cable(dev, "controller");
2205 mode = ATA_UDMA2;
2206 }
2207
2208 /* set the wanted mode on the device */
2209 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2210
2211 if (bootverbose)
2212 device_printf(dev, "%s setting %s on ITE8212F chip\n",
2213 (error) ? "failed" : "success", ata_mode2str(mode));
2214
2215 /* if the device accepted the mode change, setup the HW accordingly */
2216 if (!error) {
2217 if (mode >= ATA_UDMA0) {
2218 u_int8_t udmatiming[] =
2219 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
2220
2221 /* enable UDMA mode */
2222 pci_write_config(gparent, 0x50,
2223 pci_read_config(gparent, 0x50, 1) &
2224 ~(1 << (devno + 3)), 1);
2225
2226 /* set UDMA timing */
2227 pci_write_config(gparent,
2228 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit),
2229 udmatiming[mode & ATA_MODE_MASK], 1);
2230 }
2231 else {
2232 u_int8_t chtiming[] =
2233 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
2234
2235 /* disable UDMA mode */
2236 pci_write_config(gparent, 0x50,
2237 pci_read_config(gparent, 0x50, 1) |
2238 (1 << (devno + 3)), 1);
2239
2240 /* set active and recover timing (shared between master & slave) */
2241 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) <
2242 chtiming[ata_mode2idx(mode)])
2243 pci_write_config(gparent, 0x54 + (ch->unit << 2),
2244 chtiming[ata_mode2idx(mode)], 1);
2245 }
2246 atadev->mode = mode;
2247 }
2248 }
2249
2250
2251 /*
2252 * JMicron chipset support functions
2253 */
2254 int
2255 ata_jmicron_ident(device_t dev)
2256 {
2257 struct ata_pci_controller *ctlr = device_get_softc(dev);
2258 struct ata_chip_id *idx;
2259 static struct ata_chip_id ids[] =
2260 {{ ATA_JMB360, 0, 1, 0, ATA_SA300, "JMB360" },
2261 { ATA_JMB361, 0, 1, 1, ATA_SA300, "JMB361" },
2262 { ATA_JMB363, 0, 2, 1, ATA_SA300, "JMB363" },
2263 { ATA_JMB365, 0, 1, 2, ATA_SA300, "JMB365" },
2264 { ATA_JMB366, 0, 2, 2, ATA_SA300, "JMB366" },
2265 { ATA_JMB368, 0, 0, 1, ATA_UDMA6, "JMB368" },
2266 { 0, 0, 0, 0, 0, 0}};
2267 char buffer[64];
2268
2269 if (!(idx = ata_match_chip(dev, ids)))
2270 return ENXIO;
2271
2272 if ((pci_read_config(dev, 0xdf, 1) & 0x40) &&
2273 (pci_get_function(dev) == (pci_read_config(dev, 0x40, 1) & 0x02 >> 1)))
2274 sprintf(buffer, "JMicron %s %s controller",
2275 idx->text, ata_mode2str(ATA_UDMA6));
2276 else
2277 sprintf(buffer, "JMicron %s %s controller",
2278 idx->text, ata_mode2str(idx->max_dma));
2279 device_set_desc_copy(dev, buffer);
2280 ctlr->chip = idx;
2281 ctlr->chipinit = ata_jmicron_chipinit;
2282 return 0;
2283 }
2284
2285 static int
2286 ata_jmicron_chipinit(device_t dev)
2287 {
2288 struct ata_pci_controller *ctlr = device_get_softc(dev);
2289 int error;
2290
2291 if (ata_setup_interrupt(dev))
2292 return ENXIO;
2293
2294 /* do we have multiple PCI functions ? */
2295 if (pci_read_config(dev, 0xdf, 1) & 0x40) {
2296 /* are we on the AHCI part ? */
2297 if (ata_ahci_chipinit(dev) != ENXIO)
2298 return 0;
2299
2300 /* otherwise we are on the PATA part */
2301 ctlr->allocate = ata_pci_allocate;
2302 ctlr->reset = ata_generic_reset;
2303 ctlr->dmainit = ata_pci_dmainit;
2304 ctlr->setmode = ata_jmicron_setmode;
2305 ctlr->channels = ctlr->chip->cfg2;
2306 }
2307 else {
2308 /* set controller configuration to a combined setup we support */
2309 pci_write_config(dev, 0x40, 0x80c0a131, 4);
2310 pci_write_config(dev, 0x80, 0x01200000, 4);
2311
2312 if (ctlr->chip->cfg1 && (error = ata_ahci_chipinit(dev)))
2313 return error;
2314
2315 ctlr->allocate = ata_jmicron_allocate;
2316 ctlr->reset = ata_jmicron_reset;
2317 ctlr->dmainit = ata_jmicron_dmainit;
2318 ctlr->setmode = ata_jmicron_setmode;
2319
2320 /* set the number of HW channels */
2321 ctlr->channels = ctlr->chip->cfg1 + ctlr->chip->cfg2;
2322 }
2323 return 0;
2324 }
2325
2326 static int
2327 ata_jmicron_allocate(device_t dev)
2328 {
2329 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2330 struct ata_channel *ch = device_get_softc(dev);
2331 int error;
2332
2333 if (ch->unit >= ctlr->chip->cfg1) {
2334 ch->unit -= ctlr->chip->cfg1;
2335 error = ata_pci_allocate(dev);
2336 ch->unit += ctlr->chip->cfg1;
2337 }
2338 else
2339 error = ata_ahci_allocate(dev);
2340 return error;
2341 }
2342
2343 static void
2344 ata_jmicron_reset(device_t dev)
2345 {
2346 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2347 struct ata_channel *ch = device_get_softc(dev);
2348
2349 if (ch->unit >= ctlr->chip->cfg1)
2350 ata_generic_reset(dev);
2351 else
2352 ata_ahci_reset(dev);
2353 }
2354
2355 static void
2356 ata_jmicron_dmainit(device_t dev)
2357 {
2358 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2359 struct ata_channel *ch = device_get_softc(dev);
2360
2361 if (ch->unit >= ctlr->chip->cfg1)
2362 ata_pci_dmainit(dev);
2363 else
2364 ata_ahci_dmainit(dev);
2365 }
2366
2367 static void
2368 ata_jmicron_setmode(device_t dev, int mode)
2369 {
2370 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
2371 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2372
2373 if (pci_read_config(dev, 0xdf, 1) & 0x40 || ch->unit >= ctlr->chip->cfg1) {
2374 struct ata_device *atadev = device_get_softc(dev);
2375
2376 /* check for 80pin cable present */
2377 if (pci_read_config(dev, 0x40, 1) & 0x08)
2378 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
2379 else
2380 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2381
2382 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2383 atadev->mode = mode;
2384 }
2385 else
2386 ata_sata_setmode(dev, mode);
2387 }
2388
2389
2390 /*
2391 * Marvell chipset support functions
2392 */
2393 #define ATA_MV_HOST_BASE(ch) \
2394 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000)
2395 #define ATA_MV_EDMA_BASE(ch) \
2396 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000)
2397
2398 struct ata_marvell_response {
2399 u_int16_t tag;
2400 u_int8_t edma_status;
2401 u_int8_t dev_status;
2402 u_int32_t timestamp;
2403 };
2404
2405 struct ata_marvell_dma_prdentry {
2406 u_int32_t addrlo;
2407 u_int32_t count;
2408 u_int32_t addrhi;
2409 u_int32_t reserved;
2410 };
2411
2412 int
2413 ata_marvell_ident(device_t dev)
2414 {
2415 struct ata_pci_controller *ctlr = device_get_softc(dev);
2416 static struct ata_chip_id ids[] =
2417 {{ ATA_M88SX5040, 0, 4, MV50XX, ATA_SA150, "88SX5040" },
2418 { ATA_M88SX5041, 0, 4, MV50XX, ATA_SA150, "88SX5041" },
2419 { ATA_M88SX5080, 0, 8, MV50XX, ATA_SA150, "88SX5080" },
2420 { ATA_M88SX5081, 0, 8, MV50XX, ATA_SA150, "88SX5081" },
2421 { ATA_M88SX6041, 0, 4, MV60XX, ATA_SA300, "88SX6041" },
2422 { ATA_M88SX6081, 0, 8, MV60XX, ATA_SA300, "88SX6081" },
2423 { ATA_M88SX6101, 0, 1, MV61XX, ATA_UDMA6, "88SX6101" },
2424 { ATA_M88SX6145, 0, 2, MV61XX, ATA_UDMA6, "88SX6145" },
2425 { 0, 0, 0, 0, 0, 0}};
2426
2427 if (!(ctlr->chip = ata_match_chip(dev, ids)))
2428 return ENXIO;
2429
2430 ata_set_desc(dev);
2431
2432 switch (ctlr->chip->cfg2) {
2433 case MV50XX:
2434 case MV60XX:
2435 ctlr->chipinit = ata_marvell_edma_chipinit;
2436 break;
2437 case MV61XX:
2438 ctlr->chipinit = ata_marvell_pata_chipinit;
2439 break;
2440 }
2441 return 0;
2442 }
2443
2444 static int
2445 ata_marvell_pata_chipinit(device_t dev)
2446 {
2447 struct ata_pci_controller *ctlr = device_get_softc(dev);
2448
2449 if (ata_setup_interrupt(dev))
2450 return ENXIO;
2451
2452 ctlr->allocate = ata_marvell_pata_allocate;
2453 ctlr->setmode = ata_marvell_pata_setmode;
2454 ctlr->channels = ctlr->chip->cfg1;
2455 return 0;
2456 }
2457
2458 static int
2459 ata_marvell_pata_allocate(device_t dev)
2460 {
2461 struct ata_channel *ch = device_get_softc(dev);
2462
2463 /* setup the usual register normal pci style */
2464 if (ata_pci_allocate(dev))
2465 return ENXIO;
2466
2467 /* dont use 32 bit PIO transfers */
2468 ch->flags |= ATA_USE_16BIT;
2469
2470 return 0;
2471 }
2472
2473 static void
2474 ata_marvell_pata_setmode(device_t dev, int mode)
2475 {
2476 device_t gparent = GRANDPARENT(dev);
2477 struct ata_pci_controller *ctlr = device_get_softc(gparent);
2478 struct ata_device *atadev = device_get_softc(dev);
2479
2480 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
2481 mode = ata_check_80pin(dev, mode);
2482 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2483 atadev->mode = mode;
2484 }
2485
2486 static int
2487 ata_marvell_edma_chipinit(device_t dev)
2488 {
2489 struct ata_pci_controller *ctlr = device_get_softc(dev);
2490
2491 if (ata_setup_interrupt(dev))
2492 return ENXIO;
2493
2494 ctlr->r_type1 = SYS_RES_MEMORY;
2495 ctlr->r_rid1 = PCIR_BAR(0);
2496 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
2497 &ctlr->r_rid1, RF_ACTIVE)))
2498 return ENXIO;
2499
2500 /* mask all host controller interrupts */
2501 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000);
2502
2503 /* mask all PCI interrupts */
2504 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000);
2505
2506 ctlr->allocate = ata_marvell_edma_allocate;
2507 ctlr->reset = ata_marvell_edma_reset;
2508 ctlr->dmainit = ata_marvell_edma_dmainit;
2509 ctlr->setmode = ata_sata_setmode;
2510 ctlr->channels = ctlr->chip->cfg1;
2511
2512 /* clear host controller interrupts */
2513 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000);
2514 if (ctlr->chip->cfg1 > 4)
2515 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000);
2516
2517 /* clear PCI interrupts */
2518 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000);
2519
2520 /* unmask PCI interrupts we want */
2521 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff);
2522
2523 /* unmask host controller interrupts we want */
2524 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ |
2525 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25));
2526
2527 /* enable PCI interrupt */
2528 pci_write_config(dev, PCIR_COMMAND,
2529 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
2530 return 0;
2531 }
2532
2533 static int
2534 ata_marvell_edma_allocate(device_t dev)
2535 {
2536 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2537 struct ata_channel *ch = device_get_softc(dev);
2538 u_int64_t work = ch->dma->work_bus;
2539 int i;
2540
2541 /* clear work area */
2542 bzero(ch->dma->work, 1024+256);
2543
2544 /* set legacy ATA resources */
2545 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
2546 ch->r_io[i].res = ctlr->r_res1;
2547 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch);
2548 }
2549 ch->r_io[ATA_CONTROL].res = ctlr->r_res1;
2550 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch);
2551 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1;
2552 ata_default_registers(dev);
2553
2554 /* set SATA resources */
2555 switch (ctlr->chip->cfg2) {
2556 case MV50XX:
2557 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2558 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch);
2559 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2560 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch);
2561 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2562 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch);
2563 break;
2564 case MV60XX:
2565 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2566 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch);
2567 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2568 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch);
2569 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2570 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch);
2571 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1;
2572 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch);
2573 break;
2574 }
2575
2576 ch->flags |= ATA_NO_SLAVE;
2577 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */
2578 ata_generic_hw(dev);
2579 ch->hw.begin_transaction = ata_marvell_edma_begin_transaction;
2580 ch->hw.end_transaction = ata_marvell_edma_end_transaction;
2581 ch->hw.status = ata_marvell_edma_status;
2582
2583 /* disable the EDMA machinery */
2584 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2585 DELAY(100000); /* SOS should poll for disabled */
2586
2587 /* set configuration to non-queued 128b read transfers stop on error */
2588 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13));
2589
2590 /* request queue base high */
2591 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32);
2592
2593 /* request queue in ptr */
2594 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
2595
2596 /* request queue out ptr */
2597 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0);
2598
2599 /* response queue base high */
2600 work += 1024;
2601 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32);
2602
2603 /* response queue in ptr */
2604 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0);
2605
2606 /* response queue out ptr */
2607 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
2608
2609 /* clear SATA error register */
2610 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2611
2612 /* clear any outstanding error interrupts */
2613 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2614
2615 /* unmask all error interrupts */
2616 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
2617
2618 /* enable EDMA machinery */
2619 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2620 return 0;
2621 }
2622
2623 static int
2624 ata_marvell_edma_status(device_t dev)
2625 {
2626 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2627 struct ata_channel *ch = device_get_softc(dev);
2628 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60);
2629 int shift = (ch->unit << 1) + (ch->unit > 3);
2630
2631 if (cause & (1 << shift)) {
2632
2633 /* clear interrupt(s) */
2634 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2635
2636 /* do we have any PHY events ? */
2637 ata_sata_phy_check_events(dev);
2638 }
2639
2640 /* do we have any device action ? */
2641 return (cause & (2 << shift));
2642 }
2643
2644 /* must be called with ATA channel locked and state_mtx held */
2645 static int
2646 ata_marvell_edma_begin_transaction(struct ata_request *request)
2647 {
2648 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2649 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2650 u_int32_t req_in;
2651 u_int8_t *bytep;
2652 u_int16_t *wordp;
2653 u_int32_t *quadp;
2654 int i, tag = 0x07;
2655 int dummy, error, slot;
2656
2657 /* only DMA R/W goes through the EMDA machine */
2658 if (request->u.ata.command != ATA_READ_DMA &&
2659 request->u.ata.command != ATA_WRITE_DMA) {
2660
2661 /* disable the EDMA machinery */
2662 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)
2663 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2664 return ata_begin_transaction(request);
2665 }
2666
2667 /* check for 48 bit access and convert if needed */
2668 ata_modify_if_48bit(request);
2669
2670 /* check sanity, setup SG list and DMA engine */
2671 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
2672 request->flags & ATA_R_READ, ch->dma->sg,
2673 &dummy))) {
2674 device_printf(request->dev, "setting up DMA failed\n");
2675 request->result = error;
2676 return ATA_OP_FINISHED;
2677 }
2678
2679 /* get next free request queue slot */
2680 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch));
2681 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f;
2682 bytep = (u_int8_t *)(ch->dma->work);
2683 bytep += (slot << 5);
2684 wordp = (u_int16_t *)bytep;
2685 quadp = (u_int32_t *)bytep;
2686
2687 /* fill in this request */
2688 quadp[0] = (long)ch->dma->sg_bus & 0xffffffff;
2689 quadp[1] = (u_int64_t)ch->dma->sg_bus >> 32;
2690 wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1);
2691
2692 i = 10;
2693 bytep[i++] = (request->u.ata.count >> 8) & 0xff;
2694 bytep[i++] = 0x10 | ATA_COUNT;
2695 bytep[i++] = request->u.ata.count & 0xff;
2696 bytep[i++] = 0x10 | ATA_COUNT;
2697
2698 bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
2699 bytep[i++] = 0x10 | ATA_SECTOR;
2700 bytep[i++] = request->u.ata.lba & 0xff;
2701 bytep[i++] = 0x10 | ATA_SECTOR;
2702
2703 bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
2704 bytep[i++] = 0x10 | ATA_CYL_LSB;
2705 bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
2706 bytep[i++] = 0x10 | ATA_CYL_LSB;
2707
2708 bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
2709 bytep[i++] = 0x10 | ATA_CYL_MSB;
2710 bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
2711 bytep[i++] = 0x10 | ATA_CYL_MSB;
2712
2713 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf);
2714 bytep[i++] = 0x10 | ATA_DRIVE;
2715
2716 bytep[i++] = request->u.ata.command;
2717 bytep[i++] = 0x90 | ATA_COMMAND;
2718
2719 /* enable EDMA machinery if needed */
2720 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) {
2721 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2722 while (!(ATA_INL(ctlr->r_res1,
2723 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
2724 DELAY(10);
2725 }
2726
2727 /* tell EDMA it has a new request */
2728 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f;
2729 req_in &= 0xfffffc00;
2730 req_in += (slot << 5);
2731 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in);
2732
2733 return ATA_OP_CONTINUES;
2734 }
2735
2736 /* must be called with ATA channel locked and state_mtx held */
2737 static int
2738 ata_marvell_edma_end_transaction(struct ata_request *request)
2739 {
2740 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2741 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2742 int offset = (ch->unit > 3 ? 0x30014 : 0x20014);
2743 u_int32_t icr = ATA_INL(ctlr->r_res1, offset);
2744 int res;
2745
2746 /* EDMA interrupt */
2747 if ((icr & (0x0001 << (ch->unit & 3)))) {
2748 struct ata_marvell_response *response;
2749 u_int32_t rsp_in, rsp_out;
2750 int slot;
2751
2752 /* stop timeout */
2753 callout_stop(&request->callout);
2754
2755 /* get response ptr's */
2756 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch));
2757 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch));
2758 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f;
2759 rsp_out &= 0xffffff00;
2760 rsp_out += (slot << 3);
2761 response = (struct ata_marvell_response *)
2762 (ch->dma->work + 1024 + (slot << 3));
2763
2764 /* record status for this request */
2765 request->status = response->dev_status;
2766 request->error = 0;
2767
2768 /* ack response */
2769 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out);
2770
2771 /* update progress */
2772 if (!(request->status & ATA_S_ERROR) &&
2773 !(request->flags & ATA_R_TIMEOUT))
2774 request->donecount = request->bytecount;
2775
2776 /* unload SG list */
2777 ch->dma->unload(ch->dev);
2778
2779 res = ATA_OP_FINISHED;
2780 }
2781
2782 /* legacy ATA interrupt */
2783 else {
2784 res = ata_end_transaction(request);
2785 }
2786
2787 /* ack interrupt */
2788 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3))));
2789 return res;
2790 }
2791
2792 static void
2793 ata_marvell_edma_reset(device_t dev)
2794 {
2795 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2796 struct ata_channel *ch = device_get_softc(dev);
2797
2798 /* disable the EDMA machinery */
2799 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2800 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
2801 DELAY(10);
2802
2803 /* clear SATA error register */
2804 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2805
2806 /* clear any outstanding error interrupts */
2807 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2808
2809 /* unmask all error interrupts */
2810 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
2811
2812 /* enable channel and test for devices */
2813 if (ata_sata_phy_reset(dev))
2814 ata_generic_reset(dev);
2815
2816 /* enable EDMA machinery */
2817 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2818 }
2819
2820 static void
2821 ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs,
2822 int error)
2823 {
2824 struct ata_dmasetprd_args *args = xsc;
2825 struct ata_marvell_dma_prdentry *prd = args->dmatab;
2826 int i;
2827
2828 if ((args->error = error))
2829 return;
2830
2831 for (i = 0; i < nsegs; i++) {
2832 prd[i].addrlo = htole32(segs[i].ds_addr);
2833 prd[i].count = htole32(segs[i].ds_len);
2834 prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32);
2835 }
2836 prd[i - 1].count |= htole32(ATA_DMA_EOT);
2837 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
2838 args->nsegs = nsegs;
2839 }
2840
2841 static void
2842 ata_marvell_edma_dmainit(device_t dev)
2843 {
2844 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2845 struct ata_channel *ch = device_get_softc(dev);
2846
2847 ata_dmainit(dev);
2848 if (ch->dma) {
2849 /* note start and stop are not used here */
2850 ch->dma->setprd = ata_marvell_edma_dmasetprd;
2851
2852 if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004)
2853 ch->dma->max_address = BUS_SPACE_MAXADDR;
2854 }
2855 }
2856
2857
2858 /*
2859 * National chipset support functions
2860 */
2861 int
2862 ata_national_ident(device_t dev)
2863 {
2864 struct ata_pci_controller *ctlr = device_get_softc(dev);
2865
2866 /* this chip is a clone of the Cyrix chip, bugs and all */
2867 if (pci_get_devid(dev) == ATA_SC1100) {
2868 device_set_desc(dev, "National Geode SC1100 ATA33 controller");
2869 ctlr->chipinit = ata_national_chipinit;
2870 return 0;
2871 }
2872 return ENXIO;
2873 }
2874
2875 static int
2876 ata_national_chipinit(device_t dev)
2877 {
2878 struct ata_pci_controller *ctlr = device_get_softc(dev);
2879
2880 if (ata_setup_interrupt(dev))
2881 return ENXIO;
2882
2883 ctlr->setmode = ata_national_setmode;
2884 return 0;
2885 }
2886
2887 static void
2888 ata_national_setmode(device_t dev, int mode)
2889 {
2890 device_t gparent = GRANDPARENT(dev);
2891 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2892 struct ata_device *atadev = device_get_softc(dev);
2893 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2894 u_int32_t piotiming[] =
2895 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
2896 0x00803020, 0x20102010, 0x00100010,
2897 0x00100010, 0x00100010, 0x00100010 };
2898 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
2899 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
2900 int error;
2901
2902 ch->dma->alignment = 16;
2903 ch->dma->max_iosize = 126 * DEV_BSIZE;
2904
2905 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
2906
2907 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2908
2909 if (bootverbose)
2910 device_printf(dev, "%s setting %s on National chip\n",
2911 (error) ? "failed" : "success", ata_mode2str(mode));
2912 if (!error) {
2913 if (mode >= ATA_UDMA0) {
2914 pci_write_config(gparent, 0x44 + (devno << 3),
2915 udmatiming[mode & ATA_MODE_MASK], 4);
2916 }
2917 else if (mode >= ATA_WDMA0) {
2918 pci_write_config(gparent, 0x44 + (devno << 3),
2919 dmatiming[mode & ATA_MODE_MASK], 4);
2920 }
2921 else {
2922 pci_write_config(gparent, 0x44 + (devno << 3),
2923 pci_read_config(gparent, 0x44 + (devno << 3), 4) |
2924 0x80000000, 4);
2925 }
2926 pci_write_config(gparent, 0x40 + (devno << 3),
2927 piotiming[ata_mode2idx(mode)], 4);
2928 atadev->mode = mode;
2929 }
2930 }
2931
2932
2933 /*
2934 * NetCell chipset support functions
2935 */
2936 int
2937 ata_netcell_ident(device_t dev)
2938 {
2939 struct ata_pci_controller *ctlr = device_get_softc(dev);
2940
2941 if (pci_get_devid(dev) == ATA_NETCELL_SR) {
2942 device_set_desc(dev, "Netcell SyncRAID SR3000/5000 RAID Controller");
2943 ctlr->chipinit = ata_netcell_chipinit;
2944 return 0;
2945 }
2946 return ENXIO;
2947 }
2948
2949 static int
2950 ata_netcell_chipinit(device_t dev)
2951 {
2952 struct ata_pci_controller *ctlr = device_get_softc(dev);
2953
2954 if (ata_generic_chipinit(dev))
2955 return ENXIO;
2956
2957 ctlr->allocate = ata_netcell_allocate;
2958 return 0;
2959 }
2960
2961 static int
2962 ata_netcell_allocate(device_t dev)
2963 {
2964 struct ata_channel *ch = device_get_softc(dev);
2965
2966 /* setup the usual register normal pci style */
2967 if (ata_pci_allocate(dev))
2968 return ENXIO;
2969
2970 /* the NetCell only supports 16 bit PIO transfers */
2971 ch->flags |= ATA_USE_16BIT;
2972
2973 return 0;
2974 }
2975
2976
2977 /*
2978 * nVidia chipset support functions
2979 */
2980 int
2981 ata_nvidia_ident(device_t dev)
2982 {
2983 struct ata_pci_controller *ctlr = device_get_softc(dev);
2984 static struct ata_chip_id ids[] =
2985 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nForce" },
2986 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2" },
2987 { ATA_NFORCE2_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2 Pro" },
2988 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" },
2989 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3" },
2990 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3 Pro" },
2991 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
2992 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
2993 { ATA_NFORCE_MCP04, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP" },
2994 { ATA_NFORCE_MCP04_S1, 0, 0, NV4, ATA_SA150, "nForce MCP" },
2995 { ATA_NFORCE_MCP04_S2, 0, 0, NV4, ATA_SA150, "nForce MCP" },
2996 { ATA_NFORCE_CK804, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce CK804" },
2997 { ATA_NFORCE_CK804_S1, 0, 0, NV4, ATA_SA300, "nForce CK804" },
2998 { ATA_NFORCE_CK804_S2, 0, 0, NV4, ATA_SA300, "nForce CK804" },
2999 { ATA_NFORCE_MCP51, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP51" },
3000 { ATA_NFORCE_MCP51_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
3001 { ATA_NFORCE_MCP51_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
3002 { ATA_NFORCE_MCP55, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP55" },
3003 { ATA_NFORCE_MCP55_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
3004 { ATA_NFORCE_MCP55_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
3005 { ATA_NFORCE_MCP61, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP61" },
3006 { ATA_NFORCE_MCP61_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
3007 { ATA_NFORCE_MCP61_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
3008 { ATA_NFORCE_MCP61_S3, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
3009 { ATA_NFORCE_MCP65, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP65" },
3010 { ATA_NFORCE_MCP67, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP67" },
3011 { ATA_NFORCE_MCP73, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP73" },
3012 { ATA_NFORCE_MCP77, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP77" },
3013 { 0, 0, 0, 0, 0, 0}} ;
3014
3015 if (!(ctlr->chip = ata_match_chip(dev, ids)))
3016 return ENXIO;
3017
3018 ata_set_desc(dev);
3019 ctlr->chipinit = ata_nvidia_chipinit;
3020 return 0;
3021 }
3022
3023 static int
3024 ata_nvidia_chipinit(device_t dev)
3025 {
3026 struct ata_pci_controller *ctlr = device_get_softc(dev);
3027
3028 if (ata_setup_interrupt(dev))
3029 return ENXIO;
3030
3031 if (ctlr->chip->max_dma >= ATA_SA150) {
3032 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1)
3033 ctlr->r_type2 = SYS_RES_IOPORT;
3034 else
3035 ctlr->r_type2 = SYS_RES_MEMORY;
3036 ctlr->r_rid2 = PCIR_BAR(5);
3037 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3038 &ctlr->r_rid2, RF_ACTIVE))) {
3039 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
3040
3041 ctlr->allocate = ata_nvidia_allocate;
3042 ctlr->reset = ata_nvidia_reset;
3043
3044 /* enable control access */
3045 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1);
3046
3047 if (ctlr->chip->cfg2 & NVQ) {
3048 /* clear interrupt status */
3049 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff);
3050
3051 /* enable device and PHY state change interrupts */
3052 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d);
3053
3054 /* disable NCQ support */
3055 ATA_OUTL(ctlr->r_res2, 0x0400,
3056 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9);
3057 }
3058 else {
3059 /* clear interrupt status */
3060 ATA_OUTB(ctlr->r_res2, offset, 0xff);
3061
3062 /* enable device and PHY state change interrupts */
3063 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd);
3064 }
3065
3066 /* enable PCI interrupt */
3067 pci_write_config(dev, PCIR_COMMAND,
3068 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
3069
3070 }
3071 ctlr->setmode = ata_sata_setmode;
3072 }
3073 else {
3074 /* disable prefetch, postwrite */
3075 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
3076 ctlr->setmode = ata_via_family_setmode;
3077 }
3078 return 0;
3079 }
3080
3081 static int
3082 ata_nvidia_allocate(device_t dev)
3083 {
3084 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3085 struct ata_channel *ch = device_get_softc(dev);
3086
3087 /* setup the usual register normal pci style */
3088 if (ata_pci_allocate(dev))
3089 return ENXIO;
3090
3091 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3092 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6);
3093 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3094 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6);
3095 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3096 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6);
3097
3098 ch->hw.status = ata_nvidia_status;
3099 ch->flags |= ATA_NO_SLAVE;
3100
3101 return 0;
3102 }
3103
3104 static int
3105 ata_nvidia_status(device_t dev)
3106 {
3107 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3108 struct ata_channel *ch = device_get_softc(dev);
3109 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
3110 int shift = ch->unit << (ctlr->chip->cfg2 & NVQ ? 4 : 2);
3111 u_int32_t istatus = ATA_INL(ctlr->r_res2, offset);
3112
3113 /* do we have any PHY events ? */
3114 if (istatus & (0x0c << shift))
3115 ata_sata_phy_check_events(dev);
3116
3117 /* clear interrupt(s) */
3118 ATA_OUTB(ctlr->r_res2, offset,
3119 (0x0f << shift) | (ctlr->chip->cfg2 & NVQ ? 0x00f000f0 : 0));
3120
3121 /* do we have any device action ? */
3122 return (istatus & (0x01 << shift));
3123 }
3124
3125 static void
3126 ata_nvidia_reset(device_t dev)
3127 {
3128 if (ata_sata_phy_reset(dev))
3129 ata_generic_reset(dev);
3130 }
3131
3132
3133 /*
3134 * Promise chipset support functions
3135 */
3136 #define ATA_PDC_APKT_OFFSET 0x00000010
3137 #define ATA_PDC_HPKT_OFFSET 0x00000040
3138 #define ATA_PDC_ASG_OFFSET 0x00000080
3139 #define ATA_PDC_LSG_OFFSET 0x000000c0
3140 #define ATA_PDC_HSG_OFFSET 0x00000100
3141 #define ATA_PDC_CHN_OFFSET 0x00000400
3142 #define ATA_PDC_BUF_BASE 0x00400000
3143 #define ATA_PDC_BUF_OFFSET 0x00100000
3144 #define ATA_PDC_MAX_HPKT 8
3145 #define ATA_PDC_WRITE_REG 0x00
3146 #define ATA_PDC_WRITE_CTL 0x0e
3147 #define ATA_PDC_WRITE_END 0x08
3148 #define ATA_PDC_WAIT_NBUSY 0x10
3149 #define ATA_PDC_WAIT_READY 0x18
3150 #define ATA_PDC_1B 0x20
3151 #define ATA_PDC_2B 0x40
3152
3153 struct host_packet {
3154 u_int32_t addr;
3155 TAILQ_ENTRY(host_packet) chain;
3156 };
3157
3158 struct ata_promise_sx4 {
3159 struct mtx mtx;
3160 TAILQ_HEAD(, host_packet) queue;
3161 int busy;
3162 };
3163
3164 int
3165 ata_promise_ident(device_t dev)
3166 {
3167 struct ata_pci_controller *ctlr = device_get_softc(dev);
3168 struct ata_chip_id *idx;
3169 static struct ata_chip_id ids[] =
3170 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "PDC20246" },
3171 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20262" },
3172 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20263" },
3173 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20265" },
3174 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20267" },
3175 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20268" },
3176 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "PDC20269" },
3177 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20270" },
3178 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "PDC20271" },
3179 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "PDC20275" },
3180 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "PDC20276" },
3181 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "PDC20277" },
3182 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "PDC20318" },
3183 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "PDC20319" },
3184 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20371" },
3185 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20375" },
3186 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20376" },
3187 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20377" },
3188 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20378" },
3189 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20379" },
3190 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" },
3191 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" },
3192 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" },
3193 { ATA_PDC20771, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" },
3194 { ATA_PDC40775, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" },
3195 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20617" },
3196 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20618" },
3197 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20619" },
3198 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20620" },
3199 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "PDC20621" },
3200 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "PDC20622" },
3201 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40518" },
3202 { ATA_PDC40519, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40519" },
3203 { ATA_PDC40718, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40718" },
3204 { ATA_PDC40719, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40719" },
3205 { ATA_PDC40779, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40779" },
3206 { 0, 0, 0, 0, 0, 0}};
3207 char buffer[64];
3208 uintptr_t devid = 0;
3209
3210 if (!(idx = ata_match_chip(dev, ids)))
3211 return ENXIO;
3212
3213 /* if we are on a SuperTrak SX6000 dont attach */
3214 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
3215 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
3216 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
3217 devid == ATA_I960RM)
3218 return ENXIO;
3219
3220 strcpy(buffer, "Promise ");
3221 strcat(buffer, idx->text);
3222
3223 /* if we are on a FastTrak TX4, adjust the interrupt resource */
3224 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
3225 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
3226 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
3227 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) {
3228 static long start = 0, end = 0;
3229
3230 if (pci_get_slot(dev) == 1) {
3231 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
3232 strcat(buffer, " (channel 0+1)");
3233 }
3234 else if (pci_get_slot(dev) == 2 && start && end) {
3235 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
3236 strcat(buffer, " (channel 2+3)");
3237 }
3238 else {
3239 start = end = 0;
3240 }
3241 }
3242 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
3243 device_set_desc_copy(dev, buffer);
3244 ctlr->chip = idx;
3245 ctlr->chipinit = ata_promise_chipinit;
3246 return 0;
3247 }
3248
3249 static int
3250 ata_promise_chipinit(device_t dev)
3251 {
3252 struct ata_pci_controller *ctlr = device_get_softc(dev);
3253 int fake_reg, stat_reg;
3254
3255 if (ata_setup_interrupt(dev))
3256 return ENXIO;
3257
3258 switch (ctlr->chip->cfg1) {
3259 case PRNEW:
3260 /* setup clocks */
3261 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a);
3262
3263 ctlr->dmainit = ata_promise_dmainit;
3264 /* FALLTHROUGH */
3265
3266 case PROLD:
3267 /* enable burst mode */
3268 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01);
3269 ctlr->allocate = ata_promise_allocate;
3270 ctlr->setmode = ata_promise_setmode;
3271 return 0;
3272
3273 case PRTX:
3274 ctlr->allocate = ata_promise_tx2_allocate;
3275 ctlr->setmode = ata_promise_setmode;
3276 return 0;
3277
3278 case PRMIO:
3279 ctlr->r_type1 = SYS_RES_MEMORY;
3280 ctlr->r_rid1 = PCIR_BAR(4);
3281 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
3282 &ctlr->r_rid1, RF_ACTIVE)))
3283 goto failnfree;
3284
3285 ctlr->r_type2 = SYS_RES_MEMORY;
3286 ctlr->r_rid2 = PCIR_BAR(3);
3287 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3288 &ctlr->r_rid2, RF_ACTIVE)))
3289 goto failnfree;
3290
3291 if (ctlr->chip->cfg2 == PRSX4X) {
3292 struct ata_promise_sx4 *hpkt;
3293 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080);
3294
3295 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3296 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
3297 ata_promise_sx4_intr, ctlr, &ctlr->handle)) {
3298 device_printf(dev, "unable to setup interrupt\n");
3299 goto failnfree;
3300 }
3301
3302 /* print info about cache memory */
3303 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n",
3304 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4,
3305 ((dimm >> 24) & 0xff),
3306 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ?
3307 " ECC enabled" : "" );
3308
3309 /* adjust cache memory parameters */
3310 ATA_OUTL(ctlr->r_res2, 0x000c000c,
3311 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000));
3312
3313 /* setup host packet controls */
3314 hpkt = malloc(sizeof(struct ata_promise_sx4),
3315 M_TEMP, M_NOWAIT | M_ZERO);
3316 mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF);
3317 TAILQ_INIT(&hpkt->queue);
3318 hpkt->busy = 0;
3319 device_set_ivars(dev, hpkt);
3320 ctlr->allocate = ata_promise_mio_allocate;
3321 ctlr->reset = ata_promise_mio_reset;
3322 ctlr->dmainit = ata_promise_mio_dmainit;
3323 ctlr->setmode = ata_promise_setmode;
3324 ctlr->channels = 4;
3325 return 0;
3326 }
3327
3328 /* mio type controllers need an interrupt intercept */
3329 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3330 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
3331 ata_promise_mio_intr, ctlr, &ctlr->handle)) {
3332 device_printf(dev, "unable to setup interrupt\n");
3333 goto failnfree;
3334 }
3335
3336 switch (ctlr->chip->cfg2) {
3337 case PRPATA:
3338 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) +
3339 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2;
3340 goto sata150;
3341 case PRCMBO:
3342 ctlr->channels = 3;
3343 goto sata150;
3344 case PRSATA:
3345 ctlr->channels = 4;
3346 sata150:
3347 fake_reg = 0x60;
3348 stat_reg = 0x6c;
3349 break;
3350
3351 case PRCMBO2:
3352 ctlr->channels = 3;
3353 goto sataii;
3354 case PRSATA2:
3355 default:
3356 ctlr->channels = 4;
3357 sataii:
3358 fake_reg = 0x54;
3359 stat_reg = 0x60;
3360 break;
3361 }
3362
3363 /* prime fake interrupt register */
3364 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3365
3366 /* clear SATA status and unmask interrupts */
3367 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff);
3368
3369 /* enable "long burst lenght" on gen2 chips */
3370 if ((ctlr->chip->cfg2 == PRSATA2) || (ctlr->chip->cfg2 == PRCMBO2))
3371 ATA_OUTL(ctlr->r_res2, 0x44, ATA_INL(ctlr->r_res2, 0x44) | 0x2000);
3372
3373 ctlr->allocate = ata_promise_mio_allocate;
3374 ctlr->reset = ata_promise_mio_reset;
3375 ctlr->dmainit = ata_promise_mio_dmainit;
3376 ctlr->setmode = ata_promise_mio_setmode;
3377
3378 return 0;
3379 }
3380
3381 failnfree:
3382 if (ctlr->r_res2)
3383 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
3384 if (ctlr->r_res1)
3385 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1);
3386 return ENXIO;
3387 }
3388
3389 static int
3390 ata_promise_allocate(device_t dev)
3391 {
3392 struct ata_channel *ch = device_get_softc(dev);
3393
3394 if (ata_pci_allocate(dev))
3395 return ENXIO;
3396
3397 ch->hw.status = ata_promise_status;
3398 return 0;
3399 }
3400
3401 static int
3402 ata_promise_status(device_t dev)
3403 {
3404 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3405 struct ata_channel *ch = device_get_softc(dev);
3406
3407 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) {
3408 return ata_pci_status(dev);
3409 }
3410 return 0;
3411 }
3412
3413 static int
3414 ata_promise_dmastart(device_t dev)
3415 {
3416 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3417 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3418 struct ata_device *atadev = device_get_softc(dev);
3419
3420 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3421 ATA_OUTB(ctlr->r_res1, 0x11,
3422 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02));
3423 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20,
3424 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) |
3425 (ch->dma->cur_iosize >> 1));
3426 }
3427 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) |
3428 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
3429 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus);
3430 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3431 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) |
3432 ATA_BMCMD_START_STOP);
3433 ch->flags |= ATA_DMA_ACTIVE;
3434 return 0;
3435 }
3436
3437 static int
3438 ata_promise_dmastop(device_t dev)
3439 {
3440 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3441 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3442 struct ata_device *atadev = device_get_softc(dev);
3443 int error;
3444
3445 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3446 ATA_OUTB(ctlr->r_res1, 0x11,
3447 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02));
3448 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0);
3449 }
3450 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT);
3451 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3452 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3453 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3454 ch->flags &= ~ATA_DMA_ACTIVE;
3455 return error;
3456 }
3457
3458 static void
3459 ata_promise_dmareset(device_t dev)
3460 {
3461 struct ata_channel *ch = device_get_softc(dev);
3462
3463 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3464 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3465 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3466 ch->flags &= ~ATA_DMA_ACTIVE;
3467 }
3468
3469 static void
3470 ata_promise_dmainit(device_t dev)
3471 {
3472 struct ata_channel *ch = device_get_softc(dev);
3473
3474 ata_dmainit(dev);
3475 if (ch->dma) {
3476 ch->dma->start = ata_promise_dmastart;
3477 ch->dma->stop = ata_promise_dmastop;
3478 ch->dma->reset = ata_promise_dmareset;
3479 }
3480 }
3481
3482 static void
3483 ata_promise_setmode(device_t dev, int mode)
3484 {
3485 device_t gparent = GRANDPARENT(dev);
3486 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3487 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3488 struct ata_device *atadev = device_get_softc(dev);
3489 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
3490 int error;
3491 u_int32_t timings[][2] = {
3492 /* PROLD PRNEW mode */
3493 { 0x004ff329, 0x004fff2f }, /* PIO 0 */
3494 { 0x004fec25, 0x004ff82a }, /* PIO 1 */
3495 { 0x004fe823, 0x004ff026 }, /* PIO 2 */
3496 { 0x004fe622, 0x004fec24 }, /* PIO 3 */
3497 { 0x004fe421, 0x004fe822 }, /* PIO 4 */
3498 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */
3499 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */
3500 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */
3501 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */
3502 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */
3503 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */
3504 { 0, 0x00424ef6 }, /* UDMA 3 */
3505 { 0, 0x004127f3 }, /* UDMA 4 */
3506 { 0, 0x004127f3 } /* UDMA 5 */
3507 };
3508
3509 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
3510
3511 switch (ctlr->chip->cfg1) {
3512 case PROLD:
3513 case PRNEW:
3514 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) &
3515 (ch->unit ? 1 << 11 : 1 << 10))) {
3516 ata_print_cable(dev, "controller");
3517 mode = ATA_UDMA2;
3518 }
3519 if (ata_atapi(dev) && mode > ATA_PIO_MAX)
3520 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
3521 break;
3522
3523 case PRTX:
3524 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3525 if (mode > ATA_UDMA2 &&
3526 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) {
3527 ata_print_cable(dev, "controller");
3528 mode = ATA_UDMA2;
3529 }
3530 break;
3531
3532 case PRMIO:
3533 if (mode > ATA_UDMA2 &&
3534 (ATA_INL(ctlr->r_res2,
3535 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) +
3536 (ch->unit << 7)) & 0x01000000)) {
3537 ata_print_cable(dev, "controller");
3538 mode = ATA_UDMA2;
3539 }
3540 break;
3541 }
3542
3543 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3544
3545 if (bootverbose)
3546 device_printf(dev, "%ssetting %s on %s chip\n",
3547 (error) ? "FAILURE " : "",
3548 ata_mode2str(mode), ctlr->chip->text);
3549 if (!error) {
3550 if (ctlr->chip->cfg1 < PRTX)
3551 pci_write_config(gparent, 0x60 + (devno << 2),
3552 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
3553 atadev->mode = mode;
3554 }
3555 return;
3556 }
3557
3558 static int
3559 ata_promise_tx2_allocate(device_t dev)
3560 {
3561 struct ata_channel *ch = device_get_softc(dev);
3562
3563 if (ata_pci_allocate(dev))
3564 return ENXIO;
3565
3566 ch->hw.status = ata_promise_tx2_status;
3567 return 0;
3568 }
3569
3570 static int
3571 ata_promise_tx2_status(device_t dev)
3572 {
3573 struct ata_channel *ch = device_get_softc(dev);
3574
3575 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3576 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
3577 return ata_pci_status(dev);
3578 }
3579 return 0;
3580 }
3581
3582 static int
3583 ata_promise_mio_allocate(device_t dev)
3584 {
3585 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3586 struct ata_channel *ch = device_get_softc(dev);
3587 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0;
3588 int i;
3589
3590 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
3591 ch->r_io[i].res = ctlr->r_res2;
3592 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7);
3593 }
3594 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
3595 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7);
3596 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
3597 ata_default_registers(dev);
3598 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) ||
3599 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2)) {
3600 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3601 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8);
3602 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3603 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8);
3604 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3605 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8);
3606 ch->flags |= ATA_NO_SLAVE;
3607 }
3608 ch->flags |= ATA_USE_16BIT;
3609
3610 ata_generic_hw(dev);
3611 if (ctlr->chip->cfg2 & PRSX4X) {
3612 ch->hw.command = ata_promise_sx4_command;
3613 }
3614 else {
3615 ch->hw.command = ata_promise_mio_command;
3616 ch->hw.status = ata_promise_mio_status;
3617 }
3618 return 0;
3619 }
3620
3621 static void
3622 ata_promise_mio_intr(void *data)
3623 {
3624 struct ata_pci_controller *ctlr = data;
3625 struct ata_channel *ch;
3626 u_int32_t vector;
3627 int unit, fake_reg;
3628
3629 switch (ctlr->chip->cfg2) {
3630 case PRPATA:
3631 case PRCMBO:
3632 case PRSATA:
3633 fake_reg = 0x60;
3634 break;
3635 case PRCMBO2:
3636 case PRSATA2:
3637 default:
3638 fake_reg = 0x54;
3639 break;
3640 }
3641
3642 /*
3643 * since reading interrupt status register on early "mio" chips
3644 * clears the status bits we cannot read it for each channel later on
3645 * in the generic interrupt routine.
3646 * store the bits in an unused register in the chip so we can read
3647 * it from there safely to get around this "feature".
3648 */
3649 vector = ATA_INL(ctlr->r_res2, 0x040);
3650 ATA_OUTL(ctlr->r_res2, 0x040, vector);
3651 ATA_OUTL(ctlr->r_res2, fake_reg, vector);
3652
3653 for (unit = 0; unit < ctlr->channels; unit++) {
3654 if ((ch = ctlr->interrupt[unit].argument))
3655 ctlr->interrupt[unit].function(ch);
3656 }
3657
3658 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3659 }
3660
3661 static int
3662 ata_promise_mio_status(device_t dev)
3663 {
3664 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3665 struct ata_channel *ch = device_get_softc(dev);
3666 struct ata_connect_task *tp;
3667 u_int32_t fake_reg, stat_reg, vector, status;
3668
3669 switch (ctlr->chip->cfg2) {
3670 case PRPATA:
3671 case PRCMBO:
3672 case PRSATA:
3673 fake_reg = 0x60;
3674 stat_reg = 0x6c;
3675 break;
3676 case PRCMBO2:
3677 case PRSATA2:
3678 default:
3679 fake_reg = 0x54;
3680 stat_reg = 0x60;
3681 break;
3682 }
3683
3684 /* read and acknowledge interrupt */
3685 vector = ATA_INL(ctlr->r_res2, fake_reg);
3686
3687 /* read and clear interface status */
3688 status = ATA_INL(ctlr->r_res2, stat_reg);
3689 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit));
3690
3691 /* check for and handle disconnect events */
3692 if ((status & (0x00000001 << ch->unit)) &&
3693 (tp = (struct ata_connect_task *)
3694 malloc(sizeof(struct ata_connect_task),
3695 M_ATA, M_NOWAIT | M_ZERO))) {
3696
3697 if (bootverbose)
3698 device_printf(ch->dev, "DISCONNECT requested\n");
3699 tp->action = ATA_C_DETACH;
3700 tp->dev = ch->dev;
3701 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3702 taskqueue_enqueue(taskqueue_thread, &tp->task);
3703 }
3704
3705 /* check for and handle connect events */
3706 if ((status & (0x00000010 << ch->unit)) &&
3707 (tp = (struct ata_connect_task *)
3708 malloc(sizeof(struct ata_connect_task),
3709 M_ATA, M_NOWAIT | M_ZERO))) {
3710
3711 if (bootverbose)
3712 device_printf(ch->dev, "CONNECT requested\n");
3713 tp->action = ATA_C_ATTACH;
3714 tp->dev = ch->dev;
3715 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3716 taskqueue_enqueue(taskqueue_thread, &tp->task);
3717 }
3718
3719 /* do we have any device action ? */
3720 return (vector & (1 << (ch->unit + 1)));
3721 }
3722
3723 static int
3724 ata_promise_mio_command(struct ata_request *request)
3725 {
3726 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
3727 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
3728 u_int32_t *wordp = (u_int32_t *)ch->dma->work;
3729
3730 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001);
3731
3732 /* XXX SOS add ATAPI commands support later */
3733 switch (request->u.ata.command) {
3734 default:
3735 return ata_generic_command(request);
3736
3737 case ATA_READ_DMA:
3738 case ATA_READ_DMA48:
3739 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24));
3740 break;
3741
3742 case ATA_WRITE_DMA:
3743 case ATA_WRITE_DMA48:
3744 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24));
3745 break;
3746 }
3747 wordp[1] = htole32(ch->dma->sg_bus);
3748 wordp[2] = 0;
3749 ata_promise_apkt((u_int8_t*)wordp, request);
3750
3751 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma->work_bus);
3752 return 0;
3753 }
3754
3755 static void
3756 ata_promise_mio_reset(device_t dev)
3757 {
3758 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3759 struct ata_channel *ch = device_get_softc(dev);
3760 struct ata_promise_sx4 *hpktp;
3761
3762 switch (ctlr->chip->cfg2) {
3763 case PRSX4X:
3764
3765 /* softreset channel ATA module */
3766 hpktp = device_get_ivars(ctlr->dev);
3767 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1);
3768 ata_udelay(1000);
3769 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7),
3770 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) &
3771 ~0x00003f9f) | (ch->unit + 1));
3772
3773 /* softreset HOST module */ /* XXX SOS what about other outstandings */
3774 mtx_lock(&hpktp->mtx);
3775 ATA_OUTL(ctlr->r_res2, 0xc012c,
3776 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11));
3777 DELAY(10);
3778 ATA_OUTL(ctlr->r_res2, 0xc012c,
3779 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f));
3780 hpktp->busy = 0;
3781 mtx_unlock(&hpktp->mtx);
3782 ata_generic_reset(dev);
3783 break;
3784
3785 case PRPATA:
3786 case PRCMBO:
3787 case PRSATA:
3788 if ((ctlr->chip->cfg2 == PRSATA) ||
3789 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
3790
3791 /* mask plug/unplug intr */
3792 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit));
3793 }
3794
3795 /* softreset channels ATA module */
3796 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
3797 ata_udelay(10000);
3798 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
3799 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
3800 ~0x00003f9f) | (ch->unit + 1));
3801
3802 if ((ctlr->chip->cfg2 == PRSATA) ||
3803 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
3804
3805 if (ata_sata_phy_reset(dev))
3806 ata_generic_reset(dev);
3807
3808 /* reset and enable plug/unplug intr */
3809 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit));
3810 }
3811 else
3812 ata_generic_reset(dev);
3813 break;
3814
3815 case PRCMBO2:
3816 case PRSATA2:
3817 if ((ctlr->chip->cfg2 == PRSATA2) ||
3818 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
3819 /* set portmultiplier port */
3820 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f);
3821
3822 /* mask plug/unplug intr */
3823 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit));
3824 }
3825
3826 /* softreset channels ATA module */
3827 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
3828 ata_udelay(10000);
3829 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
3830 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
3831 ~0x00003f9f) | (ch->unit + 1));
3832
3833 if ((ctlr->chip->cfg2 == PRSATA2) ||
3834 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
3835
3836 /* set PHY mode to "improved" */
3837 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8),
3838 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) &
3839 ~0x00000003) | 0x00000001);
3840
3841 if (ata_sata_phy_reset(dev))
3842 ata_generic_reset(dev);
3843
3844 /* reset and enable plug/unplug intr */
3845 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit));
3846
3847 /* set portmultiplier port */
3848 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00);
3849 }
3850 else
3851 ata_generic_reset(dev);
3852 break;
3853
3854 }
3855 }
3856
3857 static void
3858 ata_promise_mio_dmainit(device_t dev)
3859 {
3860 struct ata_channel *ch = device_get_softc(dev);
3861
3862 /* note start and stop are not used here */
3863 ata_dmainit(dev);
3864 if (ch->dma)
3865 ch->dma->setprd = ata_promise_mio_setprd;
3866 }
3867
3868
3869 #define MAXLASTSGSIZE (32 * sizeof(u_int32_t))
3870 static void
3871 ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
3872 {
3873 struct ata_dmasetprd_args *args = xsc;
3874 struct ata_dma_prdentry *prd = args->dmatab;
3875 int i;
3876
3877 if ((args->error = error))
3878 return;
3879
3880 for (i = 0; i < nsegs; i++) {
3881 prd[i].addr = htole32(segs[i].ds_addr);
3882 prd[i].count = htole32(segs[i].ds_len);
3883 }
3884 if (segs[i - 1].ds_len > MAXLASTSGSIZE) {
3885 //printf("split last SG element of %u\n", segs[i - 1].ds_len);
3886 prd[i - 1].count = htole32(segs[i - 1].ds_len - MAXLASTSGSIZE);
3887 prd[i].count = htole32(MAXLASTSGSIZE);
3888 prd[i].addr = htole32(segs[i - 1].ds_addr +
3889 (segs[i - 1].ds_len - MAXLASTSGSIZE));
3890 nsegs++;
3891 i++;
3892 }
3893 prd[i - 1].count |= htole32(ATA_DMA_EOT);
3894 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
3895 args->nsegs = nsegs;
3896 }
3897
3898 static void
3899 ata_promise_mio_setmode(device_t dev, int mode)
3900 {
3901 device_t gparent = GRANDPARENT(dev);
3902 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3903 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3904
3905 if ( (ctlr->chip->cfg2 == PRSATA) ||
3906 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2)) ||
3907 (ctlr->chip->cfg2 == PRSATA2) ||
3908 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2)))
3909 ata_sata_setmode(dev, mode);
3910 else
3911 ata_promise_setmode(dev, mode);
3912 }
3913
3914 static void
3915 ata_promise_sx4_intr(void *data)
3916 {
3917 struct ata_pci_controller *ctlr = data;
3918 struct ata_channel *ch;
3919 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480);
3920 int unit;
3921
3922 for (unit = 0; unit < ctlr->channels; unit++) {
3923 if (vector & (1 << (unit + 1)))
3924 if ((ch = ctlr->interrupt[unit].argument))
3925 ctlr->interrupt[unit].function(ch);
3926 if (vector & (1 << (unit + 5)))
3927 if ((ch = ctlr->interrupt[unit].argument))
3928 ata_promise_queue_hpkt(ctlr,
3929 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
3930 ATA_PDC_HPKT_OFFSET));
3931 if (vector & (1 << (unit + 9))) {
3932 ata_promise_next_hpkt(ctlr);
3933 if ((ch = ctlr->interrupt[unit].argument))
3934 ctlr->interrupt[unit].function(ch);
3935 }
3936 if (vector & (1 << (unit + 13))) {
3937 ata_promise_next_hpkt(ctlr);
3938 if ((ch = ctlr->interrupt[unit].argument))
3939 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
3940 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
3941 ATA_PDC_APKT_OFFSET));
3942 }
3943 }
3944 }
3945
3946 static int
3947 ata_promise_sx4_command(struct ata_request *request)
3948 {
3949 device_t gparent = GRANDPARENT(request->dev);
3950 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3951 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
3952 struct ata_dma_prdentry *prd = ch->dma->sg;
3953 caddr_t window = rman_get_virtual(ctlr->r_res1);
3954 u_int32_t *wordp;
3955 int i, idx, length = 0;
3956
3957 /* XXX SOS add ATAPI commands support later */
3958 switch (request->u.ata.command) {
3959
3960 default:
3961 return -1;
3962
3963 case ATA_ATA_IDENTIFY:
3964 case ATA_READ:
3965 case ATA_READ48:
3966 case ATA_READ_MUL:
3967 case ATA_READ_MUL48:
3968 case ATA_WRITE:
3969 case ATA_WRITE48:
3970 case ATA_WRITE_MUL:
3971 case ATA_WRITE_MUL48:
3972 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
3973 return ata_generic_command(request);
3974
3975 case ATA_SETFEATURES:
3976 case ATA_FLUSHCACHE:
3977 case ATA_FLUSHCACHE48:
3978 case ATA_SLEEP:
3979 case ATA_SET_MULTI:
3980 wordp = (u_int32_t *)
3981 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
3982 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24));
3983 wordp[1] = 0;
3984 wordp[2] = 0;
3985 ata_promise_apkt((u_int8_t *)wordp, request);
3986 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
3987 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
3988 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
3989 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET));
3990 return 0;
3991
3992 case ATA_READ_DMA:
3993 case ATA_READ_DMA48:
3994 case ATA_WRITE_DMA:
3995 case ATA_WRITE_DMA48:
3996 wordp = (u_int32_t *)
3997 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET);
3998 i = idx = 0;
3999 do {
4000 wordp[idx++] = prd[i].addr;
4001 wordp[idx++] = prd[i].count;
4002 length += (prd[i].count & ~ATA_DMA_EOT);
4003 } while (!(prd[i++].count & ATA_DMA_EOT));
4004
4005 wordp = (u_int32_t *)
4006 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET);
4007 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
4008 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
4009
4010 wordp = (u_int32_t *)
4011 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET);
4012 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
4013 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
4014
4015 wordp = (u_int32_t *)
4016 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET);
4017 if (request->flags & ATA_R_READ)
4018 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24));
4019 if (request->flags & ATA_R_WRITE)
4020 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24));
4021 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET);
4022 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET);
4023 wordp[3] = 0;
4024
4025 wordp = (u_int32_t *)
4026 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
4027 if (request->flags & ATA_R_READ)
4028 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24));
4029 if (request->flags & ATA_R_WRITE)
4030 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24));
4031 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET);
4032 wordp[2] = 0;
4033 ata_promise_apkt((u_int8_t *)wordp, request);
4034 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
4035
4036 if (request->flags & ATA_R_READ) {
4037 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001);
4038 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001);
4039 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4040 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET));
4041 }
4042 if (request->flags & ATA_R_WRITE) {
4043 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001);
4044 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001);
4045 ata_promise_queue_hpkt(ctlr,
4046 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET));
4047 }
4048 return 0;
4049 }
4050 }
4051
4052 static int
4053 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request)
4054 {
4055 struct ata_device *atadev = device_get_softc(request->dev);
4056 int i = 12;
4057
4058 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE;
4059 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit;
4060 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL;
4061 bytep[i++] = ATA_A_4BIT;
4062
4063 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
4064 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE;
4065 bytep[i++] = request->u.ata.feature >> 8;
4066 bytep[i++] = request->u.ata.feature;
4067 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT;
4068 bytep[i++] = request->u.ata.count >> 8;
4069 bytep[i++] = request->u.ata.count;
4070 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR;
4071 bytep[i++] = request->u.ata.lba >> 24;
4072 bytep[i++] = request->u.ata.lba;
4073 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
4074 bytep[i++] = request->u.ata.lba >> 32;
4075 bytep[i++] = request->u.ata.lba >> 8;
4076 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
4077 bytep[i++] = request->u.ata.lba >> 40;
4078 bytep[i++] = request->u.ata.lba >> 16;
4079 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
4080 bytep[i++] = ATA_D_LBA | atadev->unit;
4081 }
4082 else {
4083 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE;
4084 bytep[i++] = request->u.ata.feature;
4085 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT;
4086 bytep[i++] = request->u.ata.count;
4087 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR;
4088 bytep[i++] = request->u.ata.lba;
4089 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
4090 bytep[i++] = request->u.ata.lba >> 8;
4091 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
4092 bytep[i++] = request->u.ata.lba >> 16;
4093 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
4094 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) |
4095 ATA_D_IBM | atadev->unit | ((request->u.ata.lba >> 24)&0xf);
4096 }
4097 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND;
4098 bytep[i++] = request->u.ata.command;
4099 return i;
4100 }
4101
4102 static void
4103 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt)
4104 {
4105 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
4106
4107 mtx_lock(&hpktp->mtx);
4108 if (hpktp->busy) {
4109 struct host_packet *hp =
4110 malloc(sizeof(struct host_packet), M_TEMP, M_NOWAIT | M_ZERO);
4111 hp->addr = hpkt;
4112 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain);
4113 }
4114 else {
4115 hpktp->busy = 1;
4116 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt);
4117 }
4118 mtx_unlock(&hpktp->mtx);
4119 }
4120
4121 static void
4122 ata_promise_next_hpkt(struct ata_pci_controller *ctlr)
4123 {
4124 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
4125 struct host_packet *hp;
4126
4127 mtx_lock(&hpktp->mtx);
4128 if ((hp = TAILQ_FIRST(&hpktp->queue))) {
4129 TAILQ_REMOVE(&hpktp->queue, hp, chain);
4130 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr);
4131 free(hp, M_TEMP);
4132 }
4133 else
4134 hpktp->busy = 0;
4135 mtx_unlock(&hpktp->mtx);
4136 }
4137
4138
4139 /*
4140 * ServerWorks chipset support functions
4141 */
4142 int
4143 ata_serverworks_ident(device_t dev)
4144 {
4145 struct ata_pci_controller *ctlr = device_get_softc(dev);
4146 static struct ata_chip_id ids[] =
4147 {{ ATA_ROSB4, 0x00, SWKS33, 0, ATA_UDMA2, "ROSB4" },
4148 { ATA_CSB5, 0x92, SWKS100, 0, ATA_UDMA5, "CSB5" },
4149 { ATA_CSB5, 0x00, SWKS66, 0, ATA_UDMA4, "CSB5" },
4150 { ATA_CSB6, 0x00, SWKS100, 0, ATA_UDMA5, "CSB6" },
4151 { ATA_CSB6_1, 0x00, SWKS66, 0, ATA_UDMA4, "CSB6" },
4152 { ATA_HT1000, 0x00, SWKS100, 0, ATA_UDMA5, "HT1000" },
4153 { ATA_HT1000_S1, 0x00, SWKS100, 4, ATA_SA150, "HT1000" },
4154 { ATA_HT1000_S2, 0x00, SWKSMIO, 4, ATA_SA150, "HT1000" },
4155 { ATA_K2, 0x00, SWKSMIO, 4, ATA_SA150, "K2" },
4156 { ATA_FRODO4, 0x00, SWKSMIO, 4, ATA_SA150, "Frodo4" },
4157 { ATA_FRODO8, 0x00, SWKSMIO, 8, ATA_SA150, "Frodo8" },
4158 { 0, 0, 0, 0, 0, 0}};
4159
4160 if (!(ctlr->chip = ata_match_chip(dev, ids)))
4161 return ENXIO;
4162
4163 ata_set_desc(dev);
4164 ctlr->chipinit = ata_serverworks_chipinit;
4165 return 0;
4166 }
4167
4168 static int
4169 ata_serverworks_chipinit(device_t dev)
4170 {
4171 struct ata_pci_controller *ctlr = device_get_softc(dev);
4172
4173 if (ata_setup_interrupt(dev))
4174 return ENXIO;
4175
4176 if (ctlr->chip->cfg1 == SWKSMIO) {
4177 ctlr->r_type2 = SYS_RES_MEMORY;
4178 ctlr->r_rid2 = PCIR_BAR(5);
4179 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4180 &ctlr->r_rid2, RF_ACTIVE)))
4181 return ENXIO;
4182
4183 ctlr->channels = ctlr->chip->cfg2;
4184 ctlr->allocate = ata_serverworks_allocate;
4185 ctlr->setmode = ata_sata_setmode;
4186 return 0;
4187 }
4188 else if (ctlr->chip->cfg1 == SWKS33) {
4189 device_t *children;
4190 int nchildren, i;
4191
4192 /* locate the ISA part in the southbridge and enable UDMA33 */
4193 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
4194 for (i = 0; i < nchildren; i++) {
4195 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
4196 pci_write_config(children[i], 0x64,
4197 (pci_read_config(children[i], 0x64, 4) &
4198 ~0x00002000) | 0x00004000, 4);
4199 break;
4200 }
4201 }
4202 free(children, M_TEMP);
4203 }
4204 }
4205 else {
4206 pci_write_config(dev, 0x5a,
4207 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
4208 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1);
4209 }
4210 ctlr->setmode = ata_serverworks_setmode;
4211 return 0;
4212 }
4213
4214 static int
4215 ata_serverworks_allocate(device_t dev)
4216 {
4217 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4218 struct ata_channel *ch = device_get_softc(dev);
4219 int ch_offset;
4220 int i;
4221
4222 ch_offset = ch->unit * 0x100;
4223
4224 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
4225 ch->r_io[i].res = ctlr->r_res2;
4226
4227 /* setup ATA registers */
4228 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
4229 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04;
4230 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
4231 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
4232 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
4233 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
4234 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
4235 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c;
4236 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20;
4237 ata_default_registers(dev);
4238
4239 /* setup DMA registers */
4240 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30;
4241 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32;
4242 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34;
4243
4244 /* setup SATA registers */
4245 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40;
4246 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44;
4247 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48;
4248
4249 ch->flags |= ATA_NO_SLAVE;
4250 ata_pci_hw(dev);
4251 return 0;
4252 }
4253
4254 static void
4255 ata_serverworks_setmode(device_t dev, int mode)
4256 {
4257 device_t gparent = GRANDPARENT(dev);
4258 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4259 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4260 struct ata_device *atadev = device_get_softc(dev);
4261 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4262 int offset = (devno ^ 0x01) << 3;
4263 int error;
4264 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
4265 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
4266 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
4267
4268 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4269
4270 mode = ata_check_80pin(dev, mode);
4271
4272 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4273
4274 if (bootverbose)
4275 device_printf(dev, "%ssetting %s on %s chip\n",
4276 (error) ? "FAILURE " : "",
4277 ata_mode2str(mode), ctlr->chip->text);
4278 if (!error) {
4279 if (mode >= ATA_UDMA0) {
4280 pci_write_config(gparent, 0x56,
4281 (pci_read_config(gparent, 0x56, 2) &
4282 ~(0xf << (devno << 2))) |
4283 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
4284 pci_write_config(gparent, 0x54,
4285 pci_read_config(gparent, 0x54, 1) |
4286 (0x01 << devno), 1);
4287 pci_write_config(gparent, 0x44,
4288 (pci_read_config(gparent, 0x44, 4) &
4289 ~(0xff << offset)) |
4290 (dmatimings[2] << offset), 4);
4291 }
4292 else if (mode >= ATA_WDMA0) {
4293 pci_write_config(gparent, 0x54,
4294 pci_read_config(gparent, 0x54, 1) &
4295 ~(0x01 << devno), 1);
4296 pci_write_config(gparent, 0x44,
4297 (pci_read_config(gparent, 0x44, 4) &
4298 ~(0xff << offset)) |
4299 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
4300 }
4301 else
4302 pci_write_config(gparent, 0x54,
4303 pci_read_config(gparent, 0x54, 1) &
4304 ~(0x01 << devno), 1);
4305
4306 pci_write_config(gparent, 0x40,
4307 (pci_read_config(gparent, 0x40, 4) &
4308 ~(0xff << offset)) |
4309 (piotimings[ata_mode2idx(mode)] << offset), 4);
4310 atadev->mode = mode;
4311 }
4312 }
4313
4314
4315 /*
4316 * Silicon Image Inc. (SiI) (former CMD) chipset support functions
4317 */
4318 int
4319 ata_sii_ident(device_t dev)
4320 {
4321 struct ata_pci_controller *ctlr = device_get_softc(dev);
4322 static struct ata_chip_id ids[] =
4323 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" },
4324 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" },
4325 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
4326 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
4327 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" },
4328 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
4329 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
4330 { ATA_SII3124, 0x00, SIIPRBIO, SII4CH, ATA_SA300, "SiI 3124" },
4331 { ATA_SII3132, 0x00, SIIPRBIO, 0, ATA_SA300, "SiI 3132" },
4332 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" },
4333 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" },
4334 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" },
4335 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" },
4336 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" },
4337 { 0, 0, 0, 0, 0, 0}};
4338
4339 if (!(ctlr->chip = ata_match_chip(dev, ids)))
4340 return ENXIO;
4341
4342 ata_set_desc(dev);
4343 ctlr->chipinit = ata_sii_chipinit;
4344 return 0;
4345 }
4346
4347 static int
4348 ata_sii_chipinit(device_t dev)
4349 {
4350 struct ata_pci_controller *ctlr = device_get_softc(dev);
4351
4352 if (ata_setup_interrupt(dev))
4353 return ENXIO;
4354
4355 switch (ctlr->chip->cfg1) {
4356 case SIIPRBIO:
4357 ctlr->r_type1 = SYS_RES_MEMORY;
4358 ctlr->r_rid1 = PCIR_BAR(0);
4359 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
4360 &ctlr->r_rid1, RF_ACTIVE)))
4361 return ENXIO;
4362
4363 ctlr->r_rid2 = PCIR_BAR(2);
4364 ctlr->r_type2 = SYS_RES_MEMORY;
4365 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4366 &ctlr->r_rid2, RF_ACTIVE))){
4367 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
4368 return ENXIO;
4369 }
4370 ctlr->allocate = ata_siiprb_allocate;
4371 ctlr->reset = ata_siiprb_reset;
4372 ctlr->dmainit = ata_siiprb_dmainit;
4373 ctlr->setmode = ata_sata_setmode;
4374 ctlr->channels = (ctlr->chip->cfg2 == SII4CH) ? 4 : 2;
4375
4376 /* reset controller */
4377 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
4378 DELAY(10000);
4379 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
4380
4381 /* enable PCI interrupt */
4382 pci_write_config(dev, PCIR_COMMAND,
4383 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
4384 break;
4385
4386 case SIIMEMIO:
4387 ctlr->r_type2 = SYS_RES_MEMORY;
4388 ctlr->r_rid2 = PCIR_BAR(5);
4389 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4390 &ctlr->r_rid2, RF_ACTIVE)))
4391 return ENXIO;
4392
4393 if (ctlr->chip->cfg2 & SIISETCLK) {
4394 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4395 pci_write_config(dev, 0x8a,
4396 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
4397 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4398 device_printf(dev, "%s could not set ATA133 clock\n",
4399 ctlr->chip->text);
4400 }
4401
4402 /* if we have 4 channels enable the second set */
4403 if (ctlr->chip->cfg2 & SII4CH) {
4404 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
4405 ctlr->channels = 4;
4406 }
4407
4408 /* dont block interrupts from any channel */
4409 pci_write_config(dev, 0x48,
4410 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
4411
4412 /* enable PCI interrupt as BIOS might not */
4413 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
4414
4415 ctlr->allocate = ata_sii_allocate;
4416 if (ctlr->chip->max_dma >= ATA_SA150) {
4417 ctlr->reset = ata_sii_reset;
4418 ctlr->setmode = ata_sata_setmode;
4419 }
4420 else
4421 ctlr->setmode = ata_sii_setmode;
4422 break;
4423
4424 default:
4425 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
4426 device_printf(dev, "HW has secondary channel disabled\n");
4427 ctlr->channels = 1;
4428 }
4429
4430 /* enable interrupt as BIOS might not */
4431 pci_write_config(dev, 0x71, 0x01, 1);
4432
4433 ctlr->allocate = ata_cmd_allocate;
4434 ctlr->setmode = ata_cmd_setmode;
4435 break;
4436 }
4437 return 0;
4438 }
4439
4440 static int
4441 ata_cmd_allocate(device_t dev)
4442 {
4443 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4444 struct ata_channel *ch = device_get_softc(dev);
4445
4446 /* setup the usual register normal pci style */
4447 if (ata_pci_allocate(dev))
4448 return ENXIO;
4449
4450 if (ctlr->chip->cfg2 & SIIINTR)
4451 ch->hw.status = ata_cmd_status;
4452
4453 return 0;
4454 }
4455
4456 static int
4457 ata_cmd_status(device_t dev)
4458 {
4459 struct ata_channel *ch = device_get_softc(dev);
4460 u_int8_t reg71;
4461
4462 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
4463 (ch->unit ? 0x08 : 0x04))) {
4464 pci_write_config(device_get_parent(ch->dev), 0x71,
4465 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
4466 return ata_pci_status(dev);
4467 }
4468 return 0;
4469 }
4470
4471 static void
4472 ata_cmd_setmode(device_t dev, int mode)
4473 {
4474 device_t gparent = GRANDPARENT(dev);
4475 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4476 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4477 struct ata_device *atadev = device_get_softc(dev);
4478 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4479 int error;
4480
4481 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4482
4483 mode = ata_check_80pin(dev, mode);
4484
4485 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4486
4487 if (bootverbose)
4488 device_printf(dev, "%ssetting %s on %s chip\n",
4489 (error) ? "FAILURE " : "",
4490 ata_mode2str(mode), ctlr->chip->text);
4491 if (!error) {
4492 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
4493 int ureg = ch->unit ? 0x7b : 0x73;
4494
4495 if (mode >= ATA_UDMA0) {
4496 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
4497 { 0x11, 0x42 }, { 0x25, 0x8a },
4498 { 0x15, 0x4a }, { 0x05, 0x0a } };
4499
4500 u_int8_t umode = pci_read_config(gparent, ureg, 1);
4501
4502 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
4503 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)];
4504 pci_write_config(gparent, ureg, umode, 1);
4505 }
4506 else if (mode >= ATA_WDMA0) {
4507 int dmatimings[] = { 0x87, 0x32, 0x3f };
4508
4509 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1);
4510 pci_write_config(gparent, ureg,
4511 pci_read_config(gparent, ureg, 1) &
4512 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4513 }
4514 else {
4515 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
4516 pci_write_config(gparent, treg,
4517 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
4518 pci_write_config(gparent, ureg,
4519 pci_read_config(gparent, ureg, 1) &
4520 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4521 }
4522 atadev->mode = mode;
4523 }
4524 }
4525
4526 static int
4527 ata_sii_allocate(device_t dev)
4528 {
4529 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4530 struct ata_channel *ch = device_get_softc(dev);
4531 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
4532 int i;
4533
4534 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
4535 ch->r_io[i].res = ctlr->r_res2;
4536 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
4537 }
4538 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
4539 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
4540 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
4541 ata_default_registers(dev);
4542
4543 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
4544 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
4545 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
4546 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
4547 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
4548 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
4549
4550 if (ctlr->chip->max_dma >= ATA_SA150) {
4551 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4552 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
4553 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4554 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
4555 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4556 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
4557 ch->flags |= ATA_NO_SLAVE;
4558
4559 /* enable PHY state change interrupt */
4560 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
4561 }
4562
4563 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) {
4564 /* work around errata in early chips */
4565 ch->dma->boundary = 16 * DEV_BSIZE;
4566 ch->dma->segsize = 15 * DEV_BSIZE;
4567 }
4568
4569 ata_pci_hw(dev);
4570 ch->hw.status = ata_sii_status;
4571 return 0;
4572 }
4573
4574 static int
4575 ata_sii_status(device_t dev)
4576 {
4577 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4578 struct ata_channel *ch = device_get_softc(dev);
4579 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8);
4580 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8);
4581
4582 /* do we have any PHY events ? */
4583 if (ctlr->chip->max_dma >= ATA_SA150 &&
4584 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
4585 ata_sata_phy_check_events(dev);
4586
4587 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
4588 return ata_pci_status(dev);
4589 else
4590 return 0;
4591 }
4592
4593 static void
4594 ata_sii_reset(device_t dev)
4595 {
4596 if (ata_sata_phy_reset(dev))
4597 ata_generic_reset(dev);
4598 }
4599
4600 static void
4601 ata_sii_setmode(device_t dev, int mode)
4602 {
4603 device_t gparent = GRANDPARENT(dev);
4604 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4605 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4606 struct ata_device *atadev = device_get_softc(dev);
4607 int rego = (ch->unit << 4) + (ATA_DEV(atadev->unit) << 1);
4608 int mreg = ch->unit ? 0x84 : 0x80;
4609 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2);
4610 int mval = pci_read_config(gparent, mreg, 1) & ~mask;
4611 int error;
4612
4613 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4614
4615 if (ctlr->chip->cfg2 & SIISETCLK) {
4616 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) &
4617 (ch->unit ? 0x02 : 0x01))) {
4618 ata_print_cable(dev, "controller");
4619 mode = ATA_UDMA2;
4620 }
4621 }
4622 else
4623 mode = ata_check_80pin(dev, mode);
4624
4625 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4626
4627 if (bootverbose)
4628 device_printf(dev, "%ssetting %s on %s chip\n",
4629 (error) ? "FAILURE " : "",
4630 ata_mode2str(mode), ctlr->chip->text);
4631 if (error)
4632 return;
4633
4634 if (mode >= ATA_UDMA0) {
4635 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
4636 u_int8_t ureg = 0xac + rego;
4637
4638 pci_write_config(gparent, mreg,
4639 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1);
4640 pci_write_config(gparent, ureg,
4641 (pci_read_config(gparent, ureg, 1) & ~0x3f) |
4642 udmatimings[mode & ATA_MODE_MASK], 1);
4643
4644 }
4645 else if (mode >= ATA_WDMA0) {
4646 u_int8_t dreg = 0xa8 + rego;
4647 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
4648
4649 pci_write_config(gparent, mreg,
4650 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1);
4651 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
4652
4653 }
4654 else {
4655 u_int8_t preg = 0xa4 + rego;
4656 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
4657
4658 pci_write_config(gparent, mreg,
4659 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1);
4660 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2);
4661 }
4662 atadev->mode = mode;
4663 }
4664
4665
4666 struct ata_siiprb_dma_prdentry {
4667 u_int64_t addr;
4668 u_int32_t count;
4669 u_int32_t control;
4670 } __packed;
4671
4672 struct ata_siiprb_ata_command {
4673 struct ata_siiprb_dma_prdentry prd[126];
4674 } __packed;
4675
4676 struct ata_siiprb_atapi_command {
4677 u_int8_t ccb[16];
4678 struct ata_siiprb_dma_prdentry prd[125];
4679 } __packed;
4680
4681 struct ata_siiprb_command {
4682 u_int16_t control;
4683 u_int16_t protocol_override;
4684 u_int32_t transfer_count;
4685 u_int8_t fis[24];
4686 union {
4687 struct ata_siiprb_ata_command ata;
4688 struct ata_siiprb_atapi_command atapi;
4689 } u;
4690 } __packed;
4691
4692 static int
4693 ata_siiprb_allocate(device_t dev)
4694 {
4695 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4696 struct ata_channel *ch = device_get_softc(dev);
4697 int offset = ch->unit * 0x2000;
4698
4699 /* set the SATA resources */
4700 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4701 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
4702 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4703 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
4704 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4705 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
4706 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
4707 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
4708
4709 ch->hw.begin_transaction = ata_siiprb_begin_transaction;
4710 ch->hw.end_transaction = ata_siiprb_end_transaction;
4711 ch->hw.status = ata_siiprb_status;
4712 ch->hw.command = NULL; /* not used here */
4713 return 0;
4714 }
4715
4716 static int
4717 ata_siiprb_status(device_t dev)
4718 {
4719 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4720 struct ata_channel *ch = device_get_softc(dev);
4721 u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044);
4722 int offset = ch->unit * 0x2000;
4723
4724 if (action & (1 << ch->unit)) {
4725 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
4726
4727 /* do we have any PHY events ? */
4728 ata_sata_phy_check_events(dev);
4729
4730 /* clear interrupt(s) */
4731 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
4732
4733 /* do we have any device action ? */
4734 return (istatus & 0x00000003);
4735 }
4736 return 0;
4737 }
4738
4739 static int
4740 ata_siiprb_begin_transaction(struct ata_request *request)
4741 {
4742 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
4743 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4744 struct ata_siiprb_command *prb;
4745 struct ata_siiprb_dma_prdentry *prd;
4746 int offset = ch->unit * 0x2000;
4747 u_int64_t prb_bus;
4748 int tag = 0, dummy;
4749
4750 /* SOS XXX */
4751 if (request->u.ata.command == ATA_DEVICE_RESET) {
4752 request->result = 0;
4753 return ATA_OP_FINISHED;
4754 }
4755
4756 /* check for 48 bit access and convert if needed */
4757 ata_modify_if_48bit(request);
4758
4759 /* get a piece of the workspace for this request */
4760 prb = (struct ata_siiprb_command *)
4761 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
4762
4763 /* set basic prd options ata/atapi etc etc */
4764 bzero(prb, sizeof(struct ata_siiprb_command));
4765
4766 /* setup the FIS for this request */
4767 if (!ata_request2fis_h2d(request, &prb->fis[0])) {
4768 device_printf(request->dev, "setting up SATA FIS failed\n");
4769 request->result = EIO;
4770 return ATA_OP_FINISHED;
4771 }
4772
4773 /* setup transfer type */
4774 if (request->flags & ATA_R_ATAPI) {
4775 struct ata_device *atadev = device_get_softc(request->dev);
4776
4777 bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16);
4778 if ((atadev->param.config & ATA_PROTO_MASK) == ATA_PROTO_ATAPI_12)
4779 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020);
4780 else
4781 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020);
4782 if (request->flags & ATA_R_READ)
4783 prb->control = htole16(0x0010);
4784 if (request->flags & ATA_R_WRITE)
4785 prb->control = htole16(0x0020);
4786 prd = &prb->u.atapi.prd[0];
4787 }
4788 else
4789 prd = &prb->u.ata.prd[0];
4790
4791 /* if request moves data setup and load SG list */
4792 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
4793 if (ch->dma->load(ch->dev, request->data, request->bytecount,
4794 request->flags & ATA_R_READ, prd, &dummy)) {
4795 device_printf(request->dev, "setting up DMA failed\n");
4796 request->result = EIO;
4797 return ATA_OP_FINISHED;
4798 }
4799 }
4800
4801 /* activate the prb */
4802 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
4803 ATA_OUTL(ctlr->r_res2,
4804 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
4805 ATA_OUTL(ctlr->r_res2,
4806 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
4807
4808 /* start the timeout */
4809 callout_reset(&request->callout, request->timeout * hz,
4810 (timeout_t*)ata_timeout, request);
4811 return ATA_OP_CONTINUES;
4812 }
4813
4814 static int
4815 ata_siiprb_end_transaction(struct ata_request *request)
4816 {
4817 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
4818 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4819 struct ata_siiprb_command *prb;
4820 int offset = ch->unit * 0x2000;
4821 int error, timeout, tag = 0;
4822
4823 /* kill the timeout */
4824 callout_stop(&request->callout);
4825
4826 prb = (struct ata_siiprb_command *)
4827 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
4828
4829 /* any controller errors flagged ? */
4830 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
4831 if (bootverbose)
4832 printf("ata_siiprb_end_transaction %s error=%08x\n",
4833 ata_cmd2str(request), error);
4834
4835 /* if device error status get details */
4836 if (error == 1 || error == 2) {
4837 request->status = prb->fis[2];
4838 if (request->status & ATA_S_ERROR)
4839 request->error = prb->fis[3];
4840 }
4841
4842 /* SOS XXX handle other controller errors here */
4843
4844 /* initialize port */
4845 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004);
4846
4847 /* poll for port ready */
4848 for (timeout = 0; timeout < 1000; timeout++) {
4849 DELAY(1000);
4850 if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000)
4851 break;
4852 }
4853 if (bootverbose) {
4854 if (timeout >= 1000)
4855 device_printf(ch->dev, "port initialize timeout\n");
4856 else
4857 device_printf(ch->dev, "port initialize time=%dms\n", timeout);
4858 }
4859 }
4860
4861 /* update progress */
4862 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
4863 if (request->flags & ATA_R_READ)
4864 request->donecount = prb->transfer_count;
4865 else
4866 request->donecount = request->bytecount;
4867 }
4868
4869 /* release SG list etc */
4870 ch->dma->unload(ch->dev);
4871
4872 return ATA_OP_FINISHED;
4873 }
4874
4875 static void
4876 ata_siiprb_reset(device_t dev)
4877 {
4878 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4879 struct ata_channel *ch = device_get_softc(dev);
4880 int offset = ch->unit * 0x2000;
4881 struct ata_siiprb_command *prb;
4882 u_int64_t prb_bus;
4883 u_int32_t status, signature;
4884 int timeout, tag = 0;
4885
4886 /* reset channel HW */
4887 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
4888 DELAY(1000);
4889 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
4890 DELAY(10000);
4891
4892 /* poll for channel ready */
4893 for (timeout = 0; timeout < 1000; timeout++) {
4894 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000)
4895 break;
4896 DELAY(1000);
4897 }
4898
4899 if (bootverbose) {
4900 if (timeout >= 1000)
4901 device_printf(ch->dev, "channel HW reset timeout\n");
4902 else
4903 device_printf(ch->dev, "channel HW reset time=%dms\n", timeout);
4904 }
4905
4906 /* reset phy */
4907 if (!ata_sata_phy_reset(dev)) {
4908 if (bootverbose)
4909 device_printf(ch->dev, "phy reset found no device\n");
4910 ch->devices = 0;
4911 goto finish;
4912 }
4913
4914 /* get a piece of the workspace for a soft reset request */
4915 prb = (struct ata_siiprb_command *)
4916 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
4917 bzero(prb, sizeof(struct ata_siiprb_command));
4918 prb->control = htole16(0x0080);
4919
4920 /* activate the soft reset prb */
4921 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
4922 ATA_OUTL(ctlr->r_res2,
4923 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
4924 ATA_OUTL(ctlr->r_res2,
4925 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
4926
4927 /* poll for command finished */
4928 for (timeout = 0; timeout < 10000; timeout++) {
4929 DELAY(1000);
4930 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
4931 break;
4932 }
4933 if (timeout >= 1000) {
4934 device_printf(ch->dev, "reset timeout - no device found\n");
4935 ch->devices = 0;
4936 goto finish;
4937 }
4938 if (bootverbose)
4939 device_printf(ch->dev, "soft reset exec time=%dms status=%08x\n",
4940 timeout, status);
4941
4942 /* find out whats there */
4943 prb = (struct ata_siiprb_command *)
4944 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
4945 signature =
4946 prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
4947 if (bootverbose)
4948 device_printf(ch->dev, "SIGNATURE=%08x\n", signature);
4949 switch (signature) {
4950 case 0x00000101:
4951 ch->devices = ATA_ATA_MASTER;
4952 break;
4953 case 0x96690101:
4954 ch->devices = ATA_PORTMULTIPLIER;
4955 device_printf(ch->dev, "Portmultipliers not supported yet\n");
4956 ch->devices = 0;
4957 break;
4958 case 0xeb140101:
4959 ch->devices = ATA_ATAPI_MASTER;
4960 break;
4961 default:
4962 ch->devices = 0;
4963 }
4964 if (bootverbose)
4965 device_printf(dev, "siiprb_reset devices=0x%b\n", ch->devices,
4966 "\2\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
4967
4968 finish:
4969 /* clear interrupt(s) */
4970 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
4971
4972 /* require explicit interrupt ack */
4973 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
4974
4975 /* 64bit mode */
4976 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
4977
4978 /* enable interrupts wanted */
4979 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
4980 }
4981
4982 static void
4983 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
4984 {
4985 struct ata_dmasetprd_args *args = xsc;
4986 struct ata_siiprb_dma_prdentry *prd = args->dmatab;
4987 int i;
4988
4989 if ((args->error = error))
4990 return;
4991
4992 for (i = 0; i < nsegs; i++) {
4993 prd[i].addr = htole64(segs[i].ds_addr);
4994 prd[i].count = htole32(segs[i].ds_len);
4995 }
4996 prd[i - 1].control = htole32(ATA_DMA_EOT);
4997 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
4998 args->nsegs = nsegs;
4999 }
5000
5001 static void
5002 ata_siiprb_dmainit(device_t dev)
5003 {
5004 struct ata_channel *ch = device_get_softc(dev);
5005
5006 ata_dmainit(dev);
5007 if (ch->dma) {
5008 /* note start and stop are not used here */
5009 ch->dma->setprd = ata_siiprb_dmasetprd;
5010 ch->dma->max_address = BUS_SPACE_MAXADDR;
5011 }
5012 }
5013
5014
5015 /*
5016 * Silicon Integrated Systems Corp. (SiS) chipset support functions
5017 */
5018 int
5019 ata_sis_ident(device_t dev)
5020 {
5021 struct ata_pci_controller *ctlr = device_get_softc(dev);
5022 struct ata_chip_id *idx;
5023 static struct ata_chip_id ids[] =
5024 {{ ATA_SIS182, 0x00, SISSATA, 0, ATA_SA150, "182" }, /* south */
5025 { ATA_SIS181, 0x00, SISSATA, 0, ATA_SA150, "181" }, /* south */
5026 { ATA_SIS180, 0x00, SISSATA, 0, ATA_SA150, "180" }, /* south */
5027 { ATA_SIS965, 0x00, SIS133NEW, 0, ATA_UDMA6, "965" }, /* south */
5028 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "964" }, /* south */
5029 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "963" }, /* south */
5030 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "962" }, /* south */
5031
5032 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */
5033 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */
5034 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */
5035 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */
5036
5037 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */
5038 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "633" }, /* unknown */
5039 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */
5040 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "630" }, /* 1chip */
5041 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "620" }, /* 1chip */
5042
5043 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "550" },
5044 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "540" },
5045 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "530" },
5046
5047 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "5513" },
5048 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "5513" },
5049 { 0, 0, 0, 0, 0, 0 }};
5050 char buffer[64];
5051 int found = 0;
5052
5053 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev))))
5054 return ENXIO;
5055
5056 if (idx->cfg2 && !found) {
5057 u_int8_t reg57 = pci_read_config(dev, 0x57, 1);
5058
5059 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1);
5060 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) {
5061 found = 1;
5062 idx->cfg1 = SIS133NEW;
5063 idx->max_dma = ATA_UDMA6;
5064 sprintf(buffer, "SiS 962/963 %s controller",
5065 ata_mode2str(idx->max_dma));
5066 }
5067 pci_write_config(dev, 0x57, reg57, 1);
5068 }
5069 if (idx->cfg2 && !found) {
5070 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1);
5071
5072 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1);
5073 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) {
5074 struct ata_chip_id id[] =
5075 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }};
5076
5077 found = 1;
5078 if (ata_find_chip(dev, id, pci_get_slot(dev))) {
5079 idx->cfg1 = SIS133OLD;
5080 idx->max_dma = ATA_UDMA6;
5081 }
5082 else {
5083 idx->cfg1 = SIS100NEW;
5084 idx->max_dma = ATA_UDMA5;
5085 }
5086 sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
5087 }
5088 pci_write_config(dev, 0x4a, reg4a, 1);
5089 }
5090 if (!found)
5091 sprintf(buffer,"SiS %s %s controller",
5092 idx->text, ata_mode2str(idx->max_dma));
5093
5094 device_set_desc_copy(dev, buffer);
5095 ctlr->chip = idx;
5096 ctlr->chipinit = ata_sis_chipinit;
5097 return 0;
5098 }
5099
5100 static int
5101 ata_sis_chipinit(device_t dev)
5102 {
5103 struct ata_pci_controller *ctlr = device_get_softc(dev);
5104
5105 if (ata_setup_interrupt(dev))
5106 return ENXIO;
5107
5108 switch (ctlr->chip->cfg1) {
5109 case SIS33:
5110 break;
5111 case SIS66:
5112 case SIS100OLD:
5113 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1);
5114 break;
5115 case SIS100NEW:
5116 case SIS133OLD:
5117 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1);
5118 break;
5119 case SIS133NEW:
5120 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2);
5121 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2);
5122 break;
5123 case SISSATA:
5124 ctlr->r_type2 = SYS_RES_IOPORT;
5125 ctlr->r_rid2 = PCIR_BAR(5);
5126 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
5127 &ctlr->r_rid2, RF_ACTIVE))) {
5128 ctlr->allocate = ata_sis_allocate;
5129 ctlr->reset = ata_sis_reset;
5130
5131 /* enable PCI interrupt */
5132 pci_write_config(dev, PCIR_COMMAND,
5133 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
5134 }
5135 ctlr->setmode = ata_sata_setmode;
5136 return 0;
5137 default:
5138 return ENXIO;
5139 }
5140 ctlr->setmode = ata_sis_setmode;
5141 return 0;
5142 }
5143
5144 static int
5145 ata_sis_allocate(device_t dev)
5146 {
5147 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5148 struct ata_channel *ch = device_get_softc(dev);
5149 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6);
5150
5151 /* setup the usual register normal pci style */
5152 if (ata_pci_allocate(dev))
5153 return ENXIO;
5154
5155 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
5156 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset;
5157 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
5158 ch->r_io[ATA_SERROR].offset = 0x04 + offset;
5159 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
5160 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset;
5161 ch->flags |= ATA_NO_SLAVE;
5162
5163 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */
5164 /* XXX SOS unknown how to enable PHY state change interrupt */
5165 return 0;
5166 }
5167
5168 static void
5169 ata_sis_reset(device_t dev)
5170 {
5171 if (ata_sata_phy_reset(dev))
5172 ata_generic_reset(dev);
5173 }
5174
5175 static void
5176 ata_sis_setmode(device_t dev, int mode)
5177 {
5178 device_t gparent = GRANDPARENT(dev);
5179 struct ata_pci_controller *ctlr = device_get_softc(gparent);
5180 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5181 struct ata_device *atadev = device_get_softc(dev);
5182 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
5183 int error;
5184
5185 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
5186
5187 if (ctlr->chip->cfg1 == SIS133NEW) {
5188 if (mode > ATA_UDMA2 &&
5189 pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) {
5190 ata_print_cable(dev, "controller");
5191 mode = ATA_UDMA2;
5192 }
5193 }
5194 else {
5195 if (mode > ATA_UDMA2 &&
5196 pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) {
5197 ata_print_cable(dev, "controller");
5198 mode = ATA_UDMA2;
5199 }
5200 }
5201
5202 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
5203
5204 if (bootverbose)
5205 device_printf(dev, "%ssetting %s on %s chip\n",
5206 (error) ? "FAILURE " : "",
5207 ata_mode2str(mode), ctlr->chip->text);
5208 if (!error) {
5209 switch (ctlr->chip->cfg1) {
5210 case SIS133NEW: {
5211 u_int32_t timings[] =
5212 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
5213 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
5214 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
5215 u_int32_t reg;
5216
5217 reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
5218 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4);
5219 break;
5220 }
5221 case SIS133OLD: {
5222 u_int16_t timings[] =
5223 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
5224 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
5225
5226 u_int16_t reg = 0x40 + (devno << 1);
5227
5228 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
5229 break;
5230 }
5231 case SIS100NEW: {
5232 u_int16_t timings[] =
5233 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
5234 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
5235 u_int16_t reg = 0x40 + (devno << 1);
5236
5237 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
5238 break;
5239 }
5240 case SIS100OLD:
5241 case SIS66:
5242 case SIS33: {
5243 u_int16_t timings[] =
5244 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
5245 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
5246 u_int16_t reg = 0x40 + (devno << 1);
5247
5248 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
5249 break;
5250 }
5251 }
5252 atadev->mode = mode;
5253 }
5254 }
5255
5256
5257 /* VIA Technologies Inc. chipset support functions */
5258 int
5259 ata_via_ident(device_t dev)
5260 {
5261 struct ata_pci_controller *ctlr = device_get_softc(dev);
5262 static struct ata_chip_id ids[] =
5263 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" },
5264 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" },
5265 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" },
5266 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" },
5267 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"},
5268 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" },
5269 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" },
5270 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" },
5271 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" },
5272 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" },
5273 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" },
5274 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" },
5275 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
5276 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" },
5277 { ATA_VIA8237S, 0x00, VIA133, 0x00, ATA_UDMA6, "8237S" },
5278 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" },
5279 { 0, 0, 0, 0, 0, 0 }};
5280 static struct ata_chip_id new_ids[] =
5281 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" },
5282 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" },
5283 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" },
5284 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" },
5285 { ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" },
5286 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" },
5287 { 0, 0, 0, 0, 0, 0 }};
5288
5289 if (pci_get_devid(dev) == ATA_VIA82C571) {
5290 if (!(ctlr->chip = ata_find_chip(dev, ids, -99)))
5291 return ENXIO;
5292 }
5293 else {
5294 if (!(ctlr->chip = ata_match_chip(dev, new_ids)))
5295 return ENXIO;
5296 }
5297
5298 ata_set_desc(dev);
5299 ctlr->chipinit = ata_via_chipinit;
5300 return 0;
5301 }
5302
5303 static int
5304 ata_via_chipinit(device_t dev)
5305 {
5306 struct ata_pci_controller *ctlr = device_get_softc(dev);
5307
5308 if (ata_setup_interrupt(dev))
5309 return ENXIO;
5310
5311 if (ctlr->chip->max_dma >= ATA_SA150) {
5312 /* do we have AHCI capability ? */
5313 if ((ctlr->chip->cfg2 == VIAAHCI) && ata_ahci_chipinit(dev) != ENXIO)
5314 return 0;
5315
5316 ctlr->r_type2 = SYS_RES_IOPORT;
5317 ctlr->r_rid2 = PCIR_BAR(5);
5318 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
5319 &ctlr->r_rid2, RF_ACTIVE))) {
5320 ctlr->allocate = ata_via_allocate;
5321 ctlr->reset = ata_via_reset;
5322
5323 /* enable PCI interrupt */
5324 pci_write_config(dev, PCIR_COMMAND,
5325 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
5326 }
5327
5328 if (ctlr->chip->cfg2 & VIABAR) {
5329 ctlr->channels = 3;
5330 ctlr->setmode = ata_via_setmode;
5331 }
5332 else
5333 ctlr->setmode = ata_sata_setmode;
5334 return 0;
5335 }
5336
5337 /* prepare for ATA-66 on the 82C686a and 82C596b */
5338 if (ctlr->chip->cfg2 & VIACLK)
5339 pci_write_config(dev, 0x50, 0x030b030b, 4);
5340
5341 /* the southbridge might need the data corruption fix */
5342 if (ctlr->chip->cfg2 & VIABUG)
5343 ata_via_southbridge_fixup(dev);
5344
5345 /* set fifo configuration half'n'half */
5346 pci_write_config(dev, 0x43,
5347 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
5348
5349 /* set status register read retry */
5350 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
5351
5352 /* set DMA read & end-of-sector fifo flush */
5353 pci_write_config(dev, 0x46,
5354 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
5355
5356 /* set sector size */
5357 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
5358 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
5359
5360 ctlr->setmode = ata_via_family_setmode;
5361 return 0;
5362 }
5363
5364 static int
5365 ata_via_allocate(device_t dev)
5366 {
5367 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5368 struct ata_channel *ch = device_get_softc(dev);
5369
5370 /* newer SATA chips has resources in one BAR for each channel */
5371 if (ctlr->chip->cfg2 & VIABAR) {
5372 struct resource *r_io;
5373 int i, rid;
5374
5375 rid = PCIR_BAR(ch->unit);
5376 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev),
5377 SYS_RES_IOPORT,
5378 &rid, RF_ACTIVE)))
5379 return ENXIO;
5380
5381 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
5382 ch->r_io[i].res = r_io;
5383 ch->r_io[i].offset = i;
5384 }
5385 ch->r_io[ATA_CONTROL].res = r_io;
5386 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE;
5387 ch->r_io[ATA_IDX_ADDR].res = r_io;
5388 ata_default_registers(dev);
5389 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
5390 ch->r_io[i].res = ctlr->r_res1;
5391 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
5392 }
5393 ata_pci_hw(dev);
5394 if (ch->unit >= 2)
5395 return 0;
5396 }
5397 else {
5398 /* setup the usual register normal pci style */
5399 if (ata_pci_allocate(dev))
5400 return ENXIO;
5401 }
5402
5403 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
5404 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1);
5405 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
5406 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1);
5407 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
5408 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1);
5409 ch->flags |= ATA_NO_SLAVE;
5410
5411 /* XXX SOS PHY hotplug handling missing in VIA chip ?? */
5412 /* XXX SOS unknown how to enable PHY state change interrupt */
5413 return 0;
5414 }
5415
5416 static void
5417 ata_via_reset(device_t dev)
5418 {
5419 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5420 struct ata_channel *ch = device_get_softc(dev);
5421
5422 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1))
5423 ata_generic_reset(dev);
5424 else
5425 if (ata_sata_phy_reset(dev))
5426 ata_generic_reset(dev);
5427 }
5428
5429 static void
5430 ata_via_setmode(device_t dev, int mode)
5431 {
5432 device_t gparent = GRANDPARENT(dev);
5433 struct ata_pci_controller *ctlr = device_get_softc(gparent);
5434 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5435 struct ata_device *atadev = device_get_softc(dev);
5436 int error;
5437
5438 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) {
5439 u_int8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20,
5440 0x65, 0x32, 0x20,
5441 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
5442 u_int8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 };
5443
5444 mode = ata_check_80pin(dev, ata_limit_mode(dev, mode, ATA_UDMA6));
5445 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
5446 if (bootverbose)
5447 device_printf(dev, "%ssetting %s on %s chip\n",
5448 (error) ? "FAILURE " : "", ata_mode2str(mode),
5449 ctlr->chip->text);
5450 if (!error) {
5451 pci_write_config(gparent, 0xab, pio_timings[ata_mode2idx(mode)], 1);
5452 if (mode >= ATA_UDMA0)
5453 pci_write_config(gparent, 0xb3,
5454 dma_timings[mode & ATA_MODE_MASK], 1);
5455 atadev->mode = mode;
5456 }
5457 }
5458 else
5459 ata_sata_setmode(dev, mode);
5460 }
5461
5462 static void
5463 ata_via_southbridge_fixup(device_t dev)
5464 {
5465 device_t *children;
5466 int nchildren, i;
5467
5468 if (device_get_children(device_get_parent(dev), &children, &nchildren))
5469 return;
5470
5471 for (i = 0; i < nchildren; i++) {
5472 if (pci_get_devid(children[i]) == ATA_VIA8363 ||
5473 pci_get_devid(children[i]) == ATA_VIA8371 ||
5474 pci_get_devid(children[i]) == ATA_VIA8662 ||
5475 pci_get_devid(children[i]) == ATA_VIA8361) {
5476 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
5477
5478 if ((reg76 & 0xf0) != 0xd0) {
5479 device_printf(dev,
5480 "Correcting VIA config for southbridge data corruption bug\n");
5481 pci_write_config(children[i], 0x75, 0x80, 1);
5482 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
5483 }
5484 break;
5485 }
5486 }
5487 free(children, M_TEMP);
5488 }
5489
5490
5491 /* common code for VIA, AMD & nVidia */
5492 static void
5493 ata_via_family_setmode(device_t dev, int mode)
5494 {
5495 device_t gparent = GRANDPARENT(dev);
5496 struct ata_pci_controller *ctlr = device_get_softc(gparent);
5497 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5498 struct ata_device *atadev = device_get_softc(dev);
5499 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
5500 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
5501 int modes[][7] = {
5502 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
5503 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
5504 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
5505 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
5506 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */
5507 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
5508 int reg = 0x53 - devno;
5509 int error;
5510
5511 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
5512
5513 if (ctlr->chip->cfg2 & AMDCABLE) {
5514 if (mode > ATA_UDMA2 &&
5515 !(pci_read_config(gparent, 0x42, 1) & (1 << devno))) {
5516 ata_print_cable(dev, "controller");
5517 mode = ATA_UDMA2;
5518 }
5519 }
5520 else
5521 mode = ata_check_80pin(dev, mode);
5522
5523 if (ctlr->chip->cfg2 & NVIDIA)
5524 reg += 0x10;
5525
5526 if (ctlr->chip->cfg1 != VIA133)
5527 pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
5528
5529 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
5530
5531 if (bootverbose)
5532 device_printf(dev, "%ssetting %s on %s chip\n",
5533 (error) ? "FAILURE " : "", ata_mode2str(mode),
5534 ctlr->chip->text);
5535 if (!error) {
5536 if (mode >= ATA_UDMA0)
5537 pci_write_config(gparent, reg,
5538 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
5539 else
5540 pci_write_config(gparent, reg, 0x8b, 1);
5541 atadev->mode = mode;
5542 }
5543 }
5544
5545
5546 /* misc functions */
5547 static void
5548 ata_set_desc(device_t dev)
5549 {
5550 struct ata_pci_controller *ctlr = device_get_softc(dev);
5551 char buffer[128];
5552
5553 sprintf(buffer, "%s %s %s controller",
5554 ata_pcivendor2str(dev), ctlr->chip->text,
5555 ata_mode2str(ctlr->chip->max_dma));
5556 device_set_desc_copy(dev, buffer);
5557 }
5558
5559 static struct ata_chip_id *
5560 ata_match_chip(device_t dev, struct ata_chip_id *index)
5561 {
5562 while (index->chipid != 0) {
5563 if (pci_get_devid(dev) == index->chipid &&
5564 pci_get_revid(dev) >= index->chiprev)
5565 return index;
5566 index++;
5567 }
5568 return NULL;
5569 }
5570
5571 static struct ata_chip_id *
5572 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot)
5573 {
5574 device_t *children;
5575 int nchildren, i;
5576
5577 if (device_get_children(device_get_parent(dev), &children, &nchildren))
5578 return 0;
5579
5580 while (index->chipid != 0) {
5581 for (i = 0; i < nchildren; i++) {
5582 if (((slot >= 0 && pci_get_slot(children[i]) == slot) ||
5583 (slot < 0 && pci_get_slot(children[i]) <= -slot)) &&
5584 pci_get_devid(children[i]) == index->chipid &&
5585 pci_get_revid(children[i]) >= index->chiprev) {
5586 free(children, M_TEMP);
5587 return index;
5588 }
5589 }
5590 index++;
5591 }
5592 free(children, M_TEMP);
5593 return NULL;
5594 }
5595
5596 static int
5597 ata_setup_interrupt(device_t dev)
5598 {
5599 struct ata_pci_controller *ctlr = device_get_softc(dev);
5600 int rid = ATA_IRQ_RID;
5601
5602 if (!ata_legacy(dev)) {
5603 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
5604 RF_SHAREABLE | RF_ACTIVE))) {
5605 device_printf(dev, "unable to map interrupt\n");
5606 return ENXIO;
5607 }
5608 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
5609 ata_generic_intr, ctlr, &ctlr->handle))) {
5610 /* SOS XXX release r_irq */
5611 device_printf(dev, "unable to setup interrupt\n");
5612 return ENXIO;
5613 }
5614 }
5615 return 0;
5616 }
5617
5618 struct ata_serialize {
5619 struct mtx locked_mtx;
5620 int locked_ch;
5621 int restart_ch;
5622 };
5623
5624 static int
5625 ata_serialize(device_t dev, int flags)
5626 {
5627 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5628 struct ata_channel *ch = device_get_softc(dev);
5629 struct ata_serialize *serial;
5630 static int inited = 0;
5631 int res;
5632
5633 if (!inited) {
5634 serial = malloc(sizeof(struct ata_serialize),
5635 M_TEMP, M_NOWAIT | M_ZERO);
5636 mtx_init(&serial->locked_mtx, "ATA serialize lock", NULL, MTX_DEF);
5637 serial->locked_ch = -1;
5638 serial->restart_ch = -1;
5639 device_set_ivars(ctlr->dev, serial);
5640 inited = 1;
5641 }
5642 else
5643 serial = device_get_ivars(ctlr->dev);
5644
5645 mtx_lock(&serial->locked_mtx);
5646 switch (flags) {
5647 case ATA_LF_LOCK:
5648 if (serial->locked_ch == -1)
5649 serial->locked_ch = ch->unit;
5650 if (serial->locked_ch != ch->unit)
5651 serial->restart_ch = ch->unit;
5652 break;
5653
5654 case ATA_LF_UNLOCK:
5655 if (serial->locked_ch == ch->unit) {
5656 serial->locked_ch = -1;
5657 if (serial->restart_ch != -1) {
5658 if ((ch = ctlr->interrupt[serial->restart_ch].argument)) {
5659 serial->restart_ch = -1;
5660 mtx_unlock(&serial->locked_mtx);
5661 ata_start(ch->dev);
5662 return -1;
5663 }
5664 }
5665 }
5666 break;
5667
5668 case ATA_LF_WHICH:
5669 break;
5670 }
5671 res = serial->locked_ch;
5672 mtx_unlock(&serial->locked_mtx);
5673 return res;
5674 }
5675
5676 static void
5677 ata_print_cable(device_t dev, u_int8_t *who)
5678 {
5679 device_printf(dev,
5680 "DMA limited to UDMA33, %s found non-ATA66 cable\n", who);
5681 }
5682
5683 static int
5684 ata_atapi(device_t dev)
5685 {
5686 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5687 struct ata_device *atadev = device_get_softc(dev);
5688
5689 return ((atadev->unit == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) ||
5690 (atadev->unit == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE));
5691 }
5692
5693 static int
5694 ata_check_80pin(device_t dev, int mode)
5695 {
5696 struct ata_device *atadev = device_get_softc(dev);
5697
5698 if (mode > ATA_UDMA2 && !(atadev->param.hwres & ATA_CABLE_ID)) {
5699 ata_print_cable(dev, "device");
5700 mode = ATA_UDMA2;
5701 }
5702 return mode;
5703 }
5704
5705 static int
5706 ata_mode2idx(int mode)
5707 {
5708 if ((mode & ATA_DMA_MASK) == ATA_UDMA0)
5709 return (mode & ATA_MODE_MASK) + 8;
5710 if ((mode & ATA_DMA_MASK) == ATA_WDMA0)
5711 return (mode & ATA_MODE_MASK) + 5;
5712 return (mode & ATA_MODE_MASK) - ATA_PIO0;
5713 }
Cache object: 600cf7d6366df2c44cbfa142830c0fff
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