1 /*-
2 * Copyright (c) 1998 - 2007 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: stable/7/sys/dev/ata/ata-chipset.c 198334 2009-10-21 16:12:09Z mav $");
29
30 #include "opt_ata.h"
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/ata.h>
35 #include <sys/bus.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <sys/sema.h>
41 #include <sys/taskqueue.h>
42 #include <vm/uma.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
46 #include <sys/rman.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49 #include <dev/ata/ata-all.h>
50 #include <dev/ata/ata-pci.h>
51 #include <ata_if.h>
52
53 struct ata_serialize {
54 struct mtx locked_mtx;
55 int locked_ch;
56 int restart_ch;
57 };
58
59 /* local prototypes */
60 /* ata-chipset.c */
61 static int ata_generic_chipinit(device_t dev);
62 static void ata_generic_intr(void *data);
63 static void ata_generic_setmode(device_t dev, int mode);
64 static void ata_sata_phy_check_events(device_t dev);
65 static void ata_sata_phy_event(void *context, int dummy);
66 static int ata_sata_phy_reset(device_t dev);
67 static int ata_sata_connect(struct ata_channel *ch);
68 static void ata_sata_setmode(device_t dev, int mode);
69 static int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis);
70 static int ata_ahci_chipinit(device_t dev);
71 static int ata_ahci_allocate(device_t dev);
72 static int ata_ahci_status(device_t dev);
73 static int ata_ahci_begin_transaction(struct ata_request *request);
74 static int ata_ahci_end_transaction(struct ata_request *request);
75 static void ata_ahci_reset(device_t dev);
76 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
77 static void ata_ahci_dmainit(device_t dev);
78 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request);
79 static int ata_acard_chipinit(device_t dev);
80 static int ata_acard_allocate(device_t dev);
81 static int ata_acard_status(device_t dev);
82 static void ata_acard_850_setmode(device_t dev, int mode);
83 static void ata_acard_86X_setmode(device_t dev, int mode);
84 static int ata_ali_chipinit(device_t dev);
85 static int ata_ali_allocate(device_t dev);
86 static int ata_ali_sata_allocate(device_t dev);
87 static void ata_ali_reset(device_t dev);
88 static void ata_ali_setmode(device_t dev, int mode);
89 static int ata_amd_chipinit(device_t dev);
90 static int ata_ati_chipinit(device_t dev);
91 static void ata_ati_setmode(device_t dev, int mode);
92 static int ata_cyrix_chipinit(device_t dev);
93 static void ata_cyrix_setmode(device_t dev, int mode);
94 static int ata_cypress_chipinit(device_t dev);
95 static void ata_cypress_setmode(device_t dev, int mode);
96 static int ata_highpoint_chipinit(device_t dev);
97 static int ata_highpoint_allocate(device_t dev);
98 static void ata_highpoint_setmode(device_t dev, int mode);
99 static int ata_highpoint_check_80pin(device_t dev, int mode);
100 static int ata_intel_chipinit(device_t dev);
101 static int ata_intel_allocate(device_t dev);
102 static void ata_intel_reset(device_t dev);
103 static void ata_intel_old_setmode(device_t dev, int mode);
104 static void ata_intel_new_setmode(device_t dev, int mode);
105 static void ata_intel_sata_setmode(device_t dev, int mode);
106 static int ata_intel_31244_allocate(device_t dev);
107 static int ata_intel_31244_status(device_t dev);
108 static void ata_intel_31244_tf_write(struct ata_request *request);
109 static void ata_intel_31244_reset(device_t dev);
110 static int ata_ite_chipinit(device_t dev);
111 static void ata_ite_8213_setmode(device_t dev, int mode);
112 static void ata_ite_821x_setmode(device_t dev, int mode);
113 static int ata_jmicron_chipinit(device_t dev);
114 static int ata_jmicron_allocate(device_t dev);
115 static void ata_jmicron_reset(device_t dev);
116 static void ata_jmicron_dmainit(device_t dev);
117 static void ata_jmicron_setmode(device_t dev, int mode);
118 static int ata_marvell_pata_chipinit(device_t dev);
119 static int ata_marvell_pata_allocate(device_t dev);
120 static void ata_marvell_pata_setmode(device_t dev, int mode);
121 static int ata_marvell_edma_chipinit(device_t dev);
122 static int ata_marvell_edma_allocate(device_t dev);
123 static int ata_marvell_edma_status(device_t dev);
124 static int ata_marvell_edma_begin_transaction(struct ata_request *request);
125 static int ata_marvell_edma_end_transaction(struct ata_request *request);
126 static void ata_marvell_edma_reset(device_t dev);
127 static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
128 static void ata_marvell_edma_dmainit(device_t dev);
129 static int ata_national_chipinit(device_t dev);
130 static void ata_national_setmode(device_t dev, int mode);
131 static int ata_netcell_chipinit(device_t dev);
132 static int ata_netcell_allocate(device_t dev);
133 static int ata_nvidia_chipinit(device_t dev);
134 static int ata_nvidia_allocate(device_t dev);
135 static int ata_nvidia_status(device_t dev);
136 static void ata_nvidia_reset(device_t dev);
137 static int ata_promise_chipinit(device_t dev);
138 static int ata_promise_allocate(device_t dev);
139 static int ata_promise_status(device_t dev);
140 static int ata_promise_dmastart(device_t dev);
141 static int ata_promise_dmastop(device_t dev);
142 static void ata_promise_dmareset(device_t dev);
143 static void ata_promise_dmainit(device_t dev);
144 static void ata_promise_setmode(device_t dev, int mode);
145 static int ata_promise_tx2_allocate(device_t dev);
146 static int ata_promise_tx2_status(device_t dev);
147 static int ata_promise_mio_allocate(device_t dev);
148 static void ata_promise_mio_intr(void *data);
149 static int ata_promise_mio_status(device_t dev);
150 static int ata_promise_mio_command(struct ata_request *request);
151 static void ata_promise_mio_reset(device_t dev);
152 static void ata_promise_mio_dmainit(device_t dev);
153 static void ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
154 static void ata_promise_mio_setmode(device_t dev, int mode);
155 static void ata_promise_sx4_intr(void *data);
156 static int ata_promise_sx4_command(struct ata_request *request);
157 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request);
158 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt);
159 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr);
160 static int ata_serverworks_chipinit(device_t dev);
161 static int ata_serverworks_allocate(device_t dev);
162 static void ata_serverworks_tf_read(struct ata_request *request);
163 static void ata_serverworks_tf_write(struct ata_request *request);
164 static void ata_serverworks_setmode(device_t dev, int mode);
165 static int ata_sii_chipinit(device_t dev);
166 static int ata_cmd_allocate(device_t dev);
167 static int ata_cmd_status(device_t dev);
168 static void ata_cmd_setmode(device_t dev, int mode);
169 static int ata_sii_allocate(device_t dev);
170 static int ata_sii_status(device_t dev);
171 static void ata_sii_reset(device_t dev);
172 static void ata_sii_setmode(device_t dev, int mode);
173 static int ata_siiprb_allocate(device_t dev);
174 static int ata_siiprb_status(device_t dev);
175 static int ata_siiprb_begin_transaction(struct ata_request *request);
176 static int ata_siiprb_end_transaction(struct ata_request *request);
177 static void ata_siiprb_reset(device_t dev);
178 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
179 static void ata_siiprb_dmainit(device_t dev);
180 static int ata_sis_chipinit(device_t dev);
181 static int ata_sis_allocate(device_t dev);
182 static void ata_sis_reset(device_t dev);
183 static void ata_sis_setmode(device_t dev, int mode);
184 static int ata_via_chipinit(device_t dev);
185 static int ata_via_allocate(device_t dev);
186 static void ata_via_reset(device_t dev);
187 static void ata_via_setmode(device_t dev, int mode);
188 static void ata_via_southbridge_fixup(device_t dev);
189 static void ata_via_family_setmode(device_t dev, int mode);
190 static void ata_set_desc(device_t dev);
191 static struct ata_chip_id *ata_match_chip(device_t dev, struct ata_chip_id *index);
192 static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot);
193 static int ata_setup_interrupt(device_t dev);
194 static int ata_serialize(device_t dev, int flags);
195 static void ata_serialize_init(struct ata_serialize *serial);
196 static void ata_print_cable(device_t dev, u_int8_t *who);
197 static int ata_atapi(device_t dev);
198 static int ata_check_80pin(device_t dev, int mode);
199 static int ata_mode2idx(int mode);
200
201 struct ali_sata_resources {
202 struct resource *bars[4];
203 };
204
205 /*
206 * generic ATA support functions
207 */
208 int
209 ata_generic_ident(device_t dev)
210 {
211 struct ata_pci_controller *ctlr = device_get_softc(dev);
212 char buffer[64];
213
214 sprintf(buffer, "%s ATA controller", ata_pcivendor2str(dev));
215 device_set_desc_copy(dev, buffer);
216 ctlr->chipinit = ata_generic_chipinit;
217 return 0;
218 }
219
220 static int
221 ata_generic_chipinit(device_t dev)
222 {
223 struct ata_pci_controller *ctlr = device_get_softc(dev);
224
225 if (ata_setup_interrupt(dev))
226 return ENXIO;
227 ctlr->setmode = ata_generic_setmode;
228 return 0;
229 }
230
231 static void
232 ata_generic_intr(void *data)
233 {
234 struct ata_pci_controller *ctlr = data;
235 struct ata_channel *ch;
236 int unit;
237
238 for (unit = 0; unit < ctlr->channels; unit++) {
239 if ((ch = ctlr->interrupt[unit].argument))
240 ctlr->interrupt[unit].function(ch);
241 }
242 }
243
244 static void
245 ata_generic_setmode(device_t dev, int mode)
246 {
247 struct ata_device *atadev = device_get_softc(dev);
248
249 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
250 mode = ata_check_80pin(dev, mode);
251 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
252 atadev->mode = mode;
253 }
254
255
256 /*
257 * SATA support functions
258 */
259 static void
260 ata_sata_phy_check_events(device_t dev)
261 {
262 struct ata_channel *ch = device_get_softc(dev);
263 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR);
264
265 /* clear error bits/interrupt */
266 ATA_IDX_OUTL(ch, ATA_SERROR, error);
267
268 /* do we have any events flagged ? */
269 if (error) {
270 struct ata_connect_task *tp;
271 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS);
272
273 /* if we have a connection event deal with it */
274 if ((error & ATA_SE_PHY_CHANGED) &&
275 (tp = (struct ata_connect_task *)
276 malloc(sizeof(struct ata_connect_task),
277 M_ATA, M_NOWAIT | M_ZERO))) {
278
279 if (((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) ||
280 ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)) {
281 if (bootverbose)
282 device_printf(ch->dev, "CONNECT requested\n");
283 tp->action = ATA_C_ATTACH;
284 }
285 else {
286 if (bootverbose)
287 device_printf(ch->dev, "DISCONNECT requested\n");
288 tp->action = ATA_C_DETACH;
289 }
290 tp->dev = ch->dev;
291 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
292 taskqueue_enqueue(taskqueue_thread, &tp->task);
293 }
294 }
295 }
296
297 static void
298 ata_sata_phy_event(void *context, int dummy)
299 {
300 struct ata_connect_task *tp = (struct ata_connect_task *)context;
301 struct ata_channel *ch = device_get_softc(tp->dev);
302 device_t *children;
303 int nchildren, i;
304
305 mtx_lock(&Giant); /* newbus suckage it needs Giant */
306 if (tp->action == ATA_C_ATTACH) {
307 if (bootverbose)
308 device_printf(tp->dev, "CONNECTED\n");
309 ATA_RESET(tp->dev);
310 ata_identify(tp->dev);
311 }
312 if (tp->action == ATA_C_DETACH) {
313 if (!device_get_children(tp->dev, &children, &nchildren)) {
314 for (i = 0; i < nchildren; i++)
315 if (children[i])
316 device_delete_child(tp->dev, children[i]);
317 free(children, M_TEMP);
318 }
319 mtx_lock(&ch->state_mtx);
320 ch->state = ATA_IDLE;
321 mtx_unlock(&ch->state_mtx);
322 if (bootverbose)
323 device_printf(tp->dev, "DISCONNECTED\n");
324 }
325 mtx_unlock(&Giant); /* suckage code dealt with, release Giant */
326 free(tp, M_ATA);
327 }
328
329 static int
330 ata_sata_phy_reset(device_t dev)
331 {
332 struct ata_channel *ch = device_get_softc(dev);
333 int loop, retry;
334
335 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE)
336 return ata_sata_connect(ch);
337
338 for (retry = 0; retry < 10; retry++) {
339 for (loop = 0; loop < 10; loop++) {
340 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET);
341 ata_udelay(100);
342 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) ==
343 ATA_SC_DET_RESET)
344 break;
345 }
346 ata_udelay(5000);
347 for (loop = 0; loop < 10; loop++) {
348 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_IDLE |
349 ATA_SC_IPM_DIS_PARTIAL |
350 ATA_SC_IPM_DIS_SLUMBER);
351 ata_udelay(100);
352 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 0)
353 return ata_sata_connect(ch);
354 }
355 }
356 return 0;
357 }
358
359 static int
360 ata_sata_connect(struct ata_channel *ch)
361 {
362 u_int32_t status;
363 int timeout;
364
365 /* wait up to 1 second for "connect well" */
366 for (timeout = 0; timeout < 100 ; timeout++) {
367 status = ATA_IDX_INL(ch, ATA_SSTATUS);
368 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 ||
369 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)
370 break;
371 ata_udelay(10000);
372 }
373 if (timeout >= 100) {
374 if (bootverbose)
375 device_printf(ch->dev, "SATA connect status=%08x\n", status);
376 return 0;
377 }
378 if (bootverbose)
379 device_printf(ch->dev, "SATA connect time=%dms\n", timeout * 10);
380
381 /* clear SATA error register */
382 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
383
384 return 1;
385 }
386
387 static void
388 ata_sata_setmode(device_t dev, int mode)
389 {
390 struct ata_device *atadev = device_get_softc(dev);
391
392 /*
393 * if we detect that the device isn't a real SATA device we limit
394 * the transfer mode to UDMA5/ATA100.
395 * this works around the problems some devices has with the
396 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133.
397 */
398 if (atadev->param.satacapabilities != 0x0000 &&
399 atadev->param.satacapabilities != 0xffff) {
400 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
401
402 /* on some drives we need to set the transfer mode */
403 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
404 ata_limit_mode(dev, mode, ATA_UDMA6));
405
406 /* query SATA STATUS for the speed */
407 if (ch->r_io[ATA_SSTATUS].res &&
408 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) ==
409 ATA_SS_CONWELL_GEN2))
410 atadev->mode = ATA_SA300;
411 else
412 atadev->mode = ATA_SA150;
413 }
414 else {
415 mode = ata_limit_mode(dev, mode, ATA_UDMA5);
416 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
417 atadev->mode = mode;
418 }
419 }
420
421 static int
422 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis)
423 {
424 struct ata_device *atadev = device_get_softc(request->dev);
425
426 if (request->flags & ATA_R_ATAPI) {
427 fis[0] = 0x27; /* host to device */
428 fis[1] = 0x80; /* command FIS (note PM goes here) */
429 fis[2] = ATA_PACKET_CMD;
430 if (request->flags & (ATA_R_READ | ATA_R_WRITE))
431 fis[3] = ATA_F_DMA;
432 else {
433 fis[5] = request->transfersize;
434 fis[6] = request->transfersize >> 8;
435 }
436 fis[7] = ATA_D_LBA | atadev->unit;
437 fis[15] = ATA_A_4BIT;
438 return 20;
439 }
440 else {
441 ata_modify_if_48bit(request);
442 fis[0] = 0x27; /* host to device */
443 fis[1] = 0x80; /* command FIS (note PM goes here) */
444 fis[2] = request->u.ata.command;
445 fis[3] = request->u.ata.feature;
446 fis[4] = request->u.ata.lba;
447 fis[5] = request->u.ata.lba >> 8;
448 fis[6] = request->u.ata.lba >> 16;
449 fis[7] = ATA_D_LBA | atadev->unit;
450 if (!(atadev->flags & ATA_D_48BIT_ACTIVE))
451 fis[7] |= (request->u.ata.lba >> 24 & 0x0f);
452 fis[8] = request->u.ata.lba >> 24;
453 fis[9] = request->u.ata.lba >> 32;
454 fis[10] = request->u.ata.lba >> 40;
455 fis[11] = request->u.ata.feature >> 8;
456 fis[12] = request->u.ata.count;
457 fis[13] = request->u.ata.count >> 8;
458 fis[15] = ATA_A_4BIT;
459 return 20;
460 }
461 return 0;
462 }
463
464
465 /*
466 * AHCI v1.x compliant SATA chipset support functions
467 */
468 int
469 ata_ahci_ident(device_t dev)
470 {
471 struct ata_pci_controller *ctlr = device_get_softc(dev);
472 char buffer[64];
473
474 /* is this PCI device flagged as an AHCI compliant chip ? */
475 if (pci_read_config(dev, PCIR_PROGIF, 1) != PCIP_STORAGE_SATA_AHCI_1_0)
476 return ENXIO;
477
478 if (bootverbose)
479 sprintf(buffer, "%s (ID=%08x) AHCI controller",
480 ata_pcivendor2str(dev), pci_get_devid(dev));
481 else
482 sprintf(buffer, "%s AHCI controller", ata_pcivendor2str(dev));
483 device_set_desc_copy(dev, buffer);
484 ctlr->chipinit = ata_ahci_chipinit;
485 return 0;
486 }
487
488 static int
489 ata_ahci_chipinit(device_t dev)
490 {
491 struct ata_pci_controller *ctlr = device_get_softc(dev);
492 u_int32_t version;
493
494 /* if we have a memory BAR(5) we are likely on an AHCI part */
495 ctlr->r_type2 = SYS_RES_MEMORY;
496 ctlr->r_rid2 = PCIR_BAR(5);
497 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
498 &ctlr->r_rid2, RF_ACTIVE)))
499 return ENXIO;
500
501 /* setup interrupt delivery if not done allready by a vendor driver */
502 if (!ctlr->r_irq) {
503 if (ata_setup_interrupt(dev))
504 return ENXIO;
505 }
506 else
507 device_printf(dev, "AHCI called from vendor specific driver\n");
508
509 /* enable AHCI mode */
510 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
511
512 /* reset AHCI controller */
513 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_HR);
514 DELAY(1000000);
515 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) {
516 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
517 device_printf(dev, "AHCI controller reset failure\n");
518 return ENXIO;
519 }
520
521 /* reenable AHCI mode */
522 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
523
524 /* get the number of HW channels */
525 ctlr->channels =
526 MAX(flsl(ATA_INL(ctlr->r_res2, ATA_AHCI_PI)),
527 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
528
529 /* clear interrupts */
530 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS));
531
532 /* enable AHCI interrupts */
533 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
534 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE);
535
536 ctlr->reset = ata_ahci_reset;
537 ctlr->dmainit = ata_ahci_dmainit;
538 ctlr->allocate = ata_ahci_allocate;
539 ctlr->setmode = ata_sata_setmode;
540
541 /* announce we support the HW */
542 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS);
543 device_printf(dev,
544 "AHCI Version %x%x.%x%x controller with %d ports detected\n",
545 (version >> 24) & 0xff, (version >> 16) & 0xff,
546 (version >> 8) & 0xff, version & 0xff,
547 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
548 return 0;
549 }
550
551 static int
552 ata_ahci_allocate(device_t dev)
553 {
554 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
555 struct ata_channel *ch = device_get_softc(dev);
556 u_int64_t work;
557 int offset = ch->unit << 7;
558
559 /* set the SATA resources */
560 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
561 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset;
562 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
563 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset;
564 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
565 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset;
566 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
567 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset;
568
569 ch->hw.status = ata_ahci_status;
570 ch->hw.begin_transaction = ata_ahci_begin_transaction;
571 ch->hw.end_transaction = ata_ahci_end_transaction;
572 ch->hw.command = NULL; /* not used here */
573
574 /* setup work areas */
575 work = ch->dma->work_bus + ATA_AHCI_CL_OFFSET;
576 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff);
577 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32);
578
579 work = ch->dma->work_bus + ATA_AHCI_FB_OFFSET;
580 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff);
581 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32);
582
583 /* enable wanted port interrupts */
584 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
585 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
586 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
587 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP |
588 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS |
589 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR));
590
591 /* start operations on this channel */
592 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
593 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
594 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
595 return 0;
596 }
597
598 static int
599 ata_ahci_status(device_t dev)
600 {
601 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
602 struct ata_channel *ch = device_get_softc(dev);
603 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS);
604 int offset = ch->unit << 7;
605 int tag = 0;
606
607 if (action & (1 << ch->unit)) {
608 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset);
609 u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset);
610
611 /* clear interrupt(s) */
612 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action & (1 << ch->unit));
613 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus);
614
615 /* do we have any PHY events ? */
616 /* XXX SOS check istatus phy bits */
617 ata_sata_phy_check_events(dev);
618
619 /* do we have a potentially hanging engine to take care of? */
620 if ((istatus & 0x78400050) && (cstatus & (1 << tag))) {
621
622 u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
623 int timeout = 0;
624
625 /* kill off all activity on this channel */
626 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
627 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
628
629 /* XXX SOS this is not entirely wrong */
630 do {
631 DELAY(1000);
632 if (timeout++ > 500) {
633 device_printf(dev, "stopping AHCI engine failed\n");
634 break;
635 }
636 } while (ATA_INL(ctlr->r_res2,
637 ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
638
639 /* start operations on this channel */
640 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
641 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
642
643 return 1;
644 }
645 else
646 return (!(cstatus & (1 << tag)));
647 }
648 return 0;
649 }
650
651 /* must be called with ATA channel locked and state_mtx held */
652 static int
653 ata_ahci_begin_transaction(struct ata_request *request)
654 {
655 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
656 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
657 struct ata_ahci_cmd_tab *ctp;
658 struct ata_ahci_cmd_list *clp;
659 int offset = ch->unit << 7;
660 int tag = 0, entries = 0;
661 int fis_size;
662
663 /* get a piece of the workspace for this request */
664 ctp = (struct ata_ahci_cmd_tab *)
665 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag));
666
667 /* setup the FIS for this request */
668 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) {
669 device_printf(request->dev, "setting up SATA FIS failed\n");
670 request->result = EIO;
671 return ATA_OP_FINISHED;
672 }
673
674 /* if request moves data setup and load SG list */
675 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
676 if (ch->dma->load(ch->dev, request->data, request->bytecount,
677 request->flags & ATA_R_READ,
678 ctp->prd_tab, &entries)) {
679 device_printf(request->dev, "setting up DMA failed\n");
680 request->result = EIO;
681 return ATA_OP_FINISHED;
682 }
683 }
684
685 /* setup the command list entry */
686 clp = (struct ata_ahci_cmd_list *)
687 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
688
689 clp->prd_length = entries;
690 clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) |
691 (request->flags & ATA_R_ATAPI ? ((1<<5) | (1<<7)) : 0) |
692 (fis_size / sizeof(u_int32_t));
693 clp->bytecount = 0;
694 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET +
695 (ATA_AHCI_CT_SIZE * tag));
696
697 /* clear eventual ACTIVE bit */
698 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag));
699
700 /* set command type bit */
701 if (request->flags & ATA_R_ATAPI)
702 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
703 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) |
704 ATA_AHCI_P_CMD_ATAPI);
705 else
706 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
707 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) &
708 ~ATA_AHCI_P_CMD_ATAPI);
709
710 /* issue command to controller */
711 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << tag));
712
713 if (!(request->flags & ATA_R_ATAPI)) {
714 /* device reset doesn't interrupt */
715 if (request->u.ata.command == ATA_DEVICE_RESET) {
716 u_int32_t tf_data;
717 int timeout = 1000000;
718
719 do {
720 DELAY(10);
721 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7));
722 } while ((tf_data & ATA_S_BUSY) && timeout--);
723 if (bootverbose)
724 device_printf(ch->dev, "device_reset timeout=%dus\n",
725 (1000000-timeout)*10);
726 request->status = tf_data;
727 if (request->status & ATA_S_ERROR)
728 request->error = tf_data >> 8;
729 return ATA_OP_FINISHED;
730 }
731 }
732
733 /* start the timeout */
734 callout_reset(&request->callout, request->timeout * hz,
735 (timeout_t*)ata_timeout, request);
736 return ATA_OP_CONTINUES;
737 }
738
739 /* must be called with ATA channel locked and state_mtx held */
740 static int
741 ata_ahci_end_transaction(struct ata_request *request)
742 {
743 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
744 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
745 struct ata_ahci_cmd_list *clp;
746 u_int32_t tf_data;
747 int offset = ch->unit << 7;
748 int tag = 0;
749
750 /* kill the timeout */
751 callout_stop(&request->callout);
752
753 /* get status */
754 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset);
755 request->status = tf_data;
756
757 /* if error status get details */
758 if (request->status & ATA_S_ERROR)
759 request->error = tf_data >> 8;
760
761 /* record how much data we actually moved */
762 clp = (struct ata_ahci_cmd_list *)
763 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
764 request->donecount = clp->bytecount;
765
766 /* release SG list etc */
767 ch->dma->unload(ch->dev);
768
769 return ATA_OP_FINISHED;
770 }
771
772 static void
773 ata_ahci_reset(device_t dev)
774 {
775 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
776 struct ata_channel *ch = device_get_softc(dev);
777 u_int32_t cmd, signature;
778 int offset = ch->unit << 7;
779 int timeout;
780
781 if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) {
782 device_printf(dev, "port not implemented\n");
783 return;
784 }
785 ch->devices = 0;
786
787 /* kill off all activity on this channel */
788 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
789 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
790 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
791
792 /* XXX SOS this is not entirely wrong */
793 timeout = 0;
794 do {
795 DELAY(1000);
796 if (timeout++ > 500) {
797 device_printf(dev, "stopping AHCI engine failed\n");
798 break;
799 }
800 }
801 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
802
803 /* issue Command List Override if supported */
804 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) {
805 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
806 cmd |= ATA_AHCI_P_CMD_CLO;
807 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd);
808 timeout = 0;
809 do {
810 DELAY(1000);
811 if (timeout++ > 500) {
812 device_printf(dev, "executing CLO failed\n");
813 break;
814 }
815 }
816 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO);
817 }
818
819 /* reset PHY and decide what is present */
820 if (ata_sata_phy_reset(dev)) {
821
822 /* clear any interrupts pending on this channel */
823 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
824 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
825
826 /* clear SATA error register */
827 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
828
829 /* start operations on this channel */
830 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
831 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
832 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
833
834 signature = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset);
835 if (bootverbose)
836 device_printf(dev, "SIGNATURE: %08x\n", signature);
837 switch (signature) {
838 case 0x00000101:
839 ch->devices = ATA_ATA_MASTER;
840 break;
841 case 0x96690101:
842 ch->devices = ATA_PORTMULTIPLIER;
843 device_printf(ch->dev, "Portmultipliers not supported yet\n");
844 ch->devices = 0;
845 break;
846 case 0xeb140101:
847 ch->devices = ATA_ATAPI_MASTER;
848 break;
849 default: /* SOS XXX */
850 if (bootverbose)
851 device_printf(ch->dev, "No signature, asuming disk device\n");
852 ch->devices = ATA_ATA_MASTER;
853 }
854 }
855 if (bootverbose)
856 device_printf(dev, "ahci_reset devices=0x%b\n", ch->devices,
857 "\2\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
858 }
859
860 static void
861 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
862 {
863 struct ata_dmasetprd_args *args = xsc;
864 struct ata_ahci_dma_prd *prd = args->dmatab;
865 int i;
866
867 if (!(args->error = error)) {
868 for (i = 0; i < nsegs; i++) {
869 prd[i].dba = htole64(segs[i].ds_addr);
870 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK);
871 }
872 }
873 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
874 args->nsegs = nsegs;
875 }
876
877 static void
878 ata_ahci_dmainit(device_t dev)
879 {
880 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
881 struct ata_channel *ch = device_get_softc(dev);
882
883 ata_dmainit(dev);
884 if (ch->dma) {
885 /* note start and stop are not used here */
886 ch->dma->setprd = ata_ahci_dmasetprd;
887 ch->dma->max_iosize = 8192 * DEV_BSIZE;
888 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT)
889 ch->dma->max_address = BUS_SPACE_MAXADDR;
890 }
891 }
892
893 static int
894 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request)
895 {
896 bzero(ctp->cfis, 64);
897 if (request->flags & ATA_R_ATAPI) {
898 bzero(ctp->acmd, 32);
899 bcopy(request->u.atapi.ccb, ctp->acmd, 16);
900 }
901 return ata_request2fis_h2d(request, &ctp->cfis[0]);
902 }
903
904
905 /*
906 * Acard chipset support functions
907 */
908 int
909 ata_acard_ident(device_t dev)
910 {
911 struct ata_pci_controller *ctlr = device_get_softc(dev);
912 static struct ata_chip_id ids[] =
913 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "ATP850" },
914 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "ATP860A" },
915 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "ATP860R" },
916 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "ATP865A" },
917 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "ATP865R" },
918 { 0, 0, 0, 0, 0, 0}};
919
920 if (!(ctlr->chip = ata_match_chip(dev, ids)))
921 return ENXIO;
922
923 ata_set_desc(dev);
924 ctlr->chipinit = ata_acard_chipinit;
925 return 0;
926 }
927
928 static int
929 ata_acard_chipinit(device_t dev)
930 {
931 struct ata_pci_controller *ctlr = device_get_softc(dev);
932 struct ata_serialize *serial;
933
934 if (ata_setup_interrupt(dev))
935 return ENXIO;
936
937 ctlr->allocate = ata_acard_allocate;
938 if (ctlr->chip->cfg1 == ATPOLD) {
939 ctlr->setmode = ata_acard_850_setmode;
940 ctlr->locking = ata_serialize;
941 serial = malloc(sizeof(struct ata_serialize),
942 M_TEMP, M_WAITOK | M_ZERO);
943 ata_serialize_init(serial);
944 ctlr->chipset_data = serial;
945 }
946 else
947 ctlr->setmode = ata_acard_86X_setmode;
948 return 0;
949 }
950
951 static int
952 ata_acard_allocate(device_t dev)
953 {
954 struct ata_channel *ch = device_get_softc(dev);
955
956 /* setup the usual register normal pci style */
957 if (ata_pci_allocate(dev))
958 return ENXIO;
959
960 ch->hw.status = ata_acard_status;
961 return 0;
962 }
963
964 static int
965 ata_acard_status(device_t dev)
966 {
967 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
968 struct ata_channel *ch = device_get_softc(dev);
969
970 if (ctlr->chip->cfg1 == ATPOLD &&
971 ATA_LOCKING(ch->dev, ATA_LF_WHICH) != ch->unit)
972 return 0;
973 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
974 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
975
976 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
977 ATA_BMSTAT_INTERRUPT)
978 return 0;
979 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
980 DELAY(1);
981 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
982 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
983 DELAY(1);
984 }
985 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
986 DELAY(100);
987 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
988 return 0;
989 }
990 return 1;
991 }
992
993 static void
994 ata_acard_850_setmode(device_t dev, int mode)
995 {
996 device_t gparent = GRANDPARENT(dev);
997 struct ata_pci_controller *ctlr = device_get_softc(gparent);
998 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
999 struct ata_device *atadev = device_get_softc(dev);
1000 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1001 int error;
1002
1003 mode = ata_limit_mode(dev, mode,
1004 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
1005
1006 /* XXX SOS missing WDMA0+1 + PIO modes */
1007 if (mode >= ATA_WDMA2) {
1008 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1009 if (bootverbose)
1010 device_printf(dev, "%ssetting %s on %s chip\n",
1011 (error) ? "FAILURE " : "",
1012 ata_mode2str(mode), ctlr->chip->text);
1013 if (!error) {
1014 u_int8_t reg54 = pci_read_config(gparent, 0x54, 1);
1015
1016 reg54 &= ~(0x03 << (devno << 1));
1017 if (mode >= ATA_UDMA0)
1018 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1));
1019 pci_write_config(gparent, 0x54, reg54, 1);
1020 pci_write_config(gparent, 0x4a, 0xa6, 1);
1021 pci_write_config(gparent, 0x40 + (devno << 1), 0x0301, 2);
1022 atadev->mode = mode;
1023 return;
1024 }
1025 }
1026 /* we could set PIO mode timings, but we assume the BIOS did that */
1027 }
1028
1029 static void
1030 ata_acard_86X_setmode(device_t dev, int mode)
1031 {
1032 device_t gparent = GRANDPARENT(dev);
1033 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1034 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1035 struct ata_device *atadev = device_get_softc(dev);
1036 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1037 int error;
1038
1039
1040 mode = ata_limit_mode(dev, mode,
1041 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
1042
1043 mode = ata_check_80pin(dev, mode);
1044
1045 /* XXX SOS missing WDMA0+1 + PIO modes */
1046 if (mode >= ATA_WDMA2) {
1047 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1048 if (bootverbose)
1049 device_printf(dev, "%ssetting %s on %s chip\n",
1050 (error) ? "FAILURE " : "",
1051 ata_mode2str(mode), ctlr->chip->text);
1052 if (!error) {
1053 u_int16_t reg44 = pci_read_config(gparent, 0x44, 2);
1054
1055 reg44 &= ~(0x000f << (devno << 2));
1056 if (mode >= ATA_UDMA0)
1057 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2));
1058 pci_write_config(gparent, 0x44, reg44, 2);
1059 pci_write_config(gparent, 0x4a, 0xa6, 1);
1060 pci_write_config(gparent, 0x40 + devno, 0x31, 1);
1061 atadev->mode = mode;
1062 return;
1063 }
1064 }
1065 /* we could set PIO mode timings, but we assume the BIOS did that */
1066 }
1067
1068
1069 /*
1070 * Acer Labs Inc (ALI) chipset support functions
1071 */
1072 int
1073 ata_ali_ident(device_t dev)
1074 {
1075 struct ata_pci_controller *ctlr = device_get_softc(dev);
1076 static struct ata_chip_id ids[] =
1077 {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" },
1078 { ATA_ALI_5288, 0x00, 4, ALISATA, ATA_SA300, "M5288" },
1079 { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "M5287" },
1080 { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "M5281" },
1081 { ATA_ALI_5229, 0xc5, 0, ALINEW, ATA_UDMA6, "M5229" },
1082 { ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "M5229" },
1083 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "M5229" },
1084 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "M5229" },
1085 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "M5229" },
1086 { 0, 0, 0, 0, 0, 0}};
1087
1088 if (!(ctlr->chip = ata_match_chip(dev, ids)))
1089 return ENXIO;
1090
1091 ata_set_desc(dev);
1092 ctlr->chipinit = ata_ali_chipinit;
1093 return 0;
1094 }
1095
1096 static int
1097 ata_ali_chipinit(device_t dev)
1098 {
1099 struct ata_pci_controller *ctlr = device_get_softc(dev);
1100 struct ali_sata_resources *res;
1101 int i, rid;
1102
1103 if (ata_setup_interrupt(dev))
1104 return ENXIO;
1105
1106 switch (ctlr->chip->cfg2) {
1107 case ALISATA:
1108 ctlr->channels = ctlr->chip->cfg1;
1109 ctlr->allocate = ata_ali_sata_allocate;
1110 ctlr->setmode = ata_sata_setmode;
1111
1112 /* AHCI mode is correctly supported only on the ALi 5288. */
1113 if ((ctlr->chip->chipid == ATA_ALI_5288) &&
1114 (ata_ahci_chipinit(dev) != ENXIO))
1115 return 0;
1116
1117 /* Allocate resources for later use by channel attach routines. */
1118 res = malloc(sizeof(struct ali_sata_resources), M_TEMP, M_WAITOK);
1119 for (i = 0; i < 4; i++) {
1120 rid = PCIR_BAR(i);
1121 res->bars[i] = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1122 RF_ACTIVE);
1123 if (res->bars[i] == NULL) {
1124 device_printf(dev, "Failed to allocate BAR %d\n", i);
1125 for (i--; i >=0; i--)
1126 bus_release_resource(dev, SYS_RES_IOPORT,
1127 PCIR_BAR(i), res->bars[i]);
1128 free(res, M_TEMP);
1129 }
1130 }
1131 ctlr->chipset_data = res;
1132 break;
1133
1134 case ALINEW:
1135 /* use device interrupt as byte count end */
1136 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
1137
1138 /* enable cable detection and UDMA support on newer chips */
1139 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1);
1140
1141 /* enable ATAPI UDMA mode */
1142 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1);
1143
1144 /* only chips with revision > 0xc4 can do 48bit DMA */
1145 if (ctlr->chip->chiprev <= 0xc4)
1146 device_printf(dev,
1147 "using PIO transfers above 137GB as workaround for "
1148 "48bit DMA access bug, expect reduced performance\n");
1149 ctlr->allocate = ata_ali_allocate;
1150 ctlr->reset = ata_ali_reset;
1151 ctlr->setmode = ata_ali_setmode;
1152 break;
1153
1154 case ALIOLD:
1155 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
1156 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
1157 ctlr->setmode = ata_ali_setmode;
1158 break;
1159 }
1160 return 0;
1161 }
1162
1163 static int
1164 ata_ali_allocate(device_t dev)
1165 {
1166 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1167 struct ata_channel *ch = device_get_softc(dev);
1168
1169 /* setup the usual register normal pci style */
1170 if (ata_pci_allocate(dev))
1171 return ENXIO;
1172
1173 /* older chips can't do 48bit DMA transfers */
1174 if (ctlr->chip->chiprev <= 0xc4)
1175 ch->flags |= ATA_NO_48BIT_DMA;
1176
1177 return 0;
1178 }
1179
1180 static int
1181 ata_ali_sata_allocate(device_t dev)
1182 {
1183 device_t parent = device_get_parent(dev);
1184 struct ata_pci_controller *ctlr = device_get_softc(parent);
1185 struct ata_channel *ch = device_get_softc(dev);
1186 struct ali_sata_resources *res;
1187 struct resource *io = NULL, *ctlio = NULL;
1188 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
1189 int i;
1190
1191 res = ctlr->chipset_data;
1192 if (unit01) {
1193 io = res->bars[2];
1194 ctlio = res->bars[3];
1195 } else {
1196 io = res->bars[0];
1197 ctlio = res->bars[1];
1198 }
1199
1200 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
1201 ch->r_io[i].res = io;
1202 ch->r_io[i].offset = i + (unit10 ? 8 : 0);
1203 }
1204 ch->r_io[ATA_CONTROL].res = ctlio;
1205 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0);
1206 ch->r_io[ATA_IDX_ADDR].res = io;
1207 ata_default_registers(dev);
1208 if (ctlr->r_res1) {
1209 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
1210 ch->r_io[i].res = ctlr->r_res1;
1211 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
1212 }
1213 }
1214 ch->flags |= ATA_NO_SLAVE;
1215
1216 /* XXX SOS PHY handling awkward in ALI chip not supported yet */
1217 ata_pci_hw(dev);
1218 return 0;
1219 }
1220
1221 static void
1222 ata_ali_reset(device_t dev)
1223 {
1224 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1225 struct ata_channel *ch = device_get_softc(dev);
1226 device_t *children;
1227 int nchildren, i;
1228
1229 ata_generic_reset(dev);
1230
1231 /*
1232 * workaround for datacorruption bug found on at least SUN Blade-100
1233 * find the ISA function on the southbridge and disable then enable
1234 * the ATA channel tristate buffer
1235 */
1236 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) {
1237 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) {
1238 for (i = 0; i < nchildren; i++) {
1239 if (pci_get_devid(children[i]) == ATA_ALI_1533) {
1240 pci_write_config(children[i], 0x58,
1241 pci_read_config(children[i], 0x58, 1) &
1242 ~(0x04 << ch->unit), 1);
1243 pci_write_config(children[i], 0x58,
1244 pci_read_config(children[i], 0x58, 1) |
1245 (0x04 << ch->unit), 1);
1246 break;
1247 }
1248 }
1249 free(children, M_TEMP);
1250 }
1251 }
1252 }
1253
1254 static void
1255 ata_ali_setmode(device_t dev, int mode)
1256 {
1257 device_t gparent = GRANDPARENT(dev);
1258 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1259 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1260 struct ata_device *atadev = device_get_softc(dev);
1261 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1262 int error;
1263
1264 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1265
1266 if (ctlr->chip->cfg2 & ALINEW) {
1267 if (mode > ATA_UDMA2 &&
1268 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) {
1269 ata_print_cable(dev, "controller");
1270 mode = ATA_UDMA2;
1271 }
1272 }
1273 else
1274 mode = ata_check_80pin(dev, mode);
1275
1276 if (ctlr->chip->cfg2 & ALIOLD) {
1277 /* doesn't support ATAPI DMA on write */
1278 ch->flags |= ATA_ATAPI_DMA_RO;
1279 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) {
1280 /* doesn't support ATAPI DMA on two ATAPI devices */
1281 device_printf(dev, "two atapi devices on this channel, no DMA\n");
1282 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1283 }
1284 }
1285
1286 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1287
1288 if (bootverbose)
1289 device_printf(dev, "%ssetting %s on %s chip\n",
1290 (error) ? "FAILURE " : "",
1291 ata_mode2str(mode), ctlr->chip->text);
1292 if (!error) {
1293 if (mode >= ATA_UDMA0) {
1294 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d};
1295 u_int32_t word54 = pci_read_config(gparent, 0x54, 4);
1296
1297 word54 &= ~(0x000f000f << (devno << 2));
1298 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
1299 pci_write_config(gparent, 0x54, word54, 4);
1300 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1301 0x00310001, 4);
1302 }
1303 else {
1304 u_int32_t piotimings[] =
1305 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
1306 0x00310001, 0x00440001, 0x00330001, 0x00310001};
1307
1308 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) &
1309 ~(0x0008000f << (devno << 2)), 4);
1310 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1311 piotimings[ata_mode2idx(mode)], 4);
1312 }
1313 atadev->mode = mode;
1314 }
1315 }
1316
1317
1318 /*
1319 * American Micro Devices (AMD) chipset support functions
1320 */
1321 int
1322 ata_amd_ident(device_t dev)
1323 {
1324 struct ata_pci_controller *ctlr = device_get_softc(dev);
1325 static struct ata_chip_id ids[] =
1326 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "756" },
1327 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "766" },
1328 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "768" },
1329 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "8111" },
1330 { ATA_AMD5536, 0x00, AMDNVIDIA, 0x00, ATA_UDMA5, "CS5536" },
1331 { 0, 0, 0, 0, 0, 0}};
1332
1333 if (!(ctlr->chip = ata_match_chip(dev, ids)))
1334 return ENXIO;
1335
1336 ata_set_desc(dev);
1337 ctlr->chipinit = ata_amd_chipinit;
1338 return 0;
1339 }
1340
1341 static int
1342 ata_amd_chipinit(device_t dev)
1343 {
1344 struct ata_pci_controller *ctlr = device_get_softc(dev);
1345
1346 if (ata_setup_interrupt(dev))
1347 return ENXIO;
1348
1349 /* disable/set prefetch, postwrite */
1350 if (ctlr->chip->cfg2 & AMDBUG)
1351 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1);
1352 else
1353 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
1354
1355 ctlr->setmode = ata_via_family_setmode;
1356 return 0;
1357 }
1358
1359
1360 /*
1361 * Adaptec chipset support functions
1362 */
1363 int
1364 ata_adaptec_ident(device_t dev)
1365 {
1366 struct ata_pci_controller *ctlr = device_get_softc(dev);
1367 static struct ata_chip_id ids[] =
1368 {{ ATA_ADAPTEC_1420, 0, 4, MV60XX, ATA_SA300, "1420SA" },
1369 { 0, 0, 0, 0, 0, 0}};
1370
1371 if (!(ctlr->chip = ata_match_chip(dev, ids)))
1372 return ENXIO;
1373
1374 ata_set_desc(dev);
1375 ctlr->chipinit = ata_marvell_edma_chipinit;
1376
1377 return 0;
1378 }
1379
1380
1381 /*
1382 * ATI chipset support functions
1383 */
1384 int
1385 ata_ati_ident(device_t dev)
1386 {
1387 struct ata_pci_controller *ctlr = device_get_softc(dev);
1388 static struct ata_chip_id ids[] =
1389 {{ ATA_ATI_IXP200, 0x00, 0, ATIPATA, ATA_UDMA5, "IXP200" },
1390 { ATA_ATI_IXP300, 0x00, 0, ATIPATA, ATA_UDMA6, "IXP300" },
1391 { ATA_ATI_IXP300_S1, 0x00, 0, ATISATA, ATA_SA150, "IXP300" },
1392 { ATA_ATI_IXP400, 0x00, 0, ATIPATA, ATA_UDMA6, "IXP400" },
1393 { ATA_ATI_IXP400_S1, 0x00, 0, ATISATA, ATA_SA150, "IXP400" },
1394 { ATA_ATI_IXP400_S2, 0x00, 0, ATISATA, ATA_SA150, "IXP400" },
1395 { ATA_ATI_IXP600, 0x00, 0, ATIPATA, ATA_UDMA6, "IXP600" },
1396 { ATA_ATI_IXP600_S1, 0x00, 0, ATIAHCI, ATA_SA300, "IXP600" },
1397 { ATA_ATI_IXP700, 0x00, 0, ATIPATA, ATA_UDMA6, "IXP700" },
1398 { ATA_ATI_IXP700_S1, 0x00, 0, ATIAHCI, ATA_SA300, "IXP700" },
1399 { 0, 0, 0, 0, 0, 0}};
1400
1401 if (!(ctlr->chip = ata_match_chip(dev, ids)))
1402 return ENXIO;
1403
1404 ata_set_desc(dev);
1405
1406 switch (ctlr->chip->cfg2) {
1407 case ATIPATA:
1408 ctlr->chipinit = ata_ati_chipinit;
1409 break;
1410 case ATISATA:
1411 /* the ATI SATA controller is actually a SiI 3112 controller */
1412 ctlr->chip->cfg1 = SIIMEMIO;
1413 ctlr->chipinit = ata_sii_chipinit;
1414 break;
1415 case ATIAHCI:
1416 ctlr->chipinit = ata_ahci_chipinit;
1417 break;
1418 }
1419 return 0;
1420 }
1421
1422 static int
1423 ata_ati_chipinit(device_t dev)
1424 {
1425 struct ata_pci_controller *ctlr = device_get_softc(dev);
1426
1427 if (ata_setup_interrupt(dev))
1428 return ENXIO;
1429
1430 /* IXP600 only have 1 PATA channel */
1431 if (ctlr->chip->chipid == ATA_ATI_IXP600)
1432 ctlr->channels = 1;
1433
1434 ctlr->setmode = ata_ati_setmode;
1435 return 0;
1436 }
1437
1438 static void
1439 ata_ati_setmode(device_t dev, int mode)
1440 {
1441 device_t gparent = GRANDPARENT(dev);
1442 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1443 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1444 struct ata_device *atadev = device_get_softc(dev);
1445 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1446 int offset = (devno ^ 0x01) << 3;
1447 int error;
1448 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1449 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1450 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
1451
1452 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1453
1454 mode = ata_check_80pin(dev, mode);
1455
1456 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1457
1458 if (bootverbose)
1459 device_printf(dev, "%ssetting %s on %s chip\n",
1460 (error) ? "FAILURE " : "",
1461 ata_mode2str(mode), ctlr->chip->text);
1462 if (!error) {
1463 if (mode >= ATA_UDMA0) {
1464 pci_write_config(gparent, 0x56,
1465 (pci_read_config(gparent, 0x56, 2) &
1466 ~(0xf << (devno << 2))) |
1467 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
1468 pci_write_config(gparent, 0x54,
1469 pci_read_config(gparent, 0x54, 1) |
1470 (0x01 << devno), 1);
1471 pci_write_config(gparent, 0x44,
1472 (pci_read_config(gparent, 0x44, 4) &
1473 ~(0xff << offset)) |
1474 (dmatimings[2] << offset), 4);
1475 }
1476 else if (mode >= ATA_WDMA0) {
1477 pci_write_config(gparent, 0x54,
1478 pci_read_config(gparent, 0x54, 1) &
1479 ~(0x01 << devno), 1);
1480 pci_write_config(gparent, 0x44,
1481 (pci_read_config(gparent, 0x44, 4) &
1482 ~(0xff << offset)) |
1483 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
1484 }
1485 else
1486 pci_write_config(gparent, 0x54,
1487 pci_read_config(gparent, 0x54, 1) &
1488 ~(0x01 << devno), 1);
1489
1490 pci_write_config(gparent, 0x4a,
1491 (pci_read_config(gparent, 0x4a, 2) &
1492 ~(0xf << (devno << 2))) |
1493 (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2);
1494 pci_write_config(gparent, 0x40,
1495 (pci_read_config(gparent, 0x40, 4) &
1496 ~(0xff << offset)) |
1497 (piotimings[ata_mode2idx(mode)] << offset), 4);
1498 atadev->mode = mode;
1499 }
1500 }
1501
1502
1503 /*
1504 * Cyrix chipset support functions
1505 */
1506 int
1507 ata_cyrix_ident(device_t dev)
1508 {
1509 struct ata_pci_controller *ctlr = device_get_softc(dev);
1510
1511 if (pci_get_devid(dev) == ATA_CYRIX_5530) {
1512 device_set_desc(dev, "Cyrix 5530 ATA33 controller");
1513 ctlr->chipinit = ata_cyrix_chipinit;
1514 return 0;
1515 }
1516 return ENXIO;
1517 }
1518
1519 static int
1520 ata_cyrix_chipinit(device_t dev)
1521 {
1522 struct ata_pci_controller *ctlr = device_get_softc(dev);
1523
1524 if (ata_setup_interrupt(dev))
1525 return ENXIO;
1526
1527 if (ctlr->r_res1)
1528 ctlr->setmode = ata_cyrix_setmode;
1529 else
1530 ctlr->setmode = ata_generic_setmode;
1531 return 0;
1532 }
1533
1534 static void
1535 ata_cyrix_setmode(device_t dev, int mode)
1536 {
1537 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1538 struct ata_device *atadev = device_get_softc(dev);
1539 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1540 u_int32_t piotiming[] =
1541 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
1542 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
1543 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
1544 int error;
1545
1546 ch->dma->alignment = 16;
1547 ch->dma->max_iosize = 64 * DEV_BSIZE;
1548
1549 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
1550
1551 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1552
1553 if (bootverbose)
1554 device_printf(dev, "%ssetting %s on Cyrix chip\n",
1555 (error) ? "FAILURE " : "", ata_mode2str(mode));
1556 if (!error) {
1557 if (mode >= ATA_UDMA0) {
1558 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1559 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]);
1560 }
1561 else if (mode >= ATA_WDMA0) {
1562 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1563 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]);
1564 }
1565 else {
1566 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1567 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]);
1568 }
1569 atadev->mode = mode;
1570 }
1571 }
1572
1573
1574 /*
1575 * Cypress chipset support functions
1576 */
1577 int
1578 ata_cypress_ident(device_t dev)
1579 {
1580 struct ata_pci_controller *ctlr = device_get_softc(dev);
1581
1582 /*
1583 * the Cypress chip is a mess, it contains two ATA functions, but
1584 * both channels are visible on the first one.
1585 * simply ignore the second function for now, as the right
1586 * solution (ignoring the second channel on the first function)
1587 * doesn't work with the crappy ATA interrupt setup on the alpha.
1588 */
1589 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 &&
1590 pci_get_function(dev) == 1 &&
1591 pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
1592 device_set_desc(dev, "Cypress 82C693 ATA controller");
1593 ctlr->chipinit = ata_cypress_chipinit;
1594 return 0;
1595 }
1596 return ENXIO;
1597 }
1598
1599 static int
1600 ata_cypress_chipinit(device_t dev)
1601 {
1602 struct ata_pci_controller *ctlr = device_get_softc(dev);
1603
1604 if (ata_setup_interrupt(dev))
1605 return ENXIO;
1606
1607 ctlr->setmode = ata_cypress_setmode;
1608 return 0;
1609 }
1610
1611 static void
1612 ata_cypress_setmode(device_t dev, int mode)
1613 {
1614 device_t gparent = GRANDPARENT(dev);
1615 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1616 struct ata_device *atadev = device_get_softc(dev);
1617 int error;
1618
1619 mode = ata_limit_mode(dev, mode, ATA_WDMA2);
1620
1621 /* XXX SOS missing WDMA0+1 + PIO modes */
1622 if (mode == ATA_WDMA2) {
1623 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1624 if (bootverbose)
1625 device_printf(dev, "%ssetting WDMA2 on Cypress chip\n",
1626 error ? "FAILURE " : "");
1627 if (!error) {
1628 pci_write_config(gparent, ch->unit ? 0x4e : 0x4c, 0x2020, 2);
1629 atadev->mode = mode;
1630 return;
1631 }
1632 }
1633 /* we could set PIO mode timings, but we assume the BIOS did that */
1634 }
1635
1636
1637 /*
1638 * HighPoint chipset support functions
1639 */
1640 int
1641 ata_highpoint_ident(device_t dev)
1642 {
1643 struct ata_pci_controller *ctlr = device_get_softc(dev);
1644 struct ata_chip_id *idx;
1645 static struct ata_chip_id ids[] =
1646 {{ ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HPT374" },
1647 { ATA_HPT372, 0x02, HPT372, 0x00, ATA_UDMA6, "HPT372N" },
1648 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1649 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT371" },
1650 { ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1651 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HPT370" },
1652 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HPT368" },
1653 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HPT366" },
1654 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT302" },
1655 { 0, 0, 0, 0, 0, 0}};
1656 char buffer[64];
1657
1658 if (!(idx = ata_match_chip(dev, ids)))
1659 return ENXIO;
1660
1661 strcpy(buffer, "HighPoint ");
1662 strcat(buffer, idx->text);
1663 if (idx->cfg1 == HPT374) {
1664 if (pci_get_function(dev) == 0)
1665 strcat(buffer, " (channel 0+1)");
1666 if (pci_get_function(dev) == 1)
1667 strcat(buffer, " (channel 2+3)");
1668 }
1669 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
1670 device_set_desc_copy(dev, buffer);
1671 ctlr->chip = idx;
1672 ctlr->chipinit = ata_highpoint_chipinit;
1673 return 0;
1674 }
1675
1676 static int
1677 ata_highpoint_chipinit(device_t dev)
1678 {
1679 struct ata_pci_controller *ctlr = device_get_softc(dev);
1680
1681 if (ata_setup_interrupt(dev))
1682 return ENXIO;
1683
1684 if (ctlr->chip->cfg2 == HPTOLD) {
1685 /* disable interrupt prediction */
1686 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
1687 }
1688 else {
1689 /* disable interrupt prediction */
1690 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
1691 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
1692
1693 /* enable interrupts */
1694 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
1695
1696 /* set clocks etc */
1697 if (ctlr->chip->cfg1 < HPT372)
1698 pci_write_config(dev, 0x5b, 0x22, 1);
1699 else
1700 pci_write_config(dev, 0x5b,
1701 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
1702 }
1703 ctlr->allocate = ata_highpoint_allocate;
1704 ctlr->setmode = ata_highpoint_setmode;
1705 return 0;
1706 }
1707
1708 static int
1709 ata_highpoint_allocate(device_t dev)
1710 {
1711 struct ata_channel *ch = device_get_softc(dev);
1712
1713 /* setup the usual register normal pci style */
1714 if (ata_pci_allocate(dev))
1715 return ENXIO;
1716
1717 ch->flags |= ATA_ALWAYS_DMASTAT;
1718 return 0;
1719 }
1720
1721 static void
1722 ata_highpoint_setmode(device_t dev, int mode)
1723 {
1724 device_t gparent = GRANDPARENT(dev);
1725 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1726 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1727 struct ata_device *atadev = device_get_softc(dev);
1728 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1729 int error;
1730 u_int32_t timings33[][4] = {
1731 /* HPT366 HPT370 HPT372 HPT374 mode */
1732 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
1733 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
1734 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
1735 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
1736 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
1737 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
1738 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
1739 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
1740 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */
1741 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */
1742 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */
1743 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */
1744 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */
1745 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */
1746 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */
1747 };
1748
1749 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1750
1751 if (ctlr->chip->cfg1 == HPT366 && ata_atapi(dev))
1752 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1753
1754 mode = ata_highpoint_check_80pin(dev, mode);
1755
1756 /*
1757 * most if not all HPT chips cant really handle that the device is
1758 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to
1759 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance
1760 */
1761 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
1762 ata_limit_mode(dev, mode, ATA_UDMA5));
1763 if (bootverbose)
1764 device_printf(dev, "%ssetting %s on HighPoint chip\n",
1765 (error) ? "FAILURE " : "", ata_mode2str(mode));
1766 if (!error)
1767 pci_write_config(gparent, 0x40 + (devno << 2),
1768 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
1769 atadev->mode = mode;
1770 }
1771
1772 static int
1773 ata_highpoint_check_80pin(device_t dev, int mode)
1774 {
1775 device_t gparent = GRANDPARENT(dev);
1776 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1777 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1778 u_int8_t reg, val, res;
1779
1780 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(gparent) == 1) {
1781 reg = ch->unit ? 0x57 : 0x53;
1782 val = pci_read_config(gparent, reg, 1);
1783 pci_write_config(gparent, reg, val | 0x80, 1);
1784 }
1785 else {
1786 reg = 0x5b;
1787 val = pci_read_config(gparent, reg, 1);
1788 pci_write_config(gparent, reg, val & 0xfe, 1);
1789 }
1790 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2);
1791 pci_write_config(gparent, reg, val, 1);
1792
1793 if (mode > ATA_UDMA2 && res) {
1794 ata_print_cable(dev, "controller");
1795 mode = ATA_UDMA2;
1796 }
1797 return mode;
1798 }
1799
1800
1801 /*
1802 * Intel chipset support functions
1803 */
1804 int
1805 ata_intel_ident(device_t dev)
1806 {
1807 struct ata_pci_controller *ctlr = device_get_softc(dev);
1808 static struct ata_chip_id ids[] =
1809 {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" },
1810 { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" },
1811 { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" },
1812 { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" },
1813 { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" },
1814 { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" },
1815 { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" },
1816 { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" },
1817 { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" },
1818 { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" },
1819 { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" },
1820 { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" },
1821 { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" },
1822 { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" },
1823 { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" },
1824 { ATA_I82801EB_S1, 0, 0, 2, ATA_SA150, "ICH5" },
1825 { ATA_I82801EB_R1, 0, 0, 2, ATA_SA150, "ICH5" },
1826 { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" },
1827 { ATA_I6300ESB_S1, 0, 0, 2, ATA_SA150, "6300ESB" },
1828 { ATA_I6300ESB_R1, 0, 0, 2, ATA_SA150, "6300ESB" },
1829 { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" },
1830 { ATA_I82801FB_S1, 0, AHCI, 0, ATA_SA150, "ICH6" },
1831 { ATA_I82801FB_R1, 0, AHCI, 0, ATA_SA150, "ICH6" },
1832 { ATA_I82801FBM, 0, AHCI, 0, ATA_SA150, "ICH6M" },
1833 { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" },
1834 { ATA_I82801GB_S1, 0, AHCI, 0, ATA_SA300, "ICH7" },
1835 { ATA_I82801GB_R1, 0, AHCI, 0, ATA_SA300, "ICH7" },
1836 { ATA_I82801GB_AH, 0, AHCI, 0, ATA_SA300, "ICH7" },
1837 { ATA_I82801GBM_S1, 0, AHCI, 0, ATA_SA300, "ICH7M" },
1838 { ATA_I82801GBM_R1, 0, AHCI, 0, ATA_SA300, "ICH7M" },
1839 { ATA_I82801GBM_AH, 0, AHCI, 0, ATA_SA300, "ICH7M" },
1840 { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" },
1841 { ATA_I63XXESB2_S1, 0, AHCI, 0, ATA_SA300, "63XXESB2" },
1842 { ATA_I63XXESB2_S2, 0, AHCI, 0, ATA_SA300, "63XXESB2" },
1843 { ATA_I63XXESB2_R1, 0, AHCI, 0, ATA_SA300, "63XXESB2" },
1844 { ATA_I63XXESB2_R2, 0, AHCI, 0, ATA_SA300, "63XXESB2" },
1845 { ATA_I82801HB_S1, 0, AHCI, 0, ATA_SA300, "ICH8" },
1846 { ATA_I82801HB_S2, 0, AHCI, 0, ATA_SA300, "ICH8" },
1847 { ATA_I82801HB_R1, 0, AHCI, 0, ATA_SA300, "ICH8" },
1848 { ATA_I82801HB_AH4, 0, AHCI, 0, ATA_SA300, "ICH8" },
1849 { ATA_I82801HB_AH6, 0, AHCI, 0, ATA_SA300, "ICH8" },
1850 { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" },
1851 { ATA_I82801HBM_S1, 0, AHCI, 0, ATA_SA300, "ICH8M" },
1852 { ATA_I82801HBM_S2, 0, AHCI, 0, ATA_SA300, "ICH8M" },
1853 { ATA_I82801HBM_S3, 0, AHCI, 0, ATA_SA300, "ICH8M" },
1854 { ATA_I82801IB_S1, 0, AHCI, 0, ATA_SA300, "ICH9" },
1855 { ATA_I82801IB_S2, 0, AHCI, 0, ATA_SA300, "ICH9" },
1856 { ATA_I82801IB_AH2, 0, AHCI, 0, ATA_SA300, "ICH9" },
1857 { ATA_I82801IB_AH4, 0, AHCI, 0, ATA_SA300, "ICH9" },
1858 { ATA_I82801IB_AH6, 0, AHCI, 0, ATA_SA300, "ICH9" },
1859 { ATA_I82801IB_R1, 0, AHCI, 0, ATA_SA300, "ICH9" },
1860 { ATA_I82801JIB_S1, 0, AHCI, 0, ATA_SA300, "ICH10" },
1861 { ATA_I82801JIB_AH, 0, AHCI, 0, ATA_SA300, "ICH10" },
1862 { ATA_I82801JIB_R1, 0, AHCI, 0, ATA_SA300, "ICH10" },
1863 { ATA_I82801JIB_S2, 0, AHCI, 0, ATA_SA300, "ICH10" },
1864 { ATA_I82801JD_S1, 0, AHCI, 0, ATA_SA300, "ICH10" },
1865 { ATA_I82801JD_AH, 0, AHCI, 0, ATA_SA300, "ICH10" },
1866 { ATA_I82801JD_R1, 0, AHCI, 0, ATA_SA300, "ICH10" },
1867 { ATA_I82801JD_S2, 0, AHCI, 0, ATA_SA300, "ICH10" },
1868 { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" },
1869 { 0, 0, 0, 0, 0, 0}};
1870
1871 if (!(ctlr->chip = ata_match_chip(dev, ids)))
1872 return ENXIO;
1873
1874 ata_set_desc(dev);
1875 ctlr->chipinit = ata_intel_chipinit;
1876 return 0;
1877 }
1878
1879 static int
1880 ata_intel_chipinit(device_t dev)
1881 {
1882 struct ata_pci_controller *ctlr = device_get_softc(dev);
1883
1884 if (ata_setup_interrupt(dev))
1885 return ENXIO;
1886
1887 /* good old PIIX needs special treatment (not implemented) */
1888 if (ctlr->chip->chipid == ATA_I82371FB) {
1889 ctlr->setmode = ata_intel_old_setmode;
1890 }
1891
1892 /* the intel 31244 needs special care if in DPA mode */
1893 else if (ctlr->chip->chipid == ATA_I31244) {
1894 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) {
1895 ctlr->r_type2 = SYS_RES_MEMORY;
1896 ctlr->r_rid2 = PCIR_BAR(0);
1897 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1898 &ctlr->r_rid2,
1899 RF_ACTIVE)))
1900 return ENXIO;
1901 ctlr->channels = 4;
1902 ctlr->allocate = ata_intel_31244_allocate;
1903 ctlr->reset = ata_intel_31244_reset;
1904 }
1905 ctlr->setmode = ata_sata_setmode;
1906 }
1907
1908 /* non SATA intel chips goes here */
1909 else if (ctlr->chip->max_dma < ATA_SA150) {
1910 ctlr->channels = ctlr->chip->cfg2;
1911 ctlr->allocate = ata_intel_allocate;
1912 ctlr->setmode = ata_intel_new_setmode;
1913 }
1914
1915 /* SATA parts can be either compat or AHCI */
1916 else {
1917 /* force all ports active "the legacy way" */
1918 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2);
1919
1920 ctlr->allocate = ata_intel_allocate;
1921 ctlr->reset = ata_intel_reset;
1922
1923 /*
1924 * if we have AHCI capability and AHCI or RAID mode enabled
1925 * in BIOS we try for AHCI mode
1926 */
1927 if ((ctlr->chip->cfg1 == AHCI) &&
1928 (pci_read_config(dev, 0x90, 1) & 0xc0) &&
1929 (ata_ahci_chipinit(dev) != ENXIO))
1930 return 0;
1931
1932 /* if BAR(5) is IO it should point to SATA interface registers */
1933 ctlr->r_type2 = SYS_RES_IOPORT;
1934 ctlr->r_rid2 = PCIR_BAR(5);
1935 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1936 &ctlr->r_rid2, RF_ACTIVE)))
1937 ctlr->setmode = ata_intel_sata_setmode;
1938 else
1939 ctlr->setmode = ata_sata_setmode;
1940 }
1941 return 0;
1942 }
1943
1944 static int
1945 ata_intel_allocate(device_t dev)
1946 {
1947 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1948 struct ata_channel *ch = device_get_softc(dev);
1949
1950 /* setup the usual register normal pci style */
1951 if (ata_pci_allocate(dev))
1952 return ENXIO;
1953
1954 /* if r_res2 is valid it points to SATA interface registers */
1955 if (ctlr->r_res2) {
1956 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
1957 ch->r_io[ATA_IDX_ADDR].offset = 0x00;
1958 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2;
1959 ch->r_io[ATA_IDX_DATA].offset = 0x04;
1960 }
1961
1962 ch->flags |= ATA_ALWAYS_DMASTAT;
1963 return 0;
1964 }
1965
1966 static void
1967 ata_intel_reset(device_t dev)
1968 {
1969 device_t parent = device_get_parent(dev);
1970 struct ata_pci_controller *ctlr = device_get_softc(parent);
1971 struct ata_channel *ch = device_get_softc(dev);
1972 int mask, timeout;
1973
1974 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */
1975 if (ctlr->chip->cfg1) {
1976 mask = (0x0005 << ch->unit);
1977 }
1978 else {
1979 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */
1980 if (pci_read_config(parent, 0x90, 1) & 0x04)
1981 mask = 0x0003;
1982 else {
1983 mask = (0x0001 << ch->unit);
1984 /* XXX SOS should be in intel_allocate if we grow it */
1985 ch->flags |= ATA_NO_SLAVE;
1986 }
1987 }
1988 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2);
1989 DELAY(10);
1990 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2);
1991
1992 /* wait up to 1 sec for "connect well" */
1993 for (timeout = 0; timeout < 100 ; timeout++) {
1994 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) &&
1995 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff))
1996 break;
1997 ata_udelay(10000);
1998 }
1999 ata_generic_reset(dev);
2000 }
2001
2002 static void
2003 ata_intel_old_setmode(device_t dev, int mode)
2004 {
2005 /* NOT YET */
2006 }
2007
2008 static void
2009 ata_intel_new_setmode(device_t dev, int mode)
2010 {
2011 device_t gparent = GRANDPARENT(dev);
2012 struct ata_pci_controller *ctlr = device_get_softc(gparent);
2013 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2014 struct ata_device *atadev = device_get_softc(dev);
2015 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2016 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4);
2017 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1);
2018 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1);
2019 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2);
2020 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2);
2021 u_int32_t mask40 = 0, new40 = 0;
2022 u_int8_t mask44 = 0, new44 = 0;
2023 int error;
2024 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
2025 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
2026
2027 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
2028
2029 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
2030 ata_print_cable(dev, "controller");
2031 mode = ATA_UDMA2;
2032 }
2033
2034 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2035
2036 if (bootverbose)
2037 device_printf(dev, "%ssetting %s on %s chip\n",
2038 (error) ? "FAILURE " : "",
2039 ata_mode2str(mode), ctlr->chip->text);
2040 if (!error) {
2041 if (mode >= ATA_UDMA0) {
2042 u_int8_t utimings[] = { 0x00, 0x01, 0x10, 0x01, 0x10, 0x01, 0x10 };
2043
2044 pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2);
2045 pci_write_config(gparent, 0x4a,
2046 (reg4a & ~(0x3 << (devno << 2))) |
2047 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2);
2048 }
2049 else {
2050 pci_write_config(gparent, 0x48, reg48 & ~(0x0001 << devno), 2);
2051 pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2);
2052 }
2053 reg54 |= 0x0400;
2054 if (mode >= ATA_UDMA2)
2055 reg54 |= (0x1 << devno);
2056 else
2057 reg54 &= ~(0x1 << devno);
2058 if (mode >= ATA_UDMA5)
2059 reg54 |= (0x1000 << devno);
2060 else
2061 reg54 &= ~(0x1000 << devno);
2062
2063 pci_write_config(gparent, 0x54, reg54, 2);
2064
2065 reg40 &= ~0x00ff00ff;
2066 reg40 |= 0x40774077;
2067
2068 if (atadev->unit == ATA_MASTER) {
2069 mask40 = 0x3300;
2070 new40 = timings[ata_mode2idx(mode)] << 8;
2071 }
2072 else {
2073 mask44 = 0x0f;
2074 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
2075 (timings[ata_mode2idx(mode)] & 0x03);
2076 }
2077 if (ch->unit) {
2078 mask40 <<= 16;
2079 new40 <<= 16;
2080 mask44 <<= 4;
2081 new44 <<= 4;
2082 }
2083 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4);
2084 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1);
2085
2086 atadev->mode = mode;
2087 }
2088 }
2089
2090 static void
2091 ata_intel_sata_setmode(device_t dev, int mode)
2092 {
2093 struct ata_device *atadev = device_get_softc(dev);
2094
2095 if (atadev->param.satacapabilities != 0x0000 &&
2096 atadev->param.satacapabilities != 0xffff) {
2097
2098 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2099 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2100
2101 /* on some drives we need to set the transfer mode */
2102 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
2103 ata_limit_mode(dev, mode, ATA_UDMA6));
2104
2105 /* set ATA_SSTATUS register offset */
2106 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, devno * 0x100);
2107
2108 /* query SATA STATUS for the speed */
2109 if ((ATA_IDX_INL(ch, ATA_IDX_DATA) & ATA_SS_CONWELL_MASK) ==
2110 ATA_SS_CONWELL_GEN2)
2111 atadev->mode = ATA_SA300;
2112 else
2113 atadev->mode = ATA_SA150;
2114 }
2115 else {
2116 mode = ata_limit_mode(dev, mode, ATA_UDMA5);
2117 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2118 atadev->mode = mode;
2119 }
2120 }
2121
2122 static int
2123 ata_intel_31244_allocate(device_t dev)
2124 {
2125 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2126 struct ata_channel *ch = device_get_softc(dev);
2127 int i;
2128 int ch_offset;
2129
2130 ch_offset = 0x200 + ch->unit * 0x200;
2131
2132 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
2133 ch->r_io[i].res = ctlr->r_res2;
2134
2135 /* setup ATA registers */
2136 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
2137 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06;
2138 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
2139 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
2140 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
2141 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
2142 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
2143 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d;
2144 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04;
2145 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c;
2146 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28;
2147 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29;
2148
2149 /* setup DMA registers */
2150 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100;
2151 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104;
2152 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108;
2153
2154 /* setup SATA registers */
2155 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70;
2156 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72;
2157 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74;
2158
2159 ch->flags |= ATA_NO_SLAVE;
2160 ata_pci_hw(dev);
2161 ch->hw.status = ata_intel_31244_status;
2162 ch->hw.tf_write = ata_intel_31244_tf_write;
2163
2164 /* enable PHY state change interrupt */
2165 ATA_OUTL(ctlr->r_res2, 0x4,
2166 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3)));
2167 return 0;
2168 }
2169
2170 static int
2171 ata_intel_31244_status(device_t dev)
2172 {
2173 /* do we have any PHY events ? */
2174 ata_sata_phy_check_events(dev);
2175
2176 /* any drive action to take care of ? */
2177 return ata_pci_status(dev);
2178 }
2179
2180 static void
2181 ata_intel_31244_tf_write(struct ata_request *request)
2182 {
2183 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2184 struct ata_device *atadev = device_get_softc(request->dev);
2185
2186 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
2187 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
2188 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
2189 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) |
2190 (request->u.ata.lba & 0x00ff));
2191 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) |
2192 ((request->u.ata.lba >> 8) & 0x00ff));
2193 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) |
2194 ((request->u.ata.lba >> 16) & 0x00ff));
2195 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | atadev->unit);
2196 }
2197 else {
2198 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
2199 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
2200 if (atadev->flags & ATA_D_USE_CHS) {
2201 int heads, sectors;
2202
2203 if (atadev->param.atavalid & ATA_FLAG_54_58) {
2204 heads = atadev->param.current_heads;
2205 sectors = atadev->param.current_sectors;
2206 }
2207 else {
2208 heads = atadev->param.heads;
2209 sectors = atadev->param.sectors;
2210 }
2211 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
2212 ATA_IDX_OUTB(ch, ATA_CYL_LSB,
2213 (request->u.ata.lba / (sectors * heads)));
2214 ATA_IDX_OUTB(ch, ATA_CYL_MSB,
2215 (request->u.ata.lba / (sectors * heads)) >> 8);
2216 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit |
2217 (((request->u.ata.lba% (sectors * heads)) /
2218 sectors) & 0xf));
2219 }
2220 else {
2221 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
2222 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
2223 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
2224 ATA_IDX_OUTB(ch, ATA_DRIVE,
2225 ATA_D_IBM | ATA_D_LBA | atadev->unit |
2226 ((request->u.ata.lba >> 24) & 0x0f));
2227 }
2228 }
2229 }
2230
2231 static void
2232 ata_intel_31244_reset(device_t dev)
2233 {
2234 if (ata_sata_phy_reset(dev))
2235 ata_generic_reset(dev);
2236 }
2237
2238
2239 /*
2240 * Integrated Technology Express Inc. (ITE) chipset support functions
2241 */
2242 int
2243 ata_ite_ident(device_t dev)
2244 {
2245 struct ata_pci_controller *ctlr = device_get_softc(dev);
2246 static struct ata_chip_id ids[] =
2247 {{ ATA_IT8213F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8213F" },
2248 { ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" },
2249 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" },
2250 { 0, 0, 0, 0, 0, 0}};
2251
2252 if (!(ctlr->chip = ata_match_chip(dev, ids)))
2253 return ENXIO;
2254
2255 ata_set_desc(dev);
2256 ctlr->chipinit = ata_ite_chipinit;
2257 return 0;
2258 }
2259
2260 static int
2261 ata_ite_chipinit(device_t dev)
2262 {
2263 struct ata_pci_controller *ctlr = device_get_softc(dev);
2264
2265 if (ata_setup_interrupt(dev))
2266 return ENXIO;
2267
2268 if (ctlr->chip->chipid == ATA_IT8213F) {
2269 /* the ITE 8213F only has one channel */
2270 ctlr->channels = 1;
2271
2272 ctlr->setmode = ata_ite_8213_setmode;
2273 }
2274 else {
2275 /* set PCI mode and 66Mhz reference clock */
2276 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1);
2277
2278 /* set default active & recover timings */
2279 pci_write_config(dev, 0x54, 0x31, 1);
2280 pci_write_config(dev, 0x56, 0x31, 1);
2281
2282 ctlr->setmode = ata_ite_821x_setmode;
2283 }
2284
2285 return 0;
2286 }
2287
2288 static void
2289 ata_ite_821x_setmode(device_t dev, int mode)
2290 {
2291 device_t gparent = GRANDPARENT(dev);
2292 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2293 struct ata_device *atadev = device_get_softc(dev);
2294 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2295 int error;
2296
2297 /* correct the mode for what the HW supports */
2298 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2299
2300 /* check the CBLID bits for 80 conductor cable detection */
2301 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) &
2302 (ch->unit ? (1<<3) : (1<<2)))) {
2303 ata_print_cable(dev, "controller");
2304 mode = ATA_UDMA2;
2305 }
2306
2307 /* set the wanted mode on the device */
2308 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2309
2310 if (bootverbose)
2311 device_printf(dev, "%s setting %s on ITE8212F chip\n",
2312 (error) ? "failed" : "success", ata_mode2str(mode));
2313
2314 /* if the device accepted the mode change, setup the HW accordingly */
2315 if (!error) {
2316 if (mode >= ATA_UDMA0) {
2317 u_int8_t udmatiming[] =
2318 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
2319
2320 /* enable UDMA mode */
2321 pci_write_config(gparent, 0x50,
2322 pci_read_config(gparent, 0x50, 1) &
2323 ~(1 << (devno + 3)), 1);
2324
2325 /* set UDMA timing */
2326 pci_write_config(gparent,
2327 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit),
2328 udmatiming[mode & ATA_MODE_MASK], 1);
2329 }
2330 else {
2331 u_int8_t chtiming[] =
2332 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
2333
2334 /* disable UDMA mode */
2335 pci_write_config(gparent, 0x50,
2336 pci_read_config(gparent, 0x50, 1) |
2337 (1 << (devno + 3)), 1);
2338
2339 /* set active and recover timing (shared between master & slave) */
2340 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) <
2341 chtiming[ata_mode2idx(mode)])
2342 pci_write_config(gparent, 0x54 + (ch->unit << 2),
2343 chtiming[ata_mode2idx(mode)], 1);
2344 }
2345 atadev->mode = mode;
2346 }
2347 }
2348
2349 static void
2350 ata_ite_8213_setmode(device_t dev, int mode)
2351 {
2352 device_t gparent = GRANDPARENT(dev);
2353 struct ata_pci_controller *ctlr = device_get_softc(gparent);
2354 struct ata_device *atadev = device_get_softc(dev);
2355 u_int16_t reg40 = pci_read_config(gparent, 0x40, 2);
2356 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1);
2357 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1);
2358 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2);
2359 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2);
2360 u_int16_t mask40 = 0, new40 = 0;
2361 u_int8_t mask44 = 0, new44 = 0;
2362 int devno = atadev->unit;
2363 int error;
2364 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
2365 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
2366
2367 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
2368
2369 if (mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
2370 ata_print_cable(dev, "controller");
2371 mode = ATA_UDMA2;
2372 }
2373
2374 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2375
2376 if (bootverbose)
2377 device_printf(dev, "%ssetting %s on %s chip\n",
2378 (error) ? "FAILURE " : "",
2379 ata_mode2str(mode), ctlr->chip->text);
2380 if (!error) {
2381 if (mode >= ATA_UDMA0) {
2382 u_int8_t utimings[] = { 0x00, 0x01, 0x10, 0x01, 0x10, 0x01, 0x10 };
2383
2384 pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2);
2385 pci_write_config(gparent, 0x4a,
2386 (reg4a & ~(0x3 << (devno << 2))) |
2387 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2);
2388 }
2389 else {
2390 pci_write_config(gparent, 0x48, reg48 & ~(0x0001 << devno), 2);
2391 pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2);
2392 }
2393 if (mode >= ATA_UDMA2)
2394 reg54 |= (0x1 << devno);
2395 else
2396 reg54 &= ~(0x1 << devno);
2397 if (mode >= ATA_UDMA5)
2398 reg54 |= (0x1000 << devno);
2399 else
2400 reg54 &= ~(0x1000 << devno);
2401 pci_write_config(gparent, 0x54, reg54, 2);
2402
2403 reg40 &= 0xff00;
2404 reg40 |= 0x4033;
2405 if (atadev->unit == ATA_MASTER) {
2406 reg40 |= (ata_atapi(dev) ? 0x04 : 0x00);
2407 mask40 = 0x3300;
2408 new40 = timings[ata_mode2idx(mode)] << 8;
2409 }
2410 else {
2411 reg40 |= (ata_atapi(dev) ? 0x40 : 0x00);
2412 mask44 = 0x0f;
2413 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
2414 (timings[ata_mode2idx(mode)] & 0x03);
2415 }
2416 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4);
2417 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1);
2418
2419 atadev->mode = mode;
2420 }
2421 }
2422
2423
2424 /*
2425 * JMicron chipset support functions
2426 */
2427 int
2428 ata_jmicron_ident(device_t dev)
2429 {
2430 struct ata_pci_controller *ctlr = device_get_softc(dev);
2431 struct ata_chip_id *idx;
2432 static struct ata_chip_id ids[] =
2433 {{ ATA_JMB360, 0, 1, 0, ATA_SA300, "JMB360" },
2434 { ATA_JMB361, 0, 1, 1, ATA_SA300, "JMB361" },
2435 { ATA_JMB363, 0, 2, 1, ATA_SA300, "JMB363" },
2436 { ATA_JMB365, 0, 1, 2, ATA_SA300, "JMB365" },
2437 { ATA_JMB366, 0, 2, 2, ATA_SA300, "JMB366" },
2438 { ATA_JMB368, 0, 0, 1, ATA_UDMA6, "JMB368" },
2439 { 0, 0, 0, 0, 0, 0}};
2440 char buffer[64];
2441
2442 if (!(idx = ata_match_chip(dev, ids)))
2443 return ENXIO;
2444
2445 if ((pci_read_config(dev, 0xdf, 1) & 0x40) &&
2446 (pci_get_function(dev) == (pci_read_config(dev, 0x40, 1) & 0x02 >> 1)))
2447 sprintf(buffer, "JMicron %s %s controller",
2448 idx->text, ata_mode2str(ATA_UDMA6));
2449 else
2450 sprintf(buffer, "JMicron %s %s controller",
2451 idx->text, ata_mode2str(idx->max_dma));
2452 device_set_desc_copy(dev, buffer);
2453 ctlr->chip = idx;
2454 ctlr->chipinit = ata_jmicron_chipinit;
2455 return 0;
2456 }
2457
2458 static int
2459 ata_jmicron_chipinit(device_t dev)
2460 {
2461 struct ata_pci_controller *ctlr = device_get_softc(dev);
2462 int error;
2463
2464 if (ata_setup_interrupt(dev))
2465 return ENXIO;
2466
2467 /* do we have multiple PCI functions ? */
2468 if (pci_read_config(dev, 0xdf, 1) & 0x40) {
2469 /* are we on the AHCI part ? */
2470 if (ata_ahci_chipinit(dev) != ENXIO)
2471 return 0;
2472
2473 /* otherwise we are on the PATA part */
2474 ctlr->allocate = ata_pci_allocate;
2475 ctlr->reset = ata_generic_reset;
2476 ctlr->dmainit = ata_pci_dmainit;
2477 ctlr->setmode = ata_jmicron_setmode;
2478 ctlr->channels = ctlr->chip->cfg2;
2479 }
2480 else {
2481 /* set controller configuration to a combined setup we support */
2482 pci_write_config(dev, 0x40, 0x80c0a131, 4);
2483 pci_write_config(dev, 0x80, 0x01200000, 4);
2484
2485 if (ctlr->chip->cfg1 && (error = ata_ahci_chipinit(dev)))
2486 return error;
2487
2488 ctlr->allocate = ata_jmicron_allocate;
2489 ctlr->reset = ata_jmicron_reset;
2490 ctlr->dmainit = ata_jmicron_dmainit;
2491 ctlr->setmode = ata_jmicron_setmode;
2492
2493 /* set the number of HW channels */
2494 ctlr->channels = ctlr->chip->cfg1 + ctlr->chip->cfg2;
2495 }
2496 return 0;
2497 }
2498
2499 static int
2500 ata_jmicron_allocate(device_t dev)
2501 {
2502 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2503 struct ata_channel *ch = device_get_softc(dev);
2504 int error;
2505
2506 if (ch->unit >= ctlr->chip->cfg1) {
2507 ch->unit -= ctlr->chip->cfg1;
2508 error = ata_pci_allocate(dev);
2509 ch->unit += ctlr->chip->cfg1;
2510 }
2511 else
2512 error = ata_ahci_allocate(dev);
2513 return error;
2514 }
2515
2516 static void
2517 ata_jmicron_reset(device_t dev)
2518 {
2519 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2520 struct ata_channel *ch = device_get_softc(dev);
2521
2522 if (ch->unit >= ctlr->chip->cfg1)
2523 ata_generic_reset(dev);
2524 else
2525 ata_ahci_reset(dev);
2526 }
2527
2528 static void
2529 ata_jmicron_dmainit(device_t dev)
2530 {
2531 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2532 struct ata_channel *ch = device_get_softc(dev);
2533
2534 if (ch->unit >= ctlr->chip->cfg1)
2535 ata_pci_dmainit(dev);
2536 else
2537 ata_ahci_dmainit(dev);
2538 }
2539
2540 static void
2541 ata_jmicron_setmode(device_t dev, int mode)
2542 {
2543 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
2544 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2545
2546 if (pci_read_config(dev, 0xdf, 1) & 0x40 || ch->unit >= ctlr->chip->cfg1) {
2547 struct ata_device *atadev = device_get_softc(dev);
2548
2549 /* check for 80pin cable present */
2550 if (pci_read_config(dev, 0x40, 1) & 0x08)
2551 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
2552 else
2553 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2554
2555 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2556 atadev->mode = mode;
2557 }
2558 else
2559 ata_sata_setmode(dev, mode);
2560 }
2561
2562
2563 /*
2564 * Marvell chipset support functions
2565 */
2566 #define ATA_MV_HOST_BASE(ch) \
2567 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000)
2568 #define ATA_MV_EDMA_BASE(ch) \
2569 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000)
2570
2571 struct ata_marvell_response {
2572 u_int16_t tag;
2573 u_int8_t edma_status;
2574 u_int8_t dev_status;
2575 u_int32_t timestamp;
2576 };
2577
2578 struct ata_marvell_dma_prdentry {
2579 u_int32_t addrlo;
2580 u_int32_t count;
2581 u_int32_t addrhi;
2582 u_int32_t reserved;
2583 };
2584
2585 int
2586 ata_marvell_ident(device_t dev)
2587 {
2588 struct ata_pci_controller *ctlr = device_get_softc(dev);
2589 static struct ata_chip_id ids[] =
2590 {{ ATA_M88SX5040, 0, 4, MV50XX, ATA_SA150, "88SX5040" },
2591 { ATA_M88SX5041, 0, 4, MV50XX, ATA_SA150, "88SX5041" },
2592 { ATA_M88SX5080, 0, 8, MV50XX, ATA_SA150, "88SX5080" },
2593 { ATA_M88SX5081, 0, 8, MV50XX, ATA_SA150, "88SX5081" },
2594 { ATA_M88SX6041, 0, 4, MV60XX, ATA_SA300, "88SX6041" },
2595 { ATA_M88SX6081, 0, 8, MV60XX, ATA_SA300, "88SX6081" },
2596 { ATA_M88SX6101, 0, 1, MV61XX, ATA_UDMA6, "88SX6101" },
2597 { ATA_M88SX6121, 0, 1, MV61XX, ATA_UDMA6, "88SX6121" },
2598 { ATA_M88SX6145, 0, 2, MV61XX, ATA_UDMA6, "88SX6145" },
2599 { 0, 0, 0, 0, 0, 0}};
2600
2601 if (!(ctlr->chip = ata_match_chip(dev, ids)))
2602 return ENXIO;
2603
2604 ata_set_desc(dev);
2605
2606 switch (ctlr->chip->cfg2) {
2607 case MV50XX:
2608 case MV60XX:
2609 ctlr->chipinit = ata_marvell_edma_chipinit;
2610 break;
2611 case MV61XX:
2612 ctlr->chipinit = ata_marvell_pata_chipinit;
2613 break;
2614 }
2615 return 0;
2616 }
2617
2618 static int
2619 ata_marvell_pata_chipinit(device_t dev)
2620 {
2621 struct ata_pci_controller *ctlr = device_get_softc(dev);
2622
2623 if (ata_setup_interrupt(dev))
2624 return ENXIO;
2625
2626 ctlr->allocate = ata_marvell_pata_allocate;
2627 ctlr->setmode = ata_marvell_pata_setmode;
2628 ctlr->channels = ctlr->chip->cfg1;
2629 return 0;
2630 }
2631
2632 static int
2633 ata_marvell_pata_allocate(device_t dev)
2634 {
2635 struct ata_channel *ch = device_get_softc(dev);
2636
2637 /* setup the usual register normal pci style */
2638 if (ata_pci_allocate(dev))
2639 return ENXIO;
2640
2641 /* dont use 32 bit PIO transfers */
2642 ch->flags |= ATA_USE_16BIT;
2643
2644 return 0;
2645 }
2646
2647 static void
2648 ata_marvell_pata_setmode(device_t dev, int mode)
2649 {
2650 device_t gparent = GRANDPARENT(dev);
2651 struct ata_pci_controller *ctlr = device_get_softc(gparent);
2652 struct ata_device *atadev = device_get_softc(dev);
2653
2654 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
2655 mode = ata_check_80pin(dev, mode);
2656 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2657 atadev->mode = mode;
2658 }
2659
2660 static int
2661 ata_marvell_edma_chipinit(device_t dev)
2662 {
2663 struct ata_pci_controller *ctlr = device_get_softc(dev);
2664
2665 if (ata_setup_interrupt(dev))
2666 return ENXIO;
2667
2668 ctlr->r_type1 = SYS_RES_MEMORY;
2669 ctlr->r_rid1 = PCIR_BAR(0);
2670 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
2671 &ctlr->r_rid1, RF_ACTIVE)))
2672 return ENXIO;
2673
2674 /* mask all host controller interrupts */
2675 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000);
2676
2677 /* mask all PCI interrupts */
2678 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000);
2679
2680 ctlr->allocate = ata_marvell_edma_allocate;
2681 ctlr->reset = ata_marvell_edma_reset;
2682 ctlr->dmainit = ata_marvell_edma_dmainit;
2683 ctlr->setmode = ata_sata_setmode;
2684 ctlr->channels = ctlr->chip->cfg1;
2685
2686 /* clear host controller interrupts */
2687 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000);
2688 if (ctlr->chip->cfg1 > 4)
2689 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000);
2690
2691 /* clear PCI interrupts */
2692 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000);
2693
2694 /* unmask PCI interrupts we want */
2695 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff);
2696
2697 /* unmask host controller interrupts we want */
2698 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ |
2699 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25));
2700 return 0;
2701 }
2702
2703 static int
2704 ata_marvell_edma_allocate(device_t dev)
2705 {
2706 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2707 struct ata_channel *ch = device_get_softc(dev);
2708 u_int64_t work = ch->dma->work_bus;
2709 int i;
2710
2711 /* clear work area */
2712 bzero(ch->dma->work, 1024+256);
2713 bus_dmamap_sync(ch->dma->work_tag, ch->dma->work_map,
2714 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2715
2716 /* set legacy ATA resources */
2717 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
2718 ch->r_io[i].res = ctlr->r_res1;
2719 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch);
2720 }
2721 ch->r_io[ATA_CONTROL].res = ctlr->r_res1;
2722 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch);
2723 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1;
2724 ata_default_registers(dev);
2725
2726 /* set SATA resources */
2727 switch (ctlr->chip->cfg2) {
2728 case MV50XX:
2729 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2730 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch);
2731 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2732 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch);
2733 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2734 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch);
2735 break;
2736 case MV60XX:
2737 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2738 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch);
2739 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2740 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch);
2741 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2742 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch);
2743 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1;
2744 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch);
2745 break;
2746 }
2747
2748 ch->flags |= ATA_NO_SLAVE;
2749 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */
2750 ata_generic_hw(dev);
2751 ch->hw.begin_transaction = ata_marvell_edma_begin_transaction;
2752 ch->hw.end_transaction = ata_marvell_edma_end_transaction;
2753 ch->hw.status = ata_marvell_edma_status;
2754
2755 /* disable the EDMA machinery */
2756 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2757 DELAY(100000); /* SOS should poll for disabled */
2758
2759 /* set configuration to non-queued 128b read transfers stop on error */
2760 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13));
2761
2762 /* request queue base high */
2763 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32);
2764
2765 /* request queue in ptr */
2766 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
2767
2768 /* request queue out ptr */
2769 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0);
2770
2771 /* response queue base high */
2772 work += 1024;
2773 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32);
2774
2775 /* response queue in ptr */
2776 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0);
2777
2778 /* response queue out ptr */
2779 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
2780
2781 /* clear SATA error register */
2782 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2783
2784 /* clear any outstanding error interrupts */
2785 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2786
2787 /* unmask all error interrupts */
2788 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
2789
2790 /* enable EDMA machinery */
2791 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2792 return 0;
2793 }
2794
2795 static int
2796 ata_marvell_edma_status(device_t dev)
2797 {
2798 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2799 struct ata_channel *ch = device_get_softc(dev);
2800 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60);
2801 int shift = (ch->unit << 1) + (ch->unit > 3);
2802
2803 if (cause & (1 << shift)) {
2804
2805 /* clear interrupt(s) */
2806 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2807
2808 /* do we have any PHY events ? */
2809 ata_sata_phy_check_events(dev);
2810 }
2811
2812 /* do we have any device action ? */
2813 return (cause & (2 << shift));
2814 }
2815
2816 /* must be called with ATA channel locked and state_mtx held */
2817 static int
2818 ata_marvell_edma_begin_transaction(struct ata_request *request)
2819 {
2820 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2821 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2822 u_int32_t req_in;
2823 u_int8_t *bytep;
2824 int i, tag = 0x07;
2825 int dummy, error, slot;
2826
2827 /* only DMA R/W goes through the EMDA machine */
2828 if (request->u.ata.command != ATA_READ_DMA &&
2829 request->u.ata.command != ATA_WRITE_DMA) {
2830
2831 /* disable the EDMA machinery */
2832 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)
2833 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2834 return ata_begin_transaction(request);
2835 }
2836
2837 /* check for 48 bit access and convert if needed */
2838 ata_modify_if_48bit(request);
2839
2840 /* check sanity, setup SG list and DMA engine */
2841 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
2842 request->flags & ATA_R_READ, ch->dma->sg,
2843 &dummy))) {
2844 device_printf(request->dev, "setting up DMA failed\n");
2845 request->result = error;
2846 return ATA_OP_FINISHED;
2847 }
2848
2849 /* get next free request queue slot */
2850 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch));
2851 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f;
2852 bytep = (u_int8_t *)(ch->dma->work);
2853 bytep += (slot << 5);
2854
2855 /* fill in this request */
2856 le32enc(bytep + 0 * sizeof(u_int32_t),
2857 ch->dma->sg_bus & 0xffffffff);
2858 le32enc(bytep + 1 * sizeof(u_int32_t),
2859 (u_int64_t)ch->dma->sg_bus >> 32);
2860 le16enc(bytep + 4 * sizeof(u_int16_t),
2861 (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag << 1));
2862
2863 i = 10;
2864 bytep[i++] = (request->u.ata.count >> 8) & 0xff;
2865 bytep[i++] = 0x10 | ATA_COUNT;
2866 bytep[i++] = request->u.ata.count & 0xff;
2867 bytep[i++] = 0x10 | ATA_COUNT;
2868
2869 bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
2870 bytep[i++] = 0x10 | ATA_SECTOR;
2871 bytep[i++] = request->u.ata.lba & 0xff;
2872 bytep[i++] = 0x10 | ATA_SECTOR;
2873
2874 bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
2875 bytep[i++] = 0x10 | ATA_CYL_LSB;
2876 bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
2877 bytep[i++] = 0x10 | ATA_CYL_LSB;
2878
2879 bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
2880 bytep[i++] = 0x10 | ATA_CYL_MSB;
2881 bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
2882 bytep[i++] = 0x10 | ATA_CYL_MSB;
2883
2884 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf);
2885 bytep[i++] = 0x10 | ATA_DRIVE;
2886
2887 bytep[i++] = request->u.ata.command;
2888 bytep[i++] = 0x90 | ATA_COMMAND;
2889
2890 bus_dmamap_sync(ch->dma->work_tag, ch->dma->work_map,
2891 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2892
2893 /* enable EDMA machinery if needed */
2894 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) {
2895 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2896 while (!(ATA_INL(ctlr->r_res1,
2897 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
2898 DELAY(10);
2899 }
2900
2901 /* tell EDMA it has a new request */
2902 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f;
2903 req_in &= 0xfffffc00;
2904 req_in += (slot << 5);
2905 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in);
2906
2907 return ATA_OP_CONTINUES;
2908 }
2909
2910 /* must be called with ATA channel locked and state_mtx held */
2911 static int
2912 ata_marvell_edma_end_transaction(struct ata_request *request)
2913 {
2914 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2915 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2916 int offset = (ch->unit > 3 ? 0x30014 : 0x20014);
2917 u_int32_t icr = ATA_INL(ctlr->r_res1, offset);
2918 int res;
2919
2920 /* EDMA interrupt */
2921 if ((icr & (0x0001 << (ch->unit & 3)))) {
2922 struct ata_marvell_response *response;
2923 u_int32_t rsp_in, rsp_out;
2924 int slot;
2925
2926 /* stop timeout */
2927 callout_stop(&request->callout);
2928
2929 /* get response ptr's */
2930 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch));
2931 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch));
2932 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f;
2933 rsp_out &= 0xffffff00;
2934 rsp_out += (slot << 3);
2935 bus_dmamap_sync(ch->dma->work_tag, ch->dma->work_map,
2936 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2937 response = (struct ata_marvell_response *)
2938 (ch->dma->work + 1024 + (slot << 3));
2939
2940 /* record status for this request */
2941 request->status = response->dev_status;
2942 request->error = 0;
2943
2944 /* ack response */
2945 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out);
2946
2947 /* update progress */
2948 if (!(request->status & ATA_S_ERROR) &&
2949 !(request->flags & ATA_R_TIMEOUT))
2950 request->donecount = request->bytecount;
2951
2952 /* unload SG list */
2953 ch->dma->unload(ch->dev);
2954
2955 res = ATA_OP_FINISHED;
2956 }
2957
2958 /* legacy ATA interrupt */
2959 else {
2960 res = ata_end_transaction(request);
2961 }
2962
2963 /* ack interrupt */
2964 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3))));
2965 return res;
2966 }
2967
2968 static void
2969 ata_marvell_edma_reset(device_t dev)
2970 {
2971 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2972 struct ata_channel *ch = device_get_softc(dev);
2973
2974 /* disable the EDMA machinery */
2975 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2976 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
2977 DELAY(10);
2978
2979 /* clear SATA error register */
2980 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2981
2982 /* clear any outstanding error interrupts */
2983 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2984
2985 /* unmask all error interrupts */
2986 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
2987
2988 /* enable channel and test for devices */
2989 if (ata_sata_phy_reset(dev))
2990 ata_generic_reset(dev);
2991
2992 /* enable EDMA machinery */
2993 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2994 }
2995
2996 static void
2997 ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs,
2998 int error)
2999 {
3000 struct ata_dmasetprd_args *args = xsc;
3001 struct ata_marvell_dma_prdentry *prd = args->dmatab;
3002 int i;
3003
3004 if ((args->error = error))
3005 return;
3006
3007 for (i = 0; i < nsegs; i++) {
3008 prd[i].addrlo = htole32(segs[i].ds_addr);
3009 prd[i].count = htole32(segs[i].ds_len);
3010 prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32);
3011 prd[i].reserved = 0;
3012 }
3013 prd[i - 1].count |= htole32(ATA_DMA_EOT);
3014 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
3015 args->nsegs = nsegs;
3016 }
3017
3018 static void
3019 ata_marvell_edma_dmainit(device_t dev)
3020 {
3021 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3022 struct ata_channel *ch = device_get_softc(dev);
3023
3024 ata_dmainit(dev);
3025 if (ch->dma) {
3026 /* note start and stop are not used here */
3027 ch->dma->setprd = ata_marvell_edma_dmasetprd;
3028
3029 /* if 64bit support present adjust max address used */
3030 if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004)
3031 ch->dma->max_address = BUS_SPACE_MAXADDR;
3032
3033 /* chip does not reliably do 64K DMA transfers */
3034 ch->dma->max_iosize = 64 * DEV_BSIZE;
3035 }
3036 }
3037
3038
3039 /*
3040 * National chipset support functions
3041 */
3042 int
3043 ata_national_ident(device_t dev)
3044 {
3045 struct ata_pci_controller *ctlr = device_get_softc(dev);
3046
3047 /* this chip is a clone of the Cyrix chip, bugs and all */
3048 if (pci_get_devid(dev) == ATA_SC1100) {
3049 device_set_desc(dev, "National Geode SC1100 ATA33 controller");
3050 ctlr->chipinit = ata_national_chipinit;
3051 return 0;
3052 }
3053 return ENXIO;
3054 }
3055
3056 static int
3057 ata_national_chipinit(device_t dev)
3058 {
3059 struct ata_pci_controller *ctlr = device_get_softc(dev);
3060
3061 if (ata_setup_interrupt(dev))
3062 return ENXIO;
3063
3064 ctlr->setmode = ata_national_setmode;
3065 return 0;
3066 }
3067
3068 static void
3069 ata_national_setmode(device_t dev, int mode)
3070 {
3071 device_t gparent = GRANDPARENT(dev);
3072 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3073 struct ata_device *atadev = device_get_softc(dev);
3074 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
3075 u_int32_t piotiming[] =
3076 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
3077 0x00803020, 0x20102010, 0x00100010,
3078 0x00100010, 0x00100010, 0x00100010 };
3079 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
3080 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
3081 int error;
3082
3083 ch->dma->alignment = 16;
3084 ch->dma->max_iosize = 64 * DEV_BSIZE;
3085
3086 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
3087
3088 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3089
3090 if (bootverbose)
3091 device_printf(dev, "%s setting %s on National chip\n",
3092 (error) ? "failed" : "success", ata_mode2str(mode));
3093 if (!error) {
3094 if (mode >= ATA_UDMA0) {
3095 pci_write_config(gparent, 0x44 + (devno << 3),
3096 udmatiming[mode & ATA_MODE_MASK], 4);
3097 }
3098 else if (mode >= ATA_WDMA0) {
3099 pci_write_config(gparent, 0x44 + (devno << 3),
3100 dmatiming[mode & ATA_MODE_MASK], 4);
3101 }
3102 else {
3103 pci_write_config(gparent, 0x44 + (devno << 3),
3104 pci_read_config(gparent, 0x44 + (devno << 3), 4) |
3105 0x80000000, 4);
3106 }
3107 pci_write_config(gparent, 0x40 + (devno << 3),
3108 piotiming[ata_mode2idx(mode)], 4);
3109 atadev->mode = mode;
3110 }
3111 }
3112
3113
3114 /*
3115 * NetCell chipset support functions
3116 */
3117 int
3118 ata_netcell_ident(device_t dev)
3119 {
3120 struct ata_pci_controller *ctlr = device_get_softc(dev);
3121
3122 if (pci_get_devid(dev) == ATA_NETCELL_SR) {
3123 device_set_desc(dev, "Netcell SyncRAID SR3000/5000 RAID Controller");
3124 ctlr->chipinit = ata_netcell_chipinit;
3125 return 0;
3126 }
3127 return ENXIO;
3128 }
3129
3130 static int
3131 ata_netcell_chipinit(device_t dev)
3132 {
3133 struct ata_pci_controller *ctlr = device_get_softc(dev);
3134
3135 if (ata_generic_chipinit(dev))
3136 return ENXIO;
3137
3138 ctlr->allocate = ata_netcell_allocate;
3139 return 0;
3140 }
3141
3142 static int
3143 ata_netcell_allocate(device_t dev)
3144 {
3145 struct ata_channel *ch = device_get_softc(dev);
3146
3147 /* setup the usual register normal pci style */
3148 if (ata_pci_allocate(dev))
3149 return ENXIO;
3150
3151 /* the NetCell only supports 16 bit PIO transfers */
3152 ch->flags |= ATA_USE_16BIT;
3153
3154 return 0;
3155 }
3156
3157
3158 /*
3159 * nVidia chipset support functions
3160 */
3161 int
3162 ata_nvidia_ident(device_t dev)
3163 {
3164 struct ata_pci_controller *ctlr = device_get_softc(dev);
3165 static struct ata_chip_id ids[] =
3166 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nForce" },
3167 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2" },
3168 { ATA_NFORCE2_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2 Pro" },
3169 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" },
3170 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3" },
3171 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3 Pro" },
3172 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
3173 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
3174 { ATA_NFORCE_MCP04, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP" },
3175 { ATA_NFORCE_MCP04_S1, 0, 0, NV4, ATA_SA150, "nForce MCP" },
3176 { ATA_NFORCE_MCP04_S2, 0, 0, NV4, ATA_SA150, "nForce MCP" },
3177 { ATA_NFORCE_CK804, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce CK804" },
3178 { ATA_NFORCE_CK804_S1, 0, 0, NV4, ATA_SA300, "nForce CK804" },
3179 { ATA_NFORCE_CK804_S2, 0, 0, NV4, ATA_SA300, "nForce CK804" },
3180 { ATA_NFORCE_MCP51, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP51" },
3181 { ATA_NFORCE_MCP51_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
3182 { ATA_NFORCE_MCP51_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
3183 { ATA_NFORCE_MCP55, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP55" },
3184 { ATA_NFORCE_MCP55_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
3185 { ATA_NFORCE_MCP55_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
3186 { ATA_NFORCE_MCP61, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP61" },
3187 { ATA_NFORCE_MCP61_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
3188 { ATA_NFORCE_MCP61_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
3189 { ATA_NFORCE_MCP61_S3, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
3190 { ATA_NFORCE_MCP65, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP65" },
3191 { ATA_NFORCE_MCP67, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP67" },
3192 { ATA_NFORCE_MCP67_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" },
3193 { ATA_NFORCE_MCP67_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" },
3194 { ATA_NFORCE_MCP67_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" },
3195 { ATA_NFORCE_MCP67_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" },
3196 { ATA_NFORCE_MCP67_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" },
3197 { ATA_NFORCE_MCP67_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" },
3198 { ATA_NFORCE_MCP67_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" },
3199 { ATA_NFORCE_MCP67_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" },
3200 { ATA_NFORCE_MCP67_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" },
3201 { ATA_NFORCE_MCP67_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" },
3202 { ATA_NFORCE_MCP67_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" },
3203 { ATA_NFORCE_MCP67_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" },
3204 { ATA_NFORCE_MCP73, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP73" },
3205 { ATA_NFORCE_MCP73_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" },
3206 { ATA_NFORCE_MCP73_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" },
3207 { ATA_NFORCE_MCP73_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" },
3208 { ATA_NFORCE_MCP73_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" },
3209 { ATA_NFORCE_MCP73_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" },
3210 { ATA_NFORCE_MCP73_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" },
3211 { ATA_NFORCE_MCP73_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" },
3212 { ATA_NFORCE_MCP73_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" },
3213 { ATA_NFORCE_MCP73_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" },
3214 { ATA_NFORCE_MCP73_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" },
3215 { ATA_NFORCE_MCP73_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" },
3216 { ATA_NFORCE_MCP73_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" },
3217 { ATA_NFORCE_MCP77, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP77" },
3218 { 0, 0, 0, 0, 0, 0}} ;
3219
3220 if (!(ctlr->chip = ata_match_chip(dev, ids)))
3221 return ENXIO;
3222
3223 ata_set_desc(dev);
3224 if (ctlr->chip->cfg1 & NVAHCI)
3225 ctlr->chipinit = ata_ahci_chipinit;
3226 else
3227 ctlr->chipinit = ata_nvidia_chipinit;
3228 return 0;
3229 }
3230
3231 static int
3232 ata_nvidia_chipinit(device_t dev)
3233 {
3234 struct ata_pci_controller *ctlr = device_get_softc(dev);
3235
3236 if (ata_setup_interrupt(dev))
3237 return ENXIO;
3238
3239 if (ctlr->chip->max_dma >= ATA_SA150) {
3240 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1)
3241 ctlr->r_type2 = SYS_RES_IOPORT;
3242 else
3243 ctlr->r_type2 = SYS_RES_MEMORY;
3244 ctlr->r_rid2 = PCIR_BAR(5);
3245 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3246 &ctlr->r_rid2, RF_ACTIVE))) {
3247 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
3248
3249 ctlr->allocate = ata_nvidia_allocate;
3250 ctlr->reset = ata_nvidia_reset;
3251
3252 /* enable control access */
3253 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1);
3254
3255 if (ctlr->chip->cfg2 & NVQ) {
3256 /* clear interrupt status */
3257 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff);
3258
3259 /* enable device and PHY state change interrupts */
3260 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d);
3261
3262 /* disable NCQ support */
3263 ATA_OUTL(ctlr->r_res2, 0x0400,
3264 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9);
3265 }
3266 else {
3267 /* clear interrupt status */
3268 ATA_OUTB(ctlr->r_res2, offset, 0xff);
3269
3270 /* enable device and PHY state change interrupts */
3271 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd);
3272 }
3273 }
3274 ctlr->setmode = ata_sata_setmode;
3275 }
3276 else {
3277 /* disable prefetch, postwrite */
3278 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
3279 ctlr->setmode = ata_via_family_setmode;
3280 }
3281 return 0;
3282 }
3283
3284 static int
3285 ata_nvidia_allocate(device_t dev)
3286 {
3287 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3288 struct ata_channel *ch = device_get_softc(dev);
3289
3290 /* setup the usual register normal pci style */
3291 if (ata_pci_allocate(dev))
3292 return ENXIO;
3293
3294 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3295 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6);
3296 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3297 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6);
3298 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3299 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6);
3300
3301 ch->hw.status = ata_nvidia_status;
3302 ch->flags |= ATA_NO_SLAVE;
3303
3304 return 0;
3305 }
3306
3307 static int
3308 ata_nvidia_status(device_t dev)
3309 {
3310 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3311 struct ata_channel *ch = device_get_softc(dev);
3312 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
3313 int shift = ch->unit << (ctlr->chip->cfg2 & NVQ ? 4 : 2);
3314 u_int32_t istatus = ATA_INL(ctlr->r_res2, offset);
3315
3316 /* do we have any PHY events ? */
3317 if (istatus & (0x0c << shift))
3318 ata_sata_phy_check_events(dev);
3319
3320 /* clear interrupt(s) */
3321 ATA_OUTB(ctlr->r_res2, offset,
3322 (0x0f << shift) | (ctlr->chip->cfg2 & NVQ ? 0x00f000f0 : 0));
3323
3324 /* do we have any device action ? */
3325 return (istatus & (0x01 << shift));
3326 }
3327
3328 static void
3329 ata_nvidia_reset(device_t dev)
3330 {
3331 if (ata_sata_phy_reset(dev))
3332 ata_generic_reset(dev);
3333 }
3334
3335
3336 /*
3337 * Promise chipset support functions
3338 */
3339 #define ATA_PDC_APKT_OFFSET 0x00000010
3340 #define ATA_PDC_HPKT_OFFSET 0x00000040
3341 #define ATA_PDC_ASG_OFFSET 0x00000080
3342 #define ATA_PDC_LSG_OFFSET 0x000000c0
3343 #define ATA_PDC_HSG_OFFSET 0x00000100
3344 #define ATA_PDC_CHN_OFFSET 0x00000400
3345 #define ATA_PDC_BUF_BASE 0x00400000
3346 #define ATA_PDC_BUF_OFFSET 0x00100000
3347 #define ATA_PDC_MAX_HPKT 8
3348 #define ATA_PDC_WRITE_REG 0x00
3349 #define ATA_PDC_WRITE_CTL 0x0e
3350 #define ATA_PDC_WRITE_END 0x08
3351 #define ATA_PDC_WAIT_NBUSY 0x10
3352 #define ATA_PDC_WAIT_READY 0x18
3353 #define ATA_PDC_1B 0x20
3354 #define ATA_PDC_2B 0x40
3355
3356 struct host_packet {
3357 u_int32_t addr;
3358 TAILQ_ENTRY(host_packet) chain;
3359 };
3360
3361 struct ata_promise_sx4 {
3362 struct mtx mtx;
3363 TAILQ_HEAD(, host_packet) queue;
3364 int busy;
3365 };
3366
3367 int
3368 ata_promise_ident(device_t dev)
3369 {
3370 struct ata_pci_controller *ctlr = device_get_softc(dev);
3371 struct ata_chip_id *idx;
3372 static struct ata_chip_id ids[] =
3373 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "PDC20246" },
3374 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20262" },
3375 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20263" },
3376 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20265" },
3377 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20267" },
3378 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20268" },
3379 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "PDC20269" },
3380 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20270" },
3381 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "PDC20271" },
3382 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "PDC20275" },
3383 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "PDC20276" },
3384 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "PDC20277" },
3385 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "PDC20318" },
3386 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "PDC20319" },
3387 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20371" },
3388 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20375" },
3389 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20376" },
3390 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20377" },
3391 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20378" },
3392 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20379" },
3393 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" },
3394 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" },
3395 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" },
3396 { ATA_PDC20771, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" },
3397 { ATA_PDC40775, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" },
3398 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20617" },
3399 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20618" },
3400 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20619" },
3401 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20620" },
3402 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "PDC20621" },
3403 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "PDC20622" },
3404 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40518" },
3405 { ATA_PDC40519, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40519" },
3406 { ATA_PDC40718, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40718" },
3407 { ATA_PDC40719, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40719" },
3408 { ATA_PDC40779, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40779" },
3409 { 0, 0, 0, 0, 0, 0}};
3410 char buffer[64];
3411 uintptr_t devid = 0;
3412
3413 if (!(idx = ata_match_chip(dev, ids)))
3414 return ENXIO;
3415
3416 /* if we are on a SuperTrak SX6000 dont attach */
3417 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
3418 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
3419 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
3420 devid == ATA_I960RM)
3421 return ENXIO;
3422
3423 strcpy(buffer, "Promise ");
3424 strcat(buffer, idx->text);
3425
3426 /* if we are on a FastTrak TX4, adjust the interrupt resource */
3427 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
3428 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
3429 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
3430 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) {
3431 static long start = 0, end = 0;
3432
3433 if (pci_get_slot(dev) == 1) {
3434 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
3435 strcat(buffer, " (channel 0+1)");
3436 }
3437 else if (pci_get_slot(dev) == 2 && start && end) {
3438 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
3439 strcat(buffer, " (channel 2+3)");
3440 }
3441 else {
3442 start = end = 0;
3443 }
3444 }
3445 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
3446 device_set_desc_copy(dev, buffer);
3447 ctlr->chip = idx;
3448 ctlr->chipinit = ata_promise_chipinit;
3449 return 0;
3450 }
3451
3452 static int
3453 ata_promise_chipinit(device_t dev)
3454 {
3455 struct ata_pci_controller *ctlr = device_get_softc(dev);
3456 int fake_reg, stat_reg;
3457
3458 if (ata_setup_interrupt(dev))
3459 return ENXIO;
3460
3461 switch (ctlr->chip->cfg1) {
3462 case PRNEW:
3463 /* setup clocks */
3464 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a);
3465
3466 ctlr->dmainit = ata_promise_dmainit;
3467 /* FALLTHROUGH */
3468
3469 case PROLD:
3470 /* enable burst mode */
3471 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01);
3472 ctlr->allocate = ata_promise_allocate;
3473 ctlr->setmode = ata_promise_setmode;
3474 return 0;
3475
3476 case PRTX:
3477 ctlr->allocate = ata_promise_tx2_allocate;
3478 ctlr->setmode = ata_promise_setmode;
3479 return 0;
3480
3481 case PRMIO:
3482 ctlr->r_type1 = SYS_RES_MEMORY;
3483 ctlr->r_rid1 = PCIR_BAR(4);
3484 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
3485 &ctlr->r_rid1, RF_ACTIVE)))
3486 goto failnfree;
3487
3488 ctlr->r_type2 = SYS_RES_MEMORY;
3489 ctlr->r_rid2 = PCIR_BAR(3);
3490 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3491 &ctlr->r_rid2, RF_ACTIVE)))
3492 goto failnfree;
3493
3494 if (ctlr->chip->cfg2 == PRSX4X) {
3495 struct ata_promise_sx4 *hpkt;
3496 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080);
3497
3498 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3499 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL,
3500 ata_promise_sx4_intr, ctlr, &ctlr->handle)) {
3501 device_printf(dev, "unable to setup interrupt\n");
3502 goto failnfree;
3503 }
3504
3505 /* print info about cache memory */
3506 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n",
3507 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4,
3508 ((dimm >> 24) & 0xff),
3509 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ?
3510 " ECC enabled" : "" );
3511
3512 /* adjust cache memory parameters */
3513 ATA_OUTL(ctlr->r_res2, 0x000c000c,
3514 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000));
3515
3516 /* setup host packet controls */
3517 hpkt = malloc(sizeof(struct ata_promise_sx4),
3518 M_TEMP, M_NOWAIT | M_ZERO);
3519 mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF);
3520 TAILQ_INIT(&hpkt->queue);
3521 hpkt->busy = 0;
3522 ctlr->chipset_data = hpkt;
3523 ctlr->allocate = ata_promise_mio_allocate;
3524 ctlr->reset = ata_promise_mio_reset;
3525 ctlr->dmainit = ata_promise_mio_dmainit;
3526 ctlr->setmode = ata_promise_setmode;
3527 ctlr->channels = 4;
3528 return 0;
3529 }
3530
3531 /* mio type controllers need an interrupt intercept */
3532 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3533 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL,
3534 ata_promise_mio_intr, ctlr, &ctlr->handle)) {
3535 device_printf(dev, "unable to setup interrupt\n");
3536 goto failnfree;
3537 }
3538
3539 switch (ctlr->chip->cfg2) {
3540 case PRPATA:
3541 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) +
3542 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2;
3543 goto sata150;
3544 case PRCMBO:
3545 ctlr->channels = 3;
3546 goto sata150;
3547 case PRSATA:
3548 ctlr->channels = 4;
3549 sata150:
3550 fake_reg = 0x60;
3551 stat_reg = 0x6c;
3552 break;
3553
3554 case PRCMBO2:
3555 ctlr->channels = 3;
3556 goto sataii;
3557 case PRSATA2:
3558 default:
3559 ctlr->channels = 4;
3560 sataii:
3561 fake_reg = 0x54;
3562 stat_reg = 0x60;
3563 break;
3564 }
3565
3566 /* prime fake interrupt register */
3567 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3568
3569 /* clear SATA status and unmask interrupts */
3570 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff);
3571
3572 /* enable "long burst lenght" on gen2 chips */
3573 if ((ctlr->chip->cfg2 == PRSATA2) || (ctlr->chip->cfg2 == PRCMBO2))
3574 ATA_OUTL(ctlr->r_res2, 0x44, ATA_INL(ctlr->r_res2, 0x44) | 0x2000);
3575
3576 ctlr->allocate = ata_promise_mio_allocate;
3577 ctlr->reset = ata_promise_mio_reset;
3578 ctlr->dmainit = ata_promise_mio_dmainit;
3579 ctlr->setmode = ata_promise_mio_setmode;
3580
3581 return 0;
3582 }
3583
3584 failnfree:
3585 if (ctlr->r_res2)
3586 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
3587 if (ctlr->r_res1)
3588 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1);
3589 return ENXIO;
3590 }
3591
3592 static int
3593 ata_promise_allocate(device_t dev)
3594 {
3595 struct ata_channel *ch = device_get_softc(dev);
3596
3597 if (ata_pci_allocate(dev))
3598 return ENXIO;
3599
3600 ch->hw.status = ata_promise_status;
3601 return 0;
3602 }
3603
3604 static int
3605 ata_promise_status(device_t dev)
3606 {
3607 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3608 struct ata_channel *ch = device_get_softc(dev);
3609
3610 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) {
3611 return ata_pci_status(dev);
3612 }
3613 return 0;
3614 }
3615
3616 static int
3617 ata_promise_dmastart(device_t dev)
3618 {
3619 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3620 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3621 struct ata_device *atadev = device_get_softc(dev);
3622
3623 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3624 ATA_OUTB(ctlr->r_res1, 0x11,
3625 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02));
3626 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20,
3627 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) |
3628 (ch->dma->cur_iosize >> 1));
3629 }
3630 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) |
3631 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
3632 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus);
3633 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3634 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) |
3635 ATA_BMCMD_START_STOP);
3636 ch->flags |= ATA_DMA_ACTIVE;
3637 return 0;
3638 }
3639
3640 static int
3641 ata_promise_dmastop(device_t dev)
3642 {
3643 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3644 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3645 struct ata_device *atadev = device_get_softc(dev);
3646 int error;
3647
3648 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3649 ATA_OUTB(ctlr->r_res1, 0x11,
3650 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02));
3651 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0);
3652 }
3653 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT);
3654 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3655 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3656 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3657 ch->flags &= ~ATA_DMA_ACTIVE;
3658 return error;
3659 }
3660
3661 static void
3662 ata_promise_dmareset(device_t dev)
3663 {
3664 struct ata_channel *ch = device_get_softc(dev);
3665
3666 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3667 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3668 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3669 ch->flags &= ~ATA_DMA_ACTIVE;
3670 }
3671
3672 static void
3673 ata_promise_dmainit(device_t dev)
3674 {
3675 struct ata_channel *ch = device_get_softc(dev);
3676
3677 ata_dmainit(dev);
3678 if (ch->dma) {
3679 ch->dma->start = ata_promise_dmastart;
3680 ch->dma->stop = ata_promise_dmastop;
3681 ch->dma->reset = ata_promise_dmareset;
3682 }
3683 }
3684
3685 static void
3686 ata_promise_setmode(device_t dev, int mode)
3687 {
3688 device_t gparent = GRANDPARENT(dev);
3689 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3690 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3691 struct ata_device *atadev = device_get_softc(dev);
3692 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
3693 int error;
3694 u_int32_t timings[][2] = {
3695 /* PROLD PRNEW mode */
3696 { 0x004ff329, 0x004fff2f }, /* PIO 0 */
3697 { 0x004fec25, 0x004ff82a }, /* PIO 1 */
3698 { 0x004fe823, 0x004ff026 }, /* PIO 2 */
3699 { 0x004fe622, 0x004fec24 }, /* PIO 3 */
3700 { 0x004fe421, 0x004fe822 }, /* PIO 4 */
3701 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */
3702 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */
3703 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */
3704 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */
3705 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */
3706 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */
3707 { 0, 0x00424ef6 }, /* UDMA 3 */
3708 { 0, 0x004127f3 }, /* UDMA 4 */
3709 { 0, 0x004127f3 } /* UDMA 5 */
3710 };
3711
3712 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
3713
3714 switch (ctlr->chip->cfg1) {
3715 case PROLD:
3716 case PRNEW:
3717 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) &
3718 (ch->unit ? 1 << 11 : 1 << 10))) {
3719 ata_print_cable(dev, "controller");
3720 mode = ATA_UDMA2;
3721 }
3722 if (ata_atapi(dev) && mode > ATA_PIO_MAX)
3723 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
3724 break;
3725
3726 case PRTX:
3727 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3728 if (mode > ATA_UDMA2 &&
3729 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) {
3730 ata_print_cable(dev, "controller");
3731 mode = ATA_UDMA2;
3732 }
3733 break;
3734
3735 case PRMIO:
3736 if (mode > ATA_UDMA2 &&
3737 (ATA_INL(ctlr->r_res2,
3738 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) +
3739 (ch->unit << 7)) & 0x01000000)) {
3740 ata_print_cable(dev, "controller");
3741 mode = ATA_UDMA2;
3742 }
3743 break;
3744 }
3745
3746 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3747
3748 if (bootverbose)
3749 device_printf(dev, "%ssetting %s on %s chip\n",
3750 (error) ? "FAILURE " : "",
3751 ata_mode2str(mode), ctlr->chip->text);
3752 if (!error) {
3753 if (ctlr->chip->cfg1 < PRTX)
3754 pci_write_config(gparent, 0x60 + (devno << 2),
3755 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
3756 atadev->mode = mode;
3757 }
3758 return;
3759 }
3760
3761 static int
3762 ata_promise_tx2_allocate(device_t dev)
3763 {
3764 struct ata_channel *ch = device_get_softc(dev);
3765
3766 if (ata_pci_allocate(dev))
3767 return ENXIO;
3768
3769 ch->hw.status = ata_promise_tx2_status;
3770 return 0;
3771 }
3772
3773 static int
3774 ata_promise_tx2_status(device_t dev)
3775 {
3776 struct ata_channel *ch = device_get_softc(dev);
3777
3778 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3779 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
3780 return ata_pci_status(dev);
3781 }
3782 return 0;
3783 }
3784
3785 static int
3786 ata_promise_mio_allocate(device_t dev)
3787 {
3788 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3789 struct ata_channel *ch = device_get_softc(dev);
3790 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0;
3791 int i;
3792
3793 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
3794 ch->r_io[i].res = ctlr->r_res2;
3795 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7);
3796 }
3797 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
3798 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7);
3799 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
3800 ata_default_registers(dev);
3801 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) ||
3802 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2)) {
3803 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3804 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8);
3805 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3806 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8);
3807 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3808 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8);
3809 ch->flags |= ATA_NO_SLAVE;
3810 }
3811 ch->flags |= ATA_USE_16BIT;
3812
3813 ata_generic_hw(dev);
3814 if (ctlr->chip->cfg2 & PRSX4X) {
3815 ch->hw.command = ata_promise_sx4_command;
3816 }
3817 else {
3818 ch->hw.command = ata_promise_mio_command;
3819 ch->hw.status = ata_promise_mio_status;
3820 }
3821 return 0;
3822 }
3823
3824 static void
3825 ata_promise_mio_intr(void *data)
3826 {
3827 struct ata_pci_controller *ctlr = data;
3828 struct ata_channel *ch;
3829 u_int32_t vector;
3830 int unit, fake_reg;
3831
3832 switch (ctlr->chip->cfg2) {
3833 case PRPATA:
3834 case PRCMBO:
3835 case PRSATA:
3836 fake_reg = 0x60;
3837 break;
3838 case PRCMBO2:
3839 case PRSATA2:
3840 default:
3841 fake_reg = 0x54;
3842 break;
3843 }
3844
3845 /*
3846 * since reading interrupt status register on early "mio" chips
3847 * clears the status bits we cannot read it for each channel later on
3848 * in the generic interrupt routine.
3849 * store the bits in an unused register in the chip so we can read
3850 * it from there safely to get around this "feature".
3851 */
3852 vector = ATA_INL(ctlr->r_res2, 0x040);
3853 ATA_OUTL(ctlr->r_res2, 0x040, vector);
3854 ATA_OUTL(ctlr->r_res2, fake_reg, vector);
3855
3856 for (unit = 0; unit < ctlr->channels; unit++) {
3857 if ((ch = ctlr->interrupt[unit].argument))
3858 ctlr->interrupt[unit].function(ch);
3859 }
3860
3861 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3862 }
3863
3864 static int
3865 ata_promise_mio_status(device_t dev)
3866 {
3867 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3868 struct ata_channel *ch = device_get_softc(dev);
3869 struct ata_connect_task *tp;
3870 u_int32_t fake_reg, stat_reg, vector, status;
3871
3872 switch (ctlr->chip->cfg2) {
3873 case PRPATA:
3874 case PRCMBO:
3875 case PRSATA:
3876 fake_reg = 0x60;
3877 stat_reg = 0x6c;
3878 break;
3879 case PRCMBO2:
3880 case PRSATA2:
3881 default:
3882 fake_reg = 0x54;
3883 stat_reg = 0x60;
3884 break;
3885 }
3886
3887 /* read and acknowledge interrupt */
3888 vector = ATA_INL(ctlr->r_res2, fake_reg);
3889
3890 /* read and clear interface status */
3891 status = ATA_INL(ctlr->r_res2, stat_reg);
3892 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit));
3893
3894 /* check for and handle disconnect events */
3895 if ((status & (0x00000001 << ch->unit)) &&
3896 (tp = (struct ata_connect_task *)
3897 malloc(sizeof(struct ata_connect_task),
3898 M_ATA, M_NOWAIT | M_ZERO))) {
3899
3900 if (bootverbose)
3901 device_printf(ch->dev, "DISCONNECT requested\n");
3902 tp->action = ATA_C_DETACH;
3903 tp->dev = ch->dev;
3904 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3905 taskqueue_enqueue(taskqueue_thread, &tp->task);
3906 }
3907
3908 /* check for and handle connect events */
3909 if ((status & (0x00000010 << ch->unit)) &&
3910 (tp = (struct ata_connect_task *)
3911 malloc(sizeof(struct ata_connect_task),
3912 M_ATA, M_NOWAIT | M_ZERO))) {
3913
3914 if (bootverbose)
3915 device_printf(ch->dev, "CONNECT requested\n");
3916 tp->action = ATA_C_ATTACH;
3917 tp->dev = ch->dev;
3918 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3919 taskqueue_enqueue(taskqueue_thread, &tp->task);
3920 }
3921
3922 /* do we have any device action ? */
3923 return (vector & (1 << (ch->unit + 1)));
3924 }
3925
3926 static int
3927 ata_promise_mio_command(struct ata_request *request)
3928 {
3929 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
3930 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
3931 u_int32_t *wordp = (u_int32_t *)ch->dma->work;
3932
3933 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001);
3934
3935 /* XXX SOS add ATAPI commands support later */
3936 switch (request->u.ata.command) {
3937 default:
3938 return ata_generic_command(request);
3939
3940 case ATA_READ_DMA:
3941 case ATA_READ_DMA48:
3942 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24));
3943 break;
3944
3945 case ATA_WRITE_DMA:
3946 case ATA_WRITE_DMA48:
3947 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24));
3948 break;
3949 }
3950 wordp[1] = htole32(ch->dma->sg_bus);
3951 wordp[2] = 0;
3952 ata_promise_apkt((u_int8_t*)wordp, request);
3953
3954 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma->work_bus);
3955 return 0;
3956 }
3957
3958 static void
3959 ata_promise_mio_reset(device_t dev)
3960 {
3961 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3962 struct ata_channel *ch = device_get_softc(dev);
3963 struct ata_promise_sx4 *hpktp;
3964
3965 switch (ctlr->chip->cfg2) {
3966 case PRSX4X:
3967
3968 /* softreset channel ATA module */
3969 hpktp = ctlr->chipset_data;
3970 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1);
3971 ata_udelay(1000);
3972 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7),
3973 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) &
3974 ~0x00003f9f) | (ch->unit + 1));
3975
3976 /* softreset HOST module */ /* XXX SOS what about other outstandings */
3977 mtx_lock(&hpktp->mtx);
3978 ATA_OUTL(ctlr->r_res2, 0xc012c,
3979 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11));
3980 DELAY(10);
3981 ATA_OUTL(ctlr->r_res2, 0xc012c,
3982 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f));
3983 hpktp->busy = 0;
3984 mtx_unlock(&hpktp->mtx);
3985 ata_generic_reset(dev);
3986 break;
3987
3988 case PRPATA:
3989 case PRCMBO:
3990 case PRSATA:
3991 if ((ctlr->chip->cfg2 == PRSATA) ||
3992 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
3993
3994 /* mask plug/unplug intr */
3995 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit));
3996 }
3997
3998 /* softreset channels ATA module */
3999 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
4000 ata_udelay(10000);
4001 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
4002 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
4003 ~0x00003f9f) | (ch->unit + 1));
4004
4005 if ((ctlr->chip->cfg2 == PRSATA) ||
4006 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
4007
4008 if (ata_sata_phy_reset(dev))
4009 ata_generic_reset(dev);
4010
4011 /* reset and enable plug/unplug intr */
4012 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit));
4013 }
4014 else
4015 ata_generic_reset(dev);
4016 break;
4017
4018 case PRCMBO2:
4019 case PRSATA2:
4020 if ((ctlr->chip->cfg2 == PRSATA2) ||
4021 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
4022 /* set portmultiplier port */
4023 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f);
4024
4025 /* mask plug/unplug intr */
4026 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit));
4027 }
4028
4029 /* softreset channels ATA module */
4030 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
4031 ata_udelay(10000);
4032 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
4033 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
4034 ~0x00003f9f) | (ch->unit + 1));
4035
4036 if ((ctlr->chip->cfg2 == PRSATA2) ||
4037 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
4038
4039 /* set PHY mode to "improved" */
4040 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8),
4041 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) &
4042 ~0x00000003) | 0x00000001);
4043
4044 if (ata_sata_phy_reset(dev))
4045 ata_generic_reset(dev);
4046
4047 /* reset and enable plug/unplug intr */
4048 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit));
4049
4050 /* set portmultiplier port */
4051 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00);
4052 }
4053 else
4054 ata_generic_reset(dev);
4055 break;
4056
4057 }
4058 }
4059
4060 static void
4061 ata_promise_mio_dmainit(device_t dev)
4062 {
4063 struct ata_channel *ch = device_get_softc(dev);
4064
4065 /* note start and stop are not used here */
4066 ata_dmainit(dev);
4067 if (ch->dma)
4068 ch->dma->setprd = ata_promise_mio_setprd;
4069 }
4070
4071
4072 #define MAXLASTSGSIZE (32 * sizeof(u_int32_t))
4073 static void
4074 ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
4075 {
4076 struct ata_dmasetprd_args *args = xsc;
4077 struct ata_dma_prdentry *prd = args->dmatab;
4078 int i;
4079
4080 if ((args->error = error))
4081 return;
4082
4083 for (i = 0; i < nsegs; i++) {
4084 prd[i].addr = htole32(segs[i].ds_addr);
4085 prd[i].count = htole32(segs[i].ds_len);
4086 }
4087 if (segs[i - 1].ds_len > MAXLASTSGSIZE) {
4088 //printf("split last SG element of %u\n", segs[i - 1].ds_len);
4089 prd[i - 1].count = htole32(segs[i - 1].ds_len - MAXLASTSGSIZE);
4090 prd[i].count = htole32(MAXLASTSGSIZE);
4091 prd[i].addr = htole32(segs[i - 1].ds_addr +
4092 (segs[i - 1].ds_len - MAXLASTSGSIZE));
4093 nsegs++;
4094 i++;
4095 }
4096 prd[i - 1].count |= htole32(ATA_DMA_EOT);
4097 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
4098 args->nsegs = nsegs;
4099 }
4100
4101 static void
4102 ata_promise_mio_setmode(device_t dev, int mode)
4103 {
4104 device_t gparent = GRANDPARENT(dev);
4105 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4106 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4107
4108 if ( (ctlr->chip->cfg2 == PRSATA) ||
4109 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2)) ||
4110 (ctlr->chip->cfg2 == PRSATA2) ||
4111 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2)))
4112 ata_sata_setmode(dev, mode);
4113 else
4114 ata_promise_setmode(dev, mode);
4115 }
4116
4117 static void
4118 ata_promise_sx4_intr(void *data)
4119 {
4120 struct ata_pci_controller *ctlr = data;
4121 struct ata_channel *ch;
4122 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480);
4123 int unit;
4124
4125 for (unit = 0; unit < ctlr->channels; unit++) {
4126 if (vector & (1 << (unit + 1)))
4127 if ((ch = ctlr->interrupt[unit].argument))
4128 ctlr->interrupt[unit].function(ch);
4129 if (vector & (1 << (unit + 5)))
4130 if ((ch = ctlr->interrupt[unit].argument))
4131 ata_promise_queue_hpkt(ctlr,
4132 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
4133 ATA_PDC_HPKT_OFFSET));
4134 if (vector & (1 << (unit + 9))) {
4135 ata_promise_next_hpkt(ctlr);
4136 if ((ch = ctlr->interrupt[unit].argument))
4137 ctlr->interrupt[unit].function(ch);
4138 }
4139 if (vector & (1 << (unit + 13))) {
4140 ata_promise_next_hpkt(ctlr);
4141 if ((ch = ctlr->interrupt[unit].argument))
4142 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4143 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
4144 ATA_PDC_APKT_OFFSET));
4145 }
4146 }
4147 }
4148
4149 static int
4150 ata_promise_sx4_command(struct ata_request *request)
4151 {
4152 device_t gparent = GRANDPARENT(request->dev);
4153 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4154 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4155 struct ata_dma_prdentry *prd = ch->dma->sg;
4156 caddr_t window = rman_get_virtual(ctlr->r_res1);
4157 u_int32_t *wordp;
4158 int i, idx, length = 0;
4159
4160 /* XXX SOS add ATAPI commands support later */
4161 switch (request->u.ata.command) {
4162
4163 default:
4164 return -1;
4165
4166 case ATA_ATA_IDENTIFY:
4167 case ATA_READ:
4168 case ATA_READ48:
4169 case ATA_READ_MUL:
4170 case ATA_READ_MUL48:
4171 case ATA_WRITE:
4172 case ATA_WRITE48:
4173 case ATA_WRITE_MUL:
4174 case ATA_WRITE_MUL48:
4175 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
4176 return ata_generic_command(request);
4177
4178 case ATA_SETFEATURES:
4179 case ATA_FLUSHCACHE:
4180 case ATA_FLUSHCACHE48:
4181 case ATA_SLEEP:
4182 case ATA_SET_MULTI:
4183 wordp = (u_int32_t *)
4184 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
4185 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24));
4186 wordp[1] = 0;
4187 wordp[2] = 0;
4188 ata_promise_apkt((u_int8_t *)wordp, request);
4189 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
4190 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
4191 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4192 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET));
4193 return 0;
4194
4195 case ATA_READ_DMA:
4196 case ATA_READ_DMA48:
4197 case ATA_WRITE_DMA:
4198 case ATA_WRITE_DMA48:
4199 wordp = (u_int32_t *)
4200 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET);
4201 i = idx = 0;
4202 do {
4203 wordp[idx++] = prd[i].addr;
4204 wordp[idx++] = prd[i].count;
4205 length += (prd[i].count & ~ATA_DMA_EOT);
4206 } while (!(prd[i++].count & ATA_DMA_EOT));
4207
4208 wordp = (u_int32_t *)
4209 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET);
4210 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
4211 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
4212
4213 wordp = (u_int32_t *)
4214 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET);
4215 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
4216 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
4217
4218 wordp = (u_int32_t *)
4219 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET);
4220 if (request->flags & ATA_R_READ)
4221 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24));
4222 if (request->flags & ATA_R_WRITE)
4223 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24));
4224 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET);
4225 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET);
4226 wordp[3] = 0;
4227
4228 wordp = (u_int32_t *)
4229 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
4230 if (request->flags & ATA_R_READ)
4231 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24));
4232 if (request->flags & ATA_R_WRITE)
4233 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24));
4234 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET);
4235 wordp[2] = 0;
4236 ata_promise_apkt((u_int8_t *)wordp, request);
4237 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
4238
4239 if (request->flags & ATA_R_READ) {
4240 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001);
4241 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001);
4242 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4243 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET));
4244 }
4245 if (request->flags & ATA_R_WRITE) {
4246 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001);
4247 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001);
4248 ata_promise_queue_hpkt(ctlr,
4249 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET));
4250 }
4251 return 0;
4252 }
4253 }
4254
4255 static int
4256 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request)
4257 {
4258 struct ata_device *atadev = device_get_softc(request->dev);
4259 int i = 12;
4260
4261 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE;
4262 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit;
4263 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL;
4264 bytep[i++] = ATA_A_4BIT;
4265
4266 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
4267 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE;
4268 bytep[i++] = request->u.ata.feature >> 8;
4269 bytep[i++] = request->u.ata.feature;
4270 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT;
4271 bytep[i++] = request->u.ata.count >> 8;
4272 bytep[i++] = request->u.ata.count;
4273 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR;
4274 bytep[i++] = request->u.ata.lba >> 24;
4275 bytep[i++] = request->u.ata.lba;
4276 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
4277 bytep[i++] = request->u.ata.lba >> 32;
4278 bytep[i++] = request->u.ata.lba >> 8;
4279 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
4280 bytep[i++] = request->u.ata.lba >> 40;
4281 bytep[i++] = request->u.ata.lba >> 16;
4282 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
4283 bytep[i++] = ATA_D_LBA | atadev->unit;
4284 }
4285 else {
4286 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE;
4287 bytep[i++] = request->u.ata.feature;
4288 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT;
4289 bytep[i++] = request->u.ata.count;
4290 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR;
4291 bytep[i++] = request->u.ata.lba;
4292 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
4293 bytep[i++] = request->u.ata.lba >> 8;
4294 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
4295 bytep[i++] = request->u.ata.lba >> 16;
4296 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
4297 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) |
4298 ATA_D_IBM | atadev->unit | ((request->u.ata.lba >> 24)&0xf);
4299 }
4300 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND;
4301 bytep[i++] = request->u.ata.command;
4302 return i;
4303 }
4304
4305 static void
4306 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt)
4307 {
4308 struct ata_promise_sx4 *hpktp = ctlr->chipset_data;
4309
4310 mtx_lock(&hpktp->mtx);
4311 if (hpktp->busy) {
4312 struct host_packet *hp =
4313 malloc(sizeof(struct host_packet), M_TEMP, M_NOWAIT | M_ZERO);
4314 hp->addr = hpkt;
4315 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain);
4316 }
4317 else {
4318 hpktp->busy = 1;
4319 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt);
4320 }
4321 mtx_unlock(&hpktp->mtx);
4322 }
4323
4324 static void
4325 ata_promise_next_hpkt(struct ata_pci_controller *ctlr)
4326 {
4327 struct ata_promise_sx4 *hpktp = ctlr->chipset_data;
4328 struct host_packet *hp;
4329
4330 mtx_lock(&hpktp->mtx);
4331 if ((hp = TAILQ_FIRST(&hpktp->queue))) {
4332 TAILQ_REMOVE(&hpktp->queue, hp, chain);
4333 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr);
4334 free(hp, M_TEMP);
4335 }
4336 else
4337 hpktp->busy = 0;
4338 mtx_unlock(&hpktp->mtx);
4339 }
4340
4341
4342 /*
4343 * ServerWorks chipset support functions
4344 */
4345 int
4346 ata_serverworks_ident(device_t dev)
4347 {
4348 struct ata_pci_controller *ctlr = device_get_softc(dev);
4349 static struct ata_chip_id ids[] =
4350 {{ ATA_ROSB4, 0x00, SWKS33, 0, ATA_UDMA2, "ROSB4" },
4351 { ATA_CSB5, 0x92, SWKS100, 0, ATA_UDMA5, "CSB5" },
4352 { ATA_CSB5, 0x00, SWKS66, 0, ATA_UDMA4, "CSB5" },
4353 { ATA_CSB6, 0x00, SWKS100, 0, ATA_UDMA5, "CSB6" },
4354 { ATA_CSB6_1, 0x00, SWKS66, 0, ATA_UDMA4, "CSB6" },
4355 { ATA_HT1000, 0x00, SWKS100, 0, ATA_UDMA5, "HT1000" },
4356 { ATA_HT1000_S1, 0x00, SWKSMIO, 4, ATA_SA150, "HT1000" },
4357 { ATA_HT1000_S2, 0x00, SWKSMIO, 4, ATA_SA150, "HT1000" },
4358 { ATA_K2, 0x00, SWKSMIO, 4, ATA_SA150, "K2" },
4359 { ATA_FRODO4, 0x00, SWKSMIO, 4, ATA_SA150, "Frodo4" },
4360 { ATA_FRODO8, 0x00, SWKSMIO, 8, ATA_SA150, "Frodo8" },
4361 { 0, 0, 0, 0, 0, 0}};
4362
4363 if (!(ctlr->chip = ata_match_chip(dev, ids)))
4364 return ENXIO;
4365
4366 ata_set_desc(dev);
4367 ctlr->chipinit = ata_serverworks_chipinit;
4368 return 0;
4369 }
4370
4371 static int
4372 ata_serverworks_chipinit(device_t dev)
4373 {
4374 struct ata_pci_controller *ctlr = device_get_softc(dev);
4375
4376 if (ata_setup_interrupt(dev))
4377 return ENXIO;
4378
4379 if (ctlr->chip->cfg1 == SWKSMIO) {
4380 ctlr->r_type2 = SYS_RES_MEMORY;
4381 ctlr->r_rid2 = PCIR_BAR(5);
4382 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4383 &ctlr->r_rid2, RF_ACTIVE)))
4384 return ENXIO;
4385
4386 ctlr->channels = ctlr->chip->cfg2;
4387 ctlr->allocate = ata_serverworks_allocate;
4388 ctlr->setmode = ata_sata_setmode;
4389 return 0;
4390 }
4391 else if (ctlr->chip->cfg1 == SWKS33) {
4392 device_t *children;
4393 int nchildren, i;
4394
4395 /* locate the ISA part in the southbridge and enable UDMA33 */
4396 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
4397 for (i = 0; i < nchildren; i++) {
4398 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
4399 pci_write_config(children[i], 0x64,
4400 (pci_read_config(children[i], 0x64, 4) &
4401 ~0x00002000) | 0x00004000, 4);
4402 break;
4403 }
4404 }
4405 free(children, M_TEMP);
4406 }
4407 }
4408 else {
4409 pci_write_config(dev, 0x5a,
4410 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
4411 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1);
4412 }
4413 ctlr->setmode = ata_serverworks_setmode;
4414 return 0;
4415 }
4416
4417 static int
4418 ata_serverworks_allocate(device_t dev)
4419 {
4420 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4421 struct ata_channel *ch = device_get_softc(dev);
4422 int ch_offset;
4423 int i;
4424
4425 ch_offset = ch->unit * 0x100;
4426
4427 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
4428 ch->r_io[i].res = ctlr->r_res2;
4429
4430 /* setup ATA registers */
4431 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
4432 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04;
4433 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
4434 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
4435 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
4436 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
4437 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
4438 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c;
4439 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20;
4440 ata_default_registers(dev);
4441
4442 /* setup DMA registers */
4443 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30;
4444 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32;
4445 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34;
4446
4447 /* setup SATA registers */
4448 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40;
4449 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44;
4450 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48;
4451
4452 ch->flags |= ATA_NO_SLAVE;
4453 ata_pci_hw(dev);
4454 ch->hw.tf_read = ata_serverworks_tf_read;
4455 ch->hw.tf_write = ata_serverworks_tf_write;
4456
4457 /* chip does not reliably do 64K DMA transfers */
4458 if (ch->dma)
4459 ch->dma->max_iosize = 64 * DEV_BSIZE;
4460
4461 return 0;
4462 }
4463
4464 static void
4465 ata_serverworks_tf_read(struct ata_request *request)
4466 {
4467 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4468 struct ata_device *atadev = device_get_softc(request->dev);
4469
4470 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
4471 u_int16_t temp;
4472
4473 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT);
4474 temp = ATA_IDX_INW(ch, ATA_SECTOR);
4475 request->u.ata.lba = (u_int64_t)(temp & 0x00ff) |
4476 ((u_int64_t)(temp & 0xff00) << 24);
4477 temp = ATA_IDX_INW(ch, ATA_CYL_LSB);
4478 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 8) |
4479 ((u_int64_t)(temp & 0xff00) << 32);
4480 temp = ATA_IDX_INW(ch, ATA_CYL_MSB);
4481 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 16) |
4482 ((u_int64_t)(temp & 0xff00) << 40);
4483 }
4484 else {
4485 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT) & 0x00ff;
4486 request->u.ata.lba = (ATA_IDX_INW(ch, ATA_SECTOR) & 0x00ff) |
4487 ((ATA_IDX_INW(ch, ATA_CYL_LSB) & 0x00ff) << 8) |
4488 ((ATA_IDX_INW(ch, ATA_CYL_MSB) & 0x00ff) << 16) |
4489 ((ATA_IDX_INW(ch, ATA_DRIVE) & 0xf) << 24);
4490 }
4491 }
4492
4493 static void
4494 ata_serverworks_tf_write(struct ata_request *request)
4495 {
4496 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4497 struct ata_device *atadev = device_get_softc(request->dev);
4498
4499 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
4500 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
4501 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
4502 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) |
4503 (request->u.ata.lba & 0x00ff));
4504 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) |
4505 ((request->u.ata.lba >> 8) & 0x00ff));
4506 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) |
4507 ((request->u.ata.lba >> 16) & 0x00ff));
4508 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | atadev->unit);
4509 }
4510 else {
4511 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
4512 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
4513 if (atadev->flags & ATA_D_USE_CHS) {
4514 int heads, sectors;
4515
4516 if (atadev->param.atavalid & ATA_FLAG_54_58) {
4517 heads = atadev->param.current_heads;
4518 sectors = atadev->param.current_sectors;
4519 }
4520 else {
4521 heads = atadev->param.heads;
4522 sectors = atadev->param.sectors;
4523 }
4524 ATA_IDX_OUTW(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
4525 ATA_IDX_OUTW(ch, ATA_CYL_LSB,
4526 (request->u.ata.lba / (sectors * heads)));
4527 ATA_IDX_OUTW(ch, ATA_CYL_MSB,
4528 (request->u.ata.lba / (sectors * heads)) >> 8);
4529 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit |
4530 (((request->u.ata.lba% (sectors * heads)) /
4531 sectors) & 0xf));
4532 }
4533 else {
4534 ATA_IDX_OUTW(ch, ATA_SECTOR, request->u.ata.lba);
4535 ATA_IDX_OUTW(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
4536 ATA_IDX_OUTW(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
4537 ATA_IDX_OUTW(ch, ATA_DRIVE,
4538 ATA_D_IBM | ATA_D_LBA | atadev->unit |
4539 ((request->u.ata.lba >> 24) & 0x0f));
4540 }
4541 }
4542 }
4543
4544 static void
4545 ata_serverworks_setmode(device_t dev, int mode)
4546 {
4547 device_t gparent = GRANDPARENT(dev);
4548 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4549 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4550 struct ata_device *atadev = device_get_softc(dev);
4551 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4552 int offset = (devno ^ 0x01) << 3;
4553 int error;
4554 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
4555 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
4556 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
4557
4558 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4559
4560 mode = ata_check_80pin(dev, mode);
4561
4562 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4563
4564 if (bootverbose)
4565 device_printf(dev, "%ssetting %s on %s chip\n",
4566 (error) ? "FAILURE " : "",
4567 ata_mode2str(mode), ctlr->chip->text);
4568 if (!error) {
4569 if (mode >= ATA_UDMA0) {
4570 pci_write_config(gparent, 0x56,
4571 (pci_read_config(gparent, 0x56, 2) &
4572 ~(0xf << (devno << 2))) |
4573 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
4574 pci_write_config(gparent, 0x54,
4575 pci_read_config(gparent, 0x54, 1) |
4576 (0x01 << devno), 1);
4577 pci_write_config(gparent, 0x44,
4578 (pci_read_config(gparent, 0x44, 4) &
4579 ~(0xff << offset)) |
4580 (dmatimings[2] << offset), 4);
4581 }
4582 else if (mode >= ATA_WDMA0) {
4583 pci_write_config(gparent, 0x54,
4584 pci_read_config(gparent, 0x54, 1) &
4585 ~(0x01 << devno), 1);
4586 pci_write_config(gparent, 0x44,
4587 (pci_read_config(gparent, 0x44, 4) &
4588 ~(0xff << offset)) |
4589 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
4590 }
4591 else
4592 pci_write_config(gparent, 0x54,
4593 pci_read_config(gparent, 0x54, 1) &
4594 ~(0x01 << devno), 1);
4595
4596 pci_write_config(gparent, 0x40,
4597 (pci_read_config(gparent, 0x40, 4) &
4598 ~(0xff << offset)) |
4599 (piotimings[ata_mode2idx(mode)] << offset), 4);
4600 atadev->mode = mode;
4601 }
4602 }
4603
4604
4605 /*
4606 * Silicon Image Inc. (SiI) (former CMD) chipset support functions
4607 */
4608 int
4609 ata_sii_ident(device_t dev)
4610 {
4611 struct ata_pci_controller *ctlr = device_get_softc(dev);
4612 static struct ata_chip_id ids[] =
4613 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" },
4614 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" },
4615 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
4616 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
4617 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" },
4618 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
4619 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
4620 { ATA_SII3124, 0x00, SIIPRBIO, SII4CH, ATA_SA300, "SiI 3124" },
4621 { ATA_SII3132, 0x00, SIIPRBIO, 0, ATA_SA300, "SiI 3132" },
4622 { ATA_SII3132_1, 0x00, SIIPRBIO, 0, ATA_SA300, "SiI 3132" },
4623 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" },
4624 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" },
4625 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" },
4626 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" },
4627 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" },
4628 { 0, 0, 0, 0, 0, 0}};
4629
4630 if (!(ctlr->chip = ata_match_chip(dev, ids)))
4631 return ENXIO;
4632
4633 ata_set_desc(dev);
4634 ctlr->chipinit = ata_sii_chipinit;
4635 return 0;
4636 }
4637
4638 static int
4639 ata_sii_chipinit(device_t dev)
4640 {
4641 struct ata_pci_controller *ctlr = device_get_softc(dev);
4642
4643 if (ata_setup_interrupt(dev))
4644 return ENXIO;
4645
4646 switch (ctlr->chip->cfg1) {
4647 case SIIPRBIO:
4648 ctlr->r_type1 = SYS_RES_MEMORY;
4649 ctlr->r_rid1 = PCIR_BAR(0);
4650 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
4651 &ctlr->r_rid1, RF_ACTIVE)))
4652 return ENXIO;
4653
4654 ctlr->r_rid2 = PCIR_BAR(2);
4655 ctlr->r_type2 = SYS_RES_MEMORY;
4656 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4657 &ctlr->r_rid2, RF_ACTIVE))){
4658 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
4659 return ENXIO;
4660 }
4661 ctlr->allocate = ata_siiprb_allocate;
4662 ctlr->reset = ata_siiprb_reset;
4663 ctlr->dmainit = ata_siiprb_dmainit;
4664 ctlr->setmode = ata_sata_setmode;
4665 ctlr->channels = (ctlr->chip->cfg2 == SII4CH) ? 4 : 2;
4666
4667 /* reset controller */
4668 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
4669 DELAY(10000);
4670 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
4671 break;
4672
4673 case SIIMEMIO:
4674 ctlr->r_type2 = SYS_RES_MEMORY;
4675 ctlr->r_rid2 = PCIR_BAR(5);
4676 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4677 &ctlr->r_rid2, RF_ACTIVE))){
4678 if (ctlr->chip->chipid != ATA_SII0680 ||
4679 (pci_read_config(dev, 0x8a, 1) & 1))
4680 return ENXIO;
4681 }
4682
4683 if (ctlr->chip->cfg2 & SIISETCLK) {
4684 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4685 pci_write_config(dev, 0x8a,
4686 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
4687 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4688 device_printf(dev, "%s could not set ATA133 clock\n",
4689 ctlr->chip->text);
4690 }
4691
4692 /* if we have 4 channels enable the second set */
4693 if (ctlr->chip->cfg2 & SII4CH) {
4694 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
4695 ctlr->channels = 4;
4696 }
4697
4698 /* dont block interrupts from any channel */
4699 pci_write_config(dev, 0x48,
4700 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
4701
4702 /* enable PCI interrupt as BIOS might not */
4703 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
4704
4705 if (ctlr->r_res2)
4706 ctlr->allocate = ata_sii_allocate;
4707
4708 if (ctlr->chip->max_dma >= ATA_SA150) {
4709 ctlr->reset = ata_sii_reset;
4710 ctlr->setmode = ata_sata_setmode;
4711 }
4712 else
4713 ctlr->setmode = ata_sii_setmode;
4714 break;
4715
4716 default:
4717 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
4718 device_printf(dev, "HW has secondary channel disabled\n");
4719 ctlr->channels = 1;
4720 }
4721
4722 /* enable interrupt as BIOS might not */
4723 pci_write_config(dev, 0x71, 0x01, 1);
4724
4725 ctlr->allocate = ata_cmd_allocate;
4726 ctlr->setmode = ata_cmd_setmode;
4727 break;
4728 }
4729 return 0;
4730 }
4731
4732 static int
4733 ata_cmd_allocate(device_t dev)
4734 {
4735 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4736 struct ata_channel *ch = device_get_softc(dev);
4737
4738 /* setup the usual register normal pci style */
4739 if (ata_pci_allocate(dev))
4740 return ENXIO;
4741
4742 if (ctlr->chip->cfg2 & SIIINTR)
4743 ch->hw.status = ata_cmd_status;
4744
4745 return 0;
4746 }
4747
4748 static int
4749 ata_cmd_status(device_t dev)
4750 {
4751 struct ata_channel *ch = device_get_softc(dev);
4752 u_int8_t reg71;
4753
4754 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
4755 (ch->unit ? 0x08 : 0x04))) {
4756 pci_write_config(device_get_parent(ch->dev), 0x71,
4757 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
4758 return ata_pci_status(dev);
4759 }
4760 return 0;
4761 }
4762
4763 static void
4764 ata_cmd_setmode(device_t dev, int mode)
4765 {
4766 device_t gparent = GRANDPARENT(dev);
4767 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4768 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4769 struct ata_device *atadev = device_get_softc(dev);
4770 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4771 int error;
4772
4773 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4774
4775 mode = ata_check_80pin(dev, mode);
4776
4777 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4778
4779 if (bootverbose)
4780 device_printf(dev, "%ssetting %s on %s chip\n",
4781 (error) ? "FAILURE " : "",
4782 ata_mode2str(mode), ctlr->chip->text);
4783 if (!error) {
4784 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
4785 int ureg = ch->unit ? 0x7b : 0x73;
4786
4787 if (mode >= ATA_UDMA0) {
4788 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
4789 { 0x11, 0x42 }, { 0x25, 0x8a },
4790 { 0x15, 0x4a }, { 0x05, 0x0a } };
4791
4792 u_int8_t umode = pci_read_config(gparent, ureg, 1);
4793
4794 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
4795 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)];
4796 pci_write_config(gparent, ureg, umode, 1);
4797 }
4798 else if (mode >= ATA_WDMA0) {
4799 int dmatimings[] = { 0x87, 0x32, 0x3f };
4800
4801 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1);
4802 pci_write_config(gparent, ureg,
4803 pci_read_config(gparent, ureg, 1) &
4804 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4805 }
4806 else {
4807 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
4808 pci_write_config(gparent, treg,
4809 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
4810 pci_write_config(gparent, ureg,
4811 pci_read_config(gparent, ureg, 1) &
4812 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4813 }
4814 atadev->mode = mode;
4815 }
4816 }
4817
4818 static int
4819 ata_sii_allocate(device_t dev)
4820 {
4821 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4822 struct ata_channel *ch = device_get_softc(dev);
4823 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
4824 int i;
4825
4826 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
4827 ch->r_io[i].res = ctlr->r_res2;
4828 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
4829 }
4830 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
4831 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
4832 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
4833 ata_default_registers(dev);
4834
4835 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
4836 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
4837 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
4838 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
4839 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
4840 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
4841
4842 if (ctlr->chip->max_dma >= ATA_SA150) {
4843 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4844 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
4845 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4846 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
4847 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4848 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
4849 ch->flags |= ATA_NO_SLAVE;
4850
4851 /* enable PHY state change interrupt */
4852 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
4853 }
4854
4855 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) {
4856 /* work around errata in early chips */
4857 ch->dma->boundary = 8192;
4858 ch->dma->segsize = 15 * DEV_BSIZE;
4859 }
4860
4861 ata_pci_hw(dev);
4862 ch->hw.status = ata_sii_status;
4863 return 0;
4864 }
4865
4866 static int
4867 ata_sii_status(device_t dev)
4868 {
4869 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4870 struct ata_channel *ch = device_get_softc(dev);
4871 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8);
4872 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8);
4873
4874 /* do we have any PHY events ? */
4875 if (ctlr->chip->max_dma >= ATA_SA150 &&
4876 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
4877 ata_sata_phy_check_events(dev);
4878
4879 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
4880 return ata_pci_status(dev);
4881 else
4882 return 0;
4883 }
4884
4885 static void
4886 ata_sii_reset(device_t dev)
4887 {
4888 if (ata_sata_phy_reset(dev))
4889 ata_generic_reset(dev);
4890 }
4891
4892 static void
4893 ata_sii_setmode(device_t dev, int mode)
4894 {
4895 device_t gparent = GRANDPARENT(dev);
4896 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4897 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4898 struct ata_device *atadev = device_get_softc(dev);
4899 int rego = (ch->unit << 4) + (ATA_DEV(atadev->unit) << 1);
4900 int mreg = ch->unit ? 0x84 : 0x80;
4901 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2);
4902 int mval = pci_read_config(gparent, mreg, 1) & ~mask;
4903 int error;
4904
4905 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4906
4907 if (ctlr->chip->cfg2 & SIISETCLK) {
4908 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) &
4909 (ch->unit ? 0x02 : 0x01))) {
4910 ata_print_cable(dev, "controller");
4911 mode = ATA_UDMA2;
4912 }
4913 }
4914 else
4915 mode = ata_check_80pin(dev, mode);
4916
4917 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4918
4919 if (bootverbose)
4920 device_printf(dev, "%ssetting %s on %s chip\n",
4921 (error) ? "FAILURE " : "",
4922 ata_mode2str(mode), ctlr->chip->text);
4923 if (error)
4924 return;
4925
4926 if (mode >= ATA_UDMA0) {
4927 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
4928 u_int8_t ureg = 0xac + rego;
4929
4930 pci_write_config(gparent, mreg,
4931 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1);
4932 pci_write_config(gparent, ureg,
4933 (pci_read_config(gparent, ureg, 1) & ~0x3f) |
4934 udmatimings[mode & ATA_MODE_MASK], 1);
4935
4936 }
4937 else if (mode >= ATA_WDMA0) {
4938 u_int8_t dreg = 0xa8 + rego;
4939 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
4940
4941 pci_write_config(gparent, mreg,
4942 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1);
4943 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
4944
4945 }
4946 else {
4947 u_int8_t preg = 0xa4 + rego;
4948 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
4949
4950 pci_write_config(gparent, mreg,
4951 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1);
4952 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2);
4953 }
4954 atadev->mode = mode;
4955 }
4956
4957
4958 struct ata_siiprb_dma_prdentry {
4959 u_int64_t addr;
4960 u_int32_t count;
4961 u_int32_t control;
4962 } __packed;
4963
4964 struct ata_siiprb_ata_command {
4965 struct ata_siiprb_dma_prdentry prd[126];
4966 } __packed;
4967
4968 struct ata_siiprb_atapi_command {
4969 u_int8_t ccb[16];
4970 struct ata_siiprb_dma_prdentry prd[125];
4971 } __packed;
4972
4973 struct ata_siiprb_command {
4974 u_int16_t control;
4975 u_int16_t protocol_override;
4976 u_int32_t transfer_count;
4977 u_int8_t fis[24];
4978 union {
4979 struct ata_siiprb_ata_command ata;
4980 struct ata_siiprb_atapi_command atapi;
4981 } u;
4982 } __packed;
4983
4984 static int
4985 ata_siiprb_allocate(device_t dev)
4986 {
4987 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4988 struct ata_channel *ch = device_get_softc(dev);
4989 int offset = ch->unit * 0x2000;
4990
4991 /* set the SATA resources */
4992 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4993 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
4994 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4995 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
4996 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4997 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
4998 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
4999 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
5000
5001 ch->hw.begin_transaction = ata_siiprb_begin_transaction;
5002 ch->hw.end_transaction = ata_siiprb_end_transaction;
5003 ch->hw.status = ata_siiprb_status;
5004 ch->hw.command = NULL; /* not used here */
5005 return 0;
5006 }
5007
5008 static int
5009 ata_siiprb_status(device_t dev)
5010 {
5011 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5012 struct ata_channel *ch = device_get_softc(dev);
5013 u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044);
5014 int offset = ch->unit * 0x2000;
5015
5016 if (action & (1 << ch->unit)) {
5017 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
5018
5019 /* do we have any PHY events ? */
5020 ata_sata_phy_check_events(dev);
5021
5022 /* clear interrupt(s) */
5023 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
5024
5025 /* do we have any device action ? */
5026 return (istatus & 0x00000003);
5027 }
5028 return 0;
5029 }
5030
5031 static int
5032 ata_siiprb_begin_transaction(struct ata_request *request)
5033 {
5034 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
5035 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
5036 struct ata_siiprb_command *prb;
5037 struct ata_siiprb_dma_prdentry *prd;
5038 int offset = ch->unit * 0x2000;
5039 u_int64_t prb_bus;
5040 int tag = 0, dummy;
5041
5042 /* SOS XXX */
5043 if (request->u.ata.command == ATA_DEVICE_RESET) {
5044 request->result = 0;
5045 return ATA_OP_FINISHED;
5046 }
5047
5048 /* check for 48 bit access and convert if needed */
5049 ata_modify_if_48bit(request);
5050
5051 /* get a piece of the workspace for this request */
5052 prb = (struct ata_siiprb_command *)
5053 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
5054
5055 /* set basic prd options ata/atapi etc etc */
5056 bzero(prb, sizeof(struct ata_siiprb_command));
5057
5058 /* setup the FIS for this request */
5059 if (!ata_request2fis_h2d(request, &prb->fis[0])) {
5060 device_printf(request->dev, "setting up SATA FIS failed\n");
5061 request->result = EIO;
5062 return ATA_OP_FINISHED;
5063 }
5064
5065 /* setup transfer type */
5066 if (request->flags & ATA_R_ATAPI) {
5067 struct ata_device *atadev = device_get_softc(request->dev);
5068
5069 bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16);
5070 if ((atadev->param.config & ATA_PROTO_MASK) == ATA_PROTO_ATAPI_12)
5071 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020);
5072 else
5073 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020);
5074 if (request->flags & ATA_R_READ)
5075 prb->control = htole16(0x0010);
5076 if (request->flags & ATA_R_WRITE)
5077 prb->control = htole16(0x0020);
5078 prd = &prb->u.atapi.prd[0];
5079 }
5080 else
5081 prd = &prb->u.ata.prd[0];
5082
5083 /* if request moves data setup and load SG list */
5084 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
5085 if (ch->dma->load(ch->dev, request->data, request->bytecount,
5086 request->flags & ATA_R_READ, prd, &dummy)) {
5087 device_printf(request->dev, "setting up DMA failed\n");
5088 request->result = EIO;
5089 return ATA_OP_FINISHED;
5090 }
5091 }
5092
5093 /* activate the prb */
5094 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
5095 ATA_OUTL(ctlr->r_res2,
5096 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
5097 ATA_OUTL(ctlr->r_res2,
5098 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
5099
5100 /* start the timeout */
5101 callout_reset(&request->callout, request->timeout * hz,
5102 (timeout_t*)ata_timeout, request);
5103 return ATA_OP_CONTINUES;
5104 }
5105
5106 static int
5107 ata_siiprb_end_transaction(struct ata_request *request)
5108 {
5109 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
5110 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
5111 struct ata_siiprb_command *prb;
5112 int offset = ch->unit * 0x2000;
5113 int error, timeout, tag = 0;
5114
5115 /* kill the timeout */
5116 callout_stop(&request->callout);
5117
5118 prb = (struct ata_siiprb_command *)
5119 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
5120
5121 /* any controller errors flagged ? */
5122 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
5123 if (bootverbose)
5124 printf("ata_siiprb_end_transaction %s error=%08x\n",
5125 ata_cmd2str(request), error);
5126
5127 /* if device error status get details */
5128 if (error == 1 || error == 2) {
5129 request->status = prb->fis[2];
5130 if (request->status & ATA_S_ERROR)
5131 request->error = prb->fis[3];
5132 }
5133
5134 /* SOS XXX handle other controller errors here */
5135
5136 /* initialize port */
5137 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004);
5138
5139 /* poll for port ready */
5140 for (timeout = 0; timeout < 1000; timeout++) {
5141 DELAY(1000);
5142 if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000)
5143 break;
5144 }
5145 if (bootverbose) {
5146 if (timeout >= 1000)
5147 device_printf(ch->dev, "port initialize timeout\n");
5148 else
5149 device_printf(ch->dev, "port initialize time=%dms\n", timeout);
5150 }
5151 }
5152
5153 /* update progress */
5154 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
5155 if (request->flags & ATA_R_READ)
5156 request->donecount = prb->transfer_count;
5157 else
5158 request->donecount = request->bytecount;
5159 }
5160
5161 /* release SG list etc */
5162 ch->dma->unload(ch->dev);
5163
5164 return ATA_OP_FINISHED;
5165 }
5166
5167 static void
5168 ata_siiprb_reset(device_t dev)
5169 {
5170 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5171 struct ata_channel *ch = device_get_softc(dev);
5172 int offset = ch->unit * 0x2000;
5173 struct ata_siiprb_command *prb;
5174 u_int64_t prb_bus;
5175 u_int32_t status, signature;
5176 int timeout, tag = 0;
5177
5178 /* reset channel HW */
5179 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
5180 DELAY(1000);
5181 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
5182 DELAY(10000);
5183
5184 /* poll for channel ready */
5185 for (timeout = 0; timeout < 1000; timeout++) {
5186 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000)
5187 break;
5188 DELAY(1000);
5189 }
5190
5191 if (bootverbose) {
5192 if (timeout >= 1000)
5193 device_printf(ch->dev, "channel HW reset timeout\n");
5194 else
5195 device_printf(ch->dev, "channel HW reset time=%dms\n", timeout);
5196 }
5197
5198 /* reset phy */
5199 if (!ata_sata_phy_reset(dev)) {
5200 if (bootverbose)
5201 device_printf(ch->dev, "phy reset found no device\n");
5202 ch->devices = 0;
5203 goto finish;
5204 }
5205
5206 /* get a piece of the workspace for a soft reset request */
5207 prb = (struct ata_siiprb_command *)
5208 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
5209 bzero(prb, sizeof(struct ata_siiprb_command));
5210 prb->control = htole16(0x0080);
5211
5212 /* activate the soft reset prb */
5213 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
5214 ATA_OUTL(ctlr->r_res2,
5215 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
5216 ATA_OUTL(ctlr->r_res2,
5217 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
5218
5219 /* poll for command finished */
5220 for (timeout = 0; timeout < 10000; timeout++) {
5221 DELAY(1000);
5222 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
5223 break;
5224 }
5225 if (timeout >= 1000) {
5226 device_printf(ch->dev, "reset timeout - no device found\n");
5227 ch->devices = 0;
5228 goto finish;
5229 }
5230 if (bootverbose)
5231 device_printf(ch->dev, "soft reset exec time=%dms status=%08x\n",
5232 timeout, status);
5233
5234 /* find out whats there */
5235 prb = (struct ata_siiprb_command *)
5236 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
5237 signature =
5238 prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
5239 if (bootverbose)
5240 device_printf(ch->dev, "SIGNATURE=%08x\n", signature);
5241 switch (signature) {
5242 case 0x00000101:
5243 ch->devices = ATA_ATA_MASTER;
5244 break;
5245 case 0x96690101:
5246 ch->devices = ATA_PORTMULTIPLIER;
5247 device_printf(ch->dev, "Portmultipliers not supported yet\n");
5248 ch->devices = 0;
5249 break;
5250 case 0xeb140101:
5251 ch->devices = ATA_ATAPI_MASTER;
5252 break;
5253 default:
5254 ch->devices = 0;
5255 }
5256 if (bootverbose)
5257 device_printf(dev, "siiprb_reset devices=0x%b\n", ch->devices,
5258 "\2\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
5259
5260 finish:
5261 /* clear interrupt(s) */
5262 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
5263
5264 /* require explicit interrupt ack */
5265 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
5266
5267 /* 64bit mode */
5268 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
5269
5270 /* enable interrupts wanted */
5271 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
5272 }
5273
5274 static void
5275 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
5276 {
5277 struct ata_dmasetprd_args *args = xsc;
5278 struct ata_siiprb_dma_prdentry *prd = args->dmatab;
5279 int i;
5280
5281 if ((args->error = error))
5282 return;
5283
5284 for (i = 0; i < nsegs; i++) {
5285 prd[i].addr = htole64(segs[i].ds_addr);
5286 prd[i].count = htole32(segs[i].ds_len);
5287 }
5288 prd[i - 1].control = htole32(ATA_DMA_EOT);
5289 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
5290 args->nsegs = nsegs;
5291 }
5292
5293 static void
5294 ata_siiprb_dmainit(device_t dev)
5295 {
5296 struct ata_channel *ch = device_get_softc(dev);
5297
5298 ata_dmainit(dev);
5299 if (ch->dma) {
5300 /* note start and stop are not used here */
5301 ch->dma->setprd = ata_siiprb_dmasetprd;
5302 ch->dma->max_address = BUS_SPACE_MAXADDR;
5303 }
5304 }
5305
5306
5307 /*
5308 * Silicon Integrated Systems Corp. (SiS) chipset support functions
5309 */
5310 int
5311 ata_sis_ident(device_t |