1 /*-
2 * Copyright (c) 1998 - 2007 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include "opt_ata.h"
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/ata.h>
35 #include <sys/bus.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <sys/sema.h>
41 #include <sys/taskqueue.h>
42 #include <vm/uma.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
46 #include <sys/rman.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49 #include <dev/ata/ata-all.h>
50 #include <dev/ata/ata-pci.h>
51 #include <ata_if.h>
52
53 /* local prototypes */
54 /* ata-chipset.c */
55 static int ata_generic_chipinit(device_t dev);
56 static void ata_generic_intr(void *data);
57 static void ata_generic_setmode(device_t dev, int mode);
58 static void ata_sata_phy_check_events(device_t dev);
59 static void ata_sata_phy_event(void *context, int dummy);
60 static int ata_sata_phy_reset(device_t dev);
61 static int ata_sata_connect(struct ata_channel *ch);
62 static void ata_sata_setmode(device_t dev, int mode);
63 static int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis);
64 static int ata_ahci_chipinit(device_t dev);
65 static int ata_ahci_allocate(device_t dev);
66 static int ata_ahci_status(device_t dev);
67 static int ata_ahci_begin_transaction(struct ata_request *request);
68 static int ata_ahci_end_transaction(struct ata_request *request);
69 static void ata_ahci_reset(device_t dev);
70 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
71 static void ata_ahci_dmainit(device_t dev);
72 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request);
73 static int ata_acard_chipinit(device_t dev);
74 static int ata_acard_allocate(device_t dev);
75 static int ata_acard_status(device_t dev);
76 static void ata_acard_850_setmode(device_t dev, int mode);
77 static void ata_acard_86X_setmode(device_t dev, int mode);
78 static int ata_ali_chipinit(device_t dev);
79 static int ata_ali_allocate(device_t dev);
80 static int ata_ali_sata_allocate(device_t dev);
81 static void ata_ali_reset(device_t dev);
82 static void ata_ali_setmode(device_t dev, int mode);
83 static int ata_amd_chipinit(device_t dev);
84 static int ata_ati_chipinit(device_t dev);
85 static void ata_ati_setmode(device_t dev, int mode);
86 static int ata_cyrix_chipinit(device_t dev);
87 static void ata_cyrix_setmode(device_t dev, int mode);
88 static int ata_cypress_chipinit(device_t dev);
89 static void ata_cypress_setmode(device_t dev, int mode);
90 static int ata_highpoint_chipinit(device_t dev);
91 static int ata_highpoint_allocate(device_t dev);
92 static void ata_highpoint_setmode(device_t dev, int mode);
93 static int ata_highpoint_check_80pin(device_t dev, int mode);
94 static int ata_intel_chipinit(device_t dev);
95 static int ata_intel_allocate(device_t dev);
96 static void ata_intel_reset(device_t dev);
97 static void ata_intel_old_setmode(device_t dev, int mode);
98 static void ata_intel_new_setmode(device_t dev, int mode);
99 static void ata_intel_sata_setmode(device_t dev, int mode);
100 static int ata_intel_31244_allocate(device_t dev);
101 static int ata_intel_31244_status(device_t dev);
102 static void ata_intel_31244_tf_write(struct ata_request *request);
103 static void ata_intel_31244_reset(device_t dev);
104 static int ata_ite_chipinit(device_t dev);
105 static void ata_ite_setmode(device_t dev, int mode);
106 static int ata_jmicron_chipinit(device_t dev);
107 static int ata_jmicron_allocate(device_t dev);
108 static void ata_jmicron_reset(device_t dev);
109 static void ata_jmicron_dmainit(device_t dev);
110 static void ata_jmicron_setmode(device_t dev, int mode);
111 static int ata_marvell_pata_chipinit(device_t dev);
112 static int ata_marvell_pata_allocate(device_t dev);
113 static void ata_marvell_pata_setmode(device_t dev, int mode);
114 static int ata_marvell_edma_chipinit(device_t dev);
115 static int ata_marvell_edma_allocate(device_t dev);
116 static int ata_marvell_edma_status(device_t dev);
117 static int ata_marvell_edma_begin_transaction(struct ata_request *request);
118 static int ata_marvell_edma_end_transaction(struct ata_request *request);
119 static void ata_marvell_edma_reset(device_t dev);
120 static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
121 static void ata_marvell_edma_dmainit(device_t dev);
122 static int ata_national_chipinit(device_t dev);
123 static void ata_national_setmode(device_t dev, int mode);
124 static int ata_netcell_chipinit(device_t dev);
125 static int ata_netcell_allocate(device_t dev);
126 static int ata_nvidia_chipinit(device_t dev);
127 static int ata_nvidia_allocate(device_t dev);
128 static int ata_nvidia_status(device_t dev);
129 static void ata_nvidia_reset(device_t dev);
130 static int ata_promise_chipinit(device_t dev);
131 static int ata_promise_allocate(device_t dev);
132 static int ata_promise_status(device_t dev);
133 static int ata_promise_dmastart(device_t dev);
134 static int ata_promise_dmastop(device_t dev);
135 static void ata_promise_dmareset(device_t dev);
136 static void ata_promise_dmainit(device_t dev);
137 static void ata_promise_setmode(device_t dev, int mode);
138 static int ata_promise_tx2_allocate(device_t dev);
139 static int ata_promise_tx2_status(device_t dev);
140 static int ata_promise_mio_allocate(device_t dev);
141 static void ata_promise_mio_intr(void *data);
142 static int ata_promise_mio_status(device_t dev);
143 static int ata_promise_mio_command(struct ata_request *request);
144 static void ata_promise_mio_reset(device_t dev);
145 static void ata_promise_mio_dmainit(device_t dev);
146 static void ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
147 static void ata_promise_mio_setmode(device_t dev, int mode);
148 static void ata_promise_sx4_intr(void *data);
149 static int ata_promise_sx4_command(struct ata_request *request);
150 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request);
151 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt);
152 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr);
153 static int ata_serverworks_chipinit(device_t dev);
154 static int ata_serverworks_allocate(device_t dev);
155 static void ata_serverworks_tf_read(struct ata_request *request);
156 static void ata_serverworks_tf_write(struct ata_request *request);
157 static void ata_serverworks_setmode(device_t dev, int mode);
158 static int ata_sii_chipinit(device_t dev);
159 static int ata_cmd_allocate(device_t dev);
160 static int ata_cmd_status(device_t dev);
161 static void ata_cmd_setmode(device_t dev, int mode);
162 static int ata_sii_allocate(device_t dev);
163 static int ata_sii_status(device_t dev);
164 static void ata_sii_reset(device_t dev);
165 static void ata_sii_setmode(device_t dev, int mode);
166 static int ata_siiprb_allocate(device_t dev);
167 static int ata_siiprb_status(device_t dev);
168 static int ata_siiprb_begin_transaction(struct ata_request *request);
169 static int ata_siiprb_end_transaction(struct ata_request *request);
170 static void ata_siiprb_reset(device_t dev);
171 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
172 static void ata_siiprb_dmainit(device_t dev);
173 static int ata_sis_chipinit(device_t dev);
174 static int ata_sis_allocate(device_t dev);
175 static void ata_sis_reset(device_t dev);
176 static void ata_sis_setmode(device_t dev, int mode);
177 static int ata_via_chipinit(device_t dev);
178 static int ata_via_allocate(device_t dev);
179 static void ata_via_reset(device_t dev);
180 static void ata_via_setmode(device_t dev, int mode);
181 static void ata_via_southbridge_fixup(device_t dev);
182 static void ata_via_family_setmode(device_t dev, int mode);
183 static void ata_set_desc(device_t dev);
184 static struct ata_chip_id *ata_match_chip(device_t dev, struct ata_chip_id *index);
185 static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot);
186 static int ata_setup_interrupt(device_t dev);
187 static int ata_serialize(device_t dev, int flags);
188 static void ata_print_cable(device_t dev, u_int8_t *who);
189 static int ata_atapi(device_t dev);
190 static int ata_check_80pin(device_t dev, int mode);
191 static int ata_mode2idx(int mode);
192
193
194 /*
195 * generic ATA support functions
196 */
197 int
198 ata_generic_ident(device_t dev)
199 {
200 struct ata_pci_controller *ctlr = device_get_softc(dev);
201 char buffer[64];
202
203 sprintf(buffer, "%s ATA controller", ata_pcivendor2str(dev));
204 device_set_desc_copy(dev, buffer);
205 ctlr->chipinit = ata_generic_chipinit;
206 return 0;
207 }
208
209 static int
210 ata_generic_chipinit(device_t dev)
211 {
212 struct ata_pci_controller *ctlr = device_get_softc(dev);
213
214 if (ata_setup_interrupt(dev))
215 return ENXIO;
216 ctlr->setmode = ata_generic_setmode;
217 return 0;
218 }
219
220 static void
221 ata_generic_intr(void *data)
222 {
223 struct ata_pci_controller *ctlr = data;
224 struct ata_channel *ch;
225 int unit;
226
227 for (unit = 0; unit < ctlr->channels; unit++) {
228 if ((ch = ctlr->interrupt[unit].argument))
229 ctlr->interrupt[unit].function(ch);
230 }
231 }
232
233 static void
234 ata_generic_setmode(device_t dev, int mode)
235 {
236 struct ata_device *atadev = device_get_softc(dev);
237
238 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
239 mode = ata_check_80pin(dev, mode);
240 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
241 atadev->mode = mode;
242 }
243
244
245 /*
246 * SATA support functions
247 */
248 static void
249 ata_sata_phy_check_events(device_t dev)
250 {
251 struct ata_channel *ch = device_get_softc(dev);
252 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR);
253
254 /* clear error bits/interrupt */
255 ATA_IDX_OUTL(ch, ATA_SERROR, error);
256
257 /* do we have any events flagged ? */
258 if (error) {
259 struct ata_connect_task *tp;
260 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS);
261
262 /* if we have a connection event deal with it */
263 if ((error & ATA_SE_PHY_CHANGED) &&
264 (tp = (struct ata_connect_task *)
265 malloc(sizeof(struct ata_connect_task),
266 M_ATA, M_NOWAIT | M_ZERO))) {
267
268 if (((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) ||
269 ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)) {
270 if (bootverbose)
271 device_printf(ch->dev, "CONNECT requested\n");
272 tp->action = ATA_C_ATTACH;
273 }
274 else {
275 if (bootverbose)
276 device_printf(ch->dev, "DISCONNECT requested\n");
277 tp->action = ATA_C_DETACH;
278 }
279 tp->dev = ch->dev;
280 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
281 taskqueue_enqueue(taskqueue_thread, &tp->task);
282 }
283 }
284 }
285
286 static void
287 ata_sata_phy_event(void *context, int dummy)
288 {
289 struct ata_connect_task *tp = (struct ata_connect_task *)context;
290 struct ata_channel *ch = device_get_softc(tp->dev);
291 device_t *children;
292 int nchildren, i;
293
294 mtx_lock(&Giant); /* newbus suckage it needs Giant */
295 if (tp->action == ATA_C_ATTACH) {
296 if (bootverbose)
297 device_printf(tp->dev, "CONNECTED\n");
298 ATA_RESET(tp->dev);
299 ata_identify(tp->dev);
300 }
301 if (tp->action == ATA_C_DETACH) {
302 if (!device_get_children(tp->dev, &children, &nchildren)) {
303 for (i = 0; i < nchildren; i++)
304 if (children[i])
305 device_delete_child(tp->dev, children[i]);
306 free(children, M_TEMP);
307 }
308 mtx_lock(&ch->state_mtx);
309 ch->state = ATA_IDLE;
310 mtx_unlock(&ch->state_mtx);
311 if (bootverbose)
312 device_printf(tp->dev, "DISCONNECTED\n");
313 }
314 mtx_unlock(&Giant); /* suckage code dealt with, release Giant */
315 free(tp, M_ATA);
316 }
317
318 static int
319 ata_sata_phy_reset(device_t dev)
320 {
321 struct ata_channel *ch = device_get_softc(dev);
322 int loop, retry;
323
324 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE)
325 return ata_sata_connect(ch);
326
327 for (retry = 0; retry < 10; retry++) {
328 for (loop = 0; loop < 10; loop++) {
329 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET);
330 ata_udelay(100);
331 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) ==
332 ATA_SC_DET_RESET)
333 break;
334 }
335 ata_udelay(5000);
336 for (loop = 0; loop < 10; loop++) {
337 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_IDLE |
338 ATA_SC_IPM_DIS_PARTIAL |
339 ATA_SC_IPM_DIS_SLUMBER);
340 ata_udelay(100);
341 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 0)
342 return ata_sata_connect(ch);
343 }
344 }
345 return 0;
346 }
347
348 static int
349 ata_sata_connect(struct ata_channel *ch)
350 {
351 u_int32_t status;
352 int timeout;
353
354 /* wait up to 1 second for "connect well" */
355 for (timeout = 0; timeout < 100 ; timeout++) {
356 status = ATA_IDX_INL(ch, ATA_SSTATUS);
357 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 ||
358 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)
359 break;
360 ata_udelay(10000);
361 }
362 if (timeout >= 100) {
363 if (bootverbose)
364 device_printf(ch->dev, "SATA connect status=%08x\n", status);
365 return 0;
366 }
367 if (bootverbose)
368 device_printf(ch->dev, "SATA connect time=%dms\n", timeout * 10);
369
370 /* clear SATA error register */
371 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
372
373 return 1;
374 }
375
376 static void
377 ata_sata_setmode(device_t dev, int mode)
378 {
379 struct ata_device *atadev = device_get_softc(dev);
380
381 /*
382 * if we detect that the device isn't a real SATA device we limit
383 * the transfer mode to UDMA5/ATA100.
384 * this works around the problems some devices has with the
385 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133.
386 */
387 if (atadev->param.satacapabilities != 0x0000 &&
388 atadev->param.satacapabilities != 0xffff) {
389 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
390
391 /* on some drives we need to set the transfer mode */
392 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
393 ata_limit_mode(dev, mode, ATA_UDMA6));
394
395 /* query SATA STATUS for the speed */
396 if (ch->r_io[ATA_SSTATUS].res &&
397 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) ==
398 ATA_SS_CONWELL_GEN2))
399 atadev->mode = ATA_SA300;
400 else
401 atadev->mode = ATA_SA150;
402 }
403 else {
404 mode = ata_limit_mode(dev, mode, ATA_UDMA5);
405 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
406 atadev->mode = mode;
407 }
408 }
409
410 static int
411 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis)
412 {
413 struct ata_device *atadev = device_get_softc(request->dev);
414
415 if (request->flags & ATA_R_ATAPI) {
416 fis[0] = 0x27; /* host to device */
417 fis[1] = 0x80; /* command FIS (note PM goes here) */
418 fis[2] = ATA_PACKET_CMD;
419 if (request->flags & (ATA_R_READ | ATA_R_WRITE))
420 fis[3] = ATA_F_DMA;
421 else {
422 fis[5] = request->transfersize;
423 fis[6] = request->transfersize >> 8;
424 }
425 fis[7] = ATA_D_LBA | atadev->unit;
426 fis[15] = ATA_A_4BIT;
427 return 20;
428 }
429 else {
430 ata_modify_if_48bit(request);
431 fis[0] = 0x27; /* host to device */
432 fis[1] = 0x80; /* command FIS (note PM goes here) */
433 fis[2] = request->u.ata.command;
434 fis[3] = request->u.ata.feature;
435 fis[4] = request->u.ata.lba;
436 fis[5] = request->u.ata.lba >> 8;
437 fis[6] = request->u.ata.lba >> 16;
438 fis[7] = ATA_D_LBA | atadev->unit;
439 if (!(atadev->flags & ATA_D_48BIT_ACTIVE))
440 fis[7] |= (request->u.ata.lba >> 24 & 0x0f);
441 fis[8] = request->u.ata.lba >> 24;
442 fis[9] = request->u.ata.lba >> 32;
443 fis[10] = request->u.ata.lba >> 40;
444 fis[11] = request->u.ata.feature >> 8;
445 fis[12] = request->u.ata.count;
446 fis[13] = request->u.ata.count >> 8;
447 fis[15] = ATA_A_4BIT;
448 return 20;
449 }
450 return 0;
451 }
452
453
454 /*
455 * AHCI v1.x compliant SATA chipset support functions
456 */
457 int
458 ata_ahci_ident(device_t dev)
459 {
460 struct ata_pci_controller *ctlr = device_get_softc(dev);
461 char buffer[64];
462
463 /* is this PCI device flagged as an AHCI compliant chip ? */
464 if (pci_read_config(dev, PCIR_PROGIF, 1) != PCIP_STORAGE_SATA_AHCI_1_0)
465 return ENXIO;
466
467 if (bootverbose)
468 sprintf(buffer, "%s (ID=%08x) AHCI controller",
469 ata_pcivendor2str(dev), pci_get_devid(dev));
470 else
471 sprintf(buffer, "%s AHCI controller", ata_pcivendor2str(dev));
472 device_set_desc_copy(dev, buffer);
473 ctlr->chipinit = ata_ahci_chipinit;
474 return 0;
475 }
476
477 static int
478 ata_ahci_chipinit(device_t dev)
479 {
480 struct ata_pci_controller *ctlr = device_get_softc(dev);
481 u_int32_t version;
482
483 /* if we have a memory BAR(5) we are likely on an AHCI part */
484 ctlr->r_type2 = SYS_RES_MEMORY;
485 ctlr->r_rid2 = PCIR_BAR(5);
486 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
487 &ctlr->r_rid2, RF_ACTIVE)))
488 return ENXIO;
489
490 /* setup interrupt delivery if not done allready by a vendor driver */
491 if (!ctlr->r_irq) {
492 if (ata_setup_interrupt(dev))
493 return ENXIO;
494 }
495 else
496 device_printf(dev, "AHCI called from vendor specific driver\n");
497
498 /* enable AHCI mode */
499 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
500
501 /* reset AHCI controller */
502 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_HR);
503 DELAY(1000000);
504 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) {
505 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
506 device_printf(dev, "AHCI controller reset failure\n");
507 return ENXIO;
508 }
509
510 /* reenable AHCI mode */
511 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
512
513 /* get the number of HW channels */
514 ctlr->channels =
515 MAX(flsl(ATA_INL(ctlr->r_res2, ATA_AHCI_PI)),
516 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
517
518 /* clear interrupts */
519 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS));
520
521 /* enable AHCI interrupts */
522 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
523 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE);
524
525 ctlr->reset = ata_ahci_reset;
526 ctlr->dmainit = ata_ahci_dmainit;
527 ctlr->allocate = ata_ahci_allocate;
528 ctlr->setmode = ata_sata_setmode;
529
530 /* enable PCI interrupt */
531 pci_write_config(dev, PCIR_COMMAND,
532 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
533
534 /* announce we support the HW */
535 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS);
536 device_printf(dev,
537 "AHCI Version %x%x.%x%x controller with %d ports detected\n",
538 (version >> 24) & 0xff, (version >> 16) & 0xff,
539 (version >> 8) & 0xff, version & 0xff,
540 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
541 return 0;
542 }
543
544 static int
545 ata_ahci_allocate(device_t dev)
546 {
547 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
548 struct ata_channel *ch = device_get_softc(dev);
549 u_int64_t work;
550 int offset = ch->unit << 7;
551
552 /* set the SATA resources */
553 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
554 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset;
555 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
556 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset;
557 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
558 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset;
559 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
560 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset;
561
562 ch->hw.status = ata_ahci_status;
563 ch->hw.begin_transaction = ata_ahci_begin_transaction;
564 ch->hw.end_transaction = ata_ahci_end_transaction;
565 ch->hw.command = NULL; /* not used here */
566
567 /* setup work areas */
568 work = ch->dma->work_bus + ATA_AHCI_CL_OFFSET;
569 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff);
570 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32);
571
572 work = ch->dma->work_bus + ATA_AHCI_FB_OFFSET;
573 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff);
574 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32);
575
576 /* enable wanted port interrupts */
577 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
578 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
579 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
580 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP |
581 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS |
582 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR));
583
584 /* start operations on this channel */
585 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
586 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
587 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
588 return 0;
589 }
590
591 static int
592 ata_ahci_status(device_t dev)
593 {
594 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
595 struct ata_channel *ch = device_get_softc(dev);
596 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS);
597 int offset = ch->unit << 7;
598 int tag = 0;
599
600 if (action & (1 << ch->unit)) {
601 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset);
602 u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset);
603
604 /* clear interrupt(s) */
605 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action & (1 << ch->unit));
606 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus);
607
608 /* do we have any PHY events ? */
609 /* XXX SOS check istatus phy bits */
610 ata_sata_phy_check_events(dev);
611
612 /* do we have a potentially hanging engine to take care of? */
613 if ((istatus & 0x78400050) && (cstatus & (1 << tag))) {
614
615 u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
616 int timeout = 0;
617
618 /* kill off all activity on this channel */
619 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
620 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
621
622 /* XXX SOS this is not entirely wrong */
623 do {
624 DELAY(1000);
625 if (timeout++ > 500) {
626 device_printf(dev, "stopping AHCI engine failed\n");
627 break;
628 }
629 } while (ATA_INL(ctlr->r_res2,
630 ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
631
632 /* start operations on this channel */
633 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
634 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
635
636 return 1;
637 }
638 else
639 return (!(cstatus & (1 << tag)));
640 }
641 return 0;
642 }
643
644 /* must be called with ATA channel locked and state_mtx held */
645 static int
646 ata_ahci_begin_transaction(struct ata_request *request)
647 {
648 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
649 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
650 struct ata_ahci_cmd_tab *ctp;
651 struct ata_ahci_cmd_list *clp;
652 int offset = ch->unit << 7;
653 int tag = 0, entries = 0;
654 int fis_size;
655
656 /* get a piece of the workspace for this request */
657 ctp = (struct ata_ahci_cmd_tab *)
658 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag));
659
660 /* setup the FIS for this request */
661 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) {
662 device_printf(request->dev, "setting up SATA FIS failed\n");
663 request->result = EIO;
664 return ATA_OP_FINISHED;
665 }
666
667 /* if request moves data setup and load SG list */
668 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
669 if (ch->dma->load(ch->dev, request->data, request->bytecount,
670 request->flags & ATA_R_READ,
671 ctp->prd_tab, &entries)) {
672 device_printf(request->dev, "setting up DMA failed\n");
673 request->result = EIO;
674 return ATA_OP_FINISHED;
675 }
676 }
677
678 /* setup the command list entry */
679 clp = (struct ata_ahci_cmd_list *)
680 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
681
682 clp->prd_length = entries;
683 clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) |
684 (request->flags & ATA_R_ATAPI ? ((1<<5) | (1<<7)) : 0) |
685 (fis_size / sizeof(u_int32_t));
686 clp->bytecount = 0;
687 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET +
688 (ATA_AHCI_CT_SIZE * tag));
689
690 /* clear eventual ACTIVE bit */
691 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag));
692
693 /* set command type bit */
694 if (request->flags & ATA_R_ATAPI)
695 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
696 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) |
697 ATA_AHCI_P_CMD_ATAPI);
698 else
699 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
700 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) &
701 ~ATA_AHCI_P_CMD_ATAPI);
702
703 /* issue command to controller */
704 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << tag));
705
706 if (!(request->flags & ATA_R_ATAPI)) {
707 /* device reset doesn't interrupt */
708 if (request->u.ata.command == ATA_DEVICE_RESET) {
709 u_int32_t tf_data;
710 int timeout = 1000000;
711
712 do {
713 DELAY(10);
714 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7));
715 } while ((tf_data & ATA_S_BUSY) && timeout--);
716 if (bootverbose)
717 device_printf(ch->dev, "device_reset timeout=%dus\n",
718 (1000000-timeout)*10);
719 request->status = tf_data;
720 if (request->status & ATA_S_ERROR)
721 request->error = tf_data >> 8;
722 return ATA_OP_FINISHED;
723 }
724 }
725
726 /* start the timeout */
727 callout_reset(&request->callout, request->timeout * hz,
728 (timeout_t*)ata_timeout, request);
729 return ATA_OP_CONTINUES;
730 }
731
732 /* must be called with ATA channel locked and state_mtx held */
733 static int
734 ata_ahci_end_transaction(struct ata_request *request)
735 {
736 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
737 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
738 struct ata_ahci_cmd_list *clp;
739 u_int32_t tf_data;
740 int offset = ch->unit << 7;
741 int tag = 0;
742
743 /* kill the timeout */
744 callout_stop(&request->callout);
745
746 /* get status */
747 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset);
748 request->status = tf_data;
749
750 /* if error status get details */
751 if (request->status & ATA_S_ERROR)
752 request->error = tf_data >> 8;
753
754 /* record how much data we actually moved */
755 clp = (struct ata_ahci_cmd_list *)
756 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
757 request->donecount = clp->bytecount;
758
759 /* release SG list etc */
760 ch->dma->unload(ch->dev);
761
762 return ATA_OP_FINISHED;
763 }
764
765 static void
766 ata_ahci_reset(device_t dev)
767 {
768 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
769 struct ata_channel *ch = device_get_softc(dev);
770 u_int32_t cmd, signature;
771 int offset = ch->unit << 7;
772 int timeout;
773
774 if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) {
775 device_printf(dev, "port not implemented\n");
776 return;
777 }
778 ch->devices = 0;
779
780 /* kill off all activity on this channel */
781 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
782 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
783 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
784
785 /* XXX SOS this is not entirely wrong */
786 timeout = 0;
787 do {
788 DELAY(1000);
789 if (timeout++ > 500) {
790 device_printf(dev, "stopping AHCI engine failed\n");
791 break;
792 }
793 }
794 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
795
796 /* issue Command List Override if supported */
797 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) {
798 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
799 cmd |= ATA_AHCI_P_CMD_CLO;
800 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd);
801 timeout = 0;
802 do {
803 DELAY(1000);
804 if (timeout++ > 500) {
805 device_printf(dev, "executing CLO failed\n");
806 break;
807 }
808 }
809 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO);
810 }
811
812 /* reset PHY and decide what is present */
813 if (ata_sata_phy_reset(dev)) {
814
815 /* clear any interrupts pending on this channel */
816 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
817 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
818
819 /* clear SATA error register */
820 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
821
822 /* start operations on this channel */
823 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
824 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
825 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
826
827 signature = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset);
828 if (bootverbose)
829 device_printf(dev, "SIGNATURE: %08x\n", signature);
830 switch (signature) {
831 case 0x00000101:
832 ch->devices = ATA_ATA_MASTER;
833 break;
834 case 0x96690101:
835 ch->devices = ATA_PORTMULTIPLIER;
836 device_printf(ch->dev, "Portmultipliers not supported yet\n");
837 ch->devices = 0;
838 break;
839 case 0xeb140101:
840 ch->devices = ATA_ATAPI_MASTER;
841 break;
842 default: /* SOS XXX */
843 if (bootverbose)
844 device_printf(ch->dev, "No signature, asuming disk device\n");
845 ch->devices = ATA_ATA_MASTER;
846 }
847 }
848 if (bootverbose)
849 device_printf(dev, "ahci_reset devices=0x%b\n", ch->devices,
850 "\2\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
851 }
852
853 static void
854 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
855 {
856 struct ata_dmasetprd_args *args = xsc;
857 struct ata_ahci_dma_prd *prd = args->dmatab;
858 int i;
859
860 if (!(args->error = error)) {
861 for (i = 0; i < nsegs; i++) {
862 prd[i].dba = htole64(segs[i].ds_addr);
863 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK);
864 }
865 }
866 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
867 args->nsegs = nsegs;
868 }
869
870 static void
871 ata_ahci_dmainit(device_t dev)
872 {
873 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
874 struct ata_channel *ch = device_get_softc(dev);
875
876 ata_dmainit(dev);
877 if (ch->dma) {
878 /* note start and stop are not used here */
879 ch->dma->setprd = ata_ahci_dmasetprd;
880 ch->dma->max_iosize = 8192 * DEV_BSIZE;
881 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT)
882 ch->dma->max_address = BUS_SPACE_MAXADDR;
883 }
884 }
885
886 static int
887 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request)
888 {
889 bzero(ctp->cfis, 64);
890 if (request->flags & ATA_R_ATAPI) {
891 bzero(ctp->acmd, 32);
892 bcopy(request->u.atapi.ccb, ctp->acmd, 16);
893 }
894 return ata_request2fis_h2d(request, &ctp->cfis[0]);
895 }
896
897
898 /*
899 * Acard chipset support functions
900 */
901 int
902 ata_acard_ident(device_t dev)
903 {
904 struct ata_pci_controller *ctlr = device_get_softc(dev);
905 static struct ata_chip_id ids[] =
906 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "ATP850" },
907 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "ATP860A" },
908 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "ATP860R" },
909 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "ATP865A" },
910 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "ATP865R" },
911 { 0, 0, 0, 0, 0, 0}};
912
913 if (!(ctlr->chip = ata_match_chip(dev, ids)))
914 return ENXIO;
915
916 ata_set_desc(dev);
917 ctlr->chipinit = ata_acard_chipinit;
918 return 0;
919 }
920
921 static int
922 ata_acard_chipinit(device_t dev)
923 {
924 struct ata_pci_controller *ctlr = device_get_softc(dev);
925
926 if (ata_setup_interrupt(dev))
927 return ENXIO;
928
929 ctlr->allocate = ata_acard_allocate;
930 if (ctlr->chip->cfg1 == ATPOLD) {
931 ctlr->setmode = ata_acard_850_setmode;
932 ctlr->locking = ata_serialize;
933 }
934 else
935 ctlr->setmode = ata_acard_86X_setmode;
936 return 0;
937 }
938
939 static int
940 ata_acard_allocate(device_t dev)
941 {
942 struct ata_channel *ch = device_get_softc(dev);
943
944 /* setup the usual register normal pci style */
945 if (ata_pci_allocate(dev))
946 return ENXIO;
947
948 ch->hw.status = ata_acard_status;
949 return 0;
950 }
951
952 static int
953 ata_acard_status(device_t dev)
954 {
955 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
956 struct ata_channel *ch = device_get_softc(dev);
957
958 if (ctlr->chip->cfg1 == ATPOLD &&
959 ATA_LOCKING(ch->dev, ATA_LF_WHICH) != ch->unit)
960 return 0;
961 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
962 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
963
964 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
965 ATA_BMSTAT_INTERRUPT)
966 return 0;
967 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
968 DELAY(1);
969 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
970 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
971 DELAY(1);
972 }
973 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
974 DELAY(100);
975 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
976 return 0;
977 }
978 return 1;
979 }
980
981 static void
982 ata_acard_850_setmode(device_t dev, int mode)
983 {
984 device_t gparent = GRANDPARENT(dev);
985 struct ata_pci_controller *ctlr = device_get_softc(gparent);
986 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
987 struct ata_device *atadev = device_get_softc(dev);
988 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
989 int error;
990
991 mode = ata_limit_mode(dev, mode,
992 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
993
994 /* XXX SOS missing WDMA0+1 + PIO modes */
995 if (mode >= ATA_WDMA2) {
996 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
997 if (bootverbose)
998 device_printf(dev, "%ssetting %s on %s chip\n",
999 (error) ? "FAILURE " : "",
1000 ata_mode2str(mode), ctlr->chip->text);
1001 if (!error) {
1002 u_int8_t reg54 = pci_read_config(gparent, 0x54, 1);
1003
1004 reg54 &= ~(0x03 << (devno << 1));
1005 if (mode >= ATA_UDMA0)
1006 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1));
1007 pci_write_config(gparent, 0x54, reg54, 1);
1008 pci_write_config(gparent, 0x4a, 0xa6, 1);
1009 pci_write_config(gparent, 0x40 + (devno << 1), 0x0301, 2);
1010 atadev->mode = mode;
1011 return;
1012 }
1013 }
1014 /* we could set PIO mode timings, but we assume the BIOS did that */
1015 }
1016
1017 static void
1018 ata_acard_86X_setmode(device_t dev, int mode)
1019 {
1020 device_t gparent = GRANDPARENT(dev);
1021 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1022 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1023 struct ata_device *atadev = device_get_softc(dev);
1024 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1025 int error;
1026
1027
1028 mode = ata_limit_mode(dev, mode,
1029 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
1030
1031 mode = ata_check_80pin(dev, mode);
1032
1033 /* XXX SOS missing WDMA0+1 + PIO modes */
1034 if (mode >= ATA_WDMA2) {
1035 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1036 if (bootverbose)
1037 device_printf(dev, "%ssetting %s on %s chip\n",
1038 (error) ? "FAILURE " : "",
1039 ata_mode2str(mode), ctlr->chip->text);
1040 if (!error) {
1041 u_int16_t reg44 = pci_read_config(gparent, 0x44, 2);
1042
1043 reg44 &= ~(0x000f << (devno << 2));
1044 if (mode >= ATA_UDMA0)
1045 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2));
1046 pci_write_config(gparent, 0x44, reg44, 2);
1047 pci_write_config(gparent, 0x4a, 0xa6, 1);
1048 pci_write_config(gparent, 0x40 + devno, 0x31, 1);
1049 atadev->mode = mode;
1050 return;
1051 }
1052 }
1053 /* we could set PIO mode timings, but we assume the BIOS did that */
1054 }
1055
1056
1057 /*
1058 * Acer Labs Inc (ALI) chipset support functions
1059 */
1060 int
1061 ata_ali_ident(device_t dev)
1062 {
1063 struct ata_pci_controller *ctlr = device_get_softc(dev);
1064 static struct ata_chip_id ids[] =
1065 {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" },
1066 { ATA_ALI_5288, 0x00, 4, ALISATA, ATA_SA300, "M5288" },
1067 { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "M5287" },
1068 { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "M5281" },
1069 { ATA_ALI_5229, 0xc5, 0, ALINEW, ATA_UDMA6, "M5229" },
1070 { ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "M5229" },
1071 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "M5229" },
1072 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "M5229" },
1073 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "M5229" },
1074 { 0, 0, 0, 0, 0, 0}};
1075
1076 if (!(ctlr->chip = ata_match_chip(dev, ids)))
1077 return ENXIO;
1078
1079 ata_set_desc(dev);
1080 ctlr->chipinit = ata_ali_chipinit;
1081 return 0;
1082 }
1083
1084 static int
1085 ata_ali_chipinit(device_t dev)
1086 {
1087 struct ata_pci_controller *ctlr = device_get_softc(dev);
1088
1089 if (ata_setup_interrupt(dev))
1090 return ENXIO;
1091
1092 switch (ctlr->chip->cfg2) {
1093 case ALISATA:
1094 ctlr->channels = ctlr->chip->cfg1;
1095 ctlr->allocate = ata_ali_sata_allocate;
1096 ctlr->setmode = ata_sata_setmode;
1097
1098 /* AHCI mode is correctly supported only on the ALi 5288. */
1099 if ((ctlr->chip->chipid == ATA_ALI_5288) &&
1100 (ata_ahci_chipinit(dev) != ENXIO))
1101 return 0;
1102
1103 /* enable PCI interrupt */
1104 pci_write_config(dev, PCIR_COMMAND,
1105 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
1106 break;
1107
1108 case ALINEW:
1109 /* use device interrupt as byte count end */
1110 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
1111
1112 /* enable cable detection and UDMA support on newer chips */
1113 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1);
1114
1115 /* enable ATAPI UDMA mode */
1116 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1);
1117
1118 /* only chips with revision > 0xc4 can do 48bit DMA */
1119 if (ctlr->chip->chiprev <= 0xc4)
1120 device_printf(dev,
1121 "using PIO transfers above 137GB as workaround for "
1122 "48bit DMA access bug, expect reduced performance\n");
1123 ctlr->allocate = ata_ali_allocate;
1124 ctlr->reset = ata_ali_reset;
1125 ctlr->setmode = ata_ali_setmode;
1126 break;
1127
1128 case ALIOLD:
1129 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
1130 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
1131 ctlr->setmode = ata_ali_setmode;
1132 break;
1133 }
1134 return 0;
1135 }
1136
1137 static int
1138 ata_ali_allocate(device_t dev)
1139 {
1140 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1141 struct ata_channel *ch = device_get_softc(dev);
1142
1143 /* setup the usual register normal pci style */
1144 if (ata_pci_allocate(dev))
1145 return ENXIO;
1146
1147 /* older chips can't do 48bit DMA transfers */
1148 if (ctlr->chip->chiprev <= 0xc4)
1149 ch->flags |= ATA_NO_48BIT_DMA;
1150
1151 return 0;
1152 }
1153
1154 static int
1155 ata_ali_sata_allocate(device_t dev)
1156 {
1157 device_t parent = device_get_parent(dev);
1158 struct ata_pci_controller *ctlr = device_get_softc(parent);
1159 struct ata_channel *ch = device_get_softc(dev);
1160 struct resource *io = NULL, *ctlio = NULL;
1161 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
1162 int i, rid;
1163
1164 rid = PCIR_BAR(0) + (unit01 ? 8 : 0);
1165 io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1166 if (!io)
1167 return ENXIO;
1168
1169 rid = PCIR_BAR(1) + (unit01 ? 8 : 0);
1170 ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1171 if (!ctlio) {
1172 bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io);
1173 return ENXIO;
1174 }
1175
1176 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
1177 ch->r_io[i].res = io;
1178 ch->r_io[i].offset = i + (unit10 ? 8 : 0);
1179 }
1180 ch->r_io[ATA_CONTROL].res = ctlio;
1181 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0);
1182 ch->r_io[ATA_IDX_ADDR].res = io;
1183 ata_default_registers(dev);
1184 if (ctlr->r_res1) {
1185 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
1186 ch->r_io[i].res = ctlr->r_res1;
1187 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
1188 }
1189 }
1190 ch->flags |= ATA_NO_SLAVE;
1191
1192 /* XXX SOS PHY handling awkward in ALI chip not supported yet */
1193 ata_pci_hw(dev);
1194 return 0;
1195 }
1196
1197 static void
1198 ata_ali_reset(device_t dev)
1199 {
1200 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1201 struct ata_channel *ch = device_get_softc(dev);
1202 device_t *children;
1203 int nchildren, i;
1204
1205 ata_generic_reset(dev);
1206
1207 /*
1208 * workaround for datacorruption bug found on at least SUN Blade-100
1209 * find the ISA function on the southbridge and disable then enable
1210 * the ATA channel tristate buffer
1211 */
1212 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) {
1213 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) {
1214 for (i = 0; i < nchildren; i++) {
1215 if (pci_get_devid(children[i]) == ATA_ALI_1533) {
1216 pci_write_config(children[i], 0x58,
1217 pci_read_config(children[i], 0x58, 1) &
1218 ~(0x04 << ch->unit), 1);
1219 pci_write_config(children[i], 0x58,
1220 pci_read_config(children[i], 0x58, 1) |
1221 (0x04 << ch->unit), 1);
1222 break;
1223 }
1224 }
1225 free(children, M_TEMP);
1226 }
1227 }
1228 }
1229
1230 static void
1231 ata_ali_setmode(device_t dev, int mode)
1232 {
1233 device_t gparent = GRANDPARENT(dev);
1234 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1235 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1236 struct ata_device *atadev = device_get_softc(dev);
1237 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1238 int error;
1239
1240 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1241
1242 if (ctlr->chip->cfg2 & ALINEW) {
1243 if (mode > ATA_UDMA2 &&
1244 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) {
1245 ata_print_cable(dev, "controller");
1246 mode = ATA_UDMA2;
1247 }
1248 }
1249 else
1250 mode = ata_check_80pin(dev, mode);
1251
1252 if (ctlr->chip->cfg2 & ALIOLD) {
1253 /* doesn't support ATAPI DMA on write */
1254 ch->flags |= ATA_ATAPI_DMA_RO;
1255 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) {
1256 /* doesn't support ATAPI DMA on two ATAPI devices */
1257 device_printf(dev, "two atapi devices on this channel, no DMA\n");
1258 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1259 }
1260 }
1261
1262 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1263
1264 if (bootverbose)
1265 device_printf(dev, "%ssetting %s on %s chip\n",
1266 (error) ? "FAILURE " : "",
1267 ata_mode2str(mode), ctlr->chip->text);
1268 if (!error) {
1269 if (mode >= ATA_UDMA0) {
1270 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d};
1271 u_int32_t word54 = pci_read_config(gparent, 0x54, 4);
1272
1273 word54 &= ~(0x000f000f << (devno << 2));
1274 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
1275 pci_write_config(gparent, 0x54, word54, 4);
1276 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1277 0x00310001, 4);
1278 }
1279 else {
1280 u_int32_t piotimings[] =
1281 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
1282 0x00310001, 0x00440001, 0x00330001, 0x00310001};
1283
1284 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) &
1285 ~(0x0008000f << (devno << 2)), 4);
1286 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1287 piotimings[ata_mode2idx(mode)], 4);
1288 }
1289 atadev->mode = mode;
1290 }
1291 }
1292
1293
1294 /*
1295 * American Micro Devices (AMD) chipset support functions
1296 */
1297 int
1298 ata_amd_ident(device_t dev)
1299 {
1300 struct ata_pci_controller *ctlr = device_get_softc(dev);
1301 static struct ata_chip_id ids[] =
1302 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "756" },
1303 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "766" },
1304 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "768" },
1305 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "8111" },
1306 { ATA_AMD5536, 0x00, AMDNVIDIA, 0x00, ATA_UDMA5, "CS5536" },
1307 { 0, 0, 0, 0, 0, 0}};
1308
1309 if (!(ctlr->chip = ata_match_chip(dev, ids)))
1310 return ENXIO;
1311
1312 ata_set_desc(dev);
1313 ctlr->chipinit = ata_amd_chipinit;
1314 return 0;
1315 }
1316
1317 static int
1318 ata_amd_chipinit(device_t dev)
1319 {
1320 struct ata_pci_controller *ctlr = device_get_softc(dev);
1321
1322 if (ata_setup_interrupt(dev))
1323 return ENXIO;
1324
1325 /* disable/set prefetch, postwrite */
1326 if (ctlr->chip->cfg2 & AMDBUG)
1327 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1);
1328 else
1329 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
1330
1331 ctlr->setmode = ata_via_family_setmode;
1332 return 0;
1333 }
1334
1335
1336 /*
1337 * ATI chipset support functions
1338 */
1339 int
1340 ata_ati_ident(device_t dev)
1341 {
1342 struct ata_pci_controller *ctlr = device_get_softc(dev);
1343 static struct ata_chip_id ids[] =
1344 {{ ATA_ATI_IXP200, 0x00, 0, 0, ATA_UDMA5, "IXP200" },
1345 { ATA_ATI_IXP300, 0x00, 0, 0, ATA_UDMA6, "IXP300" },
1346 { ATA_ATI_IXP300_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP300" },
1347 { ATA_ATI_IXP400, 0x00, 0, 0, ATA_UDMA6, "IXP400" },
1348 { ATA_ATI_IXP400_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" },
1349 { ATA_ATI_IXP400_S2, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" },
1350 { ATA_ATI_IXP600, 0x00, 0, 0, ATA_UDMA6, "IXP600" },
1351 { ATA_ATI_IXP700, 0x00, 0, 0, ATA_UDMA6, "IXP700" },
1352 { 0, 0, 0, 0, 0, 0}};
1353
1354 if (!(ctlr->chip = ata_match_chip(dev, ids)))
1355 return ENXIO;
1356
1357 ata_set_desc(dev);
1358
1359 /* the ATI SATA controller is actually a SiI 3112 controller*/
1360 if (ctlr->chip->cfg1 & SIIMEMIO)
1361 ctlr->chipinit = ata_sii_chipinit;
1362 else
1363 ctlr->chipinit = ata_ati_chipinit;
1364 return 0;
1365 }
1366
1367 static int
1368 ata_ati_chipinit(device_t dev)
1369 {
1370 struct ata_pci_controller *ctlr = device_get_softc(dev);
1371
1372 if (ata_setup_interrupt(dev))
1373 return ENXIO;
1374
1375 /* IXP600 & IXP700 only have 1 PATA channel */
1376 if ((ctlr->chip->chipid == ATA_ATI_IXP600) ||
1377 (ctlr->chip->chipid == ATA_ATI_IXP700))
1378 ctlr->channels = 1;
1379
1380 ctlr->setmode = ata_ati_setmode;
1381 return 0;
1382 }
1383
1384 static void
1385 ata_ati_setmode(device_t dev, int mode)
1386 {
1387 device_t gparent = GRANDPARENT(dev);
1388 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1389 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1390 struct ata_device *atadev = device_get_softc(dev);
1391 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1392 int offset = (devno ^ 0x01) << 3;
1393 int error;
1394 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1395 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1396 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
1397
1398 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1399
1400 mode = ata_check_80pin(dev, mode);
1401
1402 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1403
1404 if (bootverbose)
1405 device_printf(dev, "%ssetting %s on %s chip\n",
1406 (error) ? "FAILURE " : "",
1407 ata_mode2str(mode), ctlr->chip->text);
1408 if (!error) {
1409 if (mode >= ATA_UDMA0) {
1410 pci_write_config(gparent, 0x56,
1411 (pci_read_config(gparent, 0x56, 2) &
1412 ~(0xf << (devno << 2))) |
1413 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
1414 pci_write_config(gparent, 0x54,
1415 pci_read_config(gparent, 0x54, 1) |
1416 (0x01 << devno), 1);
1417 pci_write_config(gparent, 0x44,
1418 (pci_read_config(gparent, 0x44, 4) &
1419 ~(0xff << offset)) |
1420 (dmatimings[2] << offset), 4);
1421 }
1422 else if (mode >= ATA_WDMA0) {
1423 pci_write_config(gparent, 0x54,
1424 pci_read_config(gparent, 0x54, 1) &
1425 ~(0x01 << devno), 1);
1426 pci_write_config(gparent, 0x44,
1427 (pci_read_config(gparent, 0x44, 4) &
1428 ~(0xff << offset)) |
1429 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
1430 }
1431 else
1432 pci_write_config(gparent, 0x54,
1433 pci_read_config(gparent, 0x54, 1) &
1434 ~(0x01 << devno), 1);
1435
1436 pci_write_config(gparent, 0x4a,
1437 (pci_read_config(gparent, 0x4a, 2) &
1438 ~(0xf << (devno << 2))) |
1439 (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2);
1440 pci_write_config(gparent, 0x40,
1441 (pci_read_config(gparent, 0x40, 4) &
1442 ~(0xff << offset)) |
1443 (piotimings[ata_mode2idx(mode)] << offset), 4);
1444 atadev->mode = mode;
1445 }
1446 }
1447
1448
1449 /*
1450 * Cyrix chipset support functions
1451 */
1452 int
1453 ata_cyrix_ident(device_t dev)
1454 {
1455 struct ata_pci_controller *ctlr = device_get_softc(dev);
1456
1457 if (pci_get_devid(dev) == ATA_CYRIX_5530) {
1458 device_set_desc(dev, "Cyrix 5530 ATA33 controller");
1459 ctlr->chipinit = ata_cyrix_chipinit;
1460 return 0;
1461 }
1462 return ENXIO;
1463 }
1464
1465 static int
1466 ata_cyrix_chipinit(device_t dev)
1467 {
1468 struct ata_pci_controller *ctlr = device_get_softc(dev);
1469
1470 if (ata_setup_interrupt(dev))
1471 return ENXIO;
1472
1473 if (ctlr->r_res1)
1474 ctlr->setmode = ata_cyrix_setmode;
1475 else
1476 ctlr->setmode = ata_generic_setmode;
1477 return 0;
1478 }
1479
1480 static void
1481 ata_cyrix_setmode(device_t dev, int mode)
1482 {
1483 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1484 struct ata_device *atadev = device_get_softc(dev);
1485 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1486 u_int32_t piotiming[] =
1487 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
1488 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
1489 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
1490 int error;
1491
1492 ch->dma->alignment = 16;
1493 ch->dma->max_iosize = 126 * DEV_BSIZE;
1494
1495 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
1496
1497 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1498
1499 if (bootverbose)
1500 device_printf(dev, "%ssetting %s on Cyrix chip\n",
1501 (error) ? "FAILURE " : "", ata_mode2str(mode));
1502 if (!error) {
1503 if (mode >= ATA_UDMA0) {
1504 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1505 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]);
1506 }
1507 else if (mode >= ATA_WDMA0) {
1508 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1509 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]);
1510 }
1511 else {
1512 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1513 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]);
1514 }
1515 atadev->mode = mode;
1516 }
1517 }
1518
1519
1520 /*
1521 * Cypress chipset support functions
1522 */
1523 int
1524 ata_cypress_ident(device_t dev)
1525 {
1526 struct ata_pci_controller *ctlr = device_get_softc(dev);
1527
1528 /*
1529 * the Cypress chip is a mess, it contains two ATA functions, but
1530 * both channels are visible on the first one.
1531 * simply ignore the second function for now, as the right
1532 * solution (ignoring the second channel on the first function)
1533 * doesn't work with the crappy ATA interrupt setup on the alpha.
1534 */
1535 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 &&
1536 pci_get_function(dev) == 1 &&
1537 pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
1538 device_set_desc(dev, "Cypress 82C693 ATA controller");
1539 ctlr->chipinit = ata_cypress_chipinit;
1540 return 0;
1541 }
1542 return ENXIO;
1543 }
1544
1545 static int
1546 ata_cypress_chipinit(device_t dev)
1547 {
1548 struct ata_pci_controller *ctlr = device_get_softc(dev);
1549
1550 if (ata_setup_interrupt(dev))
1551 return ENXIO;
1552
1553 ctlr->setmode = ata_cypress_setmode;
1554 return 0;
1555 }
1556
1557 static void
1558 ata_cypress_setmode(device_t dev, int mode)
1559 {
1560 device_t gparent = GRANDPARENT(dev);
1561 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1562 struct ata_device *atadev = device_get_softc(dev);
1563 int error;
1564
1565 mode = ata_limit_mode(dev, mode, ATA_WDMA2);
1566
1567 /* XXX SOS missing WDMA0+1 + PIO modes */
1568 if (mode == ATA_WDMA2) {
1569 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1570 if (bootverbose)
1571 device_printf(dev, "%ssetting WDMA2 on Cypress chip\n",
1572 error ? "FAILURE " : "");
1573 if (!error) {
1574 pci_write_config(gparent, ch->unit ? 0x4e : 0x4c, 0x2020, 2);
1575 atadev->mode = mode;
1576 return;
1577 }
1578 }
1579 /* we could set PIO mode timings, but we assume the BIOS did that */
1580 }
1581
1582
1583 /*
1584 * HighPoint chipset support functions
1585 */
1586 int
1587 ata_highpoint_ident(device_t dev)
1588 {
1589 struct ata_pci_controller *ctlr = device_get_softc(dev);
1590 struct ata_chip_id *idx;
1591 static struct ata_chip_id ids[] =
1592 {{ ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HPT374" },
1593 { ATA_HPT372, 0x02, HPT372, 0x00, ATA_UDMA6, "HPT372N" },
1594 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1595 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT371" },
1596 { ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1597 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HPT370" },
1598 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HPT368" },
1599 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HPT366" },
1600 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT302" },
1601 { 0, 0, 0, 0, 0, 0}};
1602 char buffer[64];
1603
1604 if (!(idx = ata_match_chip(dev, ids)))
1605 return ENXIO;
1606
1607 strcpy(buffer, "HighPoint ");
1608 strcat(buffer, idx->text);
1609 if (idx->cfg1 == HPT374) {
1610 if (pci_get_function(dev) == 0)
1611 strcat(buffer, " (channel 0+1)");
1612 if (pci_get_function(dev) == 1)
1613 strcat(buffer, " (channel 2+3)");
1614 }
1615 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
1616 device_set_desc_copy(dev, buffer);
1617 ctlr->chip = idx;
1618 ctlr->chipinit = ata_highpoint_chipinit;
1619 return 0;
1620 }
1621
1622 static int
1623 ata_highpoint_chipinit(device_t dev)
1624 {
1625 struct ata_pci_controller *ctlr = device_get_softc(dev);
1626
1627 if (ata_setup_interrupt(dev))
1628 return ENXIO;
1629
1630 if (ctlr->chip->cfg2 == HPTOLD) {
1631 /* disable interrupt prediction */
1632 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
1633 }
1634 else {
1635 /* disable interrupt prediction */
1636 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
1637 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
1638
1639 /* enable interrupts */
1640 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
1641
1642 /* set clocks etc */
1643 if (ctlr->chip->cfg1 < HPT372)
1644 pci_write_config(dev, 0x5b, 0x22, 1);
1645 else
1646 pci_write_config(dev, 0x5b,
1647 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
1648 }
1649 ctlr->allocate = ata_highpoint_allocate;
1650 ctlr->setmode = ata_highpoint_setmode;
1651 return 0;
1652 }
1653
1654 static int
1655 ata_highpoint_allocate(device_t dev)
1656 {
1657 struct ata_channel *ch = device_get_softc(dev);
1658
1659 /* setup the usual register normal pci style */
1660 if (ata_pci_allocate(dev))
1661 return ENXIO;
1662
1663 ch->flags |= ATA_ALWAYS_DMASTAT;
1664 return 0;
1665 }
1666
1667 static void
1668 ata_highpoint_setmode(device_t dev, int mode)
1669 {
1670 device_t gparent = GRANDPARENT(dev);
1671 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1672 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1673 struct ata_device *atadev = device_get_softc(dev);
1674 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1675 int error;
1676 u_int32_t timings33[][4] = {
1677 /* HPT366 HPT370 HPT372 HPT374 mode */
1678 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
1679 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
1680 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
1681 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
1682 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
1683 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
1684 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
1685 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
1686 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */
1687 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */
1688 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */
1689 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */
1690 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */
1691 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */
1692 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */
1693 };
1694
1695 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1696
1697 if (ctlr->chip->cfg1 == HPT366 && ata_atapi(dev))
1698 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1699
1700 mode = ata_highpoint_check_80pin(dev, mode);
1701
1702 /*
1703 * most if not all HPT chips cant really handle that the device is
1704 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to
1705 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance
1706 */
1707 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
1708 ata_limit_mode(dev, mode, ATA_UDMA5));
1709 if (bootverbose)
1710 device_printf(dev, "%ssetting %s on HighPoint chip\n",
1711 (error) ? "FAILURE " : "", ata_mode2str(mode));
1712 if (!error)
1713 pci_write_config(gparent, 0x40 + (devno << 2),
1714 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
1715 atadev->mode = mode;
1716 }
1717
1718 static int
1719 ata_highpoint_check_80pin(device_t dev, int mode)
1720 {
1721 device_t gparent = GRANDPARENT(dev);
1722 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1723 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1724 u_int8_t reg, val, res;
1725
1726 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(gparent) == 1) {
1727 reg = ch->unit ? 0x57 : 0x53;
1728 val = pci_read_config(gparent, reg, 1);
1729 pci_write_config(gparent, reg, val | 0x80, 1);
1730 }
1731 else {
1732 reg = 0x5b;
1733 val = pci_read_config(gparent, reg, 1);
1734 pci_write_config(gparent, reg, val & 0xfe, 1);
1735 }
1736 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2);
1737 pci_write_config(gparent, reg, val, 1);
1738
1739 if (mode > ATA_UDMA2 && res) {
1740 ata_print_cable(dev, "controller");
1741 mode = ATA_UDMA2;
1742 }
1743 return mode;
1744 }
1745
1746
1747 /*
1748 * Intel chipset support functions
1749 */
1750 int
1751 ata_intel_ident(device_t dev)
1752 {
1753 struct ata_pci_controller *ctlr = device_get_softc(dev);
1754 static struct ata_chip_id ids[] =
1755 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "PIIX" },
1756 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "PIIX3" },
1757 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1758 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1759 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1760 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "ICH0" },
1761 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "ICH" },
1762 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "ICH" },
1763 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "ICH2" },
1764 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "ICH2" },
1765 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "ICH3" },
1766 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "ICH3" },
1767 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "ICH4" },
1768 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "ICH4" },
1769 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "ICH5" },
1770 { ATA_I82801EB_S1, 0, 0, 0x00, ATA_SA150, "ICH5" },
1771 { ATA_I82801EB_R1, 0, 0, 0x00, ATA_SA150, "ICH5" },
1772 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "6300ESB" },
1773 { ATA_I6300ESB_S1, 0, 0, 0x00, ATA_SA150, "6300ESB" },
1774 { ATA_I6300ESB_R1, 0, 0, 0x00, ATA_SA150, "6300ESB" },
1775 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "ICH6" },
1776 { ATA_I82801FB_S1, 0, AHCI, 0x00, ATA_SA150, "ICH6" },
1777 { ATA_I82801FB_R1, 0, AHCI, 0x00, ATA_SA150, "ICH6" },
1778 { ATA_I82801FBM, 0, AHCI, 0x00, ATA_SA150, "ICH6M" },
1779 { ATA_I82801GB, 0, 0, 0x00, ATA_UDMA5, "ICH7" },
1780 { ATA_I82801GB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1781 { ATA_I82801GB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1782 { ATA_I82801GB_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1783 { ATA_I82801GBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1784 { ATA_I82801GBM_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1785 { ATA_I82801GBM_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1786 { ATA_I63XXESB2, 0, 0, 0x00, ATA_UDMA5, "63XXESB2" },
1787 { ATA_I63XXESB2_S1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1788 { ATA_I63XXESB2_S2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1789 { ATA_I63XXESB2_R1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1790 { ATA_I63XXESB2_R2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1791 { ATA_I82801HB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1792 { ATA_I82801HB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1793 { ATA_I82801HB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1794 { ATA_I82801HB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1795 { ATA_I82801HB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1796 { ATA_I82801HBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8M" },
1797 { ATA_I82801HBM_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8M" },
1798 { ATA_I82801IB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1799 { ATA_I82801IB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1800 { ATA_I82801IB_AH2, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1801 { ATA_I82801IB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1802 { ATA_I82801IB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1803 { ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" },
1804 { 0, 0, 0, 0, 0, 0}};
1805
1806 if (!(ctlr->chip = ata_match_chip(dev, ids)))
1807 return ENXIO;
1808
1809 ata_set_desc(dev);
1810 ctlr->chipinit = ata_intel_chipinit;
1811 return 0;
1812 }
1813
1814 static int
1815 ata_intel_chipinit(device_t dev)
1816 {
1817 struct ata_pci_controller *ctlr = device_get_softc(dev);
1818
1819 if (ata_setup_interrupt(dev))
1820 return ENXIO;
1821
1822 /* good old PIIX needs special treatment (not implemented) */
1823 if (ctlr->chip->chipid == ATA_I82371FB) {
1824 ctlr->setmode = ata_intel_old_setmode;
1825 }
1826
1827 /* the intel 31244 needs special care if in DPA mode */
1828 else if (ctlr->chip->chipid == ATA_I31244) {
1829 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) {
1830 ctlr->r_type2 = SYS_RES_MEMORY;
1831 ctlr->r_rid2 = PCIR_BAR(0);
1832 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1833 &ctlr->r_rid2,
1834 RF_ACTIVE)))
1835 return ENXIO;
1836 ctlr->channels = 4;
1837 ctlr->allocate = ata_intel_31244_allocate;
1838 ctlr->reset = ata_intel_31244_reset;
1839 }
1840 ctlr->setmode = ata_sata_setmode;
1841 }
1842
1843 /* non SATA intel chips goes here */
1844 else if (ctlr->chip->max_dma < ATA_SA150) {
1845 ctlr->allocate = ata_intel_allocate;
1846 ctlr->setmode = ata_intel_new_setmode;
1847 }
1848
1849 /* SATA parts can be either compat or AHCI */
1850 else {
1851 /* force all ports active "the legacy way" */
1852 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2);
1853
1854 ctlr->allocate = ata_intel_allocate;
1855 ctlr->reset = ata_intel_reset;
1856
1857 /*
1858 * if we have AHCI capability and AHCI or RAID mode enabled
1859 * in BIOS we try for AHCI mode
1860 */
1861 if ((ctlr->chip->cfg1 == AHCI) &&
1862 (pci_read_config(dev, 0x90, 1) & 0xc0) &&
1863 (ata_ahci_chipinit(dev) != ENXIO))
1864 return 0;
1865
1866 /* if BAR(5) is IO it should point to SATA interface registers */
1867 ctlr->r_type2 = SYS_RES_IOPORT;
1868 ctlr->r_rid2 = PCIR_BAR(5);
1869 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1870 &ctlr->r_rid2, RF_ACTIVE)))
1871 ctlr->setmode = ata_intel_sata_setmode;
1872 else
1873 ctlr->setmode = ata_sata_setmode;
1874
1875 /* enable PCI interrupt */
1876 pci_write_config(dev, PCIR_COMMAND,
1877 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
1878 }
1879 return 0;
1880 }
1881
1882 static int
1883 ata_intel_allocate(device_t dev)
1884 {
1885 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1886 struct ata_channel *ch = device_get_softc(dev);
1887
1888 /* setup the usual register normal pci style */
1889 if (ata_pci_allocate(dev))
1890 return ENXIO;
1891
1892 /* if r_res2 is valid it points to SATA interface registers */
1893 if (ctlr->r_res2) {
1894 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
1895 ch->r_io[ATA_IDX_ADDR].offset = 0x00;
1896 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2;
1897 ch->r_io[ATA_IDX_DATA].offset = 0x04;
1898 }
1899
1900 ch->flags |= ATA_ALWAYS_DMASTAT;
1901 return 0;
1902 }
1903
1904 static void
1905 ata_intel_reset(device_t dev)
1906 {
1907 device_t parent = device_get_parent(dev);
1908 struct ata_pci_controller *ctlr = device_get_softc(parent);
1909 struct ata_channel *ch = device_get_softc(dev);
1910 int mask, timeout;
1911
1912 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */
1913 if (ctlr->chip->cfg1) {
1914 mask = (0x0005 << ch->unit);
1915 }
1916 else {
1917 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */
1918 if (pci_read_config(parent, 0x90, 1) & 0x04)
1919 mask = 0x0003;
1920 else {
1921 mask = (0x0001 << ch->unit);
1922 /* XXX SOS should be in intel_allocate if we grow it */
1923 ch->flags |= ATA_NO_SLAVE;
1924 }
1925 }
1926 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2);
1927 DELAY(10);
1928 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2);
1929
1930 /* wait up to 1 sec for "connect well" */
1931 for (timeout = 0; timeout < 100 ; timeout++) {
1932 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) &&
1933 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff))
1934 break;
1935 ata_udelay(10000);
1936 }
1937 ata_generic_reset(dev);
1938 }
1939
1940 static void
1941 ata_intel_old_setmode(device_t dev, int mode)
1942 {
1943 /* NOT YET */
1944 }
1945
1946 static void
1947 ata_intel_new_setmode(device_t dev, int mode)
1948 {
1949 device_t gparent = GRANDPARENT(dev);
1950 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1951 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1952 struct ata_device *atadev = device_get_softc(dev);
1953 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1954 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4);
1955 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1);
1956 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1);
1957 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2);
1958 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2);
1959 u_int32_t mask40 = 0, new40 = 0;
1960 u_int8_t mask44 = 0, new44 = 0;
1961 int error;
1962 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
1963 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
1964
1965 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1966
1967 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
1968 ata_print_cable(dev, "controller");
1969 mode = ATA_UDMA2;
1970 }
1971
1972 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1973
1974 if (bootverbose)
1975 device_printf(dev, "%ssetting %s on %s chip\n",
1976 (error) ? "FAILURE " : "",
1977 ata_mode2str(mode), ctlr->chip->text);
1978 if (error)
1979 return;
1980
1981 if (mode >= ATA_UDMA0) {
1982 pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2);
1983 pci_write_config(gparent, 0x4a,
1984 (reg4a & ~(0x3 << (devno << 2))) |
1985 ((0x01 + !(mode & 0x01)) << (devno << 2)), 2);
1986 }
1987 else {
1988 pci_write_config(gparent, 0x48, reg48 & ~(0x0001 << devno), 2);
1989 pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))), 2);
1990 }
1991 reg54 |= 0x0400;
1992 if (mode >= ATA_UDMA2)
1993 pci_write_config(gparent, 0x54, reg54 | (0x1 << devno), 2);
1994 else
1995 pci_write_config(gparent, 0x54, reg54 & ~(0x1 << devno), 2);
1996
1997 if (mode >= ATA_UDMA5)
1998 pci_write_config(gparent, 0x54, reg54 | (0x1000 << devno), 2);
1999 else
2000 pci_write_config(gparent, 0x54, reg54 & ~(0x1000 << devno), 2);
2001
2002 reg40 &= ~0x00ff00ff;
2003 reg40 |= 0x40774077;
2004
2005 if (atadev->unit == ATA_MASTER) {
2006 mask40 = 0x3300;
2007 new40 = timings[ata_mode2idx(mode)] << 8;
2008 }
2009 else {
2010 mask44 = 0x0f;
2011 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
2012 (timings[ata_mode2idx(mode)] & 0x03);
2013 }
2014 if (ch->unit) {
2015 mask40 <<= 16;
2016 new40 <<= 16;
2017 mask44 <<= 4;
2018 new44 <<= 4;
2019 }
2020 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4);
2021 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1);
2022
2023 atadev->mode = mode;
2024 }
2025
2026 static void
2027 ata_intel_sata_setmode(device_t dev, int mode)
2028 {
2029 struct ata_device *atadev = device_get_softc(dev);
2030
2031 if (atadev->param.satacapabilities != 0x0000 &&
2032 atadev->param.satacapabilities != 0xffff) {
2033
2034 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2035 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2036
2037 /* on some drives we need to set the transfer mode */
2038 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
2039 ata_limit_mode(dev, mode, ATA_UDMA6));
2040
2041 /* set ATA_SSTATUS register offset */
2042 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, devno * 0x100);
2043
2044 /* query SATA STATUS for the speed */
2045 if ((ATA_IDX_INL(ch, ATA_IDX_DATA) & ATA_SS_CONWELL_MASK) ==
2046 ATA_SS_CONWELL_GEN2)
2047 atadev->mode = ATA_SA300;
2048 else
2049 atadev->mode = ATA_SA150;
2050 }
2051 else {
2052 mode = ata_limit_mode(dev, mode, ATA_UDMA5);
2053 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2054 atadev->mode = mode;
2055 }
2056 }
2057
2058 static int
2059 ata_intel_31244_allocate(device_t dev)
2060 {
2061 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2062 struct ata_channel *ch = device_get_softc(dev);
2063 int i;
2064 int ch_offset;
2065
2066 ch_offset = 0x200 + ch->unit * 0x200;
2067
2068 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
2069 ch->r_io[i].res = ctlr->r_res2;
2070
2071 /* setup ATA registers */
2072 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
2073 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06;
2074 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
2075 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
2076 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
2077 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
2078 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
2079 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d;
2080 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04;
2081 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c;
2082 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28;
2083 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29;
2084
2085 /* setup DMA registers */
2086 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100;
2087 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104;
2088 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108;
2089
2090 /* setup SATA registers */
2091 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70;
2092 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72;
2093 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74;
2094
2095 ch->flags |= ATA_NO_SLAVE;
2096 ata_pci_hw(dev);
2097 ch->hw.status = ata_intel_31244_status;
2098 ch->hw.tf_write = ata_intel_31244_tf_write;
2099
2100 /* enable PHY state change interrupt */
2101 ATA_OUTL(ctlr->r_res2, 0x4,
2102 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3)));
2103 return 0;
2104 }
2105
2106 static int
2107 ata_intel_31244_status(device_t dev)
2108 {
2109 /* do we have any PHY events ? */
2110 ata_sata_phy_check_events(dev);
2111
2112 /* any drive action to take care of ? */
2113 return ata_pci_status(dev);
2114 }
2115
2116 static void
2117 ata_intel_31244_tf_write(struct ata_request *request)
2118 {
2119 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2120 struct ata_device *atadev = device_get_softc(request->dev);
2121
2122 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
2123 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
2124 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
2125 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) |
2126 (request->u.ata.lba & 0x00ff));
2127 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) |
2128 ((request->u.ata.lba >> 8) & 0x00ff));
2129 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) |
2130 ((request->u.ata.lba >> 16) & 0x00ff));
2131 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | atadev->unit);
2132 }
2133 else {
2134 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
2135 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
2136 if (atadev->flags & ATA_D_USE_CHS) {
2137 int heads, sectors;
2138
2139 if (atadev->param.atavalid & ATA_FLAG_54_58) {
2140 heads = atadev->param.current_heads;
2141 sectors = atadev->param.current_sectors;
2142 }
2143 else {
2144 heads = atadev->param.heads;
2145 sectors = atadev->param.sectors;
2146 }
2147 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
2148 ATA_IDX_OUTB(ch, ATA_CYL_LSB,
2149 (request->u.ata.lba / (sectors * heads)));
2150 ATA_IDX_OUTB(ch, ATA_CYL_MSB,
2151 (request->u.ata.lba / (sectors * heads)) >> 8);
2152 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit |
2153 (((request->u.ata.lba% (sectors * heads)) /
2154 sectors) & 0xf));
2155 }
2156 else {
2157 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
2158 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
2159 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
2160 ATA_IDX_OUTB(ch, ATA_DRIVE,
2161 ATA_D_IBM | ATA_D_LBA | atadev->unit |
2162 ((request->u.ata.lba >> 24) & 0x0f));
2163 }
2164 }
2165 }
2166
2167 static void
2168 ata_intel_31244_reset(device_t dev)
2169 {
2170 if (ata_sata_phy_reset(dev))
2171 ata_generic_reset(dev);
2172 }
2173
2174
2175 /*
2176 * Integrated Technology Express Inc. (ITE) chipset support functions
2177 */
2178 int
2179 ata_ite_ident(device_t dev)
2180 {
2181 struct ata_pci_controller *ctlr = device_get_softc(dev);
2182 static struct ata_chip_id ids[] =
2183 {{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" },
2184 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" },
2185 { 0, 0, 0, 0, 0, 0}};
2186
2187 if (!(ctlr->chip = ata_match_chip(dev, ids)))
2188 return ENXIO;
2189
2190 ata_set_desc(dev);
2191 ctlr->chipinit = ata_ite_chipinit;
2192 return 0;
2193 }
2194
2195 static int
2196 ata_ite_chipinit(device_t dev)
2197 {
2198 struct ata_pci_controller *ctlr = device_get_softc(dev);
2199
2200 if (ata_setup_interrupt(dev))
2201 return ENXIO;
2202
2203 ctlr->setmode = ata_ite_setmode;
2204
2205 /* set PCI mode and 66Mhz reference clock */
2206 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1);
2207
2208 /* set default active & recover timings */
2209 pci_write_config(dev, 0x54, 0x31, 1);
2210 pci_write_config(dev, 0x56, 0x31, 1);
2211 return 0;
2212 }
2213
2214 static void
2215 ata_ite_setmode(device_t dev, int mode)
2216 {
2217 device_t gparent = GRANDPARENT(dev);
2218 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2219 struct ata_device *atadev = device_get_softc(dev);
2220 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2221 int error;
2222
2223 /* correct the mode for what the HW supports */
2224 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2225
2226 /* check the CBLID bits for 80 conductor cable detection */
2227 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) &
2228 (ch->unit ? (1<<3) : (1<<2)))) {
2229 ata_print_cable(dev, "controller");
2230 mode = ATA_UDMA2;
2231 }
2232
2233 /* set the wanted mode on the device */
2234 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2235
2236 if (bootverbose)
2237 device_printf(dev, "%s setting %s on ITE8212F chip\n",
2238 (error) ? "failed" : "success", ata_mode2str(mode));
2239
2240 /* if the device accepted the mode change, setup the HW accordingly */
2241 if (!error) {
2242 if (mode >= ATA_UDMA0) {
2243 u_int8_t udmatiming[] =
2244 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
2245
2246 /* enable UDMA mode */
2247 pci_write_config(gparent, 0x50,
2248 pci_read_config(gparent, 0x50, 1) &
2249 ~(1 << (devno + 3)), 1);
2250
2251 /* set UDMA timing */
2252 pci_write_config(gparent,
2253 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit),
2254 udmatiming[mode & ATA_MODE_MASK], 1);
2255 }
2256 else {
2257 u_int8_t chtiming[] =
2258 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
2259
2260 /* disable UDMA mode */
2261 pci_write_config(gparent, 0x50,
2262 pci_read_config(gparent, 0x50, 1) |
2263 (1 << (devno + 3)), 1);
2264
2265 /* set active and recover timing (shared between master & slave) */
2266 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) <
2267 chtiming[ata_mode2idx(mode)])
2268 pci_write_config(gparent, 0x54 + (ch->unit << 2),
2269 chtiming[ata_mode2idx(mode)], 1);
2270 }
2271 atadev->mode = mode;
2272 }
2273 }
2274
2275
2276 /*
2277 * JMicron chipset support functions
2278 */
2279 int
2280 ata_jmicron_ident(device_t dev)
2281 {
2282 struct ata_pci_controller *ctlr = device_get_softc(dev);
2283 struct ata_chip_id *idx;
2284 static struct ata_chip_id ids[] =
2285 {{ ATA_JMB360, 0, 1, 0, ATA_SA300, "JMB360" },
2286 { ATA_JMB361, 0, 1, 1, ATA_SA300, "JMB361" },
2287 { ATA_JMB363, 0, 2, 1, ATA_SA300, "JMB363" },
2288 { ATA_JMB365, 0, 1, 2, ATA_SA300, "JMB365" },
2289 { ATA_JMB366, 0, 2, 2, ATA_SA300, "JMB366" },
2290 { ATA_JMB368, 0, 0, 1, ATA_UDMA6, "JMB368" },
2291 { 0, 0, 0, 0, 0, 0}};
2292 char buffer[64];
2293
2294 if (!(idx = ata_match_chip(dev, ids)))
2295 return ENXIO;
2296
2297 if ((pci_read_config(dev, 0xdf, 1) & 0x40) &&
2298 (pci_get_function(dev) == (pci_read_config(dev, 0x40, 1) & 0x02 >> 1)))
2299 sprintf(buffer, "JMicron %s %s controller",
2300 idx->text, ata_mode2str(ATA_UDMA6));
2301 else
2302 sprintf(buffer, "JMicron %s %s controller",
2303 idx->text, ata_mode2str(idx->max_dma));
2304 device_set_desc_copy(dev, buffer);
2305 ctlr->chip = idx;
2306 ctlr->chipinit = ata_jmicron_chipinit;
2307 return 0;
2308 }
2309
2310 static int
2311 ata_jmicron_chipinit(device_t dev)
2312 {
2313 struct ata_pci_controller *ctlr = device_get_softc(dev);
2314 int error;
2315
2316 if (ata_setup_interrupt(dev))
2317 return ENXIO;
2318
2319 /* do we have multiple PCI functions ? */
2320 if (pci_read_config(dev, 0xdf, 1) & 0x40) {
2321 /* are we on the AHCI part ? */
2322 if (ata_ahci_chipinit(dev) != ENXIO)
2323 return 0;
2324
2325 /* otherwise we are on the PATA part */
2326 ctlr->allocate = ata_pci_allocate;
2327 ctlr->reset = ata_generic_reset;
2328 ctlr->dmainit = ata_pci_dmainit;
2329 ctlr->setmode = ata_jmicron_setmode;
2330 ctlr->channels = ctlr->chip->cfg2;
2331 }
2332 else {
2333 /* set controller configuration to a combined setup we support */
2334 pci_write_config(dev, 0x40, 0x80c0a131, 4);
2335 pci_write_config(dev, 0x80, 0x01200000, 4);
2336
2337 if (ctlr->chip->cfg1 && (error = ata_ahci_chipinit(dev)))
2338 return error;
2339
2340 ctlr->allocate = ata_jmicron_allocate;
2341 ctlr->reset = ata_jmicron_reset;
2342 ctlr->dmainit = ata_jmicron_dmainit;
2343 ctlr->setmode = ata_jmicron_setmode;
2344
2345 /* set the number of HW channels */
2346 ctlr->channels = ctlr->chip->cfg1 + ctlr->chip->cfg2;
2347 }
2348 return 0;
2349 }
2350
2351 static int
2352 ata_jmicron_allocate(device_t dev)
2353 {
2354 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2355 struct ata_channel *ch = device_get_softc(dev);
2356 int error;
2357
2358 if (ch->unit >= ctlr->chip->cfg1) {
2359 ch->unit -= ctlr->chip->cfg1;
2360 error = ata_pci_allocate(dev);
2361 ch->unit += ctlr->chip->cfg1;
2362 }
2363 else
2364 error = ata_ahci_allocate(dev);
2365 return error;
2366 }
2367
2368 static void
2369 ata_jmicron_reset(device_t dev)
2370 {
2371 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2372 struct ata_channel *ch = device_get_softc(dev);
2373
2374 if (ch->unit >= ctlr->chip->cfg1)
2375 ata_generic_reset(dev);
2376 else
2377 ata_ahci_reset(dev);
2378 }
2379
2380 static void
2381 ata_jmicron_dmainit(device_t dev)
2382 {
2383 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2384 struct ata_channel *ch = device_get_softc(dev);
2385
2386 if (ch->unit >= ctlr->chip->cfg1)
2387 ata_pci_dmainit(dev);
2388 else
2389 ata_ahci_dmainit(dev);
2390 }
2391
2392 static void
2393 ata_jmicron_setmode(device_t dev, int mode)
2394 {
2395 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
2396 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2397
2398 if (pci_read_config(dev, 0xdf, 1) & 0x40 || ch->unit >= ctlr->chip->cfg1) {
2399 struct ata_device *atadev = device_get_softc(dev);
2400
2401 /* check for 80pin cable present */
2402 if (pci_read_config(dev, 0x40, 1) & 0x08)
2403 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
2404 else
2405 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2406
2407 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2408 atadev->mode = mode;
2409 }
2410 else
2411 ata_sata_setmode(dev, mode);
2412 }
2413
2414
2415 /*
2416 * Marvell chipset support functions
2417 */
2418 #define ATA_MV_HOST_BASE(ch) \
2419 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000)
2420 #define ATA_MV_EDMA_BASE(ch) \
2421 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000)
2422
2423 struct ata_marvell_response {
2424 u_int16_t tag;
2425 u_int8_t edma_status;
2426 u_int8_t dev_status;
2427 u_int32_t timestamp;
2428 };
2429
2430 struct ata_marvell_dma_prdentry {
2431 u_int32_t addrlo;
2432 u_int32_t count;
2433 u_int32_t addrhi;
2434 u_int32_t reserved;
2435 };
2436
2437 int
2438 ata_marvell_ident(device_t dev)
2439 {
2440 struct ata_pci_controller *ctlr = device_get_softc(dev);
2441 static struct ata_chip_id ids[] =
2442 {{ ATA_M88SX5040, 0, 4, MV50XX, ATA_SA150, "88SX5040" },
2443 { ATA_M88SX5041, 0, 4, MV50XX, ATA_SA150, "88SX5041" },
2444 { ATA_M88SX5080, 0, 8, MV50XX, ATA_SA150, "88SX5080" },
2445 { ATA_M88SX5081, 0, 8, MV50XX, ATA_SA150, "88SX5081" },
2446 { ATA_M88SX6041, 0, 4, MV60XX, ATA_SA300, "88SX6041" },
2447 { ATA_M88SX6081, 0, 8, MV60XX, ATA_SA300, "88SX6081" },
2448 { ATA_M88SX6101, 0, 1, MV61XX, ATA_UDMA6, "88SX6101" },
2449 { ATA_M88SX6145, 0, 2, MV61XX, ATA_UDMA6, "88SX6145" },
2450 { 0, 0, 0, 0, 0, 0}};
2451
2452 if (!(ctlr->chip = ata_match_chip(dev, ids)))
2453 return ENXIO;
2454
2455 ata_set_desc(dev);
2456
2457 switch (ctlr->chip->cfg2) {
2458 case MV50XX:
2459 case MV60XX:
2460 ctlr->chipinit = ata_marvell_edma_chipinit;
2461 break;
2462 case MV61XX:
2463 ctlr->chipinit = ata_marvell_pata_chipinit;
2464 break;
2465 }
2466 return 0;
2467 }
2468
2469 static int
2470 ata_marvell_pata_chipinit(device_t dev)
2471 {
2472 struct ata_pci_controller *ctlr = device_get_softc(dev);
2473
2474 if (ata_setup_interrupt(dev))
2475 return ENXIO;
2476
2477 ctlr->allocate = ata_marvell_pata_allocate;
2478 ctlr->setmode = ata_marvell_pata_setmode;
2479 ctlr->channels = ctlr->chip->cfg1;
2480 return 0;
2481 }
2482
2483 static int
2484 ata_marvell_pata_allocate(device_t dev)
2485 {
2486 struct ata_channel *ch = device_get_softc(dev);
2487
2488 /* setup the usual register normal pci style */
2489 if (ata_pci_allocate(dev))
2490 return ENXIO;
2491
2492 /* dont use 32 bit PIO transfers */
2493 ch->flags |= ATA_USE_16BIT;
2494
2495 return 0;
2496 }
2497
2498 static void
2499 ata_marvell_pata_setmode(device_t dev, int mode)
2500 {
2501 device_t gparent = GRANDPARENT(dev);
2502 struct ata_pci_controller *ctlr = device_get_softc(gparent);
2503 struct ata_device *atadev = device_get_softc(dev);
2504
2505 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
2506 mode = ata_check_80pin(dev, mode);
2507 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2508 atadev->mode = mode;
2509 }
2510
2511 static int
2512 ata_marvell_edma_chipinit(device_t dev)
2513 {
2514 struct ata_pci_controller *ctlr = device_get_softc(dev);
2515
2516 if (ata_setup_interrupt(dev))
2517 return ENXIO;
2518
2519 ctlr->r_type1 = SYS_RES_MEMORY;
2520 ctlr->r_rid1 = PCIR_BAR(0);
2521 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
2522 &ctlr->r_rid1, RF_ACTIVE)))
2523 return ENXIO;
2524
2525 /* mask all host controller interrupts */
2526 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000);
2527
2528 /* mask all PCI interrupts */
2529 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000);
2530
2531 ctlr->allocate = ata_marvell_edma_allocate;
2532 ctlr->reset = ata_marvell_edma_reset;
2533 ctlr->dmainit = ata_marvell_edma_dmainit;
2534 ctlr->setmode = ata_sata_setmode;
2535 ctlr->channels = ctlr->chip->cfg1;
2536
2537 /* clear host controller interrupts */
2538 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000);
2539 if (ctlr->chip->cfg1 > 4)
2540 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000);
2541
2542 /* clear PCI interrupts */
2543 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000);
2544
2545 /* unmask PCI interrupts we want */
2546 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff);
2547
2548 /* unmask host controller interrupts we want */
2549 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ |
2550 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25));
2551
2552 /* enable PCI interrupt */
2553 pci_write_config(dev, PCIR_COMMAND,
2554 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
2555 return 0;
2556 }
2557
2558 static int
2559 ata_marvell_edma_allocate(device_t dev)
2560 {
2561 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2562 struct ata_channel *ch = device_get_softc(dev);
2563 u_int64_t work = ch->dma->work_bus;
2564 int i;
2565
2566 /* clear work area */
2567 bzero(ch->dma->work, 1024+256);
2568
2569 /* set legacy ATA resources */
2570 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
2571 ch->r_io[i].res = ctlr->r_res1;
2572 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch);
2573 }
2574 ch->r_io[ATA_CONTROL].res = ctlr->r_res1;
2575 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch);
2576 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1;
2577 ata_default_registers(dev);
2578
2579 /* set SATA resources */
2580 switch (ctlr->chip->cfg2) {
2581 case MV50XX:
2582 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2583 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch);
2584 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2585 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch);
2586 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2587 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch);
2588 break;
2589 case MV60XX:
2590 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2591 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch);
2592 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2593 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch);
2594 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2595 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch);
2596 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1;
2597 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch);
2598 break;
2599 }
2600
2601 ch->flags |= ATA_NO_SLAVE;
2602 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */
2603 ata_generic_hw(dev);
2604 ch->hw.begin_transaction = ata_marvell_edma_begin_transaction;
2605 ch->hw.end_transaction = ata_marvell_edma_end_transaction;
2606 ch->hw.status = ata_marvell_edma_status;
2607
2608 /* disable the EDMA machinery */
2609 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2610 DELAY(100000); /* SOS should poll for disabled */
2611
2612 /* set configuration to non-queued 128b read transfers stop on error */
2613 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13));
2614
2615 /* request queue base high */
2616 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32);
2617
2618 /* request queue in ptr */
2619 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
2620
2621 /* request queue out ptr */
2622 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0);
2623
2624 /* response queue base high */
2625 work += 1024;
2626 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32);
2627
2628 /* response queue in ptr */
2629 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0);
2630
2631 /* response queue out ptr */
2632 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
2633
2634 /* clear SATA error register */
2635 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2636
2637 /* clear any outstanding error interrupts */
2638 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2639
2640 /* unmask all error interrupts */
2641 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
2642
2643 /* enable EDMA machinery */
2644 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2645 return 0;
2646 }
2647
2648 static int
2649 ata_marvell_edma_status(device_t dev)
2650 {
2651 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2652 struct ata_channel *ch = device_get_softc(dev);
2653 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60);
2654 int shift = (ch->unit << 1) + (ch->unit > 3);
2655
2656 if (cause & (1 << shift)) {
2657
2658 /* clear interrupt(s) */
2659 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2660
2661 /* do we have any PHY events ? */
2662 ata_sata_phy_check_events(dev);
2663 }
2664
2665 /* do we have any device action ? */
2666 return (cause & (2 << shift));
2667 }
2668
2669 /* must be called with ATA channel locked and state_mtx held */
2670 static int
2671 ata_marvell_edma_begin_transaction(struct ata_request *request)
2672 {
2673 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2674 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2675 u_int32_t req_in;
2676 u_int8_t *bytep;
2677 u_int16_t *wordp;
2678 u_int32_t *quadp;
2679 int i, tag = 0x07;
2680 int dummy, error, slot;
2681
2682 /* only DMA R/W goes through the EMDA machine */
2683 if (request->u.ata.command != ATA_READ_DMA &&
2684 request->u.ata.command != ATA_WRITE_DMA) {
2685
2686 /* disable the EDMA machinery */
2687 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)
2688 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2689 return ata_begin_transaction(request);
2690 }
2691
2692 /* check for 48 bit access and convert if needed */
2693 ata_modify_if_48bit(request);
2694
2695 /* check sanity, setup SG list and DMA engine */
2696 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
2697 request->flags & ATA_R_READ, ch->dma->sg,
2698 &dummy))) {
2699 device_printf(request->dev, "setting up DMA failed\n");
2700 request->result = error;
2701 return ATA_OP_FINISHED;
2702 }
2703
2704 /* get next free request queue slot */
2705 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch));
2706 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f;
2707 bytep = (u_int8_t *)(ch->dma->work);
2708 bytep += (slot << 5);
2709 wordp = (u_int16_t *)bytep;
2710 quadp = (u_int32_t *)bytep;
2711
2712 /* fill in this request */
2713 quadp[0] = (long)ch->dma->sg_bus & 0xffffffff;
2714 quadp[1] = (u_int64_t)ch->dma->sg_bus >> 32;
2715 wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1);
2716
2717 i = 10;
2718 bytep[i++] = (request->u.ata.count >> 8) & 0xff;
2719 bytep[i++] = 0x10 | ATA_COUNT;
2720 bytep[i++] = request->u.ata.count & 0xff;
2721 bytep[i++] = 0x10 | ATA_COUNT;
2722
2723 bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
2724 bytep[i++] = 0x10 | ATA_SECTOR;
2725 bytep[i++] = request->u.ata.lba & 0xff;
2726 bytep[i++] = 0x10 | ATA_SECTOR;
2727
2728 bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
2729 bytep[i++] = 0x10 | ATA_CYL_LSB;
2730 bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
2731 bytep[i++] = 0x10 | ATA_CYL_LSB;
2732
2733 bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
2734 bytep[i++] = 0x10 | ATA_CYL_MSB;
2735 bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
2736 bytep[i++] = 0x10 | ATA_CYL_MSB;
2737
2738 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf);
2739 bytep[i++] = 0x10 | ATA_DRIVE;
2740
2741 bytep[i++] = request->u.ata.command;
2742 bytep[i++] = 0x90 | ATA_COMMAND;
2743
2744 /* enable EDMA machinery if needed */
2745 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) {
2746 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2747 while (!(ATA_INL(ctlr->r_res1,
2748 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
2749 DELAY(10);
2750 }
2751
2752 /* tell EDMA it has a new request */
2753 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f;
2754 req_in &= 0xfffffc00;
2755 req_in += (slot << 5);
2756 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in);
2757
2758 return ATA_OP_CONTINUES;
2759 }
2760
2761 /* must be called with ATA channel locked and state_mtx held */
2762 static int
2763 ata_marvell_edma_end_transaction(struct ata_request *request)
2764 {
2765 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2766 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2767 int offset = (ch->unit > 3 ? 0x30014 : 0x20014);
2768 u_int32_t icr = ATA_INL(ctlr->r_res1, offset);
2769 int res;
2770
2771 /* EDMA interrupt */
2772 if ((icr & (0x0001 << (ch->unit & 3)))) {
2773 struct ata_marvell_response *response;
2774 u_int32_t rsp_in, rsp_out;
2775 int slot;
2776
2777 /* stop timeout */
2778 callout_stop(&request->callout);
2779
2780 /* get response ptr's */
2781 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch));
2782 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch));
2783 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f;
2784 rsp_out &= 0xffffff00;
2785 rsp_out += (slot << 3);
2786 response = (struct ata_marvell_response *)
2787 (ch->dma->work + 1024 + (slot << 3));
2788
2789 /* record status for this request */
2790 request->status = response->dev_status;
2791 request->error = 0;
2792
2793 /* ack response */
2794 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out);
2795
2796 /* update progress */
2797 if (!(request->status & ATA_S_ERROR) &&
2798 !(request->flags & ATA_R_TIMEOUT))
2799 request->donecount = request->bytecount;
2800
2801 /* unload SG list */
2802 ch->dma->unload(ch->dev);
2803
2804 res = ATA_OP_FINISHED;
2805 }
2806
2807 /* legacy ATA interrupt */
2808 else {
2809 res = ata_end_transaction(request);
2810 }
2811
2812 /* ack interrupt */
2813 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3))));
2814 return res;
2815 }
2816
2817 static void
2818 ata_marvell_edma_reset(device_t dev)
2819 {
2820 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2821 struct ata_channel *ch = device_get_softc(dev);
2822
2823 /* disable the EDMA machinery */
2824 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2825 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
2826 DELAY(10);
2827
2828 /* clear SATA error register */
2829 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2830
2831 /* clear any outstanding error interrupts */
2832 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2833
2834 /* unmask all error interrupts */
2835 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
2836
2837 /* enable channel and test for devices */
2838 if (ata_sata_phy_reset(dev))
2839 ata_generic_reset(dev);
2840
2841 /* enable EDMA machinery */
2842 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2843 }
2844
2845 static void
2846 ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs,
2847 int error)
2848 {
2849 struct ata_dmasetprd_args *args = xsc;
2850 struct ata_marvell_dma_prdentry *prd = args->dmatab;
2851 int i;
2852
2853 if ((args->error = error))
2854 return;
2855
2856 for (i = 0; i < nsegs; i++) {
2857 prd[i].addrlo = htole32(segs[i].ds_addr);
2858 prd[i].count = htole32(segs[i].ds_len);
2859 prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32);
2860 }
2861 prd[i - 1].count |= htole32(ATA_DMA_EOT);
2862 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
2863 args->nsegs = nsegs;
2864 }
2865
2866 static void
2867 ata_marvell_edma_dmainit(device_t dev)
2868 {
2869 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2870 struct ata_channel *ch = device_get_softc(dev);
2871
2872 ata_dmainit(dev);
2873 if (ch->dma) {
2874 /* note start and stop are not used here */
2875 ch->dma->setprd = ata_marvell_edma_dmasetprd;
2876
2877 /* if 64bit support present adjust max address used */
2878 if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004)
2879 ch->dma->max_address = BUS_SPACE_MAXADDR;
2880
2881 /* chip does not reliably do 64K DMA transfers */
2882 ch->dma->max_iosize = 126 * DEV_BSIZE;
2883 }
2884 }
2885
2886
2887 /*
2888 * National chipset support functions
2889 */
2890 int
2891 ata_national_ident(device_t dev)
2892 {
2893 struct ata_pci_controller *ctlr = device_get_softc(dev);
2894
2895 /* this chip is a clone of the Cyrix chip, bugs and all */
2896 if (pci_get_devid(dev) == ATA_SC1100) {
2897 device_set_desc(dev, "National Geode SC1100 ATA33 controller");
2898 ctlr->chipinit = ata_national_chipinit;
2899 return 0;
2900 }
2901 return ENXIO;
2902 }
2903
2904 static int
2905 ata_national_chipinit(device_t dev)
2906 {
2907 struct ata_pci_controller *ctlr = device_get_softc(dev);
2908
2909 if (ata_setup_interrupt(dev))
2910 return ENXIO;
2911
2912 ctlr->setmode = ata_national_setmode;
2913 return 0;
2914 }
2915
2916 static void
2917 ata_national_setmode(device_t dev, int mode)
2918 {
2919 device_t gparent = GRANDPARENT(dev);
2920 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2921 struct ata_device *atadev = device_get_softc(dev);
2922 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2923 u_int32_t piotiming[] =
2924 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
2925 0x00803020, 0x20102010, 0x00100010,
2926 0x00100010, 0x00100010, 0x00100010 };
2927 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
2928 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
2929 int error;
2930
2931 ch->dma->alignment = 16;
2932 ch->dma->max_iosize = 126 * DEV_BSIZE;
2933
2934 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
2935
2936 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2937
2938 if (bootverbose)
2939 device_printf(dev, "%s setting %s on National chip\n",
2940 (error) ? "failed" : "success", ata_mode2str(mode));
2941 if (!error) {
2942 if (mode >= ATA_UDMA0) {
2943 pci_write_config(gparent, 0x44 + (devno << 3),
2944 udmatiming[mode & ATA_MODE_MASK], 4);
2945 }
2946 else if (mode >= ATA_WDMA0) {
2947 pci_write_config(gparent, 0x44 + (devno << 3),
2948 dmatiming[mode & ATA_MODE_MASK], 4);
2949 }
2950 else {
2951 pci_write_config(gparent, 0x44 + (devno << 3),
2952 pci_read_config(gparent, 0x44 + (devno << 3), 4) |
2953 0x80000000, 4);
2954 }
2955 pci_write_config(gparent, 0x40 + (devno << 3),
2956 piotiming[ata_mode2idx(mode)], 4);
2957 atadev->mode = mode;
2958 }
2959 }
2960
2961
2962 /*
2963 * NetCell chipset support functions
2964 */
2965 int
2966 ata_netcell_ident(device_t dev)
2967 {
2968 struct ata_pci_controller *ctlr = device_get_softc(dev);
2969
2970 if (pci_get_devid(dev) == ATA_NETCELL_SR) {
2971 device_set_desc(dev, "Netcell SyncRAID SR3000/5000 RAID Controller");
2972 ctlr->chipinit = ata_netcell_chipinit;
2973 return 0;
2974 }
2975 return ENXIO;
2976 }
2977
2978 static int
2979 ata_netcell_chipinit(device_t dev)
2980 {
2981 struct ata_pci_controller *ctlr = device_get_softc(dev);
2982
2983 if (ata_generic_chipinit(dev))
2984 return ENXIO;
2985
2986 ctlr->allocate = ata_netcell_allocate;
2987 return 0;
2988 }
2989
2990 static int
2991 ata_netcell_allocate(device_t dev)
2992 {
2993 struct ata_channel *ch = device_get_softc(dev);
2994
2995 /* setup the usual register normal pci style */
2996 if (ata_pci_allocate(dev))
2997 return ENXIO;
2998
2999 /* the NetCell only supports 16 bit PIO transfers */
3000 ch->flags |= ATA_USE_16BIT;
3001
3002 return 0;
3003 }
3004
3005
3006 /*
3007 * nVidia chipset support functions
3008 */
3009 int
3010 ata_nvidia_ident(device_t dev)
3011 {
3012 struct ata_pci_controller *ctlr = device_get_softc(dev);
3013 static struct ata_chip_id ids[] =
3014 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nForce" },
3015 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2" },
3016 { ATA_NFORCE2_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2 Pro" },
3017 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" },
3018 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3" },
3019 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3 Pro" },
3020 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
3021 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
3022 { ATA_NFORCE_MCP04, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP" },
3023 { ATA_NFORCE_MCP04_S1, 0, 0, NV4, ATA_SA150, "nForce MCP" },
3024 { ATA_NFORCE_MCP04_S2, 0, 0, NV4, ATA_SA150, "nForce MCP" },
3025 { ATA_NFORCE_CK804, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce CK804" },
3026 { ATA_NFORCE_CK804_S1, 0, 0, NV4, ATA_SA300, "nForce CK804" },
3027 { ATA_NFORCE_CK804_S2, 0, 0, NV4, ATA_SA300, "nForce CK804" },
3028 { ATA_NFORCE_MCP51, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP51" },
3029 { ATA_NFORCE_MCP51_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
3030 { ATA_NFORCE_MCP51_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
3031 { ATA_NFORCE_MCP55, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP55" },
3032 { ATA_NFORCE_MCP55_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
3033 { ATA_NFORCE_MCP55_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
3034 { ATA_NFORCE_MCP61, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP61" },
3035 { ATA_NFORCE_MCP61_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
3036 { ATA_NFORCE_MCP61_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
3037 { ATA_NFORCE_MCP61_S3, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
3038 { ATA_NFORCE_MCP65, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP65" },
3039 { ATA_NFORCE_MCP67, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP67" },
3040 { ATA_NFORCE_MCP73, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP73" },
3041 { ATA_NFORCE_MCP77, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP77" },
3042 { 0, 0, 0, 0, 0, 0}} ;
3043
3044 if (!(ctlr->chip = ata_match_chip(dev, ids)))
3045 return ENXIO;
3046
3047 ata_set_desc(dev);
3048 ctlr->chipinit = ata_nvidia_chipinit;
3049 return 0;
3050 }
3051
3052 static int
3053 ata_nvidia_chipinit(device_t dev)
3054 {
3055 struct ata_pci_controller *ctlr = device_get_softc(dev);
3056
3057 if (ata_setup_interrupt(dev))
3058 return ENXIO;
3059
3060 if (ctlr->chip->max_dma >= ATA_SA150) {
3061 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1)
3062 ctlr->r_type2 = SYS_RES_IOPORT;
3063 else
3064 ctlr->r_type2 = SYS_RES_MEMORY;
3065 ctlr->r_rid2 = PCIR_BAR(5);
3066 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3067 &ctlr->r_rid2, RF_ACTIVE))) {
3068 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
3069
3070 ctlr->allocate = ata_nvidia_allocate;
3071 ctlr->reset = ata_nvidia_reset;
3072
3073 /* enable control access */
3074 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1);
3075
3076 if (ctlr->chip->cfg2 & NVQ) {
3077 /* clear interrupt status */
3078 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff);
3079
3080 /* enable device and PHY state change interrupts */
3081 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d);
3082
3083 /* disable NCQ support */
3084 ATA_OUTL(ctlr->r_res2, 0x0400,
3085 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9);
3086 }
3087 else {
3088 /* clear interrupt status */
3089 ATA_OUTB(ctlr->r_res2, offset, 0xff);
3090
3091 /* enable device and PHY state change interrupts */
3092 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd);
3093 }
3094
3095 /* enable PCI interrupt */
3096 pci_write_config(dev, PCIR_COMMAND,
3097 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
3098
3099 }
3100 ctlr->setmode = ata_sata_setmode;
3101 }
3102 else {
3103 /* disable prefetch, postwrite */
3104 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
3105 ctlr->setmode = ata_via_family_setmode;
3106 }
3107 return 0;
3108 }
3109
3110 static int
3111 ata_nvidia_allocate(device_t dev)
3112 {
3113 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3114 struct ata_channel *ch = device_get_softc(dev);
3115
3116 /* setup the usual register normal pci style */
3117 if (ata_pci_allocate(dev))
3118 return ENXIO;
3119
3120 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3121 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6);
3122 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3123 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6);
3124 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3125 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6);
3126
3127 ch->hw.status = ata_nvidia_status;
3128 ch->flags |= ATA_NO_SLAVE;
3129
3130 return 0;
3131 }
3132
3133 static int
3134 ata_nvidia_status(device_t dev)
3135 {
3136 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3137 struct ata_channel *ch = device_get_softc(dev);
3138 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
3139 int shift = ch->unit << (ctlr->chip->cfg2 & NVQ ? 4 : 2);
3140 u_int32_t istatus = ATA_INL(ctlr->r_res2, offset);
3141
3142 /* do we have any PHY events ? */
3143 if (istatus & (0x0c << shift))
3144 ata_sata_phy_check_events(dev);
3145
3146 /* clear interrupt(s) */
3147 ATA_OUTB(ctlr->r_res2, offset,
3148 (0x0f << shift) | (ctlr->chip->cfg2 & NVQ ? 0x00f000f0 : 0));
3149
3150 /* do we have any device action ? */
3151 return (istatus & (0x01 << shift));
3152 }
3153
3154 static void
3155 ata_nvidia_reset(device_t dev)
3156 {
3157 if (ata_sata_phy_reset(dev))
3158 ata_generic_reset(dev);
3159 }
3160
3161
3162 /*
3163 * Promise chipset support functions
3164 */
3165 #define ATA_PDC_APKT_OFFSET 0x00000010
3166 #define ATA_PDC_HPKT_OFFSET 0x00000040
3167 #define ATA_PDC_ASG_OFFSET 0x00000080
3168 #define ATA_PDC_LSG_OFFSET 0x000000c0
3169 #define ATA_PDC_HSG_OFFSET 0x00000100
3170 #define ATA_PDC_CHN_OFFSET 0x00000400
3171 #define ATA_PDC_BUF_BASE 0x00400000
3172 #define ATA_PDC_BUF_OFFSET 0x00100000
3173 #define ATA_PDC_MAX_HPKT 8
3174 #define ATA_PDC_WRITE_REG 0x00
3175 #define ATA_PDC_WRITE_CTL 0x0e
3176 #define ATA_PDC_WRITE_END 0x08
3177 #define ATA_PDC_WAIT_NBUSY 0x10
3178 #define ATA_PDC_WAIT_READY 0x18
3179 #define ATA_PDC_1B 0x20
3180 #define ATA_PDC_2B 0x40
3181
3182 struct host_packet {
3183 u_int32_t addr;
3184 TAILQ_ENTRY(host_packet) chain;
3185 };
3186
3187 struct ata_promise_sx4 {
3188 struct mtx mtx;
3189 TAILQ_HEAD(, host_packet) queue;
3190 int busy;
3191 };
3192
3193 int
3194 ata_promise_ident(device_t dev)
3195 {
3196 struct ata_pci_controller *ctlr = device_get_softc(dev);
3197 struct ata_chip_id *idx;
3198 static struct ata_chip_id ids[] =
3199 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "PDC20246" },
3200 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20262" },
3201 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20263" },
3202 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20265" },
3203 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20267" },
3204 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20268" },
3205 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "PDC20269" },
3206 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20270" },
3207 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "PDC20271" },
3208 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "PDC20275" },
3209 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "PDC20276" },
3210 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "PDC20277" },
3211 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "PDC20318" },
3212 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "PDC20319" },
3213 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20371" },
3214 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20375" },
3215 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20376" },
3216 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20377" },
3217 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20378" },
3218 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20379" },
3219 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" },
3220 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" },
3221 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" },
3222 { ATA_PDC20771, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" },
3223 { ATA_PDC40775, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" },
3224 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20617" },
3225 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20618" },
3226 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20619" },
3227 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20620" },
3228 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "PDC20621" },
3229 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "PDC20622" },
3230 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40518" },
3231 { ATA_PDC40519, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40519" },
3232 { ATA_PDC40718, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40718" },
3233 { ATA_PDC40719, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40719" },
3234 { ATA_PDC40779, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40779" },
3235 { 0, 0, 0, 0, 0, 0}};
3236 char buffer[64];
3237 uintptr_t devid = 0;
3238
3239 if (!(idx = ata_match_chip(dev, ids)))
3240 return ENXIO;
3241
3242 /* if we are on a SuperTrak SX6000 dont attach */
3243 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
3244 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
3245 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
3246 devid == ATA_I960RM)
3247 return ENXIO;
3248
3249 strcpy(buffer, "Promise ");
3250 strcat(buffer, idx->text);
3251
3252 /* if we are on a FastTrak TX4, adjust the interrupt resource */
3253 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
3254 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
3255 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
3256 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) {
3257 static long start = 0, end = 0;
3258
3259 if (pci_get_slot(dev) == 1) {
3260 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
3261 strcat(buffer, " (channel 0+1)");
3262 }
3263 else if (pci_get_slot(dev) == 2 && start && end) {
3264 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
3265 strcat(buffer, " (channel 2+3)");
3266 }
3267 else {
3268 start = end = 0;
3269 }
3270 }
3271 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
3272 device_set_desc_copy(dev, buffer);
3273 ctlr->chip = idx;
3274 ctlr->chipinit = ata_promise_chipinit;
3275 return 0;
3276 }
3277
3278 static int
3279 ata_promise_chipinit(device_t dev)
3280 {
3281 struct ata_pci_controller *ctlr = device_get_softc(dev);
3282 int fake_reg, stat_reg;
3283
3284 if (ata_setup_interrupt(dev))
3285 return ENXIO;
3286
3287 switch (ctlr->chip->cfg1) {
3288 case PRNEW:
3289 /* setup clocks */
3290 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a);
3291
3292 ctlr->dmainit = ata_promise_dmainit;
3293 /* FALLTHROUGH */
3294
3295 case PROLD:
3296 /* enable burst mode */
3297 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01);
3298 ctlr->allocate = ata_promise_allocate;
3299 ctlr->setmode = ata_promise_setmode;
3300 return 0;
3301
3302 case PRTX:
3303 ctlr->allocate = ata_promise_tx2_allocate;
3304 ctlr->setmode = ata_promise_setmode;
3305 return 0;
3306
3307 case PRMIO:
3308 ctlr->r_type1 = SYS_RES_MEMORY;
3309 ctlr->r_rid1 = PCIR_BAR(4);
3310 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
3311 &ctlr->r_rid1, RF_ACTIVE)))
3312 goto failnfree;
3313
3314 ctlr->r_type2 = SYS_RES_MEMORY;
3315 ctlr->r_rid2 = PCIR_BAR(3);
3316 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3317 &ctlr->r_rid2, RF_ACTIVE)))
3318 goto failnfree;
3319
3320 if (ctlr->chip->cfg2 == PRSX4X) {
3321 struct ata_promise_sx4 *hpkt;
3322 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080);
3323
3324 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3325 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL,
3326 ata_promise_sx4_intr, ctlr, &ctlr->handle)) {
3327 device_printf(dev, "unable to setup interrupt\n");
3328 goto failnfree;
3329 }
3330
3331 /* print info about cache memory */
3332 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n",
3333 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4,
3334 ((dimm >> 24) & 0xff),
3335 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ?
3336 " ECC enabled" : "" );
3337
3338 /* adjust cache memory parameters */
3339 ATA_OUTL(ctlr->r_res2, 0x000c000c,
3340 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000));
3341
3342 /* setup host packet controls */
3343 hpkt = malloc(sizeof(struct ata_promise_sx4),
3344 M_TEMP, M_NOWAIT | M_ZERO);
3345 mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF);
3346 TAILQ_INIT(&hpkt->queue);
3347 hpkt->busy = 0;
3348 device_set_ivars(dev, hpkt);
3349 ctlr->allocate = ata_promise_mio_allocate;
3350 ctlr->reset = ata_promise_mio_reset;
3351 ctlr->dmainit = ata_promise_mio_dmainit;
3352 ctlr->setmode = ata_promise_setmode;
3353 ctlr->channels = 4;
3354 return 0;
3355 }
3356
3357 /* mio type controllers need an interrupt intercept */
3358 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3359 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL,
3360 ata_promise_mio_intr, ctlr, &ctlr->handle)) {
3361 device_printf(dev, "unable to setup interrupt\n");
3362 goto failnfree;
3363 }
3364
3365 switch (ctlr->chip->cfg2) {
3366 case PRPATA:
3367 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) +
3368 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2;
3369 goto sata150;
3370 case PRCMBO:
3371 ctlr->channels = 3;
3372 goto sata150;
3373 case PRSATA:
3374 ctlr->channels = 4;
3375 sata150:
3376 fake_reg = 0x60;
3377 stat_reg = 0x6c;
3378 break;
3379
3380 case PRCMBO2:
3381 ctlr->channels = 3;
3382 goto sataii;
3383 case PRSATA2:
3384 default:
3385 ctlr->channels = 4;
3386 sataii:
3387 fake_reg = 0x54;
3388 stat_reg = 0x60;
3389 break;
3390 }
3391
3392 /* prime fake interrupt register */
3393 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3394
3395 /* clear SATA status and unmask interrupts */
3396 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff);
3397
3398 /* enable "long burst lenght" on gen2 chips */
3399 if ((ctlr->chip->cfg2 == PRSATA2) || (ctlr->chip->cfg2 == PRCMBO2))
3400 ATA_OUTL(ctlr->r_res2, 0x44, ATA_INL(ctlr->r_res2, 0x44) | 0x2000);
3401
3402 ctlr->allocate = ata_promise_mio_allocate;
3403 ctlr->reset = ata_promise_mio_reset;
3404 ctlr->dmainit = ata_promise_mio_dmainit;
3405 ctlr->setmode = ata_promise_mio_setmode;
3406
3407 return 0;
3408 }
3409
3410 failnfree:
3411 if (ctlr->r_res2)
3412 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
3413 if (ctlr->r_res1)
3414 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1);
3415 return ENXIO;
3416 }
3417
3418 static int
3419 ata_promise_allocate(device_t dev)
3420 {
3421 struct ata_channel *ch = device_get_softc(dev);
3422
3423 if (ata_pci_allocate(dev))
3424 return ENXIO;
3425
3426 ch->hw.status = ata_promise_status;
3427 return 0;
3428 }
3429
3430 static int
3431 ata_promise_status(device_t dev)
3432 {
3433 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3434 struct ata_channel *ch = device_get_softc(dev);
3435
3436 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) {
3437 return ata_pci_status(dev);
3438 }
3439 return 0;
3440 }
3441
3442 static int
3443 ata_promise_dmastart(device_t dev)
3444 {
3445 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3446 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3447 struct ata_device *atadev = device_get_softc(dev);
3448
3449 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3450 ATA_OUTB(ctlr->r_res1, 0x11,
3451 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02));
3452 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20,
3453 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) |
3454 (ch->dma->cur_iosize >> 1));
3455 }
3456 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) |
3457 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
3458 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus);
3459 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3460 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) |
3461 ATA_BMCMD_START_STOP);
3462 ch->flags |= ATA_DMA_ACTIVE;
3463 return 0;
3464 }
3465
3466 static int
3467 ata_promise_dmastop(device_t dev)
3468 {
3469 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3470 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3471 struct ata_device *atadev = device_get_softc(dev);
3472 int error;
3473
3474 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3475 ATA_OUTB(ctlr->r_res1, 0x11,
3476 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02));
3477 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0);
3478 }
3479 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT);
3480 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3481 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3482 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3483 ch->flags &= ~ATA_DMA_ACTIVE;
3484 return error;
3485 }
3486
3487 static void
3488 ata_promise_dmareset(device_t dev)
3489 {
3490 struct ata_channel *ch = device_get_softc(dev);
3491
3492 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3493 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3494 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3495 ch->flags &= ~ATA_DMA_ACTIVE;
3496 }
3497
3498 static void
3499 ata_promise_dmainit(device_t dev)
3500 {
3501 struct ata_channel *ch = device_get_softc(dev);
3502
3503 ata_dmainit(dev);
3504 if (ch->dma) {
3505 ch->dma->start = ata_promise_dmastart;
3506 ch->dma->stop = ata_promise_dmastop;
3507 ch->dma->reset = ata_promise_dmareset;
3508 }
3509 }
3510
3511 static void
3512 ata_promise_setmode(device_t dev, int mode)
3513 {
3514 device_t gparent = GRANDPARENT(dev);
3515 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3516 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3517 struct ata_device *atadev = device_get_softc(dev);
3518 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
3519 int error;
3520 u_int32_t timings[][2] = {
3521 /* PROLD PRNEW mode */
3522 { 0x004ff329, 0x004fff2f }, /* PIO 0 */
3523 { 0x004fec25, 0x004ff82a }, /* PIO 1 */
3524 { 0x004fe823, 0x004ff026 }, /* PIO 2 */
3525 { 0x004fe622, 0x004fec24 }, /* PIO 3 */
3526 { 0x004fe421, 0x004fe822 }, /* PIO 4 */
3527 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */
3528 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */
3529 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */
3530 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */
3531 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */
3532 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */
3533 { 0, 0x00424ef6 }, /* UDMA 3 */
3534 { 0, 0x004127f3 }, /* UDMA 4 */
3535 { 0, 0x004127f3 } /* UDMA 5 */
3536 };
3537
3538 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
3539
3540 switch (ctlr->chip->cfg1) {
3541 case PROLD:
3542 case PRNEW:
3543 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) &
3544 (ch->unit ? 1 << 11 : 1 << 10))) {
3545 ata_print_cable(dev, "controller");
3546 mode = ATA_UDMA2;
3547 }
3548 if (ata_atapi(dev) && mode > ATA_PIO_MAX)
3549 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
3550 break;
3551
3552 case PRTX:
3553 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3554 if (mode > ATA_UDMA2 &&
3555 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) {
3556 ata_print_cable(dev, "controller");
3557 mode = ATA_UDMA2;
3558 }
3559 break;
3560
3561 case PRMIO:
3562 if (mode > ATA_UDMA2 &&
3563 (ATA_INL(ctlr->r_res2,
3564 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) +
3565 (ch->unit << 7)) & 0x01000000)) {
3566 ata_print_cable(dev, "controller");
3567 mode = ATA_UDMA2;
3568 }
3569 break;
3570 }
3571
3572 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3573
3574 if (bootverbose)
3575 device_printf(dev, "%ssetting %s on %s chip\n",
3576 (error) ? "FAILURE " : "",
3577 ata_mode2str(mode), ctlr->chip->text);
3578 if (!error) {
3579 if (ctlr->chip->cfg1 < PRTX)
3580 pci_write_config(gparent, 0x60 + (devno << 2),
3581 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
3582 atadev->mode = mode;
3583 }
3584 return;
3585 }
3586
3587 static int
3588 ata_promise_tx2_allocate(device_t dev)
3589 {
3590 struct ata_channel *ch = device_get_softc(dev);
3591
3592 if (ata_pci_allocate(dev))
3593 return ENXIO;
3594
3595 ch->hw.status = ata_promise_tx2_status;
3596 return 0;
3597 }
3598
3599 static int
3600 ata_promise_tx2_status(device_t dev)
3601 {
3602 struct ata_channel *ch = device_get_softc(dev);
3603
3604 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3605 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
3606 return ata_pci_status(dev);
3607 }
3608 return 0;
3609 }
3610
3611 static int
3612 ata_promise_mio_allocate(device_t dev)
3613 {
3614 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3615 struct ata_channel *ch = device_get_softc(dev);
3616 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0;
3617 int i;
3618
3619 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
3620 ch->r_io[i].res = ctlr->r_res2;
3621 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7);
3622 }
3623 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
3624 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7);
3625 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
3626 ata_default_registers(dev);
3627 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) ||
3628 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2)) {
3629 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3630 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8);
3631 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3632 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8);
3633 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3634 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8);
3635 ch->flags |= ATA_NO_SLAVE;
3636 }
3637 ch->flags |= ATA_USE_16BIT;
3638
3639 ata_generic_hw(dev);
3640 if (ctlr->chip->cfg2 & PRSX4X) {
3641 ch->hw.command = ata_promise_sx4_command;
3642 }
3643 else {
3644 ch->hw.command = ata_promise_mio_command;
3645 ch->hw.status = ata_promise_mio_status;
3646 }
3647 return 0;
3648 }
3649
3650 static void
3651 ata_promise_mio_intr(void *data)
3652 {
3653 struct ata_pci_controller *ctlr = data;
3654 struct ata_channel *ch;
3655 u_int32_t vector;
3656 int unit, fake_reg;
3657
3658 switch (ctlr->chip->cfg2) {
3659 case PRPATA:
3660 case PRCMBO:
3661 case PRSATA:
3662 fake_reg = 0x60;
3663 break;
3664 case PRCMBO2:
3665 case PRSATA2:
3666 default:
3667 fake_reg = 0x54;
3668 break;
3669 }
3670
3671 /*
3672 * since reading interrupt status register on early "mio" chips
3673 * clears the status bits we cannot read it for each channel later on
3674 * in the generic interrupt routine.
3675 * store the bits in an unused register in the chip so we can read
3676 * it from there safely to get around this "feature".
3677 */
3678 vector = ATA_INL(ctlr->r_res2, 0x040);
3679 ATA_OUTL(ctlr->r_res2, 0x040, vector);
3680 ATA_OUTL(ctlr->r_res2, fake_reg, vector);
3681
3682 for (unit = 0; unit < ctlr->channels; unit++) {
3683 if ((ch = ctlr->interrupt[unit].argument))
3684 ctlr->interrupt[unit].function(ch);
3685 }
3686
3687 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3688 }
3689
3690 static int
3691 ata_promise_mio_status(device_t dev)
3692 {
3693 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3694 struct ata_channel *ch = device_get_softc(dev);
3695 struct ata_connect_task *tp;
3696 u_int32_t fake_reg, stat_reg, vector, status;
3697
3698 switch (ctlr->chip->cfg2) {
3699 case PRPATA:
3700 case PRCMBO:
3701 case PRSATA:
3702 fake_reg = 0x60;
3703 stat_reg = 0x6c;
3704 break;
3705 case PRCMBO2:
3706 case PRSATA2:
3707 default:
3708 fake_reg = 0x54;
3709 stat_reg = 0x60;
3710 break;
3711 }
3712
3713 /* read and acknowledge interrupt */
3714 vector = ATA_INL(ctlr->r_res2, fake_reg);
3715
3716 /* read and clear interface status */
3717 status = ATA_INL(ctlr->r_res2, stat_reg);
3718 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit));
3719
3720 /* check for and handle disconnect events */
3721 if ((status & (0x00000001 << ch->unit)) &&
3722 (tp = (struct ata_connect_task *)
3723 malloc(sizeof(struct ata_connect_task),
3724 M_ATA, M_NOWAIT | M_ZERO))) {
3725
3726 if (bootverbose)
3727 device_printf(ch->dev, "DISCONNECT requested\n");
3728 tp->action = ATA_C_DETACH;
3729 tp->dev = ch->dev;
3730 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3731 taskqueue_enqueue(taskqueue_thread, &tp->task);
3732 }
3733
3734 /* check for and handle connect events */
3735 if ((status & (0x00000010 << ch->unit)) &&
3736 (tp = (struct ata_connect_task *)
3737 malloc(sizeof(struct ata_connect_task),
3738 M_ATA, M_NOWAIT | M_ZERO))) {
3739
3740 if (bootverbose)
3741 device_printf(ch->dev, "CONNECT requested\n");
3742 tp->action = ATA_C_ATTACH;
3743 tp->dev = ch->dev;
3744 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3745 taskqueue_enqueue(taskqueue_thread, &tp->task);
3746 }
3747
3748 /* do we have any device action ? */
3749 return (vector & (1 << (ch->unit + 1)));
3750 }
3751
3752 static int
3753 ata_promise_mio_command(struct ata_request *request)
3754 {
3755 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
3756 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
3757 u_int32_t *wordp = (u_int32_t *)ch->dma->work;
3758
3759 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001);
3760
3761 /* XXX SOS add ATAPI commands support later */
3762 switch (request->u.ata.command) {
3763 default:
3764 return ata_generic_command(request);
3765
3766 case ATA_READ_DMA:
3767 case ATA_READ_DMA48:
3768 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24));
3769 break;
3770
3771 case ATA_WRITE_DMA:
3772 case ATA_WRITE_DMA48:
3773 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24));
3774 break;
3775 }
3776 wordp[1] = htole32(ch->dma->sg_bus);
3777 wordp[2] = 0;
3778 ata_promise_apkt((u_int8_t*)wordp, request);
3779
3780 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma->work_bus);
3781 return 0;
3782 }
3783
3784 static void
3785 ata_promise_mio_reset(device_t dev)
3786 {
3787 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3788 struct ata_channel *ch = device_get_softc(dev);
3789 struct ata_promise_sx4 *hpktp;
3790
3791 switch (ctlr->chip->cfg2) {
3792 case PRSX4X:
3793
3794 /* softreset channel ATA module */
3795 hpktp = device_get_ivars(ctlr->dev);
3796 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1);
3797 ata_udelay(1000);
3798 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7),
3799 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) &
3800 ~0x00003f9f) | (ch->unit + 1));
3801
3802 /* softreset HOST module */ /* XXX SOS what about other outstandings */
3803 mtx_lock(&hpktp->mtx);
3804 ATA_OUTL(ctlr->r_res2, 0xc012c,
3805 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11));
3806 DELAY(10);
3807 ATA_OUTL(ctlr->r_res2, 0xc012c,
3808 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f));
3809 hpktp->busy = 0;
3810 mtx_unlock(&hpktp->mtx);
3811 ata_generic_reset(dev);
3812 break;
3813
3814 case PRPATA:
3815 case PRCMBO:
3816 case PRSATA:
3817 if ((ctlr->chip->cfg2 == PRSATA) ||
3818 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
3819
3820 /* mask plug/unplug intr */
3821 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit));
3822 }
3823
3824 /* softreset channels ATA module */
3825 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
3826 ata_udelay(10000);
3827 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
3828 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
3829 ~0x00003f9f) | (ch->unit + 1));
3830
3831 if ((ctlr->chip->cfg2 == PRSATA) ||
3832 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
3833
3834 if (ata_sata_phy_reset(dev))
3835 ata_generic_reset(dev);
3836
3837 /* reset and enable plug/unplug intr */
3838 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit));
3839 }
3840 else
3841 ata_generic_reset(dev);
3842 break;
3843
3844 case PRCMBO2:
3845 case PRSATA2:
3846 if ((ctlr->chip->cfg2 == PRSATA2) ||
3847 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
3848 /* set portmultiplier port */
3849 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f);
3850
3851 /* mask plug/unplug intr */
3852 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit));
3853 }
3854
3855 /* softreset channels ATA module */
3856 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
3857 ata_udelay(10000);
3858 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
3859 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
3860 ~0x00003f9f) | (ch->unit + 1));
3861
3862 if ((ctlr->chip->cfg2 == PRSATA2) ||
3863 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
3864
3865 /* set PHY mode to "improved" */
3866 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8),
3867 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) &
3868 ~0x00000003) | 0x00000001);
3869
3870 if (ata_sata_phy_reset(dev))
3871 ata_generic_reset(dev);
3872
3873 /* reset and enable plug/unplug intr */
3874 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit));
3875
3876 /* set portmultiplier port */
3877 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00);
3878 }
3879 else
3880 ata_generic_reset(dev);
3881 break;
3882
3883 }
3884 }
3885
3886 static void
3887 ata_promise_mio_dmainit(device_t dev)
3888 {
3889 struct ata_channel *ch = device_get_softc(dev);
3890
3891 /* note start and stop are not used here */
3892 ata_dmainit(dev);
3893 if (ch->dma)
3894 ch->dma->setprd = ata_promise_mio_setprd;
3895 }
3896
3897
3898 #define MAXLASTSGSIZE (32 * sizeof(u_int32_t))
3899 static void
3900 ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
3901 {
3902 struct ata_dmasetprd_args *args = xsc;
3903 struct ata_dma_prdentry *prd = args->dmatab;
3904 int i;
3905
3906 if ((args->error = error))
3907 return;
3908
3909 for (i = 0; i < nsegs; i++) {
3910 prd[i].addr = htole32(segs[i].ds_addr);
3911 prd[i].count = htole32(segs[i].ds_len);
3912 }
3913 if (segs[i - 1].ds_len > MAXLASTSGSIZE) {
3914 //printf("split last SG element of %u\n", segs[i - 1].ds_len);
3915 prd[i - 1].count = htole32(segs[i - 1].ds_len - MAXLASTSGSIZE);
3916 prd[i].count = htole32(MAXLASTSGSIZE);
3917 prd[i].addr = htole32(segs[i - 1].ds_addr +
3918 (segs[i - 1].ds_len - MAXLASTSGSIZE));
3919 nsegs++;
3920 i++;
3921 }
3922 prd[i - 1].count |= htole32(ATA_DMA_EOT);
3923 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
3924 args->nsegs = nsegs;
3925 }
3926
3927 static void
3928 ata_promise_mio_setmode(device_t dev, int mode)
3929 {
3930 device_t gparent = GRANDPARENT(dev);
3931 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3932 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3933
3934 if ( (ctlr->chip->cfg2 == PRSATA) ||
3935 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2)) ||
3936 (ctlr->chip->cfg2 == PRSATA2) ||
3937 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2)))
3938 ata_sata_setmode(dev, mode);
3939 else
3940 ata_promise_setmode(dev, mode);
3941 }
3942
3943 static void
3944 ata_promise_sx4_intr(void *data)
3945 {
3946 struct ata_pci_controller *ctlr = data;
3947 struct ata_channel *ch;
3948 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480);
3949 int unit;
3950
3951 for (unit = 0; unit < ctlr->channels; unit++) {
3952 if (vector & (1 << (unit + 1)))
3953 if ((ch = ctlr->interrupt[unit].argument))
3954 ctlr->interrupt[unit].function(ch);
3955 if (vector & (1 << (unit + 5)))
3956 if ((ch = ctlr->interrupt[unit].argument))
3957 ata_promise_queue_hpkt(ctlr,
3958 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
3959 ATA_PDC_HPKT_OFFSET));
3960 if (vector & (1 << (unit + 9))) {
3961 ata_promise_next_hpkt(ctlr);
3962 if ((ch = ctlr->interrupt[unit].argument))
3963 ctlr->interrupt[unit].function(ch);
3964 }
3965 if (vector & (1 << (unit + 13))) {
3966 ata_promise_next_hpkt(ctlr);
3967 if ((ch = ctlr->interrupt[unit].argument))
3968 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
3969 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
3970 ATA_PDC_APKT_OFFSET));
3971 }
3972 }
3973 }
3974
3975 static int
3976 ata_promise_sx4_command(struct ata_request *request)
3977 {
3978 device_t gparent = GRANDPARENT(request->dev);
3979 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3980 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
3981 struct ata_dma_prdentry *prd = ch->dma->sg;
3982 caddr_t window = rman_get_virtual(ctlr->r_res1);
3983 u_int32_t *wordp;
3984 int i, idx, length = 0;
3985
3986 /* XXX SOS add ATAPI commands support later */
3987 switch (request->u.ata.command) {
3988
3989 default:
3990 return -1;
3991
3992 case ATA_ATA_IDENTIFY:
3993 case ATA_READ:
3994 case ATA_READ48:
3995 case ATA_READ_MUL:
3996 case ATA_READ_MUL48:
3997 case ATA_WRITE:
3998 case ATA_WRITE48:
3999 case ATA_WRITE_MUL:
4000 case ATA_WRITE_MUL48:
4001 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
4002 return ata_generic_command(request);
4003
4004 case ATA_SETFEATURES:
4005 case ATA_FLUSHCACHE:
4006 case ATA_FLUSHCACHE48:
4007 case ATA_SLEEP:
4008 case ATA_SET_MULTI:
4009 wordp = (u_int32_t *)
4010 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
4011 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24));
4012 wordp[1] = 0;
4013 wordp[2] = 0;
4014 ata_promise_apkt((u_int8_t *)wordp, request);
4015 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
4016 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
4017 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4018 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET));
4019 return 0;
4020
4021 case ATA_READ_DMA:
4022 case ATA_READ_DMA48:
4023 case ATA_WRITE_DMA:
4024 case ATA_WRITE_DMA48:
4025 wordp = (u_int32_t *)
4026 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET);
4027 i = idx = 0;
4028 do {
4029 wordp[idx++] = prd[i].addr;
4030 wordp[idx++] = prd[i].count;
4031 length += (prd[i].count & ~ATA_DMA_EOT);
4032 } while (!(prd[i++].count & ATA_DMA_EOT));
4033
4034 wordp = (u_int32_t *)
4035 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET);
4036 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
4037 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
4038
4039 wordp = (u_int32_t *)
4040 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET);
4041 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
4042 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
4043
4044 wordp = (u_int32_t *)
4045 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET);
4046 if (request->flags & ATA_R_READ)
4047 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24));
4048 if (request->flags & ATA_R_WRITE)
4049 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24));
4050 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET);
4051 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET);
4052 wordp[3] = 0;
4053
4054 wordp = (u_int32_t *)
4055 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
4056 if (request->flags & ATA_R_READ)
4057 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24));
4058 if (request->flags & ATA_R_WRITE)
4059 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24));
4060 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET);
4061 wordp[2] = 0;
4062 ata_promise_apkt((u_int8_t *)wordp, request);
4063 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
4064
4065 if (request->flags & ATA_R_READ) {
4066 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001);
4067 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001);
4068 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4069 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET));
4070 }
4071 if (request->flags & ATA_R_WRITE) {
4072 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001);
4073 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001);
4074 ata_promise_queue_hpkt(ctlr,
4075 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET));
4076 }
4077 return 0;
4078 }
4079 }
4080
4081 static int
4082 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request)
4083 {
4084 struct ata_device *atadev = device_get_softc(request->dev);
4085 int i = 12;
4086
4087 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE;
4088 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit;
4089 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL;
4090 bytep[i++] = ATA_A_4BIT;
4091
4092 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
4093 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE;
4094 bytep[i++] = request->u.ata.feature >> 8;
4095 bytep[i++] = request->u.ata.feature;
4096 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT;
4097 bytep[i++] = request->u.ata.count >> 8;
4098 bytep[i++] = request->u.ata.count;
4099 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR;
4100 bytep[i++] = request->u.ata.lba >> 24;
4101 bytep[i++] = request->u.ata.lba;
4102 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
4103 bytep[i++] = request->u.ata.lba >> 32;
4104 bytep[i++] = request->u.ata.lba >> 8;
4105 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
4106 bytep[i++] = request->u.ata.lba >> 40;
4107 bytep[i++] = request->u.ata.lba >> 16;
4108 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
4109 bytep[i++] = ATA_D_LBA | atadev->unit;
4110 }
4111 else {
4112 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE;
4113 bytep[i++] = request->u.ata.feature;
4114 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT;
4115 bytep[i++] = request->u.ata.count;
4116 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR;
4117 bytep[i++] = request->u.ata.lba;
4118 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
4119 bytep[i++] = request->u.ata.lba >> 8;
4120 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
4121 bytep[i++] = request->u.ata.lba >> 16;
4122 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
4123 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) |
4124 ATA_D_IBM | atadev->unit | ((request->u.ata.lba >> 24)&0xf);
4125 }
4126 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND;
4127 bytep[i++] = request->u.ata.command;
4128 return i;
4129 }
4130
4131 static void
4132 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt)
4133 {
4134 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
4135
4136 mtx_lock(&hpktp->mtx);
4137 if (hpktp->busy) {
4138 struct host_packet *hp =
4139 malloc(sizeof(struct host_packet), M_TEMP, M_NOWAIT | M_ZERO);
4140 hp->addr = hpkt;
4141 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain);
4142 }
4143 else {
4144 hpktp->busy = 1;
4145 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt);
4146 }
4147 mtx_unlock(&hpktp->mtx);
4148 }
4149
4150 static void
4151 ata_promise_next_hpkt(struct ata_pci_controller *ctlr)
4152 {
4153 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
4154 struct host_packet *hp;
4155
4156 mtx_lock(&hpktp->mtx);
4157 if ((hp = TAILQ_FIRST(&hpktp->queue))) {
4158 TAILQ_REMOVE(&hpktp->queue, hp, chain);
4159 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr);
4160 free(hp, M_TEMP);
4161 }
4162 else
4163 hpktp->busy = 0;
4164 mtx_unlock(&hpktp->mtx);
4165 }
4166
4167
4168 /*
4169 * ServerWorks chipset support functions
4170 */
4171 int
4172 ata_serverworks_ident(device_t dev)
4173 {
4174 struct ata_pci_controller *ctlr = device_get_softc(dev);
4175 static struct ata_chip_id ids[] =
4176 {{ ATA_ROSB4, 0x00, SWKS33, 0, ATA_UDMA2, "ROSB4" },
4177 { ATA_CSB5, 0x92, SWKS100, 0, ATA_UDMA5, "CSB5" },
4178 { ATA_CSB5, 0x00, SWKS66, 0, ATA_UDMA4, "CSB5" },
4179 { ATA_CSB6, 0x00, SWKS100, 0, ATA_UDMA5, "CSB6" },
4180 { ATA_CSB6_1, 0x00, SWKS66, 0, ATA_UDMA4, "CSB6" },
4181 { ATA_HT1000, 0x00, SWKS100, 0, ATA_UDMA5, "HT1000" },
4182 { ATA_HT1000_S1, 0x00, SWKS100, 4, ATA_SA150, "HT1000" },
4183 { ATA_HT1000_S2, 0x00, SWKSMIO, 4, ATA_SA150, "HT1000" },
4184 { ATA_K2, 0x00, SWKSMIO, 4, ATA_SA150, "K2" },
4185 { ATA_FRODO4, 0x00, SWKSMIO, 4, ATA_SA150, "Frodo4" },
4186 { ATA_FRODO8, 0x00, SWKSMIO, 8, ATA_SA150, "Frodo8" },
4187 { 0, 0, 0, 0, 0, 0}};
4188
4189 if (!(ctlr->chip = ata_match_chip(dev, ids)))
4190 return ENXIO;
4191
4192 ata_set_desc(dev);
4193 ctlr->chipinit = ata_serverworks_chipinit;
4194 return 0;
4195 }
4196
4197 static int
4198 ata_serverworks_chipinit(device_t dev)
4199 {
4200 struct ata_pci_controller *ctlr = device_get_softc(dev);
4201
4202 if (ata_setup_interrupt(dev))
4203 return ENXIO;
4204
4205 if (ctlr->chip->cfg1 == SWKSMIO) {
4206 ctlr->r_type2 = SYS_RES_MEMORY;
4207 ctlr->r_rid2 = PCIR_BAR(5);
4208 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4209 &ctlr->r_rid2, RF_ACTIVE)))
4210 return ENXIO;
4211
4212 ctlr->channels = ctlr->chip->cfg2;
4213 ctlr->allocate = ata_serverworks_allocate;
4214 ctlr->setmode = ata_sata_setmode;
4215 return 0;
4216 }
4217 else if (ctlr->chip->cfg1 == SWKS33) {
4218 device_t *children;
4219 int nchildren, i;
4220
4221 /* locate the ISA part in the southbridge and enable UDMA33 */
4222 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
4223 for (i = 0; i < nchildren; i++) {
4224 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
4225 pci_write_config(children[i], 0x64,
4226 (pci_read_config(children[i], 0x64, 4) &
4227 ~0x00002000) | 0x00004000, 4);
4228 break;
4229 }
4230 }
4231 free(children, M_TEMP);
4232 }
4233 }
4234 else {
4235 pci_write_config(dev, 0x5a,
4236 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
4237 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1);
4238 }
4239 ctlr->setmode = ata_serverworks_setmode;
4240 return 0;
4241 }
4242
4243 static int
4244 ata_serverworks_allocate(device_t dev)
4245 {
4246 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4247 struct ata_channel *ch = device_get_softc(dev);
4248 int ch_offset;
4249 int i;
4250
4251 ch_offset = ch->unit * 0x100;
4252
4253 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
4254 ch->r_io[i].res = ctlr->r_res2;
4255
4256 /* setup ATA registers */
4257 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
4258 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04;
4259 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
4260 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
4261 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
4262 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
4263 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
4264 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c;
4265 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20;
4266 ata_default_registers(dev);
4267
4268 /* setup DMA registers */
4269 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30;
4270 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32;
4271 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34;
4272
4273 /* setup SATA registers */
4274 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40;
4275 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44;
4276 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48;
4277
4278 ch->flags |= ATA_NO_SLAVE;
4279 ata_pci_hw(dev);
4280 ch->hw.tf_read = ata_serverworks_tf_read;
4281 ch->hw.tf_write = ata_serverworks_tf_write;
4282
4283 /* chip does not reliably do 64K DMA transfers */
4284 if (ch->dma)
4285 ch->dma->max_iosize = 126 * DEV_BSIZE;
4286
4287 return 0;
4288 }
4289
4290 static void
4291 ata_serverworks_tf_read(struct ata_request *request)
4292 {
4293 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4294 struct ata_device *atadev = device_get_softc(request->dev);
4295
4296 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
4297 u_int16_t temp;
4298
4299 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT);
4300 temp = ATA_IDX_INW(ch, ATA_SECTOR);
4301 request->u.ata.lba = (u_int64_t)(temp & 0x00ff) |
4302 ((u_int64_t)(temp & 0xff00) << 24);
4303 temp = ATA_IDX_INW(ch, ATA_CYL_LSB);
4304 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 8) |
4305 ((u_int64_t)(temp & 0xff00) << 32);
4306 temp = ATA_IDX_INW(ch, ATA_CYL_MSB);
4307 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 16) |
4308 ((u_int64_t)(temp & 0xff00) << 40);
4309 }
4310 else {
4311 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT) & 0x00ff;
4312 request->u.ata.lba = (ATA_IDX_INW(ch, ATA_SECTOR) & 0x00ff) |
4313 ((ATA_IDX_INW(ch, ATA_CYL_LSB) & 0x00ff) << 8) |
4314 ((ATA_IDX_INW(ch, ATA_CYL_MSB) & 0x00ff) << 16) |
4315 ((ATA_IDX_INW(ch, ATA_DRIVE) & 0xf) << 24);
4316 }
4317 }
4318
4319 static void
4320 ata_serverworks_tf_write(struct ata_request *request)
4321 {
4322 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4323 struct ata_device *atadev = device_get_softc(request->dev);
4324
4325 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
4326 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
4327 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
4328 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) |
4329 (request->u.ata.lba & 0x00ff));
4330 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) |
4331 ((request->u.ata.lba >> 8) & 0x00ff));
4332 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) |
4333 ((request->u.ata.lba >> 16) & 0x00ff));
4334 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | atadev->unit);
4335 }
4336 else {
4337 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
4338 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
4339 if (atadev->flags & ATA_D_USE_CHS) {
4340 int heads, sectors;
4341
4342 if (atadev->param.atavalid & ATA_FLAG_54_58) {
4343 heads = atadev->param.current_heads;
4344 sectors = atadev->param.current_sectors;
4345 }
4346 else {
4347 heads = atadev->param.heads;
4348 sectors = atadev->param.sectors;
4349 }
4350 ATA_IDX_OUTW(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
4351 ATA_IDX_OUTW(ch, ATA_CYL_LSB,
4352 (request->u.ata.lba / (sectors * heads)));
4353 ATA_IDX_OUTW(ch, ATA_CYL_MSB,
4354 (request->u.ata.lba / (sectors * heads)) >> 8);
4355 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit |
4356 (((request->u.ata.lba% (sectors * heads)) /
4357 sectors) & 0xf));
4358 }
4359 else {
4360 ATA_IDX_OUTW(ch, ATA_SECTOR, request->u.ata.lba);
4361 ATA_IDX_OUTW(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
4362 ATA_IDX_OUTW(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
4363 ATA_IDX_OUTW(ch, ATA_DRIVE,
4364 ATA_D_IBM | ATA_D_LBA | atadev->unit |
4365 ((request->u.ata.lba >> 24) & 0x0f));
4366 }
4367 }
4368 }
4369
4370 static void
4371 ata_serverworks_setmode(device_t dev, int mode)
4372 {
4373 device_t gparent = GRANDPARENT(dev);
4374 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4375 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4376 struct ata_device *atadev = device_get_softc(dev);
4377 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4378 int offset = (devno ^ 0x01) << 3;
4379 int error;
4380 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
4381 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
4382 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
4383
4384 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4385
4386 mode = ata_check_80pin(dev, mode);
4387
4388 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4389
4390 if (bootverbose)
4391 device_printf(dev, "%ssetting %s on %s chip\n",
4392 (error) ? "FAILURE " : "",
4393 ata_mode2str(mode), ctlr->chip->text);
4394 if (!error) {
4395 if (mode >= ATA_UDMA0) {
4396 pci_write_config(gparent, 0x56,
4397 (pci_read_config(gparent, 0x56, 2) &
4398 ~(0xf << (devno << 2))) |
4399 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
4400 pci_write_config(gparent, 0x54,
4401 pci_read_config(gparent, 0x54, 1) |
4402 (0x01 << devno), 1);
4403 pci_write_config(gparent, 0x44,
4404 (pci_read_config(gparent, 0x44, 4) &
4405 ~(0xff << offset)) |
4406 (dmatimings[2] << offset), 4);
4407 }
4408 else if (mode >= ATA_WDMA0) {
4409 pci_write_config(gparent, 0x54,
4410 pci_read_config(gparent, 0x54, 1) &
4411 ~(0x01 << devno), 1);
4412 pci_write_config(gparent, 0x44,
4413 (pci_read_config(gparent, 0x44, 4) &
4414 ~(0xff << offset)) |
4415 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
4416 }
4417 else
4418 pci_write_config(gparent, 0x54,
4419 pci_read_config(gparent, 0x54, 1) &
4420 ~(0x01 << devno), 1);
4421
4422 pci_write_config(gparent, 0x40,
4423 (pci_read_config(gparent, 0x40, 4) &
4424 ~(0xff << offset)) |
4425 (piotimings[ata_mode2idx(mode)] << offset), 4);
4426 atadev->mode = mode;
4427 }
4428 }
4429
4430
4431 /*
4432 * Silicon Image Inc. (SiI) (former CMD) chipset support functions
4433 */
4434 int
4435 ata_sii_ident(device_t dev)
4436 {
4437 struct ata_pci_controller *ctlr = device_get_softc(dev);
4438 static struct ata_chip_id ids[] =
4439 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" },
4440 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" },
4441 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
4442 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
4443 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" },
4444 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
4445 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
4446 { ATA_SII3124, 0x00, SIIPRBIO, SII4CH, ATA_SA300, "SiI 3124" },
4447 { ATA_SII3132, 0x00, SIIPRBIO, 0, ATA_SA300, "SiI 3132" },
4448 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" },
4449 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" },
4450 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" },
4451 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" },
4452 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" },
4453 { 0, 0, 0, 0, 0, 0}};
4454
4455 if (!(ctlr->chip = ata_match_chip(dev, ids)))
4456 return ENXIO;
4457
4458 ata_set_desc(dev);
4459 ctlr->chipinit = ata_sii_chipinit;
4460 return 0;
4461 }
4462
4463 static int
4464 ata_sii_chipinit(device_t dev)
4465 {
4466 struct ata_pci_controller *ctlr = device_get_softc(dev);
4467
4468 if (ata_setup_interrupt(dev))
4469 return ENXIO;
4470
4471 switch (ctlr->chip->cfg1) {
4472 case SIIPRBIO:
4473 ctlr->r_type1 = SYS_RES_MEMORY;
4474 ctlr->r_rid1 = PCIR_BAR(0);
4475 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
4476 &ctlr->r_rid1, RF_ACTIVE)))
4477 return ENXIO;
4478
4479 ctlr->r_rid2 = PCIR_BAR(2);
4480 ctlr->r_type2 = SYS_RES_MEMORY;
4481 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4482 &ctlr->r_rid2, RF_ACTIVE))){
4483 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
4484 return ENXIO;
4485 }
4486 ctlr->allocate = ata_siiprb_allocate;
4487 ctlr->reset = ata_siiprb_reset;
4488 ctlr->dmainit = ata_siiprb_dmainit;
4489 ctlr->setmode = ata_sata_setmode;
4490 ctlr->channels = (ctlr->chip->cfg2 == SII4CH) ? 4 : 2;
4491
4492 /* reset controller */
4493 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
4494 DELAY(10000);
4495 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
4496
4497 /* enable PCI interrupt */
4498 pci_write_config(dev, PCIR_COMMAND,
4499 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
4500 break;
4501
4502 case SIIMEMIO:
4503 ctlr->r_type2 = SYS_RES_MEMORY;
4504 ctlr->r_rid2 = PCIR_BAR(5);
4505 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4506 &ctlr->r_rid2, RF_ACTIVE)))
4507 return ENXIO;
4508
4509 if (ctlr->chip->cfg2 & SIISETCLK) {
4510 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4511 pci_write_config(dev, 0x8a,
4512 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
4513 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4514 device_printf(dev, "%s could not set ATA133 clock\n",
4515 ctlr->chip->text);
4516 }
4517
4518 /* if we have 4 channels enable the second set */
4519 if (ctlr->chip->cfg2 & SII4CH) {
4520 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
4521 ctlr->channels = 4;
4522 }
4523
4524 /* dont block interrupts from any channel */
4525 pci_write_config(dev, 0x48,
4526 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
4527
4528 /* enable PCI interrupt as BIOS might not */
4529 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
4530
4531 ctlr->allocate = ata_sii_allocate;
4532 if (ctlr->chip->max_dma >= ATA_SA150) {
4533 ctlr->reset = ata_sii_reset;
4534 ctlr->setmode = ata_sata_setmode;
4535 }
4536 else
4537 ctlr->setmode = ata_sii_setmode;
4538 break;
4539
4540 default:
4541 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
4542 device_printf(dev, "HW has secondary channel disabled\n");
4543 ctlr->channels = 1;
4544 }
4545
4546 /* enable interrupt as BIOS might not */
4547 pci_write_config(dev, 0x71, 0x01, 1);
4548
4549 ctlr->allocate = ata_cmd_allocate;
4550 ctlr->setmode = ata_cmd_setmode;
4551 break;
4552 }
4553 return 0;
4554 }
4555
4556 static int
4557 ata_cmd_allocate(device_t dev)
4558 {
4559 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4560 struct ata_channel *ch = device_get_softc(dev);
4561
4562 /* setup the usual register normal pci style */
4563 if (ata_pci_allocate(dev))
4564 return ENXIO;
4565
4566 if (ctlr->chip->cfg2 & SIIINTR)
4567 ch->hw.status = ata_cmd_status;
4568
4569 return 0;
4570 }
4571
4572 static int
4573 ata_cmd_status(device_t dev)
4574 {
4575 struct ata_channel *ch = device_get_softc(dev);
4576 u_int8_t reg71;
4577
4578 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
4579 (ch->unit ? 0x08 : 0x04))) {
4580 pci_write_config(device_get_parent(ch->dev), 0x71,
4581 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
4582 return ata_pci_status(dev);
4583 }
4584 return 0;
4585 }
4586
4587 static void
4588 ata_cmd_setmode(device_t dev, int mode)
4589 {
4590 device_t gparent = GRANDPARENT(dev);
4591 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4592 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4593 struct ata_device *atadev = device_get_softc(dev);
4594 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4595 int error;
4596
4597 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4598
4599 mode = ata_check_80pin(dev, mode);
4600
4601 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4602
4603 if (bootverbose)
4604 device_printf(dev, "%ssetting %s on %s chip\n",
4605 (error) ? "FAILURE " : "",
4606 ata_mode2str(mode), ctlr->chip->text);
4607 if (!error) {
4608 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
4609 int ureg = ch->unit ? 0x7b : 0x73;
4610
4611 if (mode >= ATA_UDMA0) {
4612 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
4613 { 0x11, 0x42 }, { 0x25, 0x8a },
4614 { 0x15, 0x4a }, { 0x05, 0x0a } };
4615
4616 u_int8_t umode = pci_read_config(gparent, ureg, 1);
4617
4618 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
4619 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)];
4620 pci_write_config(gparent, ureg, umode, 1);
4621 }
4622 else if (mode >= ATA_WDMA0) {
4623 int dmatimings[] = { 0x87, 0x32, 0x3f };
4624
4625 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1);
4626 pci_write_config(gparent, ureg,
4627 pci_read_config(gparent, ureg, 1) &
4628 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4629 }
4630 else {
4631 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
4632 pci_write_config(gparent, treg,
4633 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
4634 pci_write_config(gparent, ureg,
4635 pci_read_config(gparent, ureg, 1) &
4636 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4637 }
4638 atadev->mode = mode;
4639 }
4640 }
4641
4642 static int
4643 ata_sii_allocate(device_t dev)
4644 {
4645 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4646 struct ata_channel *ch = device_get_softc(dev);
4647 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
4648 int i;
4649
4650 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
4651 ch->r_io[i].res = ctlr->r_res2;
4652 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
4653 }
4654 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
4655 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
4656 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
4657 ata_default_registers(dev);
4658
4659 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
4660 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
4661 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
4662 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
4663 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
4664 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
4665
4666 if (ctlr->chip->max_dma >= ATA_SA150) {
4667 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4668 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
4669 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4670 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
4671 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4672 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
4673 ch->flags |= ATA_NO_SLAVE;
4674
4675 /* enable PHY state change interrupt */
4676 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
4677 }
4678
4679 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) {
4680 /* work around errata in early chips */
4681 ch->dma->boundary = 8192;
4682 ch->dma->segsize = 15 * DEV_BSIZE;
4683 }
4684
4685 ata_pci_hw(dev);
4686 ch->hw.status = ata_sii_status;
4687 return 0;
4688 }
4689
4690 static int
4691 ata_sii_status(device_t dev)
4692 {
4693 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4694 struct ata_channel *ch = device_get_softc(dev);
4695 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8);
4696 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8);
4697
4698 /* do we have any PHY events ? */
4699 if (ctlr->chip->max_dma >= ATA_SA150 &&
4700 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
4701 ata_sata_phy_check_events(dev);
4702
4703 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
4704 return ata_pci_status(dev);
4705 else
4706 return 0;
4707 }
4708
4709 static void
4710 ata_sii_reset(device_t dev)
4711 {
4712 if (ata_sata_phy_reset(dev))
4713 ata_generic_reset(dev);
4714 }
4715
4716 static void
4717 ata_sii_setmode(device_t dev, int mode)
4718 {
4719 device_t gparent = GRANDPARENT(dev);
4720 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4721 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4722 struct ata_device *atadev = device_get_softc(dev);
4723 int rego = (ch->unit << 4) + (ATA_DEV(atadev->unit) << 1);
4724 int mreg = ch->unit ? 0x84 : 0x80;
4725 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2);
4726 int mval = pci_read_config(gparent, mreg, 1) & ~mask;
4727 int error;
4728
4729 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4730
4731 if (ctlr->chip->cfg2 & SIISETCLK) {
4732 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) &
4733 (ch->unit ? 0x02 : 0x01))) {
4734 ata_print_cable(dev, "controller");
4735 mode = ATA_UDMA2;
4736 }
4737 }
4738 else
4739 mode = ata_check_80pin(dev, mode);
4740
4741 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4742
4743 if (bootverbose)
4744 device_printf(dev, "%ssetting %s on %s chip\n",
4745 (error) ? "FAILURE " : "",
4746 ata_mode2str(mode), ctlr->chip->text);
4747 if (error)
4748 return;
4749
4750 if (mode >= ATA_UDMA0) {
4751 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
4752 u_int8_t ureg = 0xac + rego;
4753
4754 pci_write_config(gparent, mreg,
4755 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1);
4756 pci_write_config(gparent, ureg,
4757 (pci_read_config(gparent, ureg, 1) & ~0x3f) |
4758 udmatimings[mode & ATA_MODE_MASK], 1);
4759
4760 }
4761 else if (mode >= ATA_WDMA0) {
4762 u_int8_t dreg = 0xa8 + rego;
4763 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
4764
4765 pci_write_config(gparent, mreg,
4766 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1);
4767 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
4768
4769 }
4770 else {
4771 u_int8_t preg = 0xa4 + rego;
4772 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
4773
4774 pci_write_config(gparent, mreg,
4775 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1);
4776 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2);
4777 }
4778 atadev->mode = mode;
4779 }
4780
4781
4782 struct ata_siiprb_dma_prdentry {
4783 u_int64_t addr;
4784 u_int32_t count;
4785 u_int32_t control;
4786 } __packed;
4787
4788 struct ata_siiprb_ata_command {
4789 struct ata_siiprb_dma_prdentry prd[126];
4790 } __packed;
4791
4792 struct ata_siiprb_atapi_command {
4793 u_int8_t ccb[16];
4794 struct ata_siiprb_dma_prdentry prd[125];
4795 } __packed;
4796
4797 struct ata_siiprb_command {
4798 u_int16_t control;
4799 u_int16_t protocol_override;
4800 u_int32_t transfer_count;
4801 u_int8_t fis[24];
4802 union {
4803 struct ata_siiprb_ata_command ata;
4804 struct ata_siiprb_atapi_command atapi;
4805 } u;
4806 } __packed;
4807
4808 static int
4809 ata_siiprb_allocate(device_t dev)
4810 {
4811 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4812 struct ata_channel *ch = device_get_softc(dev);
4813 int offset = ch->unit * 0x2000;
4814
4815 /* set the SATA resources */
4816 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4817 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
4818 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4819 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
4820 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4821 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
4822 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
4823 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
4824
4825 ch->hw.begin_transaction = ata_siiprb_begin_transaction;
4826 ch->hw.end_transaction = ata_siiprb_end_transaction;
4827 ch->hw.status = ata_siiprb_status;
4828 ch->hw.command = NULL; /* not used here */
4829 return 0;
4830 }
4831
4832 static int
4833 ata_siiprb_status(device_t dev)
4834 {
4835 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4836 struct ata_channel *ch = device_get_softc(dev);
4837 u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044);
4838 int offset = ch->unit * 0x2000;
4839
4840 if (action & (1 << ch->unit)) {
4841 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
4842
4843 /* do we have any PHY events ? */
4844 ata_sata_phy_check_events(dev);
4845
4846 /* clear interrupt(s) */
4847 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
4848
4849 /* do we have any device action ? */
4850 return (istatus & 0x00000003);
4851 }
4852 return 0;
4853 }
4854
4855 static int
4856 ata_siiprb_begin_transaction(struct ata_request *request)
4857 {
4858 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
4859 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4860 struct ata_siiprb_command *prb;
4861 struct ata_siiprb_dma_prdentry *prd;
4862 int offset = ch->unit * 0x2000;
4863 u_int64_t prb_bus;
4864 int tag = 0, dummy;
4865
4866 /* SOS XXX */
4867 if (request->u.ata.command == ATA_DEVICE_RESET) {
4868 request->result = 0;
4869 return ATA_OP_FINISHED;
4870 }
4871
4872 /* check for 48 bit access and convert if needed */
4873 ata_modify_if_48bit(request);
4874
4875 /* get a piece of the workspace for this request */
4876 prb = (struct ata_siiprb_command *)
4877 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
4878
4879 /* set basic prd options ata/atapi etc etc */
4880 bzero(prb, sizeof(struct ata_siiprb_command));
4881
4882 /* setup the FIS for this request */
4883 if (!ata_request2fis_h2d(request, &prb->fis[0])) {
4884 device_printf(request->dev, "setting up SATA FIS failed\n");
4885 request->result = EIO;
4886 return ATA_OP_FINISHED;
4887 }
4888
4889 /* setup transfer type */
4890 if (request->flags & ATA_R_ATAPI) {
4891 struct ata_device *atadev = device_get_softc(request->dev);
4892
4893 bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16);
4894 if ((atadev->param.config & ATA_PROTO_MASK) == ATA_PROTO_ATAPI_12)
4895 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020);
4896 else
4897 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020);
4898 if (request->flags & ATA_R_READ)
4899 prb->control = htole16(0x0010);
4900 if (request->flags & ATA_R_WRITE)
4901 prb->control = htole16(0x0020);
4902 prd = &prb->u.atapi.prd[0];
4903 }
4904 else
4905 prd = &prb->u.ata.prd[0];
4906
4907 /* if request moves data setup and load SG list */
4908 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
4909 if (ch->dma->load(ch->dev, request->data, request->bytecount,
4910 request->flags & ATA_R_READ, prd, &dummy)) {
4911 device_printf(request->dev, "setting up DMA failed\n");
4912 request->result = EIO;
4913 return ATA_OP_FINISHED;
4914 }
4915 }
4916
4917 /* activate the prb */
4918 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
4919 ATA_OUTL(ctlr->r_res2,
4920 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
4921 ATA_OUTL(ctlr->r_res2,
4922 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
4923
4924 /* start the timeout */
4925 callout_reset(&request->callout, request->timeout * hz,
4926 (timeout_t*)ata_timeout, request);
4927 return ATA_OP_CONTINUES;
4928 }
4929
4930 static int
4931 ata_siiprb_end_transaction(struct ata_request *request)
4932 {
4933 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
4934 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4935 struct ata_siiprb_command *prb;
4936 int offset = ch->unit * 0x2000;
4937 int error, timeout, tag = 0;
4938
4939 /* kill the timeout */
4940 callout_stop(&request->callout);
4941
4942 prb = (struct ata_siiprb_command *)
4943 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
4944
4945 /* any controller errors flagged ? */
4946 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
4947 if (bootverbose)
4948 printf("ata_siiprb_end_transaction %s error=%08x\n",
4949 ata_cmd2str(request), error);
4950
4951 /* if device error status get details */
4952 if (error == 1 || error == 2) {
4953 request->status = prb->fis[2];
4954 if (request->status & ATA_S_ERROR)
4955 request->error = prb->fis[3];
4956 }
4957
4958 /* SOS XXX handle other controller errors here */
4959
4960 /* initialize port */
4961 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004);
4962
4963 /* poll for port ready */
4964 for (timeout = 0; timeout < 1000; timeout++) {
4965 DELAY(1000);
4966 if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000)
4967 break;
4968 }
4969 if (bootverbose) {
4970 if (timeout >= 1000)
4971 device_printf(ch->dev, "port initialize timeout\n");
4972 else
4973 device_printf(ch->dev, "port initialize time=%dms\n", timeout);
4974 }
4975 }
4976
4977 /* update progress */
4978 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
4979 if (request->flags & ATA_R_READ)
4980 request->donecount = prb->transfer_count;
4981 else
4982 request->donecount = request->bytecount;
4983 }
4984
4985 /* release SG list etc */
4986 ch->dma->unload(ch->dev);
4987
4988 return ATA_OP_FINISHED;
4989 }
4990
4991 static void
4992 ata_siiprb_reset(device_t dev)
4993 {
4994 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4995 struct ata_channel *ch = device_get_softc(dev);
4996 int offset = ch->unit * 0x2000;
4997 struct ata_siiprb_command *prb;
4998 u_int64_t prb_bus;
4999 u_int32_t status, signature;
5000 int timeout, tag = 0;
5001
5002 /* reset channel HW */
5003 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
5004 DELAY(1000);
5005 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
5006 DELAY(10000);
5007
5008 /* poll for channel ready */
5009 for (timeout = 0; timeout < 1000; timeout++) {
5010 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000)
5011 break;
5012 DELAY(1000);
5013 }
5014
5015 if (bootverbose) {
5016 if (timeout >= 1000)
5017 device_printf(ch->dev, "channel HW reset timeout\n");
5018 else
5019 device_printf(ch->dev, "channel HW reset time=%dms\n", timeout);
5020 }
5021
5022 /* reset phy */
5023 if (!ata_sata_phy_reset(dev)) {
5024 if (bootverbose)
5025 device_printf(ch->dev, "phy reset found no device\n");
5026 ch->devices = 0;
5027 goto finish;
5028 }
5029
5030 /* get a piece of the workspace for a soft reset request */
5031 prb = (struct ata_siiprb_command *)
5032 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
5033 bzero(prb, sizeof(struct ata_siiprb_command));
5034 prb->control = htole16(0x0080);
5035
5036 /* activate the soft reset prb */
5037 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
5038 ATA_OUTL(ctlr->r_res2,
5039 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
5040 ATA_OUTL(ctlr->r_res2,
5041 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
5042
5043 /* poll for command finished */
5044 for (timeout = 0; timeout < 10000; timeout++) {
5045 DELAY(1000);
5046 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
5047 break;
5048 }
5049 if (timeout >= 1000) {
5050 device_printf(ch->dev, "reset timeout - no device found\n");
5051 ch->devices = 0;
5052 goto finish;
5053 }
5054 if (bootverbose)
5055 device_printf(ch->dev, "soft reset exec time=%dms status=%08x\n",
5056 timeout, status);
5057
5058 /* find out whats there */
5059 prb = (struct ata_siiprb_command *)
5060 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
5061 signature =
5062 prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
5063 if (bootverbose)
5064 device_printf(ch->dev, "SIGNATURE=%08x\n", signature);
5065 switch (signature) {
5066 case 0x00000101:
5067 ch->devices = ATA_ATA_MASTER;
5068 break;
5069 case 0x96690101:
5070 ch->devices = ATA_PORTMULTIPLIER;
5071 device_printf(ch->dev, "Portmultipliers not supported yet\n");
5072 ch->devices = 0;
5073 break;
5074 case 0xeb140101:
5075 ch->devices = ATA_ATAPI_MASTER;
5076 break;
5077 default:
5078 ch->devices = 0;
5079 }
5080 if (bootverbose)
5081 device_printf(dev, "siiprb_reset devices=0x%b\n", ch->devices,
5082 "\2\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
5083
5084 finish:
5085 /* clear interrupt(s) */
5086 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
5087
5088 /* require explicit interrupt ack */
5089 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
5090
5091 /* 64bit mode */
5092 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
5093
5094 /* enable interrupts wanted */
5095 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
5096 }
5097
5098 static void
5099 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
5100 {
5101 struct ata_dmasetprd_args *args = xsc;
5102 struct ata_siiprb_dma_prdentry *prd = args->dmatab;
5103 int i;
5104
5105 if ((args->error = error))
5106 return;
5107
5108 for (i = 0; i < nsegs; i++) {
5109 prd[i].addr = htole64(segs[i].ds_addr);
5110 prd[i].count = htole32(segs[i].ds_len);
5111 }
5112 prd[i - 1].control = htole32(ATA_DMA_EOT);
5113 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
5114 args->nsegs = nsegs;
5115 }
5116
5117 static void
5118 ata_siiprb_dmainit(device_t dev)
5119 {
5120 struct ata_channel *ch = device_get_softc(dev);
5121
5122 ata_dmainit(dev);
5123 if (ch->dma) {
5124 /* note start and stop are not used here */
5125 ch->dma->setprd = ata_siiprb_dmasetprd;
5126 ch->dma->max_address = BUS_SPACE_MAXADDR;
5127 }
5128 }
5129
5130
5131 /*
5132 * Silicon Integrated Systems Corp. (SiS) chipset support functions
5133 */
5134 int
5135 ata_sis_ident(device_t dev)
5136 {
5137 struct ata_pci_controller *ctlr = device_get_softc(dev);
5138 struct ata_chip_id *idx;
5139 static struct ata_chip_id ids[] =
5140 {{ ATA_SIS182, 0x00, SISSATA, 0, ATA_SA150, "182" }, /* south */
5141 { ATA_SIS181, 0x00, SISSATA, 0, ATA_SA150, "181" }, /* south */
5142 { ATA_SIS180, 0x00, SISSATA, 0, ATA_SA150, "180" }, /* south */
5143 { ATA_SIS965, 0x00, SIS133NEW, 0, ATA_UDMA6, "965" }, /* south */
5144 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "964" }, /* south */
5145 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "963" }, /* south */
5146 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "962" }, /* south */
5147
5148 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */
5149 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */
5150 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */
5151 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */
5152
5153 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */
5154 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "633" }, /* unknown */
5155 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */
5156 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "630" }, /* 1chip */
5157 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "620" }, /* 1chip */
5158
5159 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "550" },
5160 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "540" },
5161 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "530" },
5162
5163 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "5513" },
5164 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "5513" },
5165 { 0, 0, 0, 0, 0, 0 }};
5166 char buffer[64];
5167 int found = 0;
5168
5169 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev))))
5170 return ENXIO;
5171
5172 if (idx->cfg2 && !found) {
5173 u_int8_t reg57 = pci_read_config(dev, 0x57, 1);
5174
5175 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1);
5176 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) {
5177 found = 1;
5178 idx->cfg1 = SIS133NEW;
5179 idx->max_dma = ATA_UDMA6;
5180 sprintf(buffer, "SiS 962/963 %s controller",
5181 ata_mode2str(idx->max_dma));
5182 }
5183 pci_write_config(dev, 0x57, reg57, 1);
5184 }
5185 if (idx->cfg2 && !found) {
5186 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1);
5187
5188 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1);
5189 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) {
5190 struct ata_chip_id id[] =
5191 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }};
5192
5193 found = 1;
5194 if (ata_find_chip(dev, id, pci_get_slot(dev))) {
5195 idx->cfg1 = SIS133OLD;
5196 idx->max_dma = ATA_UDMA6;
5197 }
5198 else {
5199 idx->cfg1 = SIS100NEW;
5200 idx->max_dma = ATA_UDMA5;
5201 }
5202 sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
5203 }
5204 pci_write_config(dev, 0x4a, reg4a, 1);
5205 }
5206 if (!found)
5207 sprintf(buffer,"SiS %s %s controller",
5208 idx->text, ata_mode2str(idx->max_dma));
5209
5210 device_set_desc_copy(dev, buffer);
5211 ctlr->chip = idx;
5212 ctlr->chipinit = ata_sis_chipinit;
5213 return 0;
5214 }
5215
5216 static int
5217 ata_sis_chipinit(device_t dev)
5218 {
5219 struct ata_pci_controller *ctlr = device_get_softc(dev);
5220
5221 if (ata_setup_interrupt(dev))
5222 return ENXIO;
5223
5224 switch (ctlr->chip->cfg1) {
5225 case SIS33:
5226 break;
5227 case SIS66:
5228 case SIS100OLD:
5229 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1);
5230 break;
5231 case SIS100NEW:
5232 case SIS133OLD:
5233 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1);
5234 break;
5235 case SIS133NEW:
5236 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2);
5237 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2);
5238 break;
5239 case SISSATA:
5240 ctlr->r_type2 = SYS_RES_IOPORT;
5241 ctlr->r_rid2 = PCIR_BAR(5);
5242 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
5243 &ctlr->r_rid2, RF_ACTIVE))) {
5244 ctlr->allocate = ata_sis_allocate;
5245 ctlr->reset = ata_sis_reset;
5246
5247 /* enable PCI interrupt */
5248 pci_write_config(dev, PCIR_COMMAND,
5249 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
5250 }
5251 ctlr->setmode = ata_sata_setmode;
5252 return 0;
5253 default:
5254 return ENXIO;
5255 }
5256 ctlr->setmode = ata_sis_setmode;
5257 return 0;
5258 }
5259
5260 static int
5261 ata_sis_allocate(device_t dev)
5262 {
5263 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5264 struct ata_channel *ch = device_get_softc(dev);
5265 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6);
5266
5267 /* setup the usual register normal pci style */
5268 if (ata_pci_allocate(dev))
5269 return ENXIO;
5270
5271 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
5272 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset;
5273 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
5274 ch->r_io[ATA_SERROR].offset = 0x04 + offset;
5275 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
5276 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset;
5277 ch->flags |= ATA_NO_SLAVE;
5278
5279 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */
5280 /* XXX SOS unknown how to enable PHY state change interrupt */
5281 return 0;
5282 }
5283
5284 static void
5285 ata_sis_reset(device_t dev)
5286 {
5287 if (ata_sata_phy_reset(dev))
5288 ata_generic_reset(dev);
5289 }
5290
5291 static void
5292 ata_sis_setmode(device_t dev, int mode)
5293 {
5294 device_t gparent = GRANDPARENT(dev);
5295 struct ata_pci_controller *ctlr = device_get_softc(gparent);
5296 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5297 struct ata_device *atadev = device_get_softc(dev);
5298 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
5299 int error;
5300
5301 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
5302
5303 if (ctlr->chip->cfg1 == SIS133NEW) {
5304 if (mode > ATA_UDMA2 &&
5305 pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) {
5306 ata_print_cable(dev, "controller");
5307 mode = ATA_UDMA2;
5308 }
5309 }
5310 else {
5311 if (mode > ATA_UDMA2 &&
5312 pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) {
5313 ata_print_cable(dev, "controller");
5314 mode = ATA_UDMA2;
5315 }
5316 }
5317
5318 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
5319
5320 if (bootverbose)
5321 device_printf(dev, "%ssetting %s on %s chip\n",
5322 (error) ? "FAILURE " : "",
5323 ata_mode2str(mode), ctlr->chip->text);
5324 if (!error) {
5325 switch (ctlr->chip->cfg1) {
5326 case SIS133NEW: {
5327 u_int32_t timings[] =
5328 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
5329 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
5330 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
5331 u_int32_t reg;
5332
5333 reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
5334 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4);
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