1 /*-
2 * Copyright (c) 1998 - 2007 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include "opt_ata.h"
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/ata.h>
35 #include <sys/bus.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <sys/sema.h>
41 #include <sys/taskqueue.h>
42 #include <vm/uma.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
46 #include <sys/rman.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49 #include <dev/ata/ata-all.h>
50 #include <dev/ata/ata-pci.h>
51 #include <ata_if.h>
52
53 /* local prototypes */
54 /* ata-chipset.c */
55 static int ata_generic_chipinit(device_t dev);
56 static void ata_generic_intr(void *data);
57 static void ata_generic_setmode(device_t dev, int mode);
58 static void ata_sata_phy_check_events(device_t dev);
59 static void ata_sata_phy_event(void *context, int dummy);
60 static int ata_sata_phy_reset(device_t dev);
61 static int ata_sata_connect(struct ata_channel *ch);
62 static void ata_sata_setmode(device_t dev, int mode);
63 static int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis);
64 static int ata_ahci_chipinit(device_t dev);
65 static int ata_ahci_allocate(device_t dev);
66 static int ata_ahci_status(device_t dev);
67 static int ata_ahci_begin_transaction(struct ata_request *request);
68 static int ata_ahci_end_transaction(struct ata_request *request);
69 static void ata_ahci_reset(device_t dev);
70 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
71 static void ata_ahci_dmainit(device_t dev);
72 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request);
73 static int ata_acard_chipinit(device_t dev);
74 static int ata_acard_allocate(device_t dev);
75 static int ata_acard_status(device_t dev);
76 static void ata_acard_850_setmode(device_t dev, int mode);
77 static void ata_acard_86X_setmode(device_t dev, int mode);
78 static int ata_ali_chipinit(device_t dev);
79 static int ata_ali_allocate(device_t dev);
80 static int ata_ali_sata_allocate(device_t dev);
81 static void ata_ali_reset(device_t dev);
82 static void ata_ali_setmode(device_t dev, int mode);
83 static int ata_amd_chipinit(device_t dev);
84 static int ata_ati_chipinit(device_t dev);
85 static void ata_ati_setmode(device_t dev, int mode);
86 static int ata_cyrix_chipinit(device_t dev);
87 static void ata_cyrix_setmode(device_t dev, int mode);
88 static int ata_cypress_chipinit(device_t dev);
89 static void ata_cypress_setmode(device_t dev, int mode);
90 static int ata_highpoint_chipinit(device_t dev);
91 static int ata_highpoint_allocate(device_t dev);
92 static void ata_highpoint_setmode(device_t dev, int mode);
93 static int ata_highpoint_check_80pin(device_t dev, int mode);
94 static int ata_intel_chipinit(device_t dev);
95 static int ata_intel_allocate(device_t dev);
96 static void ata_intel_reset(device_t dev);
97 static void ata_intel_old_setmode(device_t dev, int mode);
98 static void ata_intel_new_setmode(device_t dev, int mode);
99 static void ata_intel_sata_setmode(device_t dev, int mode);
100 static int ata_intel_31244_allocate(device_t dev);
101 static int ata_intel_31244_status(device_t dev);
102 static void ata_intel_31244_tf_write(struct ata_request *request);
103 static void ata_intel_31244_reset(device_t dev);
104 static int ata_ite_chipinit(device_t dev);
105 static void ata_ite_setmode(device_t dev, int mode);
106 static int ata_jmicron_chipinit(device_t dev);
107 static int ata_jmicron_allocate(device_t dev);
108 static void ata_jmicron_reset(device_t dev);
109 static void ata_jmicron_dmainit(device_t dev);
110 static void ata_jmicron_setmode(device_t dev, int mode);
111 static int ata_marvell_pata_chipinit(device_t dev);
112 static int ata_marvell_pata_allocate(device_t dev);
113 static void ata_marvell_pata_setmode(device_t dev, int mode);
114 static int ata_marvell_edma_chipinit(device_t dev);
115 static int ata_marvell_edma_allocate(device_t dev);
116 static int ata_marvell_edma_status(device_t dev);
117 static int ata_marvell_edma_begin_transaction(struct ata_request *request);
118 static int ata_marvell_edma_end_transaction(struct ata_request *request);
119 static void ata_marvell_edma_reset(device_t dev);
120 static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
121 static void ata_marvell_edma_dmainit(device_t dev);
122 static int ata_national_chipinit(device_t dev);
123 static void ata_national_setmode(device_t dev, int mode);
124 static int ata_netcell_chipinit(device_t dev);
125 static int ata_netcell_allocate(device_t dev);
126 static int ata_nvidia_chipinit(device_t dev);
127 static int ata_nvidia_allocate(device_t dev);
128 static int ata_nvidia_status(device_t dev);
129 static void ata_nvidia_reset(device_t dev);
130 static int ata_promise_chipinit(device_t dev);
131 static int ata_promise_allocate(device_t dev);
132 static int ata_promise_status(device_t dev);
133 static int ata_promise_dmastart(device_t dev);
134 static int ata_promise_dmastop(device_t dev);
135 static void ata_promise_dmareset(device_t dev);
136 static void ata_promise_dmainit(device_t dev);
137 static void ata_promise_setmode(device_t dev, int mode);
138 static int ata_promise_tx2_allocate(device_t dev);
139 static int ata_promise_tx2_status(device_t dev);
140 static int ata_promise_mio_allocate(device_t dev);
141 static void ata_promise_mio_intr(void *data);
142 static int ata_promise_mio_status(device_t dev);
143 static int ata_promise_mio_command(struct ata_request *request);
144 static void ata_promise_mio_reset(device_t dev);
145 static void ata_promise_mio_dmainit(device_t dev);
146 static void ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
147 static void ata_promise_mio_setmode(device_t dev, int mode);
148 static void ata_promise_sx4_intr(void *data);
149 static int ata_promise_sx4_command(struct ata_request *request);
150 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request);
151 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt);
152 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr);
153 static int ata_serverworks_chipinit(device_t dev);
154 static int ata_serverworks_allocate(device_t dev);
155 static void ata_serverworks_tf_read(struct ata_request *request);
156 static void ata_serverworks_tf_write(struct ata_request *request);
157 static void ata_serverworks_setmode(device_t dev, int mode);
158 static int ata_sii_chipinit(device_t dev);
159 static int ata_cmd_allocate(device_t dev);
160 static int ata_cmd_status(device_t dev);
161 static void ata_cmd_setmode(device_t dev, int mode);
162 static int ata_sii_allocate(device_t dev);
163 static int ata_sii_status(device_t dev);
164 static void ata_sii_reset(device_t dev);
165 static void ata_sii_setmode(device_t dev, int mode);
166 static int ata_siiprb_allocate(device_t dev);
167 static int ata_siiprb_status(device_t dev);
168 static int ata_siiprb_begin_transaction(struct ata_request *request);
169 static int ata_siiprb_end_transaction(struct ata_request *request);
170 static void ata_siiprb_reset(device_t dev);
171 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
172 static void ata_siiprb_dmainit(device_t dev);
173 static int ata_sis_chipinit(device_t dev);
174 static int ata_sis_allocate(device_t dev);
175 static void ata_sis_reset(device_t dev);
176 static void ata_sis_setmode(device_t dev, int mode);
177 static int ata_via_chipinit(device_t dev);
178 static int ata_via_allocate(device_t dev);
179 static void ata_via_reset(device_t dev);
180 static void ata_via_setmode(device_t dev, int mode);
181 static void ata_via_southbridge_fixup(device_t dev);
182 static void ata_via_family_setmode(device_t dev, int mode);
183 static void ata_set_desc(device_t dev);
184 static struct ata_chip_id *ata_match_chip(device_t dev, struct ata_chip_id *index);
185 static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot);
186 static int ata_setup_interrupt(device_t dev);
187 static int ata_serialize(device_t dev, int flags);
188 static void ata_print_cable(device_t dev, u_int8_t *who);
189 static int ata_atapi(device_t dev);
190 static int ata_check_80pin(device_t dev, int mode);
191 static int ata_mode2idx(int mode);
192
193
194 /*
195 * generic ATA support functions
196 */
197 int
198 ata_generic_ident(device_t dev)
199 {
200 struct ata_pci_controller *ctlr = device_get_softc(dev);
201 char buffer[64];
202
203 sprintf(buffer, "%s ATA controller", ata_pcivendor2str(dev));
204 device_set_desc_copy(dev, buffer);
205 ctlr->chipinit = ata_generic_chipinit;
206 return 0;
207 }
208
209 static int
210 ata_generic_chipinit(device_t dev)
211 {
212 struct ata_pci_controller *ctlr = device_get_softc(dev);
213
214 if (ata_setup_interrupt(dev))
215 return ENXIO;
216 ctlr->setmode = ata_generic_setmode;
217 return 0;
218 }
219
220 static void
221 ata_generic_intr(void *data)
222 {
223 struct ata_pci_controller *ctlr = data;
224 struct ata_channel *ch;
225 int unit;
226
227 for (unit = 0; unit < ctlr->channels; unit++) {
228 if ((ch = ctlr->interrupt[unit].argument))
229 ctlr->interrupt[unit].function(ch);
230 }
231 }
232
233 static void
234 ata_generic_setmode(device_t dev, int mode)
235 {
236 struct ata_device *atadev = device_get_softc(dev);
237
238 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
239 mode = ata_check_80pin(dev, mode);
240 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
241 atadev->mode = mode;
242 }
243
244
245 /*
246 * SATA support functions
247 */
248 static void
249 ata_sata_phy_check_events(device_t dev)
250 {
251 struct ata_channel *ch = device_get_softc(dev);
252 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR);
253
254 /* clear error bits/interrupt */
255 ATA_IDX_OUTL(ch, ATA_SERROR, error);
256
257 /* do we have any events flagged ? */
258 if (error) {
259 struct ata_connect_task *tp;
260 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS);
261
262 /* if we have a connection event deal with it */
263 if ((error & ATA_SE_PHY_CHANGED) &&
264 (tp = (struct ata_connect_task *)
265 malloc(sizeof(struct ata_connect_task),
266 M_ATA, M_NOWAIT | M_ZERO))) {
267
268 if (((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) ||
269 ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)) {
270 if (bootverbose)
271 device_printf(ch->dev, "CONNECT requested\n");
272 tp->action = ATA_C_ATTACH;
273 }
274 else {
275 if (bootverbose)
276 device_printf(ch->dev, "DISCONNECT requested\n");
277 tp->action = ATA_C_DETACH;
278 }
279 tp->dev = ch->dev;
280 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
281 taskqueue_enqueue(taskqueue_thread, &tp->task);
282 }
283 }
284 }
285
286 static void
287 ata_sata_phy_event(void *context, int dummy)
288 {
289 struct ata_connect_task *tp = (struct ata_connect_task *)context;
290 struct ata_channel *ch = device_get_softc(tp->dev);
291 device_t *children;
292 int nchildren, i;
293
294 mtx_lock(&Giant); /* newbus suckage it needs Giant */
295 if (tp->action == ATA_C_ATTACH) {
296 if (bootverbose)
297 device_printf(tp->dev, "CONNECTED\n");
298 ATA_RESET(tp->dev);
299 ata_identify(tp->dev);
300 }
301 if (tp->action == ATA_C_DETACH) {
302 if (!device_get_children(tp->dev, &children, &nchildren)) {
303 for (i = 0; i < nchildren; i++)
304 if (children[i])
305 device_delete_child(tp->dev, children[i]);
306 free(children, M_TEMP);
307 }
308 mtx_lock(&ch->state_mtx);
309 ch->state = ATA_IDLE;
310 mtx_unlock(&ch->state_mtx);
311 if (bootverbose)
312 device_printf(tp->dev, "DISCONNECTED\n");
313 }
314 mtx_unlock(&Giant); /* suckage code dealt with, release Giant */
315 free(tp, M_ATA);
316 }
317
318 static int
319 ata_sata_phy_reset(device_t dev)
320 {
321 struct ata_channel *ch = device_get_softc(dev);
322 int loop, retry;
323
324 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE)
325 return ata_sata_connect(ch);
326
327 for (retry = 0; retry < 10; retry++) {
328 for (loop = 0; loop < 10; loop++) {
329 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET);
330 ata_udelay(100);
331 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) ==
332 ATA_SC_DET_RESET)
333 break;
334 }
335 ata_udelay(5000);
336 for (loop = 0; loop < 10; loop++) {
337 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_IDLE |
338 ATA_SC_IPM_DIS_PARTIAL |
339 ATA_SC_IPM_DIS_SLUMBER);
340 ata_udelay(100);
341 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 0)
342 return ata_sata_connect(ch);
343 }
344 }
345 return 0;
346 }
347
348 static int
349 ata_sata_connect(struct ata_channel *ch)
350 {
351 u_int32_t status;
352 int timeout;
353
354 /* wait up to 1 second for "connect well" */
355 for (timeout = 0; timeout < 100 ; timeout++) {
356 status = ATA_IDX_INL(ch, ATA_SSTATUS);
357 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 ||
358 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)
359 break;
360 ata_udelay(10000);
361 }
362 if (timeout >= 100) {
363 if (bootverbose)
364 device_printf(ch->dev, "SATA connect status=%08x\n", status);
365 return 0;
366 }
367 if (bootverbose)
368 device_printf(ch->dev, "SATA connect time=%dms\n", timeout * 10);
369
370 /* clear SATA error register */
371 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
372
373 return 1;
374 }
375
376 static void
377 ata_sata_setmode(device_t dev, int mode)
378 {
379 struct ata_device *atadev = device_get_softc(dev);
380
381 /*
382 * if we detect that the device isn't a real SATA device we limit
383 * the transfer mode to UDMA5/ATA100.
384 * this works around the problems some devices has with the
385 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133.
386 */
387 if (atadev->param.satacapabilities != 0x0000 &&
388 atadev->param.satacapabilities != 0xffff) {
389 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
390
391 /* on some drives we need to set the transfer mode */
392 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
393 ata_limit_mode(dev, mode, ATA_UDMA6));
394
395 /* query SATA STATUS for the speed */
396 if (ch->r_io[ATA_SSTATUS].res &&
397 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) ==
398 ATA_SS_CONWELL_GEN2))
399 atadev->mode = ATA_SA300;
400 else
401 atadev->mode = ATA_SA150;
402 }
403 else {
404 mode = ata_limit_mode(dev, mode, ATA_UDMA5);
405 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
406 atadev->mode = mode;
407 }
408 }
409
410 static int
411 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis)
412 {
413 struct ata_device *atadev = device_get_softc(request->dev);
414
415 if (request->flags & ATA_R_ATAPI) {
416 fis[0] = 0x27; /* host to device */
417 fis[1] = 0x80; /* command FIS (note PM goes here) */
418 fis[2] = ATA_PACKET_CMD;
419 if (request->flags & (ATA_R_READ | ATA_R_WRITE))
420 fis[3] = ATA_F_DMA;
421 else {
422 fis[5] = request->transfersize;
423 fis[6] = request->transfersize >> 8;
424 }
425 fis[7] = ATA_D_LBA | atadev->unit;
426 fis[15] = ATA_A_4BIT;
427 return 20;
428 }
429 else {
430 ata_modify_if_48bit(request);
431 fis[0] = 0x27; /* host to device */
432 fis[1] = 0x80; /* command FIS (note PM goes here) */
433 fis[2] = request->u.ata.command;
434 fis[3] = request->u.ata.feature;
435 fis[4] = request->u.ata.lba;
436 fis[5] = request->u.ata.lba >> 8;
437 fis[6] = request->u.ata.lba >> 16;
438 fis[7] = ATA_D_LBA | atadev->unit;
439 if (!(atadev->flags & ATA_D_48BIT_ACTIVE))
440 fis[7] |= (request->u.ata.lba >> 24 & 0x0f);
441 fis[8] = request->u.ata.lba >> 24;
442 fis[9] = request->u.ata.lba >> 32;
443 fis[10] = request->u.ata.lba >> 40;
444 fis[11] = request->u.ata.feature >> 8;
445 fis[12] = request->u.ata.count;
446 fis[13] = request->u.ata.count >> 8;
447 fis[15] = ATA_A_4BIT;
448 return 20;
449 }
450 return 0;
451 }
452
453
454 /*
455 * AHCI v1.x compliant SATA chipset support functions
456 */
457 int
458 ata_ahci_ident(device_t dev)
459 {
460 struct ata_pci_controller *ctlr = device_get_softc(dev);
461 char buffer[64];
462
463 /* is this PCI device flagged as an AHCI compliant chip ? */
464 if (pci_read_config(dev, PCIR_PROGIF, 1) != PCIP_STORAGE_SATA_AHCI_1_0)
465 return ENXIO;
466
467 if (bootverbose)
468 sprintf(buffer, "%s (ID=%08x) AHCI controller",
469 ata_pcivendor2str(dev), pci_get_devid(dev));
470 else
471 sprintf(buffer, "%s AHCI controller", ata_pcivendor2str(dev));
472 device_set_desc_copy(dev, buffer);
473 ctlr->chipinit = ata_ahci_chipinit;
474 return 0;
475 }
476
477 static int
478 ata_ahci_chipinit(device_t dev)
479 {
480 struct ata_pci_controller *ctlr = device_get_softc(dev);
481 u_int32_t version;
482
483 /* if we have a memory BAR(5) we are likely on an AHCI part */
484 ctlr->r_type2 = SYS_RES_MEMORY;
485 ctlr->r_rid2 = PCIR_BAR(5);
486 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
487 &ctlr->r_rid2, RF_ACTIVE)))
488 return ENXIO;
489
490 /* setup interrupt delivery if not done allready by a vendor driver */
491 if (!ctlr->r_irq) {
492 if (ata_setup_interrupt(dev))
493 return ENXIO;
494 }
495 else
496 device_printf(dev, "AHCI called from vendor specific driver\n");
497
498 /* enable AHCI mode */
499 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
500
501 /* reset AHCI controller */
502 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_HR);
503 DELAY(1000000);
504 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) {
505 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
506 device_printf(dev, "AHCI controller reset failure\n");
507 return ENXIO;
508 }
509
510 /* reenable AHCI mode */
511 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
512
513 /* get the number of HW channels */
514 ctlr->channels =
515 MAX(flsl(ATA_INL(ctlr->r_res2, ATA_AHCI_PI)),
516 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
517
518 /* clear interrupts */
519 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS));
520
521 /* enable AHCI interrupts */
522 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
523 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE);
524
525 ctlr->reset = ata_ahci_reset;
526 ctlr->dmainit = ata_ahci_dmainit;
527 ctlr->allocate = ata_ahci_allocate;
528 ctlr->setmode = ata_sata_setmode;
529
530 /* enable PCI interrupt */
531 pci_write_config(dev, PCIR_COMMAND,
532 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
533
534 /* announce we support the HW */
535 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS);
536 device_printf(dev,
537 "AHCI Version %x%x.%x%x controller with %d ports detected\n",
538 (version >> 24) & 0xff, (version >> 16) & 0xff,
539 (version >> 8) & 0xff, version & 0xff,
540 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
541 return 0;
542 }
543
544 static int
545 ata_ahci_allocate(device_t dev)
546 {
547 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
548 struct ata_channel *ch = device_get_softc(dev);
549 u_int64_t work;
550 int offset = ch->unit << 7;
551
552 /* set the SATA resources */
553 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
554 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset;
555 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
556 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset;
557 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
558 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset;
559 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
560 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset;
561
562 ch->hw.status = ata_ahci_status;
563 ch->hw.begin_transaction = ata_ahci_begin_transaction;
564 ch->hw.end_transaction = ata_ahci_end_transaction;
565 ch->hw.command = NULL; /* not used here */
566
567 /* setup work areas */
568 work = ch->dma->work_bus + ATA_AHCI_CL_OFFSET;
569 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff);
570 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32);
571
572 work = ch->dma->work_bus + ATA_AHCI_FB_OFFSET;
573 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff);
574 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32);
575
576 /* enable wanted port interrupts */
577 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
578 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
579 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
580 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP |
581 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS |
582 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR));
583
584 /* start operations on this channel */
585 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
586 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
587 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
588 return 0;
589 }
590
591 static int
592 ata_ahci_status(device_t dev)
593 {
594 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
595 struct ata_channel *ch = device_get_softc(dev);
596 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS);
597 int offset = ch->unit << 7;
598 int tag = 0;
599
600 if (action & (1 << ch->unit)) {
601 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset);
602 u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset);
603
604 /* clear interrupt(s) */
605 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action & (1 << ch->unit));
606 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus);
607
608 /* do we have any PHY events ? */
609 /* XXX SOS check istatus phy bits */
610 ata_sata_phy_check_events(dev);
611
612 /* do we have a potentially hanging engine to take care of? */
613 if ((istatus & 0x78400050) && (cstatus & (1 << tag))) {
614
615 u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
616 int timeout = 0;
617
618 /* kill off all activity on this channel */
619 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
620 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
621
622 /* XXX SOS this is not entirely wrong */
623 do {
624 DELAY(1000);
625 if (timeout++ > 500) {
626 device_printf(dev, "stopping AHCI engine failed\n");
627 break;
628 }
629 } while (ATA_INL(ctlr->r_res2,
630 ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
631
632 /* start operations on this channel */
633 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
634 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
635
636 return 1;
637 }
638 else
639 return (!(cstatus & (1 << tag)));
640 }
641 return 0;
642 }
643
644 /* must be called with ATA channel locked and state_mtx held */
645 static int
646 ata_ahci_begin_transaction(struct ata_request *request)
647 {
648 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
649 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
650 struct ata_ahci_cmd_tab *ctp;
651 struct ata_ahci_cmd_list *clp;
652 int offset = ch->unit << 7;
653 int tag = 0, entries = 0;
654 int fis_size;
655
656 /* get a piece of the workspace for this request */
657 ctp = (struct ata_ahci_cmd_tab *)
658 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag));
659
660 /* setup the FIS for this request */
661 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) {
662 device_printf(request->dev, "setting up SATA FIS failed\n");
663 request->result = EIO;
664 return ATA_OP_FINISHED;
665 }
666
667 /* if request moves data setup and load SG list */
668 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
669 if (ch->dma->load(ch->dev, request->data, request->bytecount,
670 request->flags & ATA_R_READ,
671 ctp->prd_tab, &entries)) {
672 device_printf(request->dev, "setting up DMA failed\n");
673 request->result = EIO;
674 return ATA_OP_FINISHED;
675 }
676 }
677
678 /* setup the command list entry */
679 clp = (struct ata_ahci_cmd_list *)
680 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
681
682 clp->prd_length = entries;
683 clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) |
684 (request->flags & ATA_R_ATAPI ? ((1<<5) | (1<<7)) : 0) |
685 (fis_size / sizeof(u_int32_t));
686 clp->bytecount = 0;
687 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET +
688 (ATA_AHCI_CT_SIZE * tag));
689
690 /* clear eventual ACTIVE bit */
691 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag));
692
693 /* set command type bit */
694 if (request->flags & ATA_R_ATAPI)
695 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
696 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) |
697 ATA_AHCI_P_CMD_ATAPI);
698 else
699 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
700 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) &
701 ~ATA_AHCI_P_CMD_ATAPI);
702
703 /* issue command to controller */
704 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << tag));
705
706 if (!(request->flags & ATA_R_ATAPI)) {
707 /* device reset doesn't interrupt */
708 if (request->u.ata.command == ATA_DEVICE_RESET) {
709 u_int32_t tf_data;
710 int timeout = 1000000;
711
712 do {
713 DELAY(10);
714 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7));
715 } while ((tf_data & ATA_S_BUSY) && timeout--);
716 if (bootverbose)
717 device_printf(ch->dev, "device_reset timeout=%dus\n",
718 (1000000-timeout)*10);
719 request->status = tf_data;
720 if (request->status & ATA_S_ERROR)
721 request->error = tf_data >> 8;
722 return ATA_OP_FINISHED;
723 }
724 }
725
726 /* start the timeout */
727 callout_reset(&request->callout, request->timeout * hz,
728 (timeout_t*)ata_timeout, request);
729 return ATA_OP_CONTINUES;
730 }
731
732 /* must be called with ATA channel locked and state_mtx held */
733 static int
734 ata_ahci_end_transaction(struct ata_request *request)
735 {
736 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
737 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
738 struct ata_ahci_cmd_list *clp;
739 u_int32_t tf_data;
740 int offset = ch->unit << 7;
741 int tag = 0;
742
743 /* kill the timeout */
744 callout_stop(&request->callout);
745
746 /* get status */
747 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset);
748 request->status = tf_data;
749
750 /* if error status get details */
751 if (request->status & ATA_S_ERROR)
752 request->error = tf_data >> 8;
753
754 /* record how much data we actually moved */
755 clp = (struct ata_ahci_cmd_list *)
756 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
757 request->donecount = clp->bytecount;
758
759 /* release SG list etc */
760 ch->dma->unload(ch->dev);
761
762 return ATA_OP_FINISHED;
763 }
764
765 static void
766 ata_ahci_reset(device_t dev)
767 {
768 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
769 struct ata_channel *ch = device_get_softc(dev);
770 u_int32_t cmd, signature;
771 int offset = ch->unit << 7;
772 int timeout;
773
774 if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) {
775 device_printf(dev, "port not implemented\n");
776 return;
777 }
778 ch->devices = 0;
779
780 /* kill off all activity on this channel */
781 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
782 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
783 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
784
785 /* XXX SOS this is not entirely wrong */
786 timeout = 0;
787 do {
788 DELAY(1000);
789 if (timeout++ > 500) {
790 device_printf(dev, "stopping AHCI engine failed\n");
791 break;
792 }
793 }
794 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
795
796 /* issue Command List Override if supported */
797 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) {
798 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
799 cmd |= ATA_AHCI_P_CMD_CLO;
800 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd);
801 timeout = 0;
802 do {
803 DELAY(1000);
804 if (timeout++ > 500) {
805 device_printf(dev, "executing CLO failed\n");
806 break;
807 }
808 }
809 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO);
810 }
811
812 /* reset PHY and decide what is present */
813 if (ata_sata_phy_reset(dev)) {
814
815 /* clear any interrupts pending on this channel */
816 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
817 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
818
819 /* clear SATA error register */
820 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
821
822 /* start operations on this channel */
823 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
824 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
825 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
826
827 signature = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset);
828 if (bootverbose)
829 device_printf(dev, "SIGNATURE: %08x\n", signature);
830 switch (signature) {
831 case 0x00000101:
832 ch->devices = ATA_ATA_MASTER;
833 break;
834 case 0x96690101:
835 ch->devices = ATA_PORTMULTIPLIER;
836 device_printf(ch->dev, "Portmultipliers not supported yet\n");
837 ch->devices = 0;
838 break;
839 case 0xeb140101:
840 ch->devices = ATA_ATAPI_MASTER;
841 break;
842 default: /* SOS XXX */
843 if (bootverbose)
844 device_printf(ch->dev, "No signature, asuming disk device\n");
845 ch->devices = ATA_ATA_MASTER;
846 }
847 }
848 if (bootverbose)
849 device_printf(dev, "ahci_reset devices=0x%b\n", ch->devices,
850 "\2\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
851 }
852
853 static void
854 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
855 {
856 struct ata_dmasetprd_args *args = xsc;
857 struct ata_ahci_dma_prd *prd = args->dmatab;
858 int i;
859
860 if (!(args->error = error)) {
861 for (i = 0; i < nsegs; i++) {
862 prd[i].dba = htole64(segs[i].ds_addr);
863 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK);
864 }
865 }
866 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
867 args->nsegs = nsegs;
868 }
869
870 static void
871 ata_ahci_dmainit(device_t dev)
872 {
873 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
874 struct ata_channel *ch = device_get_softc(dev);
875
876 ata_dmainit(dev);
877 if (ch->dma) {
878 /* note start and stop are not used here */
879 ch->dma->setprd = ata_ahci_dmasetprd;
880 ch->dma->max_iosize = 8192 * DEV_BSIZE;
881 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT)
882 ch->dma->max_address = BUS_SPACE_MAXADDR;
883 }
884 }
885
886 static int
887 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request)
888 {
889 bzero(ctp->cfis, 64);
890 if (request->flags & ATA_R_ATAPI) {
891 bzero(ctp->acmd, 32);
892 bcopy(request->u.atapi.ccb, ctp->acmd, 16);
893 }
894 return ata_request2fis_h2d(request, &ctp->cfis[0]);
895 }
896
897
898 /*
899 * Acard chipset support functions
900 */
901 int
902 ata_acard_ident(device_t dev)
903 {
904 struct ata_pci_controller *ctlr = device_get_softc(dev);
905 static struct ata_chip_id ids[] =
906 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "ATP850" },
907 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "ATP860A" },
908 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "ATP860R" },
909 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "ATP865A" },
910 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "ATP865R" },
911 { 0, 0, 0, 0, 0, 0}};
912
913 if (!(ctlr->chip = ata_match_chip(dev, ids)))
914 return ENXIO;
915
916 ata_set_desc(dev);
917 ctlr->chipinit = ata_acard_chipinit;
918 return 0;
919 }
920
921 static int
922 ata_acard_chipinit(device_t dev)
923 {
924 struct ata_pci_controller *ctlr = device_get_softc(dev);
925
926 if (ata_setup_interrupt(dev))
927 return ENXIO;
928
929 ctlr->allocate = ata_acard_allocate;
930 if (ctlr->chip->cfg1 == ATPOLD) {
931 ctlr->setmode = ata_acard_850_setmode;
932 ctlr->locking = ata_serialize;
933 }
934 else
935 ctlr->setmode = ata_acard_86X_setmode;
936 return 0;
937 }
938
939 static int
940 ata_acard_allocate(device_t dev)
941 {
942 struct ata_channel *ch = device_get_softc(dev);
943
944 /* setup the usual register normal pci style */
945 if (ata_pci_allocate(dev))
946 return ENXIO;
947
948 ch->hw.status = ata_acard_status;
949 return 0;
950 }
951
952 static int
953 ata_acard_status(device_t dev)
954 {
955 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
956 struct ata_channel *ch = device_get_softc(dev);
957
958 if (ctlr->chip->cfg1 == ATPOLD &&
959 ATA_LOCKING(ch->dev, ATA_LF_WHICH) != ch->unit)
960 return 0;
961 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
962 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
963
964 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
965 ATA_BMSTAT_INTERRUPT)
966 return 0;
967 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
968 DELAY(1);
969 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
970 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
971 DELAY(1);
972 }
973 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
974 DELAY(100);
975 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
976 return 0;
977 }
978 return 1;
979 }
980
981 static void
982 ata_acard_850_setmode(device_t dev, int mode)
983 {
984 device_t gparent = GRANDPARENT(dev);
985 struct ata_pci_controller *ctlr = device_get_softc(gparent);
986 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
987 struct ata_device *atadev = device_get_softc(dev);
988 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
989 int error;
990
991 mode = ata_limit_mode(dev, mode,
992 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
993
994 /* XXX SOS missing WDMA0+1 + PIO modes */
995 if (mode >= ATA_WDMA2) {
996 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
997 if (bootverbose)
998 device_printf(dev, "%ssetting %s on %s chip\n",
999 (error) ? "FAILURE " : "",
1000 ata_mode2str(mode), ctlr->chip->text);
1001 if (!error) {
1002 u_int8_t reg54 = pci_read_config(gparent, 0x54, 1);
1003
1004 reg54 &= ~(0x03 << (devno << 1));
1005 if (mode >= ATA_UDMA0)
1006 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1));
1007 pci_write_config(gparent, 0x54, reg54, 1);
1008 pci_write_config(gparent, 0x4a, 0xa6, 1);
1009 pci_write_config(gparent, 0x40 + (devno << 1), 0x0301, 2);
1010 atadev->mode = mode;
1011 return;
1012 }
1013 }
1014 /* we could set PIO mode timings, but we assume the BIOS did that */
1015 }
1016
1017 static void
1018 ata_acard_86X_setmode(device_t dev, int mode)
1019 {
1020 device_t gparent = GRANDPARENT(dev);
1021 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1022 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1023 struct ata_device *atadev = device_get_softc(dev);
1024 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1025 int error;
1026
1027
1028 mode = ata_limit_mode(dev, mode,
1029 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
1030
1031 mode = ata_check_80pin(dev, mode);
1032
1033 /* XXX SOS missing WDMA0+1 + PIO modes */
1034 if (mode >= ATA_WDMA2) {
1035 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1036 if (bootverbose)
1037 device_printf(dev, "%ssetting %s on %s chip\n",
1038 (error) ? "FAILURE " : "",
1039 ata_mode2str(mode), ctlr->chip->text);
1040 if (!error) {
1041 u_int16_t reg44 = pci_read_config(gparent, 0x44, 2);
1042
1043 reg44 &= ~(0x000f << (devno << 2));
1044 if (mode >= ATA_UDMA0)
1045 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2));
1046 pci_write_config(gparent, 0x44, reg44, 2);
1047 pci_write_config(gparent, 0x4a, 0xa6, 1);
1048 pci_write_config(gparent, 0x40 + devno, 0x31, 1);
1049 atadev->mode = mode;
1050 return;
1051 }
1052 }
1053 /* we could set PIO mode timings, but we assume the BIOS did that */
1054 }
1055
1056
1057 /*
1058 * Acer Labs Inc (ALI) chipset support functions
1059 */
1060 int
1061 ata_ali_ident(device_t dev)
1062 {
1063 struct ata_pci_controller *ctlr = device_get_softc(dev);
1064 static struct ata_chip_id ids[] =
1065 {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" },
1066 { ATA_ALI_5288, 0x00, 4, ALISATA, ATA_SA300, "M5288" },
1067 { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "M5287" },
1068 { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "M5281" },
1069 { ATA_ALI_5229, 0xc5, 0, ALINEW, ATA_UDMA6, "M5229" },
1070 { ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "M5229" },
1071 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "M5229" },
1072 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "M5229" },
1073 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "M5229" },
1074 { 0, 0, 0, 0, 0, 0}};
1075
1076 if (!(ctlr->chip = ata_match_chip(dev, ids)))
1077 return ENXIO;
1078
1079 ata_set_desc(dev);
1080 ctlr->chipinit = ata_ali_chipinit;
1081 return 0;
1082 }
1083
1084 static int
1085 ata_ali_chipinit(device_t dev)
1086 {
1087 struct ata_pci_controller *ctlr = device_get_softc(dev);
1088
1089 if (ata_setup_interrupt(dev))
1090 return ENXIO;
1091
1092 switch (ctlr->chip->cfg2) {
1093 case ALISATA:
1094 ctlr->channels = ctlr->chip->cfg1;
1095 ctlr->allocate = ata_ali_sata_allocate;
1096 ctlr->setmode = ata_sata_setmode;
1097
1098 /* AHCI mode is correctly supported only on the ALi 5288. */
1099 if ((ctlr->chip->chipid == ATA_ALI_5288) &&
1100 (ata_ahci_chipinit(dev) != ENXIO))
1101 return 0;
1102
1103 /* enable PCI interrupt */
1104 pci_write_config(dev, PCIR_COMMAND,
1105 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
1106 break;
1107
1108 case ALINEW:
1109 /* use device interrupt as byte count end */
1110 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
1111
1112 /* enable cable detection and UDMA support on newer chips */
1113 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1);
1114
1115 /* enable ATAPI UDMA mode */
1116 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1);
1117
1118 /* only chips with revision > 0xc4 can do 48bit DMA */
1119 if (ctlr->chip->chiprev <= 0xc4)
1120 device_printf(dev,
1121 "using PIO transfers above 137GB as workaround for "
1122 "48bit DMA access bug, expect reduced performance\n");
1123 ctlr->allocate = ata_ali_allocate;
1124 ctlr->reset = ata_ali_reset;
1125 ctlr->setmode = ata_ali_setmode;
1126 break;
1127
1128 case ALIOLD:
1129 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
1130 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
1131 ctlr->setmode = ata_ali_setmode;
1132 break;
1133 }
1134 return 0;
1135 }
1136
1137 static int
1138 ata_ali_allocate(device_t dev)
1139 {
1140 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1141 struct ata_channel *ch = device_get_softc(dev);
1142
1143 /* setup the usual register normal pci style */
1144 if (ata_pci_allocate(dev))
1145 return ENXIO;
1146
1147 /* older chips can't do 48bit DMA transfers */
1148 if (ctlr->chip->chiprev <= 0xc4)
1149 ch->flags |= ATA_NO_48BIT_DMA;
1150
1151 return 0;
1152 }
1153
1154 static int
1155 ata_ali_sata_allocate(device_t dev)
1156 {
1157 device_t parent = device_get_parent(dev);
1158 struct ata_pci_controller *ctlr = device_get_softc(parent);
1159 struct ata_channel *ch = device_get_softc(dev);
1160 struct resource *io = NULL, *ctlio = NULL;
1161 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
1162 int i, rid;
1163
1164 rid = PCIR_BAR(0) + (unit01 ? 8 : 0);
1165 io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1166 if (!io)
1167 return ENXIO;
1168
1169 rid = PCIR_BAR(1) + (unit01 ? 8 : 0);
1170 ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1171 if (!ctlio) {
1172 bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io);
1173 return ENXIO;
1174 }
1175
1176 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
1177 ch->r_io[i].res = io;
1178 ch->r_io[i].offset = i + (unit10 ? 8 : 0);
1179 }
1180 ch->r_io[ATA_CONTROL].res = ctlio;
1181 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0);
1182 ch->r_io[ATA_IDX_ADDR].res = io;
1183 ata_default_registers(dev);
1184 if (ctlr->r_res1) {
1185 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
1186 ch->r_io[i].res = ctlr->r_res1;
1187 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
1188 }
1189 }
1190 ch->flags |= ATA_NO_SLAVE;
1191
1192 /* XXX SOS PHY handling awkward in ALI chip not supported yet */
1193 ata_pci_hw(dev);
1194 return 0;
1195 }
1196
1197 static void
1198 ata_ali_reset(device_t dev)
1199 {
1200 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1201 struct ata_channel *ch = device_get_softc(dev);
1202 device_t *children;
1203 int nchildren, i;
1204
1205 ata_generic_reset(dev);
1206
1207 /*
1208 * workaround for datacorruption bug found on at least SUN Blade-100
1209 * find the ISA function on the southbridge and disable then enable
1210 * the ATA channel tristate buffer
1211 */
1212 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) {
1213 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) {
1214 for (i = 0; i < nchildren; i++) {
1215 if (pci_get_devid(children[i]) == ATA_ALI_1533) {
1216 pci_write_config(children[i], 0x58,
1217 pci_read_config(children[i], 0x58, 1) &
1218 ~(0x04 << ch->unit), 1);
1219 pci_write_config(children[i], 0x58,
1220 pci_read_config(children[i], 0x58, 1) |
1221 (0x04 << ch->unit), 1);
1222 break;
1223 }
1224 }
1225 free(children, M_TEMP);
1226 }
1227 }
1228 }
1229
1230 static void
1231 ata_ali_setmode(device_t dev, int mode)
1232 {
1233 device_t gparent = GRANDPARENT(dev);
1234 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1235 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1236 struct ata_device *atadev = device_get_softc(dev);
1237 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1238 int error;
1239
1240 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1241
1242 if (ctlr->chip->cfg2 & ALINEW) {
1243 if (mode > ATA_UDMA2 &&
1244 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) {
1245 ata_print_cable(dev, "controller");
1246 mode = ATA_UDMA2;
1247 }
1248 }
1249 else
1250 mode = ata_check_80pin(dev, mode);
1251
1252 if (ctlr->chip->cfg2 & ALIOLD) {
1253 /* doesn't support ATAPI DMA on write */
1254 ch->flags |= ATA_ATAPI_DMA_RO;
1255 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) {
1256 /* doesn't support ATAPI DMA on two ATAPI devices */
1257 device_printf(dev, "two atapi devices on this channel, no DMA\n");
1258 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1259 }
1260 }
1261
1262 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1263
1264 if (bootverbose)
1265 device_printf(dev, "%ssetting %s on %s chip\n",
1266 (error) ? "FAILURE " : "",
1267 ata_mode2str(mode), ctlr->chip->text);
1268 if (!error) {
1269 if (mode >= ATA_UDMA0) {
1270 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d};
1271 u_int32_t word54 = pci_read_config(gparent, 0x54, 4);
1272
1273 word54 &= ~(0x000f000f << (devno << 2));
1274 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
1275 pci_write_config(gparent, 0x54, word54, 4);
1276 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1277 0x00310001, 4);
1278 }
1279 else {
1280 u_int32_t piotimings[] =
1281 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
1282 0x00310001, 0x00440001, 0x00330001, 0x00310001};
1283
1284 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) &
1285 ~(0x0008000f << (devno << 2)), 4);
1286 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1287 piotimings[ata_mode2idx(mode)], 4);
1288 }
1289 atadev->mode = mode;
1290 }
1291 }
1292
1293
1294 /*
1295 * American Micro Devices (AMD) chipset support functions
1296 */
1297 int
1298 ata_amd_ident(device_t dev)
1299 {
1300 struct ata_pci_controller *ctlr = device_get_softc(dev);
1301 static struct ata_chip_id ids[] =
1302 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "756" },
1303 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "766" },
1304 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "768" },
1305 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "8111" },
1306 { ATA_AMD5536, 0x00, AMDNVIDIA, 0x00, ATA_UDMA5, "CS5536" },
1307 { 0, 0, 0, 0, 0, 0}};
1308
1309 if (!(ctlr->chip = ata_match_chip(dev, ids)))
1310 return ENXIO;
1311
1312 ata_set_desc(dev);
1313 ctlr->chipinit = ata_amd_chipinit;
1314 return 0;
1315 }
1316
1317 static int
1318 ata_amd_chipinit(device_t dev)
1319 {
1320 struct ata_pci_controller *ctlr = device_get_softc(dev);
1321
1322 if (ata_setup_interrupt(dev))
1323 return ENXIO;
1324
1325 /* disable/set prefetch, postwrite */
1326 if (ctlr->chip->cfg2 & AMDBUG)
1327 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1);
1328 else
1329 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
1330
1331 ctlr->setmode = ata_via_family_setmode;
1332 return 0;
1333 }
1334
1335
1336 /*
1337 * ATI chipset support functions
1338 */
1339 int
1340 ata_ati_ident(device_t dev)
1341 {
1342 struct ata_pci_controller *ctlr = device_get_softc(dev);
1343 static struct ata_chip_id ids[] =
1344 {{ ATA_ATI_IXP200, 0x00, 0, ATIPATA, ATA_UDMA5, "IXP200" },
1345 { ATA_ATI_IXP300, 0x00, 0, ATIPATA, ATA_UDMA6, "IXP300" },
1346 { ATA_ATI_IXP300_S1, 0x00, 0, ATISATA, ATA_SA150, "IXP300" },
1347 { ATA_ATI_IXP400, 0x00, 0, ATIPATA, ATA_UDMA6, "IXP400" },
1348 { ATA_ATI_IXP400_S1, 0x00, 0, ATISATA, ATA_SA150, "IXP400" },
1349 { ATA_ATI_IXP400_S2, 0x00, 0, ATISATA, ATA_SA150, "IXP400" },
1350 { ATA_ATI_IXP600, 0x00, 0, ATIPATA, ATA_UDMA6, "IXP600" },
1351 { ATA_ATI_IXP600_S1, 0x00, 0, ATIAHCI, ATA_SA300, "IXP600" },
1352 { ATA_ATI_IXP700, 0x00, 0, ATIPATA, ATA_UDMA6, "IXP700" },
1353 { ATA_ATI_IXP700_S1, 0x00, 0, ATIAHCI, ATA_SA300, "IXP700" },
1354 { 0, 0, 0, 0, 0, 0}};
1355
1356 if (!(ctlr->chip = ata_match_chip(dev, ids)))
1357 return ENXIO;
1358
1359 ata_set_desc(dev);
1360
1361 switch (ctlr->chip->cfg2) {
1362 case ATIPATA:
1363 ctlr->chipinit = ata_ati_chipinit;
1364 break;
1365 case ATISATA:
1366 /* the ATI SATA controller is actually a SiI 3112 controller */
1367 ctlr->chip->cfg1 = SIIMEMIO;
1368 ctlr->chipinit = ata_sii_chipinit;
1369 break;
1370 case ATIAHCI:
1371 ctlr->chipinit = ata_ahci_chipinit;
1372 break;
1373 }
1374 return 0;
1375 }
1376
1377 static int
1378 ata_ati_chipinit(device_t dev)
1379 {
1380 struct ata_pci_controller *ctlr = device_get_softc(dev);
1381
1382 if (ata_setup_interrupt(dev))
1383 return ENXIO;
1384
1385 /* IXP600 & IXP700 only have 1 PATA channel */
1386 if ((ctlr->chip->chipid == ATA_ATI_IXP600) ||
1387 (ctlr->chip->chipid == ATA_ATI_IXP700))
1388 ctlr->channels = 1;
1389
1390 ctlr->setmode = ata_ati_setmode;
1391 return 0;
1392 }
1393
1394 static void
1395 ata_ati_setmode(device_t dev, int mode)
1396 {
1397 device_t gparent = GRANDPARENT(dev);
1398 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1399 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1400 struct ata_device *atadev = device_get_softc(dev);
1401 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1402 int offset = (devno ^ 0x01) << 3;
1403 int error;
1404 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1405 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1406 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
1407
1408 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1409
1410 mode = ata_check_80pin(dev, mode);
1411
1412 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1413
1414 if (bootverbose)
1415 device_printf(dev, "%ssetting %s on %s chip\n",
1416 (error) ? "FAILURE " : "",
1417 ata_mode2str(mode), ctlr->chip->text);
1418 if (!error) {
1419 if (mode >= ATA_UDMA0) {
1420 pci_write_config(gparent, 0x56,
1421 (pci_read_config(gparent, 0x56, 2) &
1422 ~(0xf << (devno << 2))) |
1423 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
1424 pci_write_config(gparent, 0x54,
1425 pci_read_config(gparent, 0x54, 1) |
1426 (0x01 << devno), 1);
1427 pci_write_config(gparent, 0x44,
1428 (pci_read_config(gparent, 0x44, 4) &
1429 ~(0xff << offset)) |
1430 (dmatimings[2] << offset), 4);
1431 }
1432 else if (mode >= ATA_WDMA0) {
1433 pci_write_config(gparent, 0x54,
1434 pci_read_config(gparent, 0x54, 1) &
1435 ~(0x01 << devno), 1);
1436 pci_write_config(gparent, 0x44,
1437 (pci_read_config(gparent, 0x44, 4) &
1438 ~(0xff << offset)) |
1439 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
1440 }
1441 else
1442 pci_write_config(gparent, 0x54,
1443 pci_read_config(gparent, 0x54, 1) &
1444 ~(0x01 << devno), 1);
1445
1446 pci_write_config(gparent, 0x4a,
1447 (pci_read_config(gparent, 0x4a, 2) &
1448 ~(0xf << (devno << 2))) |
1449 (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2);
1450 pci_write_config(gparent, 0x40,
1451 (pci_read_config(gparent, 0x40, 4) &
1452 ~(0xff << offset)) |
1453 (piotimings[ata_mode2idx(mode)] << offset), 4);
1454 atadev->mode = mode;
1455 }
1456 }
1457
1458
1459 /*
1460 * Cyrix chipset support functions
1461 */
1462 int
1463 ata_cyrix_ident(device_t dev)
1464 {
1465 struct ata_pci_controller *ctlr = device_get_softc(dev);
1466
1467 if (pci_get_devid(dev) == ATA_CYRIX_5530) {
1468 device_set_desc(dev, "Cyrix 5530 ATA33 controller");
1469 ctlr->chipinit = ata_cyrix_chipinit;
1470 return 0;
1471 }
1472 return ENXIO;
1473 }
1474
1475 static int
1476 ata_cyrix_chipinit(device_t dev)
1477 {
1478 struct ata_pci_controller *ctlr = device_get_softc(dev);
1479
1480 if (ata_setup_interrupt(dev))
1481 return ENXIO;
1482
1483 if (ctlr->r_res1)
1484 ctlr->setmode = ata_cyrix_setmode;
1485 else
1486 ctlr->setmode = ata_generic_setmode;
1487 return 0;
1488 }
1489
1490 static void
1491 ata_cyrix_setmode(device_t dev, int mode)
1492 {
1493 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1494 struct ata_device *atadev = device_get_softc(dev);
1495 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1496 u_int32_t piotiming[] =
1497 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
1498 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
1499 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
1500 int error;
1501
1502 ch->dma->alignment = 16;
1503 ch->dma->max_iosize = 64 * DEV_BSIZE;
1504
1505 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
1506
1507 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1508
1509 if (bootverbose)
1510 device_printf(dev, "%ssetting %s on Cyrix chip\n",
1511 (error) ? "FAILURE " : "", ata_mode2str(mode));
1512 if (!error) {
1513 if (mode >= ATA_UDMA0) {
1514 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1515 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]);
1516 }
1517 else if (mode >= ATA_WDMA0) {
1518 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1519 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]);
1520 }
1521 else {
1522 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1523 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]);
1524 }
1525 atadev->mode = mode;
1526 }
1527 }
1528
1529
1530 /*
1531 * Cypress chipset support functions
1532 */
1533 int
1534 ata_cypress_ident(device_t dev)
1535 {
1536 struct ata_pci_controller *ctlr = device_get_softc(dev);
1537
1538 /*
1539 * the Cypress chip is a mess, it contains two ATA functions, but
1540 * both channels are visible on the first one.
1541 * simply ignore the second function for now, as the right
1542 * solution (ignoring the second channel on the first function)
1543 * doesn't work with the crappy ATA interrupt setup on the alpha.
1544 */
1545 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 &&
1546 pci_get_function(dev) == 1 &&
1547 pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
1548 device_set_desc(dev, "Cypress 82C693 ATA controller");
1549 ctlr->chipinit = ata_cypress_chipinit;
1550 return 0;
1551 }
1552 return ENXIO;
1553 }
1554
1555 static int
1556 ata_cypress_chipinit(device_t dev)
1557 {
1558 struct ata_pci_controller *ctlr = device_get_softc(dev);
1559
1560 if (ata_setup_interrupt(dev))
1561 return ENXIO;
1562
1563 ctlr->setmode = ata_cypress_setmode;
1564 return 0;
1565 }
1566
1567 static void
1568 ata_cypress_setmode(device_t dev, int mode)
1569 {
1570 device_t gparent = GRANDPARENT(dev);
1571 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1572 struct ata_device *atadev = device_get_softc(dev);
1573 int error;
1574
1575 mode = ata_limit_mode(dev, mode, ATA_WDMA2);
1576
1577 /* XXX SOS missing WDMA0+1 + PIO modes */
1578 if (mode == ATA_WDMA2) {
1579 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1580 if (bootverbose)
1581 device_printf(dev, "%ssetting WDMA2 on Cypress chip\n",
1582 error ? "FAILURE " : "");
1583 if (!error) {
1584 pci_write_config(gparent, ch->unit ? 0x4e : 0x4c, 0x2020, 2);
1585 atadev->mode = mode;
1586 return;
1587 }
1588 }
1589 /* we could set PIO mode timings, but we assume the BIOS did that */
1590 }
1591
1592
1593 /*
1594 * HighPoint chipset support functions
1595 */
1596 int
1597 ata_highpoint_ident(device_t dev)
1598 {
1599 struct ata_pci_controller *ctlr = device_get_softc(dev);
1600 struct ata_chip_id *idx;
1601 static struct ata_chip_id ids[] =
1602 {{ ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HPT374" },
1603 { ATA_HPT372, 0x02, HPT372, 0x00, ATA_UDMA6, "HPT372N" },
1604 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1605 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT371" },
1606 { ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1607 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HPT370" },
1608 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HPT368" },
1609 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HPT366" },
1610 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT302" },
1611 { 0, 0, 0, 0, 0, 0}};
1612 char buffer[64];
1613
1614 if (!(idx = ata_match_chip(dev, ids)))
1615 return ENXIO;
1616
1617 strcpy(buffer, "HighPoint ");
1618 strcat(buffer, idx->text);
1619 if (idx->cfg1 == HPT374) {
1620 if (pci_get_function(dev) == 0)
1621 strcat(buffer, " (channel 0+1)");
1622 if (pci_get_function(dev) == 1)
1623 strcat(buffer, " (channel 2+3)");
1624 }
1625 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
1626 device_set_desc_copy(dev, buffer);
1627 ctlr->chip = idx;
1628 ctlr->chipinit = ata_highpoint_chipinit;
1629 return 0;
1630 }
1631
1632 static int
1633 ata_highpoint_chipinit(device_t dev)
1634 {
1635 struct ata_pci_controller *ctlr = device_get_softc(dev);
1636
1637 if (ata_setup_interrupt(dev))
1638 return ENXIO;
1639
1640 if (ctlr->chip->cfg2 == HPTOLD) {
1641 /* disable interrupt prediction */
1642 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
1643 }
1644 else {
1645 /* disable interrupt prediction */
1646 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
1647 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
1648
1649 /* enable interrupts */
1650 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
1651
1652 /* set clocks etc */
1653 if (ctlr->chip->cfg1 < HPT372)
1654 pci_write_config(dev, 0x5b, 0x22, 1);
1655 else
1656 pci_write_config(dev, 0x5b,
1657 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
1658 }
1659 ctlr->allocate = ata_highpoint_allocate;
1660 ctlr->setmode = ata_highpoint_setmode;
1661 return 0;
1662 }
1663
1664 static int
1665 ata_highpoint_allocate(device_t dev)
1666 {
1667 struct ata_channel *ch = device_get_softc(dev);
1668
1669 /* setup the usual register normal pci style */
1670 if (ata_pci_allocate(dev))
1671 return ENXIO;
1672
1673 ch->flags |= ATA_ALWAYS_DMASTAT;
1674 return 0;
1675 }
1676
1677 static void
1678 ata_highpoint_setmode(device_t dev, int mode)
1679 {
1680 device_t gparent = GRANDPARENT(dev);
1681 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1682 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1683 struct ata_device *atadev = device_get_softc(dev);
1684 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1685 int error;
1686 u_int32_t timings33[][4] = {
1687 /* HPT366 HPT370 HPT372 HPT374 mode */
1688 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
1689 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
1690 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
1691 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
1692 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
1693 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
1694 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
1695 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
1696 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */
1697 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */
1698 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */
1699 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */
1700 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */
1701 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */
1702 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */
1703 };
1704
1705 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1706
1707 if (ctlr->chip->cfg1 == HPT366 && ata_atapi(dev))
1708 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1709
1710 mode = ata_highpoint_check_80pin(dev, mode);
1711
1712 /*
1713 * most if not all HPT chips cant really handle that the device is
1714 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to
1715 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance
1716 */
1717 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
1718 ata_limit_mode(dev, mode, ATA_UDMA5));
1719 if (bootverbose)
1720 device_printf(dev, "%ssetting %s on HighPoint chip\n",
1721 (error) ? "FAILURE " : "", ata_mode2str(mode));
1722 if (!error)
1723 pci_write_config(gparent, 0x40 + (devno << 2),
1724 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
1725 atadev->mode = mode;
1726 }
1727
1728 static int
1729 ata_highpoint_check_80pin(device_t dev, int mode)
1730 {
1731 device_t gparent = GRANDPARENT(dev);
1732 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1733 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1734 u_int8_t reg, val, res;
1735
1736 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(gparent) == 1) {
1737 reg = ch->unit ? 0x57 : 0x53;
1738 val = pci_read_config(gparent, reg, 1);
1739 pci_write_config(gparent, reg, val | 0x80, 1);
1740 }
1741 else {
1742 reg = 0x5b;
1743 val = pci_read_config(gparent, reg, 1);
1744 pci_write_config(gparent, reg, val & 0xfe, 1);
1745 }
1746 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2);
1747 pci_write_config(gparent, reg, val, 1);
1748
1749 if (mode > ATA_UDMA2 && res) {
1750 ata_print_cable(dev, "controller");
1751 mode = ATA_UDMA2;
1752 }
1753 return mode;
1754 }
1755
1756
1757 /*
1758 * Intel chipset support functions
1759 */
1760 int
1761 ata_intel_ident(device_t dev)
1762 {
1763 struct ata_pci_controller *ctlr = device_get_softc(dev);
1764 static struct ata_chip_id ids[] =
1765 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "PIIX" },
1766 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "PIIX3" },
1767 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1768 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1769 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1770 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "ICH0" },
1771 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "ICH" },
1772 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "ICH" },
1773 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "ICH2" },
1774 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "ICH2" },
1775 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "ICH3" },
1776 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "ICH3" },
1777 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "ICH4" },
1778 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "ICH4" },
1779 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "ICH5" },
1780 { ATA_I82801EB_S1, 0, 0, 0x00, ATA_SA150, "ICH5" },
1781 { ATA_I82801EB_R1, 0, 0, 0x00, ATA_SA150, "ICH5" },
1782 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "6300ESB" },
1783 { ATA_I6300ESB_S1, 0, 0, 0x00, ATA_SA150, "6300ESB" },
1784 { ATA_I6300ESB_R1, 0, 0, 0x00, ATA_SA150, "6300ESB" },
1785 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "ICH6" },
1786 { ATA_I82801FB_S1, 0, AHCI, 0x00, ATA_SA150, "ICH6" },
1787 { ATA_I82801FB_R1, 0, AHCI, 0x00, ATA_SA150, "ICH6" },
1788 { ATA_I82801FBM, 0, AHCI, 0x00, ATA_SA150, "ICH6M" },
1789 { ATA_I82801GB, 0, 0, 0x00, ATA_UDMA5, "ICH7" },
1790 { ATA_I82801GB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1791 { ATA_I82801GB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1792 { ATA_I82801GB_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1793 { ATA_I82801GBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1794 { ATA_I82801GBM_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1795 { ATA_I82801GBM_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1796 { ATA_I63XXESB2, 0, 0, 0x00, ATA_UDMA5, "63XXESB2" },
1797 { ATA_I63XXESB2_S1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1798 { ATA_I63XXESB2_S2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1799 { ATA_I63XXESB2_R1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1800 { ATA_I63XXESB2_R2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1801 { ATA_I82801HB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1802 { ATA_I82801HB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1803 { ATA_I82801HB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1804 { ATA_I82801HB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1805 { ATA_I82801HB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1806 { ATA_I82801HBM, 0, 0, 0x00, ATA_UDMA5, "ICH8M" },
1807 { ATA_I82801HBM_S1, 0, 0, 0x00, ATA_SA150, "ICH8M" },
1808 { ATA_I82801HBM_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8M" },
1809 { ATA_I82801HBM_S3, 0, AHCI, 0x00, ATA_SA300, "ICH8M" },
1810 { ATA_I82801IB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1811 { ATA_I82801IB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1812 { ATA_I82801IB_AH2, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1813 { ATA_I82801IB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1814 { ATA_I82801IB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1815 { ATA_I82801IB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1816 { ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" },
1817 { 0, 0, 0, 0, 0, 0}};
1818
1819 if (!(ctlr->chip = ata_match_chip(dev, ids)))
1820 return ENXIO;
1821
1822 ata_set_desc(dev);
1823 ctlr->chipinit = ata_intel_chipinit;
1824 return 0;
1825 }
1826
1827 static int
1828 ata_intel_chipinit(device_t dev)
1829 {
1830 struct ata_pci_controller *ctlr = device_get_softc(dev);
1831
1832 if (ata_setup_interrupt(dev))
1833 return ENXIO;
1834
1835 /* good old PIIX needs special treatment (not implemented) */
1836 if (ctlr->chip->chipid == ATA_I82371FB) {
1837 ctlr->setmode = ata_intel_old_setmode;
1838 }
1839
1840 /* the intel 31244 needs special care if in DPA mode */
1841 else if (ctlr->chip->chipid == ATA_I31244) {
1842 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) {
1843 ctlr->r_type2 = SYS_RES_MEMORY;
1844 ctlr->r_rid2 = PCIR_BAR(0);
1845 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1846 &ctlr->r_rid2,
1847 RF_ACTIVE)))
1848 return ENXIO;
1849 ctlr->channels = 4;
1850 ctlr->allocate = ata_intel_31244_allocate;
1851 ctlr->reset = ata_intel_31244_reset;
1852 }
1853 ctlr->setmode = ata_sata_setmode;
1854 }
1855
1856 /* non SATA intel chips goes here */
1857 else if (ctlr->chip->max_dma < ATA_SA150) {
1858 ctlr->allocate = ata_intel_allocate;
1859 ctlr->setmode = ata_intel_new_setmode;
1860 }
1861
1862 /* SATA parts can be either compat or AHCI */
1863 else {
1864 /* force all ports active "the legacy way" */
1865 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2);
1866
1867 ctlr->allocate = ata_intel_allocate;
1868 ctlr->reset = ata_intel_reset;
1869
1870 /*
1871 * if we have AHCI capability and AHCI or RAID mode enabled
1872 * in BIOS we try for AHCI mode
1873 */
1874 if ((ctlr->chip->cfg1 == AHCI) &&
1875 (pci_read_config(dev, 0x90, 1) & 0xc0) &&
1876 (ata_ahci_chipinit(dev) != ENXIO))
1877 return 0;
1878
1879 /* if BAR(5) is IO it should point to SATA interface registers */
1880 ctlr->r_type2 = SYS_RES_IOPORT;
1881 ctlr->r_rid2 = PCIR_BAR(5);
1882 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1883 &ctlr->r_rid2, RF_ACTIVE)))
1884 ctlr->setmode = ata_intel_sata_setmode;
1885 else
1886 ctlr->setmode = ata_sata_setmode;
1887
1888 /* enable PCI interrupt */
1889 pci_write_config(dev, PCIR_COMMAND,
1890 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
1891 }
1892 return 0;
1893 }
1894
1895 static int
1896 ata_intel_allocate(device_t dev)
1897 {
1898 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1899 struct ata_channel *ch = device_get_softc(dev);
1900
1901 /* setup the usual register normal pci style */
1902 if (ata_pci_allocate(dev))
1903 return ENXIO;
1904
1905 /* if r_res2 is valid it points to SATA interface registers */
1906 if (ctlr->r_res2) {
1907 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
1908 ch->r_io[ATA_IDX_ADDR].offset = 0x00;
1909 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2;
1910 ch->r_io[ATA_IDX_DATA].offset = 0x04;
1911 }
1912
1913 ch->flags |= ATA_ALWAYS_DMASTAT;
1914 return 0;
1915 }
1916
1917 static void
1918 ata_intel_reset(device_t dev)
1919 {
1920 device_t parent = device_get_parent(dev);
1921 struct ata_pci_controller *ctlr = device_get_softc(parent);
1922 struct ata_channel *ch = device_get_softc(dev);
1923 int mask, timeout;
1924
1925 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */
1926 if (ctlr->chip->cfg1) {
1927 mask = (0x0005 << ch->unit);
1928 }
1929 else {
1930 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */
1931 if (pci_read_config(parent, 0x90, 1) & 0x04)
1932 mask = 0x0003;
1933 else {
1934 mask = (0x0001 << ch->unit);
1935 /* XXX SOS should be in intel_allocate if we grow it */
1936 ch->flags |= ATA_NO_SLAVE;
1937 }
1938 }
1939 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2);
1940 DELAY(10);
1941 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2);
1942
1943 /* wait up to 1 sec for "connect well" */
1944 for (timeout = 0; timeout < 100 ; timeout++) {
1945 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) &&
1946 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff))
1947 break;
1948 ata_udelay(10000);
1949 }
1950 ata_generic_reset(dev);
1951 }
1952
1953 static void
1954 ata_intel_old_setmode(device_t dev, int mode)
1955 {
1956 /* NOT YET */
1957 }
1958
1959 static void
1960 ata_intel_new_setmode(device_t dev, int mode)
1961 {
1962 device_t gparent = GRANDPARENT(dev);
1963 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1964 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1965 struct ata_device *atadev = device_get_softc(dev);
1966 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1967 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4);
1968 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1);
1969 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1);
1970 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2);
1971 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2);
1972 u_int32_t mask40 = 0, new40 = 0;
1973 u_int8_t mask44 = 0, new44 = 0;
1974 int error;
1975 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
1976 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
1977
1978 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1979
1980 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
1981 ata_print_cable(dev, "controller");
1982 mode = ATA_UDMA2;
1983 }
1984
1985 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1986
1987 if (bootverbose)
1988 device_printf(dev, "%ssetting %s on %s chip\n",
1989 (error) ? "FAILURE " : "",
1990 ata_mode2str(mode), ctlr->chip->text);
1991 if (error)
1992 return;
1993
1994 if (mode >= ATA_UDMA0) {
1995 pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2);
1996 pci_write_config(gparent, 0x4a,
1997 (reg4a & ~(0x3 << (devno << 2))) |
1998 ((0x01 + !(mode & 0x01)) << (devno << 2)), 2);
1999 }
2000 else {
2001 pci_write_config(gparent, 0x48, reg48 & ~(0x0001 << devno), 2);
2002 pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))), 2);
2003 }
2004 reg54 |= 0x0400;
2005 if (mode >= ATA_UDMA2)
2006 pci_write_config(gparent, 0x54, reg54 | (0x1 << devno), 2);
2007 else
2008 pci_write_config(gparent, 0x54, reg54 & ~(0x1 << devno), 2);
2009
2010 if (mode >= ATA_UDMA5)
2011 pci_write_config(gparent, 0x54, reg54 | (0x1000 << devno), 2);
2012 else
2013 pci_write_config(gparent, 0x54, reg54 & ~(0x1000 << devno), 2);
2014
2015 reg40 &= ~0x00ff00ff;
2016 reg40 |= 0x40774077;
2017
2018 if (atadev->unit == ATA_MASTER) {
2019 mask40 = 0x3300;
2020 new40 = timings[ata_mode2idx(mode)] << 8;
2021 }
2022 else {
2023 mask44 = 0x0f;
2024 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
2025 (timings[ata_mode2idx(mode)] & 0x03);
2026 }
2027 if (ch->unit) {
2028 mask40 <<= 16;
2029 new40 <<= 16;
2030 mask44 <<= 4;
2031 new44 <<= 4;
2032 }
2033 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4);
2034 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1);
2035
2036 atadev->mode = mode;
2037 }
2038
2039 static void
2040 ata_intel_sata_setmode(device_t dev, int mode)
2041 {
2042 struct ata_device *atadev = device_get_softc(dev);
2043
2044 if (atadev->param.satacapabilities != 0x0000 &&
2045 atadev->param.satacapabilities != 0xffff) {
2046
2047 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2048 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2049
2050 /* on some drives we need to set the transfer mode */
2051 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
2052 ata_limit_mode(dev, mode, ATA_UDMA6));
2053
2054 /* set ATA_SSTATUS register offset */
2055 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, devno * 0x100);
2056
2057 /* query SATA STATUS for the speed */
2058 if ((ATA_IDX_INL(ch, ATA_IDX_DATA) & ATA_SS_CONWELL_MASK) ==
2059 ATA_SS_CONWELL_GEN2)
2060 atadev->mode = ATA_SA300;
2061 else
2062 atadev->mode = ATA_SA150;
2063 }
2064 else {
2065 mode = ata_limit_mode(dev, mode, ATA_UDMA5);
2066 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2067 atadev->mode = mode;
2068 }
2069 }
2070
2071 static int
2072 ata_intel_31244_allocate(device_t dev)
2073 {
2074 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2075 struct ata_channel *ch = device_get_softc(dev);
2076 int i;
2077 int ch_offset;
2078
2079 ch_offset = 0x200 + ch->unit * 0x200;
2080
2081 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
2082 ch->r_io[i].res = ctlr->r_res2;
2083
2084 /* setup ATA registers */
2085 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
2086 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06;
2087 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
2088 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
2089 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
2090 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
2091 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
2092 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d;
2093 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04;
2094 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c;
2095 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28;
2096 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29;
2097
2098 /* setup DMA registers */
2099 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100;
2100 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104;
2101 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108;
2102
2103 /* setup SATA registers */
2104 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70;
2105 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72;
2106 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74;
2107
2108 ch->flags |= ATA_NO_SLAVE;
2109 ata_pci_hw(dev);
2110 ch->hw.status = ata_intel_31244_status;
2111 ch->hw.tf_write = ata_intel_31244_tf_write;
2112
2113 /* enable PHY state change interrupt */
2114 ATA_OUTL(ctlr->r_res2, 0x4,
2115 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3)));
2116 return 0;
2117 }
2118
2119 static int
2120 ata_intel_31244_status(device_t dev)
2121 {
2122 /* do we have any PHY events ? */
2123 ata_sata_phy_check_events(dev);
2124
2125 /* any drive action to take care of ? */
2126 return ata_pci_status(dev);
2127 }
2128
2129 static void
2130 ata_intel_31244_tf_write(struct ata_request *request)
2131 {
2132 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2133 struct ata_device *atadev = device_get_softc(request->dev);
2134
2135 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
2136 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
2137 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
2138 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) |
2139 (request->u.ata.lba & 0x00ff));
2140 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) |
2141 ((request->u.ata.lba >> 8) & 0x00ff));
2142 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) |
2143 ((request->u.ata.lba >> 16) & 0x00ff));
2144 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | atadev->unit);
2145 }
2146 else {
2147 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
2148 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
2149 if (atadev->flags & ATA_D_USE_CHS) {
2150 int heads, sectors;
2151
2152 if (atadev->param.atavalid & ATA_FLAG_54_58) {
2153 heads = atadev->param.current_heads;
2154 sectors = atadev->param.current_sectors;
2155 }
2156 else {
2157 heads = atadev->param.heads;
2158 sectors = atadev->param.sectors;
2159 }
2160 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
2161 ATA_IDX_OUTB(ch, ATA_CYL_LSB,
2162 (request->u.ata.lba / (sectors * heads)));
2163 ATA_IDX_OUTB(ch, ATA_CYL_MSB,
2164 (request->u.ata.lba / (sectors * heads)) >> 8);
2165 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit |
2166 (((request->u.ata.lba% (sectors * heads)) /
2167 sectors) & 0xf));
2168 }
2169 else {
2170 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
2171 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
2172 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
2173 ATA_IDX_OUTB(ch, ATA_DRIVE,
2174 ATA_D_IBM | ATA_D_LBA | atadev->unit |
2175 ((request->u.ata.lba >> 24) & 0x0f));
2176 }
2177 }
2178 }
2179
2180 static void
2181 ata_intel_31244_reset(device_t dev)
2182 {
2183 if (ata_sata_phy_reset(dev))
2184 ata_generic_reset(dev);
2185 }
2186
2187
2188 /*
2189 * Integrated Technology Express Inc. (ITE) chipset support functions
2190 */
2191 int
2192 ata_ite_ident(device_t dev)
2193 {
2194 struct ata_pci_controller *ctlr = device_get_softc(dev);
2195 static struct ata_chip_id ids[] =
2196 {{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" },
2197 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" },
2198 { 0, 0, 0, 0, 0, 0}};
2199
2200 if (!(ctlr->chip = ata_match_chip(dev, ids)))
2201 return ENXIO;
2202
2203 ata_set_desc(dev);
2204 ctlr->chipinit = ata_ite_chipinit;
2205 return 0;
2206 }
2207
2208 static int
2209 ata_ite_chipinit(device_t dev)
2210 {
2211 struct ata_pci_controller *ctlr = device_get_softc(dev);
2212
2213 if (ata_setup_interrupt(dev))
2214 return ENXIO;
2215
2216 ctlr->setmode = ata_ite_setmode;
2217
2218 /* set PCI mode and 66Mhz reference clock */
2219 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1);
2220
2221 /* set default active & recover timings */
2222 pci_write_config(dev, 0x54, 0x31, 1);
2223 pci_write_config(dev, 0x56, 0x31, 1);
2224 return 0;
2225 }
2226
2227 static void
2228 ata_ite_setmode(device_t dev, int mode)
2229 {
2230 device_t gparent = GRANDPARENT(dev);
2231 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2232 struct ata_device *atadev = device_get_softc(dev);
2233 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2234 int error;
2235
2236 /* correct the mode for what the HW supports */
2237 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2238
2239 /* check the CBLID bits for 80 conductor cable detection */
2240 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) &
2241 (ch->unit ? (1<<3) : (1<<2)))) {
2242 ata_print_cable(dev, "controller");
2243 mode = ATA_UDMA2;
2244 }
2245
2246 /* set the wanted mode on the device */
2247 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2248
2249 if (bootverbose)
2250 device_printf(dev, "%s setting %s on ITE8212F chip\n",
2251 (error) ? "failed" : "success", ata_mode2str(mode));
2252
2253 /* if the device accepted the mode change, setup the HW accordingly */
2254 if (!error) {
2255 if (mode >= ATA_UDMA0) {
2256 u_int8_t udmatiming[] =
2257 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
2258
2259 /* enable UDMA mode */
2260 pci_write_config(gparent, 0x50,
2261 pci_read_config(gparent, 0x50, 1) &
2262 ~(1 << (devno + 3)), 1);
2263
2264 /* set UDMA timing */
2265 pci_write_config(gparent,
2266 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit),
2267 udmatiming[mode & ATA_MODE_MASK], 1);
2268 }
2269 else {
2270 u_int8_t chtiming[] =
2271 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
2272
2273 /* disable UDMA mode */
2274 pci_write_config(gparent, 0x50,
2275 pci_read_config(gparent, 0x50, 1) |
2276 (1 << (devno + 3)), 1);
2277
2278 /* set active and recover timing (shared between master & slave) */
2279 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) <
2280 chtiming[ata_mode2idx(mode)])
2281 pci_write_config(gparent, 0x54 + (ch->unit << 2),
2282 chtiming[ata_mode2idx(mode)], 1);
2283 }
2284 atadev->mode = mode;
2285 }
2286 }
2287
2288
2289 /*
2290 * JMicron chipset support functions
2291 */
2292 int
2293 ata_jmicron_ident(device_t dev)
2294 {
2295 struct ata_pci_controller *ctlr = device_get_softc(dev);
2296 struct ata_chip_id *idx;
2297 static struct ata_chip_id ids[] =
2298 {{ ATA_JMB360, 0, 1, 0, ATA_SA300, "JMB360" },
2299 { ATA_JMB361, 0, 1, 1, ATA_SA300, "JMB361" },
2300 { ATA_JMB363, 0, 2, 1, ATA_SA300, "JMB363" },
2301 { ATA_JMB365, 0, 1, 2, ATA_SA300, "JMB365" },
2302 { ATA_JMB366, 0, 2, 2, ATA_SA300, "JMB366" },
2303 { ATA_JMB368, 0, 0, 1, ATA_UDMA6, "JMB368" },
2304 { 0, 0, 0, 0, 0, 0}};
2305 char buffer[64];
2306
2307 if (!(idx = ata_match_chip(dev, ids)))
2308 return ENXIO;
2309
2310 if ((pci_read_config(dev, 0xdf, 1) & 0x40) &&
2311 (pci_get_function(dev) == (pci_read_config(dev, 0x40, 1) & 0x02 >> 1)))
2312 sprintf(buffer, "JMicron %s %s controller",
2313 idx->text, ata_mode2str(ATA_UDMA6));
2314 else
2315 sprintf(buffer, "JMicron %s %s controller",
2316 idx->text, ata_mode2str(idx->max_dma));
2317 device_set_desc_copy(dev, buffer);
2318 ctlr->chip = idx;
2319 ctlr->chipinit = ata_jmicron_chipinit;
2320 return 0;
2321 }
2322
2323 static int
2324 ata_jmicron_chipinit(device_t dev)
2325 {
2326 struct ata_pci_controller *ctlr = device_get_softc(dev);
2327 int error;
2328
2329 if (ata_setup_interrupt(dev))
2330 return ENXIO;
2331
2332 /* do we have multiple PCI functions ? */
2333 if (pci_read_config(dev, 0xdf, 1) & 0x40) {
2334 /* are we on the AHCI part ? */
2335 if (ata_ahci_chipinit(dev) != ENXIO)
2336 return 0;
2337
2338 /* otherwise we are on the PATA part */
2339 ctlr->allocate = ata_pci_allocate;
2340 ctlr->reset = ata_generic_reset;
2341 ctlr->dmainit = ata_pci_dmainit;
2342 ctlr->setmode = ata_jmicron_setmode;
2343 ctlr->channels = ctlr->chip->cfg2;
2344 }
2345 else {
2346 /* set controller configuration to a combined setup we support */
2347 pci_write_config(dev, 0x40, 0x80c0a131, 4);
2348 pci_write_config(dev, 0x80, 0x01200000, 4);
2349
2350 if (ctlr->chip->cfg1 && (error = ata_ahci_chipinit(dev)))
2351 return error;
2352
2353 ctlr->allocate = ata_jmicron_allocate;
2354 ctlr->reset = ata_jmicron_reset;
2355 ctlr->dmainit = ata_jmicron_dmainit;
2356 ctlr->setmode = ata_jmicron_setmode;
2357
2358 /* set the number of HW channels */
2359 ctlr->channels = ctlr->chip->cfg1 + ctlr->chip->cfg2;
2360 }
2361 return 0;
2362 }
2363
2364 static int
2365 ata_jmicron_allocate(device_t dev)
2366 {
2367 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2368 struct ata_channel *ch = device_get_softc(dev);
2369 int error;
2370
2371 if (ch->unit >= ctlr->chip->cfg1) {
2372 ch->unit -= ctlr->chip->cfg1;
2373 error = ata_pci_allocate(dev);
2374 ch->unit += ctlr->chip->cfg1;
2375 }
2376 else
2377 error = ata_ahci_allocate(dev);
2378 return error;
2379 }
2380
2381 static void
2382 ata_jmicron_reset(device_t dev)
2383 {
2384 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2385 struct ata_channel *ch = device_get_softc(dev);
2386
2387 if (ch->unit >= ctlr->chip->cfg1)
2388 ata_generic_reset(dev);
2389 else
2390 ata_ahci_reset(dev);
2391 }
2392
2393 static void
2394 ata_jmicron_dmainit(device_t dev)
2395 {
2396 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2397 struct ata_channel *ch = device_get_softc(dev);
2398
2399 if (ch->unit >= ctlr->chip->cfg1)
2400 ata_pci_dmainit(dev);
2401 else
2402 ata_ahci_dmainit(dev);
2403 }
2404
2405 static void
2406 ata_jmicron_setmode(device_t dev, int mode)
2407 {
2408 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
2409 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2410
2411 if (pci_read_config(dev, 0xdf, 1) & 0x40 || ch->unit >= ctlr->chip->cfg1) {
2412 struct ata_device *atadev = device_get_softc(dev);
2413
2414 /* check for 80pin cable present */
2415 if (pci_read_config(dev, 0x40, 1) & 0x08)
2416 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
2417 else
2418 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2419
2420 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2421 atadev->mode = mode;
2422 }
2423 else
2424 ata_sata_setmode(dev, mode);
2425 }
2426
2427
2428 /*
2429 * Marvell chipset support functions
2430 */
2431 #define ATA_MV_HOST_BASE(ch) \
2432 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000)
2433 #define ATA_MV_EDMA_BASE(ch) \
2434 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000)
2435
2436 struct ata_marvell_response {
2437 u_int16_t tag;
2438 u_int8_t edma_status;
2439 u_int8_t dev_status;
2440 u_int32_t timestamp;
2441 };
2442
2443 struct ata_marvell_dma_prdentry {
2444 u_int32_t addrlo;
2445 u_int32_t count;
2446 u_int32_t addrhi;
2447 u_int32_t reserved;
2448 };
2449
2450 int
2451 ata_marvell_ident(device_t dev)
2452 {
2453 struct ata_pci_controller *ctlr = device_get_softc(dev);
2454 static struct ata_chip_id ids[] =
2455 {{ ATA_M88SX5040, 0, 4, MV50XX, ATA_SA150, "88SX5040" },
2456 { ATA_M88SX5041, 0, 4, MV50XX, ATA_SA150, "88SX5041" },
2457 { ATA_M88SX5080, 0, 8, MV50XX, ATA_SA150, "88SX5080" },
2458 { ATA_M88SX5081, 0, 8, MV50XX, ATA_SA150, "88SX5081" },
2459 { ATA_M88SX6041, 0, 4, MV60XX, ATA_SA300, "88SX6041" },
2460 { ATA_M88SX6081, 0, 8, MV60XX, ATA_SA300, "88SX6081" },
2461 { ATA_M88SX6101, 0, 1, MV61XX, ATA_UDMA6, "88SX6101" },
2462 { ATA_M88SX6145, 0, 2, MV61XX, ATA_UDMA6, "88SX6145" },
2463 { 0, 0, 0, 0, 0, 0}};
2464
2465 if (!(ctlr->chip = ata_match_chip(dev, ids)))
2466 return ENXIO;
2467
2468 ata_set_desc(dev);
2469
2470 switch (ctlr->chip->cfg2) {
2471 case MV50XX:
2472 case MV60XX:
2473 ctlr->chipinit = ata_marvell_edma_chipinit;
2474 break;
2475 case MV61XX:
2476 ctlr->chipinit = ata_marvell_pata_chipinit;
2477 break;
2478 }
2479 return 0;
2480 }
2481
2482 static int
2483 ata_marvell_pata_chipinit(device_t dev)
2484 {
2485 struct ata_pci_controller *ctlr = device_get_softc(dev);
2486
2487 if (ata_setup_interrupt(dev))
2488 return ENXIO;
2489
2490 ctlr->allocate = ata_marvell_pata_allocate;
2491 ctlr->setmode = ata_marvell_pata_setmode;
2492 ctlr->channels = ctlr->chip->cfg1;
2493 return 0;
2494 }
2495
2496 static int
2497 ata_marvell_pata_allocate(device_t dev)
2498 {
2499 struct ata_channel *ch = device_get_softc(dev);
2500
2501 /* setup the usual register normal pci style */
2502 if (ata_pci_allocate(dev))
2503 return ENXIO;
2504
2505 /* dont use 32 bit PIO transfers */
2506 ch->flags |= ATA_USE_16BIT;
2507
2508 return 0;
2509 }
2510
2511 static void
2512 ata_marvell_pata_setmode(device_t dev, int mode)
2513 {
2514 device_t gparent = GRANDPARENT(dev);
2515 struct ata_pci_controller *ctlr = device_get_softc(gparent);
2516 struct ata_device *atadev = device_get_softc(dev);
2517
2518 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
2519 mode = ata_check_80pin(dev, mode);
2520 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2521 atadev->mode = mode;
2522 }
2523
2524 static int
2525 ata_marvell_edma_chipinit(device_t dev)
2526 {
2527 struct ata_pci_controller *ctlr = device_get_softc(dev);
2528
2529 if (ata_setup_interrupt(dev))
2530 return ENXIO;
2531
2532 ctlr->r_type1 = SYS_RES_MEMORY;
2533 ctlr->r_rid1 = PCIR_BAR(0);
2534 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
2535 &ctlr->r_rid1, RF_ACTIVE)))
2536 return ENXIO;
2537
2538 /* mask all host controller interrupts */
2539 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000);
2540
2541 /* mask all PCI interrupts */
2542 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000);
2543
2544 ctlr->allocate = ata_marvell_edma_allocate;
2545 ctlr->reset = ata_marvell_edma_reset;
2546 ctlr->dmainit = ata_marvell_edma_dmainit;
2547 ctlr->setmode = ata_sata_setmode;
2548 ctlr->channels = ctlr->chip->cfg1;
2549
2550 /* clear host controller interrupts */
2551 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000);
2552 if (ctlr->chip->cfg1 > 4)
2553 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000);
2554
2555 /* clear PCI interrupts */
2556 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000);
2557
2558 /* unmask PCI interrupts we want */
2559 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff);
2560
2561 /* unmask host controller interrupts we want */
2562 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ |
2563 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25));
2564
2565 /* enable PCI interrupt */
2566 pci_write_config(dev, PCIR_COMMAND,
2567 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
2568 return 0;
2569 }
2570
2571 static int
2572 ata_marvell_edma_allocate(device_t dev)
2573 {
2574 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2575 struct ata_channel *ch = device_get_softc(dev);
2576 u_int64_t work = ch->dma->work_bus;
2577 int i;
2578
2579 /* clear work area */
2580 bzero(ch->dma->work, 1024+256);
2581
2582 /* set legacy ATA resources */
2583 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
2584 ch->r_io[i].res = ctlr->r_res1;
2585 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch);
2586 }
2587 ch->r_io[ATA_CONTROL].res = ctlr->r_res1;
2588 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch);
2589 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1;
2590 ata_default_registers(dev);
2591
2592 /* set SATA resources */
2593 switch (ctlr->chip->cfg2) {
2594 case MV50XX:
2595 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2596 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch);
2597 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2598 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch);
2599 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2600 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch);
2601 break;
2602 case MV60XX:
2603 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2604 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch);
2605 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2606 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch);
2607 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2608 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch);
2609 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1;
2610 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch);
2611 break;
2612 }
2613
2614 ch->flags |= ATA_NO_SLAVE;
2615 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */
2616 ata_generic_hw(dev);
2617 ch->hw.begin_transaction = ata_marvell_edma_begin_transaction;
2618 ch->hw.end_transaction = ata_marvell_edma_end_transaction;
2619 ch->hw.status = ata_marvell_edma_status;
2620
2621 /* disable the EDMA machinery */
2622 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2623 DELAY(100000); /* SOS should poll for disabled */
2624
2625 /* set configuration to non-queued 128b read transfers stop on error */
2626 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13));
2627
2628 /* request queue base high */
2629 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32);
2630
2631 /* request queue in ptr */
2632 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
2633
2634 /* request queue out ptr */
2635 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0);
2636
2637 /* response queue base high */
2638 work += 1024;
2639 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32);
2640
2641 /* response queue in ptr */
2642 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0);
2643
2644 /* response queue out ptr */
2645 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
2646
2647 /* clear SATA error register */
2648 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2649
2650 /* clear any outstanding error interrupts */
2651 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2652
2653 /* unmask all error interrupts */
2654 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
2655
2656 /* enable EDMA machinery */
2657 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2658 return 0;
2659 }
2660
2661 static int
2662 ata_marvell_edma_status(device_t dev)
2663 {
2664 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2665 struct ata_channel *ch = device_get_softc(dev);
2666 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60);
2667 int shift = (ch->unit << 1) + (ch->unit > 3);
2668
2669 if (cause & (1 << shift)) {
2670
2671 /* clear interrupt(s) */
2672 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2673
2674 /* do we have any PHY events ? */
2675 ata_sata_phy_check_events(dev);
2676 }
2677
2678 /* do we have any device action ? */
2679 return (cause & (2 << shift));
2680 }
2681
2682 /* must be called with ATA channel locked and state_mtx held */
2683 static int
2684 ata_marvell_edma_begin_transaction(struct ata_request *request)
2685 {
2686 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2687 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2688 u_int32_t req_in;
2689 u_int8_t *bytep;
2690 u_int16_t *wordp;
2691 u_int32_t *quadp;
2692 int i, tag = 0x07;
2693 int dummy, error, slot;
2694
2695 /* only DMA R/W goes through the EMDA machine */
2696 if (request->u.ata.command != ATA_READ_DMA &&
2697 request->u.ata.command != ATA_WRITE_DMA) {
2698
2699 /* disable the EDMA machinery */
2700 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)
2701 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2702 return ata_begin_transaction(request);
2703 }
2704
2705 /* check for 48 bit access and convert if needed */
2706 ata_modify_if_48bit(request);
2707
2708 /* check sanity, setup SG list and DMA engine */
2709 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
2710 request->flags & ATA_R_READ, ch->dma->sg,
2711 &dummy))) {
2712 device_printf(request->dev, "setting up DMA failed\n");
2713 request->result = error;
2714 return ATA_OP_FINISHED;
2715 }
2716
2717 /* get next free request queue slot */
2718 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch));
2719 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f;
2720 bytep = (u_int8_t *)(ch->dma->work);
2721 bytep += (slot << 5);
2722 wordp = (u_int16_t *)bytep;
2723 quadp = (u_int32_t *)bytep;
2724
2725 /* fill in this request */
2726 quadp[0] = (long)ch->dma->sg_bus & 0xffffffff;
2727 quadp[1] = (u_int64_t)ch->dma->sg_bus >> 32;
2728 wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1);
2729
2730 i = 10;
2731 bytep[i++] = (request->u.ata.count >> 8) & 0xff;
2732 bytep[i++] = 0x10 | ATA_COUNT;
2733 bytep[i++] = request->u.ata.count & 0xff;
2734 bytep[i++] = 0x10 | ATA_COUNT;
2735
2736 bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
2737 bytep[i++] = 0x10 | ATA_SECTOR;
2738 bytep[i++] = request->u.ata.lba & 0xff;
2739 bytep[i++] = 0x10 | ATA_SECTOR;
2740
2741 bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
2742 bytep[i++] = 0x10 | ATA_CYL_LSB;
2743 bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
2744 bytep[i++] = 0x10 | ATA_CYL_LSB;
2745
2746 bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
2747 bytep[i++] = 0x10 | ATA_CYL_MSB;
2748 bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
2749 bytep[i++] = 0x10 | ATA_CYL_MSB;
2750
2751 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf);
2752 bytep[i++] = 0x10 | ATA_DRIVE;
2753
2754 bytep[i++] = request->u.ata.command;
2755 bytep[i++] = 0x90 | ATA_COMMAND;
2756
2757 /* enable EDMA machinery if needed */
2758 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) {
2759 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2760 while (!(ATA_INL(ctlr->r_res1,
2761 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
2762 DELAY(10);
2763 }
2764
2765 /* tell EDMA it has a new request */
2766 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f;
2767 req_in &= 0xfffffc00;
2768 req_in += (slot << 5);
2769 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in);
2770
2771 return ATA_OP_CONTINUES;
2772 }
2773
2774 /* must be called with ATA channel locked and state_mtx held */
2775 static int
2776 ata_marvell_edma_end_transaction(struct ata_request *request)
2777 {
2778 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2779 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2780 int offset = (ch->unit > 3 ? 0x30014 : 0x20014);
2781 u_int32_t icr = ATA_INL(ctlr->r_res1, offset);
2782 int res;
2783
2784 /* EDMA interrupt */
2785 if ((icr & (0x0001 << (ch->unit & 3)))) {
2786 struct ata_marvell_response *response;
2787 u_int32_t rsp_in, rsp_out;
2788 int slot;
2789
2790 /* stop timeout */
2791 callout_stop(&request->callout);
2792
2793 /* get response ptr's */
2794 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch));
2795 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch));
2796 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f;
2797 rsp_out &= 0xffffff00;
2798 rsp_out += (slot << 3);
2799 response = (struct ata_marvell_response *)
2800 (ch->dma->work + 1024 + (slot << 3));
2801
2802 /* record status for this request */
2803 request->status = response->dev_status;
2804 request->error = 0;
2805
2806 /* ack response */
2807 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out);
2808
2809 /* update progress */
2810 if (!(request->status & ATA_S_ERROR) &&
2811 !(request->flags & ATA_R_TIMEOUT))
2812 request->donecount = request->bytecount;
2813
2814 /* unload SG list */
2815 ch->dma->unload(ch->dev);
2816
2817 res = ATA_OP_FINISHED;
2818 }
2819
2820 /* legacy ATA interrupt */
2821 else {
2822 res = ata_end_transaction(request);
2823 }
2824
2825 /* ack interrupt */
2826 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3))));
2827 return res;
2828 }
2829
2830 static void
2831 ata_marvell_edma_reset(device_t dev)
2832 {
2833 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2834 struct ata_channel *ch = device_get_softc(dev);
2835
2836 /* disable the EDMA machinery */
2837 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2838 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
2839 DELAY(10);
2840
2841 /* clear SATA error register */
2842 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2843
2844 /* clear any outstanding error interrupts */
2845 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2846
2847 /* unmask all error interrupts */
2848 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
2849
2850 /* enable channel and test for devices */
2851 if (ata_sata_phy_reset(dev))
2852 ata_generic_reset(dev);
2853
2854 /* enable EDMA machinery */
2855 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2856 }
2857
2858 static void
2859 ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs,
2860 int error)
2861 {
2862 struct ata_dmasetprd_args *args = xsc;
2863 struct ata_marvell_dma_prdentry *prd = args->dmatab;
2864 int i;
2865
2866 if ((args->error = error))
2867 return;
2868
2869 for (i = 0; i < nsegs; i++) {
2870 prd[i].addrlo = htole32(segs[i].ds_addr);
2871 prd[i].count = htole32(segs[i].ds_len);
2872 prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32);
2873 }
2874 prd[i - 1].count |= htole32(ATA_DMA_EOT);
2875 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
2876 args->nsegs = nsegs;
2877 }
2878
2879 static void
2880 ata_marvell_edma_dmainit(device_t dev)
2881 {
2882 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2883 struct ata_channel *ch = device_get_softc(dev);
2884
2885 ata_dmainit(dev);
2886 if (ch->dma) {
2887 /* note start and stop are not used here */
2888 ch->dma->setprd = ata_marvell_edma_dmasetprd;
2889
2890 /* if 64bit support present adjust max address used */
2891 if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004)
2892 ch->dma->max_address = BUS_SPACE_MAXADDR;
2893
2894 /* chip does not reliably do 64K DMA transfers */
2895 ch->dma->max_iosize = 64 * DEV_BSIZE;
2896 }
2897 }
2898
2899
2900 /*
2901 * National chipset support functions
2902 */
2903 int
2904 ata_national_ident(device_t dev)
2905 {
2906 struct ata_pci_controller *ctlr = device_get_softc(dev);
2907
2908 /* this chip is a clone of the Cyrix chip, bugs and all */
2909 if (pci_get_devid(dev) == ATA_SC1100) {
2910 device_set_desc(dev, "National Geode SC1100 ATA33 controller");
2911 ctlr->chipinit = ata_national_chipinit;
2912 return 0;
2913 }
2914 return ENXIO;
2915 }
2916
2917 static int
2918 ata_national_chipinit(device_t dev)
2919 {
2920 struct ata_pci_controller *ctlr = device_get_softc(dev);
2921
2922 if (ata_setup_interrupt(dev))
2923 return ENXIO;
2924
2925 ctlr->setmode = ata_national_setmode;
2926 return 0;
2927 }
2928
2929 static void
2930 ata_national_setmode(device_t dev, int mode)
2931 {
2932 device_t gparent = GRANDPARENT(dev);
2933 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2934 struct ata_device *atadev = device_get_softc(dev);
2935 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2936 u_int32_t piotiming[] =
2937 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
2938 0x00803020, 0x20102010, 0x00100010,
2939 0x00100010, 0x00100010, 0x00100010 };
2940 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
2941 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
2942 int error;
2943
2944 ch->dma->alignment = 16;
2945 ch->dma->max_iosize = 64 * DEV_BSIZE;
2946
2947 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
2948
2949 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2950
2951 if (bootverbose)
2952 device_printf(dev, "%s setting %s on National chip\n",
2953 (error) ? "failed" : "success", ata_mode2str(mode));
2954 if (!error) {
2955 if (mode >= ATA_UDMA0) {
2956 pci_write_config(gparent, 0x44 + (devno << 3),
2957 udmatiming[mode & ATA_MODE_MASK], 4);
2958 }
2959 else if (mode >= ATA_WDMA0) {
2960 pci_write_config(gparent, 0x44 + (devno << 3),
2961 dmatiming[mode & ATA_MODE_MASK], 4);
2962 }
2963 else {
2964 pci_write_config(gparent, 0x44 + (devno << 3),
2965 pci_read_config(gparent, 0x44 + (devno << 3), 4) |
2966 0x80000000, 4);
2967 }
2968 pci_write_config(gparent, 0x40 + (devno << 3),
2969 piotiming[ata_mode2idx(mode)], 4);
2970 atadev->mode = mode;
2971 }
2972 }
2973
2974
2975 /*
2976 * NetCell chipset support functions
2977 */
2978 int
2979 ata_netcell_ident(device_t dev)
2980 {
2981 struct ata_pci_controller *ctlr = device_get_softc(dev);
2982
2983 if (pci_get_devid(dev) == ATA_NETCELL_SR) {
2984 device_set_desc(dev, "Netcell SyncRAID SR3000/5000 RAID Controller");
2985 ctlr->chipinit = ata_netcell_chipinit;
2986 return 0;
2987 }
2988 return ENXIO;
2989 }
2990
2991 static int
2992 ata_netcell_chipinit(device_t dev)
2993 {
2994 struct ata_pci_controller *ctlr = device_get_softc(dev);
2995
2996 if (ata_generic_chipinit(dev))
2997 return ENXIO;
2998
2999 ctlr->allocate = ata_netcell_allocate;
3000 return 0;
3001 }
3002
3003 static int
3004 ata_netcell_allocate(device_t dev)
3005 {
3006 struct ata_channel *ch = device_get_softc(dev);
3007
3008 /* setup the usual register normal pci style */
3009 if (ata_pci_allocate(dev))
3010 return ENXIO;
3011
3012 /* the NetCell only supports 16 bit PIO transfers */
3013 ch->flags |= ATA_USE_16BIT;
3014
3015 return 0;
3016 }
3017
3018
3019 /*
3020 * nVidia chipset support functions
3021 */
3022 int
3023 ata_nvidia_ident(device_t dev)
3024 {
3025 struct ata_pci_controller *ctlr = device_get_softc(dev);
3026 static struct ata_chip_id ids[] =
3027 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nForce" },
3028 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2" },
3029 { ATA_NFORCE2_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2 Pro" },
3030 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" },
3031 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3" },
3032 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3 Pro" },
3033 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
3034 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
3035 { ATA_NFORCE_MCP04, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP" },
3036 { ATA_NFORCE_MCP04_S1, 0, 0, NV4, ATA_SA150, "nForce MCP" },
3037 { ATA_NFORCE_MCP04_S2, 0, 0, NV4, ATA_SA150, "nForce MCP" },
3038 { ATA_NFORCE_CK804, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce CK804" },
3039 { ATA_NFORCE_CK804_S1, 0, 0, NV4, ATA_SA300, "nForce CK804" },
3040 { ATA_NFORCE_CK804_S2, 0, 0, NV4, ATA_SA300, "nForce CK804" },
3041 { ATA_NFORCE_MCP51, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP51" },
3042 { ATA_NFORCE_MCP51_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
3043 { ATA_NFORCE_MCP51_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
3044 { ATA_NFORCE_MCP55, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP55" },
3045 { ATA_NFORCE_MCP55_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
3046 { ATA_NFORCE_MCP55_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
3047 { ATA_NFORCE_MCP61, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP61" },
3048 { ATA_NFORCE_MCP61_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
3049 { ATA_NFORCE_MCP61_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
3050 { ATA_NFORCE_MCP61_S3, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
3051 { ATA_NFORCE_MCP65, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP65" },
3052 { ATA_NFORCE_MCP67, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP67" },
3053 { ATA_NFORCE_MCP73, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP73" },
3054 { ATA_NFORCE_MCP77, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP77" },
3055 { 0, 0, 0, 0, 0, 0}} ;
3056
3057 if (!(ctlr->chip = ata_match_chip(dev, ids)))
3058 return ENXIO;
3059
3060 ata_set_desc(dev);
3061 ctlr->chipinit = ata_nvidia_chipinit;
3062 return 0;
3063 }
3064
3065 static int
3066 ata_nvidia_chipinit(device_t dev)
3067 {
3068 struct ata_pci_controller *ctlr = device_get_softc(dev);
3069
3070 if (ata_setup_interrupt(dev))
3071 return ENXIO;
3072
3073 if (ctlr->chip->max_dma >= ATA_SA150) {
3074 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1)
3075 ctlr->r_type2 = SYS_RES_IOPORT;
3076 else
3077 ctlr->r_type2 = SYS_RES_MEMORY;
3078 ctlr->r_rid2 = PCIR_BAR(5);
3079 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3080 &ctlr->r_rid2, RF_ACTIVE))) {
3081 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
3082
3083 ctlr->allocate = ata_nvidia_allocate;
3084 ctlr->reset = ata_nvidia_reset;
3085
3086 /* enable control access */
3087 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1);
3088
3089 if (ctlr->chip->cfg2 & NVQ) {
3090 /* clear interrupt status */
3091 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff);
3092
3093 /* enable device and PHY state change interrupts */
3094 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d);
3095
3096 /* disable NCQ support */
3097 ATA_OUTL(ctlr->r_res2, 0x0400,
3098 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9);
3099 }
3100 else {
3101 /* clear interrupt status */
3102 ATA_OUTB(ctlr->r_res2, offset, 0xff);
3103
3104 /* enable device and PHY state change interrupts */
3105 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd);
3106 }
3107
3108 /* enable PCI interrupt */
3109 pci_write_config(dev, PCIR_COMMAND,
3110 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
3111
3112 }
3113 ctlr->setmode = ata_sata_setmode;
3114 }
3115 else {
3116 /* disable prefetch, postwrite */
3117 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
3118 ctlr->setmode = ata_via_family_setmode;
3119 }
3120 return 0;
3121 }
3122
3123 static int
3124 ata_nvidia_allocate(device_t dev)
3125 {
3126 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3127 struct ata_channel *ch = device_get_softc(dev);
3128
3129 /* setup the usual register normal pci style */
3130 if (ata_pci_allocate(dev))
3131 return ENXIO;
3132
3133 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3134 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6);
3135 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3136 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6);
3137 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3138 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6);
3139
3140 ch->hw.status = ata_nvidia_status;
3141 ch->flags |= ATA_NO_SLAVE;
3142
3143 return 0;
3144 }
3145
3146 static int
3147 ata_nvidia_status(device_t dev)
3148 {
3149 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3150 struct ata_channel *ch = device_get_softc(dev);
3151 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
3152 int shift = ch->unit << (ctlr->chip->cfg2 & NVQ ? 4 : 2);
3153 u_int32_t istatus = ATA_INL(ctlr->r_res2, offset);
3154
3155 /* do we have any PHY events ? */
3156 if (istatus & (0x0c << shift))
3157 ata_sata_phy_check_events(dev);
3158
3159 /* clear interrupt(s) */
3160 ATA_OUTB(ctlr->r_res2, offset,
3161 (0x0f << shift) | (ctlr->chip->cfg2 & NVQ ? 0x00f000f0 : 0));
3162
3163 /* do we have any device action ? */
3164 return (istatus & (0x01 << shift));
3165 }
3166
3167 static void
3168 ata_nvidia_reset(device_t dev)
3169 {
3170 if (ata_sata_phy_reset(dev))
3171 ata_generic_reset(dev);
3172 }
3173
3174
3175 /*
3176 * Promise chipset support functions
3177 */
3178 #define ATA_PDC_APKT_OFFSET 0x00000010
3179 #define ATA_PDC_HPKT_OFFSET 0x00000040
3180 #define ATA_PDC_ASG_OFFSET 0x00000080
3181 #define ATA_PDC_LSG_OFFSET 0x000000c0
3182 #define ATA_PDC_HSG_OFFSET 0x00000100
3183 #define ATA_PDC_CHN_OFFSET 0x00000400
3184 #define ATA_PDC_BUF_BASE 0x00400000
3185 #define ATA_PDC_BUF_OFFSET 0x00100000
3186 #define ATA_PDC_MAX_HPKT 8
3187 #define ATA_PDC_WRITE_REG 0x00
3188 #define ATA_PDC_WRITE_CTL 0x0e
3189 #define ATA_PDC_WRITE_END 0x08
3190 #define ATA_PDC_WAIT_NBUSY 0x10
3191 #define ATA_PDC_WAIT_READY 0x18
3192 #define ATA_PDC_1B 0x20
3193 #define ATA_PDC_2B 0x40
3194
3195 struct host_packet {
3196 u_int32_t addr;
3197 TAILQ_ENTRY(host_packet) chain;
3198 };
3199
3200 struct ata_promise_sx4 {
3201 struct mtx mtx;
3202 TAILQ_HEAD(, host_packet) queue;
3203 int busy;
3204 };
3205
3206 int
3207 ata_promise_ident(device_t dev)
3208 {
3209 struct ata_pci_controller *ctlr = device_get_softc(dev);
3210 struct ata_chip_id *idx;
3211 static struct ata_chip_id ids[] =
3212 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "PDC20246" },
3213 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20262" },
3214 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20263" },
3215 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20265" },
3216 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20267" },
3217 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20268" },
3218 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "PDC20269" },
3219 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20270" },
3220 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "PDC20271" },
3221 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "PDC20275" },
3222 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "PDC20276" },
3223 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "PDC20277" },
3224 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "PDC20318" },
3225 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "PDC20319" },
3226 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20371" },
3227 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20375" },
3228 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20376" },
3229 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20377" },
3230 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20378" },
3231 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20379" },
3232 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" },
3233 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" },
3234 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" },
3235 { ATA_PDC20771, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" },
3236 { ATA_PDC40775, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" },
3237 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20617" },
3238 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20618" },
3239 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20619" },
3240 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20620" },
3241 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "PDC20621" },
3242 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "PDC20622" },
3243 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40518" },
3244 { ATA_PDC40519, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40519" },
3245 { ATA_PDC40718, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40718" },
3246 { ATA_PDC40719, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40719" },
3247 { ATA_PDC40779, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40779" },
3248 { 0, 0, 0, 0, 0, 0}};
3249 char buffer[64];
3250 uintptr_t devid = 0;
3251
3252 if (!(idx = ata_match_chip(dev, ids)))
3253 return ENXIO;
3254
3255 /* if we are on a SuperTrak SX6000 dont attach */
3256 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
3257 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
3258 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
3259 devid == ATA_I960RM)
3260 return ENXIO;
3261
3262 strcpy(buffer, "Promise ");
3263 strcat(buffer, idx->text);
3264
3265 /* if we are on a FastTrak TX4, adjust the interrupt resource */
3266 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
3267 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
3268 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
3269 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) {
3270 static long start = 0, end = 0;
3271
3272 if (pci_get_slot(dev) == 1) {
3273 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
3274 strcat(buffer, " (channel 0+1)");
3275 }
3276 else if (pci_get_slot(dev) == 2 && start && end) {
3277 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
3278 strcat(buffer, " (channel 2+3)");
3279 }
3280 else {
3281 start = end = 0;
3282 }
3283 }
3284 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
3285 device_set_desc_copy(dev, buffer);
3286 ctlr->chip = idx;
3287 ctlr->chipinit = ata_promise_chipinit;
3288 return 0;
3289 }
3290
3291 static int
3292 ata_promise_chipinit(device_t dev)
3293 {
3294 struct ata_pci_controller *ctlr = device_get_softc(dev);
3295 int fake_reg, stat_reg;
3296
3297 if (ata_setup_interrupt(dev))
3298 return ENXIO;
3299
3300 switch (ctlr->chip->cfg1) {
3301 case PRNEW:
3302 /* setup clocks */
3303 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a);
3304
3305 ctlr->dmainit = ata_promise_dmainit;
3306 /* FALLTHROUGH */
3307
3308 case PROLD:
3309 /* enable burst mode */
3310 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01);
3311 ctlr->allocate = ata_promise_allocate;
3312 ctlr->setmode = ata_promise_setmode;
3313 return 0;
3314
3315 case PRTX:
3316 ctlr->allocate = ata_promise_tx2_allocate;
3317 ctlr->setmode = ata_promise_setmode;
3318 return 0;
3319
3320 case PRMIO:
3321 ctlr->r_type1 = SYS_RES_MEMORY;
3322 ctlr->r_rid1 = PCIR_BAR(4);
3323 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
3324 &ctlr->r_rid1, RF_ACTIVE)))
3325 goto failnfree;
3326
3327 ctlr->r_type2 = SYS_RES_MEMORY;
3328 ctlr->r_rid2 = PCIR_BAR(3);
3329 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3330 &ctlr->r_rid2, RF_ACTIVE)))
3331 goto failnfree;
3332
3333 if (ctlr->chip->cfg2 == PRSX4X) {
3334 struct ata_promise_sx4 *hpkt;
3335 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080);
3336
3337 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3338 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL,
3339 ata_promise_sx4_intr, ctlr, &ctlr->handle)) {
3340 device_printf(dev, "unable to setup interrupt\n");
3341 goto failnfree;
3342 }
3343
3344 /* print info about cache memory */
3345 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n",
3346 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4,
3347 ((dimm >> 24) & 0xff),
3348 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ?
3349 " ECC enabled" : "" );
3350
3351 /* adjust cache memory parameters */
3352 ATA_OUTL(ctlr->r_res2, 0x000c000c,
3353 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000));
3354
3355 /* setup host packet controls */
3356 hpkt = malloc(sizeof(struct ata_promise_sx4),
3357 M_TEMP, M_NOWAIT | M_ZERO);
3358 mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF);
3359 TAILQ_INIT(&hpkt->queue);
3360 hpkt->busy = 0;
3361 device_set_ivars(dev, hpkt);
3362 ctlr->allocate = ata_promise_mio_allocate;
3363 ctlr->reset = ata_promise_mio_reset;
3364 ctlr->dmainit = ata_promise_mio_dmainit;
3365 ctlr->setmode = ata_promise_setmode;
3366 ctlr->channels = 4;
3367 return 0;
3368 }
3369
3370 /* mio type controllers need an interrupt intercept */
3371 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3372 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL,
3373 ata_promise_mio_intr, ctlr, &ctlr->handle)) {
3374 device_printf(dev, "unable to setup interrupt\n");
3375 goto failnfree;
3376 }
3377
3378 switch (ctlr->chip->cfg2) {
3379 case PRPATA:
3380 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) +
3381 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2;
3382 goto sata150;
3383 case PRCMBO:
3384 ctlr->channels = 3;
3385 goto sata150;
3386 case PRSATA:
3387 ctlr->channels = 4;
3388 sata150:
3389 fake_reg = 0x60;
3390 stat_reg = 0x6c;
3391 break;
3392
3393 case PRCMBO2:
3394 ctlr->channels = 3;
3395 goto sataii;
3396 case PRSATA2:
3397 default:
3398 ctlr->channels = 4;
3399 sataii:
3400 fake_reg = 0x54;
3401 stat_reg = 0x60;
3402 break;
3403 }
3404
3405 /* prime fake interrupt register */
3406 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3407
3408 /* clear SATA status and unmask interrupts */
3409 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff);
3410
3411 /* enable "long burst lenght" on gen2 chips */
3412 if ((ctlr->chip->cfg2 == PRSATA2) || (ctlr->chip->cfg2 == PRCMBO2))
3413 ATA_OUTL(ctlr->r_res2, 0x44, ATA_INL(ctlr->r_res2, 0x44) | 0x2000);
3414
3415 ctlr->allocate = ata_promise_mio_allocate;
3416 ctlr->reset = ata_promise_mio_reset;
3417 ctlr->dmainit = ata_promise_mio_dmainit;
3418 ctlr->setmode = ata_promise_mio_setmode;
3419
3420 return 0;
3421 }
3422
3423 failnfree:
3424 if (ctlr->r_res2)
3425 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
3426 if (ctlr->r_res1)
3427 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1);
3428 return ENXIO;
3429 }
3430
3431 static int
3432 ata_promise_allocate(device_t dev)
3433 {
3434 struct ata_channel *ch = device_get_softc(dev);
3435
3436 if (ata_pci_allocate(dev))
3437 return ENXIO;
3438
3439 ch->hw.status = ata_promise_status;
3440 return 0;
3441 }
3442
3443 static int
3444 ata_promise_status(device_t dev)
3445 {
3446 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3447 struct ata_channel *ch = device_get_softc(dev);
3448
3449 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) {
3450 return ata_pci_status(dev);
3451 }
3452 return 0;
3453 }
3454
3455 static int
3456 ata_promise_dmastart(device_t dev)
3457 {
3458 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3459 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3460 struct ata_device *atadev = device_get_softc(dev);
3461
3462 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3463 ATA_OUTB(ctlr->r_res1, 0x11,
3464 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02));
3465 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20,
3466 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) |
3467 (ch->dma->cur_iosize >> 1));
3468 }
3469 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) |
3470 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
3471 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus);
3472 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3473 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) |
3474 ATA_BMCMD_START_STOP);
3475 ch->flags |= ATA_DMA_ACTIVE;
3476 return 0;
3477 }
3478
3479 static int
3480 ata_promise_dmastop(device_t dev)
3481 {
3482 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3483 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3484 struct ata_device *atadev = device_get_softc(dev);
3485 int error;
3486
3487 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3488 ATA_OUTB(ctlr->r_res1, 0x11,
3489 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02));
3490 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0);
3491 }
3492 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT);
3493 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3494 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3495 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3496 ch->flags &= ~ATA_DMA_ACTIVE;
3497 return error;
3498 }
3499
3500 static void
3501 ata_promise_dmareset(device_t dev)
3502 {
3503 struct ata_channel *ch = device_get_softc(dev);
3504
3505 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3506 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3507 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3508 ch->flags &= ~ATA_DMA_ACTIVE;
3509 }
3510
3511 static void
3512 ata_promise_dmainit(device_t dev)
3513 {
3514 struct ata_channel *ch = device_get_softc(dev);
3515
3516 ata_dmainit(dev);
3517 if (ch->dma) {
3518 ch->dma->start = ata_promise_dmastart;
3519 ch->dma->stop = ata_promise_dmastop;
3520 ch->dma->reset = ata_promise_dmareset;
3521 }
3522 }
3523
3524 static void
3525 ata_promise_setmode(device_t dev, int mode)
3526 {
3527 device_t gparent = GRANDPARENT(dev);
3528 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3529 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3530 struct ata_device *atadev = device_get_softc(dev);
3531 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
3532 int error;
3533 u_int32_t timings[][2] = {
3534 /* PROLD PRNEW mode */
3535 { 0x004ff329, 0x004fff2f }, /* PIO 0 */
3536 { 0x004fec25, 0x004ff82a }, /* PIO 1 */
3537 { 0x004fe823, 0x004ff026 }, /* PIO 2 */
3538 { 0x004fe622, 0x004fec24 }, /* PIO 3 */
3539 { 0x004fe421, 0x004fe822 }, /* PIO 4 */
3540 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */
3541 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */
3542 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */
3543 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */
3544 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */
3545 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */
3546 { 0, 0x00424ef6 }, /* UDMA 3 */
3547 { 0, 0x004127f3 }, /* UDMA 4 */
3548 { 0, 0x004127f3 } /* UDMA 5 */
3549 };
3550
3551 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
3552
3553 switch (ctlr->chip->cfg1) {
3554 case PROLD:
3555 case PRNEW:
3556 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) &
3557 (ch->unit ? 1 << 11 : 1 << 10))) {
3558 ata_print_cable(dev, "controller");
3559 mode = ATA_UDMA2;
3560 }
3561 if (ata_atapi(dev) && mode > ATA_PIO_MAX)
3562 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
3563 break;
3564
3565 case PRTX:
3566 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3567 if (mode > ATA_UDMA2 &&
3568 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) {
3569 ata_print_cable(dev, "controller");
3570 mode = ATA_UDMA2;
3571 }
3572 break;
3573
3574 case PRMIO:
3575 if (mode > ATA_UDMA2 &&
3576 (ATA_INL(ctlr->r_res2,
3577 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) +
3578 (ch->unit << 7)) & 0x01000000)) {
3579 ata_print_cable(dev, "controller");
3580 mode = ATA_UDMA2;
3581 }
3582 break;
3583 }
3584
3585 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3586
3587 if (bootverbose)
3588 device_printf(dev, "%ssetting %s on %s chip\n",
3589 (error) ? "FAILURE " : "",
3590 ata_mode2str(mode), ctlr->chip->text);
3591 if (!error) {
3592 if (ctlr->chip->cfg1 < PRTX)
3593 pci_write_config(gparent, 0x60 + (devno << 2),
3594 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
3595 atadev->mode = mode;
3596 }
3597 return;
3598 }
3599
3600 static int
3601 ata_promise_tx2_allocate(device_t dev)
3602 {
3603 struct ata_channel *ch = device_get_softc(dev);
3604
3605 if (ata_pci_allocate(dev))
3606 return ENXIO;
3607
3608 ch->hw.status = ata_promise_tx2_status;
3609 return 0;
3610 }
3611
3612 static int
3613 ata_promise_tx2_status(device_t dev)
3614 {
3615 struct ata_channel *ch = device_get_softc(dev);
3616
3617 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3618 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
3619 return ata_pci_status(dev);
3620 }
3621 return 0;
3622 }
3623
3624 static int
3625 ata_promise_mio_allocate(device_t dev)
3626 {
3627 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3628 struct ata_channel *ch = device_get_softc(dev);
3629 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0;
3630 int i;
3631
3632 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
3633 ch->r_io[i].res = ctlr->r_res2;
3634 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7);
3635 }
3636 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
3637 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7);
3638 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
3639 ata_default_registers(dev);
3640 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) ||
3641 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2)) {
3642 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3643 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8);
3644 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3645 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8);
3646 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3647 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8);
3648 ch->flags |= ATA_NO_SLAVE;
3649 }
3650 ch->flags |= ATA_USE_16BIT;
3651
3652 ata_generic_hw(dev);
3653 if (ctlr->chip->cfg2 & PRSX4X) {
3654 ch->hw.command = ata_promise_sx4_command;
3655 }
3656 else {
3657 ch->hw.command = ata_promise_mio_command;
3658 ch->hw.status = ata_promise_mio_status;
3659 }
3660 return 0;
3661 }
3662
3663 static void
3664 ata_promise_mio_intr(void *data)
3665 {
3666 struct ata_pci_controller *ctlr = data;
3667 struct ata_channel *ch;
3668 u_int32_t vector;
3669 int unit, fake_reg;
3670
3671 switch (ctlr->chip->cfg2) {
3672 case PRPATA:
3673 case PRCMBO:
3674 case PRSATA:
3675 fake_reg = 0x60;
3676 break;
3677 case PRCMBO2:
3678 case PRSATA2:
3679 default:
3680 fake_reg = 0x54;
3681 break;
3682 }
3683
3684 /*
3685 * since reading interrupt status register on early "mio" chips
3686 * clears the status bits we cannot read it for each channel later on
3687 * in the generic interrupt routine.
3688 * store the bits in an unused register in the chip so we can read
3689 * it from there safely to get around this "feature".
3690 */
3691 vector = ATA_INL(ctlr->r_res2, 0x040);
3692 ATA_OUTL(ctlr->r_res2, 0x040, vector);
3693 ATA_OUTL(ctlr->r_res2, fake_reg, vector);
3694
3695 for (unit = 0; unit < ctlr->channels; unit++) {
3696 if ((ch = ctlr->interrupt[unit].argument))
3697 ctlr->interrupt[unit].function(ch);
3698 }
3699
3700 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3701 }
3702
3703 static int
3704 ata_promise_mio_status(device_t dev)
3705 {
3706 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3707 struct ata_channel *ch = device_get_softc(dev);
3708 struct ata_connect_task *tp;
3709 u_int32_t fake_reg, stat_reg, vector, status;
3710
3711 switch (ctlr->chip->cfg2) {
3712 case PRPATA:
3713 case PRCMBO:
3714 case PRSATA:
3715 fake_reg = 0x60;
3716 stat_reg = 0x6c;
3717 break;
3718 case PRCMBO2:
3719 case PRSATA2:
3720 default:
3721 fake_reg = 0x54;
3722 stat_reg = 0x60;
3723 break;
3724 }
3725
3726 /* read and acknowledge interrupt */
3727 vector = ATA_INL(ctlr->r_res2, fake_reg);
3728
3729 /* read and clear interface status */
3730 status = ATA_INL(ctlr->r_res2, stat_reg);
3731 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit));
3732
3733 /* check for and handle disconnect events */
3734 if ((status & (0x00000001 << ch->unit)) &&
3735 (tp = (struct ata_connect_task *)
3736 malloc(sizeof(struct ata_connect_task),
3737 M_ATA, M_NOWAIT | M_ZERO))) {
3738
3739 if (bootverbose)
3740 device_printf(ch->dev, "DISCONNECT requested\n");
3741 tp->action = ATA_C_DETACH;
3742 tp->dev = ch->dev;
3743 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3744 taskqueue_enqueue(taskqueue_thread, &tp->task);
3745 }
3746
3747 /* check for and handle connect events */
3748 if ((status & (0x00000010 << ch->unit)) &&
3749 (tp = (struct ata_connect_task *)
3750 malloc(sizeof(struct ata_connect_task),
3751 M_ATA, M_NOWAIT | M_ZERO))) {
3752
3753 if (bootverbose)
3754 device_printf(ch->dev, "CONNECT requested\n");
3755 tp->action = ATA_C_ATTACH;
3756 tp->dev = ch->dev;
3757 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3758 taskqueue_enqueue(taskqueue_thread, &tp->task);
3759 }
3760
3761 /* do we have any device action ? */
3762 return (vector & (1 << (ch->unit + 1)));
3763 }
3764
3765 static int
3766 ata_promise_mio_command(struct ata_request *request)
3767 {
3768 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
3769 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
3770 u_int32_t *wordp = (u_int32_t *)ch->dma->work;
3771
3772 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001);
3773
3774 /* XXX SOS add ATAPI commands support later */
3775 switch (request->u.ata.command) {
3776 default:
3777 return ata_generic_command(request);
3778
3779 case ATA_READ_DMA:
3780 case ATA_READ_DMA48:
3781 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24));
3782 break;
3783
3784 case ATA_WRITE_DMA:
3785 case ATA_WRITE_DMA48:
3786 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24));
3787 break;
3788 }
3789 wordp[1] = htole32(ch->dma->sg_bus);
3790 wordp[2] = 0;
3791 ata_promise_apkt((u_int8_t*)wordp, request);
3792
3793 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma->work_bus);
3794 return 0;
3795 }
3796
3797 static void
3798 ata_promise_mio_reset(device_t dev)
3799 {
3800 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3801 struct ata_channel *ch = device_get_softc(dev);
3802 struct ata_promise_sx4 *hpktp;
3803
3804 switch (ctlr->chip->cfg2) {
3805 case PRSX4X:
3806
3807 /* softreset channel ATA module */
3808 hpktp = device_get_ivars(ctlr->dev);
3809 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1);
3810 ata_udelay(1000);
3811 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7),
3812 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) &
3813 ~0x00003f9f) | (ch->unit + 1));
3814
3815 /* softreset HOST module */ /* XXX SOS what about other outstandings */
3816 mtx_lock(&hpktp->mtx);
3817 ATA_OUTL(ctlr->r_res2, 0xc012c,
3818 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11));
3819 DELAY(10);
3820 ATA_OUTL(ctlr->r_res2, 0xc012c,
3821 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f));
3822 hpktp->busy = 0;
3823 mtx_unlock(&hpktp->mtx);
3824 ata_generic_reset(dev);
3825 break;
3826
3827 case PRPATA:
3828 case PRCMBO:
3829 case PRSATA:
3830 if ((ctlr->chip->cfg2 == PRSATA) ||
3831 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
3832
3833 /* mask plug/unplug intr */
3834 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit));
3835 }
3836
3837 /* softreset channels ATA module */
3838 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
3839 ata_udelay(10000);
3840 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
3841 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
3842 ~0x00003f9f) | (ch->unit + 1));
3843
3844 if ((ctlr->chip->cfg2 == PRSATA) ||
3845 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
3846
3847 if (ata_sata_phy_reset(dev))
3848 ata_generic_reset(dev);
3849
3850 /* reset and enable plug/unplug intr */
3851 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit));
3852 }
3853 else
3854 ata_generic_reset(dev);
3855 break;
3856
3857 case PRCMBO2:
3858 case PRSATA2:
3859 if ((ctlr->chip->cfg2 == PRSATA2) ||
3860 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
3861 /* set portmultiplier port */
3862 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f);
3863
3864 /* mask plug/unplug intr */
3865 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit));
3866 }
3867
3868 /* softreset channels ATA module */
3869 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
3870 ata_udelay(10000);
3871 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
3872 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
3873 ~0x00003f9f) | (ch->unit + 1));
3874
3875 if ((ctlr->chip->cfg2 == PRSATA2) ||
3876 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
3877
3878 /* set PHY mode to "improved" */
3879 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8),
3880 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) &
3881 ~0x00000003) | 0x00000001);
3882
3883 if (ata_sata_phy_reset(dev))
3884 ata_generic_reset(dev);
3885
3886 /* reset and enable plug/unplug intr */
3887 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit));
3888
3889 /* set portmultiplier port */
3890 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00);
3891 }
3892 else
3893 ata_generic_reset(dev);
3894 break;
3895
3896 }
3897 }
3898
3899 static void
3900 ata_promise_mio_dmainit(device_t dev)
3901 {
3902 struct ata_channel *ch = device_get_softc(dev);
3903
3904 /* note start and stop are not used here */
3905 ata_dmainit(dev);
3906 if (ch->dma)
3907 ch->dma->setprd = ata_promise_mio_setprd;
3908 }
3909
3910
3911 #define MAXLASTSGSIZE (32 * sizeof(u_int32_t))
3912 static void
3913 ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
3914 {
3915 struct ata_dmasetprd_args *args = xsc;
3916 struct ata_dma_prdentry *prd = args->dmatab;
3917 int i;
3918
3919 if ((args->error = error))
3920 return;
3921
3922 for (i = 0; i < nsegs; i++) {
3923 prd[i].addr = htole32(segs[i].ds_addr);
3924 prd[i].count = htole32(segs[i].ds_len);
3925 }
3926 if (segs[i - 1].ds_len > MAXLASTSGSIZE) {
3927 //printf("split last SG element of %u\n", segs[i - 1].ds_len);
3928 prd[i - 1].count = htole32(segs[i - 1].ds_len - MAXLASTSGSIZE);
3929 prd[i].count = htole32(MAXLASTSGSIZE);
3930 prd[i].addr = htole32(segs[i - 1].ds_addr +
3931 (segs[i - 1].ds_len - MAXLASTSGSIZE));
3932 nsegs++;
3933 i++;
3934 }
3935 prd[i - 1].count |= htole32(ATA_DMA_EOT);
3936 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
3937 args->nsegs = nsegs;
3938 }
3939
3940 static void
3941 ata_promise_mio_setmode(device_t dev, int mode)
3942 {
3943 device_t gparent = GRANDPARENT(dev);
3944 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3945 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3946
3947 if ( (ctlr->chip->cfg2 == PRSATA) ||
3948 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2)) ||
3949 (ctlr->chip->cfg2 == PRSATA2) ||
3950 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2)))
3951 ata_sata_setmode(dev, mode);
3952 else
3953 ata_promise_setmode(dev, mode);
3954 }
3955
3956 static void
3957 ata_promise_sx4_intr(void *data)
3958 {
3959 struct ata_pci_controller *ctlr = data;
3960 struct ata_channel *ch;
3961 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480);
3962 int unit;
3963
3964 for (unit = 0; unit < ctlr->channels; unit++) {
3965 if (vector & (1 << (unit + 1)))
3966 if ((ch = ctlr->interrupt[unit].argument))
3967 ctlr->interrupt[unit].function(ch);
3968 if (vector & (1 << (unit + 5)))
3969 if ((ch = ctlr->interrupt[unit].argument))
3970 ata_promise_queue_hpkt(ctlr,
3971 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
3972 ATA_PDC_HPKT_OFFSET));
3973 if (vector & (1 << (unit + 9))) {
3974 ata_promise_next_hpkt(ctlr);
3975 if ((ch = ctlr->interrupt[unit].argument))
3976 ctlr->interrupt[unit].function(ch);
3977 }
3978 if (vector & (1 << (unit + 13))) {
3979 ata_promise_next_hpkt(ctlr);
3980 if ((ch = ctlr->interrupt[unit].argument))
3981 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
3982 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
3983 ATA_PDC_APKT_OFFSET));
3984 }
3985 }
3986 }
3987
3988 static int
3989 ata_promise_sx4_command(struct ata_request *request)
3990 {
3991 device_t gparent = GRANDPARENT(request->dev);
3992 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3993 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
3994 struct ata_dma_prdentry *prd = ch->dma->sg;
3995 caddr_t window = rman_get_virtual(ctlr->r_res1);
3996 u_int32_t *wordp;
3997 int i, idx, length = 0;
3998
3999 /* XXX SOS add ATAPI commands support later */
4000 switch (request->u.ata.command) {
4001
4002 default:
4003 return -1;
4004
4005 case ATA_ATA_IDENTIFY:
4006 case ATA_READ:
4007 case ATA_READ48:
4008 case ATA_READ_MUL:
4009 case ATA_READ_MUL48:
4010 case ATA_WRITE:
4011 case ATA_WRITE48:
4012 case ATA_WRITE_MUL:
4013 case ATA_WRITE_MUL48:
4014 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
4015 return ata_generic_command(request);
4016
4017 case ATA_SETFEATURES:
4018 case ATA_FLUSHCACHE:
4019 case ATA_FLUSHCACHE48:
4020 case ATA_SLEEP:
4021 case ATA_SET_MULTI:
4022 wordp = (u_int32_t *)
4023 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
4024 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24));
4025 wordp[1] = 0;
4026 wordp[2] = 0;
4027 ata_promise_apkt((u_int8_t *)wordp, request);
4028 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
4029 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
4030 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4031 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET));
4032 return 0;
4033
4034 case ATA_READ_DMA:
4035 case ATA_READ_DMA48:
4036 case ATA_WRITE_DMA:
4037 case ATA_WRITE_DMA48:
4038 wordp = (u_int32_t *)
4039 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET);
4040 i = idx = 0;
4041 do {
4042 wordp[idx++] = prd[i].addr;
4043 wordp[idx++] = prd[i].count;
4044 length += (prd[i].count & ~ATA_DMA_EOT);
4045 } while (!(prd[i++].count & ATA_DMA_EOT));
4046
4047 wordp = (u_int32_t *)
4048 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET);
4049 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
4050 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
4051
4052 wordp = (u_int32_t *)
4053 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET);
4054 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
4055 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
4056
4057 wordp = (u_int32_t *)
4058 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET);
4059 if (request->flags & ATA_R_READ)
4060 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24));
4061 if (request->flags & ATA_R_WRITE)
4062 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24));
4063 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET);
4064 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET);
4065 wordp[3] = 0;
4066
4067 wordp = (u_int32_t *)
4068 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
4069 if (request->flags & ATA_R_READ)
4070 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24));
4071 if (request->flags & ATA_R_WRITE)
4072 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24));
4073 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET);
4074 wordp[2] = 0;
4075 ata_promise_apkt((u_int8_t *)wordp, request);
4076 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
4077
4078 if (request->flags & ATA_R_READ) {
4079 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001);
4080 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001);
4081 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4082 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET));
4083 }
4084 if (request->flags & ATA_R_WRITE) {
4085 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001);
4086 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001);
4087 ata_promise_queue_hpkt(ctlr,
4088 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET));
4089 }
4090 return 0;
4091 }
4092 }
4093
4094 static int
4095 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request)
4096 {
4097 struct ata_device *atadev = device_get_softc(request->dev);
4098 int i = 12;
4099
4100 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE;
4101 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit;
4102 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL;
4103 bytep[i++] = ATA_A_4BIT;
4104
4105 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
4106 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE;
4107 bytep[i++] = request->u.ata.feature >> 8;
4108 bytep[i++] = request->u.ata.feature;
4109 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT;
4110 bytep[i++] = request->u.ata.count >> 8;
4111 bytep[i++] = request->u.ata.count;
4112 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR;
4113 bytep[i++] = request->u.ata.lba >> 24;
4114 bytep[i++] = request->u.ata.lba;
4115 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
4116 bytep[i++] = request->u.ata.lba >> 32;
4117 bytep[i++] = request->u.ata.lba >> 8;
4118 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
4119 bytep[i++] = request->u.ata.lba >> 40;
4120 bytep[i++] = request->u.ata.lba >> 16;
4121 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
4122 bytep[i++] = ATA_D_LBA | atadev->unit;
4123 }
4124 else {
4125 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE;
4126 bytep[i++] = request->u.ata.feature;
4127 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT;
4128 bytep[i++] = request->u.ata.count;
4129 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR;
4130 bytep[i++] = request->u.ata.lba;
4131 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
4132 bytep[i++] = request->u.ata.lba >> 8;
4133 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
4134 bytep[i++] = request->u.ata.lba >> 16;
4135 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
4136 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) |
4137 ATA_D_IBM | atadev->unit | ((request->u.ata.lba >> 24)&0xf);
4138 }
4139 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND;
4140 bytep[i++] = request->u.ata.command;
4141 return i;
4142 }
4143
4144 static void
4145 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt)
4146 {
4147 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
4148
4149 mtx_lock(&hpktp->mtx);
4150 if (hpktp->busy) {
4151 struct host_packet *hp =
4152 malloc(sizeof(struct host_packet), M_TEMP, M_NOWAIT | M_ZERO);
4153 hp->addr = hpkt;
4154 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain);
4155 }
4156 else {
4157 hpktp->busy = 1;
4158 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt);
4159 }
4160 mtx_unlock(&hpktp->mtx);
4161 }
4162
4163 static void
4164 ata_promise_next_hpkt(struct ata_pci_controller *ctlr)
4165 {
4166 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
4167 struct host_packet *hp;
4168
4169 mtx_lock(&hpktp->mtx);
4170 if ((hp = TAILQ_FIRST(&hpktp->queue))) {
4171 TAILQ_REMOVE(&hpktp->queue, hp, chain);
4172 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr);
4173 free(hp, M_TEMP);
4174 }
4175 else
4176 hpktp->busy = 0;
4177 mtx_unlock(&hpktp->mtx);
4178 }
4179
4180
4181 /*
4182 * ServerWorks chipset support functions
4183 */
4184 int
4185 ata_serverworks_ident(device_t dev)
4186 {
4187 struct ata_pci_controller *ctlr = device_get_softc(dev);
4188 static struct ata_chip_id ids[] =
4189 {{ ATA_ROSB4, 0x00, SWKS33, 0, ATA_UDMA2, "ROSB4" },
4190 { ATA_CSB5, 0x92, SWKS100, 0, ATA_UDMA5, "CSB5" },
4191 { ATA_CSB5, 0x00, SWKS66, 0, ATA_UDMA4, "CSB5" },
4192 { ATA_CSB6, 0x00, SWKS100, 0, ATA_UDMA5, "CSB6" },
4193 { ATA_CSB6_1, 0x00, SWKS66, 0, ATA_UDMA4, "CSB6" },
4194 { ATA_HT1000, 0x00, SWKS100, 0, ATA_UDMA5, "HT1000" },
4195 { ATA_HT1000_S1, 0x00, SWKSMIO, 4, ATA_SA150, "HT1000" },
4196 { ATA_HT1000_S2, 0x00, SWKSMIO, 4, ATA_SA150, "HT1000" },
4197 { ATA_K2, 0x00, SWKSMIO, 4, ATA_SA150, "K2" },
4198 { ATA_FRODO4, 0x00, SWKSMIO, 4, ATA_SA150, "Frodo4" },
4199 { ATA_FRODO8, 0x00, SWKSMIO, 8, ATA_SA150, "Frodo8" },
4200 { 0, 0, 0, 0, 0, 0}};
4201
4202 if (!(ctlr->chip = ata_match_chip(dev, ids)))
4203 return ENXIO;
4204
4205 ata_set_desc(dev);
4206 ctlr->chipinit = ata_serverworks_chipinit;
4207 return 0;
4208 }
4209
4210 static int
4211 ata_serverworks_chipinit(device_t dev)
4212 {
4213 struct ata_pci_controller *ctlr = device_get_softc(dev);
4214
4215 if (ata_setup_interrupt(dev))
4216 return ENXIO;
4217
4218 if (ctlr->chip->cfg1 == SWKSMIO) {
4219 ctlr->r_type2 = SYS_RES_MEMORY;
4220 ctlr->r_rid2 = PCIR_BAR(5);
4221 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4222 &ctlr->r_rid2, RF_ACTIVE)))
4223 return ENXIO;
4224
4225 ctlr->channels = ctlr->chip->cfg2;
4226 ctlr->allocate = ata_serverworks_allocate;
4227 ctlr->setmode = ata_sata_setmode;
4228 return 0;
4229 }
4230 else if (ctlr->chip->cfg1 == SWKS33) {
4231 device_t *children;
4232 int nchildren, i;
4233
4234 /* locate the ISA part in the southbridge and enable UDMA33 */
4235 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
4236 for (i = 0; i < nchildren; i++) {
4237 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
4238 pci_write_config(children[i], 0x64,
4239 (pci_read_config(children[i], 0x64, 4) &
4240 ~0x00002000) | 0x00004000, 4);
4241 break;
4242 }
4243 }
4244 free(children, M_TEMP);
4245 }
4246 }
4247 else {
4248 pci_write_config(dev, 0x5a,
4249 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
4250 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1);
4251 }
4252 ctlr->setmode = ata_serverworks_setmode;
4253 return 0;
4254 }
4255
4256 static int
4257 ata_serverworks_allocate(device_t dev)
4258 {
4259 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4260 struct ata_channel *ch = device_get_softc(dev);
4261 int ch_offset;
4262 int i;
4263
4264 ch_offset = ch->unit * 0x100;
4265
4266 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
4267 ch->r_io[i].res = ctlr->r_res2;
4268
4269 /* setup ATA registers */
4270 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
4271 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04;
4272 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
4273 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
4274 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
4275 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
4276 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
4277 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c;
4278 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20;
4279 ata_default_registers(dev);
4280
4281 /* setup DMA registers */
4282 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30;
4283 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32;
4284 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34;
4285
4286 /* setup SATA registers */
4287 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40;
4288 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44;
4289 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48;
4290
4291 ch->flags |= ATA_NO_SLAVE;
4292 ata_pci_hw(dev);
4293 ch->hw.tf_read = ata_serverworks_tf_read;
4294 ch->hw.tf_write = ata_serverworks_tf_write;
4295
4296 /* chip does not reliably do 64K DMA transfers */
4297 if (ch->dma)
4298 ch->dma->max_iosize = 64 * DEV_BSIZE;
4299
4300 return 0;
4301 }
4302
4303 static void
4304 ata_serverworks_tf_read(struct ata_request *request)
4305 {
4306 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4307 struct ata_device *atadev = device_get_softc(request->dev);
4308
4309 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
4310 u_int16_t temp;
4311
4312 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT);
4313 temp = ATA_IDX_INW(ch, ATA_SECTOR);
4314 request->u.ata.lba = (u_int64_t)(temp & 0x00ff) |
4315 ((u_int64_t)(temp & 0xff00) << 24);
4316 temp = ATA_IDX_INW(ch, ATA_CYL_LSB);
4317 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 8) |
4318 ((u_int64_t)(temp & 0xff00) << 32);
4319 temp = ATA_IDX_INW(ch, ATA_CYL_MSB);
4320 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 16) |
4321 ((u_int64_t)(temp & 0xff00) << 40);
4322 }
4323 else {
4324 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT) & 0x00ff;
4325 request->u.ata.lba = (ATA_IDX_INW(ch, ATA_SECTOR) & 0x00ff) |
4326 ((ATA_IDX_INW(ch, ATA_CYL_LSB) & 0x00ff) << 8) |
4327 ((ATA_IDX_INW(ch, ATA_CYL_MSB) & 0x00ff) << 16) |
4328 ((ATA_IDX_INW(ch, ATA_DRIVE) & 0xf) << 24);
4329 }
4330 }
4331
4332 static void
4333 ata_serverworks_tf_write(struct ata_request *request)
4334 {
4335 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4336 struct ata_device *atadev = device_get_softc(request->dev);
4337
4338 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
4339 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
4340 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
4341 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) |
4342 (request->u.ata.lba & 0x00ff));
4343 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) |
4344 ((request->u.ata.lba >> 8) & 0x00ff));
4345 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) |
4346 ((request->u.ata.lba >> 16) & 0x00ff));
4347 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | atadev->unit);
4348 }
4349 else {
4350 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
4351 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
4352 if (atadev->flags & ATA_D_USE_CHS) {
4353 int heads, sectors;
4354
4355 if (atadev->param.atavalid & ATA_FLAG_54_58) {
4356 heads = atadev->param.current_heads;
4357 sectors = atadev->param.current_sectors;
4358 }
4359 else {
4360 heads = atadev->param.heads;
4361 sectors = atadev->param.sectors;
4362 }
4363 ATA_IDX_OUTW(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
4364 ATA_IDX_OUTW(ch, ATA_CYL_LSB,
4365 (request->u.ata.lba / (sectors * heads)));
4366 ATA_IDX_OUTW(ch, ATA_CYL_MSB,
4367 (request->u.ata.lba / (sectors * heads)) >> 8);
4368 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit |
4369 (((request->u.ata.lba% (sectors * heads)) /
4370 sectors) & 0xf));
4371 }
4372 else {
4373 ATA_IDX_OUTW(ch, ATA_SECTOR, request->u.ata.lba);
4374 ATA_IDX_OUTW(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
4375 ATA_IDX_OUTW(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
4376 ATA_IDX_OUTW(ch, ATA_DRIVE,
4377 ATA_D_IBM | ATA_D_LBA | atadev->unit |
4378 ((request->u.ata.lba >> 24) & 0x0f));
4379 }
4380 }
4381 }
4382
4383 static void
4384 ata_serverworks_setmode(device_t dev, int mode)
4385 {
4386 device_t gparent = GRANDPARENT(dev);
4387 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4388 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4389 struct ata_device *atadev = device_get_softc(dev);
4390 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4391 int offset = (devno ^ 0x01) << 3;
4392 int error;
4393 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
4394 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
4395 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
4396
4397 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4398
4399 mode = ata_check_80pin(dev, mode);
4400
4401 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4402
4403 if (bootverbose)
4404 device_printf(dev, "%ssetting %s on %s chip\n",
4405 (error) ? "FAILURE " : "",
4406 ata_mode2str(mode), ctlr->chip->text);
4407 if (!error) {
4408 if (mode >= ATA_UDMA0) {
4409 pci_write_config(gparent, 0x56,
4410 (pci_read_config(gparent, 0x56, 2) &
4411 ~(0xf << (devno << 2))) |
4412 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
4413 pci_write_config(gparent, 0x54,
4414 pci_read_config(gparent, 0x54, 1) |
4415 (0x01 << devno), 1);
4416 pci_write_config(gparent, 0x44,
4417 (pci_read_config(gparent, 0x44, 4) &
4418 ~(0xff << offset)) |
4419 (dmatimings[2] << offset), 4);
4420 }
4421 else if (mode >= ATA_WDMA0) {
4422 pci_write_config(gparent, 0x54,
4423 pci_read_config(gparent, 0x54, 1) &
4424 ~(0x01 << devno), 1);
4425 pci_write_config(gparent, 0x44,
4426 (pci_read_config(gparent, 0x44, 4) &
4427 ~(0xff << offset)) |
4428 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
4429 }
4430 else
4431 pci_write_config(gparent, 0x54,
4432 pci_read_config(gparent, 0x54, 1) &
4433 ~(0x01 << devno), 1);
4434
4435 pci_write_config(gparent, 0x40,
4436 (pci_read_config(gparent, 0x40, 4) &
4437 ~(0xff << offset)) |
4438 (piotimings[ata_mode2idx(mode)] << offset), 4);
4439 atadev->mode = mode;
4440 }
4441 }
4442
4443
4444 /*
4445 * Silicon Image Inc. (SiI) (former CMD) chipset support functions
4446 */
4447 int
4448 ata_sii_ident(device_t dev)
4449 {
4450 struct ata_pci_controller *ctlr = device_get_softc(dev);
4451 static struct ata_chip_id ids[] =
4452 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" },
4453 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" },
4454 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
4455 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
4456 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" },
4457 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
4458 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
4459 { ATA_SII3124, 0x00, SIIPRBIO, SII4CH, ATA_SA300, "SiI 3124" },
4460 { ATA_SII3132, 0x00, SIIPRBIO, 0, ATA_SA300, "SiI 3132" },
4461 { ATA_SII3132_1, 0x00, SIIPRBIO, 0, ATA_SA300, "SiI 3132" },
4462 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" },
4463 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" },
4464 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" },
4465 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" },
4466 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" },
4467 { 0, 0, 0, 0, 0, 0}};
4468
4469 if (!(ctlr->chip = ata_match_chip(dev, ids)))
4470 return ENXIO;
4471
4472 ata_set_desc(dev);
4473 ctlr->chipinit = ata_sii_chipinit;
4474 return 0;
4475 }
4476
4477 static int
4478 ata_sii_chipinit(device_t dev)
4479 {
4480 struct ata_pci_controller *ctlr = device_get_softc(dev);
4481
4482 if (ata_setup_interrupt(dev))
4483 return ENXIO;
4484
4485 switch (ctlr->chip->cfg1) {
4486 case SIIPRBIO:
4487 ctlr->r_type1 = SYS_RES_MEMORY;
4488 ctlr->r_rid1 = PCIR_BAR(0);
4489 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
4490 &ctlr->r_rid1, RF_ACTIVE)))
4491 return ENXIO;
4492
4493 ctlr->r_rid2 = PCIR_BAR(2);
4494 ctlr->r_type2 = SYS_RES_MEMORY;
4495 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4496 &ctlr->r_rid2, RF_ACTIVE))){
4497 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
4498 return ENXIO;
4499 }
4500 ctlr->allocate = ata_siiprb_allocate;
4501 ctlr->reset = ata_siiprb_reset;
4502 ctlr->dmainit = ata_siiprb_dmainit;
4503 ctlr->setmode = ata_sata_setmode;
4504 ctlr->channels = (ctlr->chip->cfg2 == SII4CH) ? 4 : 2;
4505
4506 /* reset controller */
4507 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
4508 DELAY(10000);
4509 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
4510
4511 /* enable PCI interrupt */
4512 pci_write_config(dev, PCIR_COMMAND,
4513 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
4514 break;
4515
4516 case SIIMEMIO:
4517 ctlr->r_type2 = SYS_RES_MEMORY;
4518 ctlr->r_rid2 = PCIR_BAR(5);
4519 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4520 &ctlr->r_rid2, RF_ACTIVE))) {
4521 if (ctlr->chip->chipid != ATA_SII0680 ||
4522 (pci_read_config(dev, 0x8a, 1) & 1))
4523 return ENXIO;
4524 }
4525
4526 if (ctlr->chip->cfg2 & SIISETCLK) {
4527 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4528 pci_write_config(dev, 0x8a,
4529 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
4530 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4531 device_printf(dev, "%s could not set ATA133 clock\n",
4532 ctlr->chip->text);
4533 }
4534
4535 /* if we have 4 channels enable the second set */
4536 if (ctlr->chip->cfg2 & SII4CH) {
4537 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
4538 ctlr->channels = 4;
4539 }
4540
4541 /* dont block interrupts from any channel */
4542 pci_write_config(dev, 0x48,
4543 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
4544
4545 /* enable PCI interrupt as BIOS might not */
4546 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
4547
4548 if (ctlr->r_res2)
4549 ctlr->allocate = ata_sii_allocate;
4550
4551 if (ctlr->chip->max_dma >= ATA_SA150) {
4552 ctlr->reset = ata_sii_reset;
4553 ctlr->setmode = ata_sata_setmode;
4554 }
4555 else
4556 ctlr->setmode = ata_sii_setmode;
4557 break;
4558
4559 default:
4560 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
4561 device_printf(dev, "HW has secondary channel disabled\n");
4562 ctlr->channels = 1;
4563 }
4564
4565 /* enable interrupt as BIOS might not */
4566 pci_write_config(dev, 0x71, 0x01, 1);
4567
4568 ctlr->allocate = ata_cmd_allocate;
4569 ctlr->setmode = ata_cmd_setmode;
4570 break;
4571 }
4572 return 0;
4573 }
4574
4575 static int
4576 ata_cmd_allocate(device_t dev)
4577 {
4578 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4579 struct ata_channel *ch = device_get_softc(dev);
4580
4581 /* setup the usual register normal pci style */
4582 if (ata_pci_allocate(dev))
4583 return ENXIO;
4584
4585 if (ctlr->chip->cfg2 & SIIINTR)
4586 ch->hw.status = ata_cmd_status;
4587
4588 return 0;
4589 }
4590
4591 static int
4592 ata_cmd_status(device_t dev)
4593 {
4594 struct ata_channel *ch = device_get_softc(dev);
4595 u_int8_t reg71;
4596
4597 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
4598 (ch->unit ? 0x08 : 0x04))) {
4599 pci_write_config(device_get_parent(ch->dev), 0x71,
4600 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
4601 return ata_pci_status(dev);
4602 }
4603 return 0;
4604 }
4605
4606 static void
4607 ata_cmd_setmode(device_t dev, int mode)
4608 {
4609 device_t gparent = GRANDPARENT(dev);
4610 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4611 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4612 struct ata_device *atadev = device_get_softc(dev);
4613 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4614 int error;
4615
4616 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4617
4618 mode = ata_check_80pin(dev, mode);
4619
4620 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4621
4622 if (bootverbose)
4623 device_printf(dev, "%ssetting %s on %s chip\n",
4624 (error) ? "FAILURE " : "",
4625 ata_mode2str(mode), ctlr->chip->text);
4626 if (!error) {
4627 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
4628 int ureg = ch->unit ? 0x7b : 0x73;
4629
4630 if (mode >= ATA_UDMA0) {
4631 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
4632 { 0x11, 0x42 }, { 0x25, 0x8a },
4633 { 0x15, 0x4a }, { 0x05, 0x0a } };
4634
4635 u_int8_t umode = pci_read_config(gparent, ureg, 1);
4636
4637 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
4638 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)];
4639 pci_write_config(gparent, ureg, umode, 1);
4640 }
4641 else if (mode >= ATA_WDMA0) {
4642 int dmatimings[] = { 0x87, 0x32, 0x3f };
4643
4644 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1);
4645 pci_write_config(gparent, ureg,
4646 pci_read_config(gparent, ureg, 1) &
4647 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4648 }
4649 else {
4650 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
4651 pci_write_config(gparent, treg,
4652 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
4653 pci_write_config(gparent, ureg,
4654 pci_read_config(gparent, ureg, 1) &
4655 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4656 }
4657 atadev->mode = mode;
4658 }
4659 }
4660
4661 static int
4662 ata_sii_allocate(device_t dev)
4663 {
4664 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4665 struct ata_channel *ch = device_get_softc(dev);
4666 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
4667 int i;
4668
4669 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
4670 ch->r_io[i].res = ctlr->r_res2;
4671 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
4672 }
4673 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
4674 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
4675 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
4676 ata_default_registers(dev);
4677
4678 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
4679 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
4680 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
4681 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
4682 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
4683 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
4684
4685 if (ctlr->chip->max_dma >= ATA_SA150) {
4686 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4687 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
4688 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4689 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
4690 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4691 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
4692 ch->flags |= ATA_NO_SLAVE;
4693
4694 /* enable PHY state change interrupt */
4695 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
4696 }
4697
4698 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) {
4699 /* work around errata in early chips */
4700 ch->dma->boundary = 8192;
4701 ch->dma->segsize = 15 * DEV_BSIZE;
4702 }
4703
4704 ata_pci_hw(dev);
4705 ch->hw.status = ata_sii_status;
4706 return 0;
4707 }
4708
4709 static int
4710 ata_sii_status(device_t dev)
4711 {
4712 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4713 struct ata_channel *ch = device_get_softc(dev);
4714 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8);
4715 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8);
4716
4717 /* do we have any PHY events ? */
4718 if (ctlr->chip->max_dma >= ATA_SA150 &&
4719 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
4720 ata_sata_phy_check_events(dev);
4721
4722 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
4723 return ata_pci_status(dev);
4724 else
4725 return 0;
4726 }
4727
4728 static void
4729 ata_sii_reset(device_t dev)
4730 {
4731 if (ata_sata_phy_reset(dev))
4732 ata_generic_reset(dev);
4733 }
4734
4735 static void
4736 ata_sii_setmode(device_t dev, int mode)
4737 {
4738 device_t gparent = GRANDPARENT(dev);
4739 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4740 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4741 struct ata_device *atadev = device_get_softc(dev);
4742 int rego = (ch->unit << 4) + (ATA_DEV(atadev->unit) << 1);
4743 int mreg = ch->unit ? 0x84 : 0x80;
4744 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2);
4745 int mval = pci_read_config(gparent, mreg, 1) & ~mask;
4746 int error;
4747
4748 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4749
4750 if (ctlr->chip->cfg2 & SIISETCLK) {
4751 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) &
4752 (ch->unit ? 0x02 : 0x01))) {
4753 ata_print_cable(dev, "controller");
4754 mode = ATA_UDMA2;
4755 }
4756 }
4757 else
4758 mode = ata_check_80pin(dev, mode);
4759
4760 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4761
4762 if (bootverbose)
4763 device_printf(dev, "%ssetting %s on %s chip\n",
4764 (error) ? "FAILURE " : "",
4765 ata_mode2str(mode), ctlr->chip->text);
4766 if (error)
4767 return;
4768
4769 if (mode >= ATA_UDMA0) {
4770 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
4771 u_int8_t ureg = 0xac + rego;
4772
4773 pci_write_config(gparent, mreg,
4774 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1);
4775 pci_write_config(gparent, ureg,
4776 (pci_read_config(gparent, ureg, 1) & ~0x3f) |
4777 udmatimings[mode & ATA_MODE_MASK], 1);
4778
4779 }
4780 else if (mode >= ATA_WDMA0) {
4781 u_int8_t dreg = 0xa8 + rego;
4782 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
4783
4784 pci_write_config(gparent, mreg,
4785 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1);
4786 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
4787
4788 }
4789 else {
4790 u_int8_t preg = 0xa4 + rego;
4791 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
4792
4793 pci_write_config(gparent, mreg,
4794 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1);
4795 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2);
4796 }
4797 atadev->mode = mode;
4798 }
4799
4800
4801 struct ata_siiprb_dma_prdentry {
4802 u_int64_t addr;
4803 u_int32_t count;
4804 u_int32_t control;
4805 } __packed;
4806
4807 struct ata_siiprb_ata_command {
4808 struct ata_siiprb_dma_prdentry prd[126];
4809 } __packed;
4810
4811 struct ata_siiprb_atapi_command {
4812 u_int8_t ccb[16];
4813 struct ata_siiprb_dma_prdentry prd[125];
4814 } __packed;
4815
4816 struct ata_siiprb_command {
4817 u_int16_t control;
4818 u_int16_t protocol_override;
4819 u_int32_t transfer_count;
4820 u_int8_t fis[24];
4821 union {
4822 struct ata_siiprb_ata_command ata;
4823 struct ata_siiprb_atapi_command atapi;
4824 } u;
4825 } __packed;
4826
4827 static int
4828 ata_siiprb_allocate(device_t dev)
4829 {
4830 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4831 struct ata_channel *ch = device_get_softc(dev);
4832 int offset = ch->unit * 0x2000;
4833
4834 /* set the SATA resources */
4835 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4836 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
4837 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4838 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
4839 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4840 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
4841 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
4842 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
4843
4844 ch->hw.begin_transaction = ata_siiprb_begin_transaction;
4845 ch->hw.end_transaction = ata_siiprb_end_transaction;
4846 ch->hw.status = ata_siiprb_status;
4847 ch->hw.command = NULL; /* not used here */
4848 return 0;
4849 }
4850
4851 static int
4852 ata_siiprb_status(device_t dev)
4853 {
4854 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4855 struct ata_channel *ch = device_get_softc(dev);
4856 u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044);
4857 int offset = ch->unit * 0x2000;
4858
4859 if (action & (1 << ch->unit)) {
4860 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
4861
4862 /* do we have any PHY events ? */
4863 ata_sata_phy_check_events(dev);
4864
4865 /* clear interrupt(s) */
4866 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
4867
4868 /* do we have any device action ? */
4869 return (istatus & 0x00000003);
4870 }
4871 return 0;
4872 }
4873
4874 static int
4875 ata_siiprb_begin_transaction(struct ata_request *request)
4876 {
4877 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
4878 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4879 struct ata_siiprb_command *prb;
4880 struct ata_siiprb_dma_prdentry *prd;
4881 int offset = ch->unit * 0x2000;
4882 u_int64_t prb_bus;
4883 int tag = 0, dummy;
4884
4885 /* SOS XXX */
4886 if (request->u.ata.command == ATA_DEVICE_RESET) {
4887 request->result = 0;
4888 return ATA_OP_FINISHED;
4889 }
4890
4891 /* check for 48 bit access and convert if needed */
4892 ata_modify_if_48bit(request);
4893
4894 /* get a piece of the workspace for this request */
4895 prb = (struct ata_siiprb_command *)
4896 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
4897
4898 /* set basic prd options ata/atapi etc etc */
4899 bzero(prb, sizeof(struct ata_siiprb_command));
4900
4901 /* setup the FIS for this request */
4902 if (!ata_request2fis_h2d(request, &prb->fis[0])) {
4903 device_printf(request->dev, "setting up SATA FIS failed\n");
4904 request->result = EIO;
4905 return ATA_OP_FINISHED;
4906 }
4907
4908 /* setup transfer type */
4909 if (request->flags & ATA_R_ATAPI) {
4910 struct ata_device *atadev = device_get_softc(request->dev);
4911
4912 bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16);
4913 if ((atadev->param.config & ATA_PROTO_MASK) == ATA_PROTO_ATAPI_12)
4914 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020);
4915 else
4916 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020);
4917 if (request->flags & ATA_R_READ)
4918 prb->control = htole16(0x0010);
4919 if (request->flags & ATA_R_WRITE)
4920 prb->control = htole16(0x0020);
4921 prd = &prb->u.atapi.prd[0];
4922 }
4923 else
4924 prd = &prb->u.ata.prd[0];
4925
4926 /* if request moves data setup and load SG list */
4927 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
4928 if (ch->dma->load(ch->dev, request->data, request->bytecount,
4929 request->flags & ATA_R_READ, prd, &dummy)) {
4930 device_printf(request->dev, "setting up DMA failed\n");
4931 request->result = EIO;
4932 return ATA_OP_FINISHED;
4933 }
4934 }
4935
4936 /* activate the prb */
4937 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
4938 ATA_OUTL(ctlr->r_res2,
4939 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
4940 ATA_OUTL(ctlr->r_res2,
4941 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
4942
4943 /* start the timeout */
4944 callout_reset(&request->callout, request->timeout * hz,
4945 (timeout_t*)ata_timeout, request);
4946 return ATA_OP_CONTINUES;
4947 }
4948
4949 static int
4950 ata_siiprb_end_transaction(struct ata_request *request)
4951 {
4952 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
4953 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4954 struct ata_siiprb_command *prb;
4955 int offset = ch->unit * 0x2000;
4956 int error, timeout, tag = 0;
4957
4958 /* kill the timeout */
4959 callout_stop(&request->callout);
4960
4961 prb = (struct ata_siiprb_command *)
4962 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
4963
4964 /* any controller errors flagged ? */
4965 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
4966 if (bootverbose)
4967 printf("ata_siiprb_end_transaction %s error=%08x\n",
4968 ata_cmd2str(request), error);
4969
4970 /* if device error status get details */
4971 if (error == 1 || error == 2) {
4972 request->status = prb->fis[2];
4973 if (request->status & ATA_S_ERROR)
4974 request->error = prb->fis[3];
4975 }
4976
4977 /* SOS XXX handle other controller errors here */
4978
4979 /* initialize port */
4980 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004);
4981
4982 /* poll for port ready */
4983 for (timeout = 0; timeout < 1000; timeout++) {
4984 DELAY(1000);
4985 if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000)
4986 break;
4987 }
4988 if (bootverbose) {
4989 if (timeout >= 1000)
4990 device_printf(ch->dev, "port initialize timeout\n");
4991 else
4992 device_printf(ch->dev, "port initialize time=%dms\n", timeout);
4993 }
4994 }
4995
4996 /* update progress */
4997 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
4998 if (request->flags & ATA_R_READ)
4999 request->donecount = prb->transfer_count;
5000 else
5001 request->donecount = request->bytecount;
5002 }
5003
5004 /* release SG list etc */
5005 ch->dma->unload(ch->dev);
5006
5007 return ATA_OP_FINISHED;
5008 }
5009
5010 static void
5011 ata_siiprb_reset(device_t dev)
5012 {
5013 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5014 struct ata_channel *ch = device_get_softc(dev);
5015 int offset = ch->unit * 0x2000;
5016 struct ata_siiprb_command *prb;
5017 u_int64_t prb_bus;
5018 u_int32_t status, signature;
5019 int timeout, tag = 0;
5020
5021 /* reset channel HW */
5022 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
5023 DELAY(1000);
5024 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
5025 DELAY(10000);
5026
5027 /* poll for channel ready */
5028 for (timeout = 0; timeout < 1000; timeout++) {
5029 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000)
5030 break;
5031 DELAY(1000);
5032 }
5033
5034 if (bootverbose) {
5035 if (timeout >= 1000)
5036 device_printf(ch->dev, "channel HW reset timeout\n");
5037 else
5038 device_printf(ch->dev, "channel HW reset time=%dms\n", timeout);
5039 }
5040
5041 /* reset phy */
5042 if (!ata_sata_phy_reset(dev)) {
5043 if (bootverbose)
5044 device_printf(ch->dev, "phy reset found no device\n");
5045 ch->devices = 0;
5046 goto finish;
5047 }
5048
5049 /* get a piece of the workspace for a soft reset request */
5050 prb = (struct ata_siiprb_command *)
5051 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
5052 bzero(prb, sizeof(struct ata_siiprb_command));
5053 prb->control = htole16(0x0080);
5054
5055 /* activate the soft reset prb */
5056 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
5057 ATA_OUTL(ctlr->r_res2,
5058 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
5059 ATA_OUTL(ctlr->r_res2,
5060 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
5061
5062 /* poll for command finished */
5063 for (timeout = 0; timeout < 10000; timeout++) {
5064 DELAY(1000);
5065 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
5066 break;
5067 }
5068 if (timeout >= 1000) {
5069 device_printf(ch->dev, "reset timeout - no device found\n");
5070 ch->devices = 0;
5071 goto finish;
5072 }
5073 if (bootverbose)
5074 device_printf(ch->dev, "soft reset exec time=%dms status=%08x\n",
5075 timeout, status);
5076
5077 /* find out whats there */
5078 prb = (struct ata_siiprb_command *)
5079 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
5080 signature =
5081 prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
5082 if (bootverbose)
5083 device_printf(ch->dev, "SIGNATURE=%08x\n", signature);
5084 switch (signature) {
5085 case 0x00000101:
5086 ch->devices = ATA_ATA_MASTER;
5087 break;
5088 case 0x96690101:
5089 ch->devices = ATA_PORTMULTIPLIER;
5090 device_printf(ch->dev, "Portmultipliers not supported yet\n");
5091 ch->devices = 0;
5092 break;
5093 case 0xeb140101:
5094 ch->devices = ATA_ATAPI_MASTER;
5095 break;
5096 default:
5097 ch->devices = 0;
5098 }
5099 if (bootverbose)
5100 device_printf(dev, "siiprb_reset devices=0x%b\n", ch->devices,
5101 "\2\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
5102
5103 finish:
5104 /* clear interrupt(s) */
5105 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
5106
5107 /* require explicit interrupt ack */
5108 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
5109
5110 /* 64bit mode */
5111 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
5112
5113 /* enable interrupts wanted */
5114 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
5115 }
5116
5117 static void
5118 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
5119 {
5120 struct ata_dmasetprd_args *args = xsc;
5121 struct ata_siiprb_dma_prdentry *prd = args->dmatab;
5122 int i;
5123
5124 if ((args->error = error))
5125 return;
5126
5127 for (i = 0; i < nsegs; i++) {
5128 prd[i].addr = htole64(segs[i].ds_addr);
5129 prd[i].count = htole32(segs[i].ds_len);
5130 }
5131 prd[i - 1].control = htole32(ATA_DMA_EOT);
5132 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
5133 args->nsegs = nsegs;
5134 }
5135
5136 static void
5137 ata_siiprb_dmainit(device_t dev)
5138 {
5139 struct ata_channel *ch = device_get_softc(dev);
5140
5141 ata_dmainit(dev);
5142 if (ch->dma) {
5143 /* note start and stop are not used here */
5144 ch->dma->setprd = ata_siiprb_dmasetprd;
5145 ch->dma->max_address = BUS_SPACE_MAXADDR;
5146 }
5147 }
5148
5149
5150 /*
5151 * Silicon Integrated Systems Corp. (SiS) chipset support functions
5152 */
5153 int
5154 ata_sis_ident(device_t dev)
5155 {
5156 struct ata_pci_controller *ctlr = device_get_softc(dev);
5157 struct ata_chip_id *idx;
5158 static struct ata_chip_id ids[] =
5159 {{ ATA_SIS182, 0x00, SISSATA, 0, ATA_SA150, "182" }, /* south */
5160 { ATA_SIS181, 0x00, SISSATA, 0, ATA_SA150, "181" }, /* south */
5161 { ATA_SIS180, 0x00, SISSATA, 0, ATA_SA150, "180" }, /* south */
5162 { ATA_SIS965, 0x00, SIS133NEW, 0, ATA_UDMA6, "965" }, /* south */
5163 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "964" }, /* south */
5164 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "963" }, /* south */
5165 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "962" }, /* south */
5166
5167 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */
5168 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */
5169 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */
5170 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */
5171
5172 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */
5173 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "633" }, /* unknown */
5174 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */
5175 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "630" }, /* 1chip */
5176 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "620" }, /* 1chip */
5177
5178 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "550" },
5179 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "540" },
5180 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "530" },
5181
5182 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "5513" },
5183 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "5513" },
5184 { 0, 0, 0, 0, 0, 0 }};
5185 char buffer[64];
5186 int found = 0;
5187
5188 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev))))
5189 return ENXIO;
5190
5191 if (idx->cfg2 && !found) {
5192 u_int8_t reg57 = pci_read_config(dev, 0x57, 1);
5193
5194 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1);
5195 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) {
5196 found = 1;
5197 idx->cfg1 = SIS133NEW;
5198 idx->max_dma = ATA_UDMA6;
5199 sprintf(buffer, "SiS 962/963 %s controller",
5200 ata_mode2str(idx->max_dma));
5201 }
5202 pci_write_config(dev, 0x57, reg57, 1);
5203 }
5204 if (idx->cfg2 && !found) {
5205 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1);
5206
5207 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1);
5208 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) {
5209 struct ata_chip_id id[] =
5210 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }};
5211
5212 found = 1;
5213 if (ata_find_chip(dev, id, pci_get_slot(dev))) {
5214 idx->cfg1 = SIS133OLD;
5215 idx->max_dma = ATA_UDMA6;
5216 }
5217 else {
5218 idx->cfg1 = SIS100NEW;
5219 idx->max_dma = ATA_UDMA5;
5220 }
5221 sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
5222 }
5223 pci_write_config(dev, 0x4a, reg4a, 1);
5224 }
5225 if (!found)
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