1 /*-
2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-acerlabs.c 206604 2010-04-14 15:29:32Z mav $");
29
30 #include "opt_ata.h"
31 #include <sys/param.h>
32 #include <sys/module.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/ata.h>
36 #include <sys/bus.h>
37 #include <sys/endian.h>
38 #include <sys/malloc.h>
39 #include <sys/lock.h>
40 #include <sys/mutex.h>
41 #include <sys/sema.h>
42 #include <sys/taskqueue.h>
43 #include <vm/uma.h>
44 #include <machine/stdarg.h>
45 #include <machine/resource.h>
46 #include <machine/bus.h>
47 #include <sys/rman.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/ata/ata-all.h>
51 #include <dev/ata/ata-pci.h>
52 #include <ata_if.h>
53
54 /* local prototypes */
55 static int ata_ali_chipinit(device_t dev);
56 static int ata_ali_ch_attach(device_t dev);
57 static int ata_ali_sata_ch_attach(device_t dev);
58 static void ata_ali_reset(device_t dev);
59 static int ata_ali_setmode(device_t dev, int target, int mode);
60
61 /* misc defines */
62 #define ALI_OLD 0x01
63 #define ALI_NEW 0x02
64 #define ALI_SATA 0x04
65
66 struct ali_sata_resources {
67 struct resource *bars[4];
68 };
69
70 /*
71 * Acer Labs Inc (ALI) chipset support functions
72 */
73 static int
74 ata_ali_probe(device_t dev)
75 {
76 struct ata_pci_controller *ctlr = device_get_softc(dev);
77 static struct ata_chip_id ids[] =
78 {{ ATA_ALI_5289, 0x00, 2, ALI_SATA, ATA_SA150, "M5289" },
79 { ATA_ALI_5288, 0x00, 4, ALI_SATA, ATA_SA300, "M5288" },
80 { ATA_ALI_5287, 0x00, 4, ALI_SATA, ATA_SA150, "M5287" },
81 { ATA_ALI_5281, 0x00, 2, ALI_SATA, ATA_SA150, "M5281" },
82 { ATA_ALI_5228, 0xc5, 0, ALI_NEW, ATA_UDMA6, "M5228" },
83 { ATA_ALI_5229, 0xc5, 0, ALI_NEW, ATA_UDMA6, "M5229" },
84 { ATA_ALI_5229, 0xc4, 0, ALI_NEW, ATA_UDMA5, "M5229" },
85 { ATA_ALI_5229, 0xc2, 0, ALI_NEW, ATA_UDMA4, "M5229" },
86 { ATA_ALI_5229, 0x20, 0, ALI_OLD, ATA_UDMA2, "M5229" },
87 { ATA_ALI_5229, 0x00, 0, ALI_OLD, ATA_WDMA2, "M5229" },
88 { 0, 0, 0, 0, 0, 0}};
89
90 if (pci_get_vendor(dev) != ATA_ACER_LABS_ID)
91 return ENXIO;
92
93 if (!(ctlr->chip = ata_match_chip(dev, ids)))
94 return ENXIO;
95
96 ata_set_desc(dev);
97 ctlr->chipinit = ata_ali_chipinit;
98 return (BUS_PROBE_DEFAULT);
99 }
100
101 static int
102 ata_ali_chipinit(device_t dev)
103 {
104 struct ata_pci_controller *ctlr = device_get_softc(dev);
105 struct ali_sata_resources *res;
106 int i, rid;
107
108 if (ata_setup_interrupt(dev, ata_generic_intr))
109 return ENXIO;
110
111 switch (ctlr->chip->cfg2) {
112 case ALI_SATA:
113 ctlr->channels = ctlr->chip->cfg1;
114 ctlr->ch_attach = ata_ali_sata_ch_attach;
115 ctlr->ch_detach = ata_pci_ch_detach;
116 ctlr->setmode = ata_sata_setmode;
117 ctlr->getrev = ata_sata_getrev;
118
119 /* AHCI mode is correctly supported only on the ALi 5288. */
120 if ((ctlr->chip->chipid == ATA_ALI_5288) &&
121 (ata_ahci_chipinit(dev) != ENXIO))
122 return 0;
123
124 /* Allocate resources for later use by channel attach routines. */
125 res = malloc(sizeof(struct ali_sata_resources), M_TEMP, M_WAITOK);
126 for (i = 0; i < 4; i++) {
127 rid = PCIR_BAR(i);
128 res->bars[i] = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
129 RF_ACTIVE);
130 if (res->bars[i] == NULL) {
131 device_printf(dev, "Failed to allocate BAR %d\n", i);
132 for (i--; i >=0; i--)
133 bus_release_resource(dev, SYS_RES_IOPORT,
134 PCIR_BAR(i), res->bars[i]);
135 free(res, M_TEMP);
136 }
137 }
138 ctlr->chipset_data = res;
139 break;
140
141 case ALI_NEW:
142 /* use device interrupt as byte count end */
143 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
144
145 /* enable cable detection and UDMA support on revisions < 0xc7 */
146 if (ctlr->chip->chiprev < 0xc7)
147 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) |
148 0x09, 1);
149
150 /* enable ATAPI UDMA mode (even if we are going to do PIO) */
151 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) |
152 (ctlr->chip->chiprev >= 0xc7 ? 0x03 : 0x01), 1);
153
154 /* only chips with revision > 0xc4 can do 48bit DMA */
155 if (ctlr->chip->chiprev <= 0xc4)
156 device_printf(dev,
157 "using PIO transfers above 137GB as workaround for "
158 "48bit DMA access bug, expect reduced performance\n");
159 ctlr->ch_attach = ata_ali_ch_attach;
160 ctlr->ch_detach = ata_pci_ch_detach;
161 ctlr->reset = ata_ali_reset;
162 ctlr->setmode = ata_ali_setmode;
163 break;
164
165 case ALI_OLD:
166 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
167 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
168 ctlr->setmode = ata_ali_setmode;
169 break;
170 }
171 return 0;
172 }
173
174 static int
175 ata_ali_ch_attach(device_t dev)
176 {
177 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
178 struct ata_channel *ch = device_get_softc(dev);
179
180 /* setup the usual register normal pci style */
181 if (ata_pci_ch_attach(dev))
182 return ENXIO;
183
184 if (ctlr->chip->cfg2 & ALI_NEW && ctlr->chip->chiprev < 0xc7)
185 ch->flags |= ATA_CHECKS_CABLE;
186 /* older chips can't do 48bit DMA transfers */
187 if (ctlr->chip->chiprev <= 0xc4) {
188 ch->flags |= ATA_NO_48BIT_DMA;
189 if (ch->dma.max_iosize > 256 * 512)
190 ch->dma.max_iosize = 256 * 512;
191 }
192
193 return 0;
194 }
195
196 static int
197 ata_ali_sata_ch_attach(device_t dev)
198 {
199 device_t parent = device_get_parent(dev);
200 struct ata_pci_controller *ctlr = device_get_softc(parent);
201 struct ata_channel *ch = device_get_softc(dev);
202 struct ali_sata_resources *res;
203 struct resource *io = NULL, *ctlio = NULL;
204 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
205 int i;
206
207 res = ctlr->chipset_data;
208 if (unit01) {
209 io = res->bars[2];
210 ctlio = res->bars[3];
211 } else {
212 io = res->bars[0];
213 ctlio = res->bars[1];
214 }
215 ata_pci_dmainit(dev);
216 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
217 ch->r_io[i].res = io;
218 ch->r_io[i].offset = i + (unit10 ? 8 : 0);
219 }
220 ch->r_io[ATA_CONTROL].res = ctlio;
221 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0);
222 ch->r_io[ATA_IDX_ADDR].res = io;
223 ata_default_registers(dev);
224 if (ctlr->r_res1) {
225 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
226 ch->r_io[i].res = ctlr->r_res1;
227 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
228 }
229 }
230 ch->flags |= ATA_NO_SLAVE;
231 ch->flags |= ATA_SATA;
232
233 /* XXX SOS PHY handling awkward in ALI chip not supported yet */
234 ata_pci_hw(dev);
235 return 0;
236 }
237
238 static void
239 ata_ali_reset(device_t dev)
240 {
241 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
242 struct ata_channel *ch = device_get_softc(dev);
243 device_t *children;
244 int nchildren, i;
245
246 ata_generic_reset(dev);
247
248 /*
249 * workaround for datacorruption bug found on at least SUN Blade-100
250 * find the ISA function on the southbridge and disable then enable
251 * the ATA channel tristate buffer
252 */
253 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) {
254 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) {
255 for (i = 0; i < nchildren; i++) {
256 if (pci_get_devid(children[i]) == ATA_ALI_1533) {
257 pci_write_config(children[i], 0x58,
258 pci_read_config(children[i], 0x58, 1) &
259 ~(0x04 << ch->unit), 1);
260 pci_write_config(children[i], 0x58,
261 pci_read_config(children[i], 0x58, 1) |
262 (0x04 << ch->unit), 1);
263 break;
264 }
265 }
266 free(children, M_TEMP);
267 }
268 }
269 }
270
271 static int
272 ata_ali_setmode(device_t dev, int target, int mode)
273 {
274 device_t parent = device_get_parent(dev);
275 struct ata_pci_controller *ctlr = device_get_softc(parent);
276 struct ata_channel *ch = device_get_softc(dev);
277 int devno = (ch->unit << 1) + target;
278 int piomode;
279 u_int32_t piotimings[] =
280 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
281 0x00310001, 0x006d0003, 0x00330001, 0x00310001 };
282 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d};
283 u_int32_t word54;
284
285 mode = min(mode, ctlr->chip->max_dma);
286
287 if (ctlr->chip->cfg2 & ALI_NEW && ctlr->chip->chiprev < 0xc7) {
288 if (mode > ATA_UDMA2 &&
289 pci_read_config(parent, 0x4a, 1) & (1 << ch->unit)) {
290 ata_print_cable(dev, "controller");
291 mode = ATA_UDMA2;
292 }
293 }
294 if (ctlr->chip->cfg2 & ALI_OLD) {
295 /* doesn't support ATAPI DMA on write */
296 ch->flags |= ATA_ATAPI_DMA_RO;
297 if (ch->devices & ATA_ATAPI_MASTER &&
298 ch->devices & ATA_ATAPI_SLAVE) {
299 /* doesn't support ATAPI DMA on two ATAPI devices */
300 device_printf(dev, "two atapi devices on this channel,"
301 " no DMA\n");
302 mode = min(mode, ATA_PIO_MAX);
303 }
304 }
305 /* Set UDMA mode */
306 word54 = pci_read_config(parent, 0x54, 4);
307 if (mode >= ATA_UDMA0) {
308 word54 &= ~(0x000f000f << (devno << 2));
309 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
310 piomode = ATA_PIO4;
311 }
312 else {
313 word54 &= ~(0x0008000f << (devno << 2));
314 piomode = mode;
315 }
316 pci_write_config(parent, 0x54, word54, 4);
317 /* Set PIO/WDMA mode */
318 pci_write_config(parent, 0x58 + (ch->unit << 2),
319 piotimings[ata_mode2idx(piomode)], 4);
320 return (mode);
321 }
322
323 ATA_DECLARE_DRIVER(ata_ali);
324 MODULE_DEPEND(ata_ali, ata_ahci, 1, 1, 1);
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