Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ata/chipsets/ata-ati.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/module.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/ata.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 #include <sys/malloc.h> 40 #include <sys/lock.h> 41 #include <sys/mutex.h> 42 #include <sys/sema.h> 43 #include <sys/taskqueue.h> 44 #include <vm/uma.h> 45 #include <machine/stdarg.h> 46 #include <machine/resource.h> 47 #include <machine/bus.h> 48 #include <sys/rman.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include <dev/ata/ata-all.h> 52 #include <dev/ata/ata-pci.h> 53 #include <ata_if.h> 54 55 /* local prototypes */ 56 static int ata_ati_chipinit(device_t dev); 57 static int ata_ati_dumb_ch_attach(device_t dev); 58 static int ata_ati_ixp700_ch_attach(device_t dev); 59 static int ata_ati_setmode(device_t dev, int target, int mode); 60 61 /* misc defines */ 62 #define SII_MEMIO 1 /* must match ata_siliconimage.c's definition */ 63 #define SII_BUG 0x04 /* must match ata_siliconimage.c's definition */ 64 65 #define ATI_SATA SII_MEMIO 66 #define ATI_PATA 0x02 67 #define ATI_AHCI 0x04 68 69 /* 70 * ATI chipset support functions 71 */ 72 static int 73 ata_ati_probe(device_t dev) 74 { 75 struct ata_pci_controller *ctlr = device_get_softc(dev); 76 static const struct ata_chip_id ids[] = 77 {{ ATA_ATI_IXP200, 0x00, ATI_PATA, 0, ATA_UDMA5, "IXP200" }, 78 { ATA_ATI_IXP300, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP300" }, 79 { ATA_ATI_IXP300_S1, 0x00, ATI_SATA, SII_BUG, ATA_SA150, "IXP300" }, 80 { ATA_ATI_IXP400, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP400" }, 81 { ATA_ATI_IXP400_S1, 0x00, ATI_SATA, SII_BUG, ATA_SA150, "IXP400" }, 82 { ATA_ATI_IXP400_S2, 0x00, ATI_SATA, SII_BUG, ATA_SA150, "IXP400" }, 83 { ATA_ATI_IXP600, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP600" }, 84 { ATA_ATI_IXP600_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP600" }, 85 { ATA_ATI_IXP700, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP700/800" }, 86 { ATA_ATI_IXP700_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 87 { ATA_ATI_IXP700_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 88 { ATA_ATI_IXP700_S3, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 89 { ATA_ATI_IXP700_S4, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 90 { ATA_ATI_IXP800_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP800" }, 91 { ATA_ATI_IXP800_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP800" }, 92 { ATA_AMD_HUDSON2, 0x00, ATI_PATA, 0, ATA_UDMA6, "Hudson-2" }, 93 { ATA_AMD_HUDSON2_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 94 { ATA_AMD_HUDSON2_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 95 { ATA_AMD_HUDSON2_S3, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 96 { ATA_AMD_HUDSON2_S4, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 97 { ATA_AMD_HUDSON2_S5, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 98 { 0, 0, 0, 0, 0, 0}}; 99 100 if (pci_get_vendor(dev) != ATA_AMD_ID && pci_get_vendor(dev) != ATA_ATI_ID) 101 return ENXIO; 102 103 if (!(ctlr->chip = ata_match_chip(dev, ids))) 104 return ENXIO; 105 106 switch (ctlr->chip->cfg1) { 107 case ATI_PATA: 108 ctlr->chipinit = ata_ati_chipinit; 109 break; 110 case ATI_SATA: 111 /* 112 * the ATI SATA controller is actually a SiI 3112 controller 113 */ 114 ctlr->chipinit = ata_sii_chipinit; 115 break; 116 case ATI_AHCI: 117 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) 118 return (ENXIO); 119 ctlr->chipinit = ata_ati_chipinit; 120 break; 121 } 122 123 ata_set_desc(dev); 124 return (BUS_PROBE_LOW_PRIORITY); 125 } 126 127 static int 128 ata_ati_chipinit(device_t dev) 129 { 130 struct ata_pci_controller *ctlr = device_get_softc(dev); 131 device_t smbdev; 132 uint8_t satacfg; 133 134 if (ata_setup_interrupt(dev, ata_generic_intr)) 135 return ENXIO; 136 137 if (ctlr->chip->cfg1 == ATI_AHCI) { 138 ctlr->ch_attach = ata_ati_dumb_ch_attach; 139 ctlr->setmode = ata_sata_setmode; 140 return (0); 141 } 142 switch (ctlr->chip->chipid) { 143 case ATA_ATI_IXP600: 144 /* IXP600 only has 1 PATA channel */ 145 ctlr->channels = 1; 146 break; 147 case ATA_ATI_IXP700: 148 /* 149 * When "combined mode" is enabled, an additional PATA channel is 150 * emulated with two SATA ports and appears on this device. 151 * This mode can only be detected via SMB controller. 152 */ 153 smbdev = pci_find_device(ATA_ATI_ID, 0x4385); 154 if (smbdev != NULL) { 155 satacfg = pci_read_config(smbdev, 0xad, 1); 156 if (bootverbose) 157 device_printf(dev, "SATA controller %s (%s%s channel)\n", 158 (satacfg & 0x01) == 0 ? "disabled" : "enabled", 159 (satacfg & 0x08) == 0 ? "" : "combined mode, ", 160 (satacfg & 0x10) == 0 ? "primary" : "secondary"); 161 ctlr->chipset_data = (void *)(uintptr_t)satacfg; 162 /* 163 * If SATA controller is enabled but combined mode is disabled, 164 * we have only one PATA channel. Ignore a non-existent channel. 165 */ 166 if ((satacfg & 0x09) == 0x01) 167 ctlr->ichannels &= ~(1 << ((satacfg & 0x10) >> 4)); 168 else { 169 ctlr->ch_attach = ata_ati_ixp700_ch_attach; 170 } 171 } 172 break; 173 } 174 175 ctlr->setmode = ata_ati_setmode; 176 return 0; 177 } 178 179 static int 180 ata_ati_dumb_ch_attach(device_t dev) 181 { 182 struct ata_channel *ch = device_get_softc(dev); 183 184 if (ata_pci_ch_attach(dev)) 185 return ENXIO; 186 ch->flags |= ATA_SATA; 187 return (0); 188 } 189 190 static int 191 ata_ati_ixp700_ch_attach(device_t dev) 192 { 193 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 194 struct ata_channel *ch = device_get_softc(dev); 195 uint8_t satacfg = (uint8_t)(uintptr_t)ctlr->chipset_data; 196 197 /* Setup the usual register normal pci style. */ 198 if (ata_pci_ch_attach(dev)) 199 return ENXIO; 200 201 /* One of channels is PATA, another is SATA. */ 202 if (ch->unit == ((satacfg & 0x10) >> 4)) 203 ch->flags |= ATA_SATA; 204 return (0); 205 } 206 207 static int 208 ata_ati_setmode(device_t dev, int target, int mode) 209 { 210 device_t parent = device_get_parent(dev); 211 struct ata_pci_controller *ctlr = device_get_softc(parent); 212 struct ata_channel *ch = device_get_softc(dev); 213 int devno = (ch->unit << 1) + target; 214 int offset = (devno ^ 0x01) << 3; 215 int piomode; 216 static const uint8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; 217 static const uint8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 218 219 mode = min(mode, ctlr->chip->max_dma); 220 if (mode >= ATA_UDMA0) { 221 /* Set UDMA mode, enable UDMA, set WDMA2/PIO4 */ 222 pci_write_config(parent, 0x56, 223 (pci_read_config(parent, 0x56, 2) & 224 ~(0xf << (devno << 2))) | 225 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 226 pci_write_config(parent, 0x54, 227 pci_read_config(parent, 0x54, 1) | 228 (0x01 << devno), 1); 229 pci_write_config(parent, 0x44, 230 (pci_read_config(parent, 0x44, 4) & 231 ~(0xff << offset)) | 232 (dmatimings[2] << offset), 4); 233 piomode = ATA_PIO4; 234 } else if (mode >= ATA_WDMA0) { 235 /* Disable UDMA, set WDMA mode and timings, calculate PIO. */ 236 pci_write_config(parent, 0x54, 237 pci_read_config(parent, 0x54, 1) & 238 ~(0x01 << devno), 1); 239 pci_write_config(parent, 0x44, 240 (pci_read_config(parent, 0x44, 4) & 241 ~(0xff << offset)) | 242 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 243 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 244 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 245 } else { 246 /* Disable UDMA, set requested PIO. */ 247 pci_write_config(parent, 0x54, 248 pci_read_config(parent, 0x54, 1) & 249 ~(0x01 << devno), 1); 250 piomode = mode; 251 } 252 /* Set PIO mode and timings, calculated above. */ 253 pci_write_config(parent, 0x4a, 254 (pci_read_config(parent, 0x4a, 2) & 255 ~(0xf << (devno << 2))) | 256 ((piomode - ATA_PIO0) << (devno<<2)),2); 257 pci_write_config(parent, 0x40, 258 (pci_read_config(parent, 0x40, 4) & 259 ~(0xff << offset)) | 260 (piotimings[ata_mode2idx(piomode)] << offset), 4); 261 return (mode); 262 } 263 264 ATA_DECLARE_DRIVER(ata_ati); 265 MODULE_DEPEND(ata_ati, ata_sii, 1, 1, 1);
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