Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ata/chipsets/ata-fsl.c
Version:
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012 The FreeBSD Foundation 5 * 6 * This software was developed by Oleksandr Rybalko under sponsorship 7 * from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/module.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/ata.h> 39 #include <sys/bus.h> 40 #include <sys/endian.h> 41 #include <sys/malloc.h> 42 #include <sys/lock.h> 43 #include <sys/mutex.h> 44 #include <sys/sema.h> 45 #include <sys/taskqueue.h> 46 #include <vm/uma.h> 47 #include <machine/stdarg.h> 48 #include <machine/resource.h> 49 #include <machine/bus.h> 50 #include <sys/rman.h> 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/ata/ata-all.h> 54 #include <dev/ata/ata-pci.h> 55 #include <ata_if.h> 56 57 #include <dev/fdt/fdt_common.h> 58 #include <dev/ofw/openfirm.h> 59 #include <dev/ofw/ofw_bus.h> 60 #include <dev/ofw/ofw_bus_subr.h> 61 62 #include <machine/fdt.h> 63 64 /* local prototypes */ 65 static int imx_ata_ch_attach(device_t dev); 66 static int imx_ata_setmode(device_t dev, int target, int mode); 67 68 static int 69 imx_ata_probe(device_t dev) 70 { 71 if (!ofw_bus_status_okay(dev)) 72 return (ENXIO); 73 74 if (!ofw_bus_is_compatible(dev, "fsl,imx51-ata") && 75 !ofw_bus_is_compatible(dev, "fsl,imx53-ata")) 76 return (ENXIO); 77 78 device_set_desc(dev, "Freescale Integrated PATA Controller"); 79 return (BUS_PROBE_LOW_PRIORITY); 80 } 81 82 static void 83 imx_ata_intr(void *data) 84 { 85 struct ata_pci_controller *ctrl = data; 86 87 bus_write_2(ctrl->r_res1, 0x28, bus_read_2(ctrl->r_res1, 0x28)); 88 ctrl->interrupt[0].function(ctrl->interrupt[0].argument); 89 } 90 91 static int 92 imx_ata_attach(device_t dev) 93 { 94 struct ata_pci_controller *ctrl; 95 device_t child; 96 int unit; 97 98 ctrl = device_get_softc(dev); 99 /* do chipset specific setups only needed once */ 100 ctrl->legacy = ata_legacy(dev); 101 ctrl->channels = 1; 102 ctrl->ichannels = -1; 103 ctrl->ch_attach = ata_pci_ch_attach; 104 ctrl->ch_detach = ata_pci_ch_detach; 105 ctrl->dev = dev; 106 107 ctrl->r_type1 = SYS_RES_MEMORY; 108 ctrl->r_rid1 = 0; 109 ctrl->r_res1 = bus_alloc_resource_any(dev, ctrl->r_type1, 110 &ctrl->r_rid1, RF_ACTIVE); 111 112 if (ata_setup_interrupt(dev, imx_ata_intr)) { 113 device_printf(dev, "failed to setup interrupt\n"); 114 return ENXIO; 115 } 116 117 ctrl->channels = 1; 118 119 ctrl->ch_attach = imx_ata_ch_attach; 120 ctrl->setmode = imx_ata_setmode; 121 122 /* attach all channels on this controller */ 123 unit = 0; 124 child = device_add_child(dev, "ata", ((unit == 0) && ctrl->legacy) ? 125 unit : devclass_find_free_unit(ata_devclass, 2)); 126 if (child == NULL) 127 device_printf(dev, "failed to add ata child device\n"); 128 else 129 device_set_ivars(child, (void *)(intptr_t)unit); 130 131 bus_generic_attach(dev); 132 return 0; 133 } 134 135 static int 136 imx_ata_ch_attach(device_t dev) 137 { 138 struct ata_pci_controller *ctrl; 139 struct ata_channel *ch; 140 int i; 141 142 ctrl = device_get_softc(device_get_parent(dev)); 143 ch = device_get_softc(dev); 144 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 145 ch->r_io[i].res = ctrl->r_res1; 146 147 bus_write_2(ctrl->r_res1, 0x24, 0x80); 148 DELAY(100); 149 bus_write_2(ctrl->r_res1, 0x24, 0xc0); 150 DELAY(100); 151 152 /* Write TIME_OFF/ON/1/2W */ 153 bus_write_1(ctrl->r_res1, 0x00, 3); 154 bus_write_1(ctrl->r_res1, 0x01, 3); 155 bus_write_1(ctrl->r_res1, 0x02, (25 + 15) / 15); 156 bus_write_1(ctrl->r_res1, 0x03, (70 + 15) / 15); 157 158 /* Write TIME_2R/AX/RDX/4 */ 159 bus_write_1(ctrl->r_res1, 0x04, (70 + 15) / 15); 160 bus_write_1(ctrl->r_res1, 0x05, (50 + 15) / 15 + 2); 161 bus_write_1(ctrl->r_res1, 0x06, 1); 162 bus_write_1(ctrl->r_res1, 0x07, (10 + 15) / 15); 163 164 /* Write TIME_9 ; the rest of timing registers is irrelevant for PIO */ 165 bus_write_1(ctrl->r_res1, 0x08, (10 + 15) / 15); 166 167 bus_write_2(ctrl->r_res1, 0x24, 0xc1); 168 DELAY(30000); 169 170 /* setup ATA registers */ 171 ch->r_io[ATA_DATA ].offset = 0xa0; 172 ch->r_io[ATA_FEATURE].offset = 0xa4; 173 ch->r_io[ATA_ERROR ].offset = 0xa4; 174 ch->r_io[ATA_COUNT ].offset = 0xa8; 175 ch->r_io[ATA_SECTOR ].offset = 0xac; 176 ch->r_io[ATA_CYL_LSB].offset = 0xb0; 177 ch->r_io[ATA_CYL_MSB].offset = 0xb4; 178 ch->r_io[ATA_DRIVE ].offset = 0xb8; 179 ch->r_io[ATA_COMMAND].offset = 0xbc; 180 181 ch->r_io[ATA_STATUS ].offset = 0xbc; 182 ch->r_io[ATA_ALTSTAT].offset = 0xd8; 183 ch->r_io[ATA_CONTROL].offset = 0xd8; 184 185 ata_pci_hw(dev); 186 187 ch->flags |= ATA_NO_SLAVE; 188 ch->flags |= ATA_USE_16BIT; 189 ch->flags |= ATA_CHECKS_CABLE; 190 ch->flags |= ATA_KNOWN_PRESENCE; 191 192 /* Clear pending interrupts. */ 193 bus_write_2(ctrl->r_res1, 0x28, 0xf8); 194 /* Enable all, but Idle interrupts. */ 195 bus_write_2(ctrl->r_res1, 0x2c, 0x88); 196 197 return 0; 198 } 199 200 static int 201 imx_ata_setmode(device_t dev, int target, int mode) 202 { 203 204 return (min(mode, ATA_PIO4)); 205 } 206 207 static device_method_t imx_ata_methods[] = { 208 DEVMETHOD(device_probe, imx_ata_probe), 209 DEVMETHOD(device_attach, imx_ata_attach), 210 DEVMETHOD(device_detach, ata_pci_detach), 211 DEVMETHOD(device_suspend, ata_pci_suspend), 212 DEVMETHOD(device_resume, ata_pci_resume), 213 DEVMETHOD(device_shutdown, bus_generic_shutdown), 214 DEVMETHOD(bus_read_ivar, ata_pci_read_ivar), 215 DEVMETHOD(bus_write_ivar, ata_pci_write_ivar), 216 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource), 217 DEVMETHOD(bus_release_resource, ata_pci_release_resource), 218 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 219 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 220 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr), 221 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr), 222 DEVMETHOD(pci_read_config, ata_pci_read_config), 223 DEVMETHOD(pci_write_config, ata_pci_write_config), 224 DEVMETHOD(bus_print_child, ata_pci_print_child), 225 DEVMETHOD(bus_child_location, ata_pci_child_location), 226 DEVMETHOD_END 227 }; 228 static driver_t imx_ata_driver = { 229 "atapci", 230 imx_ata_methods, 231 sizeof(struct ata_pci_controller) 232 }; 233 DRIVER_MODULE(imx_ata, simplebus, imx_ata_driver, NULL, NULL); 234 MODULE_VERSION(imx_ata, 1); 235 MODULE_DEPEND(imx_ata, ata, 1, 1, 1); 236 MODULE_DEPEND(imx_ata, atapci, 1, 1, 1);
Cache object: 698e3ab01a2491499f8fab8d3eccca0f
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