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sys/dev/ata/chipsets/ata-intel.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/module.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/ata.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 #include <sys/malloc.h> 40 #include <sys/lock.h> 41 #include <sys/mutex.h> 42 #include <sys/sema.h> 43 #include <sys/taskqueue.h> 44 #include <vm/uma.h> 45 #include <machine/stdarg.h> 46 #include <machine/resource.h> 47 #include <machine/bus.h> 48 #include <sys/rman.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include <dev/ata/ata-all.h> 52 #include <dev/ata/ata-pci.h> 53 #include <ata_if.h> 54 55 /* local prototypes */ 56 static int ata_intel_chipinit(device_t dev); 57 static int ata_intel_chipdeinit(device_t dev); 58 static int ata_intel_ch_attach(device_t dev); 59 static void ata_intel_reset(device_t dev); 60 static int ata_intel_old_setmode(device_t dev, int target, int mode); 61 static int ata_intel_new_setmode(device_t dev, int target, int mode); 62 static int ata_intel_sch_setmode(device_t dev, int target, int mode); 63 static int ata_intel_sata_getrev(device_t dev, int target); 64 static int ata_intel_sata_status(device_t dev); 65 static int ata_intel_sata_ahci_read(device_t dev, int port, 66 int reg, u_int32_t *result); 67 static int ata_intel_sata_cscr_read(device_t dev, int port, 68 int reg, u_int32_t *result); 69 static int ata_intel_sata_sidpr_read(device_t dev, int port, 70 int reg, u_int32_t *result); 71 static int ata_intel_sata_ahci_write(device_t dev, int port, 72 int reg, u_int32_t result); 73 static int ata_intel_sata_cscr_write(device_t dev, int port, 74 int reg, u_int32_t result); 75 static int ata_intel_sata_sidpr_write(device_t dev, int port, 76 int reg, u_int32_t result); 77 static int ata_intel_sata_sidpr_test(device_t dev); 78 static int ata_intel_31244_ch_attach(device_t dev); 79 static int ata_intel_31244_ch_detach(device_t dev); 80 static int ata_intel_31244_status(device_t dev); 81 static void ata_intel_31244_tf_write(struct ata_request *request); 82 static void ata_intel_31244_reset(device_t dev); 83 84 /* misc defines */ 85 #define INTEL_ICH5 2 86 #define INTEL_6CH 4 87 #define INTEL_6CH2 8 88 #define INTEL_ICH7 16 89 90 struct ata_intel_data { 91 struct mtx lock; 92 u_char smap[4]; 93 }; 94 95 #define ATA_INTEL_SMAP(ctlr, ch) \ 96 &((struct ata_intel_data *)((ctlr)->chipset_data))->smap[(ch)->unit * 2] 97 #define ATA_INTEL_LOCK(ctlr) \ 98 mtx_lock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock) 99 #define ATA_INTEL_UNLOCK(ctlr) \ 100 mtx_unlock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock) 101 102 /* 103 * Intel chipset support functions 104 */ 105 static int 106 ata_intel_probe(device_t dev) 107 { 108 struct ata_pci_controller *ctlr = device_get_softc(dev); 109 static const struct ata_chip_id ids[] = 110 {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" }, 111 { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" }, 112 { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 113 { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 114 { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 115 { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" }, 116 { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" }, 117 { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" }, 118 { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" }, 119 { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" }, 120 { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" }, 121 { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" }, 122 { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" }, 123 { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" }, 124 { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" }, 125 { ATA_I82801EB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 126 { ATA_I82801EB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 127 { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" }, 128 { ATA_I6300ESB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 129 { ATA_I6300ESB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 130 { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" }, 131 { ATA_I82801FB_S1, 0, 0, 0, ATA_SA150, "ICH6" }, 132 { ATA_I82801FB_R1, 0, 0, 0, ATA_SA150, "ICH6" }, 133 { ATA_I82801FBM, 0, 0, 0, ATA_SA150, "ICH6M" }, 134 { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" }, 135 { ATA_I82801GB_S1, 0, INTEL_ICH7, 0, ATA_SA300, "ICH7" }, 136 { ATA_I82801GBM_S1, 0, INTEL_ICH7, 0, ATA_SA150, "ICH7M" }, 137 { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" }, 138 { ATA_I63XXESB2_S1, 0, 0, 0, ATA_SA300, "63XXESB2" }, 139 { ATA_I82801HB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8" }, 140 { ATA_I82801HB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH8" }, 141 { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" }, 142 { ATA_I82801HBM_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8M" }, 143 { ATA_I82801IB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH9" }, 144 { ATA_I82801IB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 145 { ATA_I82801IB_S3, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 146 { ATA_I82801IBM_S1, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, 147 { ATA_I82801IBM_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, 148 { ATA_I82801JIB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 149 { ATA_I82801JIB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 150 { ATA_I82801JD_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 151 { ATA_I82801JD_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 152 { ATA_I82801JI_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 153 { ATA_I82801JI_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 154 { ATA_IBP_S1, 0, INTEL_6CH, 0, ATA_SA300, "Ibex Peak" }, 155 { ATA_IBP_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Ibex Peak" }, 156 { ATA_IBP_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Ibex Peak" }, 157 { ATA_IBP_S4, 0, INTEL_6CH, 0, ATA_SA300, "Ibex Peak-M" }, 158 { ATA_IBP_S5, 0, INTEL_6CH2, 0, ATA_SA300, "Ibex Peak-M" }, 159 { ATA_IBP_S6, 0, INTEL_6CH, 0, ATA_SA300, "Ibex Peak-M" }, 160 { ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA600, "Cougar Point" }, 161 { ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA600, "Cougar Point" }, 162 { ATA_CPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 163 { ATA_CPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 164 { ATA_PBG_S1, 0, INTEL_6CH, 0, ATA_SA600, "Patsburg" }, 165 { ATA_PBG_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Patsburg" }, 166 { ATA_PPT_S1, 0, INTEL_6CH, 0, ATA_SA600, "Panther Point" }, 167 { ATA_PPT_S2, 0, INTEL_6CH, 0, ATA_SA600, "Panther Point" }, 168 { ATA_PPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 169 { ATA_PPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 170 { ATA_AVOTON_S1, 0, INTEL_6CH, 0, ATA_SA600, "Avoton" }, 171 { ATA_AVOTON_S2, 0, INTEL_6CH, 0, ATA_SA600, "Avoton" }, 172 { ATA_AVOTON_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Avoton" }, 173 { ATA_AVOTON_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Avoton" }, 174 { ATA_LPT_S1, 0, INTEL_6CH, 0, ATA_SA600, "Lynx Point" }, 175 { ATA_LPT_S2, 0, INTEL_6CH, 0, ATA_SA600, "Lynx Point" }, 176 { ATA_LPT_S3, 0, INTEL_6CH2, 0, ATA_SA600, "Lynx Point" }, 177 { ATA_LPT_S4, 0, INTEL_6CH2, 0, ATA_SA600, "Lynx Point" }, 178 { ATA_WCPT_S1, 0, INTEL_6CH, 0, ATA_SA600, "Wildcat Point" }, 179 { ATA_WCPT_S2, 0, INTEL_6CH, 0, ATA_SA600, "Wildcat Point" }, 180 { ATA_WCPT_S3, 0, INTEL_6CH2, 0, ATA_SA600, "Wildcat Point" }, 181 { ATA_WCPT_S4, 0, INTEL_6CH2, 0, ATA_SA600, "Wildcat Point" }, 182 { ATA_WELLS_S1, 0, INTEL_6CH, 0, ATA_SA600, "Wellsburg" }, 183 { ATA_WELLS_S2, 0, INTEL_6CH2, 0, ATA_SA600, "Wellsburg" }, 184 { ATA_WELLS_S3, 0, INTEL_6CH, 0, ATA_SA600, "Wellsburg" }, 185 { ATA_WELLS_S4, 0, INTEL_6CH2, 0, ATA_SA600, "Wellsburg" }, 186 { ATA_LPTLP_S1, 0, INTEL_6CH, 0, ATA_SA600, "Lynx Point-LP" }, 187 { ATA_LPTLP_S2, 0, INTEL_6CH, 0, ATA_SA600, "Lynx Point-LP" }, 188 { ATA_LPTLP_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point-LP" }, 189 { ATA_LPTLP_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point-LP" }, 190 { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" }, 191 { ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" }, 192 { ATA_COLETOCRK_S1, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" }, 193 { ATA_COLETOCRK_S2, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" }, 194 { 0, 0, 0, 0, 0, 0}}; 195 196 if (pci_get_vendor(dev) != ATA_INTEL_ID) 197 return ENXIO; 198 199 if (!(ctlr->chip = ata_match_chip(dev, ids))) 200 return ENXIO; 201 202 ata_set_desc(dev); 203 ctlr->chipinit = ata_intel_chipinit; 204 ctlr->chipdeinit = ata_intel_chipdeinit; 205 return (BUS_PROBE_LOW_PRIORITY); 206 } 207 208 static int 209 ata_intel_chipinit(device_t dev) 210 { 211 struct ata_pci_controller *ctlr = device_get_softc(dev); 212 struct ata_intel_data *data; 213 214 if (ata_setup_interrupt(dev, ata_generic_intr)) 215 return ENXIO; 216 217 data = malloc(sizeof(struct ata_intel_data), M_ATAPCI, M_WAITOK | M_ZERO); 218 mtx_init(&data->lock, "Intel SATA lock", NULL, MTX_DEF); 219 ctlr->chipset_data = (void *)data; 220 221 /* good old PIIX needs special treatment (not implemented) */ 222 if (ctlr->chip->chipid == ATA_I82371FB) { 223 ctlr->setmode = ata_intel_old_setmode; 224 } 225 226 /* the intel 31244 needs special care if in DPA mode */ 227 else if (ctlr->chip->chipid == ATA_I31244) { 228 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 229 ctlr->r_type2 = SYS_RES_MEMORY; 230 ctlr->r_rid2 = PCIR_BAR(0); 231 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 232 &ctlr->r_rid2, 233 RF_ACTIVE))) 234 return ENXIO; 235 ctlr->channels = 4; 236 ctlr->ch_attach = ata_intel_31244_ch_attach; 237 ctlr->ch_detach = ata_intel_31244_ch_detach; 238 ctlr->reset = ata_intel_31244_reset; 239 } 240 ctlr->setmode = ata_sata_setmode; 241 ctlr->getrev = ata_sata_getrev; 242 } 243 /* SCH */ 244 else if (ctlr->chip->chipid == ATA_ISCH) { 245 ctlr->channels = 1; 246 ctlr->ch_attach = ata_intel_ch_attach; 247 ctlr->ch_detach = ata_pci_ch_detach; 248 ctlr->setmode = ata_intel_sch_setmode; 249 } 250 /* non SATA intel chips goes here */ 251 else if (ctlr->chip->max_dma < ATA_SA150) { 252 ctlr->channels = ctlr->chip->cfg2; 253 ctlr->ch_attach = ata_intel_ch_attach; 254 ctlr->ch_detach = ata_pci_ch_detach; 255 ctlr->setmode = ata_intel_new_setmode; 256 } 257 258 /* SATA parts can be either compat or AHCI */ 259 else { 260 /* force all ports active "the legacy way" */ 261 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2); 262 263 ctlr->ch_attach = ata_intel_ch_attach; 264 ctlr->ch_detach = ata_pci_ch_detach; 265 ctlr->reset = ata_intel_reset; 266 267 /* BAR(5) may point to SATA interface registers */ 268 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 269 ctlr->r_type2 = SYS_RES_MEMORY; 270 ctlr->r_rid2 = PCIR_BAR(5); 271 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 272 &ctlr->r_rid2, RF_ACTIVE); 273 if (ctlr->r_res2 != NULL) { 274 /* Set SCRAE bit to enable registers access. */ 275 pci_write_config(dev, 0x94, 276 pci_read_config(dev, 0x94, 4) | (1 << 9), 4); 277 /* Set Ports Implemented register bits. */ 278 ATA_OUTL(ctlr->r_res2, 0x0C, 279 ATA_INL(ctlr->r_res2, 0x0C) | 0xf); 280 } 281 /* Skip BAR(5) on ICH8M Apples, system locks up on access. */ 282 } else if (ctlr->chip->chipid != ATA_I82801HBM_S1 || 283 pci_get_subvendor(dev) != 0x106b) { 284 ctlr->r_type2 = SYS_RES_IOPORT; 285 ctlr->r_rid2 = PCIR_BAR(5); 286 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 287 &ctlr->r_rid2, RF_ACTIVE); 288 } 289 if (ctlr->r_res2 != NULL || 290 (ctlr->chip->cfg1 & INTEL_ICH5)) 291 ctlr->getrev = ata_intel_sata_getrev; 292 ctlr->setmode = ata_sata_setmode; 293 } 294 return 0; 295 } 296 297 static int 298 ata_intel_chipdeinit(device_t dev) 299 { 300 struct ata_pci_controller *ctlr = device_get_softc(dev); 301 struct ata_intel_data *data; 302 303 data = ctlr->chipset_data; 304 mtx_destroy(&data->lock); 305 free(data, M_ATAPCI); 306 ctlr->chipset_data = NULL; 307 return (0); 308 } 309 310 static int 311 ata_intel_ch_attach(device_t dev) 312 { 313 struct ata_pci_controller *ctlr; 314 struct ata_channel *ch; 315 u_char *smap; 316 u_int map; 317 318 /* setup the usual register normal pci style */ 319 if (ata_pci_ch_attach(dev)) 320 return (ENXIO); 321 322 ctlr = device_get_softc(device_get_parent(dev)); 323 ch = device_get_softc(dev); 324 325 /* if r_res2 is valid it points to SATA interface registers */ 326 if (ctlr->r_res2) { 327 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 328 ch->r_io[ATA_IDX_ADDR].offset = 0x00; 329 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; 330 ch->r_io[ATA_IDX_DATA].offset = 0x04; 331 } 332 333 ch->flags |= ATA_ALWAYS_DMASTAT; 334 if (ctlr->chip->max_dma >= ATA_SA150) { 335 smap = ATA_INTEL_SMAP(ctlr, ch); 336 map = pci_read_config(device_get_parent(dev), 0x90, 1); 337 if (ctlr->chip->cfg1 & INTEL_ICH5) { 338 map &= 0x07; 339 if ((map & 0x04) == 0) { 340 ch->flags |= ATA_SATA; 341 ch->flags |= ATA_NO_SLAVE; 342 smap[0] = (map & 0x01) ^ ch->unit; 343 smap[1] = 0; 344 } else if ((map & 0x02) == 0 && ch->unit == 0) { 345 ch->flags |= ATA_SATA; 346 smap[0] = (map & 0x01) ? 1 : 0; 347 smap[1] = (map & 0x01) ? 0 : 1; 348 } else if ((map & 0x02) != 0 && ch->unit == 1) { 349 ch->flags |= ATA_SATA; 350 smap[0] = (map & 0x01) ? 1 : 0; 351 smap[1] = (map & 0x01) ? 0 : 1; 352 } 353 } else if (ctlr->chip->cfg1 & INTEL_6CH2) { 354 ch->flags |= ATA_SATA; 355 ch->flags |= ATA_NO_SLAVE; 356 smap[0] = (ch->unit == 0) ? 0 : 1; 357 smap[1] = 0; 358 } else { 359 map &= 0x03; 360 if (map == 0x00) { 361 ch->flags |= ATA_SATA; 362 smap[0] = (ch->unit == 0) ? 0 : 1; 363 smap[1] = (ch->unit == 0) ? 2 : 3; 364 } else if (map == 0x02 && ch->unit == 0) { 365 ch->flags |= ATA_SATA; 366 smap[0] = 0; 367 smap[1] = 2; 368 } else if (map == 0x01 && ch->unit == 1) { 369 ch->flags |= ATA_SATA; 370 smap[0] = 1; 371 smap[1] = 3; 372 } 373 } 374 if (ch->flags & ATA_SATA) { 375 if ((ctlr->chip->cfg1 & INTEL_ICH5)) { 376 ch->hw.pm_read = ata_intel_sata_cscr_read; 377 ch->hw.pm_write = ata_intel_sata_cscr_write; 378 } else if (ctlr->r_res2) { 379 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 380 ch->hw.pm_read = ata_intel_sata_ahci_read; 381 ch->hw.pm_write = ata_intel_sata_ahci_write; 382 } else if (ata_intel_sata_sidpr_test(dev)) { 383 ch->hw.pm_read = ata_intel_sata_sidpr_read; 384 ch->hw.pm_write = ata_intel_sata_sidpr_write; 385 } 386 } 387 if (ch->hw.pm_write != NULL) { 388 ch->flags |= ATA_PERIODIC_POLL; 389 ch->hw.status = ata_intel_sata_status; 390 ata_sata_scr_write(ch, 0, 391 ATA_SERROR, 0xffffffff); 392 if ((ch->flags & ATA_NO_SLAVE) == 0) { 393 ata_sata_scr_write(ch, 1, 394 ATA_SERROR, 0xffffffff); 395 } 396 } 397 } else 398 ctlr->setmode = ata_intel_new_setmode; 399 if (ctlr->chip->max_dma >= ATA_SA600) 400 ch->flags |= ATA_USE_16BIT; 401 } else if (ctlr->chip->chipid != ATA_ISCH) 402 ch->flags |= ATA_CHECKS_CABLE; 403 return (0); 404 } 405 406 static void 407 ata_intel_reset(device_t dev) 408 { 409 device_t parent = device_get_parent(dev); 410 struct ata_pci_controller *ctlr = device_get_softc(parent); 411 struct ata_channel *ch = device_get_softc(dev); 412 int mask, pshift, timeout, devs; 413 u_char *smap; 414 uint16_t pcs; 415 416 /* In combined mode, skip SATA stuff for PATA channel. */ 417 if ((ch->flags & ATA_SATA) == 0) 418 return (ata_generic_reset(dev)); 419 420 /* Do hard-reset on respective SATA ports. */ 421 smap = ATA_INTEL_SMAP(ctlr, ch); 422 mask = 1 << smap[0]; 423 if ((ch->flags & ATA_NO_SLAVE) == 0) 424 mask |= (1 << smap[1]); 425 pci_write_config(parent, 0x92, 426 pci_read_config(parent, 0x92, 2) & ~mask, 2); 427 DELAY(100); 428 pci_write_config(parent, 0x92, 429 pci_read_config(parent, 0x92, 2) | mask, 2); 430 431 /* Wait up to 1 sec for "connect well". */ 432 if (ctlr->chip->cfg1 & (INTEL_6CH | INTEL_6CH2)) 433 pshift = 8; 434 else 435 pshift = 4; 436 for (timeout = 0; timeout < 100 ; timeout++) { 437 pcs = (pci_read_config(parent, 0x92, 2) >> pshift) & mask; 438 if ((pcs == mask) && (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 439 break; 440 ata_udelay(10000); 441 } 442 443 if (bootverbose) 444 device_printf(dev, "SATA reset: ports status=0x%02x\n", pcs); 445 /* If any device found, do soft-reset. */ 446 if (ch->hw.pm_read != NULL) { 447 devs = ata_sata_phy_reset(dev, 0, 2) ? ATA_ATA_MASTER : 0; 448 if ((ch->flags & ATA_NO_SLAVE) == 0) 449 devs |= ata_sata_phy_reset(dev, 1, 2) ? 450 ATA_ATA_SLAVE : 0; 451 } else { 452 devs = (pcs & (1 << smap[0])) ? ATA_ATA_MASTER : 0; 453 if ((ch->flags & ATA_NO_SLAVE) == 0) 454 devs |= (pcs & (1 << smap[1])) ? 455 ATA_ATA_SLAVE : 0; 456 } 457 if (devs) { 458 ata_generic_reset(dev); 459 /* Reset may give fake slave when only ATAPI master present. */ 460 ch->devices &= (devs | (devs * ATA_ATAPI_MASTER)); 461 } else 462 ch->devices = 0; 463 } 464 465 static int 466 ata_intel_old_setmode(device_t dev, int target, int mode) 467 { 468 device_t parent = device_get_parent(dev); 469 struct ata_pci_controller *ctlr = device_get_softc(parent); 470 471 mode = min(mode, ctlr->chip->max_dma); 472 return (mode); 473 } 474 475 static int 476 ata_intel_new_setmode(device_t dev, int target, int mode) 477 { 478 device_t parent = device_get_parent(dev); 479 struct ata_pci_controller *ctlr = device_get_softc(parent); 480 struct ata_channel *ch = device_get_softc(dev); 481 int devno = (ch->unit << 1) + target; 482 int piomode; 483 u_int32_t reg40 = pci_read_config(parent, 0x40, 4); 484 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 485 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 486 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 487 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 488 u_int32_t mask40 = 0, new40 = 0; 489 u_int8_t mask44 = 0, new44 = 0; 490 static const uint8_t timings[] = 491 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 492 static const uint8_t utimings[] = 493 { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 494 495 /* In combined mode, skip PATA stuff for SATA channel. */ 496 if (ch->flags & ATA_SATA) 497 return (ata_sata_setmode(dev, target, mode)); 498 499 mode = min(mode, ctlr->chip->max_dma); 500 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 501 !(reg54 & (0x10 << devno))) { 502 ata_print_cable(dev, "controller"); 503 mode = ATA_UDMA2; 504 } 505 /* Enable/disable UDMA and set timings. */ 506 if (mode >= ATA_UDMA0) { 507 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2); 508 pci_write_config(parent, 0x4a, 509 (reg4a & ~(0x3 << (devno << 2))) | 510 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2); 511 piomode = ATA_PIO4; 512 } else { 513 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2); 514 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2); 515 piomode = mode; 516 } 517 reg54 |= 0x0400; 518 /* Set UDMA reference clock (33/66/133MHz). */ 519 reg54 &= ~(0x1001 << devno); 520 if (mode >= ATA_UDMA5) 521 reg54 |= (0x1000 << devno); 522 else if (mode >= ATA_UDMA3) 523 reg54 |= (0x1 << devno); 524 pci_write_config(parent, 0x54, reg54, 2); 525 /* Allow PIO/WDMA timing controls. */ 526 reg40 &= ~0x00ff00ff; 527 reg40 |= 0x40774077; 528 /* Set PIO/WDMA timings. */ 529 if (target == 0) { 530 mask40 = 0x3300; 531 new40 = timings[ata_mode2idx(piomode)] << 8; 532 } else { 533 mask44 = 0x0f; 534 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 535 (timings[ata_mode2idx(piomode)] & 0x03); 536 } 537 if (ch->unit) { 538 mask40 <<= 16; 539 new40 <<= 16; 540 mask44 <<= 4; 541 new44 <<= 4; 542 } 543 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 544 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 545 return (mode); 546 } 547 548 static int 549 ata_intel_sch_setmode(device_t dev, int target, int mode) 550 { 551 device_t parent = device_get_parent(dev); 552 struct ata_pci_controller *ctlr = device_get_softc(parent); 553 u_int8_t dtim = 0x80 + (target << 2); 554 u_int32_t tim = pci_read_config(parent, dtim, 4); 555 int piomode; 556 557 mode = min(mode, ctlr->chip->max_dma); 558 if (mode >= ATA_UDMA0) { 559 tim |= (0x1 << 31); 560 tim &= ~(0x7 << 16); 561 tim |= ((mode & ATA_MODE_MASK) << 16); 562 piomode = ATA_PIO4; 563 } else if (mode >= ATA_WDMA0) { 564 tim &= ~(0x1 << 31); 565 tim &= ~(0x3 << 8); 566 tim |= ((mode & ATA_MODE_MASK) << 8); 567 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 568 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 569 } else 570 piomode = mode; 571 tim &= ~(0x7); 572 tim |= (piomode & 0x7); 573 pci_write_config(parent, dtim, tim, 4); 574 return (mode); 575 } 576 577 static int 578 ata_intel_sata_getrev(device_t dev, int target) 579 { 580 struct ata_channel *ch = device_get_softc(dev); 581 uint32_t status; 582 583 if (ata_sata_scr_read(ch, target, ATA_SSTATUS, &status) == 0) 584 return ((status & 0x0f0) >> 4); 585 return (0xff); 586 } 587 588 static int 589 ata_intel_sata_status(device_t dev) 590 { 591 struct ata_channel *ch = device_get_softc(dev); 592 593 ata_sata_phy_check_events(dev, 0); 594 if ((ch->flags & ATA_NO_SLAVE) == 0) 595 ata_sata_phy_check_events(dev, 1); 596 597 return ata_pci_status(dev); 598 } 599 600 static int 601 ata_intel_sata_ahci_read(device_t dev, int port, int reg, u_int32_t *result) 602 { 603 struct ata_pci_controller *ctlr; 604 struct ata_channel *ch; 605 device_t parent; 606 u_char *smap; 607 int offset; 608 609 parent = device_get_parent(dev); 610 ctlr = device_get_softc(parent); 611 ch = device_get_softc(dev); 612 port = (port == 1) ? 1 : 0; 613 smap = ATA_INTEL_SMAP(ctlr, ch); 614 offset = 0x100 + smap[port] * 0x80; 615 switch (reg) { 616 case ATA_SSTATUS: 617 reg = 0x28; 618 break; 619 case ATA_SCONTROL: 620 reg = 0x2c; 621 break; 622 case ATA_SERROR: 623 reg = 0x30; 624 break; 625 default: 626 return (EINVAL); 627 } 628 *result = ATA_INL(ctlr->r_res2, offset + reg); 629 return (0); 630 } 631 632 static int 633 ata_intel_sata_cscr_read(device_t dev, int port, int reg, u_int32_t *result) 634 { 635 struct ata_pci_controller *ctlr; 636 struct ata_channel *ch; 637 device_t parent; 638 u_char *smap; 639 640 parent = device_get_parent(dev); 641 ctlr = device_get_softc(parent); 642 ch = device_get_softc(dev); 643 smap = ATA_INTEL_SMAP(ctlr, ch); 644 port = (port == 1) ? 1 : 0; 645 switch (reg) { 646 case ATA_SSTATUS: 647 reg = 0; 648 break; 649 case ATA_SERROR: 650 reg = 1; 651 break; 652 case ATA_SCONTROL: 653 reg = 2; 654 break; 655 default: 656 return (EINVAL); 657 } 658 ATA_INTEL_LOCK(ctlr); 659 pci_write_config(parent, 0xa0, 660 0x50 + smap[port] * 0x10 + reg * 4, 4); 661 *result = pci_read_config(parent, 0xa4, 4); 662 ATA_INTEL_UNLOCK(ctlr); 663 return (0); 664 } 665 666 static int 667 ata_intel_sata_sidpr_read(device_t dev, int port, int reg, u_int32_t *result) 668 { 669 struct ata_pci_controller *ctlr; 670 struct ata_channel *ch; 671 device_t parent; 672 673 parent = device_get_parent(dev); 674 ctlr = device_get_softc(parent); 675 ch = device_get_softc(dev); 676 port = (port == 1) ? 1 : 0; 677 switch (reg) { 678 case ATA_SSTATUS: 679 reg = 0; 680 break; 681 case ATA_SCONTROL: 682 reg = 1; 683 break; 684 case ATA_SERROR: 685 reg = 2; 686 break; 687 default: 688 return (EINVAL); 689 } 690 ATA_INTEL_LOCK(ctlr); 691 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 692 *result = ATA_IDX_INL(ch, ATA_IDX_DATA); 693 ATA_INTEL_UNLOCK(ctlr); 694 return (0); 695 } 696 697 static int 698 ata_intel_sata_ahci_write(device_t dev, int port, int reg, u_int32_t value) 699 { 700 struct ata_pci_controller *ctlr; 701 struct ata_channel *ch; 702 device_t parent; 703 u_char *smap; 704 int offset; 705 706 parent = device_get_parent(dev); 707 ctlr = device_get_softc(parent); 708 ch = device_get_softc(dev); 709 port = (port == 1) ? 1 : 0; 710 smap = ATA_INTEL_SMAP(ctlr, ch); 711 offset = 0x100 + smap[port] * 0x80; 712 switch (reg) { 713 case ATA_SSTATUS: 714 reg = 0x28; 715 break; 716 case ATA_SCONTROL: 717 reg = 0x2c; 718 break; 719 case ATA_SERROR: 720 reg = 0x30; 721 break; 722 default: 723 return (EINVAL); 724 } 725 ATA_OUTL(ctlr->r_res2, offset + reg, value); 726 return (0); 727 } 728 729 static int 730 ata_intel_sata_cscr_write(device_t dev, int port, int reg, u_int32_t value) 731 { 732 struct ata_pci_controller *ctlr; 733 struct ata_channel *ch; 734 device_t parent; 735 u_char *smap; 736 737 parent = device_get_parent(dev); 738 ctlr = device_get_softc(parent); 739 ch = device_get_softc(dev); 740 smap = ATA_INTEL_SMAP(ctlr, ch); 741 port = (port == 1) ? 1 : 0; 742 switch (reg) { 743 case ATA_SSTATUS: 744 reg = 0; 745 break; 746 case ATA_SERROR: 747 reg = 1; 748 break; 749 case ATA_SCONTROL: 750 reg = 2; 751 break; 752 default: 753 return (EINVAL); 754 } 755 ATA_INTEL_LOCK(ctlr); 756 pci_write_config(parent, 0xa0, 757 0x50 + smap[port] * 0x10 + reg * 4, 4); 758 pci_write_config(parent, 0xa4, value, 4); 759 ATA_INTEL_UNLOCK(ctlr); 760 return (0); 761 } 762 763 static int 764 ata_intel_sata_sidpr_write(device_t dev, int port, int reg, u_int32_t value) 765 { 766 struct ata_pci_controller *ctlr; 767 struct ata_channel *ch; 768 device_t parent; 769 770 parent = device_get_parent(dev); 771 ctlr = device_get_softc(parent); 772 ch = device_get_softc(dev); 773 port = (port == 1) ? 1 : 0; 774 switch (reg) { 775 case ATA_SSTATUS: 776 reg = 0; 777 break; 778 case ATA_SCONTROL: 779 reg = 1; 780 break; 781 case ATA_SERROR: 782 reg = 2; 783 break; 784 default: 785 return (EINVAL); 786 } 787 ATA_INTEL_LOCK(ctlr); 788 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 789 ATA_IDX_OUTL(ch, ATA_IDX_DATA, value); 790 ATA_INTEL_UNLOCK(ctlr); 791 return (0); 792 } 793 794 static int 795 ata_intel_sata_sidpr_test(device_t dev) 796 { 797 struct ata_channel *ch = device_get_softc(dev); 798 int port; 799 uint32_t val; 800 801 port = (ch->flags & ATA_NO_SLAVE) ? 0 : 1; 802 for (; port >= 0; port--) { 803 ata_intel_sata_sidpr_read(dev, port, ATA_SCONTROL, &val); 804 if ((val & ATA_SC_IPM_MASK) == 805 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)) 806 return (1); 807 val |= ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER; 808 ata_intel_sata_sidpr_write(dev, port, ATA_SCONTROL, val); 809 ata_intel_sata_sidpr_read(dev, port, ATA_SCONTROL, &val); 810 if ((val & ATA_SC_IPM_MASK) == 811 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)) 812 return (1); 813 } 814 if (bootverbose) 815 device_printf(dev, 816 "SControl registers are not functional: %08x\n", val); 817 return (0); 818 } 819 820 static int 821 ata_intel_31244_ch_attach(device_t dev) 822 { 823 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 824 struct ata_channel *ch = device_get_softc(dev); 825 int i; 826 int ch_offset; 827 828 ata_pci_dmainit(dev); 829 830 ch_offset = 0x200 + ch->unit * 0x200; 831 832 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 833 ch->r_io[i].res = ctlr->r_res2; 834 835 /* setup ATA registers */ 836 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 837 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 838 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 839 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 840 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 841 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 842 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 843 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 844 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 845 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 846 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 847 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 848 849 /* setup DMA registers */ 850 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 851 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 852 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 853 854 /* setup SATA registers */ 855 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 856 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 857 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 858 859 ch->flags |= ATA_NO_SLAVE; 860 ch->flags |= ATA_SATA; 861 ata_pci_hw(dev); 862 ch->hw.status = ata_intel_31244_status; 863 ch->hw.tf_write = ata_intel_31244_tf_write; 864 865 /* enable PHY state change interrupt */ 866 ATA_OUTL(ctlr->r_res2, 0x4, 867 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 868 return 0; 869 } 870 871 static int 872 ata_intel_31244_ch_detach(device_t dev) 873 { 874 875 ata_pci_dmafini(dev); 876 return (0); 877 } 878 879 static int 880 ata_intel_31244_status(device_t dev) 881 { 882 /* do we have any PHY events ? */ 883 ata_sata_phy_check_events(dev, -1); 884 885 /* any drive action to take care of ? */ 886 return ata_pci_status(dev); 887 } 888 889 static void 890 ata_intel_31244_tf_write(struct ata_request *request) 891 { 892 struct ata_channel *ch = device_get_softc(request->parent); 893 894 if (request->flags & ATA_R_48BIT) { 895 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 896 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 897 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 898 (request->u.ata.lba & 0x00ff)); 899 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 900 ((request->u.ata.lba >> 8) & 0x00ff)); 901 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 902 ((request->u.ata.lba >> 16) & 0x00ff)); 903 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 904 } 905 else { 906 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 907 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 908 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 909 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 910 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 911 ATA_IDX_OUTB(ch, ATA_DRIVE, 912 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 913 ((request->u.ata.lba >> 24) & 0x0f)); 914 } 915 } 916 917 static void 918 ata_intel_31244_reset(device_t dev) 919 { 920 struct ata_channel *ch = device_get_softc(dev); 921 922 if (ata_sata_phy_reset(dev, -1, 1)) 923 ata_generic_reset(dev); 924 else 925 ch->devices = 0; 926 } 927 928 ATA_DECLARE_DRIVER(ata_intel);
Cache object: 7d0b6bd98a2c2638d33e5e7037bfd7a8
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