Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/ata/chipsets/ata-nvidia.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/module.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/ata.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 #include <sys/malloc.h> 40 #include <sys/lock.h> 41 #include <sys/mutex.h> 42 #include <sys/sema.h> 43 #include <sys/taskqueue.h> 44 #include <vm/uma.h> 45 #include <machine/stdarg.h> 46 #include <machine/resource.h> 47 #include <machine/bus.h> 48 #include <sys/rman.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include <dev/ata/ata-all.h> 52 #include <dev/ata/ata-pci.h> 53 #include <ata_if.h> 54 55 /* local prototypes */ 56 static int ata_nvidia_chipinit(device_t dev); 57 static int ata_nvidia_ch_attach(device_t dev); 58 static int ata_nvidia_ch_attach_dumb(device_t dev); 59 static int ata_nvidia_status(device_t dev); 60 static void ata_nvidia_reset(device_t dev); 61 static int ata_nvidia_setmode(device_t dev, int target, int mode); 62 63 /* misc defines */ 64 #define NV4 0x01 65 #define NVQ 0x02 66 #define NVAHCI 0x04 67 68 /* 69 * nVidia chipset support functions 70 */ 71 static int 72 ata_nvidia_probe(device_t dev) 73 { 74 struct ata_pci_controller *ctlr = device_get_softc(dev); 75 static const struct ata_chip_id ids[] = 76 {{ ATA_NFORCE1, 0, 0, 0, ATA_UDMA5, "nForce" }, 77 { ATA_NFORCE2, 0, 0, 0, ATA_UDMA6, "nForce2" }, 78 { ATA_NFORCE2_PRO, 0, 0, 0, ATA_UDMA6, "nForce2 Pro" }, 79 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" }, 80 { ATA_NFORCE3, 0, 0, 0, ATA_UDMA6, "nForce3" }, 81 { ATA_NFORCE3_PRO, 0, 0, 0, ATA_UDMA6, "nForce3 Pro" }, 82 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 83 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 84 { ATA_NFORCE_MCP04, 0, 0, 0, ATA_UDMA6, "nForce MCP" }, 85 { ATA_NFORCE_MCP04_S1, 0, NV4, 0, ATA_SA150, "nForce MCP" }, 86 { ATA_NFORCE_MCP04_S2, 0, NV4, 0, ATA_SA150, "nForce MCP" }, 87 { ATA_NFORCE_CK804, 0, 0, 0, ATA_UDMA6, "nForce CK804" }, 88 { ATA_NFORCE_CK804_S1, 0, NV4, 0, ATA_SA300, "nForce CK804" }, 89 { ATA_NFORCE_CK804_S2, 0, NV4, 0, ATA_SA300, "nForce CK804" }, 90 { ATA_NFORCE_MCP51, 0, 0, 0, ATA_UDMA6, "nForce MCP51" }, 91 { ATA_NFORCE_MCP51_S1, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP51" }, 92 { ATA_NFORCE_MCP51_S2, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP51" }, 93 { ATA_NFORCE_MCP55, 0, 0, 0, ATA_UDMA6, "nForce MCP55" }, 94 { ATA_NFORCE_MCP55_S1, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP55" }, 95 { ATA_NFORCE_MCP55_S2, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP55" }, 96 { ATA_NFORCE_MCP61, 0, 0, 0, ATA_UDMA6, "nForce MCP61" }, 97 { ATA_NFORCE_MCP61_S1, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP61" }, 98 { ATA_NFORCE_MCP61_S2, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP61" }, 99 { ATA_NFORCE_MCP61_S3, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP61" }, 100 { ATA_NFORCE_MCP65, 0, 0, 0, ATA_UDMA6, "nForce MCP65" }, 101 { ATA_NFORCE_MCP65_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 102 { ATA_NFORCE_MCP65_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 103 { ATA_NFORCE_MCP65_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 104 { ATA_NFORCE_MCP65_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 105 { ATA_NFORCE_MCP65_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 106 { ATA_NFORCE_MCP65_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 107 { ATA_NFORCE_MCP65_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 108 { ATA_NFORCE_MCP65_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 109 { ATA_NFORCE_MCP67, 0, 0, 0, ATA_UDMA6, "nForce MCP67" }, 110 { ATA_NFORCE_MCP67_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 111 { ATA_NFORCE_MCP67_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 112 { ATA_NFORCE_MCP67_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 113 { ATA_NFORCE_MCP67_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 114 { ATA_NFORCE_MCP67_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 115 { ATA_NFORCE_MCP67_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 116 { ATA_NFORCE_MCP67_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 117 { ATA_NFORCE_MCP67_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 118 { ATA_NFORCE_MCP67_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 119 { ATA_NFORCE_MCP67_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 120 { ATA_NFORCE_MCP67_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 121 { ATA_NFORCE_MCP67_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 122 { ATA_NFORCE_MCP67_AC, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 123 { ATA_NFORCE_MCP73, 0, 0, 0, ATA_UDMA6, "nForce MCP73" }, 124 { ATA_NFORCE_MCP73_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 125 { ATA_NFORCE_MCP73_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 126 { ATA_NFORCE_MCP73_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 127 { ATA_NFORCE_MCP73_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 128 { ATA_NFORCE_MCP73_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 129 { ATA_NFORCE_MCP73_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 130 { ATA_NFORCE_MCP73_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 131 { ATA_NFORCE_MCP73_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 132 { ATA_NFORCE_MCP73_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 133 { ATA_NFORCE_MCP73_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 134 { ATA_NFORCE_MCP73_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 135 { ATA_NFORCE_MCP73_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 136 { ATA_NFORCE_MCP77, 0, 0, 0, ATA_UDMA6, "nForce MCP77" }, 137 { ATA_NFORCE_MCP77_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 138 { ATA_NFORCE_MCP77_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 139 { ATA_NFORCE_MCP77_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 140 { ATA_NFORCE_MCP77_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 141 { ATA_NFORCE_MCP77_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 142 { ATA_NFORCE_MCP77_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 143 { ATA_NFORCE_MCP77_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 144 { ATA_NFORCE_MCP77_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 145 { ATA_NFORCE_MCP77_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 146 { ATA_NFORCE_MCP77_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 147 { ATA_NFORCE_MCP77_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 148 { ATA_NFORCE_MCP77_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 149 { ATA_NFORCE_MCP79_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 150 { ATA_NFORCE_MCP79_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 151 { ATA_NFORCE_MCP79_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 152 { ATA_NFORCE_MCP79_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 153 { ATA_NFORCE_MCP79_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 154 { ATA_NFORCE_MCP79_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 155 { ATA_NFORCE_MCP79_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 156 { ATA_NFORCE_MCP79_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 157 { ATA_NFORCE_MCP79_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 158 { ATA_NFORCE_MCP79_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 159 { ATA_NFORCE_MCP79_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 160 { ATA_NFORCE_MCP79_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 161 { ATA_NFORCE_MCP89_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 162 { ATA_NFORCE_MCP89_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 163 { ATA_NFORCE_MCP89_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 164 { ATA_NFORCE_MCP89_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 165 { ATA_NFORCE_MCP89_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 166 { ATA_NFORCE_MCP89_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 167 { ATA_NFORCE_MCP89_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 168 { ATA_NFORCE_MCP89_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 169 { ATA_NFORCE_MCP89_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 170 { ATA_NFORCE_MCP89_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 171 { ATA_NFORCE_MCP89_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 172 { ATA_NFORCE_MCP89_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 173 { 0, 0, 0, 0, 0, 0}} ; 174 175 if (pci_get_vendor(dev) != ATA_NVIDIA_ID) 176 return ENXIO; 177 178 if (!(ctlr->chip = ata_match_chip(dev, ids))) 179 return ENXIO; 180 181 if ((ctlr->chip->cfg1 & NVAHCI) && 182 pci_get_subclass(dev) != PCIS_STORAGE_IDE) 183 return (ENXIO); 184 185 ata_set_desc(dev); 186 ctlr->chipinit = ata_nvidia_chipinit; 187 return (BUS_PROBE_LOW_PRIORITY); 188 } 189 190 static int 191 ata_nvidia_chipinit(device_t dev) 192 { 193 struct ata_pci_controller *ctlr = device_get_softc(dev); 194 195 if (ata_setup_interrupt(dev, ata_generic_intr)) 196 return ENXIO; 197 198 if (ctlr->chip->cfg1 & NVAHCI) { 199 ctlr->ch_attach = ata_nvidia_ch_attach_dumb; 200 ctlr->setmode = ata_sata_setmode; 201 } else if (ctlr->chip->max_dma >= ATA_SA150) { 202 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1) 203 ctlr->r_type2 = SYS_RES_IOPORT; 204 else 205 ctlr->r_type2 = SYS_RES_MEMORY; 206 ctlr->r_rid2 = PCIR_BAR(5); 207 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 208 &ctlr->r_rid2, RF_ACTIVE))) { 209 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; 210 211 ctlr->ch_attach = ata_nvidia_ch_attach; 212 ctlr->ch_detach = ata_pci_ch_detach; 213 ctlr->reset = ata_nvidia_reset; 214 215 /* enable control access */ 216 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1); 217 /* MCP55 seems to need some time to allow r_res2 read. */ 218 DELAY(10); 219 if (ctlr->chip->cfg1 & NVQ) { 220 /* clear interrupt status */ 221 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff); 222 223 /* enable device and PHY state change interrupts */ 224 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d); 225 226 /* disable NCQ support */ 227 ATA_OUTL(ctlr->r_res2, 0x0400, 228 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9); 229 } 230 else { 231 /* clear interrupt status */ 232 ATA_OUTB(ctlr->r_res2, offset, 0xff); 233 234 /* enable device and PHY state change interrupts */ 235 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd); 236 } 237 } 238 ctlr->setmode = ata_sata_setmode; 239 ctlr->getrev = ata_sata_getrev; 240 } 241 else { 242 /* disable prefetch, postwrite */ 243 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1); 244 ctlr->setmode = ata_nvidia_setmode; 245 } 246 return 0; 247 } 248 249 static int 250 ata_nvidia_ch_attach(device_t dev) 251 { 252 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 253 struct ata_channel *ch = device_get_softc(dev); 254 255 /* setup the usual register normal pci style */ 256 if (ata_pci_ch_attach(dev)) 257 return ENXIO; 258 259 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 260 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6); 261 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 262 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6); 263 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 264 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6); 265 266 ch->hw.status = ata_nvidia_status; 267 ch->flags |= ATA_NO_SLAVE; 268 ch->flags |= ATA_SATA; 269 return 0; 270 } 271 272 static int 273 ata_nvidia_ch_attach_dumb(device_t dev) 274 { 275 struct ata_channel *ch = device_get_softc(dev); 276 277 if (ata_pci_ch_attach(dev)) 278 return ENXIO; 279 ch->flags |= ATA_SATA; 280 return 0; 281 } 282 283 static int 284 ata_nvidia_status(device_t dev) 285 { 286 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 287 struct ata_channel *ch = device_get_softc(dev); 288 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; 289 int shift = ch->unit << (ctlr->chip->cfg1 & NVQ ? 4 : 2); 290 u_int32_t istatus; 291 292 /* get interrupt status */ 293 if (ctlr->chip->cfg1 & NVQ) 294 istatus = ATA_INL(ctlr->r_res2, offset); 295 else 296 istatus = ATA_INB(ctlr->r_res2, offset); 297 298 /* do we have any PHY events ? */ 299 if (istatus & (0x0c << shift)) 300 ata_sata_phy_check_events(dev, -1); 301 302 /* clear interrupt(s) */ 303 if (ctlr->chip->cfg1 & NVQ) 304 ATA_OUTL(ctlr->r_res2, offset, (0x0f << shift) | 0x00f000f0); 305 else 306 ATA_OUTB(ctlr->r_res2, offset, (0x0f << shift)); 307 308 /* do we have any device action ? */ 309 return (istatus & (0x01 << shift)); 310 } 311 312 static void 313 ata_nvidia_reset(device_t dev) 314 { 315 struct ata_channel *ch = device_get_softc(dev); 316 317 if (ata_sata_phy_reset(dev, -1, 1)) 318 ata_generic_reset(dev); 319 else 320 ch->devices = 0; 321 } 322 323 static int 324 ata_nvidia_setmode(device_t dev, int target, int mode) 325 { 326 device_t parent = device_get_parent(dev); 327 struct ata_pci_controller *ctlr = device_get_softc(parent); 328 struct ata_channel *ch = device_get_softc(dev); 329 int devno = (ch->unit << 1) + target; 330 int piomode; 331 static const uint8_t timings[] = 332 { 0xa8, 0x65, 0x42, 0x22, 0x20, 0xa8, 0x22, 0x20 }; 333 static const uint8_t modes[] = 334 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }; 335 int reg = 0x63 - devno; 336 337 mode = min(mode, ctlr->chip->max_dma); 338 339 if (mode >= ATA_UDMA0) { 340 pci_write_config(parent, reg, modes[mode & ATA_MODE_MASK], 1); 341 piomode = ATA_PIO4; 342 } else { 343 pci_write_config(parent, reg, 0x8b, 1); 344 piomode = mode; 345 } 346 pci_write_config(parent, reg - 0x08, timings[ata_mode2idx(piomode)], 1); 347 return (mode); 348 } 349 350 ATA_DECLARE_DRIVER(ata_nvidia);
Cache object: 357af12efc8719eaef6ceb20ea085a3e
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