1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31
32 #include <sys/param.h>
33 #include <sys/module.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/ata.h>
37 #include <sys/bus.h>
38 #include <sys/endian.h>
39 #include <sys/malloc.h>
40 #include <sys/lock.h>
41 #include <sys/mutex.h>
42 #include <sys/sema.h>
43 #include <sys/taskqueue.h>
44 #include <vm/uma.h>
45 #include <machine/stdarg.h>
46 #include <machine/resource.h>
47 #include <machine/bus.h>
48 #include <sys/rman.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/ata/ata-all.h>
52 #include <dev/ata/ata-pci.h>
53 #include <ata_if.h>
54
55 /* local prototypes */
56 static int ata_sis_chipinit(device_t dev);
57 static int ata_sis_ch_attach(device_t dev);
58 static void ata_sis_reset(device_t dev);
59 static int ata_sis_setmode(device_t dev, int target, int mode);
60
61 /* misc defines */
62 #define SIS_33 1
63 #define SIS_66 2
64 #define SIS_100NEW 3
65 #define SIS_100OLD 4
66 #define SIS_133NEW 5
67 #define SIS_133OLD 6
68 #define SIS_SATA 7
69
70 /*
71 * Silicon Integrated Systems Corp. (SiS) chipset support functions
72 */
73 static int
74 ata_sis_probe(device_t dev)
75 {
76 struct ata_pci_controller *ctlr = device_get_softc(dev);
77 const struct ata_chip_id *idx;
78 static const struct ata_chip_id ids[] =
79 {{ ATA_SIS182, 0x00, SIS_SATA, 0, ATA_SA150, "182" }, /* south */
80 { ATA_SIS181, 0x00, SIS_SATA, 0, ATA_SA150, "181" }, /* south */
81 { ATA_SIS180, 0x00, SIS_SATA, 0, ATA_SA150, "180" }, /* south */
82 { ATA_SIS965, 0x00, SIS_133NEW, 0, ATA_UDMA6, "965" }, /* south */
83 { ATA_SIS964, 0x00, SIS_133NEW, 0, ATA_UDMA6, "964" }, /* south */
84 { ATA_SIS963, 0x00, SIS_133NEW, 0, ATA_UDMA6, "963" }, /* south */
85 { ATA_SIS962, 0x00, SIS_133NEW, 0, ATA_UDMA6, "962" }, /* south */
86
87 { ATA_SIS745, 0x00, SIS_100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */
88 { ATA_SIS735, 0x00, SIS_100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */
89 { ATA_SIS733, 0x00, SIS_100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */
90 { ATA_SIS730, 0x00, SIS_100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */
91
92 { ATA_SIS635, 0x00, SIS_100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */
93 { ATA_SIS633, 0x00, SIS_100NEW, 0, ATA_UDMA5, "633" }, /* unknown */
94 { ATA_SIS630, 0x30, SIS_100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */
95 { ATA_SIS630, 0x00, SIS_66, 0, ATA_UDMA4, "630" }, /* 1chip */
96 { ATA_SIS620, 0x00, SIS_66, 0, ATA_UDMA4, "620" }, /* 1chip */
97
98 { ATA_SIS550, 0x00, SIS_66, 0, ATA_UDMA5, "550" },
99 { ATA_SIS540, 0x00, SIS_66, 0, ATA_UDMA4, "540" },
100 { ATA_SIS530, 0x00, SIS_66, 0, ATA_UDMA4, "530" },
101
102 { ATA_SIS5513, 0xc2, SIS_33, 1, ATA_UDMA2, "5513" },
103 { ATA_SIS5513, 0x00, SIS_33, 1, ATA_WDMA2, "5513" },
104 { 0, 0, 0, 0, 0, 0 }};
105 static struct ata_chip_id id[] =
106 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }};
107 char buffer[64];
108 int found = 0;
109
110 if (pci_get_class(dev) != PCIC_STORAGE)
111 return (ENXIO);
112
113 if (pci_get_vendor(dev) != ATA_SIS_ID)
114 return ENXIO;
115
116 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev))))
117 return ENXIO;
118
119 if (idx->cfg2) {
120 u_int8_t reg57 = pci_read_config(dev, 0x57, 1);
121
122 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1);
123 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) {
124 found = 1;
125 memcpy(&id[0], idx, sizeof(id[0]));
126 id[0].cfg1 = SIS_133NEW;
127 id[0].max_dma = ATA_UDMA6;
128 sprintf(buffer, "SiS 962/963 %s controller",
129 ata_mode2str(idx->max_dma));
130 }
131 pci_write_config(dev, 0x57, reg57, 1);
132 }
133 if (idx->cfg2 && !found) {
134 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1);
135
136 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1);
137 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) {
138 found = 1;
139 if (ata_find_chip(dev, id, pci_get_slot(dev))) {
140 id[0].cfg1 = SIS_133OLD;
141 id[0].max_dma = ATA_UDMA6;
142 } else {
143 id[0].cfg1 = SIS_100NEW;
144 id[0].max_dma = ATA_UDMA5;
145 }
146 sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
147 }
148 pci_write_config(dev, 0x4a, reg4a, 1);
149 }
150 if (!found)
151 sprintf(buffer,"SiS %s %s controller",
152 idx->text, ata_mode2str(idx->max_dma));
153 else
154 idx = &id[0];
155
156 device_set_desc_copy(dev, buffer);
157 ctlr->chip = idx;
158 ctlr->chipinit = ata_sis_chipinit;
159 return (BUS_PROBE_LOW_PRIORITY);
160 }
161
162 static int
163 ata_sis_chipinit(device_t dev)
164 {
165 struct ata_pci_controller *ctlr = device_get_softc(dev);
166
167 if (ata_setup_interrupt(dev, ata_generic_intr))
168 return ENXIO;
169
170 switch (ctlr->chip->cfg1) {
171 case SIS_33:
172 break;
173 case SIS_66:
174 case SIS_100OLD:
175 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1);
176 break;
177 case SIS_100NEW:
178 case SIS_133OLD:
179 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1);
180 break;
181 case SIS_133NEW:
182 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2);
183 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2);
184 break;
185 case SIS_SATA:
186 ctlr->r_type2 = SYS_RES_IOPORT;
187 ctlr->r_rid2 = PCIR_BAR(5);
188 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
189 &ctlr->r_rid2, RF_ACTIVE))) {
190 ctlr->ch_attach = ata_sis_ch_attach;
191 ctlr->ch_detach = ata_pci_ch_detach;
192 ctlr->reset = ata_sis_reset;
193 }
194 ctlr->setmode = ata_sata_setmode;
195 ctlr->getrev = ata_sata_getrev;
196 return 0;
197 default:
198 return ENXIO;
199 }
200 ctlr->setmode = ata_sis_setmode;
201 return 0;
202 }
203
204 static int
205 ata_sis_ch_attach(device_t dev)
206 {
207 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
208 struct ata_channel *ch = device_get_softc(dev);
209 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6);
210
211 /* setup the usual register normal pci style */
212 if (ata_pci_ch_attach(dev))
213 return ENXIO;
214
215 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
216 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset;
217 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
218 ch->r_io[ATA_SERROR].offset = 0x04 + offset;
219 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
220 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset;
221 ch->flags |= ATA_NO_SLAVE;
222 ch->flags |= ATA_SATA;
223
224 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */
225 /* XXX SOS unknown how to enable PHY state change interrupt */
226 return 0;
227 }
228
229 static void
230 ata_sis_reset(device_t dev)
231 {
232 struct ata_channel *ch = device_get_softc(dev);
233
234 if (ata_sata_phy_reset(dev, -1, 1))
235 ata_generic_reset(dev);
236 else
237 ch->devices = 0;
238 }
239
240 static int
241 ata_sis_setmode(device_t dev, int target, int mode)
242 {
243 device_t parent = device_get_parent(dev);
244 struct ata_pci_controller *ctlr = device_get_softc(parent);
245 struct ata_channel *ch = device_get_softc(dev);
246 int devno = (ch->unit << 1) + target;
247
248 mode = min(mode, ctlr->chip->max_dma);
249
250 if (ctlr->chip->cfg1 == SIS_133NEW) {
251 if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
252 pci_read_config(parent, ch->unit ? 0x52 : 0x50,2) & 0x8000) {
253 ata_print_cable(dev, "controller");
254 mode = ATA_UDMA2;
255 }
256 } else {
257 if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
258 pci_read_config(parent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) {
259 ata_print_cable(dev, "controller");
260 mode = ATA_UDMA2;
261 }
262 }
263
264 switch (ctlr->chip->cfg1) {
265 case SIS_133NEW: {
266 static const uint32_t timings[] =
267 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
268 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
269 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
270 u_int32_t reg;
271
272 reg = (pci_read_config(parent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
273 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 4);
274 break;
275 }
276 case SIS_133OLD: {
277 static const uint16_t timings[] =
278 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
279 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
280
281 u_int16_t reg = 0x40 + (devno << 1);
282
283 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
284 break;
285 }
286 case SIS_100NEW: {
287 static const uint16_t timings[] =
288 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
289 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
290 u_int16_t reg = 0x40 + (devno << 1);
291
292 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
293 break;
294 }
295 case SIS_100OLD:
296 case SIS_66:
297 case SIS_33: {
298 static const uint16_t timings[] =
299 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
300 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
301 u_int16_t reg = 0x40 + (devno << 1);
302
303 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
304 break;
305 }
306 }
307 return (mode);
308 }
309
310 ATA_DECLARE_DRIVER(ata_sis);
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