The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ath/ah_osdep.h

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    1 /*-
    2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer,
   10  *    without modification.
   11  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
   12  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
   13  *    redistribution must be conditioned upon including a substantially
   14  *    similar Disclaimer requirement for further binary redistribution.
   15  *
   16  * NO WARRANTY
   17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
   18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
   19  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
   20  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
   21  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
   22  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
   25  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   27  * THE POSSIBILITY OF SUCH DAMAGES.
   28  *
   29  * $FreeBSD$
   30  */
   31 #ifndef _ATH_AH_OSDEP_H_
   32 #define _ATH_AH_OSDEP_H_
   33 /*
   34  * Atheros Hardware Access Layer (HAL) OS Dependent Definitions.
   35  */
   36 #include <sys/cdefs.h>
   37 #include <sys/param.h>
   38 #include <sys/systm.h>
   39 #include <sys/endian.h>
   40 #include <sys/linker_set.h>
   41 
   42 #include <machine/bus.h>
   43 
   44 /*
   45  * Bus i/o type definitions.
   46  */
   47 typedef void *HAL_SOFTC;
   48 typedef bus_space_tag_t HAL_BUS_TAG;
   49 typedef bus_space_handle_t HAL_BUS_HANDLE;
   50 
   51 /*
   52  * Linker set writearounds for chip and RF backend registration.
   53  */
   54 #define OS_DATA_SET(set, item)  DATA_SET(set, item)
   55 #define OS_SET_DECLARE(set, ptype)      SET_DECLARE(set, ptype)
   56 #define OS_SET_FOREACH(pvar, set)       SET_FOREACH(pvar, set)
   57 
   58 /*
   59  * Delay n microseconds.
   60  */
   61 #define OS_DELAY(_n)    DELAY(_n)
   62 
   63 #define OS_INLINE       __inline
   64 #define OS_MEMZERO(_a, _n)      bzero((_a), (_n))
   65 #define OS_MEMCPY(_d, _s, _n)   memcpy(_d,_s,_n)
   66 
   67 #define abs(_a)         __builtin_abs(_a)
   68 
   69 struct ath_hal;
   70 
   71 /*
   72  * The hardware registers are native little-endian byte order.
   73  * Big-endian hosts are handled by enabling hardware byte-swap
   74  * of register reads and writes at reset.  But the PCI clock
   75  * domain registers are not byte swapped!  Thus, on big-endian
   76  * platforms we have to explicitly byte-swap those registers.
   77  * OS_REG_UNSWAPPED identifies the registers that need special handling.
   78  */
   79 #if _BYTE_ORDER == _BIG_ENDIAN
   80 #define OS_REG_UNSWAPPED(_reg) \
   81         (((_reg) >= 0x4000 && (_reg) < 0x5000) || \
   82          ((_reg) >= 0x7000 && (_reg) < 0x8000))
   83 #else /* _BYTE_ORDER == _LITTLE_ENDIAN */
   84 #define OS_REG_UNSWAPPED(_reg)  (0)
   85 #endif /* _BYTE_ORDER */
   86 
   87 /*
   88  * Register read/write operations are either handled through
   89  * platform-dependent routines (or when debugging is enabled
   90  * with AH_DEBUG); or they are inline expanded using the macros
   91  * defined below.
   92  */
   93 #if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ)
   94 #define OS_REG_WRITE(_ah, _reg, _val)   ath_hal_reg_write(_ah, _reg, _val)
   95 #define OS_REG_READ(_ah, _reg)          ath_hal_reg_read(_ah, _reg)
   96 
   97 extern  void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);
   98 extern  u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
   99 #else
  100 /*
  101  * The hardware registers are native little-endian byte order.
  102  * Big-endian hosts are handled by enabling hardware byte-swap
  103  * of register reads and writes at reset.  But the PCI clock
  104  * domain registers are not byte swapped!  Thus, on big-endian
  105  * platforms we have to explicitly byte-swap those registers.
  106  * Most of this code is collapsed at compile time because the
  107  * register values are constants.
  108  */
  109 #if _BYTE_ORDER == _BIG_ENDIAN
  110 #define OS_REG_WRITE(_ah, _reg, _val) do {                              \
  111         if (OS_REG_UNSWAPPED(_reg))                                     \
  112                 bus_space_write_4((bus_space_tag_t)(_ah)->ah_st,        \
  113                     (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val));  \
  114         else                                                            \
  115                 bus_space_write_stream_4((bus_space_tag_t)(_ah)->ah_st, \
  116                     (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val));  \
  117 } while (0)
  118 #define OS_REG_READ(_ah, _reg)                                          \
  119         (OS_REG_UNSWAPPED(_reg) ?                                       \
  120                 bus_space_read_4((bus_space_tag_t)(_ah)->ah_st,         \
  121                     (bus_space_handle_t)(_ah)->ah_sh, (_reg)) :         \
  122                 bus_space_read_stream_4((bus_space_tag_t)(_ah)->ah_st,  \
  123                     (bus_space_handle_t)(_ah)->ah_sh, (_reg)))
  124 #else /* _BYTE_ORDER == _LITTLE_ENDIAN */
  125 #define OS_REG_WRITE(_ah, _reg, _val)                                   \
  126         bus_space_write_4((bus_space_tag_t)(_ah)->ah_st,                \
  127             (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val))
  128 #define OS_REG_READ(_ah, _reg)                                          \
  129         bus_space_read_4((bus_space_tag_t)(_ah)->ah_st,                 \
  130             (bus_space_handle_t)(_ah)->ah_sh, (_reg))
  131 #endif /* _BYTE_ORDER */
  132 #endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */
  133 
  134 #ifdef AH_DEBUG_ALQ
  135 extern  void OS_MARK(struct ath_hal *, u_int id, u_int32_t value);
  136 #else
  137 #define OS_MARK(_ah, _id, _v)
  138 #endif
  139 
  140 #endif /* _ATH_AH_OSDEP_H_ */

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