Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/ath/ath_hal/ah_eeprom_v14.h
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1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD$ 20 */ 21 #ifndef _AH_EEPROM_V14_H_ 22 #define _AH_EEPROM_V14_H_ 23 24 #include "ah_eeprom.h" 25 26 /* reg_off = 4 * (eep_off) */ 27 #define AR5416_EEPROM_S 2 28 #define AR5416_EEPROM_OFFSET 0x2000 29 #define AR5416_EEPROM_START_ADDR 0x503f1200 30 #define AR5416_EEPROM_MAX 0xae0 /* Ignore for the moment used only on the flash implementations */ 31 #define AR5416_EEPROM_MAGIC 0xa55a 32 #define AR5416_EEPROM_MAGIC_OFFSET 0x0 33 34 #define owl_get_ntxchains(_txchainmask) \ 35 (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 36 37 #ifdef __LINUX_ARM_ARCH__ /* AP71 */ 38 #define owl_eep_start_loc 0 39 #else 40 #define owl_eep_start_loc 256 41 #endif 42 43 /* End temp defines */ 44 45 #define AR5416_EEP_NO_BACK_VER 0x1 46 #define AR5416_EEP_VER 0xE 47 #define AR5416_EEP_VER_MINOR_MASK 0xFFF 48 // Adds modal params txFrameToPaOn, txFrametoDataStart, ht40PowerInc 49 #define AR5416_EEP_MINOR_VER_2 0x2 50 // Adds modal params bswAtten, bswMargin, swSettle and base OpFlags for HT20/40 Disable 51 #define AR5416_EEP_MINOR_VER_3 0x3 52 #define AR5416_EEP_MINOR_VER_7 0x7 53 #define AR5416_EEP_MINOR_VER_9 0x9 54 #define AR5416_EEP_MINOR_VER_10 0xa 55 #define AR5416_EEP_MINOR_VER_16 0x10 56 #define AR5416_EEP_MINOR_VER_17 0x11 57 #define AR5416_EEP_MINOR_VER_19 0x13 58 #define AR5416_EEP_MINOR_VER_20 0x14 59 #define AR5416_EEP_MINOR_VER_21 0x15 60 #define AR5416_EEP_MINOR_VER_22 0x16 61 62 // 16-bit offset location start of calibration struct 63 #define AR5416_EEP_START_LOC 256 64 #define AR5416_NUM_5G_CAL_PIERS 8 65 #define AR5416_NUM_2G_CAL_PIERS 4 66 #define AR5416_NUM_5G_20_TARGET_POWERS 8 67 #define AR5416_NUM_5G_40_TARGET_POWERS 8 68 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3 69 #define AR5416_NUM_2G_20_TARGET_POWERS 4 70 #define AR5416_NUM_2G_40_TARGET_POWERS 4 71 #define AR5416_NUM_CTLS 24 72 #define AR5416_NUM_BAND_EDGES 8 73 #define AR5416_NUM_PD_GAINS 4 74 #define AR5416_PD_GAINS_IN_MASK 4 75 #define AR5416_PD_GAIN_ICEPTS 5 76 #define AR5416_EEPROM_MODAL_SPURS 5 77 #define AR5416_MAX_RATE_POWER 63 78 #define AR5416_NUM_PDADC_VALUES 128 79 #define AR5416_NUM_RATES 16 80 #define AR5416_BCHAN_UNUSED 0xFF 81 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 82 #define AR5416_EEPMISC_BIG_ENDIAN 0x01 83 #define FREQ2FBIN(x,y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) 84 #define AR5416_MAX_CHAINS 3 85 #define AR5416_PWR_TABLE_OFFSET_DB -5 86 #define AR5416_ANT_16S 25 87 88 #define AR5416_NUM_ANT_CHAIN_FIELDS 7 89 #define AR5416_NUM_ANT_COMMON_FIELDS 4 90 #define AR5416_SIZE_ANT_CHAIN_FIELD 3 91 #define AR5416_SIZE_ANT_COMMON_FIELD 4 92 #define AR5416_ANT_CHAIN_MASK 0x7 93 #define AR5416_ANT_COMMON_MASK 0xf 94 #define AR5416_CHAIN_0_IDX 0 95 #define AR5416_CHAIN_1_IDX 1 96 #define AR5416_CHAIN_2_IDX 2 97 98 #define AR5416_OPFLAGS_11A 0x01 99 #define AR5416_OPFLAGS_11G 0x02 100 #define AR5416_OPFLAGS_N_5G_HT40 0x04 /* If set, disable 5G HT40 */ 101 #define AR5416_OPFLAGS_N_2G_HT40 0x08 102 #define AR5416_OPFLAGS_N_5G_HT20 0x10 103 #define AR5416_OPFLAGS_N_2G_HT20 0x20 104 105 /* RF silent fields in EEPROM */ 106 #define EEP_RFSILENT_ENABLED 0x0001 /* enabled/disabled */ 107 #define EEP_RFSILENT_ENABLED_S 0 108 #define EEP_RFSILENT_POLARITY 0x0002 /* polarity */ 109 #define EEP_RFSILENT_POLARITY_S 1 110 #define EEP_RFSILENT_GPIO_SEL 0x001c /* gpio PIN */ 111 #define EEP_RFSILENT_GPIO_SEL_S 2 112 113 /* Rx gain type values */ 114 #define AR5416_EEP_RXGAIN_23dB_BACKOFF 0 115 #define AR5416_EEP_RXGAIN_13dB_BACKOFF 1 116 #define AR5416_EEP_RXGAIN_ORIG 2 117 118 /* Tx gain type values */ 119 #define AR5416_EEP_TXGAIN_ORIG 0 120 #define AR5416_EEP_TXGAIN_HIGH_POWER 1 121 122 typedef struct spurChanStruct { 123 uint16_t spurChan; 124 uint8_t spurRangeLow; 125 uint8_t spurRangeHigh; 126 } __packed SPUR_CHAN; 127 128 typedef struct CalTargetPowerLegacy { 129 uint8_t bChannel; 130 uint8_t tPow2x[4]; 131 } __packed CAL_TARGET_POWER_LEG; 132 133 typedef struct CalTargetPowerHt { 134 uint8_t bChannel; 135 uint8_t tPow2x[8]; 136 } __packed CAL_TARGET_POWER_HT; 137 138 typedef struct CalCtlEdges { 139 uint8_t bChannel; 140 uint8_t tPowerFlag; /* [0..5] tPower [6..7] flag */ 141 #define CAL_CTL_EDGES_POWER 0x3f 142 #define CAL_CTL_EDGES_POWER_S 0 143 #define CAL_CTL_EDGES_FLAG 0xc0 144 #define CAL_CTL_EDGES_FLAG_S 6 145 } __packed CAL_CTL_EDGES; 146 147 /* 148 * These are the secondary regulatory domain flags 149 * for regDmn[1]. 150 */ 151 #define AR5416_REGDMN_EN_FCC_MID 0x01 /* 5.47 - 5.7GHz operation */ 152 #define AR5416_REGDMN_EN_JAP_MID 0x02 /* 5.47 - 5.7GHz operation */ 153 #define AR5416_REGDMN_EN_FCC_DFS_HT40 0x04 /* FCC HT40 + DFS operation */ 154 #define AR5416_REGDMN_EN_JAP_HT40 0x08 /* JP HT40 operation */ 155 #define AR5416_REGDMN_EN_JAP_DFS_HT40 0x10 /* JP HT40 + DFS operation */ 156 157 /* 158 * NB: The format in EEPROM has words 0 and 2 swapped (i.e. version 159 * and length are swapped). We reverse their position after reading 160 * the data into host memory so the version field is at the same 161 * offset as in previous EEPROM layouts. This makes utilities that 162 * inspect the EEPROM contents work without looking at the PCI device 163 * id which may or may not be reliable. 164 */ 165 typedef struct BaseEepHeader { 166 uint16_t version; /* NB: length in EEPROM */ 167 uint16_t checksum; 168 uint16_t length; /* NB: version in EEPROM */ 169 uint8_t opCapFlags; 170 uint8_t eepMisc; 171 uint16_t regDmn[2]; 172 uint8_t macAddr[6]; 173 uint8_t rxMask; 174 uint8_t txMask; 175 uint16_t rfSilent; 176 uint16_t blueToothOptions; 177 uint16_t deviceCap; 178 uint32_t binBuildNumber; 179 uint8_t deviceType; 180 uint8_t pwdclkind; 181 uint8_t fastClk5g; 182 uint8_t divChain; 183 uint8_t rxGainType; 184 uint8_t dacHiPwrMode_5G;/* use the DAC high power mode (MB91) */ 185 uint8_t openLoopPwrCntl;/* 1: use open loop power control, 186 0: use closed loop power control */ 187 uint8_t dacLpMode; 188 uint8_t txGainType; /* high power tx gain table support */ 189 uint8_t rcChainMask; /* "1" if the card is an HB93 1x2 */ 190 uint8_t desiredScaleCCK; 191 uint8_t pwr_table_offset; 192 uint8_t frac_n_5g; /* 193 * bit 0: indicates that fracN synth 194 * mode applies to all 5G channels 195 */ 196 uint8_t futureBase[21]; 197 } __packed BASE_EEP_HEADER; // 64 B 198 199 typedef struct ModalEepHeader { 200 uint32_t antCtrlChain[AR5416_MAX_CHAINS]; // 12 201 uint32_t antCtrlCommon; // 4 202 int8_t antennaGainCh[AR5416_MAX_CHAINS]; // 3 203 uint8_t switchSettling; // 1 204 uint8_t txRxAttenCh[AR5416_MAX_CHAINS]; // 3 205 uint8_t rxTxMarginCh[AR5416_MAX_CHAINS]; // 3 206 uint8_t adcDesiredSize; // 1 207 int8_t pgaDesiredSize; // 1 208 uint8_t xlnaGainCh[AR5416_MAX_CHAINS]; // 3 209 uint8_t txEndToXpaOff; // 1 210 uint8_t txEndToRxOn; // 1 211 uint8_t txFrameToXpaOn; // 1 212 uint8_t thresh62; // 1 213 uint8_t noiseFloorThreshCh[AR5416_MAX_CHAINS]; // 3 214 uint8_t xpdGain; // 1 215 uint8_t xpd; // 1 216 int8_t iqCalICh[AR5416_MAX_CHAINS]; // 1 217 int8_t iqCalQCh[AR5416_MAX_CHAINS]; // 1 218 uint8_t pdGainOverlap; // 1 219 uint8_t ob; // 1 220 uint8_t db; // 1 221 uint8_t xpaBiasLvl; // 1 222 uint8_t pwrDecreaseFor2Chain; // 1 223 uint8_t pwrDecreaseFor3Chain; // 1 -> 48 B 224 uint8_t txFrameToDataStart; // 1 225 uint8_t txFrameToPaOn; // 1 226 uint8_t ht40PowerIncForPdadc; // 1 227 uint8_t bswAtten[AR5416_MAX_CHAINS]; // 3 228 uint8_t bswMargin[AR5416_MAX_CHAINS]; // 3 229 uint8_t swSettleHt40; // 1 230 uint8_t xatten2Db[AR5416_MAX_CHAINS]; // 3 -> New for AR9280 (0xa20c/b20c 11:6) 231 uint8_t xatten2Margin[AR5416_MAX_CHAINS]; // 3 -> New for AR9280 (0xa20c/b20c 21:17) 232 uint8_t ob_ch1; // 1 -> ob and db become chain specific from AR9280 233 uint8_t db_ch1; // 1 234 uint8_t flagBits; // 1 235 #define AR5416_EEP_FLAG_USEANT1 0x80 /* +1 configured antenna */ 236 #define AR5416_EEP_FLAG_FORCEXPAON 0x40 /* force XPA bit for 5G */ 237 #define AR5416_EEP_FLAG_LOCALBIAS 0x20 /* enable local bias */ 238 #define AR5416_EEP_FLAG_FEMBANDSELECT 0x10 /* FEM band select used */ 239 #define AR5416_EEP_FLAG_XLNABUFIN 0x08 240 #define AR5416_EEP_FLAG_XLNAISEL1 0x04 241 #define AR5416_EEP_FLAG_XLNAISEL2 0x02 242 #define AR5416_EEP_FLAG_XLNABUFMODE 0x01 243 uint8_t miscBits; // [0..1]: bb_tx_dac_scale_cck 244 uint16_t xpaBiasLvlFreq[3]; // 3 245 uint8_t futureModal[6]; // 6 246 247 SPUR_CHAN spurChans[AR5416_EEPROM_MODAL_SPURS]; // 20 B 248 } __packed MODAL_EEP_HEADER; // == 100 B 249 250 typedef struct calDataPerFreqOpLoop { 251 uint8_t pwrPdg[2][5]; /* power measurement */ 252 uint8_t vpdPdg[2][5]; /* pdadc voltage at power measurement */ 253 uint8_t pcdac[2][5]; /* pcdac used for power measurement */ 254 uint8_t empty[2][5]; /* future use */ 255 } __packed CAL_DATA_PER_FREQ_OP_LOOP; 256 257 typedef struct CalCtlData { 258 CAL_CTL_EDGES ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; 259 } __packed CAL_CTL_DATA; 260 261 typedef struct calDataPerFreq { 262 uint8_t pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 263 uint8_t vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 264 } __packed CAL_DATA_PER_FREQ; 265 266 struct ar5416eeprom { 267 BASE_EEP_HEADER baseEepHeader; // 64 B 268 uint8_t custData[64]; // 64 B 269 MODAL_EEP_HEADER modalHeader[2]; // 200 B 270 uint8_t calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; 271 uint8_t calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; 272 CAL_DATA_PER_FREQ calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS]; 273 CAL_DATA_PER_FREQ calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS]; 274 CAL_TARGET_POWER_LEG calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS]; 275 CAL_TARGET_POWER_HT calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; 276 CAL_TARGET_POWER_HT calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; 277 CAL_TARGET_POWER_LEG calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; 278 CAL_TARGET_POWER_LEG calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS]; 279 CAL_TARGET_POWER_HT calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; 280 CAL_TARGET_POWER_HT calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; 281 uint8_t ctlIndex[AR5416_NUM_CTLS]; 282 CAL_CTL_DATA ctlData[AR5416_NUM_CTLS]; 283 uint8_t padding; 284 } __packed; 285 286 typedef struct { 287 struct ar5416eeprom ee_base; 288 #define NUM_EDGES 8 289 uint16_t ee_numCtls; 290 RD_EDGES_POWER ee_rdEdgesPower[NUM_EDGES*AR5416_NUM_CTLS]; 291 /* XXX these are dynamically calculated for use by shared code */ 292 int8_t ee_antennaGainMax[2]; 293 } HAL_EEPROM_v14; 294 #endif /* _AH_EEPROM_V14_H_ */
Cache object: 3e94dad513f0c61921208e29b12b4e51
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