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sys/dev/ath/ath_hal/ah_regdomain/ah_rd_domains.h
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1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2005-2006 Atheros Communications, Inc. 6 * All rights reserved. 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 * 20 * $FreeBSD$ 21 */ 22 23 #ifndef __AH_REGDOMAIN_DOMAINS_H__ 24 #define __AH_REGDOMAIN_DOMAINS_H__ 25 26 /* 27 * BMLEN defines the size of the bitmask used to hold frequency 28 * band specifications. Note this must agree with the BM macro 29 * definition that's used to setup initializers. See also further 30 * comments below. 31 */ 32 /* BMLEN is now defined in ah_regdomain.h */ 33 #define W0(_a) \ 34 (((_a) >= 0 && (_a) < 64 ? (((uint64_t) 1)<<(_a)) : (uint64_t) 0)) 35 #define W1(_a) \ 36 (((_a) > 63 && (_a) < 128 ? (((uint64_t) 1)<<((_a)-64)) : (uint64_t) 0)) 37 #define BM1(_fa) { W0(_fa), W1(_fa) } 38 #define BM2(_fa, _fb) { W0(_fa) | W0(_fb), W1(_fa) | W1(_fb) } 39 #define BM3(_fa, _fb, _fc) \ 40 { W0(_fa) | W0(_fb) | W0(_fc), W1(_fa) | W1(_fb) | W1(_fc) } 41 #define BM4(_fa, _fb, _fc, _fd) \ 42 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd), \ 43 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) } 44 #define BM5(_fa, _fb, _fc, _fd, _fe) \ 45 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe), \ 46 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) } 47 #define BM6(_fa, _fb, _fc, _fd, _fe, _ff) \ 48 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff), \ 49 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) } 50 #define BM7(_fa, _fb, _fc, _fd, _fe, _ff, _fg) \ 51 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \ 52 W0(_fg),\ 53 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \ 54 W1(_fg) } 55 #define BM8(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh) \ 56 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \ 57 W0(_fg) | W0(_fh) , \ 58 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \ 59 W1(_fg) | W1(_fh) } 60 #define BM9(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh, _fi) \ 61 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \ 62 W0(_fg) | W0(_fh) | W0(_fi) , \ 63 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \ 64 W1(_fg) | W1(_fh) | W1(_fi) } 65 66 static REG_DOMAIN regDomains[] = { 67 {.regDmnEnum = DEBUG_REG_DMN, 68 .conformanceTestLimit = FCC, 69 .dfsMask = DFS_FCC3, 70 .chan11a = BM4(F1_4950_4980, 71 F1_5120_5240, 72 F1_5260_5700, 73 F1_5745_5825), 74 .chan11a_half = BM4(F1_4945_4985, 75 F2_5120_5240, 76 F2_5260_5700, 77 F7_5745_5825), 78 .chan11a_quarter = BM4(F1_4942_4987, 79 F3_5120_5240, 80 F3_5260_5700, 81 F8_5745_5825), 82 .chan11a_turbo = BM8(T1_5130_5210, 83 T1_5250_5330, 84 T1_5370_5490, 85 T1_5530_5650, 86 T1_5150_5190, 87 T1_5230_5310, 88 T1_5350_5470, 89 T1_5510_5670), 90 .chan11a_dyn_turbo = BM4(T1_5200_5240, 91 T1_5280_5280, 92 T1_5540_5660, 93 T1_5765_5805), 94 .chan11b = BM4(F1_2312_2372, 95 F1_2412_2472, 96 F1_2484_2484, 97 F1_2512_2732), 98 .chan11g = BM3(G1_2312_2372, G1_2412_2472, G1_2512_2732), 99 .chan11g_turbo = BM3(T1_2312_2372, T1_2437_2437, T1_2512_2732), 100 .chan11g_half = BM3(G2_2312_2372, G4_2412_2472, G2_2512_2732), 101 .chan11g_quarter = BM3(G3_2312_2372, G5_2412_2472, G3_2512_2732), 102 }, 103 104 {.regDmnEnum = APL1, 105 .conformanceTestLimit = FCC, 106 .chan11a = BM1(F4_5745_5825), 107 }, 108 109 {.regDmnEnum = APL2, 110 .conformanceTestLimit = FCC, 111 .chan11a = BM1(F1_5745_5805), 112 }, 113 114 {.regDmnEnum = APL3, 115 .conformanceTestLimit = FCC, 116 .chan11a = BM2(F1_5280_5320, F2_5745_5805), 117 }, 118 119 {.regDmnEnum = APL4, 120 .conformanceTestLimit = FCC, 121 .chan11a = BM2(F4_5180_5240, F3_5745_5825), 122 }, 123 124 {.regDmnEnum = APL5, 125 .conformanceTestLimit = FCC, 126 .chan11a = BM1(F2_5745_5825), 127 }, 128 129 {.regDmnEnum = APL6, 130 .conformanceTestLimit = ETSI, 131 .dfsMask = DFS_ETSI, 132 .pscan = PSCAN_FCC_T | PSCAN_FCC, 133 .chan11a = BM3(F4_5180_5240, F2_5260_5320, F3_5745_5825), 134 .chan11a_turbo = BM3(T2_5210_5210, T1_5250_5290, T1_5760_5800), 135 }, 136 137 {.regDmnEnum = APL8, 138 .conformanceTestLimit = ETSI, 139 .flags = DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB, 140 .chan11a = BM2(F6_5260_5320, F4_5745_5825), 141 }, 142 143 {.regDmnEnum = APL9, 144 .conformanceTestLimit = ETSI, 145 .dfsMask = DFS_ETSI, 146 .pscan = PSCAN_ETSI, 147 .flags = DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB, 148 .chan11a = BM3(F1_5180_5320, F1_5500_5620, F3_5745_5805), 149 }, 150 151 {.regDmnEnum = ETSI1, 152 .conformanceTestLimit = ETSI, 153 .dfsMask = DFS_ETSI, 154 .pscan = PSCAN_ETSI, 155 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 156 .chan11a = BM3(W2_5180_5240, F2_5260_5320, F2_5500_5700), 157 }, 158 159 {.regDmnEnum = ETSI2, 160 .conformanceTestLimit = ETSI, 161 .dfsMask = DFS_ETSI, 162 .pscan = PSCAN_ETSI, 163 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 164 .chan11a = BM1(F3_5180_5240), 165 }, 166 167 {.regDmnEnum = ETSI3, 168 .conformanceTestLimit = ETSI, 169 .dfsMask = DFS_ETSI, 170 .pscan = PSCAN_ETSI, 171 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 172 .chan11a = BM2(W2_5180_5240, F2_5260_5320), 173 }, 174 175 {.regDmnEnum = ETSI4, 176 .conformanceTestLimit = ETSI, 177 .dfsMask = DFS_ETSI, 178 .pscan = PSCAN_ETSI, 179 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 180 .chan11a = BM2(F3_5180_5240, F1_5260_5320), 181 }, 182 183 {.regDmnEnum = ETSI5, 184 .conformanceTestLimit = ETSI, 185 .dfsMask = DFS_ETSI, 186 .pscan = PSCAN_ETSI, 187 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 188 .chan11a = BM1(F1_5180_5240), 189 }, 190 191 {.regDmnEnum = ETSI6, 192 .conformanceTestLimit = ETSI, 193 .dfsMask = DFS_ETSI, 194 .pscan = PSCAN_ETSI, 195 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 196 .chan11a = BM3(F5_5180_5240, F1_5260_5280, F3_5500_5700), 197 }, 198 199 {.regDmnEnum = FCC1, 200 .conformanceTestLimit = FCC, 201 .chan11a = BM3(F2_5180_5240, F4_5260_5320, F5_5745_5825), 202 .chan11a_turbo = BM3(T1_5210_5210, T2_5250_5290, T2_5760_5800), 203 .chan11a_dyn_turbo = BM3(T1_5200_5240, T1_5280_5280, T1_5765_5805), 204 }, 205 206 {.regDmnEnum = FCC2, 207 .conformanceTestLimit = FCC, 208 .chan11a = BM3(F6_5180_5240, F5_5260_5320, F6_5745_5825), 209 .chan11a_dyn_turbo = BM3(T2_5200_5240, T1_5280_5280, T1_5765_5805), 210 }, 211 212 {.regDmnEnum = FCC3, 213 .conformanceTestLimit = FCC, 214 .dfsMask = DFS_FCC3, 215 .pscan = PSCAN_FCC | PSCAN_FCC_T, 216 .chan11a = BM4(F2_5180_5240, 217 F3_5260_5320, 218 F1_5500_5700, 219 F5_5745_5825), 220 .chan11a_turbo = BM4(T1_5210_5210, 221 T1_5250_5250, 222 T1_5290_5290, 223 T2_5760_5800), 224 .chan11a_dyn_turbo = BM3(T1_5200_5240, T2_5280_5280, T1_5540_5660), 225 }, 226 227 {.regDmnEnum = FCC4, 228 .conformanceTestLimit = FCC, 229 .dfsMask = DFS_FCC3, 230 .pscan = PSCAN_FCC | PSCAN_FCC_T, 231 .chan11a = BM1(F1_4950_4980), 232 .chan11a_half = BM1(F1_4945_4985), 233 .chan11a_quarter = BM1(F1_4942_4987), 234 }, 235 236 /* FCC1 w/ 1/2 and 1/4 width channels */ 237 {.regDmnEnum = FCC5, 238 .conformanceTestLimit = FCC, 239 .chan11a = BM3(F2_5180_5240, F4_5260_5320, F5_5745_5825), 240 .chan11a_turbo = BM3(T1_5210_5210, T2_5250_5290, T2_5760_5800), 241 .chan11a_dyn_turbo = BM3(T1_5200_5240, T1_5280_5280, T1_5765_5805), 242 .chan11a_half = BM3(F7_5180_5240, F7_5260_5320, F9_5745_5825), 243 .chan11a_quarter = BM3(F8_5180_5240, F8_5260_5320,F10_5745_5825), 244 }, 245 246 {.regDmnEnum = FCC6, 247 .conformanceTestLimit = FCC, 248 .chan11a = BM5(F8_5180_5240, F5_5260_5320, F1_5500_5580, F2_5660_5720, F6_5745_5825), 249 .chan11a_turbo = BM3(T7_5210_5210, T3_5250_5290, T2_5760_5800), 250 .chan11a_dyn_turbo = BM4(T7_5200_5200, T1_5240_5240, T2_5280_5280, T1_5765_5805), 251 #if 0 252 .chan11a_half = BM3(F7_5180_5240, F7_5260_5320, F9_5745_5825), 253 .chan11a_quarter = BM3(F8_5180_5240, F8_5260_5320,F10_5745_5825), 254 #endif 255 }, 256 257 {.regDmnEnum = MKK1, 258 .conformanceTestLimit = MKK, 259 .pscan = PSCAN_MKK1, 260 .flags = DISALLOW_ADHOC_11A_TURB, 261 .chan11a = BM1(F1_5170_5230), 262 }, 263 264 {.regDmnEnum = MKK2, 265 .conformanceTestLimit = MKK, 266 .pscan = PSCAN_MKK2, 267 .flags = DISALLOW_ADHOC_11A_TURB, 268 .chan11a = BM3(F1_4920_4980, F1_5040_5080, F1_5170_5230), 269 .chan11a_half = BM4(F1_4915_4925, 270 F1_4935_4945, 271 F1_5035_5040, 272 F1_5055_5055), 273 }, 274 275 /* UNI-1 even */ 276 {.regDmnEnum = MKK3, 277 .conformanceTestLimit = MKK, 278 .pscan = PSCAN_MKK3, 279 .flags = DISALLOW_ADHOC_11A_TURB, 280 .chan11a = BM1(F4_5180_5240), 281 }, 282 283 /* UNI-1 even + UNI-2 */ 284 {.regDmnEnum = MKK4, 285 .conformanceTestLimit = MKK, 286 .dfsMask = DFS_MKK4, 287 .pscan = PSCAN_MKK3, 288 .flags = DISALLOW_ADHOC_11A_TURB, 289 .chan11a = BM2(F4_5180_5240, F2_5260_5320), 290 }, 291 292 /* UNI-1 even + UNI-2 + mid-band */ 293 {.regDmnEnum = MKK5, 294 .conformanceTestLimit = MKK, 295 .dfsMask = DFS_MKK4, 296 .pscan = PSCAN_MKK3, 297 .flags = DISALLOW_ADHOC_11A_TURB, 298 .chan11a = BM3(F4_5180_5240, F2_5260_5320, F4_5500_5700), 299 }, 300 301 /* UNI-1 odd + even */ 302 {.regDmnEnum = MKK6, 303 .conformanceTestLimit = MKK, 304 .pscan = PSCAN_MKK1, 305 .flags = DISALLOW_ADHOC_11A_TURB, 306 .chan11a = BM2(F2_5170_5230, F4_5180_5240), 307 }, 308 309 /* UNI-1 odd + UNI-1 even + UNI-2 */ 310 {.regDmnEnum = MKK7, 311 .conformanceTestLimit = MKK, 312 .dfsMask = DFS_MKK4, 313 .pscan = PSCAN_MKK1 | PSCAN_MKK3, 314 .flags = DISALLOW_ADHOC_11A_TURB, 315 .chan11a = BM3(F1_5170_5230, F4_5180_5240, F2_5260_5320), 316 }, 317 318 /* UNI-1 odd + UNI-1 even + UNI-2 + mid-band */ 319 {.regDmnEnum = MKK8, 320 .conformanceTestLimit = MKK, 321 .dfsMask = DFS_MKK4, 322 .pscan = PSCAN_MKK1 | PSCAN_MKK3, 323 .flags = DISALLOW_ADHOC_11A_TURB, 324 .chan11a = BM4(F1_5170_5230, 325 F4_5180_5240, 326 F2_5260_5320, 327 F4_5500_5700), 328 }, 329 330 /* UNI-1 even + 4.9 GHZ */ 331 {.regDmnEnum = MKK9, 332 .conformanceTestLimit = MKK, 333 .pscan = PSCAN_MKK3, 334 .flags = DISALLOW_ADHOC_11A_TURB, 335 .chan11a = BM7(F1_4915_4925, 336 F1_4935_4945, 337 F1_4920_4980, 338 F1_5035_5040, 339 F1_5055_5055, 340 F1_5040_5080, 341 F4_5180_5240), 342 }, 343 344 /* UNI-1 even + UNI-2 + 4.9 GHZ */ 345 {.regDmnEnum = MKK10, 346 .conformanceTestLimit = MKK, 347 .dfsMask = DFS_MKK4, 348 .pscan = PSCAN_MKK3, 349 .flags = DISALLOW_ADHOC_11A_TURB, 350 .chan11a = BM8(F1_4915_4925, 351 F1_4935_4945, 352 F1_4920_4980, 353 F1_5035_5040, 354 F1_5055_5055, 355 F1_5040_5080, 356 F4_5180_5240, 357 F2_5260_5320), 358 }, 359 360 /* Defined here to use when 2G channels are authorised for country K2 */ 361 {.regDmnEnum = APLD, 362 .conformanceTestLimit = NO_CTL, 363 .chan11b = BM2(F2_2312_2372,F2_2412_2472), 364 .chan11g = BM2(G2_2312_2372,G2_2412_2472), 365 }, 366 367 {.regDmnEnum = ETSIA, 368 .conformanceTestLimit = NO_CTL, 369 .pscan = PSCAN_ETSIA, 370 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 371 .chan11b = BM1(F1_2457_2472), 372 .chan11g = BM1(G1_2457_2472), 373 .chan11g_turbo = BM1(T2_2437_2437) 374 }, 375 376 {.regDmnEnum = ETSIB, 377 .conformanceTestLimit = ETSI, 378 .pscan = PSCAN_ETSIB, 379 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 380 .chan11b = BM1(F1_2432_2442), 381 .chan11g = BM1(G1_2432_2442), 382 .chan11g_turbo = BM1(T2_2437_2437) 383 }, 384 385 {.regDmnEnum = ETSIC, 386 .conformanceTestLimit = ETSI, 387 .pscan = PSCAN_ETSIC, 388 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 389 .chan11b = BM1(F3_2412_2472), 390 .chan11g = BM1(G3_2412_2472), 391 .chan11g_turbo = BM1(T2_2437_2437) 392 }, 393 394 {.regDmnEnum = FCCA, 395 .conformanceTestLimit = FCC, 396 .chan11b = BM1(F1_2412_2462), 397 .chan11g = BM1(G1_2412_2462), 398 .chan11g_turbo = BM1(T2_2437_2437), 399 }, 400 401 /* FCCA w/ 1/2 and 1/4 width channels */ 402 {.regDmnEnum = FCCB, 403 .conformanceTestLimit = FCC, 404 .chan11b = BM1(F1_2412_2462), 405 .chan11g = BM1(G1_2412_2462), 406 .chan11g_turbo = BM1(T2_2437_2437), 407 .chan11g_half = BM1(G3_2412_2462), 408 .chan11g_quarter = BM1(G4_2412_2462), 409 }, 410 411 {.regDmnEnum = MKKA, 412 .conformanceTestLimit = MKK, 413 .pscan = PSCAN_MKKA | PSCAN_MKKA_G 414 | PSCAN_MKKA1 | PSCAN_MKKA1_G 415 | PSCAN_MKKA2 | PSCAN_MKKA2_G, 416 .flags = DISALLOW_ADHOC_11A_TURB, 417 .chan11b = BM3(F2_2412_2462, F1_2467_2472, F2_2484_2484), 418 .chan11g = BM2(G2_2412_2462, G1_2467_2472), 419 .chan11g_turbo = BM1(T2_2437_2437) 420 }, 421 422 {.regDmnEnum = MKKC, 423 .conformanceTestLimit = MKK, 424 .chan11b = BM1(F2_2412_2472), 425 .chan11g = BM1(G2_2412_2472), 426 .chan11g_turbo = BM1(T2_2437_2437) 427 }, 428 429 {.regDmnEnum = WORLD, 430 .conformanceTestLimit = ETSI, 431 .chan11b = BM1(F2_2412_2472), 432 .chan11g = BM1(G2_2412_2472), 433 .chan11g_turbo = BM1(T2_2437_2437) 434 }, 435 436 {.regDmnEnum = WOR0_WORLD, 437 .conformanceTestLimit = NO_CTL, 438 .dfsMask = DFS_FCC3 | DFS_ETSI, 439 .pscan = PSCAN_WWR, 440 .flags = ADHOC_PER_11D, 441 .chan11a = BM5(W1_5260_5320, 442 W1_5180_5240, 443 W1_5170_5230, 444 W1_5745_5825, 445 W1_5500_5700), 446 .chan11a_turbo = BM3(WT1_5210_5250, 447 WT1_5290_5290, 448 WT1_5760_5800), 449 .chan11b = BM8(W1_2412_2412, 450 W1_2437_2442, 451 W1_2462_2462, 452 W1_2472_2472, 453 W1_2417_2432, 454 W1_2447_2457, 455 W1_2467_2467, 456 W1_2484_2484), 457 .chan11g = BM7(WG1_2412_2412, 458 WG1_2437_2442, 459 WG1_2462_2462, 460 WG1_2472_2472, 461 WG1_2417_2432, 462 WG1_2447_2457, 463 WG1_2467_2467), 464 .chan11g_turbo = BM1(T3_2437_2437) 465 }, 466 467 {.regDmnEnum = WOR01_WORLD, 468 .conformanceTestLimit = NO_CTL, 469 .dfsMask = DFS_FCC3 | DFS_ETSI, 470 .pscan = PSCAN_WWR, 471 .flags = ADHOC_PER_11D, 472 .chan11a = BM5(W1_5260_5320, 473 W1_5180_5240, 474 W1_5170_5230, 475 W1_5745_5825, 476 W1_5500_5700), 477 .chan11a_turbo = BM3(WT1_5210_5250, 478 WT1_5290_5290, 479 WT1_5760_5800), 480 .chan11b = BM5(W1_2412_2412, 481 W1_2437_2442, 482 W1_2462_2462, 483 W1_2417_2432, 484 W1_2447_2457), 485 .chan11g = BM5(WG1_2412_2412, 486 WG1_2437_2442, 487 WG1_2462_2462, 488 WG1_2417_2432, 489 WG1_2447_2457), 490 .chan11g_turbo = BM1(T3_2437_2437)}, 491 492 {.regDmnEnum = WOR02_WORLD, 493 .conformanceTestLimit = NO_CTL, 494 .dfsMask = DFS_FCC3 | DFS_ETSI, 495 .pscan = PSCAN_WWR, 496 .flags = ADHOC_PER_11D, 497 .chan11a = BM5(W1_5260_5320, 498 W1_5180_5240, 499 W1_5170_5230, 500 W1_5745_5825, 501 W1_5500_5700), 502 .chan11a_turbo = BM3(WT1_5210_5250, 503 WT1_5290_5290, 504 WT1_5760_5800), 505 .chan11b = BM7(W1_2412_2412, 506 W1_2437_2442, 507 W1_2462_2462, 508 W1_2472_2472, 509 W1_2417_2432, 510 W1_2447_2457, 511 W1_2467_2467), 512 .chan11g = BM7(WG1_2412_2412, 513 WG1_2437_2442, 514 WG1_2462_2462, 515 WG1_2472_2472, 516 WG1_2417_2432, 517 WG1_2447_2457, 518 WG1_2467_2467), 519 .chan11g_turbo = BM1(T3_2437_2437)}, 520 521 {.regDmnEnum = EU1_WORLD, 522 .conformanceTestLimit = NO_CTL, 523 .dfsMask = DFS_FCC3 | DFS_ETSI, 524 .pscan = PSCAN_WWR, 525 .flags = ADHOC_PER_11D, 526 .chan11a = BM5(W1_5260_5320, 527 W1_5180_5240, 528 W1_5170_5230, 529 W1_5745_5825, 530 W1_5500_5700), 531 .chan11a_turbo = BM3(WT1_5210_5250, 532 WT1_5290_5290, 533 WT1_5760_5800), 534 .chan11b = BM7(W1_2412_2412, 535 W1_2437_2442, 536 W1_2462_2462, 537 W2_2472_2472, 538 W1_2417_2432, 539 W1_2447_2457, 540 W2_2467_2467), 541 .chan11g = BM7(WG1_2412_2412, 542 WG1_2437_2442, 543 WG1_2462_2462, 544 WG2_2472_2472, 545 WG1_2417_2432, 546 WG1_2447_2457, 547 WG2_2467_2467), 548 .chan11g_turbo = BM1(T3_2437_2437)}, 549 550 {.regDmnEnum = WOR1_WORLD, 551 .conformanceTestLimit = NO_CTL, 552 .dfsMask = DFS_FCC3 | DFS_ETSI, 553 .pscan = PSCAN_WWR, 554 .flags = DISALLOW_ADHOC_11A, 555 .chan11a = BM5(W1_5260_5320, 556 W1_5180_5240, 557 W1_5170_5230, 558 W1_5745_5825, 559 W1_5500_5700), 560 .chan11b = BM8(W1_2412_2412, 561 W1_2437_2442, 562 W1_2462_2462, 563 W1_2472_2472, 564 W1_2417_2432, 565 W1_2447_2457, 566 W1_2467_2467, 567 W1_2484_2484), 568 .chan11g = BM7(WG1_2412_2412, 569 WG1_2437_2442, 570 WG1_2462_2462, 571 WG1_2472_2472, 572 WG1_2417_2432, 573 WG1_2447_2457, 574 WG1_2467_2467), 575 .chan11g_turbo = BM1(T3_2437_2437) 576 }, 577 578 {.regDmnEnum = WOR2_WORLD, 579 .conformanceTestLimit = NO_CTL, 580 .dfsMask = DFS_FCC3 | DFS_ETSI, 581 .pscan = PSCAN_WWR, 582 .flags = DISALLOW_ADHOC_11A, 583 .chan11a = BM5(W1_5260_5320, 584 W1_5180_5240, 585 W1_5170_5230, 586 W1_5745_5825, 587 W1_5500_5700), 588 .chan11a_turbo = BM3(WT1_5210_5250, 589 WT1_5290_5290, 590 WT1_5760_5800), 591 .chan11b = BM8(W1_2412_2412, 592 W1_2437_2442, 593 W1_2462_2462, 594 W1_2472_2472, 595 W1_2417_2432, 596 W1_2447_2457, 597 W1_2467_2467, 598 W1_2484_2484), 599 .chan11g = BM7(WG1_2412_2412, 600 WG1_2437_2442, 601 WG1_2462_2462, 602 WG1_2472_2472, 603 WG1_2417_2432, 604 WG1_2447_2457, 605 WG1_2467_2467), 606 .chan11g_turbo = BM1(T3_2437_2437)}, 607 608 {.regDmnEnum = WOR3_WORLD, 609 .conformanceTestLimit = NO_CTL, 610 .dfsMask = DFS_FCC3 | DFS_ETSI, 611 .pscan = PSCAN_WWR, 612 .flags = ADHOC_PER_11D, 613 .chan11a = BM4(W1_5260_5320, 614 W1_5180_5240, 615 W1_5170_5230, 616 W1_5745_5825), 617 .chan11a_turbo = BM3(WT1_5210_5250, 618 WT1_5290_5290, 619 WT1_5760_5800), 620 .chan11b = BM7(W1_2412_2412, 621 W1_2437_2442, 622 W1_2462_2462, 623 W1_2472_2472, 624 W1_2417_2432, 625 W1_2447_2457, 626 W1_2467_2467), 627 .chan11g = BM7(WG1_2412_2412, 628 WG1_2437_2442, 629 WG1_2462_2462, 630 WG1_2472_2472, 631 WG1_2417_2432, 632 WG1_2447_2457, 633 WG1_2467_2467), 634 .chan11g_turbo = BM1(T3_2437_2437)}, 635 636 {.regDmnEnum = WOR4_WORLD, 637 .conformanceTestLimit = NO_CTL, 638 .dfsMask = DFS_FCC3 | DFS_ETSI, 639 .pscan = PSCAN_WWR, 640 .flags = DISALLOW_ADHOC_11A, 641 .chan11a = BM4(W2_5260_5320, 642 W2_5180_5240, 643 F2_5745_5805, 644 W2_5825_5825), 645 .chan11a_turbo = BM3(WT1_5210_5250, 646 WT1_5290_5290, 647 WT1_5760_5800), 648 .chan11b = BM5(W1_2412_2412, 649 W1_2437_2442, 650 W1_2462_2462, 651 W1_2417_2432, 652 W1_2447_2457), 653 .chan11g = BM5(WG1_2412_2412, 654 WG1_2437_2442, 655 WG1_2462_2462, 656 WG1_2417_2432, 657 WG1_2447_2457), 658 .chan11g_turbo = BM1(T3_2437_2437)}, 659 660 {.regDmnEnum = WOR5_ETSIC, 661 .conformanceTestLimit = NO_CTL, 662 .dfsMask = DFS_FCC3 | DFS_ETSI, 663 .pscan = PSCAN_WWR, 664 .flags = DISALLOW_ADHOC_11A, 665 .chan11a = BM3(W1_5260_5320, W2_5180_5240, F6_5745_5825), 666 .chan11b = BM7(W1_2412_2412, 667 W1_2437_2442, 668 W1_2462_2462, 669 W2_2472_2472, 670 W1_2417_2432, 671 W1_2447_2457, 672 W2_2467_2467), 673 .chan11g = BM7(WG1_2412_2412, 674 WG1_2437_2442, 675 WG1_2462_2462, 676 WG2_2472_2472, 677 WG1_2417_2432, 678 WG1_2447_2457, 679 WG2_2467_2467), 680 .chan11g_turbo = BM1(T3_2437_2437)}, 681 682 {.regDmnEnum = WOR9_WORLD, 683 .conformanceTestLimit = NO_CTL, 684 .dfsMask = DFS_FCC3 | DFS_ETSI, 685 .pscan = PSCAN_WWR, 686 .flags = DISALLOW_ADHOC_11A, 687 .chan11a = BM4(W1_5260_5320, 688 W1_5180_5240, 689 W1_5745_5825, 690 W1_5500_5700), 691 .chan11a_turbo = BM3(WT1_5210_5250, 692 WT1_5290_5290, 693 WT1_5760_5800), 694 .chan11b = BM5(W1_2412_2412, 695 W1_2437_2442, 696 W1_2462_2462, 697 W1_2417_2432, 698 W1_2447_2457), 699 .chan11g = BM5(WG1_2412_2412, 700 WG1_2437_2442, 701 WG1_2462_2462, 702 WG1_2417_2432, 703 WG1_2447_2457), 704 .chan11g_turbo = BM1(T3_2437_2437)}, 705 706 {.regDmnEnum = WORA_WORLD, 707 .conformanceTestLimit = NO_CTL, 708 .dfsMask = DFS_FCC3 | DFS_ETSI, 709 .pscan = PSCAN_WWR, 710 .flags = DISALLOW_ADHOC_11A, 711 .chan11a = BM4(W1_5260_5320, 712 W1_5180_5240, 713 W1_5745_5825, 714 W1_5500_5700), 715 .chan11b = BM7(W1_2412_2412, 716 W1_2437_2442, 717 W1_2462_2462, 718 W1_2472_2472, 719 W1_2417_2432, 720 W1_2447_2457, 721 W1_2467_2467), 722 .chan11g = BM7(WG1_2412_2412, 723 WG1_2437_2442, 724 WG1_2462_2462, 725 WG1_2472_2472, 726 WG1_2417_2432, 727 WG1_2447_2457, 728 WG1_2467_2467), 729 .chan11g_turbo = BM1(T3_2437_2437)}, 730 731 {.regDmnEnum = WORB_WORLD, 732 .conformanceTestLimit = NO_CTL, 733 .dfsMask = DFS_FCC3 | DFS_ETSI, 734 .pscan = PSCAN_WWR, 735 .flags = DISALLOW_ADHOC_11A, 736 .chan11a = BM4(W1_5260_5320, 737 W1_5180_5240, 738 W1_5745_5825, 739 W1_5500_5700), 740 .chan11b = BM7(W1_2412_2412, 741 W1_2437_2442, 742 W1_2462_2462, 743 W1_2472_2472, 744 W1_2417_2432, 745 W1_2447_2457, 746 W1_2467_2467), 747 .chan11g = BM7(WG1_2412_2412, 748 WG1_2437_2442, 749 WG1_2462_2462, 750 WG1_2472_2472, 751 WG1_2417_2432, 752 WG1_2447_2457, 753 WG1_2467_2467), 754 .chan11g_turbo = BM1(T3_2437_2437)}, 755 756 {.regDmnEnum = WORC_WORLD, 757 .conformanceTestLimit = NO_CTL, 758 .dfsMask = DFS_FCC3 | DFS_ETSI, 759 .pscan = PSCAN_WWR, 760 .flags = ADHOC_PER_11D, 761 .chan11a = BM4(W1_5260_5320, 762 W1_5180_5240, 763 W1_5745_5825, 764 W1_5500_5700), 765 .chan11b = BM7(W1_2412_2412, 766 W1_2437_2442, 767 W1_2462_2462, 768 W1_2472_2472, 769 W1_2417_2432, 770 W1_2447_2457, 771 W1_2467_2467), 772 .chan11g = BM7(WG1_2412_2412, 773 WG1_2437_2442, 774 WG1_2462_2462, 775 WG1_2472_2472, 776 WG1_2417_2432, 777 WG1_2447_2457, 778 WG1_2467_2467), 779 .chan11g_turbo = BM1(T3_2437_2437)}, 780 781 {.regDmnEnum = NULL1, 782 .conformanceTestLimit = NO_CTL, 783 } 784 }; 785 786 #endif
Cache object: 35a554c7a30cae72db7a5102b3aff7cb
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