The Design and Implementation of the FreeBSD Operating System, Second Edition
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sys/dev/ath/ath_hal/ah_regdomain/ah_rd_freqbands.h

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    1 /*-
    2  * SPDX-License-Identifier: ISC
    3  *
    4  * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
    5  * Copyright (c) 2005-2006 Atheros Communications, Inc.
    6  * All rights reserved.
    7  *
    8  * Permission to use, copy, modify, and/or distribute this software for any
    9  * purpose with or without fee is hereby granted, provided that the above
   10  * copyright notice and this permission notice appear in all copies.
   11  *
   12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   19  *
   20  * $FreeBSD$
   21  */
   22 
   23 #ifndef __AH_REGDOMAIN_FREQBANDS_H__
   24 #define __AH_REGDOMAIN_FREQBANDS_H__
   25 
   26 #define AFTER(x)        ((x)+1)
   27 
   28 /*
   29  * Frequency band collections are defined using bitmasks.  Each bit
   30  * in a mask is the index of an entry in one of the following tables.
   31  * Bitmasks are BMLEN*64 bits so if a table grows beyond that the bit
   32  * vectors must be enlarged or the tables split somehow (e.g. split
   33  * 1/2 and 1/4 rate channels into a separate table).
   34  *
   35  * Beware of ordering; the indices are defined relative to the preceding
   36  * entry so if things get off there will be confusion.  A good way to
   37  * check the indices is to collect them in a switch statement in a stub
   38  * function so the compiler checks for duplicates.
   39  */
   40 
   41 /*
   42  * 5GHz 11A channel tags
   43  */
   44 static REG_DMN_FREQ_BAND regDmn5GhzFreq[] = {
   45         { 4915, 4925, 23, 0, 10,  5, NO_DFS, PSCAN_MKK2 },
   46 #define F1_4915_4925    0
   47         { 4935, 4945, 23, 0, 10,  5, NO_DFS, PSCAN_MKK2 },
   48 #define F1_4935_4945    AFTER(F1_4915_4925)
   49         { 4920, 4980, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2 },
   50 #define F1_4920_4980    AFTER(F1_4935_4945)
   51         { 4942, 4987, 27, 6,  5,  5, NO_DFS, PSCAN_FCC },
   52 #define F1_4942_4987    AFTER(F1_4920_4980)
   53         { 4945, 4985, 30, 6, 10,  5, NO_DFS, PSCAN_FCC },
   54 #define F1_4945_4985    AFTER(F1_4942_4987)
   55         { 4950, 4980, 33, 6, 20,  5, NO_DFS, PSCAN_FCC },
   56 #define F1_4950_4980    AFTER(F1_4945_4985)
   57         { 5035, 5040, 23, 0, 10,  5, NO_DFS, PSCAN_MKK2 },
   58 #define F1_5035_5040    AFTER(F1_4950_4980)
   59         { 5040, 5080, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2 },
   60 #define F1_5040_5080    AFTER(F1_5035_5040)
   61         { 5055, 5055, 23, 0, 10,  5, NO_DFS, PSCAN_MKK2 },
   62 #define F1_5055_5055    AFTER(F1_5040_5080)
   63 
   64         { 5120, 5240, 5,  6, 20, 20, NO_DFS, NO_PSCAN },
   65 #define F1_5120_5240    AFTER(F1_5055_5055)
   66         { 5120, 5240, 5,  6, 10, 10, NO_DFS, NO_PSCAN },
   67 #define F2_5120_5240    AFTER(F1_5120_5240)
   68         { 5120, 5240, 5,  6,  5,  5, NO_DFS, NO_PSCAN },
   69 #define F3_5120_5240    AFTER(F2_5120_5240)
   70 
   71         { 5170, 5230, 23, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2 },
   72 #define F1_5170_5230    AFTER(F3_5120_5240)
   73         { 5170, 5230, 20, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2 },
   74 #define F2_5170_5230    AFTER(F1_5170_5230)
   75 
   76         { 5180, 5240, 15, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI },
   77 #define F1_5180_5240    AFTER(F2_5170_5230)
   78         { 5180, 5240, 17, 6, 20, 20, NO_DFS, PSCAN_FCC },
   79 #define F2_5180_5240    AFTER(F1_5180_5240)
   80         { 5180, 5240, 18, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI },
   81 #define F3_5180_5240    AFTER(F2_5180_5240)
   82         { 5180, 5240, 20, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI },
   83 #define F4_5180_5240    AFTER(F3_5180_5240)
   84         { 5180, 5240, 23, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI },
   85 #define F5_5180_5240    AFTER(F4_5180_5240)
   86         { 5180, 5240, 23, 6, 20, 20, NO_DFS, PSCAN_FCC },
   87 #define F6_5180_5240    AFTER(F5_5180_5240)
   88         { 5180, 5240, 17, 6, 20, 10, NO_DFS, PSCAN_FCC },
   89 #define F7_5180_5240    AFTER(F6_5180_5240)
   90         { 5180, 5240, 17, 6, 20,  5, NO_DFS, PSCAN_FCC },
   91 #define F8_5180_5240    AFTER(F7_5180_5240)
   92         { 5180, 5320, 20, 6, 20, 20, DFS_ETSI, PSCAN_ETSI },
   93 
   94 #define F1_5180_5320    AFTER(F8_5180_5240)
   95         { 5240, 5280, 23, 0, 20, 20, DFS_FCC3, PSCAN_FCC | PSCAN_ETSI },
   96 
   97 #define F1_5240_5280    AFTER(F1_5180_5320)
   98         { 5260, 5280, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI },
   99 
  100 #define F1_5260_5280    AFTER(F1_5240_5280)
  101         { 5260, 5320, 18, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI },
  102 
  103 #define F1_5260_5320    AFTER(F1_5260_5280)
  104         { 5260, 5320, 20, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_FCC | PSCAN_ETSI | PSCAN_MKK3  },
  105 #define F2_5260_5320    AFTER(F1_5260_5320)
  106 
  107         { 5260, 5320, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC },
  108 #define F3_5260_5320    AFTER(F2_5260_5320)
  109         { 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC },
  110 #define F4_5260_5320    AFTER(F3_5260_5320)
  111         { 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC },
  112 #define F5_5260_5320    AFTER(F4_5260_5320)
  113         { 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN },
  114 #define F6_5260_5320    AFTER(F5_5260_5320)
  115         { 5260, 5320, 23, 6, 20, 10, DFS_FCC3 | DFS_ETSI, PSCAN_FCC },
  116 #define F7_5260_5320    AFTER(F6_5260_5320)
  117         { 5260, 5320, 23, 6, 20,  5, DFS_FCC3 | DFS_ETSI, PSCAN_FCC },
  118 #define F8_5260_5320    AFTER(F7_5260_5320)
  119 
  120         { 5260, 5700, 5,  6, 20, 20, DFS_FCC3 | DFS_ETSI, NO_PSCAN },
  121 #define F1_5260_5700    AFTER(F8_5260_5320)
  122         { 5260, 5700, 5,  6, 10, 10, DFS_FCC3 | DFS_ETSI, NO_PSCAN },
  123 #define F2_5260_5700    AFTER(F1_5260_5700)
  124         { 5260, 5700, 5,  6,  5,  5, DFS_FCC3 | DFS_ETSI, NO_PSCAN },
  125 #define F3_5260_5700    AFTER(F2_5260_5700)
  126 
  127         { 5280, 5320, 17, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC },
  128 #define F1_5280_5320    AFTER(F3_5260_5700)
  129 
  130         { 5500, 5580, 23, 6, 20, 20, DFS_FCC3, PSCAN_FCC },
  131 #define F1_5500_5580    AFTER(F1_5280_5320)
  132 
  133         { 5500, 5620, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI },
  134 #define F1_5500_5620    AFTER(F1_5500_5580)
  135 
  136         { 5500, 5700, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC },
  137 #define F1_5500_5700    AFTER(F1_5500_5620)
  138         { 5500, 5700, 27, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI },
  139 #define F2_5500_5700    AFTER(F1_5500_5700)
  140         { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI },
  141 #define F3_5500_5700    AFTER(F2_5500_5700)
  142         { 5500, 5700, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_MKK3 | PSCAN_FCC },
  143 #define F4_5500_5700    AFTER(F3_5500_5700)
  144         { 5660, 5720, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI },
  145 #define F2_5660_5720    AFTER(F4_5500_5700)
  146 
  147         { 5745, 5805, 23, 0, 20, 20, NO_DFS, NO_PSCAN },
  148 #define F1_5745_5805    AFTER(F2_5660_5720)
  149         { 5745, 5805, 30, 6, 20, 20, NO_DFS, NO_PSCAN },
  150 #define F2_5745_5805    AFTER(F1_5745_5805)
  151         { 5745, 5805, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI },
  152 #define F3_5745_5805    AFTER(F2_5745_5805)
  153         { 5745, 5825, 5,  6, 20, 20, NO_DFS, NO_PSCAN },
  154 #define F1_5745_5825    AFTER(F3_5745_5805)
  155         { 5745, 5825, 17, 0, 20, 20, NO_DFS, NO_PSCAN },
  156 #define F2_5745_5825    AFTER(F1_5745_5825)
  157         { 5745, 5825, 20, 0, 20, 20, NO_DFS, NO_PSCAN },
  158 #define F3_5745_5825    AFTER(F2_5745_5825)
  159         { 5745, 5825, 30, 0, 20, 20, NO_DFS, NO_PSCAN },
  160 #define F4_5745_5825    AFTER(F3_5745_5825)
  161         { 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN },
  162 #define F5_5745_5825    AFTER(F4_5745_5825)
  163         { 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN },
  164 #define F6_5745_5825    AFTER(F5_5745_5825)
  165         { 5745, 5825, 5,  6, 10, 10, NO_DFS, NO_PSCAN },
  166 #define F7_5745_5825    AFTER(F6_5745_5825)
  167         { 5745, 5825, 5,  6,  5,  5, NO_DFS, NO_PSCAN },
  168 #define F8_5745_5825    AFTER(F7_5745_5825)
  169         { 5745, 5825, 30, 6, 20, 10, NO_DFS, NO_PSCAN },
  170 #define F9_5745_5825    AFTER(F8_5745_5825)
  171         { 5745, 5825, 30, 6, 20,  5, NO_DFS, NO_PSCAN },
  172 #define F10_5745_5825   AFTER(F9_5745_5825)
  173 
  174         /*
  175          * Below are the world roaming channels
  176          * All WWR domains have no power limit, instead use the card's CTL
  177          * or max power settings.
  178          */
  179         { 4920, 4980, 30, 0, 20, 20, NO_DFS, PSCAN_WWR },
  180 #define W1_4920_4980    AFTER(F10_5745_5825)
  181         { 5040, 5080, 30, 0, 20, 20, NO_DFS, PSCAN_WWR },
  182 #define W1_5040_5080    AFTER(W1_4920_4980)
  183         { 5170, 5230, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR },
  184 #define W1_5170_5230    AFTER(W1_5040_5080)
  185         { 5180, 5240, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR },
  186 #define W1_5180_5240    AFTER(W1_5170_5230)
  187         { 5260, 5320, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR },
  188 #define W1_5260_5320    AFTER(W1_5180_5240)
  189         { 5745, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR },
  190 #define W1_5745_5825    AFTER(W1_5260_5320)
  191         { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR },
  192 #define W1_5500_5700    AFTER(W1_5745_5825)
  193         { 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN },
  194 #define W2_5260_5320    AFTER(W1_5500_5700)
  195         { 5180, 5240, 30, 0, 20, 20, NO_DFS, NO_PSCAN },
  196 #define W2_5180_5240    AFTER(W2_5260_5320)
  197         { 5825, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR },
  198 #define W2_5825_5825    AFTER(W2_5180_5240)
  199 };
  200 
  201 /*
  202  * 5GHz Turbo (dynamic & static) tags
  203  */
  204 static REG_DMN_FREQ_BAND regDmn5GhzTurboFreq[] = {
  205         { 5130, 5210, 5,  6, 40, 40, NO_DFS, NO_PSCAN },
  206 #define T1_5130_5210    0
  207         { 5250, 5330, 5,  6, 40, 40, DFS_FCC3, NO_PSCAN },
  208 #define T1_5250_5330    AFTER(T1_5130_5210)
  209         { 5370, 5490, 5,  6, 40, 40, NO_DFS, NO_PSCAN },
  210 #define T1_5370_5490    AFTER(T1_5250_5330)
  211         { 5530, 5650, 5,  6, 40, 40, DFS_FCC3, NO_PSCAN },
  212 #define T1_5530_5650    AFTER(T1_5370_5490)
  213         { 5200, 5200, 23, 6, 40, 40, NO_DFS, NO_PSCAN },
  214 #define T7_5200_5200    AFTER(T1_5530_5650)
  215         { 5150, 5190, 5,  6, 40, 40, NO_DFS, NO_PSCAN },
  216 #define T1_5230_5310    AFTER(T7_5200_5200)
  217         { 5350, 5470, 5,  6, 40, 40, NO_DFS, NO_PSCAN },
  218 #define T1_5150_5190    AFTER(T1_5230_5310)
  219         { 5230, 5310, 5,  6, 40, 40, DFS_FCC3, NO_PSCAN },
  220 #define T1_5350_5470    AFTER(T1_5150_5190)
  221         { 5510, 5670, 5,  6, 40, 40, DFS_FCC3, NO_PSCAN },
  222 #define T1_5510_5670    AFTER(T1_5350_5470)
  223 
  224         { 5200, 5240, 17, 6, 40, 40, NO_DFS, NO_PSCAN },
  225 #define T1_5200_5240    AFTER(T1_5510_5670)
  226         { 5200, 5240, 23, 6, 40, 40, NO_DFS, NO_PSCAN },
  227 #define T2_5200_5240    AFTER(T1_5200_5240)
  228         { 5210, 5210, 17, 6, 40, 40, NO_DFS, NO_PSCAN },
  229 #define T1_5210_5210    AFTER(T2_5200_5240)
  230         { 5210, 5210, 23, 0, 40, 40, NO_DFS, NO_PSCAN },
  231 #define T2_5210_5210    AFTER(T1_5210_5210)
  232         { 5210, 5210, 23, 6, 40, 40, NO_DFS, NO_PSCAN },
  233 #define T7_5210_5210    AFTER(T2_5210_5210)
  234 
  235         { 5240, 5240, 23, 6, 40, 40, NO_DFS, PSCAN_FCC_T },
  236 #define T1_5240_5240    AFTER(T7_5210_5210)
  237         { 5280, 5280, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T },
  238 #define T1_5280_5280    AFTER(T1_5240_5240)
  239         { 5280, 5280, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T },
  240 #define T2_5280_5280    AFTER(T1_5280_5280)
  241         { 5250, 5250, 17, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T },
  242 #define T1_5250_5250    AFTER(T2_5280_5280)
  243         { 5290, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T },
  244 #define T1_5290_5290    AFTER(T1_5250_5250)
  245         { 5250, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T },
  246 #define T1_5250_5290    AFTER(T1_5290_5290)
  247         { 5250, 5290, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T },
  248 #define T2_5250_5290    AFTER(T1_5250_5290)
  249         { 5250, 5290, 23, 6, 40, 40, NO_DFS, PSCAN_FCC_T },
  250 #define T3_5250_5290    AFTER(T2_5250_5290)
  251 
  252         { 5540, 5660, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T },
  253 #define T1_5540_5660    AFTER(T3_5250_5290)
  254         { 5760, 5800, 20, 0, 40, 40, NO_DFS, NO_PSCAN },
  255 #define T1_5760_5800    AFTER(T1_5540_5660)
  256         { 5760, 5800, 30, 6, 40, 40, NO_DFS, NO_PSCAN },
  257 #define T2_5760_5800    AFTER(T1_5760_5800)
  258 
  259         { 5765, 5805, 30, 6, 40, 40, NO_DFS, NO_PSCAN },
  260 #define T1_5765_5805    AFTER(T2_5760_5800)
  261 
  262         /*
  263          * Below are the WWR frequencies
  264          */
  265         { 5210, 5250, 15, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR },
  266 #define WT1_5210_5250   AFTER(T1_5765_5805)
  267         { 5290, 5290, 18, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR },
  268 #define WT1_5290_5290   AFTER(WT1_5210_5250)
  269         { 5540, 5660, 20, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR },
  270 #define WT1_5540_5660   AFTER(WT1_5290_5290)
  271         { 5760, 5800, 20, 0, 40, 40, NO_DFS, PSCAN_WWR },
  272 #define WT1_5760_5800   AFTER(WT1_5540_5660)
  273 };
  274 
  275 /*
  276  * 2GHz 11b channel tags
  277  */
  278 static REG_DMN_FREQ_BAND regDmn2GhzFreq[] = {
  279         { 2312, 2372, 5,  6, 20, 5, NO_DFS, NO_PSCAN },
  280 #define F1_2312_2372    0
  281         { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
  282 #define F2_2312_2372    AFTER(F1_2312_2372)
  283 
  284         { 2412, 2472, 5,  6, 20, 5, NO_DFS, NO_PSCAN },
  285 #define F1_2412_2472    AFTER(F2_2312_2372)
  286         { 2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA },
  287 #define F2_2412_2472    AFTER(F1_2412_2472)
  288         { 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN },
  289 #define F3_2412_2472    AFTER(F2_2412_2472)
  290 
  291         { 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN },
  292 #define F1_2412_2462    AFTER(F3_2412_2472)
  293         { 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA },
  294 #define F2_2412_2462    AFTER(F1_2412_2462)
  295 
  296         { 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
  297 #define F1_2432_2442    AFTER(F2_2412_2462)
  298 
  299         { 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
  300 #define F1_2457_2472    AFTER(F1_2432_2442)
  301 
  302         { 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA },
  303 #define F1_2467_2472    AFTER(F1_2457_2472)
  304 
  305         { 2484, 2484, 5,  6, 20, 5, NO_DFS, NO_PSCAN },
  306 #define F1_2484_2484    AFTER(F1_2467_2472)
  307         { 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA | PSCAN_MKKA1 | PSCAN_MKKA2 },
  308 #define F2_2484_2484    AFTER(F1_2484_2484)
  309 
  310         { 2512, 2732, 5,  6, 20, 5, NO_DFS, NO_PSCAN },
  311 #define F1_2512_2732    AFTER(F2_2484_2484)
  312 
  313         /*
  314          * WWR have powers opened up to 20dBm.
  315          * Limits should often come from CTL/Max powers
  316          */
  317         { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
  318 #define W1_2312_2372    AFTER(F1_2512_2732)
  319         { 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
  320 #define W1_2412_2412    AFTER(W1_2312_2372)
  321         { 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
  322 #define W1_2417_2432    AFTER(W1_2412_2412)
  323         { 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
  324 #define W1_2437_2442    AFTER(W1_2417_2432)
  325         { 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
  326 #define W1_2447_2457    AFTER(W1_2437_2442)
  327         { 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
  328 #define W1_2462_2462    AFTER(W1_2447_2457)
  329         { 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN },
  330 #define W1_2467_2467    AFTER(W1_2462_2462)
  331         { 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN },
  332 #define W2_2467_2467    AFTER(W1_2467_2467)
  333         { 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN },
  334 #define W1_2472_2472    AFTER(W2_2467_2467)
  335         { 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN },
  336 #define W2_2472_2472    AFTER(W1_2472_2472)
  337         { 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN },
  338 #define W1_2484_2484    AFTER(W2_2472_2472)
  339         { 2484, 2484, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN },
  340 #define W2_2484_2484    AFTER(W1_2484_2484)
  341 };
  342 
  343 /*
  344  * 2GHz 11g channel tags
  345  */
  346 static REG_DMN_FREQ_BAND regDmn2Ghz11gFreq[] = {
  347         { 2312, 2372, 5,  6, 20, 5, NO_DFS, NO_PSCAN },
  348 #define G1_2312_2372    0
  349         { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
  350 #define G2_2312_2372    AFTER(G1_2312_2372)
  351         { 2312, 2372, 5,  6, 10, 5, NO_DFS, NO_PSCAN },
  352 #define G3_2312_2372    AFTER(G2_2312_2372)
  353         { 2312, 2372, 5,  6,  5, 5, NO_DFS, NO_PSCAN },
  354 #define G4_2312_2372    AFTER(G3_2312_2372)
  355 
  356         { 2412, 2472, 5,  6, 20, 5, NO_DFS, NO_PSCAN },
  357 #define G1_2412_2472    AFTER(G4_2312_2372)
  358         { 2412, 2472, 20, 0, 20, 5,  NO_DFS, PSCAN_MKKA_G },
  359 #define G2_2412_2472    AFTER(G1_2412_2472)
  360         { 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN },
  361 #define G3_2412_2472    AFTER(G2_2412_2472)
  362         { 2412, 2472, 5,  6, 10, 5, NO_DFS, NO_PSCAN },
  363 #define G4_2412_2472    AFTER(G3_2412_2472)
  364         { 2412, 2472, 5,  6,  5, 5, NO_DFS, NO_PSCAN },
  365 #define G5_2412_2472    AFTER(G4_2412_2472)
  366 
  367         { 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN },
  368 #define G1_2412_2462    AFTER(G5_2412_2472)
  369         { 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G },
  370 #define G2_2412_2462    AFTER(G1_2412_2462)
  371         { 2412, 2462, 27, 6, 10, 5, NO_DFS, NO_PSCAN },
  372 #define G3_2412_2462    AFTER(G2_2412_2462)
  373         { 2412, 2462, 27, 6,  5, 5, NO_DFS, NO_PSCAN },
  374 #define G4_2412_2462    AFTER(G3_2412_2462)
  375 
  376         { 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
  377 #define G1_2432_2442    AFTER(G4_2412_2462)
  378 
  379         { 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
  380 #define G1_2457_2472    AFTER(G1_2432_2442)
  381 
  382         { 2512, 2732, 5,  6, 20, 5, NO_DFS, NO_PSCAN },
  383 #define G1_2512_2732    AFTER(G1_2457_2472)
  384         { 2512, 2732, 5,  6, 10, 5, NO_DFS, NO_PSCAN },
  385 #define G2_2512_2732    AFTER(G1_2512_2732)
  386         { 2512, 2732, 5,  6,  5, 5, NO_DFS, NO_PSCAN },
  387 #define G3_2512_2732    AFTER(G2_2512_2732)
  388 
  389         { 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA },
  390 #define G1_2467_2472    AFTER(G3_2512_2732)
  391 
  392         /*
  393          * WWR open up the power to 20dBm
  394          */
  395         { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
  396 #define WG1_2312_2372   AFTER(G1_2467_2472)
  397         { 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
  398 #define WG1_2412_2412   AFTER(WG1_2312_2372)
  399         { 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
  400 #define WG1_2417_2432   AFTER(WG1_2412_2412)
  401         { 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
  402 #define WG1_2437_2442   AFTER(WG1_2417_2432)
  403         { 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
  404 #define WG1_2447_2457   AFTER(WG1_2437_2442)
  405         { 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN },
  406 #define WG1_2462_2462   AFTER(WG1_2447_2457)
  407         { 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN },
  408 #define WG1_2467_2467   AFTER(WG1_2462_2462)
  409         { 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN },
  410 #define WG2_2467_2467   AFTER(WG1_2467_2467)
  411         { 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN },
  412 #define WG1_2472_2472   AFTER(WG2_2467_2467)
  413         { 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN },
  414 #define WG2_2472_2472   AFTER(WG1_2472_2472)
  415 };
  416 
  417 /*
  418  * 2GHz Dynamic turbo tags
  419  */
  420 static REG_DMN_FREQ_BAND regDmn2Ghz11gTurboFreq[] = {
  421         { 2312, 2372, 5,  6, 40, 40, NO_DFS, NO_PSCAN },
  422 #define T1_2312_2372    0
  423         { 2437, 2437, 5,  6, 40, 40, NO_DFS, NO_PSCAN },
  424 #define T1_2437_2437    AFTER(T1_2312_2372)
  425         { 2437, 2437, 20, 6, 40, 40, NO_DFS, NO_PSCAN },
  426 #define T2_2437_2437    AFTER(T1_2437_2437)
  427         { 2437, 2437, 18, 6, 40, 40, NO_DFS, PSCAN_WWR },
  428 #define T3_2437_2437    AFTER(T2_2437_2437)
  429         { 2512, 2732, 5,  6, 40, 40, NO_DFS, NO_PSCAN },
  430 #define T1_2512_2732    AFTER(T3_2437_2437)
  431 };
  432 
  433 #endif

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