Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/ath/ath_hal/ar5211/ar5211_attach.c
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1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2006 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD$ 20 */ 21 #include "opt_ah.h" 22 23 #include "ah.h" 24 #include "ah_internal.h" 25 #include "ah_devid.h" 26 27 #include "ar5211/ar5211.h" 28 #include "ar5211/ar5211reg.h" 29 #include "ar5211/ar5211phy.h" 30 31 #include "ah_eeprom_v3.h" 32 33 static HAL_BOOL ar5211GetChannelEdges(struct ath_hal *ah, 34 uint16_t flags, uint16_t *low, uint16_t *high); 35 static HAL_BOOL ar5211GetChipPowerLimits(struct ath_hal *ah, 36 struct ieee80211_channel *chan); 37 38 static void ar5211ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 39 HAL_BOOL power_off); 40 static void ar5211DisablePCIE(struct ath_hal *ah); 41 42 static const struct ath_hal_private ar5211hal = {{ 43 .ah_magic = AR5211_MAGIC, 44 45 .ah_getRateTable = ar5211GetRateTable, 46 .ah_detach = ar5211Detach, 47 48 /* Reset Functions */ 49 .ah_reset = ar5211Reset, 50 .ah_phyDisable = ar5211PhyDisable, 51 .ah_disable = ar5211Disable, 52 .ah_configPCIE = ar5211ConfigPCIE, 53 .ah_disablePCIE = ar5211DisablePCIE, 54 .ah_setPCUConfig = ar5211SetPCUConfig, 55 .ah_perCalibration = ar5211PerCalibration, 56 .ah_perCalibrationN = ar5211PerCalibrationN, 57 .ah_resetCalValid = ar5211ResetCalValid, 58 .ah_setTxPowerLimit = ar5211SetTxPowerLimit, 59 .ah_getChanNoise = ath_hal_getChanNoise, 60 61 /* Transmit functions */ 62 .ah_updateTxTrigLevel = ar5211UpdateTxTrigLevel, 63 .ah_setupTxQueue = ar5211SetupTxQueue, 64 .ah_setTxQueueProps = ar5211SetTxQueueProps, 65 .ah_getTxQueueProps = ar5211GetTxQueueProps, 66 .ah_releaseTxQueue = ar5211ReleaseTxQueue, 67 .ah_resetTxQueue = ar5211ResetTxQueue, 68 .ah_getTxDP = ar5211GetTxDP, 69 .ah_setTxDP = ar5211SetTxDP, 70 .ah_numTxPending = ar5211NumTxPending, 71 .ah_startTxDma = ar5211StartTxDma, 72 .ah_stopTxDma = ar5211StopTxDma, 73 .ah_setupTxDesc = ar5211SetupTxDesc, 74 .ah_setupXTxDesc = ar5211SetupXTxDesc, 75 .ah_fillTxDesc = ar5211FillTxDesc, 76 .ah_procTxDesc = ar5211ProcTxDesc, 77 .ah_getTxIntrQueue = ar5211GetTxIntrQueue, 78 .ah_reqTxIntrDesc = ar5211IntrReqTxDesc, 79 .ah_getTxCompletionRates = ar5211GetTxCompletionRates, 80 .ah_setTxDescLink = ar5211SetTxDescLink, 81 .ah_getTxDescLink = ar5211GetTxDescLink, 82 .ah_getTxDescLinkPtr = ar5211GetTxDescLinkPtr, 83 84 /* RX Functions */ 85 .ah_getRxDP = ar5211GetRxDP, 86 .ah_setRxDP = ar5211SetRxDP, 87 .ah_enableReceive = ar5211EnableReceive, 88 .ah_stopDmaReceive = ar5211StopDmaReceive, 89 .ah_startPcuReceive = ar5211StartPcuReceive, 90 .ah_stopPcuReceive = ar5211StopPcuReceive, 91 .ah_setMulticastFilter = ar5211SetMulticastFilter, 92 .ah_setMulticastFilterIndex = ar5211SetMulticastFilterIndex, 93 .ah_clrMulticastFilterIndex = ar5211ClrMulticastFilterIndex, 94 .ah_getRxFilter = ar5211GetRxFilter, 95 .ah_setRxFilter = ar5211SetRxFilter, 96 .ah_setupRxDesc = ar5211SetupRxDesc, 97 .ah_procRxDesc = ar5211ProcRxDesc, 98 .ah_rxMonitor = ar5211RxMonitor, 99 .ah_aniPoll = ar5211AniPoll, 100 .ah_procMibEvent = ar5211MibEvent, 101 102 /* Misc Functions */ 103 .ah_getCapability = ar5211GetCapability, 104 .ah_setCapability = ar5211SetCapability, 105 .ah_getDiagState = ar5211GetDiagState, 106 .ah_getMacAddress = ar5211GetMacAddress, 107 .ah_setMacAddress = ar5211SetMacAddress, 108 .ah_getBssIdMask = ar5211GetBssIdMask, 109 .ah_setBssIdMask = ar5211SetBssIdMask, 110 .ah_setRegulatoryDomain = ar5211SetRegulatoryDomain, 111 .ah_setLedState = ar5211SetLedState, 112 .ah_writeAssocid = ar5211WriteAssocid, 113 .ah_gpioCfgInput = ar5211GpioCfgInput, 114 .ah_gpioCfgOutput = ar5211GpioCfgOutput, 115 .ah_gpioGet = ar5211GpioGet, 116 .ah_gpioSet = ar5211GpioSet, 117 .ah_gpioSetIntr = ar5211GpioSetIntr, 118 .ah_getTsf32 = ar5211GetTsf32, 119 .ah_getTsf64 = ar5211GetTsf64, 120 .ah_resetTsf = ar5211ResetTsf, 121 .ah_detectCardPresent = ar5211DetectCardPresent, 122 .ah_updateMibCounters = ar5211UpdateMibCounters, 123 .ah_getRfGain = ar5211GetRfgain, 124 .ah_getDefAntenna = ar5211GetDefAntenna, 125 .ah_setDefAntenna = ar5211SetDefAntenna, 126 .ah_getAntennaSwitch = ar5211GetAntennaSwitch, 127 .ah_setAntennaSwitch = ar5211SetAntennaSwitch, 128 .ah_setSifsTime = ar5211SetSifsTime, 129 .ah_getSifsTime = ar5211GetSifsTime, 130 .ah_setSlotTime = ar5211SetSlotTime, 131 .ah_getSlotTime = ar5211GetSlotTime, 132 .ah_setAckTimeout = ar5211SetAckTimeout, 133 .ah_getAckTimeout = ar5211GetAckTimeout, 134 .ah_setAckCTSRate = ar5211SetAckCTSRate, 135 .ah_getAckCTSRate = ar5211GetAckCTSRate, 136 .ah_setCTSTimeout = ar5211SetCTSTimeout, 137 .ah_getCTSTimeout = ar5211GetCTSTimeout, 138 .ah_setDecompMask = ar5211SetDecompMask, 139 .ah_setCoverageClass = ar5211SetCoverageClass, 140 .ah_setQuiet = ar5211SetQuiet, 141 .ah_get11nExtBusy = ar5211Get11nExtBusy, 142 .ah_getMibCycleCounts = ar5211GetMibCycleCounts, 143 .ah_setChainMasks = ar5211SetChainMasks, 144 .ah_enableDfs = ar5211EnableDfs, 145 .ah_getDfsThresh = ar5211GetDfsThresh, 146 /* XXX procRadarEvent */ 147 /* XXX isFastClockEnabled */ 148 .ah_setNav = ar5211SetNav, 149 .ah_getNav = ar5211GetNav, 150 151 /* Key Cache Functions */ 152 .ah_getKeyCacheSize = ar5211GetKeyCacheSize, 153 .ah_resetKeyCacheEntry = ar5211ResetKeyCacheEntry, 154 .ah_isKeyCacheEntryValid = ar5211IsKeyCacheEntryValid, 155 .ah_setKeyCacheEntry = ar5211SetKeyCacheEntry, 156 .ah_setKeyCacheEntryMac = ar5211SetKeyCacheEntryMac, 157 158 /* Power Management Functions */ 159 .ah_setPowerMode = ar5211SetPowerMode, 160 .ah_getPowerMode = ar5211GetPowerMode, 161 162 /* Beacon Functions */ 163 .ah_setBeaconTimers = ar5211SetBeaconTimers, 164 .ah_beaconInit = ar5211BeaconInit, 165 .ah_setStationBeaconTimers = ar5211SetStaBeaconTimers, 166 .ah_resetStationBeaconTimers = ar5211ResetStaBeaconTimers, 167 .ah_getNextTBTT = ar5211GetNextTBTT, 168 169 /* Interrupt Functions */ 170 .ah_isInterruptPending = ar5211IsInterruptPending, 171 .ah_getPendingInterrupts = ar5211GetPendingInterrupts, 172 .ah_getInterrupts = ar5211GetInterrupts, 173 .ah_setInterrupts = ar5211SetInterrupts }, 174 175 .ah_getChannelEdges = ar5211GetChannelEdges, 176 .ah_getWirelessModes = ar5211GetWirelessModes, 177 .ah_eepromRead = ar5211EepromRead, 178 #ifdef AH_SUPPORT_WRITE_EEPROM 179 .ah_eepromWrite = ar5211EepromWrite, 180 #endif 181 .ah_getChipPowerLimits = ar5211GetChipPowerLimits, 182 }; 183 184 static HAL_BOOL ar5211ChipTest(struct ath_hal *); 185 static HAL_BOOL ar5211FillCapabilityInfo(struct ath_hal *ah); 186 187 /* 188 * Return the revsion id for the radio chip. This 189 * fetched via the PHY. 190 */ 191 static uint32_t 192 ar5211GetRadioRev(struct ath_hal *ah) 193 { 194 uint32_t val; 195 int i; 196 197 OS_REG_WRITE(ah, (AR_PHY_BASE + (0x34 << 2)), 0x00001c16); 198 for (i = 0; i < 8; i++) 199 OS_REG_WRITE(ah, (AR_PHY_BASE + (0x20 << 2)), 0x00010000); 200 val = (OS_REG_READ(ah, AR_PHY_BASE + (256 << 2)) >> 24) & 0xff; 201 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 202 return ath_hal_reverseBits(val, 8); 203 } 204 205 /* 206 * Attach for an AR5211 part. 207 */ 208 static struct ath_hal * 209 ar5211Attach(uint16_t devid, HAL_SOFTC sc, 210 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 211 HAL_OPS_CONFIG *ah_config, HAL_STATUS *status) 212 { 213 #define N(a) (sizeof(a)/sizeof(a[0])) 214 struct ath_hal_5211 *ahp; 215 struct ath_hal *ah; 216 uint32_t val; 217 uint16_t eeval; 218 HAL_STATUS ecode; 219 220 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 221 __func__, sc, (void*) st, (void*) sh); 222 223 /* NB: memory is returned zero'd */ 224 ahp = ath_hal_malloc(sizeof (struct ath_hal_5211)); 225 if (ahp == AH_NULL) { 226 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 227 "%s: cannot allocate memory for state block\n", __func__); 228 ecode = HAL_ENOMEM; 229 goto bad; 230 } 231 ah = &ahp->ah_priv.h; 232 /* set initial values */ 233 OS_MEMCPY(&ahp->ah_priv, &ar5211hal, sizeof(struct ath_hal_private)); 234 ah->ah_sc = sc; 235 ah->ah_st = st; 236 ah->ah_sh = sh; 237 238 ah->ah_devid = devid; /* NB: for AH_DEBUG_ALQ */ 239 AH_PRIVATE(ah)->ah_devid = devid; 240 AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */ 241 242 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 243 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 244 245 ahp->ah_diversityControl = HAL_ANT_VARIABLE; 246 ahp->ah_staId1Defaults = 0; 247 ahp->ah_rssiThr = INIT_RSSI_THR; 248 ahp->ah_sifstime = (u_int) -1; 249 ahp->ah_slottime = (u_int) -1; 250 ahp->ah_acktimeout = (u_int) -1; 251 ahp->ah_ctstimeout = (u_int) -1; 252 253 if (!ar5211ChipReset(ah, AH_NULL)) { /* reset chip */ 254 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 255 ecode = HAL_EIO; 256 goto bad; 257 } 258 if (AH_PRIVATE(ah)->ah_devid == AR5211_FPGA11B) { 259 /* set it back to OFDM mode to be able to read analog rev id */ 260 OS_REG_WRITE(ah, AR5211_PHY_MODE, AR5211_PHY_MODE_OFDM); 261 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_44); 262 OS_DELAY(1000); 263 } 264 265 /* Read Revisions from Chips */ 266 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID_M; 267 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 268 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION_M; 269 270 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_MAUI_2 || 271 AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_OAHU) { 272 HALDEBUG(ah, HAL_DEBUG_ANY, 273 "%s: Mac Chip Rev 0x%x is not supported by this driver\n", 274 __func__, AH_PRIVATE(ah)->ah_macVersion); 275 ecode = HAL_ENOTSUPP; 276 goto bad; 277 } 278 279 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 280 281 if (!ar5211ChipTest(ah)) { 282 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 283 __func__); 284 ecode = HAL_ESELFTEST; 285 goto bad; 286 } 287 288 /* Set correct Baseband to analog shift setting to access analog chips. */ 289 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) { 290 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007); 291 } else { 292 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000047); 293 } 294 OS_DELAY(2000); 295 296 /* Read Radio Chip Rev Extract */ 297 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5211GetRadioRev(ah); 298 if ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xf0) != RAD5_SREV_MAJOR) { 299 HALDEBUG(ah, HAL_DEBUG_ANY, 300 "%s: 5G Radio Chip Rev 0x%02X is not supported by this " 301 "driver\n", __func__, AH_PRIVATE(ah)->ah_analog5GhzRev); 302 ecode = HAL_ENOTSUPP; 303 goto bad; 304 } 305 306 val = (OS_REG_READ(ah, AR_PCICFG) & AR_PCICFG_EEPROM_SIZE_M) >> 307 AR_PCICFG_EEPROM_SIZE_S; 308 if (val != AR_PCICFG_EEPROM_SIZE_16K) { 309 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unsupported EEPROM size " 310 "%u (0x%x) found\n", __func__, val, val); 311 ecode = HAL_EESIZE; 312 goto bad; 313 } 314 ecode = ath_hal_legacyEepromAttach(ah); 315 if (ecode != HAL_OK) { 316 goto bad; 317 } 318 319 /* If Bmode and AR5211, verify 2.4 analog exists */ 320 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU && 321 ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) { 322 /* Set correct Baseband to analog shift setting to access analog chips. */ 323 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00004007); 324 OS_DELAY(2000); 325 AH_PRIVATE(ah)->ah_analog2GhzRev = ar5211GetRadioRev(ah); 326 327 /* Set baseband for 5GHz chip */ 328 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007); 329 OS_DELAY(2000); 330 if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != RAD2_SREV_MAJOR) { 331 HALDEBUG(ah, HAL_DEBUG_ANY, 332 "%s: 2G Radio Chip Rev 0x%x is not supported by " 333 "this driver\n", __func__, 334 AH_PRIVATE(ah)->ah_analog2GhzRev); 335 ecode = HAL_ENOTSUPP; 336 goto bad; 337 } 338 } else { 339 ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_FALSE); 340 } 341 342 ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval); 343 if (ecode != HAL_OK) { 344 HALDEBUG(ah, HAL_DEBUG_ANY, 345 "%s: cannot read regulatory domain from EEPROM\n", 346 __func__); 347 goto bad; 348 } 349 AH_PRIVATE(ah)->ah_currentRD = eeval; 350 AH_PRIVATE(ah)->ah_getNfAdjust = ar5211GetNfAdjust; 351 352 /* 353 * Got everything we need now to setup the capabilities. 354 */ 355 (void) ar5211FillCapabilityInfo(ah); 356 357 /* Initialize gain ladder thermal calibration structure */ 358 ar5211InitializeGainValues(ah); 359 360 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 361 if (ecode != HAL_OK) { 362 HALDEBUG(ah, HAL_DEBUG_ANY, 363 "%s: error getting mac address from EEPROM\n", __func__); 364 goto bad; 365 } 366 367 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 368 369 return ah; 370 bad: 371 if (ahp) 372 ar5211Detach((struct ath_hal *) ahp); 373 if (status) 374 *status = ecode; 375 return AH_NULL; 376 #undef N 377 } 378 379 void 380 ar5211Detach(struct ath_hal *ah) 381 { 382 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 383 384 HALASSERT(ah != AH_NULL); 385 HALASSERT(ah->ah_magic == AR5211_MAGIC); 386 387 ath_hal_eepromDetach(ah); 388 ath_hal_free(ah); 389 } 390 391 static HAL_BOOL 392 ar5211ChipTest(struct ath_hal *ah) 393 { 394 uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) }; 395 uint32_t regHold[2]; 396 uint32_t patternData[4] = 397 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 398 int i, j; 399 400 /* Test PHY & MAC registers */ 401 for (i = 0; i < 2; i++) { 402 uint32_t addr = regAddr[i]; 403 uint32_t wrData, rdData; 404 405 regHold[i] = OS_REG_READ(ah, addr); 406 for (j = 0; j < 0x100; j++) { 407 wrData = (j << 16) | j; 408 OS_REG_WRITE(ah, addr, wrData); 409 rdData = OS_REG_READ(ah, addr); 410 if (rdData != wrData) { 411 HALDEBUG(ah, HAL_DEBUG_ANY, 412 "%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 413 __func__, addr, wrData, rdData); 414 return AH_FALSE; 415 } 416 } 417 for (j = 0; j < 4; j++) { 418 wrData = patternData[j]; 419 OS_REG_WRITE(ah, addr, wrData); 420 rdData = OS_REG_READ(ah, addr); 421 if (wrData != rdData) { 422 HALDEBUG(ah, HAL_DEBUG_ANY, 423 "%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 424 __func__, addr, wrData, rdData); 425 return AH_FALSE; 426 } 427 } 428 OS_REG_WRITE(ah, regAddr[i], regHold[i]); 429 } 430 OS_DELAY(100); 431 return AH_TRUE; 432 } 433 434 /* 435 * Store the channel edges for the requested operational mode 436 */ 437 static HAL_BOOL 438 ar5211GetChannelEdges(struct ath_hal *ah, 439 uint16_t flags, uint16_t *low, uint16_t *high) 440 { 441 if (flags & IEEE80211_CHAN_5GHZ) { 442 *low = 4920; 443 *high = 6100; 444 return AH_TRUE; 445 } 446 if (flags & IEEE80211_CHAN_2GHZ && 447 ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) { 448 *low = 2312; 449 *high = 2732; 450 return AH_TRUE; 451 } 452 return AH_FALSE; 453 } 454 455 static HAL_BOOL 456 ar5211GetChipPowerLimits(struct ath_hal *ah, struct ieee80211_channel *chan) 457 { 458 /* XXX fill in, this is just a placeholder */ 459 HALDEBUG(ah, HAL_DEBUG_ATTACH, 460 "%s: no min/max power for %u/0x%x\n", 461 __func__, chan->ic_freq, chan->ic_flags); 462 chan->ic_maxpower = MAX_RATE_POWER; 463 chan->ic_minpower = 0; 464 return AH_TRUE; 465 } 466 467 static void 468 ar5211ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 469 { 470 } 471 472 static void 473 ar5211DisablePCIE(struct ath_hal *ah) 474 { 475 } 476 477 /* 478 * Fill all software cached or static hardware state information. 479 */ 480 static HAL_BOOL 481 ar5211FillCapabilityInfo(struct ath_hal *ah) 482 { 483 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 484 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 485 486 /* Construct wireless mode from EEPROM */ 487 pCap->halWirelessModes = 0; 488 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 489 pCap->halWirelessModes |= HAL_MODE_11A; 490 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE)) 491 pCap->halWirelessModes |= HAL_MODE_TURBO; 492 } 493 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) 494 pCap->halWirelessModes |= HAL_MODE_11B; 495 496 pCap->halLow2GhzChan = 2312; 497 pCap->halHigh2GhzChan = 2732; 498 pCap->halLow5GhzChan = 4920; 499 pCap->halHigh5GhzChan = 6100; 500 501 pCap->halChanSpreadSupport = AH_TRUE; 502 pCap->halSleepAfterBeaconBroken = AH_TRUE; 503 pCap->halPSPollBroken = AH_TRUE; 504 pCap->halVEOLSupport = AH_TRUE; 505 pCap->halNumMRRetries = 1; /* No hardware MRR support */ 506 pCap->halNumTxMaps = 1; /* Single TX ptr per descr */ 507 508 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 509 pCap->halKeyCacheSize = 128; 510 511 /* XXX not needed */ 512 pCap->halChanHalfRate = AH_FALSE; 513 pCap->halChanQuarterRate = AH_FALSE; 514 515 /* 516 * RSSI uses the combined field; some 11n NICs may use 517 * the control chain RSSI. 518 */ 519 pCap->halUseCombinedRadarRssi = AH_TRUE; 520 521 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 522 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 523 /* NB: enabled by default */ 524 ahpriv->ah_rfkillEnabled = AH_TRUE; 525 pCap->halRfSilentSupport = AH_TRUE; 526 } 527 528 pCap->halRxTstampPrecision = 13; 529 pCap->halTxTstampPrecision = 16; 530 pCap->halIntrMask = HAL_INT_COMMON 531 | HAL_INT_RX 532 | HAL_INT_TX 533 | HAL_INT_FATAL 534 | HAL_INT_BNR 535 | HAL_INT_TIM 536 ; 537 538 pCap->hal4kbSplitTransSupport = AH_TRUE; 539 pCap->halHasRxSelfLinkedTail = AH_TRUE; 540 541 /* XXX might be ok w/ some chip revs */ 542 ahpriv->ah_rxornIsFatal = AH_TRUE; 543 return AH_TRUE; 544 } 545 546 static const char* 547 ar5211Probe(uint16_t vendorid, uint16_t devid) 548 { 549 if (vendorid == ATHEROS_VENDOR_ID) { 550 if (devid == AR5211_DEVID || devid == AR5311_DEVID || 551 devid == AR5211_DEFAULT) 552 return "Atheros 5211"; 553 if (devid == AR5211_FPGA11B) 554 return "Atheros 5211 (FPGA)"; 555 } 556 return AH_NULL; 557 } 558 AH_CHIP(AR5211, ar5211Probe, ar5211Attach);
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