The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

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    1 /*-
    2  * SPDX-License-Identifier: ISC
    3  *
    4  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
    5  * Copyright (c) 2002-2006 Atheros Communications, Inc.
    6  *
    7  * Permission to use, copy, modify, and/or distribute this software for any
    8  * purpose with or without fee is hereby granted, provided that the above
    9  * copyright notice and this permission notice appear in all copies.
   10  *
   11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   18  *
   19  * $FreeBSD$
   20  */
   21 #include "opt_ah.h"
   22 
   23 #include "ah.h"
   24 #include "ah_internal.h"
   25 
   26 #include "ar5211/ar5211.h"
   27 #include "ar5211/ar5211reg.h"
   28 #include "ar5211/ar5211desc.h"
   29 
   30 /*
   31  * Routines used to initialize and generated beacons for the AR5211/AR5311.
   32  */
   33 
   34 /*
   35  * Return the hardware NextTBTT in TSF
   36  */
   37 uint64_t
   38 ar5211GetNextTBTT(struct ath_hal *ah)
   39 {
   40 #define TU_TO_TSF(_tu)  (((uint64_t)(_tu)) << 10)
   41         return TU_TO_TSF(OS_REG_READ(ah, AR_TIMER0));
   42 #undef TU_TO_TSF
   43 }
   44 
   45 /*
   46  * Initialize all of the hardware registers used to send beacons.
   47  */
   48 void
   49 ar5211SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt)
   50 {
   51 
   52         OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt);
   53         OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba);
   54         OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba);
   55         OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim);
   56         /*
   57          * Set the Beacon register after setting all timers.
   58          */
   59         OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);
   60 }
   61 
   62 /*
   63  * Legacy api to initialize all of the beacon registers.
   64  */
   65 void
   66 ar5211BeaconInit(struct ath_hal *ah,
   67         uint32_t next_beacon, uint32_t beacon_period)
   68 {
   69         HAL_BEACON_TIMERS bt;
   70 
   71         bt.bt_nexttbtt = next_beacon;
   72         /* 
   73          * TIMER1: in AP/adhoc mode this controls the DMA beacon
   74          * alert timer; otherwise it controls the next wakeup time.
   75          * TIMER2: in AP mode, it controls the SBA beacon alert
   76          * interrupt; otherwise it sets the start of the next CFP.
   77          */
   78         switch (AH_PRIVATE(ah)->ah_opmode) {
   79         case HAL_M_STA:
   80         case HAL_M_MONITOR:
   81                 bt.bt_nextdba = 0xffff;
   82                 bt.bt_nextswba = 0x7ffff;
   83                 break;
   84         case HAL_M_IBSS:
   85         case HAL_M_HOSTAP:
   86                 bt.bt_nextdba = (next_beacon -
   87                         ah->ah_config.ah_dma_beacon_response_time) << 3;        /* 1/8 TU */
   88                 bt.bt_nextswba = (next_beacon -
   89             ah->ah_config.ah_sw_beacon_response_time) << 3;     /* 1/8 TU */
   90                 break;
   91         }
   92         /*
   93          * Set the ATIM window 
   94          * Our hardware does not support an ATIM window of 0
   95          * (beacons will not work).  If the ATIM windows is 0,
   96          * force it to 1.
   97          */
   98         bt.bt_nextatim = next_beacon + 1;
   99         bt.bt_intval = beacon_period &
  100                 (AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN);
  101         ar5211SetBeaconTimers(ah, &bt);
  102 }
  103 
  104 void
  105 ar5211ResetStaBeaconTimers(struct ath_hal *ah)
  106 {
  107         uint32_t val;
  108 
  109         OS_REG_WRITE(ah, AR_TIMER0, 0);         /* no beacons */
  110         val = OS_REG_READ(ah, AR_STA_ID1);
  111         val |= AR_STA_ID1_PWR_SAV;              /* XXX */
  112         /* tell the h/w that the associated AP is not PCF capable */
  113         OS_REG_WRITE(ah, AR_STA_ID1,
  114                 val & ~(AR_STA_ID1_DEFAULT_ANTENNA | AR_STA_ID1_PCF));
  115         OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);
  116 }
  117 
  118 /*
  119  * Set all the beacon related bits on the h/w for stations
  120  * i.e. initializes the corresponding h/w timers;
  121  * also tells the h/w whether to anticipate PCF beacons
  122  */
  123 void
  124 ar5211SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)
  125 {
  126         struct ath_hal_5211 *ahp = AH5211(ah);
  127 
  128         HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: setting beacon timers\n", __func__);
  129 
  130         HALASSERT(bs->bs_intval != 0);
  131         /* if the AP will do PCF */
  132         if (bs->bs_cfpmaxduration != 0) {
  133                 /* tell the h/w that the associated AP is PCF capable */
  134                 OS_REG_WRITE(ah, AR_STA_ID1,
  135                         OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF);
  136 
  137                 /* set CFP_PERIOD(1.024ms) register */
  138                 OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod);
  139 
  140                 /* set CFP_DUR(1.024ms) register to max cfp duration */
  141                 OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration);
  142 
  143                 /* set TIMER2(128us) to anticipated time of next CFP */
  144                 OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3);
  145         } else {
  146                 /* tell the h/w that the associated AP is not PCF capable */
  147                 OS_REG_WRITE(ah, AR_STA_ID1,
  148                         OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF);
  149         }
  150 
  151         /*
  152          * Set TIMER0(1.024ms) to the anticipated time of the next beacon.
  153          */
  154         OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt);
  155 
  156         /*
  157          * Start the beacon timers by setting the BEACON register
  158          * to the beacon interval; also write the tim offset which
  159          * we should know by now.  The code, in ar5211WriteAssocid,
  160          * also sets the tim offset once the AID is known which can
  161          * be left as such for now.
  162          */
  163         OS_REG_WRITE(ah, AR_BEACON, 
  164                 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
  165                 | SM(bs->bs_intval, AR_BEACON_PERIOD)
  166                 | SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM)
  167         );
  168 
  169         /*
  170          * Configure the BMISS interrupt.  Note that we
  171          * assume the caller blocks interrupts while enabling
  172          * the threshold.
  173          */
  174         HALASSERT(bs->bs_bmissthreshold <= MS(0xffffffff, AR_RSSI_THR_BM_THR));
  175         ahp->ah_rssiThr = (ahp->ah_rssiThr &~ AR_RSSI_THR_BM_THR)
  176                         | SM(bs->bs_bmissthreshold, AR_RSSI_THR_BM_THR);
  177         OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
  178 
  179         /*
  180          * Set the sleep duration in 1/8 TU's.
  181          */
  182 #define SLEEP_SLOP      3
  183         OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLDUR,
  184                 (bs->bs_sleepduration - SLEEP_SLOP) << 3);
  185 #undef SLEEP_SLOP
  186 }

Cache object: 4471f9c6c31f4f54b27b8d26259cfa2c


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