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sys/dev/ath/ath_hal/ar5212/ar5212_attach.c
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1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD$ 20 */ 21 #include "opt_ah.h" 22 23 #include "ah.h" 24 #include "ah_internal.h" 25 #include "ah_devid.h" 26 27 #include "ar5212/ar5212.h" 28 #include "ar5212/ar5212reg.h" 29 #include "ar5212/ar5212phy.h" 30 31 #define AH_5212_COMMON 32 #include "ar5212/ar5212.ini" 33 34 static void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 35 HAL_BOOL power_off); 36 static void ar5212DisablePCIE(struct ath_hal *ah); 37 38 static const struct ath_hal_private ar5212hal = {{ 39 .ah_magic = AR5212_MAGIC, 40 41 .ah_getRateTable = ar5212GetRateTable, 42 .ah_detach = ar5212Detach, 43 44 /* Reset Functions */ 45 .ah_reset = ar5212Reset, 46 .ah_phyDisable = ar5212PhyDisable, 47 .ah_disable = ar5212Disable, 48 .ah_configPCIE = ar5212ConfigPCIE, 49 .ah_disablePCIE = ar5212DisablePCIE, 50 .ah_setPCUConfig = ar5212SetPCUConfig, 51 .ah_perCalibration = ar5212PerCalibration, 52 .ah_perCalibrationN = ar5212PerCalibrationN, 53 .ah_resetCalValid = ar5212ResetCalValid, 54 .ah_setTxPowerLimit = ar5212SetTxPowerLimit, 55 .ah_getChanNoise = ath_hal_getChanNoise, 56 57 /* Transmit functions */ 58 .ah_updateTxTrigLevel = ar5212UpdateTxTrigLevel, 59 .ah_setupTxQueue = ar5212SetupTxQueue, 60 .ah_setTxQueueProps = ar5212SetTxQueueProps, 61 .ah_getTxQueueProps = ar5212GetTxQueueProps, 62 .ah_releaseTxQueue = ar5212ReleaseTxQueue, 63 .ah_resetTxQueue = ar5212ResetTxQueue, 64 .ah_getTxDP = ar5212GetTxDP, 65 .ah_setTxDP = ar5212SetTxDP, 66 .ah_numTxPending = ar5212NumTxPending, 67 .ah_startTxDma = ar5212StartTxDma, 68 .ah_stopTxDma = ar5212StopTxDma, 69 .ah_setupTxDesc = ar5212SetupTxDesc, 70 .ah_setupXTxDesc = ar5212SetupXTxDesc, 71 .ah_fillTxDesc = ar5212FillTxDesc, 72 .ah_procTxDesc = ar5212ProcTxDesc, 73 .ah_getTxIntrQueue = ar5212GetTxIntrQueue, 74 .ah_reqTxIntrDesc = ar5212IntrReqTxDesc, 75 .ah_getTxCompletionRates = ar5212GetTxCompletionRates, 76 .ah_setTxDescLink = ar5212SetTxDescLink, 77 .ah_getTxDescLink = ar5212GetTxDescLink, 78 .ah_getTxDescLinkPtr = ar5212GetTxDescLinkPtr, 79 80 /* RX Functions */ 81 .ah_getRxDP = ar5212GetRxDP, 82 .ah_setRxDP = ar5212SetRxDP, 83 .ah_enableReceive = ar5212EnableReceive, 84 .ah_stopDmaReceive = ar5212StopDmaReceive, 85 .ah_startPcuReceive = ar5212StartPcuReceive, 86 .ah_stopPcuReceive = ar5212StopPcuReceive, 87 .ah_setMulticastFilter = ar5212SetMulticastFilter, 88 .ah_setMulticastFilterIndex = ar5212SetMulticastFilterIndex, 89 .ah_clrMulticastFilterIndex = ar5212ClrMulticastFilterIndex, 90 .ah_getRxFilter = ar5212GetRxFilter, 91 .ah_setRxFilter = ar5212SetRxFilter, 92 .ah_setupRxDesc = ar5212SetupRxDesc, 93 .ah_procRxDesc = ar5212ProcRxDesc, 94 .ah_rxMonitor = ar5212RxMonitor, 95 .ah_aniPoll = ar5212AniPoll, 96 .ah_procMibEvent = ar5212ProcessMibIntr, 97 98 /* Misc Functions */ 99 .ah_getCapability = ar5212GetCapability, 100 .ah_setCapability = ar5212SetCapability, 101 .ah_getDiagState = ar5212GetDiagState, 102 .ah_getMacAddress = ar5212GetMacAddress, 103 .ah_setMacAddress = ar5212SetMacAddress, 104 .ah_getBssIdMask = ar5212GetBssIdMask, 105 .ah_setBssIdMask = ar5212SetBssIdMask, 106 .ah_setRegulatoryDomain = ar5212SetRegulatoryDomain, 107 .ah_setLedState = ar5212SetLedState, 108 .ah_writeAssocid = ar5212WriteAssocid, 109 .ah_gpioCfgInput = ar5212GpioCfgInput, 110 .ah_gpioCfgOutput = ar5212GpioCfgOutput, 111 .ah_gpioGet = ar5212GpioGet, 112 .ah_gpioSet = ar5212GpioSet, 113 .ah_gpioSetIntr = ar5212GpioSetIntr, 114 .ah_getTsf32 = ar5212GetTsf32, 115 .ah_getTsf64 = ar5212GetTsf64, 116 .ah_setTsf64 = ar5212SetTsf64, 117 .ah_resetTsf = ar5212ResetTsf, 118 .ah_detectCardPresent = ar5212DetectCardPresent, 119 .ah_updateMibCounters = ar5212UpdateMibCounters, 120 .ah_getRfGain = ar5212GetRfgain, 121 .ah_getDefAntenna = ar5212GetDefAntenna, 122 .ah_setDefAntenna = ar5212SetDefAntenna, 123 .ah_getAntennaSwitch = ar5212GetAntennaSwitch, 124 .ah_setAntennaSwitch = ar5212SetAntennaSwitch, 125 .ah_setSifsTime = ar5212SetSifsTime, 126 .ah_getSifsTime = ar5212GetSifsTime, 127 .ah_setSlotTime = ar5212SetSlotTime, 128 .ah_getSlotTime = ar5212GetSlotTime, 129 .ah_setAckTimeout = ar5212SetAckTimeout, 130 .ah_getAckTimeout = ar5212GetAckTimeout, 131 .ah_setAckCTSRate = ar5212SetAckCTSRate, 132 .ah_getAckCTSRate = ar5212GetAckCTSRate, 133 .ah_setCTSTimeout = ar5212SetCTSTimeout, 134 .ah_getCTSTimeout = ar5212GetCTSTimeout, 135 .ah_setDecompMask = ar5212SetDecompMask, 136 .ah_setCoverageClass = ar5212SetCoverageClass, 137 .ah_setQuiet = ar5212SetQuiet, 138 .ah_getMibCycleCounts = ar5212GetMibCycleCounts, 139 .ah_setChainMasks = ar5212SetChainMasks, 140 .ah_getNav = ar5212GetNav, 141 .ah_setNav = ar5212SetNav, 142 143 /* DFS Functions */ 144 .ah_enableDfs = ar5212EnableDfs, 145 .ah_getDfsThresh = ar5212GetDfsThresh, 146 .ah_getDfsDefaultThresh = ar5212GetDfsDefaultThresh, 147 .ah_procRadarEvent = ar5212ProcessRadarEvent, 148 .ah_isFastClockEnabled = ar5212IsFastClockEnabled, 149 .ah_get11nExtBusy = ar5212Get11nExtBusy, 150 151 /* Key Cache Functions */ 152 .ah_getKeyCacheSize = ar5212GetKeyCacheSize, 153 .ah_resetKeyCacheEntry = ar5212ResetKeyCacheEntry, 154 .ah_isKeyCacheEntryValid = ar5212IsKeyCacheEntryValid, 155 .ah_setKeyCacheEntry = ar5212SetKeyCacheEntry, 156 .ah_setKeyCacheEntryMac = ar5212SetKeyCacheEntryMac, 157 158 /* Power Management Functions */ 159 .ah_setPowerMode = ar5212SetPowerMode, 160 .ah_getPowerMode = ar5212GetPowerMode, 161 162 /* Beacon Functions */ 163 .ah_setBeaconTimers = ar5212SetBeaconTimers, 164 .ah_beaconInit = ar5212BeaconInit, 165 .ah_setStationBeaconTimers = ar5212SetStaBeaconTimers, 166 .ah_resetStationBeaconTimers = ar5212ResetStaBeaconTimers, 167 .ah_getNextTBTT = ar5212GetNextTBTT, 168 169 /* Interrupt Functions */ 170 .ah_isInterruptPending = ar5212IsInterruptPending, 171 .ah_getPendingInterrupts = ar5212GetPendingInterrupts, 172 .ah_getInterrupts = ar5212GetInterrupts, 173 .ah_setInterrupts = ar5212SetInterrupts }, 174 175 .ah_getChannelEdges = ar5212GetChannelEdges, 176 .ah_getWirelessModes = ar5212GetWirelessModes, 177 .ah_eepromRead = ar5212EepromRead, 178 #ifdef AH_SUPPORT_WRITE_EEPROM 179 .ah_eepromWrite = ar5212EepromWrite, 180 #endif 181 .ah_getChipPowerLimits = ar5212GetChipPowerLimits, 182 }; 183 184 uint32_t 185 ar5212GetRadioRev(struct ath_hal *ah) 186 { 187 uint32_t val; 188 int i; 189 190 /* Read Radio Chip Rev Extract */ 191 OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16); 192 for (i = 0; i < 8; i++) 193 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 194 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 195 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 196 return ath_hal_reverseBits(val, 8); 197 } 198 199 static void 200 ar5212AniSetup(struct ath_hal *ah) 201 { 202 static const struct ar5212AniParams aniparams = { 203 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 204 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 205 .coarseHigh = { -14, -14, -14, -14, -12 }, 206 .coarseLow = { -64, -64, -64, -64, -70 }, 207 .firpwr = { -78, -78, -78, -78, -80 }, 208 .maxSpurImmunityLevel = 2, /* NB: depends on chip rev */ 209 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 210 .maxFirstepLevel = 2, /* levels 0..2 */ 211 .firstep = { 0, 4, 8 }, 212 .ofdmTrigHigh = 500, 213 .ofdmTrigLow = 200, 214 .cckTrigHigh = 200, 215 .cckTrigLow = 100, 216 .rssiThrHigh = 40, 217 .rssiThrLow = 7, 218 .period = 100, 219 }; 220 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) { 221 struct ar5212AniParams tmp; 222 OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams)); 223 tmp.maxSpurImmunityLevel = 7; /* Venice and earlier */ 224 ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE); 225 } else 226 ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 227 228 /* Set overridable ANI methods */ 229 AH5212(ah)->ah_aniControl = ar5212AniControl; 230 } 231 232 /* 233 * Attach for an AR5212 part. 234 */ 235 void 236 ar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc, 237 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 238 { 239 #define N(a) (sizeof(a)/sizeof(a[0])) 240 static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] = 241 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 242 struct ath_hal *ah; 243 244 ah = &ahp->ah_priv.h; 245 /* set initial values */ 246 OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private)); 247 ah->ah_sc = sc; 248 ah->ah_st = st; 249 ah->ah_sh = sh; 250 251 ah->ah_devid = devid; /* NB: for alq */ 252 AH_PRIVATE(ah)->ah_devid = devid; 253 AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */ 254 255 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 256 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 257 258 ahp->ah_antControl = HAL_ANT_VARIABLE; 259 ahp->ah_diversity = AH_TRUE; 260 ahp->ah_bIQCalibration = AH_FALSE; 261 /* 262 * Enable MIC handling. 263 */ 264 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 265 ahp->ah_rssiThr = INIT_RSSI_THR; 266 ahp->ah_tpcEnabled = AH_FALSE; /* disabled by default */ 267 ahp->ah_phyPowerOn = AH_FALSE; 268 ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK) 269 | SM(MAX_RATE_POWER, AR_TPC_CTS) 270 | SM(MAX_RATE_POWER, AR_TPC_CHIRP); 271 ahp->ah_beaconInterval = 100; /* XXX [20..1000] */ 272 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */ 273 ahp->ah_slottime = (u_int) -1; 274 ahp->ah_acktimeout = (u_int) -1; 275 ahp->ah_ctstimeout = (u_int) -1; 276 ahp->ah_sifstime = (u_int) -1; 277 ahp->ah_txTrigLev = INIT_TX_FIFO_THRESHOLD; 278 ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD; 279 280 OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN); 281 #undef N 282 } 283 284 /* 285 * Validate MAC version and revision. 286 */ 287 static HAL_BOOL 288 ar5212IsMacSupported(uint8_t macVersion, uint8_t macRev) 289 { 290 #define N(a) (sizeof(a)/sizeof(a[0])) 291 static const struct { 292 uint8_t version; 293 uint8_t revMin, revMax; 294 } macs[] = { 295 { AR_SREV_VERSION_VENICE, 296 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 297 { AR_SREV_VERSION_GRIFFIN, 298 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 299 { AR_SREV_5413, 300 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 301 { AR_SREV_5424, 302 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 303 { AR_SREV_2425, 304 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 305 { AR_SREV_2417, 306 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 307 }; 308 int i; 309 310 for (i = 0; i < N(macs); i++) 311 if (macs[i].version == macVersion && 312 macs[i].revMin <= macRev && macRev <= macs[i].revMax) 313 return AH_TRUE; 314 return AH_FALSE; 315 #undef N 316 } 317 318 /* 319 * Attach for an AR5212 part. 320 */ 321 static struct ath_hal * 322 ar5212Attach(uint16_t devid, HAL_SOFTC sc, 323 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 324 HAL_OPS_CONFIG *ah_config, HAL_STATUS *status) 325 { 326 #define AH_EEPROM_PROTECT(ah) \ 327 (AH_PRIVATE(ah)->ah_ispcie)? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT) 328 struct ath_hal_5212 *ahp; 329 struct ath_hal *ah; 330 struct ath_hal_rf *rf; 331 uint32_t val; 332 uint16_t eeval; 333 HAL_STATUS ecode; 334 335 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 336 __func__, sc, (void*) st, (void*) sh); 337 338 /* NB: memory is returned zero'd */ 339 ahp = ath_hal_malloc(sizeof (struct ath_hal_5212)); 340 if (ahp == AH_NULL) { 341 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 342 "%s: cannot allocate memory for state block\n", __func__); 343 *status = HAL_ENOMEM; 344 return AH_NULL; 345 } 346 ar5212InitState(ahp, devid, sc, st, sh, status); 347 ah = &ahp->ah_priv.h; 348 349 if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 350 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 351 __func__); 352 ecode = HAL_EIO; 353 goto bad; 354 } 355 /* Read Revisions from Chips before taking out of reset */ 356 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 357 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 358 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 359 AH_PRIVATE(ah)->ah_ispcie = IS_5424(ah) || IS_2425(ah); 360 361 if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) { 362 HALDEBUG(ah, HAL_DEBUG_ANY, 363 "%s: Mac Chip Rev 0x%02x.%x not supported\n" , 364 __func__, AH_PRIVATE(ah)->ah_macVersion, 365 AH_PRIVATE(ah)->ah_macRev); 366 ecode = HAL_ENOTSUPP; 367 goto bad; 368 } 369 370 /* setup common ini data; rf backends handle remainder */ 371 HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6); 372 HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2); 373 374 if (!ar5212ChipReset(ah, AH_NULL)) { /* reset chip */ 375 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 376 ecode = HAL_EIO; 377 goto bad; 378 } 379 380 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 381 382 if (AH_PRIVATE(ah)->ah_ispcie) { 383 /* XXX: build flag to disable this? */ 384 ath_hal_configPCIE(ah, AH_FALSE, AH_FALSE); 385 } 386 387 if (!ar5212ChipTest(ah)) { 388 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 389 __func__); 390 ecode = HAL_ESELFTEST; 391 goto bad; 392 } 393 394 /* Enable PCI core retry fix in software for Hainan and up */ 395 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE) 396 OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN); 397 398 /* 399 * Set correct Baseband to analog shift 400 * setting to access analog chips. 401 */ 402 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 403 404 /* Read Radio Chip Rev Extract */ 405 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 406 407 rf = ath_hal_rfprobe(ah, &ecode); 408 if (rf == AH_NULL) 409 goto bad; 410 411 /* NB: silently accept anything in release code per Atheros */ 412 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 413 case AR_RAD5111_SREV_MAJOR: 414 case AR_RAD5112_SREV_MAJOR: 415 case AR_RAD2112_SREV_MAJOR: 416 case AR_RAD2111_SREV_MAJOR: 417 case AR_RAD2413_SREV_MAJOR: 418 case AR_RAD5413_SREV_MAJOR: 419 case AR_RAD5424_SREV_MAJOR: 420 break; 421 default: 422 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 423 /* 424 * When RF_Silent is used, the 425 * analog chip is reset. So when the system boots 426 * up with the radio switch off we cannot determine 427 * the RF chip rev. To workaround this check the 428 * mac+phy revs and if Hainan, set the radio rev 429 * to Derby. 430 */ 431 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 432 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN && 433 AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) { 434 AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN; 435 break; 436 } 437 if (IS_2413(ah)) { /* Griffin */ 438 AH_PRIVATE(ah)->ah_analog5GhzRev = 439 AR_RAD2413_SREV_MAJOR | 0x1; 440 break; 441 } 442 if (IS_5413(ah)) { /* Eagle */ 443 AH_PRIVATE(ah)->ah_analog5GhzRev = 444 AR_RAD5413_SREV_MAJOR | 0x2; 445 break; 446 } 447 if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */ 448 AH_PRIVATE(ah)->ah_analog5GhzRev = 449 AR_RAD5424_SREV_MAJOR | 0x2; 450 break; 451 } 452 } 453 #ifdef AH_DEBUG 454 HALDEBUG(ah, HAL_DEBUG_ANY, 455 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 456 "this driver\n", 457 __func__, AH_PRIVATE(ah)->ah_analog5GhzRev); 458 ecode = HAL_ENOTSUPP; 459 goto bad; 460 #endif 461 } 462 if (IS_RAD5112_REV1(ah)) { 463 HALDEBUG(ah, HAL_DEBUG_ANY, 464 "%s: 5112 Rev 1 is not supported by this " 465 "driver (analog5GhzRev 0x%x)\n", __func__, 466 AH_PRIVATE(ah)->ah_analog5GhzRev); 467 ecode = HAL_ENOTSUPP; 468 goto bad; 469 } 470 471 val = OS_REG_READ(ah, AR_PCICFG); 472 val = MS(val, AR_PCICFG_EEPROM_SIZE); 473 if (val == 0) { 474 if (!AH_PRIVATE(ah)->ah_ispcie) { 475 HALDEBUG(ah, HAL_DEBUG_ANY, 476 "%s: unsupported EEPROM size %u (0x%x) found\n", 477 __func__, val, val); 478 ecode = HAL_EESIZE; 479 goto bad; 480 } 481 /* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */ 482 } else if (val != AR_PCICFG_EEPROM_SIZE_16K) { 483 if (AR_PCICFG_EEPROM_SIZE_FAILED == val) { 484 HALDEBUG(ah, HAL_DEBUG_ANY, 485 "%s: unsupported EEPROM size %u (0x%x) found\n", 486 __func__, val, val); 487 ecode = HAL_EESIZE; 488 goto bad; 489 } 490 HALDEBUG(ah, HAL_DEBUG_ANY, 491 "%s: EEPROM size = %d. Must be %d (16k).\n", 492 __func__, val, AR_PCICFG_EEPROM_SIZE_16K); 493 ecode = HAL_EESIZE; 494 goto bad; 495 } 496 ecode = ath_hal_legacyEepromAttach(ah); 497 if (ecode != HAL_OK) { 498 goto bad; 499 } 500 ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON); 501 502 /* 503 * If Bmode and AR5212, verify 2.4 analog exists 504 */ 505 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) && 506 (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) { 507 /* 508 * Set correct Baseband to analog shift 509 * setting to access analog chips. 510 */ 511 OS_REG_WRITE(ah, AR_PHY(0), 0x00004007); 512 OS_DELAY(2000); 513 AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah); 514 515 /* Set baseband for 5GHz chip */ 516 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 517 OS_DELAY(2000); 518 if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) { 519 HALDEBUG(ah, HAL_DEBUG_ANY, 520 "%s: 2G Radio Chip Rev 0x%02X is not " 521 "supported by this driver\n", __func__, 522 AH_PRIVATE(ah)->ah_analog2GhzRev); 523 ecode = HAL_ENOTSUPP; 524 goto bad; 525 } 526 } 527 528 ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval); 529 if (ecode != HAL_OK) { 530 HALDEBUG(ah, HAL_DEBUG_ANY, 531 "%s: cannot read regulatory domain from EEPROM\n", 532 __func__); 533 goto bad; 534 } 535 AH_PRIVATE(ah)->ah_currentRD = eeval; 536 /* XXX record serial number */ 537 538 /* 539 * Got everything we need now to setup the capabilities. 540 */ 541 if (!ar5212FillCapabilityInfo(ah)) { 542 HALDEBUG(ah, HAL_DEBUG_ANY, 543 "%s: failed ar5212FillCapabilityInfo\n", __func__); 544 ecode = HAL_EEREAD; 545 goto bad; 546 } 547 548 if (!rf->attach(ah, &ecode)) { 549 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 550 __func__, ecode); 551 goto bad; 552 } 553 /* 554 * Set noise floor adjust method; we arrange a 555 * direct call instead of thunking. 556 */ 557 AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust; 558 559 /* Initialize gain ladder thermal calibration structure */ 560 ar5212InitializeGainValues(ah); 561 562 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 563 if (ecode != HAL_OK) { 564 HALDEBUG(ah, HAL_DEBUG_ANY, 565 "%s: error getting mac address from EEPROM\n", __func__); 566 goto bad; 567 } 568 569 ar5212AniSetup(ah); 570 /* Setup of Radar/AR structures happens in ath_hal_initchannels*/ 571 ar5212InitNfCalHistBuffer(ah); 572 573 /* XXX EAR stuff goes here */ 574 575 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 576 577 return ah; 578 579 bad: 580 if (ahp) 581 ar5212Detach((struct ath_hal *) ahp); 582 if (status) 583 *status = ecode; 584 return AH_NULL; 585 #undef AH_EEPROM_PROTECT 586 } 587 588 void 589 ar5212Detach(struct ath_hal *ah) 590 { 591 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 592 593 HALASSERT(ah != AH_NULL); 594 HALASSERT(ah->ah_magic == AR5212_MAGIC); 595 596 ar5212AniDetach(ah); 597 ar5212RfDetach(ah); 598 ar5212Disable(ah); 599 ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 600 601 ath_hal_eepromDetach(ah); 602 ath_hal_free(ah); 603 } 604 605 HAL_BOOL 606 ar5212ChipTest(struct ath_hal *ah) 607 { 608 uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) }; 609 uint32_t regHold[2]; 610 uint32_t patternData[4] = 611 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 612 int i, j; 613 614 /* Test PHY & MAC registers */ 615 for (i = 0; i < 2; i++) { 616 uint32_t addr = regAddr[i]; 617 uint32_t wrData, rdData; 618 619 regHold[i] = OS_REG_READ(ah, addr); 620 for (j = 0; j < 0x100; j++) { 621 wrData = (j << 16) | j; 622 OS_REG_WRITE(ah, addr, wrData); 623 rdData = OS_REG_READ(ah, addr); 624 if (rdData != wrData) { 625 HALDEBUG(ah, HAL_DEBUG_ANY, 626 "%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 627 __func__, addr, wrData, rdData); 628 return AH_FALSE; 629 } 630 } 631 for (j = 0; j < 4; j++) { 632 wrData = patternData[j]; 633 OS_REG_WRITE(ah, addr, wrData); 634 rdData = OS_REG_READ(ah, addr); 635 if (wrData != rdData) { 636 HALDEBUG(ah, HAL_DEBUG_ANY, 637 "%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 638 __func__, addr, wrData, rdData); 639 return AH_FALSE; 640 } 641 } 642 OS_REG_WRITE(ah, regAddr[i], regHold[i]); 643 } 644 OS_DELAY(100); 645 return AH_TRUE; 646 } 647 648 /* 649 * Store the channel edges for the requested operational mode 650 */ 651 HAL_BOOL 652 ar5212GetChannelEdges(struct ath_hal *ah, 653 uint16_t flags, uint16_t *low, uint16_t *high) 654 { 655 if (flags & IEEE80211_CHAN_5GHZ) { 656 *low = 4915; 657 *high = 6100; 658 return AH_TRUE; 659 } 660 if ((flags & IEEE80211_CHAN_2GHZ) && 661 (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) || 662 ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) { 663 *low = 2312; 664 *high = 2732; 665 return AH_TRUE; 666 } 667 return AH_FALSE; 668 } 669 670 /* 671 * Disable PLL when in L0s as well as receiver clock when in L1. 672 * This power saving option must be enabled through the Serdes. 673 * 674 * Programming the Serdes must go through the same 288 bit serial shift 675 * register as the other analog registers. Hence the 9 writes. 676 * 677 * XXX Clean up the magic numbers. 678 */ 679 static void 680 ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 681 { 682 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 683 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 684 685 /* RX shut off when elecidle is asserted */ 686 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 687 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 688 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 689 690 /* Shut off PLL and CLKREQ active in L1 */ 691 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 692 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 693 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 694 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); 695 696 /* Load the new settings */ 697 OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 698 } 699 700 static void 701 ar5212DisablePCIE(struct ath_hal *ah) 702 { 703 /* NB: fill in for 9100 */ 704 } 705 706 /* 707 * Fill all software cached or static hardware state information. 708 * Return failure if capabilities are to come from EEPROM and 709 * cannot be read. 710 */ 711 HAL_BOOL 712 ar5212FillCapabilityInfo(struct ath_hal *ah) 713 { 714 #define AR_KEYTABLE_SIZE 128 715 #define IS_GRIFFIN_LITE(ah) \ 716 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \ 717 AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE) 718 #define IS_COBRA(ah) \ 719 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA) 720 #define IS_2112(ah) \ 721 ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR) 722 723 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 724 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 725 uint16_t capField, val; 726 727 /* Read the capability EEPROM location */ 728 if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) { 729 HALDEBUG(ah, HAL_DEBUG_ANY, 730 "%s: unable to read caps from eeprom\n", __func__); 731 return AH_FALSE; 732 } 733 if (IS_2112(ah)) 734 ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE); 735 if (capField == 0 && IS_GRIFFIN_LITE(ah)) { 736 /* 737 * For griffin-lite cards with unprogrammed capabilities. 738 */ 739 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 740 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 741 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 742 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 743 HALDEBUG(ah, HAL_DEBUG_ATTACH, 744 "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n", 745 __func__, capField); 746 } 747 748 /* Modify reg domain on newer cards that need to work with older sw */ 749 if (ahpriv->ah_opmode != HAL_M_HOSTAP && 750 ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) { 751 if (ahpriv->ah_currentRD == 0x64 || 752 ahpriv->ah_currentRD == 0x65) 753 ahpriv->ah_currentRD += 5; 754 else if (ahpriv->ah_currentRD == 0x41) 755 ahpriv->ah_currentRD = 0x43; 756 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n", 757 __func__, ahpriv->ah_currentRD); 758 } 759 760 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 || 761 AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) { 762 HALDEBUG(ah, HAL_DEBUG_ATTACH, 763 "%s: enable Bmode and disable turbo for Swan/Nala\n", 764 __func__); 765 ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE); 766 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 767 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 768 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 769 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 770 } 771 772 /* Construct wireless mode from EEPROM */ 773 pCap->halWirelessModes = 0; 774 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 775 pCap->halWirelessModes |= HAL_MODE_11A; 776 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE)) 777 pCap->halWirelessModes |= HAL_MODE_TURBO; 778 } 779 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) 780 pCap->halWirelessModes |= HAL_MODE_11B; 781 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) && 782 ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) { 783 pCap->halWirelessModes |= HAL_MODE_11G; 784 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE)) 785 pCap->halWirelessModes |= HAL_MODE_108G; 786 } 787 788 pCap->halLow2GhzChan = 2312; 789 /* XXX 2417 too? */ 790 if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah)) 791 pCap->halHigh2GhzChan = 2500; 792 else 793 pCap->halHigh2GhzChan = 2732; 794 795 /* 796 * For AR5111 version < 4, the lowest centre frequency supported is 797 * 5130MHz. For AR5111 version 4, the 4.9GHz channels are supported 798 * but only in 10MHz increments. 799 * 800 * In addition, the programming method is wrong - it uses the IEEE 801 * channel number to calculate the frequency, rather than the 802 * channel centre. Since half/quarter rates re-use some of the 803 * 5GHz channel IEEE numbers, this will result in a badly programmed 804 * synth. 805 * 806 * Until the relevant support is written, just limit lower frequency 807 * support for AR5111 so things aren't incorrectly programmed. 808 * 809 * XXX It's also possible this code doesn't correctly limit the 810 * centre frequencies of potential channels; this is very important 811 * for half/quarter rate! 812 */ 813 if (AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR) { 814 pCap->halLow5GhzChan = 5120; /* XXX lowest centre = 5130MHz */ 815 } else { 816 pCap->halLow5GhzChan = 4915; 817 } 818 pCap->halHigh5GhzChan = 6100; 819 820 pCap->halCipherCkipSupport = AH_FALSE; 821 pCap->halCipherTkipSupport = AH_TRUE; 822 pCap->halCipherAesCcmSupport = 823 (ath_hal_eepromGetFlag(ah, AR_EEP_AES) && 824 ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) || 825 ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) && 826 (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU)))); 827 828 pCap->halMicCkipSupport = AH_FALSE; 829 pCap->halMicTkipSupport = AH_TRUE; 830 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 831 /* 832 * Starting with Griffin TX+RX mic keys can be combined 833 * in one key cache slot. 834 */ 835 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN) 836 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 837 else 838 pCap->halTkipMicTxRxKeySupport = AH_FALSE; 839 pCap->halChanSpreadSupport = AH_TRUE; 840 pCap->halSleepAfterBeaconBroken = AH_TRUE; 841 842 if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) { 843 pCap->halCompressSupport = 844 ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) && 845 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 846 pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST); 847 pCap->halFastFramesSupport = 848 ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) && 849 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 850 pCap->halChapTuningSupport = AH_TRUE; 851 pCap->halTurboPrimeSupport = AH_TRUE; 852 } 853 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 854 855 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 856 pCap->halNumMRRetries = 4; /* Hardware supports 4 MRR */ 857 pCap->halNumTxMaps = 1; /* Single TX ptr per descr */ 858 pCap->halVEOLSupport = AH_TRUE; 859 pCap->halBssIdMaskSupport = AH_TRUE; 860 pCap->halMcastKeySrchSupport = AH_TRUE; 861 if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE && 862 ahpriv->ah_macRev == 8) || 863 ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE) 864 pCap->halTsfAddSupport = AH_TRUE; 865 866 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 867 pCap->halTotalQueues = val; 868 else 869 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 870 871 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 872 pCap->halKeyCacheSize = val; 873 else 874 pCap->halKeyCacheSize = AR_KEYTABLE_SIZE; 875 876 pCap->halChanHalfRate = AH_TRUE; 877 pCap->halChanQuarterRate = AH_TRUE; 878 879 /* 880 * RSSI uses the combined field; some 11n NICs may use 881 * the control chain RSSI. 882 */ 883 pCap->halUseCombinedRadarRssi = AH_TRUE; 884 885 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 886 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 887 /* NB: enabled by default */ 888 ahpriv->ah_rfkillEnabled = AH_TRUE; 889 pCap->halRfSilentSupport = AH_TRUE; 890 } 891 892 /* NB: this is a guess, no one seems to know the answer */ 893 ahpriv->ah_rxornIsFatal = 894 (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE); 895 896 /* enable features that first appeared in Hainan */ 897 if ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 898 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) || 899 AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) { 900 /* h/w phy counters */ 901 pCap->halHwPhyCounterSupport = AH_TRUE; 902 /* bssid match disable */ 903 pCap->halBssidMatchSupport = AH_TRUE; 904 } 905 906 pCap->halRxTstampPrecision = 15; 907 pCap->halTxTstampPrecision = 16; 908 pCap->halIntrMask = HAL_INT_COMMON 909 | HAL_INT_RX 910 | HAL_INT_TX 911 | HAL_INT_FATAL 912 | HAL_INT_BNR 913 | HAL_INT_BMISC 914 ; 915 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) 916 pCap->halIntrMask &= ~HAL_INT_TBTT; 917 918 pCap->hal4kbSplitTransSupport = AH_TRUE; 919 pCap->halHasRxSelfLinkedTail = AH_TRUE; 920 921 return AH_TRUE; 922 #undef IS_COBRA 923 #undef IS_GRIFFIN_LITE 924 #undef AR_KEYTABLE_SIZE 925 } 926 927 static const char* 928 ar5212Probe(uint16_t vendorid, uint16_t devid) 929 { 930 if (vendorid == ATHEROS_VENDOR_ID || 931 vendorid == ATHEROS_3COM_VENDOR_ID || 932 vendorid == ATHEROS_3COM2_VENDOR_ID) { 933 switch (devid) { 934 case AR5212_FPGA: 935 return "Atheros 5212 (FPGA)"; 936 case AR5212_DEVID: 937 case AR5212_DEVID_IBM: 938 case AR5212_DEFAULT: 939 return "Atheros 5212"; 940 case AR5212_AR2413: 941 return "Atheros 2413"; 942 case AR5212_AR2417: 943 return "Atheros 2417"; 944 case AR5212_AR5413: 945 return "Atheros 5413"; 946 case AR5212_AR5424: 947 return "Atheros 5424/2424"; 948 } 949 } 950 return AH_NULL; 951 } 952 AH_CHIP(AR5212, ar5212Probe, ar5212Attach);
Cache object: 8fce490dcdeb8c2b1a972c2d73bd6295
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