The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c

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    1 /*-
    2  * SPDX-License-Identifier: ISC
    3  *
    4  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
    5  * Copyright (c) 2002-2008 Atheros Communications, Inc.
    6  *
    7  * Permission to use, copy, modify, and/or distribute this software for any
    8  * purpose with or without fee is hereby granted, provided that the above
    9  * copyright notice and this permission notice appear in all copies.
   10  *
   11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   18  *
   19  * $FreeBSD$
   20  */
   21 #include "opt_ah.h"
   22 
   23 #include "ah.h"
   24 #include "ah_internal.h"
   25 #include "ah_devid.h"
   26 
   27 #include "ar5416/ar5416.h"
   28 #include "ar5416/ar5416reg.h"
   29 #include "ar5416/ar5416phy.h"
   30 
   31 /* Adc DC Offset Cal aliases */
   32 #define totalAdcDcOffsetIOddPhase(i)    caldata[0][i].s
   33 #define totalAdcDcOffsetIEvenPhase(i)   caldata[1][i].s
   34 #define totalAdcDcOffsetQOddPhase(i)    caldata[2][i].s
   35 #define totalAdcDcOffsetQEvenPhase(i)   caldata[3][i].s
   36 
   37 void
   38 ar5416AdcDcCalCollect(struct ath_hal *ah)
   39 {
   40         struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
   41         int i;
   42 
   43         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
   44                 cal->totalAdcDcOffsetIOddPhase(i) += (int32_t)
   45                     OS_REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
   46                 cal->totalAdcDcOffsetIEvenPhase(i) += (int32_t)
   47                     OS_REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
   48                 cal->totalAdcDcOffsetQOddPhase(i) += (int32_t)
   49                     OS_REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
   50                 cal->totalAdcDcOffsetQEvenPhase(i) += (int32_t)
   51                     OS_REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
   52 
   53                 HALDEBUG(ah, HAL_DEBUG_PERCAL,
   54                     "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",
   55                    cal->calSamples, i,
   56                    cal->totalAdcDcOffsetIOddPhase(i),
   57                    cal->totalAdcDcOffsetIEvenPhase(i),
   58                    cal->totalAdcDcOffsetQOddPhase(i),
   59                    cal->totalAdcDcOffsetQEvenPhase(i));
   60         }
   61 }
   62 
   63 void
   64 ar5416AdcDcCalibration(struct ath_hal *ah, uint8_t numChains)
   65 {
   66         struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
   67         const HAL_PERCAL_DATA *calData = cal->cal_curr->calData;
   68         uint32_t numSamples;
   69         int i;
   70 
   71         numSamples = (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
   72         for (i = 0; i < numChains; i++) {
   73                 uint32_t iOddMeasOffset = cal->totalAdcDcOffsetIOddPhase(i);
   74                 uint32_t iEvenMeasOffset = cal->totalAdcDcOffsetIEvenPhase(i);
   75                 int32_t qOddMeasOffset = cal->totalAdcDcOffsetQOddPhase(i);
   76                 int32_t qEvenMeasOffset = cal->totalAdcDcOffsetQEvenPhase(i);
   77                 int32_t qDcMismatch, iDcMismatch;
   78                 uint32_t val;
   79 
   80                 HALDEBUG(ah, HAL_DEBUG_PERCAL,
   81                     "Starting ADC DC Offset Cal for Chain %d\n", i);
   82 
   83                 HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_odd_i = %d\n",
   84                     iOddMeasOffset);
   85                 HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_even_i = %d\n",
   86                     iEvenMeasOffset);
   87                 HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_odd_q = %d\n",
   88                     qOddMeasOffset);
   89                 HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_even_q = %d\n",
   90                     qEvenMeasOffset);
   91 
   92                 HALASSERT(numSamples);
   93 
   94                 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
   95                     numSamples) & 0x1ff;
   96                 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
   97                     numSamples) & 0x1ff;
   98                 HALDEBUG(ah, HAL_DEBUG_PERCAL,
   99                     " dc_offset_mismatch_i = 0x%08x\n", iDcMismatch);
  100                 HALDEBUG(ah, HAL_DEBUG_PERCAL,
  101                     " dc_offset_mismatch_q = 0x%08x\n", qDcMismatch);
  102 
  103                 val = OS_REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
  104                 val &= 0xc0000fff;
  105                 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
  106                 OS_REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); 
  107 
  108                 HALDEBUG(ah, HAL_DEBUG_PERCAL,
  109                     "ADC DC Offset Cal done for Chain %d\n", i);
  110         }
  111         OS_REG_SET_BIT(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
  112             AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
  113 }

Cache object: 042ed8114ebf4d554fcdc4aa51096efa


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