ar5416_recv.c

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    1 /*-
    2  * SPDX-License-Identifier: ISC
    3  *
    4  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
    5  * Copyright (c) 2002-2008 Atheros Communications, Inc.
    6  *
    7  * Permission to use, copy, modify, and/or distribute this software for any
    8  * purpose with or without fee is hereby granted, provided that the above
    9  * copyright notice and this permission notice appear in all copies.
   10  *
   11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   18  *
   19  * $FreeBSD$
   20  */
   21 #include "opt_ah.h"
   22 
   23 #include "ah.h"
   24 #include "ah_desc.h"
   25 #include "ah_internal.h"
   26 
   27 #include "ar5416/ar5416.h"
   28 #include "ar5416/ar5416reg.h"
   29 #include "ar5416/ar5416desc.h"
   30 
   31 /*
   32  * Get the receive filter.
   33  */
   34 uint32_t
   35 ar5416GetRxFilter(struct ath_hal *ah)
   36 {
   37         uint32_t bits = OS_REG_READ(ah, AR_RX_FILTER);
   38         uint32_t phybits = OS_REG_READ(ah, AR_PHY_ERR);
   39 
   40         if (phybits & AR_PHY_ERR_RADAR)
   41                 bits |= HAL_RX_FILTER_PHYRADAR;
   42         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
   43                 bits |= HAL_RX_FILTER_PHYERR;
   44         return bits;
   45 }
   46 
   47 /*
   48  * Set the receive filter.
   49  */
   50 void
   51 ar5416SetRxFilter(struct ath_hal *ah, u_int32_t bits)
   52 {
   53         uint32_t phybits;
   54 
   55         OS_REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff));
   56         phybits = 0;
   57         if (bits & HAL_RX_FILTER_PHYRADAR)
   58                 phybits |= AR_PHY_ERR_RADAR;
   59         if (bits & HAL_RX_FILTER_PHYERR)
   60                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
   61         OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
   62         if (phybits) {
   63                 OS_REG_WRITE(ah, AR_RXCFG,
   64                     OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
   65         } else {
   66                 OS_REG_WRITE(ah, AR_RXCFG,
   67                     OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
   68         }
   69 }
   70 
   71 /*
   72  * Stop Receive at the DMA engine
   73  */
   74 HAL_BOOL
   75 ar5416StopDmaReceive(struct ath_hal *ah)
   76 {
   77         HAL_BOOL status;
   78 
   79         OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP);
   80         OS_REG_WRITE(ah, AR_CR, AR_CR_RXD);     /* Set receive disable bit */
   81         if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
   82                 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP_ERR);
   83 #ifdef AH_DEBUG
   84                 ath_hal_printf(ah, "%s: dma failed to stop in 10ms\n"
   85                         "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
   86                         __func__,
   87                         OS_REG_READ(ah, AR_CR),
   88                         OS_REG_READ(ah, AR_DIAG_SW));
   89 #endif
   90                 status = AH_FALSE;
   91         } else {
   92                 status = AH_TRUE;
   93         }
   94 
   95         /*
   96          * XXX Is this to flush whatever is in a FIFO somewhere?
   97          * XXX If so, what should the correct behaviour should be?
   98          */
   99         if (AR_SREV_9100(ah))
  100                 OS_DELAY(3000);
  101 
  102         return (status);
  103 }
  104 
  105 /*
  106  * Start receive at the PCU engine
  107  */
  108 void
  109 ar5416StartPcuReceive(struct ath_hal *ah, HAL_BOOL is_scanning)
  110 {
  111         struct ath_hal_private *ahp = AH_PRIVATE(ah);
  112 
  113         HALDEBUG(ah, HAL_DEBUG_RX, "%s: Start PCU Receive \n", __func__);
  114         ar5212EnableMibCounters(ah);
  115         /* NB: restore current settings if we're not scanning */
  116         ar5416AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, ! is_scanning);
  117         /*
  118          * NB: must do after enabling phy errors to avoid rx
  119          *     frames w/ corrupted descriptor status.
  120          */
  121         OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
  122 }
  123 
  124 /*
  125  * Stop receive at the PCU engine
  126  * and abort current frame in PCU
  127  */
  128 void
  129 ar5416StopPcuReceive(struct ath_hal *ah)
  130 {
  131         OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
  132     
  133         HALDEBUG(ah, HAL_DEBUG_RX, "%s: Stop PCU Receive \n", __func__);
  134         ar5212DisableMibCounters(ah);
  135 }
  136 
  137 /*
  138  * Initialize RX descriptor, by clearing the status and setting
  139  * the size (and any other flags).
  140  */
  141 HAL_BOOL
  142 ar5416SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,
  143     uint32_t size, u_int flags)
  144 {
  145         struct ar5416_desc *ads = AR5416DESC(ds);
  146 
  147         HALASSERT((size &~ AR_BufLen) == 0);
  148 
  149         ads->ds_ctl1 = size & AR_BufLen;
  150         if (flags & HAL_RXDESC_INTREQ)
  151                 ads->ds_ctl1 |= AR_RxIntrReq;
  152 
  153         /* this should be enough */
  154         ads->ds_rxstatus8 &= ~AR_RxDone;
  155 
  156         /* clear the rest of the status fields */
  157         OS_MEMZERO(&(ads->u), sizeof(ads->u));
  158 
  159         return AH_TRUE;
  160 }
  161 
  162 /*
  163  * Process an RX descriptor, and return the status to the caller.
  164  * Copy some hardware specific items into the software portion
  165  * of the descriptor.
  166  *
  167  * NB: the caller is responsible for validating the memory contents
  168  *     of the descriptor (e.g. flushing any cached copy).
  169  */
  170 HAL_STATUS
  171 ar5416ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
  172     uint32_t pa, struct ath_desc *nds, uint64_t tsf,
  173     struct ath_rx_status *rs)
  174 {
  175         struct ar5416_desc *ads = AR5416DESC(ds);
  176 
  177         if ((ads->ds_rxstatus8 & AR_RxDone) == 0)
  178                 return HAL_EINPROGRESS;
  179 
  180         rs->rs_status = 0;
  181         rs->rs_flags = 0;
  182 
  183         rs->rs_datalen = ads->ds_rxstatus1 & AR_DataLen;
  184         rs->rs_tstamp =  ads->AR_RcvTimestamp;
  185 
  186         rs->rs_rssi = MS(ads->ds_rxstatus4, AR_RxRSSICombined);
  187         rs->rs_rssi_ctl[0] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt00);
  188         rs->rs_rssi_ctl[1] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt01);
  189         rs->rs_rssi_ctl[2] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt02);
  190         rs->rs_rssi_ext[0] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt10);
  191         rs->rs_rssi_ext[1] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt11);
  192         rs->rs_rssi_ext[2] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt12);
  193 
  194         if (ads->ds_rxstatus8 & AR_RxKeyIdxValid)
  195                 rs->rs_keyix = MS(ads->ds_rxstatus8, AR_KeyIdx);
  196         else
  197                 rs->rs_keyix = HAL_RXKEYIX_INVALID;
  198 
  199         /* NB: caller expected to do rate table mapping */
  200         rs->rs_rate = RXSTATUS_RATE(ah, ads);
  201         rs->rs_more = (ads->ds_rxstatus1 & AR_RxMore) ? 1 : 0;
  202 
  203         rs->rs_isaggr = (ads->ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
  204         rs->rs_moreaggr = (ads->ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
  205         rs->rs_antenna = MS(ads->ds_rxstatus3, AR_RxAntenna);
  206 
  207         if (ads->ds_rxstatus3 & AR_GI)
  208                 rs->rs_flags |= HAL_RX_GI;
  209         if (ads->ds_rxstatus3 & AR_2040)
  210                 rs->rs_flags |= HAL_RX_2040;
  211 
  212         /*
  213          * Only the AR9280 and later chips support STBC RX, so
  214          * ensure we only set this bit for those chips.
  215          */
  216         if (AR_SREV_MERLIN_10_OR_LATER(ah)
  217             && ads->ds_rxstatus3 & AR_STBCFrame)
  218                 rs->rs_flags |= HAL_RX_STBC;
  219 
  220         if (ads->ds_rxstatus8 & AR_PreDelimCRCErr)
  221                 rs->rs_flags |= HAL_RX_DELIM_CRC_PRE;
  222         if (ads->ds_rxstatus8 & AR_PostDelimCRCErr)
  223                 rs->rs_flags |= HAL_RX_DELIM_CRC_POST;
  224         if (ads->ds_rxstatus8 & AR_DecryptBusyErr)
  225                 rs->rs_flags |= HAL_RX_DECRYPT_BUSY;
  226         if (ads->ds_rxstatus8 & AR_HiRxChain)
  227                 rs->rs_flags |= HAL_RX_HI_RX_CHAIN;
  228 
  229         if ((ads->ds_rxstatus8 & AR_RxFrameOK) == 0) {
  230                 /*
  231                  * These four bits should not be set together.  The
  232                  * 5416 spec states a Michael error can only occur if
  233                  * DecryptCRCErr not set (and TKIP is used).  Experience
  234                  * indicates however that you can also get Michael errors
  235                  * when a CRC error is detected, but these are specious.
  236                  * Consequently we filter them out here so we don't
  237                  * confuse and/or complicate drivers.
  238                  */
  239 
  240                 /*
  241                  * The AR5416 sometimes sets both AR_CRCErr and AR_PHYErr
  242                  * when reporting radar pulses.  In this instance
  243                  * set HAL_RXERR_PHY as well as HAL_RXERR_CRC and
  244                  * let the driver layer figure out what to do.
  245                  *
  246                  * See PR kern/169362.
  247                  */
  248                 if (ads->ds_rxstatus8 & AR_PHYErr) {
  249                         u_int phyerr;
  250 
  251                         /*
  252                          * Packets with OFDM_RESTART on post delimiter are CRC OK and
  253                          * usable and MAC ACKs them.
  254                          * To avoid packet from being lost, we remove the PHY Err flag
  255                          * so that driver layer does not drop them.
  256                          */
  257                         phyerr = MS(ads->ds_rxstatus8, AR_PHYErrCode);
  258 
  259                         if ((phyerr == HAL_PHYERR_OFDM_RESTART) &&
  260                             (ads->ds_rxstatus8 & AR_PostDelimCRCErr)) {
  261                                 ath_hal_printf(ah,
  262                                     "%s: OFDM_RESTART on post-delim CRC error\n",
  263                                     __func__);
  264                                 rs->rs_phyerr = 0;
  265                         } else {
  266                                 rs->rs_status |= HAL_RXERR_PHY;
  267                                 rs->rs_phyerr = phyerr;
  268                         }
  269                 }
  270                 if (ads->ds_rxstatus8 & AR_CRCErr)
  271                         rs->rs_status |= HAL_RXERR_CRC;
  272                 else if (ads->ds_rxstatus8 & AR_DecryptCRCErr)
  273                         rs->rs_status |= HAL_RXERR_DECRYPT;
  274                 else if (ads->ds_rxstatus8 & AR_MichaelErr)
  275                         rs->rs_status |= HAL_RXERR_MIC;
  276         }
  277 
  278         if (ads->ds_rxstatus8 & AR_KeyMiss)
  279                 rs->rs_status |= HAL_RXERR_KEYMISS;
  280 
  281         return HAL_OK;
  282 }
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FreeBSD/Linux Kernel Cross Reference sys/dev/ath/ath_hal/ar5416/ar5416_recv.c

FreeBSD/Linux Kernel Cross Reference
sys/dev/ath/ath_hal/ar5416/ar5416_recv.c
