Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/ath/ath_hal/ar5416/ar5416reg.h
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1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD$ 20 */ 21 #ifndef _DEV_ATH_AR5416REG_H 22 #define _DEV_ATH_AR5416REG_H 23 24 #include <dev/ath/ath_hal/ar5212/ar5212reg.h> 25 26 /* 27 * Register added starting with the AR5416 28 */ 29 #define AR_MIRT 0x0020 /* interrupt rate threshold */ 30 #define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */ 31 #define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */ 32 #define AR_GTXTO 0x0064 /* global transmit timeout */ 33 #define AR_GTTM 0x0068 /* global transmit timeout mode */ 34 #define AR_CST 0x006C /* carrier sense timeout */ 35 #define AR_MAC_LED 0x1f04 /* LED control */ 36 #define AR_WA 0x4004 /* PCIE work-arounds */ 37 #define AR_PCIE_PM_CTRL 0x4014 38 #define AR_AHB_MODE 0x4024 /* AHB mode for dma */ 39 #define AR_INTR_SYNC_CAUSE_CLR 0x4028 /* clear interrupt */ 40 #define AR_INTR_SYNC_CAUSE 0x4028 /* check pending interrupts */ 41 #define AR_INTR_SYNC_ENABLE 0x402c /* enable interrupts */ 42 #define AR_INTR_ASYNC_MASK 0x4030 /* asynchronous interrupt mask */ 43 #define AR_INTR_SYNC_MASK 0x4034 /* synchronous interrupt mask */ 44 #define AR_INTR_ASYNC_CAUSE 0x4038 /* check pending interrupts */ 45 #define AR_INTR_ASYNC_CAUSE_CLR 0x4038 /* clear pending interrupts */ 46 #define AR_INTR_ASYNC_ENABLE 0x403c /* enable interrupts */ 47 #define AR5416_PCIE_SERDES 0x4040 48 #define AR5416_PCIE_SERDES2 0x4044 49 #define AR_GPIO_IN_OUT 0x4048 /* GPIO input/output register */ 50 #define AR_GPIO_OE_OUT 0x404c /* GPIO output enable register */ 51 #define AR_GPIO_INTR_POL 0x4050 /* GPIO interrupt polarity */ 52 53 #define AR_GPIO_INPUT_EN_VAL 0x4054 /* GPIO input enable and value */ 54 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 55 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2 56 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 57 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S 3 58 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010 59 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S 4 60 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 61 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7 62 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400 63 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S 10 64 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_BB 0x00000800 65 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_BB_S 11 66 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 67 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 12 68 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 69 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15 70 #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 71 #define AR_GPIO_JTAG_DISABLE 0x00020000 72 73 #define AR_GPIO_INPUT_MUX1 0x4058 74 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00 75 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8 76 #define AR_GPIO_INPUT_MUX1_BT_FREQUENCY 0x0000f000 77 #define AR_GPIO_INPUT_MUX1_BT_FREQUENCY_S 12 78 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000 79 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 80 81 #define AR_GPIO_INPUT_MUX2 0x405c 82 #define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f 83 #define AR_GPIO_INPUT_MUX2_CLK25_S 0 84 #define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0 85 #define AR_GPIO_INPUT_MUX2_RFSILENT_S 4 86 #define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00 87 #define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 88 89 #define AR_GPIO_OUTPUT_MUX1 0x4060 90 #define AR_GPIO_OUTPUT_MUX2 0x4064 91 #define AR_GPIO_OUTPUT_MUX3 0x4068 92 93 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 94 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 95 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 96 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 97 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 98 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 99 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 100 101 #define AR_EEPROM_STATUS_DATA 0x407c 102 #define AR_OBS 0x4080 103 #define AR_GPIO_PDPU 0x4088 104 105 #ifdef AH_SUPPORT_AR9130 106 #define AR_RTC_BASE 0x20000 107 #else 108 #define AR_RTC_BASE 0x7000 109 #endif /* AH_SUPPORT_AR9130 */ 110 111 #define AR_RTC_RC AR_RTC_BASE + 0x00 /* reset control */ 112 #define AR_RTC_PLL_CONTROL AR_RTC_BASE + 0x14 113 #define AR_RTC_RESET AR_RTC_BASE + 0x40 /* RTC reset register */ 114 #define AR_RTC_STATUS AR_RTC_BASE + 0x44 /* system sleep status */ 115 #define AR_RTC_SLEEP_CLK AR_RTC_BASE + 0x48 116 #define AR_RTC_FORCE_WAKE AR_RTC_BASE + 0x4c /* control MAC force wake */ 117 #define AR_RTC_INTR_CAUSE AR_RTC_BASE + 0x50 /* RTC interrupt cause/clear */ 118 #define AR_RTC_INTR_ENABLE AR_RTC_BASE + 0x54 /* RTC interrupt enable */ 119 #define AR_RTC_INTR_MASK AR_RTC_BASE + 0x58 /* RTC interrupt mask */ 120 121 #ifdef AH_SUPPORT_AR9130 122 /* RTC_DERIVED_* - only for AR9130 */ 123 #define AR_RTC_DERIVED_CLK (AR_RTC_BASE + 0x0038) 124 #define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe 125 #define AR_RTC_DERIVED_CLK_PERIOD_S 1 126 #endif /* AH_SUPPORT_AR9130 */ 127 128 /* AR_USEC: 0x801c */ 129 #define AR5416_USEC_TX_LAT 0x007FC000 /* tx latency to start of SIGNAL (usec) */ 130 #define AR5416_USEC_TX_LAT_S 14 /* tx latency to start of SIGNAL (usec) */ 131 #define AR5416_USEC_RX_LAT 0x1F800000 /* rx latency to start of SIGNAL (usec) */ 132 #define AR5416_USEC_RX_LAT_S 23 /* rx latency to start of SIGNAL (usec) */ 133 134 #define AR_RESET_TSF 0x8020 135 136 /* 137 * AR_SLEEP1 / AR_SLEEP2 are in the same place as in 138 * AR5212, however the fields have changed. 139 */ 140 #define AR5416_SLEEP1 0x80d4 141 #define AR5416_SLEEP2 0x80d8 142 #define AR_RXFIFO_CFG 0x8114 143 #define AR_PHY_ERR_1 0x812c 144 #define AR_PHY_ERR_MASK_1 0x8130 /* mask for AR_PHY_ERR_1 */ 145 #define AR_PHY_ERR_2 0x8134 146 #define AR_PHY_ERR_MASK_2 0x8138 /* mask for AR_PHY_ERR_2 */ 147 #define AR_TSFOOR_THRESHOLD 0x813c 148 #define AR_PHY_ERR_3 0x8168 149 #define AR_PHY_ERR_MASK_3 0x816c /* mask for AR_PHY_ERR_3 */ 150 #define AR_BT_COEX_WEIGHT2 0x81c4 151 #define AR_TXOP_X 0x81ec /* txop for legacy non-qos */ 152 #define AR_TXOP_0_3 0x81f0 /* txop for various tid's */ 153 #define AR_TXOP_4_7 0x81f4 154 #define AR_TXOP_8_11 0x81f8 155 #define AR_TXOP_12_15 0x81fc 156 /* generic timers based on tsf - all uS */ 157 #define AR_NEXT_TBTT 0x8200 158 #define AR_NEXT_DBA 0x8204 159 #define AR_NEXT_SWBA 0x8208 160 #define AR_NEXT_CFP 0x8208 161 #define AR_NEXT_HCF 0x820C 162 #define AR_NEXT_TIM 0x8210 163 #define AR_NEXT_DTIM 0x8214 164 #define AR_NEXT_QUIET 0x8218 165 #define AR_NEXT_NDP 0x821C 166 #define AR5416_BEACON_PERIOD 0x8220 167 #define AR_DBA_PERIOD 0x8224 168 #define AR_SWBA_PERIOD 0x8228 169 #define AR_HCF_PERIOD 0x822C 170 #define AR_TIM_PERIOD 0x8230 171 #define AR_DTIM_PERIOD 0x8234 172 #define AR_QUIET_PERIOD 0x8238 173 #define AR_NDP_PERIOD 0x823C 174 #define AR_TIMER_MODE 0x8240 175 #define AR_SLP32_MODE 0x8244 176 #define AR_SLP32_WAKE 0x8248 177 #define AR_SLP32_INC 0x824c 178 #define AR_SLP_CNT 0x8250 /* 32kHz cycles with mac asleep */ 179 #define AR_SLP_CYCLE_CNT 0x8254 /* absolute number of 32kHz cycles */ 180 #define AR_SLP_MIB_CTRL 0x8258 181 #define AR_2040_MODE 0x8318 182 #define AR_EXTRCCNT 0x8328 /* extension channel rx clear count */ 183 #define AR_SELFGEN_MASK 0x832c /* rx and cal chain masks */ 184 #define AR_PHY_ERR_MASK_REG 0x8338 185 #define AR_PCU_TXBUF_CTRL 0x8340 186 #define AR_PCU_MISC_MODE2 0x8344 187 188 /* DMA & PCI Registers in PCI space (usable during sleep)*/ 189 #define AR_RC_AHB 0x00000001 /* AHB reset */ 190 #define AR_RC_APB 0x00000002 /* APB reset */ 191 #define AR_RC_HOSTIF 0x00000100 /* host interface reset */ 192 193 #define AR_MIRT_VAL 0x0000ffff /* in uS */ 194 #define AR_MIRT_VAL_S 16 195 196 #define AR_TIMT_LAST 0x0000ffff /* Last packet threshold */ 197 #define AR_TIMT_LAST_S 0 198 #define AR_TIMT_FIRST 0xffff0000 /* First packet threshold */ 199 #define AR_TIMT_FIRST_S 16 200 201 #define AR_RIMT_LAST 0x0000ffff /* Last packet threshold */ 202 #define AR_RIMT_LAST_S 0 203 #define AR_RIMT_FIRST 0xffff0000 /* First packet threshold */ 204 #define AR_RIMT_FIRST_S 16 205 206 #define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 207 #define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 208 #define AR_GTXTO_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 209 210 #define AR_GTTM_USEC 0x00000001 // usec strobe 211 #define AR_GTTM_IGNORE_IDLE 0x00000002 // ignore channel idle 212 #define AR_GTTM_RESET_IDLE 0x00000004 // reset counter on channel idle low 213 #define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe 214 215 #define AR_CST_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 216 #define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 217 #define AR_CST_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 218 219 /* MAC tx DMA size config */ 220 #define AR_TXCFG_DMASZ_MASK 0x00000003 221 #define AR_TXCFG_DMASZ_4B 0 222 #define AR_TXCFG_DMASZ_8B 1 223 #define AR_TXCFG_DMASZ_16B 2 224 #define AR_TXCFG_DMASZ_32B 3 225 #define AR_TXCFG_DMASZ_64B 4 226 #define AR_TXCFG_DMASZ_128B 5 227 #define AR_TXCFG_DMASZ_256B 6 228 #define AR_TXCFG_DMASZ_512B 7 229 #define AR_TXCFG_ATIM_TXPOLICY 0x00000800 230 231 /* MAC rx DMA size config */ 232 #define AR_RXCFG_DMASZ_MASK 0x00000007 233 #define AR_RXCFG_DMASZ_4B 0 234 #define AR_RXCFG_DMASZ_8B 1 235 #define AR_RXCFG_DMASZ_16B 2 236 #define AR_RXCFG_DMASZ_32B 3 237 #define AR_RXCFG_DMASZ_64B 4 238 #define AR_RXCFG_DMASZ_128B 5 239 #define AR_RXCFG_DMASZ_256B 6 240 #define AR_RXCFG_DMASZ_512B 7 241 242 /* MAC Led registers */ 243 #define AR_CFG_SCLK_RATE_IND 0x00000003 /* sleep clock indication */ 244 #define AR_CFG_SCLK_RATE_IND_S 0 245 #define AR_CFG_SCLK_32MHZ 0x00000000 /* Sleep clock rate */ 246 #define AR_CFG_SCLK_4MHZ 0x00000001 /* Sleep clock rate */ 247 #define AR_CFG_SCLK_1MHZ 0x00000002 /* Sleep clock rate */ 248 #define AR_CFG_SCLK_32KHZ 0x00000003 /* Sleep clock rate */ 249 #define AR_MAC_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode */ 250 #define AR_MAC_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select */ 251 #define AR_MAC_LED_MODE 0x00000380 /* LED mode select */ 252 #define AR_MAC_LED_MODE_S 7 253 #define AR_MAC_LED_MODE_PROP 0 /* Blink prop to filtered tx/rx */ 254 #define AR_MAC_LED_MODE_RPROP 1 /* Blink prop to unfiltered tx/rx */ 255 #define AR_MAC_LED_MODE_SPLIT 2 /* Blink power for tx/net for rx */ 256 #define AR_MAC_LED_MODE_RAND 3 /* Blink randomly */ 257 #define AR_MAC_LED_MODE_POWON 5 /* Power LED on (s/w control) */ 258 #define AR_MAC_LED_MODE_NETON 6 /* Network LED on (s/w control) */ 259 #define AR_MAC_LED_ASSOC 0x00000c00 260 #define AR_MAC_LED_ASSOC_NONE 0x0 /* STA is not associated or trying */ 261 #define AR_MAC_LED_ASSOC_ACTIVE 0x1 /* STA is associated */ 262 #define AR_MAC_LED_ASSOC_PEND 0x2 /* STA is trying to associate */ 263 #define AR_MAC_LED_ASSOC_S 10 264 265 #define AR_WA_BIT6 0x00000040 266 #define AR_WA_BIT7 0x00000080 267 #define AR_WA_D3_L1_DISABLE 0x00004000 /* */ 268 #define AR_WA_UNTIE_RESET_EN 0x00008000 /* ena PCI reset to POR */ 269 #define AR_WA_RESET_EN 0x00040000 /* ena AR_WA_UNTIE_RESET_EN */ 270 #define AR_WA_ANALOG_SHIFT 0x00100000 271 #define AR_WA_POR_SHORT 0x00200000 /* PCIE phy reset control */ 272 #define AR_WA_BIT22 0x00400000 273 #define AR_WA_BIT23 0x00800000 274 275 #define AR_WA_DEFAULT 0x0000073f 276 #define AR9280_WA_DEFAULT 0x0040073b /* disable bit 2, see commit */ 277 #define AR9285_WA_DEFAULT 0x004a05cb 278 279 #define AR_PCIE_PM_CTRL_ENA 0x00080000 280 281 #define AR_AHB_EXACT_WR_EN 0x00000000 /* write exact bytes */ 282 #define AR_AHB_BUF_WR_EN 0x00000001 /* buffer write up to cacheline*/ 283 #define AR_AHB_EXACT_RD_EN 0x00000000 /* read exact bytes */ 284 #define AR_AHB_CACHELINE_RD_EN 0x00000002 /* read up to end of cacheline */ 285 #define AR_AHB_PREFETCH_RD_EN 0x00000004 /* prefetch up to page boundary*/ 286 #define AR_AHB_PAGE_SIZE_1K 0x00000000 /* set page-size as 1k */ 287 #define AR_AHB_PAGE_SIZE_2K 0x00000008 /* set page-size as 2k */ 288 #define AR_AHB_PAGE_SIZE_4K 0x00000010 /* set page-size as 4k */ 289 /* Kiwi */ 290 #define AR_AHB_CUSTOM_BURST_EN 0x000000C0 /* set Custom Burst Mode */ 291 #define AR_AHB_CUSTOM_BURST_EN_S 6 /* set Custom Burst Mode */ 292 #define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL 3 /* set both bits in Async FIFO mode */ 293 294 /* MAC PCU Registers */ 295 #define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 /* Don't replace seq num */ 296 297 /* Extended PCU DIAG_SW control fields */ 298 #define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 /* dual chain channel info */ 299 #define AR_DIAG_RX_ABORT 0x02000000 /* abort rx */ 300 #define AR_DIAG_SATURATE_CCNT 0x04000000 /* sat. cycle cnts (no shift) */ 301 #define AR_DIAG_OBS_PT_SEL2 0x08000000 /* observation point sel */ 302 #define AR_DIAG_RXCLEAR_CTL_LOW 0x10000000 /* force rx_clear(ctl) low/busy */ 303 #define AR_DIAG_RXCLEAR_EXT_LOW 0x20000000 /* force rx_clear(ext) low/busy */ 304 305 #define AR_TXOP_X_VAL 0x000000FF 306 307 #define AR_RESET_TSF_ONCE 0x01000000 /* reset tsf once; self-clears*/ 308 309 /* Interrupts */ 310 #define AR_ISR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 311 #define AR_ISR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 312 #define AR_ISR_GENTMR 0x10000000 /* OR of generic timer bits in S5 */ 313 #define AR_ISR_TXINTM 0x40000000 /* Tx int after mitigation */ 314 #define AR_ISR_RXINTM 0x80000000 /* Rx int after mitigation */ 315 316 #define AR_ISR_S2_CST 0x00400000 /* Carrier sense timeout */ 317 #define AR_ISR_S2_GTT 0x00800000 /* Global transmit timeout */ 318 #define AR_ISR_S2_TSFOOR 0x40000000 /* RX TSF out of range */ 319 320 #define AR_ISR_S5 0x0098 321 #define AR_ISR_S5_S 0x00d8 322 #define AR_ISR_S5_GENTIMER7 0x00000080 // Mask for timer 7 trigger 323 #define AR_ISR_S5_TIM_TIMER 0x00000010 // TIM Timer ISR 324 #define AR_ISR_S5_DTIM_TIMER 0x00000020 // DTIM Timer ISR 325 #define AR_ISR_S5_GENTIMER_TRIG 0x0000FF80 // ISR for generic timer trigger 7-15 326 #define AR_ISR_S5_GENTIMER_TRIG_S 0 327 #define AR_ISR_S5_GENTIMER_THRESH 0xFF800000 // ISR for generic timer threshold 7-15 328 #define AR_ISR_S5_GENTIMER_THRESH_S 16 329 330 #define AR_INTR_SPURIOUS 0xffffffff 331 #define AR_INTR_RTC_IRQ 0x00000001 /* rtc in shutdown state */ 332 #define AR_INTR_MAC_IRQ 0x00000002 /* pending mac interrupt */ 333 #define AR_INTR_EEP_PROT_ACCESS 0x00000004 /* eeprom protected access */ 334 #define AR_INTR_MAC_AWAKE 0x00020000 /* mac is awake */ 335 #define AR_INTR_MAC_ASLEEP 0x00040000 /* mac is asleep */ 336 337 /* Interrupt Mask Registers */ 338 #define AR_IMR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 339 #define AR_IMR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 340 #define AR_IMR_TXINTM 0x40000000 /* Tx int after mitigation */ 341 #define AR_IMR_RXINTM 0x80000000 /* Rx int after mitigation */ 342 343 #define AR_IMR_S2_CST 0x00400000 /* Carrier sense timeout */ 344 #define AR_IMR_S2_GTT 0x00800000 /* Global transmit timeout */ 345 346 /* synchronous interrupt signals */ 347 #define AR_INTR_SYNC_RTC_IRQ 0x00000001 348 #define AR_INTR_SYNC_MAC_IRQ 0x00000002 349 #define AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS 0x00000004 350 #define AR_INTR_SYNC_APB_TIMEOUT 0x00000008 351 #define AR_INTR_SYNC_PCI_MODE_CONFLICT 0x00000010 352 #define AR_INTR_SYNC_HOST1_FATAL 0x00000020 353 #define AR_INTR_SYNC_HOST1_PERR 0x00000040 354 #define AR_INTR_SYNC_TRCV_FIFO_PERR 0x00000080 355 #define AR_INTR_SYNC_RADM_CPL_EP 0x00000100 356 #define AR_INTR_SYNC_RADM_CPL_DLLP_ABORT 0x00000200 357 #define AR_INTR_SYNC_RADM_CPL_TLP_ABORT 0x00000400 358 #define AR_INTR_SYNC_RADM_CPL_ECRC_ERR 0x00000800 359 #define AR_INTR_SYNC_RADM_CPL_TIMEOUT 0x00001000 360 #define AR_INTR_SYNC_LOCAL_TIMEOUT 0x00002000 361 #define AR_INTR_SYNC_PM_ACCESS 0x00004000 362 #define AR_INTR_SYNC_MAC_AWAKE 0x00008000 363 #define AR_INTR_SYNC_MAC_ASLEEP 0x00010000 364 #define AR_INTR_SYNC_MAC_SLEEP_ACCESS 0x00020000 365 #define AR_INTR_SYNC_ALL 0x0003FFFF 366 367 /* default synchronous interrupt signals enabled */ 368 #define AR_INTR_SYNC_DEFAULT \ 369 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR | \ 370 AR_INTR_SYNC_RADM_CPL_EP | AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \ 371 AR_INTR_SYNC_RADM_CPL_TLP_ABORT | AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \ 372 AR_INTR_SYNC_RADM_CPL_TIMEOUT | AR_INTR_SYNC_LOCAL_TIMEOUT | \ 373 AR_INTR_SYNC_MAC_SLEEP_ACCESS) 374 375 #define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 376 #define AR_INTR_SYNC_MASK_GPIO_S 18 377 378 #define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 379 #define AR_INTR_SYNC_ENABLE_GPIO_S 18 380 381 #define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 /* async int mask */ 382 #define AR_INTR_ASYNC_MASK_GPIO_S 18 383 384 #define AR_INTR_ASYNC_CAUSE_GPIO 0xFFFC0000 /* GPIO interrupts */ 385 #define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | AR_INTR_ASYNC_CAUSE_GPIO) 386 387 #define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 /* enable interrupts */ 388 #define AR_INTR_ASYNC_ENABLE_GPIO_S 18 389 390 /* RTC registers */ 391 #define AR_RTC_RC_M 0x00000003 392 #define AR_RTC_RC_MAC_WARM 0x00000001 393 #define AR_RTC_RC_MAC_COLD 0x00000002 394 #ifdef AH_SUPPORT_AR9130 395 #define AR_RTC_RC_COLD_RESET 0x00000004 396 #define AR_RTC_RC_WARM_RESET 0x00000008 397 #endif /* AH_SUPPORT_AR9130 */ 398 #define AR_RTC_PLL_DIV 0x0000001f 399 #define AR_RTC_PLL_DIV_S 0 400 #define AR_RTC_PLL_DIV2 0x00000020 401 #define AR_RTC_PLL_REFDIV_5 0x000000c0 402 403 #define AR_RTC_SOWL_PLL_DIV 0x000003ff 404 #define AR_RTC_SOWL_PLL_DIV_S 0 405 #define AR_RTC_SOWL_PLL_REFDIV 0x00003C00 406 #define AR_RTC_SOWL_PLL_REFDIV_S 10 407 #define AR_RTC_SOWL_PLL_CLKSEL 0x0000C000 408 #define AR_RTC_SOWL_PLL_CLKSEL_S 14 409 410 #define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */ 411 412 #define AR_RTC_PM_STATUS_M 0x0000000f /* Pwr Mgmt Status */ 413 #ifdef AH_SUPPORT_AR9130 414 #define AR_RTC_STATUS_M 0x0000000f /* RTC Status */ 415 #else 416 #define AR_RTC_STATUS_M 0x0000003f /* RTC Status */ 417 #endif /* AH_SUPPORT_AR9130 */ 418 #define AR_RTC_STATUS_SHUTDOWN 0x00000001 419 #define AR_RTC_STATUS_ON 0x00000002 420 #define AR_RTC_STATUS_SLEEP 0x00000004 421 #define AR_RTC_STATUS_WAKEUP 0x00000008 422 #define AR_RTC_STATUS_COLDRESET 0x00000010 /* Not currently used */ 423 #define AR_RTC_STATUS_PLLCHANGE 0x00000020 /* Not currently used */ 424 425 #define AR_RTC_SLEEP_DERIVED_CLK 0x2 426 427 #define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ 428 #define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ 429 430 #define AR_RTC_PLL_CLKSEL 0x00000300 431 #define AR_RTC_PLL_CLKSEL_S 8 432 433 /* AR9280: rf long shift registers */ 434 #define AR_AN_RF2G1_CH0 0x7810 435 #define AR_AN_RF5G1_CH0 0x7818 436 #define AR_AN_RF2G1_CH1 0x7834 437 #define AR_AN_RF5G1_CH1 0x783C 438 #define AR_AN_TOP2 0x7894 439 #define AR_AN_SYNTH9 0x7868 440 441 #define AR_AN_RF2G1_CH0_OB 0x03800000 442 #define AR_AN_RF2G1_CH0_OB_S 23 443 #define AR_AN_RF2G1_CH0_DB 0x1C000000 444 #define AR_AN_RF2G1_CH0_DB_S 26 445 446 #define AR_AN_RF5G1_CH0_OB5 0x00070000 447 #define AR_AN_RF5G1_CH0_OB5_S 16 448 #define AR_AN_RF5G1_CH0_DB5 0x00380000 449 #define AR_AN_RF5G1_CH0_DB5_S 19 450 451 #define AR_AN_RF2G1_CH1_OB 0x03800000 452 #define AR_AN_RF2G1_CH1_OB_S 23 453 #define AR_AN_RF2G1_CH1_DB 0x1C000000 454 #define AR_AN_RF2G1_CH1_DB_S 26 455 456 #define AR_AN_RF5G1_CH1_OB5 0x00070000 457 #define AR_AN_RF5G1_CH1_OB5_S 16 458 #define AR_AN_RF5G1_CH1_DB5 0x00380000 459 #define AR_AN_RF5G1_CH1_DB5_S 19 460 461 #define AR_AN_TOP1 0x7890 462 #define AR_AN_TOP1_DACIPMODE 0x00040000 463 #define AR_AN_TOP1_DACIPMODE_S 18 464 465 #define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 466 #define AR_AN_TOP2_XPABIAS_LVL_S 30 467 #define AR_AN_TOP2_LOCALBIAS 0x00200000 468 #define AR_AN_TOP2_LOCALBIAS_S 21 469 #define AR_AN_TOP2_PWDCLKIND 0x00400000 470 #define AR_AN_TOP2_PWDCLKIND_S 22 471 472 #define AR_AN_SYNTH9_REFDIVA 0xf8000000 473 #define AR_AN_SYNTH9_REFDIVA_S 27 474 475 #define AR9271_AN_RF2G6_OFFS 0x07f00000 476 #define AR9271_AN_RF2G6_OFFS_S 20 477 478 /* Sleep control */ 479 #define AR5416_SLEEP1_ASSUME_DTIM 0x00080000 480 #define AR5416_SLEEP1_CAB_TIMEOUT 0xFFE00000 /* Cab timeout (TU) */ 481 #define AR5416_SLEEP1_CAB_TIMEOUT_S 21 482 483 #define AR5416_SLEEP2_BEACON_TIMEOUT 0xFFE00000 /* Beacon timeout (TU)*/ 484 #define AR5416_SLEEP2_BEACON_TIMEOUT_S 21 485 486 /* Sleep Registers */ 487 #define AR_SLP32_HALFCLK_LATENCY 0x000FFFFF /* rising <-> falling edge */ 488 #define AR_SLP32_ENA 0x00100000 489 #define AR_SLP32_TSF_WRITE_STATUS 0x00200000 /* tsf update in progress */ 490 491 #define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF /* time to wake crystal */ 492 493 #define AR_SLP32_TST_INC 0x000FFFFF 494 495 #define AR_SLP_MIB_CLEAR 0x00000001 /* clear pending */ 496 #define AR_SLP_MIB_PENDING 0x00000002 /* clear counters */ 497 498 #define AR_TIMER_MODE_TBTT 0x00000001 499 #define AR_TIMER_MODE_DBA 0x00000002 500 #define AR_TIMER_MODE_SWBA 0x00000004 501 #define AR_TIMER_MODE_HCF 0x00000008 502 #define AR_TIMER_MODE_TIM 0x00000010 503 #define AR_TIMER_MODE_DTIM 0x00000020 504 #define AR_TIMER_MODE_QUIET 0x00000040 505 #define AR_TIMER_MODE_NDP 0x00000080 506 #define AR_TIMER_MODE_OVERFLOW_INDEX 0x00000700 507 #define AR_TIMER_MODE_OVERFLOW_INDEX_S 8 508 #define AR_TIMER_MODE_THRESH 0xFFFFF000 509 #define AR_TIMER_MODE_THRESH_S 12 510 511 /* PCU Misc modes */ 512 #define AR_PCU_FORCE_BSSID_MATCH 0x00000001 /* force bssid to match */ 513 #define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 /* tx/rx mic keys together */ 514 #define AR_PCU_TX_ADD_TSF 0x00000008 /* add tx_tsf + int_tsf */ 515 #define AR_PCU_CCK_SIFS_MODE 0x00000010 /* assume 11b sifs */ 516 #define AR_PCU_RX_ANT_UPDT 0x00000800 /* KC_RX_ANT_UPDATE */ 517 #define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 /* enforce txop / tbtt */ 518 #define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 /* count bmiss's when sleeping */ 519 #define AR_PCU_BUG_12306_FIX_ENA 0x00020000 /* use rx_clear to count sifs */ 520 #define AR_PCU_FORCE_QUIET_COLL 0x00040000 /* kill xmit for channel change */ 521 #define AR_PCU_BT_ANT_PREVENT_RX 0x00100000 522 #define AR_PCU_BT_ANT_PREVENT_RX_S 20 523 #define AR_PCU_TBTT_PROTECT 0x00200000 /* no xmit up to tbtt+20 uS */ 524 #define AR_PCU_CLEAR_VMF 0x01000000 /* clear vmf mode (fast cc)*/ 525 #define AR_PCU_CLEAR_BA_VALID 0x04000000 /* clear ba state */ 526 #define AR_PCU_SEL_EVM 0x08000000 /* select EVM data or PLCP header */ 527 528 #define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 529 #define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 530 /* 531 * This bit enables the Multicast search based on both MAC Address and Key ID. 532 * If bit is 0, then Multicast search is based on MAC address only. 533 * For Merlin and above only. 534 */ 535 #define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE 0x00000040 536 #define AR_PCU_MISC_MODE2_ENABLE_AGGWEP 0x00020000 /* Kiwi or later? */ 537 #define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 538 #define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 539 540 /* For Kiwi */ 541 #define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358 542 #define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400 543 #define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000 544 545 /* TSF2. For Kiwi only */ 546 #define AR_TSF2_L32 0x8390 547 #define AR_TSF2_U32 0x8394 548 549 /* MAC Direct Connect Control. For Kiwi only */ 550 #define AR_DIRECT_CONNECT 0x83A0 551 #define AR_DC_AP_STA_EN 0x00000001 552 553 /* GPIO Interrupt */ 554 #define AR_INTR_GPIO 0x3FF00000 /* gpio interrupted */ 555 #define AR_INTR_GPIO_S 20 556 557 #define AR_GPIO_OUT_CTRL 0x000003FF /* 0 = out, 1 = in */ 558 #define AR_GPIO_OUT_VAL 0x000FFC00 559 #define AR_GPIO_OUT_VAL_S 10 560 #define AR_GPIO_INTR_CTRL 0x3FF00000 561 #define AR_GPIO_INTR_CTRL_S 20 562 563 #define AR_GPIO_IN_VAL 0x0FFFC000 /* pre-9280 */ 564 #define AR_GPIO_IN_VAL_S 14 565 #define AR928X_GPIO_IN_VAL 0x000FFC00 566 #define AR928X_GPIO_IN_VAL_S 10 567 #define AR9285_GPIO_IN_VAL 0x00FFF000 568 #define AR9285_GPIO_IN_VAL_S 12 569 #define AR9287_GPIO_IN_VAL 0x003FF800 570 #define AR9287_GPIO_IN_VAL_S 11 571 572 #define AR_GPIO_OE_OUT_DRV 0x3 /* 2 bit mask shifted by 2*bitpos */ 573 #define AR_GPIO_OE_OUT_DRV_NO 0x0 /* tristate */ 574 #define AR_GPIO_OE_OUT_DRV_LOW 0x1 /* drive if low */ 575 #define AR_GPIO_OE_OUT_DRV_HI 0x2 /* drive if high */ 576 #define AR_GPIO_OE_OUT_DRV_ALL 0x3 /* drive always */ 577 578 #define AR_GPIO_INTR_POL_VAL 0x1FFF 579 #define AR_GPIO_INTR_POL_VAL_S 0 580 581 #define AR_GPIO_JTAG_DISABLE 0x00020000 582 583 #define AR_2040_JOINED_RX_CLEAR 0x00000001 /* use ctl + ext rx_clear for cca */ 584 585 #define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF 586 #define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 587 #define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380 588 589 /* IFS, SIFS, slot, etc for Async FIFO mode (Kiwi) */ 590 #define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR 0x000003AB 591 #define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR 0x16001D56 592 #define AR_USEC_ASYNC_FIFO_DUR 0x12e00074 593 #define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR 0x00000420 594 #define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR 0x0000A5EB 595 596 /* Used by Kiwi Async FIFO */ 597 #define AR_MAC_PCU_LOGIC_ANALYZER 0x8264 598 #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000 599 600 /* Eeprom defines */ 601 #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff 602 #define AR_EEPROM_STATUS_DATA_VAL_S 0 603 #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 604 #define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 605 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 606 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 607 608 /* K2 (9271) */ 609 #define AR9271_CLOCK_CONTROL 0x50040 610 #define AR9271_CLOCK_SELECTION_22 0x0 611 #define AR9271_CLOCK_SELECTION_88 0x1 612 #define AR9271_CLOCK_SELECTION_44 0x2 613 #define AR9271_CLOCK_SELECTION_117 0x4 614 #define AR9271_CLOCK_SELECTION_OSC_40 0x6 615 #define AR9271_CLOCK_SELECTION_RTC 0x7 616 #define AR9271_SPI_SEL 0x100 617 #define AR9271_UART_SEL 0x200 618 619 #define AR9271_RESET_POWER_DOWN_CONTROL 0x50044 620 #define AR9271_RADIO_RF_RST 0x20 621 #define AR9271_GATE_MAC_CTL 0x4000 622 #define AR9271_MAIN_PLL_PWD_CTL 0x40000 623 624 #define AR9271_CLKMISC 0x4090 625 #define AR9271_OSC_to_10M_EN 0x00000001 626 627 /* 628 * AR5212 defines the MAC revision mask as 0xF, but both ath9k and 629 * the Atheros HAL define it as 0x7. 630 * 631 * What this means however is AR5416 silicon revisions have 632 * changed. The below macros are for what is contained in the 633 * lower four bits; if the lower three bits are taken into account 634 * the revisions become 1.0 => 0x0, 2.0 => 0x1, 2.2 => 0x2. 635 */ 636 637 /* These are the legacy revisions, with a four bit AR_SREV_REVISION mask */ 638 #define AR_SREV_REVISION_OWL_10 0x08 639 #define AR_SREV_REVISION_OWL_20 0x09 640 #define AR_SREV_REVISION_OWL_22 0x0a 641 642 #define AR_RAD5133_SREV_MAJOR 0xc0 /* Fowl: 2+5G/3x3 */ 643 #define AR_RAD2133_SREV_MAJOR 0xd0 /* Fowl: 2G/3x3 */ 644 #define AR_RAD5122_SREV_MAJOR 0xe0 /* Fowl: 5G/2x2 */ 645 #define AR_RAD2122_SREV_MAJOR 0xf0 /* Fowl: 2+5G/2x2 */ 646 647 /* Test macro for owl 1.0 */ 648 #define IS_5416V1(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_OWL_10) 649 #define IS_5416V2(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_20) 650 #define IS_5416V2_2(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_OWL_22) 651 652 /* Misc; compatibility with Atheros HAL */ 653 #define AR_SREV_5416_V20_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_20_OR_LATER(_ah)) 654 #define AR_SREV_5416_V22_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_22_OR_LATER(_ah)) 655 656 /* Expanded Mac Silicon Rev (16 bits starting with Sowl) */ 657 #define AR_XSREV_ID 0xFFFFFFFF /* Chip ID */ 658 #define AR_XSREV_ID_S 0 659 #define AR_XSREV_VERSION 0xFFFC0000 /* Chip version */ 660 #define AR_XSREV_VERSION_S 18 661 #define AR_XSREV_TYPE 0x0003F000 /* Chip type */ 662 #define AR_XSREV_TYPE_S 12 663 #define AR_XSREV_TYPE_CHAIN 0x00001000 /* Chain Mode (1:3 chains, 664 * 0:2 chains) */ 665 #define AR_XSREV_TYPE_HOST_MODE 0x00002000 /* Host Mode (1:PCI, 0:PCIe) */ 666 #define AR_XSREV_REVISION 0x00000F00 667 #define AR_XSREV_REVISION_S 8 668 669 #define AR_XSREV_VERSION_OWL_PCI 0x0D 670 #define AR_XSREV_VERSION_OWL_PCIE 0x0C 671 672 /* 673 * These are from ath9k/Atheros and assume an AR_SREV version mask 674 * of 0x07, rather than 0x0F which is being used in the FreeBSD HAL. 675 * Thus, don't use these values as they're incorrect here; use 676 * AR_SREV_REVISION_OWL_{10,20,22}. 677 */ 678 #if 0 679 #define AR_XSREV_REVISION_OWL_10 0 /* Owl 1.0 */ 680 #define AR_XSREV_REVISION_OWL_20 1 /* Owl 2.0/2.1 */ 681 #define AR_XSREV_REVISION_OWL_22 2 /* Owl 2.2 */ 682 #endif 683 684 #define AR_XSREV_VERSION_HOWL 0x14 /* Howl (AR9130) */ 685 #define AR_XSREV_VERSION_SOWL 0x40 /* Sowl (AR9160) */ 686 #define AR_XSREV_REVISION_SOWL_10 0 /* Sowl 1.0 */ 687 #define AR_XSREV_REVISION_SOWL_11 1 /* Sowl 1.1 */ 688 #define AR_XSREV_VERSION_MERLIN 0x80 /* Merlin Version */ 689 #define AR_XSREV_REVISION_MERLIN_10 0 /* Merlin 1.0 */ 690 #define AR_XSREV_REVISION_MERLIN_20 1 /* Merlin 2.0 */ 691 #define AR_XSREV_REVISION_MERLIN_21 2 /* Merlin 2.1 */ 692 #define AR_XSREV_VERSION_KITE 0xC0 /* Kite Version */ 693 #define AR_XSREV_REVISION_KITE_10 0 /* Kite 1.0 */ 694 #define AR_XSREV_REVISION_KITE_11 1 /* Kite 1.1 */ 695 #define AR_XSREV_REVISION_KITE_12 2 /* Kite 1.2 */ 696 #define AR_XSREV_VERSION_KIWI 0x180 /* Kiwi (AR9287) */ 697 #define AR_XSREV_REVISION_KIWI_10 0 /* Kiwi 1.0 */ 698 #define AR_XSREV_REVISION_KIWI_11 1 /* Kiwi 1.1 */ 699 #define AR_XSREV_REVISION_KIWI_12 2 /* Kiwi 1.2 */ 700 #define AR_XSREV_REVISION_KIWI_13 3 /* Kiwi 1.3 */ 701 702 /* Owl (AR5416) */ 703 #define AR_SREV_OWL(_ah) \ 704 ((AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_OWL_PCI) || \ 705 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_OWL_PCIE)) 706 707 #define AR_SREV_OWL_20_OR_LATER(_ah) \ 708 ((AR_SREV_OWL(_ah) && \ 709 AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_20) || \ 710 AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_HOWL) 711 712 #define AR_SREV_OWL_22_OR_LATER(_ah) \ 713 ((AR_SREV_OWL(_ah) && \ 714 AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_22) || \ 715 AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_HOWL) 716 717 /* Howl (AR9130) */ 718 719 #define AR_SREV_HOWL(_ah) \ 720 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_HOWL) 721 722 #define AR_SREV_9100(_ah) AR_SREV_HOWL(_ah) 723 724 /* Sowl (AR9160) */ 725 726 #define AR_SREV_SOWL(_ah) \ 727 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_SOWL) 728 729 #define AR_SREV_SOWL_10_OR_LATER(_ah) \ 730 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL) 731 732 #define AR_SREV_SOWL_11(_ah) \ 733 (AR_SREV_SOWL(_ah) && \ 734 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_SOWL_11) 735 736 /* Merlin (AR9280) */ 737 738 #define AR_SREV_MERLIN(_ah) \ 739 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_MERLIN) 740 741 #define AR_SREV_MERLIN_10_OR_LATER(_ah) \ 742 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN) 743 744 #define AR_SREV_MERLIN_20(_ah) \ 745 (AR_SREV_MERLIN(_ah) && \ 746 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20) 747 748 #define AR_SREV_MERLIN_20_OR_LATER(_ah) \ 749 ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_MERLIN) || \ 750 (AR_SREV_MERLIN((_ah)) && \ 751 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20)) 752 753 /* Kite (AR9285) */ 754 755 #define AR_SREV_KITE(_ah) \ 756 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KITE) 757 758 #define AR_SREV_KITE_10_OR_LATER(_ah) \ 759 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KITE) 760 761 #define AR_SREV_KITE_11(_ah) \ 762 (AR_SREV_KITE(ah) && \ 763 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_11) 764 765 #define AR_SREV_KITE_11_OR_LATER(_ah) \ 766 ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_KITE) || \ 767 (AR_SREV_KITE((_ah)) && \ 768 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_11)) 769 770 #define AR_SREV_KITE_12(_ah) \ 771 (AR_SREV_KITE(ah) && \ 772 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_12) 773 774 #define AR_SREV_KITE_12_OR_LATER(_ah) \ 775 ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_KITE) || \ 776 (AR_SREV_KITE((_ah)) && \ 777 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_12)) 778 779 #define AR_SREV_9285E_20(_ah) \ 780 (AR_SREV_KITE_12_OR_LATER(_ah) && \ 781 ((OS_REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1)) 782 783 #define AR_SREV_KIWI(_ah) \ 784 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KIWI) 785 786 #define AR_SREV_KIWI_10_OR_LATER(_ah) \ 787 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KIWI) 788 789 /* XXX TODO: make these handle macVersion > Kiwi */ 790 #define AR_SREV_KIWI_11_OR_LATER(_ah) \ 791 (AR_SREV_KIWI(_ah) && \ 792 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KIWI_11) 793 794 #define AR_SREV_KIWI_11(_ah) \ 795 (AR_SREV_KIWI(_ah) && \ 796 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KIWI_11) 797 798 #define AR_SREV_KIWI_12(_ah) \ 799 (AR_SREV_KIWI(_ah) && \ 800 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KIWI_12) 801 802 #define AR_SREV_KIWI_12_OR_LATER(_ah) \ 803 (AR_SREV_KIWI(_ah) && \ 804 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KIWI_12) 805 806 #define AR_SREV_KIWI_13_OR_LATER(_ah) \ 807 (AR_SREV_KIWI(_ah) && \ 808 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KIWI_13) 809 810 /* Not yet implemented chips */ 811 #define AR_SREV_9271(_ah) 0 812 813 #endif /* _DEV_ATH_AR5416REG_H */
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