Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/ath/ath_hal/ar9002/ar9287_attach.c
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1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD$ 20 */ 21 #include "opt_ah.h" 22 23 #include "ah.h" 24 #include "ah_internal.h" 25 #include "ah_devid.h" 26 27 #include "ah_eeprom_v14.h" /* XXX for tx/rx gain */ 28 #include "ah_eeprom_9287.h" 29 30 #include "ar9002/ar9280.h" 31 #include "ar9002/ar9287.h" 32 #include "ar5416/ar5416reg.h" 33 #include "ar5416/ar5416phy.h" 34 35 #include "ar9002/ar9287_cal.h" 36 #include "ar9002/ar9287_reset.h" 37 #include "ar9002/ar9287_olc.h" 38 39 #include "ar9002/ar9287.ini" 40 41 static const HAL_PERCAL_DATA ar9287_iq_cal = { /* single sample */ 42 .calName = "IQ", .calType = IQ_MISMATCH_CAL, 43 .calNumSamples = MIN_CAL_SAMPLES, 44 .calCountMax = PER_MAX_LOG_COUNT, 45 .calCollect = ar5416IQCalCollect, 46 .calPostProc = ar5416IQCalibration 47 }; 48 static const HAL_PERCAL_DATA ar9287_adc_gain_cal = { /* single sample */ 49 .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 50 .calNumSamples = MIN_CAL_SAMPLES, 51 .calCountMax = PER_MIN_LOG_COUNT, 52 .calCollect = ar5416AdcGainCalCollect, 53 .calPostProc = ar5416AdcGainCalibration 54 }; 55 static const HAL_PERCAL_DATA ar9287_adc_dc_cal = { /* single sample */ 56 .calName = "ADC DC", .calType = ADC_DC_CAL, 57 .calNumSamples = MIN_CAL_SAMPLES, 58 .calCountMax = PER_MIN_LOG_COUNT, 59 .calCollect = ar5416AdcDcCalCollect, 60 .calPostProc = ar5416AdcDcCalibration 61 }; 62 static const HAL_PERCAL_DATA ar9287_adc_init_dc_cal = { 63 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 64 .calNumSamples = MIN_CAL_SAMPLES, 65 .calCountMax = INIT_LOG_COUNT, 66 .calCollect = ar5416AdcDcCalCollect, 67 .calPostProc = ar5416AdcDcCalibration 68 }; 69 70 static void ar9287ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 71 HAL_BOOL power_off); 72 static void ar9287DisablePCIE(struct ath_hal *ah); 73 static HAL_BOOL ar9287FillCapabilityInfo(struct ath_hal *ah); 74 static void ar9287WriteIni(struct ath_hal *ah, 75 const struct ieee80211_channel *chan); 76 77 static void 78 ar9287AniSetup(struct ath_hal *ah) 79 { 80 /* 81 * These are the parameters from the AR5416 ANI code; 82 * they likely need quite a bit of adjustment for the 83 * AR9287. 84 */ 85 static const struct ar5212AniParams aniparams = { 86 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 87 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 88 .coarseHigh = { -14, -14, -14, -14, -12 }, 89 .coarseLow = { -64, -64, -64, -64, -70 }, 90 .firpwr = { -78, -78, -78, -78, -80 }, 91 .maxSpurImmunityLevel = 7, 92 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 93 .maxFirstepLevel = 2, /* levels 0..2 */ 94 .firstep = { 0, 4, 8 }, 95 .ofdmTrigHigh = 500, 96 .ofdmTrigLow = 200, 97 .cckTrigHigh = 200, 98 .cckTrigLow = 100, 99 .rssiThrHigh = 40, 100 .rssiThrLow = 7, 101 .period = 100, 102 }; 103 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 104 AH5416(ah)->ah_ani_function &= ~ HAL_ANI_NOISE_IMMUNITY_LEVEL; 105 106 /* NB: ANI is not enabled yet */ 107 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 108 } 109 110 /* 111 * Attach for an AR9287 part. 112 */ 113 static struct ath_hal * 114 ar9287Attach(uint16_t devid, HAL_SOFTC sc, 115 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 116 HAL_OPS_CONFIG *ah_config, 117 HAL_STATUS *status) 118 { 119 struct ath_hal_9287 *ahp9287; 120 struct ath_hal_5212 *ahp; 121 struct ath_hal *ah; 122 uint32_t val; 123 HAL_STATUS ecode; 124 HAL_BOOL rfStatus; 125 int8_t pwr_table_offset; 126 127 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 128 __func__, sc, (void*) st, (void*) sh); 129 130 /* NB: memory is returned zero'd */ 131 ahp9287 = ath_hal_malloc(sizeof (struct ath_hal_9287)); 132 if (ahp9287 == AH_NULL) { 133 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 134 "%s: cannot allocate memory for state block\n", __func__); 135 *status = HAL_ENOMEM; 136 return AH_NULL; 137 } 138 ahp = AH5212(ahp9287); 139 ah = &ahp->ah_priv.h; 140 141 ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 142 143 if (eepromdata != AH_NULL) { 144 AH_PRIVATE(ah)->ah_eepromRead = ath_hal_EepromDataRead; 145 AH_PRIVATE(ah)->ah_eepromWrite = NULL; 146 ah->ah_eepromdata = eepromdata; 147 } 148 149 /* XXX override with 9280 specific state */ 150 /* override 5416 methods for our needs */ 151 AH5416(ah)->ah_initPLL = ar9280InitPLL; 152 153 ah->ah_setAntennaSwitch = ar9287SetAntennaSwitch; 154 ah->ah_configPCIE = ar9287ConfigPCIE; 155 ah->ah_disablePCIE = ar9287DisablePCIE; 156 157 AH5416(ah)->ah_cal.iqCalData.calData = &ar9287_iq_cal; 158 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9287_adc_gain_cal; 159 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9287_adc_dc_cal; 160 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9287_adc_init_dc_cal; 161 /* Better performance without ADC Gain Calibration */ 162 AH5416(ah)->ah_cal.suppCals = ADC_DC_CAL | IQ_MISMATCH_CAL; 163 164 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 165 AH5416(ah)->ah_writeIni = ar9287WriteIni; 166 167 ah->ah_setTxPower = ar9287SetTransmitPower; 168 ah->ah_setBoardValues = ar9287SetBoardValues; 169 170 AH5416(ah)->ah_olcInit = ar9287olcInit; 171 AH5416(ah)->ah_olcTempCompensation = ar9287olcTemperatureCompensation; 172 //AH5416(ah)->ah_setPowerCalTable = ar9287SetPowerCalTable; 173 AH5416(ah)->ah_cal_initcal = ar9287InitCalHardware; 174 AH5416(ah)->ah_cal_pacal = ar9287PACal; 175 176 /* XXX NF calibration */ 177 /* XXX Ini override? (IFS vars - since the kiwi mac clock is faster?) */ 178 /* XXX what else is kiwi-specific in the radio/calibration pathway? */ 179 180 AH5416(ah)->ah_rx_chainmask = AR9287_DEFAULT_RXCHAINMASK; 181 AH5416(ah)->ah_tx_chainmask = AR9287_DEFAULT_TXCHAINMASK; 182 183 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 184 /* reset chip */ 185 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 186 __func__); 187 ecode = HAL_EIO; 188 goto bad; 189 } 190 191 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 192 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 193 __func__); 194 ecode = HAL_EIO; 195 goto bad; 196 } 197 /* Read Revisions from Chips before taking out of reset */ 198 val = OS_REG_READ(ah, AR_SREV); 199 HALDEBUG(ah, HAL_DEBUG_ATTACH, 200 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 201 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 202 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 203 /* NB: include chip type to differentiate from pre-Sowl versions */ 204 AH_PRIVATE(ah)->ah_macVersion = 205 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 206 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 207 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 208 209 /* Don't support Kiwi < 1.2; those are pre-release chips */ 210 if (! AR_SREV_KIWI_12_OR_LATER(ah)) { 211 ath_hal_printf(ah, "[ath]: Kiwi < 1.2 is not supported\n"); 212 ecode = HAL_EIO; 213 goto bad; 214 } 215 216 /* setup common ini data; rf backends handle remainder */ 217 HAL_INI_INIT(&ahp->ah_ini_modes, ar9287Modes_9287_1_1, 6); 218 HAL_INI_INIT(&ahp->ah_ini_common, ar9287Common_9287_1_1, 2); 219 220 /* If pcie_clock_req */ 221 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 222 ar9287PciePhy_clkreq_always_on_L1_9287_1_1, 2); 223 224 /* XXX WoW ini values */ 225 226 /* Else */ 227 #if 0 228 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 229 ar9287PciePhy_clkreq_off_L1_9287_1_1, 2); 230 #endif 231 232 /* Initialise Japan arrays */ 233 HAL_INI_INIT(&ahp9287->ah_ini_cckFirNormal, 234 ar9287Common_normal_cck_fir_coeff_9287_1_1, 2); 235 HAL_INI_INIT(&ahp9287->ah_ini_cckFirJapan2484, 236 ar9287Common_japan_2484_cck_fir_coeff_9287_1_1, 2); 237 238 ar5416AttachPCIE(ah); 239 240 ecode = ath_hal_9287EepromAttach(ah); 241 if (ecode != HAL_OK) 242 goto bad; 243 244 if (!ar5416ChipReset(ah, AH_NULL, HAL_RESET_NORMAL)) { /* reset chip */ 245 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 246 ecode = HAL_EIO; 247 goto bad; 248 } 249 250 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 251 252 if (!ar5212ChipTest(ah)) { 253 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 254 __func__); 255 ecode = HAL_ESELFTEST; 256 goto bad; 257 } 258 259 /* 260 * Set correct Baseband to analog shift 261 * setting to access analog chips. 262 */ 263 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 264 265 /* Read Radio Chip Rev Extract */ 266 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 267 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 268 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 269 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 270 break; 271 default: 272 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 273 AH_PRIVATE(ah)->ah_analog5GhzRev = 274 AR_RAD5133_SREV_MAJOR; 275 break; 276 } 277 #ifdef AH_DEBUG 278 HALDEBUG(ah, HAL_DEBUG_ANY, 279 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 280 "this driver\n", __func__, 281 AH_PRIVATE(ah)->ah_analog5GhzRev); 282 ecode = HAL_ENOTSUPP; 283 goto bad; 284 #endif 285 } 286 rfStatus = ar9287RfAttach(ah, &ecode); 287 if (!rfStatus) { 288 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 289 __func__, ecode); 290 goto bad; 291 } 292 293 /* 294 * We only implement open-loop TX power control 295 * for the AR9287 in this codebase. 296 */ 297 if (! ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) { 298 ath_hal_printf(ah, "[ath] AR9287 w/ closed-loop TX power control" 299 " isn't supported.\n"); 300 ecode = HAL_ENOTSUPP; 301 goto bad; 302 } 303 304 /* 305 * Check whether the power table offset isn't the default. 306 * This can occur with eeprom minor V21 or greater on Merlin. 307 */ 308 (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset); 309 if (pwr_table_offset != AR5416_PWR_TABLE_OFFSET_DB) 310 ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n", 311 AR5416_PWR_TABLE_OFFSET_DB, (int) pwr_table_offset); 312 313 /* setup rxgain table */ 314 HAL_INI_INIT(&ahp9287->ah_ini_rxgain, ar9287Modes_rx_gain_9287_1_1, 6); 315 316 /* setup txgain table */ 317 HAL_INI_INIT(&ahp9287->ah_ini_txgain, ar9287Modes_tx_gain_9287_1_1, 6); 318 319 /* 320 * Got everything we need now to setup the capabilities. 321 */ 322 if (!ar9287FillCapabilityInfo(ah)) { 323 ecode = HAL_EEREAD; 324 goto bad; 325 } 326 327 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 328 if (ecode != HAL_OK) { 329 HALDEBUG(ah, HAL_DEBUG_ANY, 330 "%s: error getting mac address from EEPROM\n", __func__); 331 goto bad; 332 } 333 /* XXX How about the serial number ? */ 334 /* Read Reg Domain */ 335 AH_PRIVATE(ah)->ah_currentRD = 336 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 337 AH_PRIVATE(ah)->ah_currentRDext = AR9287_RDEXT_DEFAULT; 338 339 /* 340 * ah_miscMode is populated by ar5416FillCapabilityInfo() 341 * starting from griffin. Set here to make sure that 342 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 343 * placed into hardware. 344 */ 345 if (ahp->ah_miscMode != 0) 346 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 347 348 ar9287AniSetup(ah); /* Anti Noise Immunity */ 349 350 /* Setup noise floor min/max/nominal values */ 351 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ; 352 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ; 353 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ; 354 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_5GHZ; 355 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_5GHZ; 356 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9287_5GHZ; 357 358 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 359 360 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 361 362 return ah; 363 bad: 364 if (ah != AH_NULL) 365 ah->ah_detach(ah); 366 if (status) 367 *status = ecode; 368 return AH_NULL; 369 } 370 371 static void 372 ar9287ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 373 { 374 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 375 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 376 OS_DELAY(1000); 377 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 378 /* Yes, Kiwi uses the Kite PCIe PHY WA */ 379 OS_REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT); 380 } 381 } 382 383 static void 384 ar9287DisablePCIE(struct ath_hal *ah) 385 { 386 /* XXX TODO */ 387 } 388 389 static void 390 ar9287WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 391 { 392 u_int modesIndex, freqIndex; 393 int regWrites = 0; 394 395 /* Setup the indices for the next set of register array writes */ 396 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 397 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 398 freqIndex = 2; 399 if (IEEE80211_IS_CHAN_HT40(chan)) 400 modesIndex = 3; 401 else if (IEEE80211_IS_CHAN_108G(chan)) 402 modesIndex = 5; 403 else 404 modesIndex = 4; 405 } else { 406 freqIndex = 1; 407 if (IEEE80211_IS_CHAN_HT40(chan) || 408 IEEE80211_IS_CHAN_TURBO(chan)) 409 modesIndex = 2; 410 else 411 modesIndex = 1; 412 } 413 414 /* Set correct Baseband to analog shift setting to access analog chips. */ 415 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 416 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 417 418 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, modesIndex, regWrites); 419 regWrites = ath_hal_ini_write(ah, &AH9287(ah)->ah_ini_rxgain, modesIndex, regWrites); 420 regWrites = ath_hal_ini_write(ah, &AH9287(ah)->ah_ini_txgain, modesIndex, regWrites); 421 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 1, regWrites); 422 } 423 424 /* 425 * Fill all software cached or static hardware state information. 426 * Return failure if capabilities are to come from EEPROM and 427 * cannot be read. 428 */ 429 static HAL_BOOL 430 ar9287FillCapabilityInfo(struct ath_hal *ah) 431 { 432 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 433 434 if (!ar5416FillCapabilityInfo(ah)) 435 return AH_FALSE; 436 pCap->halNumGpioPins = 10; 437 pCap->halWowSupport = AH_TRUE; 438 pCap->halWowMatchPatternExact = AH_TRUE; 439 #if 0 440 pCap->halWowMatchPatternDword = AH_TRUE; 441 #endif 442 443 pCap->halCSTSupport = AH_TRUE; 444 pCap->halRifsRxSupport = AH_TRUE; 445 pCap->halRifsTxSupport = AH_TRUE; 446 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 447 pCap->halExtChanDfsSupport = AH_TRUE; 448 pCap->halUseCombinedRadarRssi = AH_TRUE; 449 #if 0 450 /* XXX bluetooth */ 451 pCap->halBtCoexSupport = AH_TRUE; 452 #endif 453 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 454 pCap->hal4kbSplitTransSupport = AH_FALSE; 455 /* Disable this so Block-ACK works correctly */ 456 pCap->halHasRxSelfLinkedTail = AH_FALSE; 457 pCap->halPSPollBroken = AH_FALSE; 458 pCap->halSpectralScanSupport = AH_TRUE; 459 460 /* Hardware supports (at least) single-stream STBC TX/RX */ 461 pCap->halRxStbcSupport = 1; 462 pCap->halTxStbcSupport = 1; 463 464 /* Hardware supports short-GI w/ 20MHz */ 465 pCap->halHTSGI20Support = 1; 466 467 pCap->halEnhancedDfsSupport = AH_TRUE; 468 469 return AH_TRUE; 470 } 471 472 /* 473 * This has been disabled - having the HAL flip chainmasks on/off 474 * when attempting to implement 11n disrupts things. For now, just 475 * leave this flipped off and worry about implementing TX diversity 476 * for legacy and MCS0-15 when 11n is fully functioning. 477 */ 478 HAL_BOOL 479 ar9287SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 480 { 481 return AH_TRUE; 482 } 483 484 static const char* 485 ar9287Probe(uint16_t vendorid, uint16_t devid) 486 { 487 if (vendorid == ATHEROS_VENDOR_ID) { 488 if (devid == AR9287_DEVID_PCI) 489 return "Atheros 9227"; 490 if (devid == AR9287_DEVID_PCIE) 491 return "Atheros 9287"; 492 } 493 return AH_NULL; 494 } 495 AH_CHIP(AR9287, ar9287Probe, ar9287Attach);
Cache object: 1b6ea9cf88167df767e9cc42378cdace
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