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sys/dev/ath/if_ath_rx.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 18 * NO WARRANTY 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGES. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 /* 36 * Driver for the Atheros Wireless LAN controller. 37 * 38 * This software is derived from work of Atsushi Onoe; his contribution 39 * is greatly appreciated. 40 */ 41 42 #include "opt_inet.h" 43 #include "opt_ath.h" 44 /* 45 * This is needed for register operations which are performed 46 * by the driver - eg, calls to ath_hal_gettsf32(). 47 * 48 * It's also required for any AH_DEBUG checks in here, eg the 49 * module dependencies. 50 */ 51 #include "opt_ah.h" 52 #include "opt_wlan.h" 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/sysctl.h> 57 #include <sys/mbuf.h> 58 #include <sys/malloc.h> 59 #include <sys/lock.h> 60 #include <sys/mutex.h> 61 #include <sys/kernel.h> 62 #include <sys/socket.h> 63 #include <sys/sockio.h> 64 #include <sys/errno.h> 65 #include <sys/callout.h> 66 #include <sys/bus.h> 67 #include <sys/endian.h> 68 #include <sys/kthread.h> 69 #include <sys/taskqueue.h> 70 #include <sys/priv.h> 71 #include <sys/module.h> 72 #include <sys/ktr.h> 73 #include <sys/smp.h> /* for mp_ncpus */ 74 75 #include <machine/bus.h> 76 77 #include <net/if.h> 78 #include <net/if_var.h> 79 #include <net/if_dl.h> 80 #include <net/if_media.h> 81 #include <net/if_types.h> 82 #include <net/if_arp.h> 83 #include <net/ethernet.h> 84 #include <net/if_llc.h> 85 86 #include <net80211/ieee80211_var.h> 87 #include <net80211/ieee80211_regdomain.h> 88 #ifdef IEEE80211_SUPPORT_SUPERG 89 #include <net80211/ieee80211_superg.h> 90 #endif 91 #ifdef IEEE80211_SUPPORT_TDMA 92 #include <net80211/ieee80211_tdma.h> 93 #endif 94 95 #include <net/bpf.h> 96 97 #ifdef INET 98 #include <netinet/in.h> 99 #include <netinet/if_ether.h> 100 #endif 101 102 #include <dev/ath/if_athvar.h> 103 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 104 #include <dev/ath/ath_hal/ah_diagcodes.h> 105 106 #include <dev/ath/if_ath_debug.h> 107 #include <dev/ath/if_ath_misc.h> 108 #include <dev/ath/if_ath_tsf.h> 109 #include <dev/ath/if_ath_tx.h> 110 #include <dev/ath/if_ath_sysctl.h> 111 #include <dev/ath/if_ath_led.h> 112 #include <dev/ath/if_ath_keycache.h> 113 #include <dev/ath/if_ath_rx.h> 114 #include <dev/ath/if_ath_beacon.h> 115 #include <dev/ath/if_athdfs.h> 116 #include <dev/ath/if_ath_descdma.h> 117 118 #ifdef ATH_TX99_DIAG 119 #include <dev/ath/ath_tx99/ath_tx99.h> 120 #endif 121 122 #ifdef ATH_DEBUG_ALQ 123 #include <dev/ath/if_ath_alq.h> 124 #endif 125 126 #include <dev/ath/if_ath_lna_div.h> 127 128 /* 129 * Calculate the receive filter according to the 130 * operating mode and state: 131 * 132 * o always accept unicast, broadcast, and multicast traffic 133 * o accept PHY error frames when hardware doesn't have MIB support 134 * to count and we need them for ANI (sta mode only until recently) 135 * and we are not scanning (ANI is disabled) 136 * NB: older hal's add rx filter bits out of sight and we need to 137 * blindly preserve them 138 * o probe request frames are accepted only when operating in 139 * hostap, adhoc, mesh, or monitor modes 140 * o enable promiscuous mode 141 * - when in monitor mode 142 * - if interface marked PROMISC (assumes bridge setting is filtered) 143 * o accept beacons: 144 * - when operating in station mode for collecting rssi data when 145 * the station is otherwise quiet, or 146 * - when operating in adhoc mode so the 802.11 layer creates 147 * node table entries for peers, 148 * - when scanning 149 * - when doing s/w beacon miss (e.g. for ap+sta) 150 * - when operating in ap mode in 11g to detect overlapping bss that 151 * require protection 152 * - when operating in mesh mode to detect neighbors 153 * o accept control frames: 154 * - when in monitor mode 155 * XXX HT protection for 11n 156 */ 157 u_int32_t 158 ath_calcrxfilter(struct ath_softc *sc) 159 { 160 struct ieee80211com *ic = &sc->sc_ic; 161 u_int32_t rfilt; 162 163 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 164 if (!sc->sc_needmib && !sc->sc_scanning) 165 rfilt |= HAL_RX_FILTER_PHYERR; 166 if (ic->ic_opmode != IEEE80211_M_STA) 167 rfilt |= HAL_RX_FILTER_PROBEREQ; 168 /* XXX ic->ic_monvaps != 0? */ 169 if (ic->ic_opmode == IEEE80211_M_MONITOR || ic->ic_promisc > 0) 170 rfilt |= HAL_RX_FILTER_PROM; 171 172 /* 173 * Only listen to all beacons if we're scanning. 174 * 175 * Otherwise we only really need to hear beacons from 176 * our own BSSID. 177 * 178 * IBSS? software beacon miss? Just receive all beacons. 179 * We need to hear beacons/probe requests from everyone so 180 * we can merge ibss. 181 */ 182 if (ic->ic_opmode == IEEE80211_M_IBSS || sc->sc_swbmiss) { 183 rfilt |= HAL_RX_FILTER_BEACON; 184 } else if (ic->ic_opmode == IEEE80211_M_STA) { 185 if (sc->sc_do_mybeacon && ! sc->sc_scanning) { 186 rfilt |= HAL_RX_FILTER_MYBEACON; 187 } else { /* scanning, non-mybeacon chips */ 188 rfilt |= HAL_RX_FILTER_BEACON; 189 } 190 } 191 192 /* 193 * NB: We don't recalculate the rx filter when 194 * ic_protmode changes; otherwise we could do 195 * this only when ic_protmode != NONE. 196 */ 197 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 198 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 199 rfilt |= HAL_RX_FILTER_BEACON; 200 201 /* 202 * Enable hardware PS-POLL RX only for hostap mode; 203 * STA mode sends PS-POLL frames but never 204 * receives them. 205 */ 206 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL, 207 0, NULL) == HAL_OK && 208 ic->ic_opmode == IEEE80211_M_HOSTAP) 209 rfilt |= HAL_RX_FILTER_PSPOLL; 210 211 if (sc->sc_nmeshvaps) { 212 rfilt |= HAL_RX_FILTER_BEACON; 213 if (sc->sc_hasbmatch) 214 rfilt |= HAL_RX_FILTER_BSSID; 215 else 216 rfilt |= HAL_RX_FILTER_PROM; 217 } 218 if (ic->ic_opmode == IEEE80211_M_MONITOR) 219 rfilt |= HAL_RX_FILTER_CONTROL; 220 221 /* 222 * Enable RX of compressed BAR frames only when doing 223 * 802.11n. Required for A-MPDU. 224 */ 225 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan)) 226 rfilt |= HAL_RX_FILTER_COMPBAR; 227 228 /* 229 * Enable radar PHY errors if requested by the 230 * DFS module. 231 */ 232 if (sc->sc_dodfs) 233 rfilt |= HAL_RX_FILTER_PHYRADAR; 234 235 /* 236 * Enable spectral PHY errors if requested by the 237 * spectral module. 238 */ 239 if (sc->sc_dospectral) 240 rfilt |= HAL_RX_FILTER_PHYRADAR; 241 242 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s\n", 243 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode]); 244 return rfilt; 245 } 246 247 static int 248 ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 249 { 250 struct ath_hal *ah = sc->sc_ah; 251 int error; 252 struct mbuf *m; 253 struct ath_desc *ds; 254 255 /* XXX TODO: ATH_RX_LOCK_ASSERT(sc); */ 256 257 m = bf->bf_m; 258 if (m == NULL) { 259 /* 260 * NB: by assigning a page to the rx dma buffer we 261 * implicitly satisfy the Atheros requirement that 262 * this buffer be cache-line-aligned and sized to be 263 * multiple of the cache line size. Not doing this 264 * causes weird stuff to happen (for the 5210 at least). 265 */ 266 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 267 if (m == NULL) { 268 DPRINTF(sc, ATH_DEBUG_ANY, 269 "%s: no mbuf/cluster\n", __func__); 270 sc->sc_stats.ast_rx_nombuf++; 271 return ENOMEM; 272 } 273 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 274 275 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 276 bf->bf_dmamap, m, 277 bf->bf_segs, &bf->bf_nseg, 278 BUS_DMA_NOWAIT); 279 if (error != 0) { 280 DPRINTF(sc, ATH_DEBUG_ANY, 281 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 282 __func__, error); 283 sc->sc_stats.ast_rx_busdma++; 284 m_freem(m); 285 return error; 286 } 287 KASSERT(bf->bf_nseg == 1, 288 ("multi-segment packet; nseg %u", bf->bf_nseg)); 289 bf->bf_m = m; 290 } 291 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 292 293 /* 294 * Setup descriptors. For receive we always terminate 295 * the descriptor list with a self-linked entry so we'll 296 * not get overrun under high load (as can happen with a 297 * 5212 when ANI processing enables PHY error frames). 298 * 299 * To insure the last descriptor is self-linked we create 300 * each descriptor as self-linked and add it to the end. As 301 * each additional descriptor is added the previous self-linked 302 * entry is ``fixed'' naturally. This should be safe even 303 * if DMA is happening. When processing RX interrupts we 304 * never remove/process the last, self-linked, entry on the 305 * descriptor list. This insures the hardware always has 306 * someplace to write a new frame. 307 */ 308 /* 309 * 11N: we can no longer afford to self link the last descriptor. 310 * MAC acknowledges BA status as long as it copies frames to host 311 * buffer (or rx fifo). This can incorrectly acknowledge packets 312 * to a sender if last desc is self-linked. 313 */ 314 ds = bf->bf_desc; 315 if (sc->sc_rxslink) 316 ds->ds_link = bf->bf_daddr; /* link to self */ 317 else 318 ds->ds_link = 0; /* terminate the list */ 319 ds->ds_data = bf->bf_segs[0].ds_addr; 320 ath_hal_setuprxdesc(ah, ds 321 , m->m_len /* buffer size */ 322 , 0 323 ); 324 325 if (sc->sc_rxlink != NULL) 326 *sc->sc_rxlink = bf->bf_daddr; 327 sc->sc_rxlink = &ds->ds_link; 328 return 0; 329 } 330 331 /* 332 * Intercept management frames to collect beacon rssi data 333 * and to do ibss merges. 334 */ 335 void 336 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 337 int subtype, const struct ieee80211_rx_stats *rxs, int rssi, int nf) 338 { 339 struct ieee80211vap *vap = ni->ni_vap; 340 struct ath_softc *sc = vap->iv_ic->ic_softc; 341 uint64_t tsf_beacon_old, tsf_beacon; 342 uint64_t nexttbtt; 343 int64_t tsf_delta; 344 int32_t tsf_delta_bmiss; 345 int32_t tsf_remainder; 346 uint64_t tsf_beacon_target; 347 int tsf_intval; 348 349 tsf_beacon_old = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32; 350 tsf_beacon_old |= le32dec(ni->ni_tstamp.data); 351 352 #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10) 353 tsf_intval = 1; 354 if (ni->ni_intval > 0) { 355 tsf_intval = TU_TO_TSF(ni->ni_intval); 356 } 357 #undef TU_TO_TSF 358 359 /* 360 * Call up first so subsequent work can use information 361 * potentially stored in the node (e.g. for ibss merge). 362 */ 363 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rxs, rssi, nf); 364 switch (subtype) { 365 case IEEE80211_FC0_SUBTYPE_BEACON: 366 /* 367 * Always update the per-node beacon RSSI if we're hearing 368 * beacons from that node. 369 */ 370 ATH_RSSI_LPF(ATH_NODE(ni)->an_node_stats.ns_avgbrssi, rssi); 371 372 /* 373 * Only do the following processing if it's for 374 * the current BSS. 375 * 376 * In scan and IBSS mode we receive all beacons, 377 * which means we need to filter out stuff 378 * that isn't for us or we'll end up constantly 379 * trying to sync / merge to BSSes that aren't 380 * actually us. 381 */ 382 if ((vap->iv_opmode != IEEE80211_M_HOSTAP) && 383 IEEE80211_ADDR_EQ(ni->ni_bssid, vap->iv_bss->ni_bssid)) { 384 /* update rssi statistics for use by the hal */ 385 /* XXX unlocked check against vap->iv_bss? */ 386 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 387 388 tsf_beacon = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32; 389 tsf_beacon |= le32dec(ni->ni_tstamp.data); 390 391 nexttbtt = ath_hal_getnexttbtt(sc->sc_ah); 392 393 /* 394 * Let's calculate the delta and remainder, so we can see 395 * if the beacon timer from the AP is varying by more than 396 * a few TU. (Which would be a huge, huge problem.) 397 */ 398 tsf_delta = (long long) tsf_beacon - (long long) tsf_beacon_old; 399 400 tsf_delta_bmiss = tsf_delta / tsf_intval; 401 402 /* 403 * If our delta is greater than half the beacon interval, 404 * let's round the bmiss value up to the next beacon 405 * interval. Ie, we're running really, really early 406 * on the next beacon. 407 */ 408 if (tsf_delta % tsf_intval > (tsf_intval / 2)) 409 tsf_delta_bmiss ++; 410 411 tsf_beacon_target = tsf_beacon_old + 412 (((unsigned long long) tsf_delta_bmiss) * (long long) tsf_intval); 413 414 /* 415 * The remainder using '%' is between 0 .. intval-1. 416 * If we're actually running too fast, then the remainder 417 * will be some large number just under intval-1. 418 * So we need to look at whether we're running 419 * before or after the target beacon interval 420 * and if we are, modify how we do the remainder 421 * calculation. 422 */ 423 if (tsf_beacon < tsf_beacon_target) { 424 tsf_remainder = 425 -(tsf_intval - ((tsf_beacon - tsf_beacon_old) % tsf_intval)); 426 } else { 427 tsf_remainder = (tsf_beacon - tsf_beacon_old) % tsf_intval; 428 } 429 430 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: %s: old_tsf=%llu (%u), new_tsf=%llu (%u), target_tsf=%llu (%u), delta=%lld, bmiss=%d, remainder=%d\n", 431 __func__, 432 ieee80211_get_vap_ifname(vap), 433 (unsigned long long) tsf_beacon_old, 434 (unsigned int) (tsf_beacon_old >> 10), 435 (unsigned long long) tsf_beacon, 436 (unsigned int ) (tsf_beacon >> 10), 437 (unsigned long long) tsf_beacon_target, 438 (unsigned int) (tsf_beacon_target >> 10), 439 (long long) tsf_delta, 440 tsf_delta_bmiss, 441 tsf_remainder); 442 443 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: %s: ni=%6D bssid=%6D tsf=%llu (%u), nexttbtt=%llu (%u), delta=%d\n", 444 __func__, 445 ieee80211_get_vap_ifname(vap), 446 ni->ni_bssid, ":", 447 vap->iv_bss->ni_bssid, ":", 448 (unsigned long long) tsf_beacon, 449 (unsigned int) (tsf_beacon >> 10), 450 (unsigned long long) nexttbtt, 451 (unsigned int) (nexttbtt >> 10), 452 (int32_t) tsf_beacon - (int32_t) nexttbtt + tsf_intval); 453 454 /* 455 * We only do syncbeacon on STA VAPs; not on IBSS; 456 * but don't do it with swbmiss enabled or we 457 * may end up overwriting AP mode beacon config. 458 * 459 * The driver (and net80211) should be smarter about 460 * this.. 461 */ 462 if (vap->iv_opmode == IEEE80211_M_STA && 463 sc->sc_syncbeacon && 464 (!sc->sc_swbmiss) && 465 ni == vap->iv_bss && 466 ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) && 467 (vap->iv_state == IEEE80211_S_RUN || vap->iv_state == IEEE80211_S_SLEEP)) { 468 DPRINTF(sc, ATH_DEBUG_BEACON, 469 "%s: syncbeacon=1; syncing\n", 470 __func__); 471 /* 472 * Resync beacon timers using the tsf of the beacon 473 * frame we just received. 474 */ 475 ath_beacon_config(sc, vap); 476 sc->sc_syncbeacon = 0; 477 } 478 } 479 480 /* fall thru... */ 481 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 482 if (vap->iv_opmode == IEEE80211_M_IBSS && 483 vap->iv_state == IEEE80211_S_RUN && 484 ieee80211_ibss_merge_check(ni)) { 485 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 486 uint64_t tsf = ath_extend_tsf(sc, rstamp, 487 ath_hal_gettsf64(sc->sc_ah)); 488 /* 489 * Handle ibss merge as needed; check the tsf on the 490 * frame before attempting the merge. The 802.11 spec 491 * says the station should change it's bssid to match 492 * the oldest station with the same ssid, where oldest 493 * is determined by the tsf. Note that hardware 494 * reconfiguration happens through callback to 495 * ath_newstate as the state machine will go from 496 * RUN -> RUN when this happens. 497 */ 498 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 499 DPRINTF(sc, ATH_DEBUG_STATE, 500 "ibss merge, rstamp %u tsf %ju " 501 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 502 (uintmax_t)ni->ni_tstamp.tsf); 503 (void) ieee80211_ibss_merge(ni); 504 } 505 } 506 break; 507 } 508 } 509 510 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 511 static void 512 ath_rx_tap_vendor(struct ath_softc *sc, struct mbuf *m, 513 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 514 { 515 516 /* Fill in the extension bitmap */ 517 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER); 518 519 /* Fill in the vendor header */ 520 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f; 521 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03; 522 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00; 523 524 /* XXX what should this be? */ 525 sc->sc_rx_th.wr_vh.vh_sub_ns = 0; 526 sc->sc_rx_th.wr_vh.vh_skip_len = 527 htole16(sizeof(struct ath_radiotap_vendor_hdr)); 528 529 /* General version info */ 530 sc->sc_rx_th.wr_v.vh_version = 1; 531 532 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask; 533 534 /* rssi */ 535 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0]; 536 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1]; 537 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2]; 538 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0]; 539 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1]; 540 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2]; 541 542 /* evm */ 543 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0; 544 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1; 545 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2; 546 /* These are only populated from the AR9300 or later */ 547 sc->sc_rx_th.wr_v.evm[3] = rs->rs_evm3; 548 sc->sc_rx_th.wr_v.evm[4] = rs->rs_evm4; 549 550 /* direction */ 551 sc->sc_rx_th.wr_v.vh_flags = ATH_VENDOR_PKT_RX; 552 553 /* RX rate */ 554 sc->sc_rx_th.wr_v.vh_rx_hwrate = rs->rs_rate; 555 556 /* RX flags */ 557 sc->sc_rx_th.wr_v.vh_rs_flags = rs->rs_flags; 558 559 if (rs->rs_isaggr) 560 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_ISAGGR; 561 if (rs->rs_moreaggr) 562 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_MOREAGGR; 563 564 /* phyerr info */ 565 if (rs->rs_status & HAL_RXERR_PHY) { 566 sc->sc_rx_th.wr_v.vh_phyerr_code = rs->rs_phyerr; 567 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_RXPHYERR; 568 } else { 569 sc->sc_rx_th.wr_v.vh_phyerr_code = 0xff; 570 } 571 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status; 572 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi; 573 } 574 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 575 576 static void 577 ath_rx_tap(struct ath_softc *sc, struct mbuf *m, 578 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 579 { 580 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 581 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 582 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 583 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 584 const HAL_RATE_TABLE *rt; 585 uint8_t rix; 586 587 rt = sc->sc_currates; 588 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 589 rix = rt->rateCodeToIndex[rs->rs_rate]; 590 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 591 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 592 593 /* 802.11 specific flags */ 594 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 595 if (rs->rs_status & HAL_RXERR_PHY) { 596 /* 597 * PHY error - make sure the channel flags 598 * reflect the actual channel configuration, 599 * not the received frame. 600 */ 601 if (IEEE80211_IS_CHAN_HT40U(sc->sc_curchan)) 602 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 603 else if (IEEE80211_IS_CHAN_HT40D(sc->sc_curchan)) 604 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 605 else if (IEEE80211_IS_CHAN_HT20(sc->sc_curchan)) 606 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 607 } else if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 608 struct ieee80211com *ic = &sc->sc_ic; 609 610 if ((rs->rs_flags & HAL_RX_2040) == 0) 611 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 612 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 613 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 614 else 615 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 616 617 if (rs->rs_flags & HAL_RX_GI) 618 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 619 } 620 621 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf)); 622 if (rs->rs_status & HAL_RXERR_CRC) 623 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 624 /* XXX propagate other error flags from descriptor */ 625 sc->sc_rx_th.wr_antnoise = nf; 626 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi; 627 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 628 #undef CHAN_HT 629 #undef CHAN_HT20 630 #undef CHAN_HT40U 631 #undef CHAN_HT40D 632 } 633 634 static void 635 ath_handle_micerror(struct ieee80211com *ic, 636 struct ieee80211_frame *wh, int keyix) 637 { 638 struct ieee80211_node *ni; 639 640 /* XXX recheck MIC to deal w/ chips that lie */ 641 /* XXX discard MIC errors on !data frames */ 642 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 643 if (ni != NULL) { 644 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 645 ieee80211_free_node(ni); 646 } 647 } 648 649 /* 650 * Process a single packet. 651 * 652 * The mbuf must already be synced, unmapped and removed from bf->bf_m 653 * by this stage. 654 * 655 * The mbuf must be consumed by this routine - either passed up the 656 * net80211 stack, put on the holding queue, or freed. 657 */ 658 int 659 ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status, 660 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf, 661 struct mbuf *m) 662 { 663 uint64_t rstamp; 664 /* XXX TODO: make this an mbuf tag? */ 665 struct ieee80211_rx_stats rxs; 666 int len, type, i; 667 struct ieee80211com *ic = &sc->sc_ic; 668 struct ieee80211_node *ni; 669 int is_good = 0; 670 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 671 672 NET_EPOCH_ASSERT(); 673 674 /* 675 * Calculate the correct 64 bit TSF given 676 * the TSF64 register value and rs_tstamp. 677 */ 678 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf); 679 680 /* 802.11 return codes - These aren't specifically errors */ 681 if (rs->rs_flags & HAL_RX_GI) 682 sc->sc_stats.ast_rx_halfgi++; 683 if (rs->rs_flags & HAL_RX_2040) 684 sc->sc_stats.ast_rx_2040++; 685 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE) 686 sc->sc_stats.ast_rx_pre_crc_err++; 687 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST) 688 sc->sc_stats.ast_rx_post_crc_err++; 689 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY) 690 sc->sc_stats.ast_rx_decrypt_busy_err++; 691 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN) 692 sc->sc_stats.ast_rx_hi_rx_chain++; 693 if (rs->rs_flags & HAL_RX_STBC) 694 sc->sc_stats.ast_rx_stbc++; 695 696 if (rs->rs_status != 0) { 697 if (rs->rs_status & HAL_RXERR_CRC) 698 sc->sc_stats.ast_rx_crcerr++; 699 if (rs->rs_status & HAL_RXERR_FIFO) 700 sc->sc_stats.ast_rx_fifoerr++; 701 if (rs->rs_status & HAL_RXERR_PHY) { 702 sc->sc_stats.ast_rx_phyerr++; 703 /* Process DFS radar events */ 704 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) || 705 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) { 706 /* Now pass it to the radar processing code */ 707 ath_dfs_process_phy_err(sc, m, rstamp, rs); 708 } 709 710 /* 711 * Be suitably paranoid about receiving phy errors 712 * out of the stats array bounds 713 */ 714 if (rs->rs_phyerr < ATH_IOCTL_STATS_NUM_RX_PHYERR) 715 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++; 716 goto rx_error; /* NB: don't count in ierrors */ 717 } 718 if (rs->rs_status & HAL_RXERR_DECRYPT) { 719 /* 720 * Decrypt error. If the error occurred 721 * because there was no hardware key, then 722 * let the frame through so the upper layers 723 * can process it. This is necessary for 5210 724 * parts which have no way to setup a ``clear'' 725 * key cache entry. 726 * 727 * XXX do key cache faulting 728 */ 729 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 730 goto rx_accept; 731 sc->sc_stats.ast_rx_badcrypt++; 732 } 733 /* 734 * Similar as above - if the failure was a keymiss 735 * just punt it up to the upper layers for now. 736 */ 737 if (rs->rs_status & HAL_RXERR_KEYMISS) { 738 sc->sc_stats.ast_rx_keymiss++; 739 goto rx_accept; 740 } 741 if (rs->rs_status & HAL_RXERR_MIC) { 742 sc->sc_stats.ast_rx_badmic++; 743 /* 744 * Do minimal work required to hand off 745 * the 802.11 header for notification. 746 */ 747 /* XXX frag's and qos frames */ 748 len = rs->rs_datalen; 749 if (len >= sizeof (struct ieee80211_frame)) { 750 ath_handle_micerror(ic, 751 mtod(m, struct ieee80211_frame *), 752 sc->sc_splitmic ? 753 rs->rs_keyix-32 : rs->rs_keyix); 754 } 755 } 756 counter_u64_add(ic->ic_ierrors, 1); 757 rx_error: 758 /* 759 * Cleanup any pending partial frame. 760 */ 761 if (re->m_rxpending != NULL) { 762 m_freem(re->m_rxpending); 763 re->m_rxpending = NULL; 764 } 765 /* 766 * When a tap is present pass error frames 767 * that have been requested. By default we 768 * pass decrypt+mic errors but others may be 769 * interesting (e.g. crc). 770 */ 771 if (ieee80211_radiotap_active(ic) && 772 (rs->rs_status & sc->sc_monpass)) { 773 /* NB: bpf needs the mbuf length setup */ 774 len = rs->rs_datalen; 775 m->m_pkthdr.len = m->m_len = len; 776 ath_rx_tap(sc, m, rs, rstamp, nf); 777 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 778 ath_rx_tap_vendor(sc, m, rs, rstamp, nf); 779 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 780 ieee80211_radiotap_rx_all(ic, m); 781 } 782 /* XXX pass MIC errors up for s/w reclaculation */ 783 m_freem(m); m = NULL; 784 goto rx_next; 785 } 786 rx_accept: 787 len = rs->rs_datalen; 788 m->m_len = len; 789 790 if (rs->rs_more) { 791 /* 792 * Frame spans multiple descriptors; save 793 * it for the next completed descriptor, it 794 * will be used to construct a jumbogram. 795 */ 796 if (re->m_rxpending != NULL) { 797 /* NB: max frame size is currently 2 clusters */ 798 sc->sc_stats.ast_rx_toobig++; 799 m_freem(re->m_rxpending); 800 } 801 m->m_pkthdr.len = len; 802 re->m_rxpending = m; 803 m = NULL; 804 goto rx_next; 805 } else if (re->m_rxpending != NULL) { 806 /* 807 * This is the second part of a jumbogram, 808 * chain it to the first mbuf, adjust the 809 * frame length, and clear the rxpending state. 810 */ 811 re->m_rxpending->m_next = m; 812 re->m_rxpending->m_pkthdr.len += len; 813 m = re->m_rxpending; 814 re->m_rxpending = NULL; 815 } else { 816 /* 817 * Normal single-descriptor receive; setup packet length. 818 */ 819 m->m_pkthdr.len = len; 820 } 821 822 /* 823 * Validate rs->rs_antenna. 824 * 825 * Some users w/ AR9285 NICs have reported crashes 826 * here because rs_antenna field is bogusly large. 827 * Let's enforce the maximum antenna limit of 8 828 * (and it shouldn't be hard coded, but that's a 829 * separate problem) and if there's an issue, print 830 * out an error and adjust rs_antenna to something 831 * sensible. 832 * 833 * This code should be removed once the actual 834 * root cause of the issue has been identified. 835 * For example, it may be that the rs_antenna 836 * field is only valid for the last frame of 837 * an aggregate and it just happens that it is 838 * "mostly" right. (This is a general statement - 839 * the majority of the statistics are only valid 840 * for the last frame in an aggregate. 841 */ 842 if (rs->rs_antenna >= ATH_IOCTL_STATS_NUM_RX_ANTENNA) { 843 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n", 844 __func__, rs->rs_antenna); 845 #ifdef ATH_DEBUG 846 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 847 #endif /* ATH_DEBUG */ 848 rs->rs_antenna = 0; /* XXX better than nothing */ 849 } 850 851 /* 852 * If this is an AR9285/AR9485, then the receive and LNA 853 * configuration is stored in RSSI[2] / EXTRSSI[2]. 854 * We can extract this out to build a much better 855 * receive antenna profile. 856 * 857 * Yes, this just blurts over the above RX antenna field 858 * for now. It's fine, the AR9285 doesn't really use 859 * that. 860 * 861 * Later on we should store away the fine grained LNA 862 * information and keep separate counters just for 863 * that. It'll help when debugging the AR9285/AR9485 864 * combined diversity code. 865 */ 866 if (sc->sc_rx_lnamixer) { 867 rs->rs_antenna = 0; 868 869 /* Bits 0:1 - the LNA configuration used */ 870 rs->rs_antenna |= 871 ((rs->rs_rssi_ctl[2] & HAL_RX_LNA_CFG_USED) 872 >> HAL_RX_LNA_CFG_USED_S); 873 874 /* Bit 2 - the external RX antenna switch */ 875 if (rs->rs_rssi_ctl[2] & HAL_RX_LNA_EXTCFG) 876 rs->rs_antenna |= 0x4; 877 } 878 879 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 880 881 /* 882 * Populate the rx status block. When there are bpf 883 * listeners we do the additional work to provide 884 * complete status. Otherwise we fill in only the 885 * material required by ieee80211_input. Note that 886 * noise setting is filled in above. 887 */ 888 if (ieee80211_radiotap_active(ic)) { 889 ath_rx_tap(sc, m, rs, rstamp, nf); 890 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 891 ath_rx_tap_vendor(sc, m, rs, rstamp, nf); 892 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 893 } 894 895 /* 896 * From this point on we assume the frame is at least 897 * as large as ieee80211_frame_min; verify that. 898 */ 899 if (len < IEEE80211_MIN_LEN) { 900 if (!ieee80211_radiotap_active(ic)) { 901 DPRINTF(sc, ATH_DEBUG_RECV, 902 "%s: short packet %d\n", __func__, len); 903 sc->sc_stats.ast_rx_tooshort++; 904 } else { 905 /* NB: in particular this captures ack's */ 906 ieee80211_radiotap_rx_all(ic, m); 907 } 908 m_freem(m); m = NULL; 909 goto rx_next; 910 } 911 912 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 913 const HAL_RATE_TABLE *rt = sc->sc_currates; 914 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 915 916 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 917 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 918 } 919 920 m_adj(m, -IEEE80211_CRC_LEN); 921 922 /* 923 * Locate the node for sender, track state, and then 924 * pass the (referenced) node up to the 802.11 layer 925 * for its use. 926 */ 927 ni = ieee80211_find_rxnode_withkey(ic, 928 mtod(m, const struct ieee80211_frame_min *), 929 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 930 IEEE80211_KEYIX_NONE : rs->rs_keyix); 931 sc->sc_lastrs = rs; 932 933 if (rs->rs_isaggr) 934 sc->sc_stats.ast_rx_agg++; 935 936 /* 937 * Populate the per-chain RSSI values where appropriate. 938 */ 939 bzero(&rxs, sizeof(rxs)); 940 rxs.r_flags |= IEEE80211_R_NF | IEEE80211_R_RSSI | 941 IEEE80211_R_C_CHAIN | 942 IEEE80211_R_C_NF | 943 IEEE80211_R_C_RSSI | 944 IEEE80211_R_TSF64 | 945 IEEE80211_R_TSF_START; /* XXX TODO: validate */ 946 rxs.c_rssi = rs->rs_rssi; 947 rxs.c_nf = nf; 948 rxs.c_chain = 3; /* XXX TODO: check */ 949 rxs.c_rx_tsf = rstamp; 950 951 for (i = 0; i < 3; i++) { 952 rxs.c_rssi_ctl[i] = rs->rs_rssi_ctl[i]; 953 rxs.c_rssi_ext[i] = rs->rs_rssi_ext[i]; 954 /* 955 * XXX note: we currently don't track 956 * per-chain noisefloor. 957 */ 958 rxs.c_nf_ctl[i] = nf; 959 rxs.c_nf_ext[i] = nf; 960 } 961 962 if (ni != NULL) { 963 /* 964 * Only punt packets for ampdu reorder processing for 965 * 11n nodes; net80211 enforces that M_AMPDU is only 966 * set for 11n nodes. 967 */ 968 if (ni->ni_flags & IEEE80211_NODE_HT) 969 m->m_flags |= M_AMPDU; 970 971 /* 972 * Inform rate control about the received RSSI. 973 * It can then use this information to potentially drastically 974 * alter the available rate based on the RSSI estimate. 975 * 976 * This is super important when associating to a far away station; 977 * you don't want to waste time trying higher rates at some low 978 * packet exchange rate (like during DHCP) just to establish 979 * that higher MCS rates aren't available. 980 */ 981 ATH_RSSI_LPF(ATH_NODE(ni)->an_node_stats.ns_avgrssi, 982 rs->rs_rssi); 983 ath_rate_update_rx_rssi(sc, ATH_NODE(ni), 984 ATH_RSSI(ATH_NODE(ni)->an_node_stats.ns_avgrssi)); 985 986 /* 987 * Sending station is known, dispatch directly. 988 */ 989 (void) ieee80211_add_rx_params(m, &rxs); 990 type = ieee80211_input_mimo(ni, m); 991 ieee80211_free_node(ni); 992 m = NULL; 993 /* 994 * Arrange to update the last rx timestamp only for 995 * frames from our ap when operating in station mode. 996 * This assumes the rx key is always setup when 997 * associated. 998 */ 999 if (ic->ic_opmode == IEEE80211_M_STA && 1000 rs->rs_keyix != HAL_RXKEYIX_INVALID) 1001 is_good = 1; 1002 } else { 1003 (void) ieee80211_add_rx_params(m, &rxs); 1004 type = ieee80211_input_mimo_all(ic, m); 1005 m = NULL; 1006 } 1007 1008 /* 1009 * At this point we have passed the frame up the stack; thus 1010 * the mbuf is no longer ours. 1011 */ 1012 1013 /* 1014 * Track legacy station RX rssi and do any rx antenna management. 1015 */ 1016 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 1017 if (sc->sc_diversity) { 1018 /* 1019 * When using fast diversity, change the default rx 1020 * antenna if diversity chooses the other antenna 3 1021 * times in a row. 1022 */ 1023 if (sc->sc_defant != rs->rs_antenna) { 1024 if (++sc->sc_rxotherant >= 3) 1025 ath_setdefantenna(sc, rs->rs_antenna); 1026 } else 1027 sc->sc_rxotherant = 0; 1028 } 1029 1030 /* Handle slow diversity if enabled */ 1031 if (sc->sc_dolnadiv) { 1032 ath_lna_rx_comb_scan(sc, rs, ticks, hz); 1033 } 1034 1035 if (sc->sc_softled) { 1036 /* 1037 * Blink for any data frame. Otherwise do a 1038 * heartbeat-style blink when idle. The latter 1039 * is mainly for station mode where we depend on 1040 * periodic beacon frames to trigger the poll event. 1041 */ 1042 if (type == IEEE80211_FC0_TYPE_DATA) { 1043 const HAL_RATE_TABLE *rt = sc->sc_currates; 1044 ath_led_event(sc, 1045 rt->rateCodeToIndex[rs->rs_rate]); 1046 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 1047 ath_led_event(sc, 0); 1048 } 1049 rx_next: 1050 /* 1051 * Debugging - complain if we didn't NULL the mbuf pointer 1052 * here. 1053 */ 1054 if (m != NULL) { 1055 device_printf(sc->sc_dev, 1056 "%s: mbuf %p should've been freed!\n", 1057 __func__, 1058 m); 1059 } 1060 return (is_good); 1061 } 1062 1063 #define ATH_RX_MAX 128 1064 1065 /* 1066 * XXX TODO: break out the "get buffers" from "call ath_rx_pkt()" like 1067 * the EDMA code does. 1068 * 1069 * XXX TODO: then, do all of the RX list management stuff inside 1070 * ATH_RX_LOCK() so we don't end up potentially racing. The EDMA 1071 * code is doing it right. 1072 */ 1073 static void 1074 ath_rx_proc(struct ath_softc *sc, int resched) 1075 { 1076 #define PA2DESC(_sc, _pa) \ 1077 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1078 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1079 struct ath_buf *bf; 1080 struct ath_hal *ah = sc->sc_ah; 1081 #ifdef IEEE80211_SUPPORT_SUPERG 1082 struct ieee80211com *ic = &sc->sc_ic; 1083 #endif 1084 struct ath_desc *ds; 1085 struct ath_rx_status *rs; 1086 struct mbuf *m; 1087 int ngood; 1088 HAL_STATUS status; 1089 int16_t nf; 1090 u_int64_t tsf; 1091 int npkts = 0; 1092 int kickpcu = 0; 1093 int ret; 1094 1095 NET_EPOCH_ASSERT(); 1096 1097 /* XXX we must not hold the ATH_LOCK here */ 1098 ATH_UNLOCK_ASSERT(sc); 1099 ATH_PCU_UNLOCK_ASSERT(sc); 1100 1101 ATH_PCU_LOCK(sc); 1102 sc->sc_rxproc_cnt++; 1103 kickpcu = sc->sc_kickpcu; 1104 ATH_PCU_UNLOCK(sc); 1105 1106 ATH_LOCK(sc); 1107 ath_power_set_power_state(sc, HAL_PM_AWAKE); 1108 ATH_UNLOCK(sc); 1109 1110 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__); 1111 ngood = 0; 1112 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 1113 sc->sc_stats.ast_rx_noise = nf; 1114 tsf = ath_hal_gettsf64(ah); 1115 do { 1116 /* 1117 * Don't process too many packets at a time; give the 1118 * TX thread time to also run - otherwise the TX 1119 * latency can jump by quite a bit, causing throughput 1120 * degredation. 1121 */ 1122 if (!kickpcu && npkts >= ATH_RX_MAX) 1123 break; 1124 1125 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1126 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */ 1127 device_printf(sc->sc_dev, "%s: no buffer!\n", __func__); 1128 break; 1129 } else if (bf == NULL) { 1130 /* 1131 * End of List: 1132 * this can happen for non-self-linked RX chains 1133 */ 1134 sc->sc_stats.ast_rx_hitqueueend++; 1135 break; 1136 } 1137 m = bf->bf_m; 1138 if (m == NULL) { /* NB: shouldn't happen */ 1139 /* 1140 * If mbuf allocation failed previously there 1141 * will be no mbuf; try again to re-populate it. 1142 */ 1143 /* XXX make debug msg */ 1144 device_printf(sc->sc_dev, "%s: no mbuf!\n", __func__); 1145 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1146 goto rx_proc_next; 1147 } 1148 ds = bf->bf_desc; 1149 if (ds->ds_link == bf->bf_daddr) { 1150 /* NB: never process the self-linked entry at the end */ 1151 sc->sc_stats.ast_rx_hitqueueend++; 1152 break; 1153 } 1154 /* XXX sync descriptor memory */ 1155 /* 1156 * Must provide the virtual address of the current 1157 * descriptor, the physical address, and the virtual 1158 * address of the next descriptor in the h/w chain. 1159 * This allows the HAL to look ahead to see if the 1160 * hardware is done with a descriptor by checking the 1161 * done bit in the following descriptor and the address 1162 * of the current descriptor the DMA engine is working 1163 * on. All this is necessary because of our use of 1164 * a self-linked list to avoid rx overruns. 1165 */ 1166 rs = &bf->bf_status.ds_rxstat; 1167 status = ath_hal_rxprocdesc(ah, ds, 1168 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1169 #ifdef ATH_DEBUG 1170 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 1171 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 1172 #endif 1173 1174 #ifdef ATH_DEBUG_ALQ 1175 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS)) 1176 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS, 1177 sc->sc_rx_statuslen, (char *) ds); 1178 #endif /* ATH_DEBUG_ALQ */ 1179 1180 if (status == HAL_EINPROGRESS) 1181 break; 1182 1183 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1184 npkts++; 1185 1186 /* 1187 * Process a single frame. 1188 */ 1189 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD); 1190 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1191 bf->bf_m = NULL; 1192 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf, m)) 1193 ngood++; 1194 rx_proc_next: 1195 /* 1196 * If there's a holding buffer, insert that onto 1197 * the RX list; the hardware is now definitely not pointing 1198 * to it now. 1199 */ 1200 ret = 0; 1201 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf != NULL) { 1202 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, 1203 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf, 1204 bf_list); 1205 ret = ath_rxbuf_init(sc, 1206 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf); 1207 } 1208 /* 1209 * Next, throw our buffer into the holding entry. The hardware 1210 * may use the descriptor to read the link pointer before 1211 * DMAing the next descriptor in to write out a packet. 1212 */ 1213 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = bf; 1214 } while (ret == 0); 1215 1216 /* rx signal state monitoring */ 1217 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 1218 if (ngood) 1219 sc->sc_lastrx = tsf; 1220 1221 ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood); 1222 /* Queue DFS tasklet if needed */ 1223 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan)) 1224 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask); 1225 1226 /* 1227 * Now that all the RX frames were handled that 1228 * need to be handled, kick the PCU if there's 1229 * been an RXEOL condition. 1230 */ 1231 if (resched && kickpcu) { 1232 ATH_PCU_LOCK(sc); 1233 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu"); 1234 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n", 1235 __func__, npkts); 1236 1237 /* 1238 * Go through the process of fully tearing down 1239 * the RX buffers and reinitialising them. 1240 * 1241 * There's a hardware bug that causes the RX FIFO 1242 * to get confused under certain conditions and 1243 * constantly write over the same frame, leading 1244 * the RX driver code here to get heavily confused. 1245 */ 1246 /* 1247 * XXX Has RX DMA stopped enough here to just call 1248 * ath_startrecv()? 1249 * XXX Do we need to use the holding buffer to restart 1250 * RX DMA by appending entries to the final 1251 * descriptor? Quite likely. 1252 */ 1253 #if 1 1254 ath_startrecv(sc); 1255 #else 1256 /* 1257 * Disabled for now - it'd be nice to be able to do 1258 * this in order to limit the amount of CPU time spent 1259 * reinitialising the RX side (and thus minimise RX 1260 * drops) however there's a hardware issue that 1261 * causes things to get too far out of whack. 1262 */ 1263 /* 1264 * XXX can we hold the PCU lock here? 1265 * Are there any net80211 buffer calls involved? 1266 */ 1267 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1268 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1269 ath_hal_rxena(ah); /* enable recv descriptors */ 1270 ath_mode_init(sc); /* set filters, etc. */ 1271 ath_hal_startpcurecv(ah, (!! sc->sc_scanning)); /* re-enable PCU/DMA engine */ 1272 #endif 1273 1274 ath_hal_intrset(ah, sc->sc_imask); 1275 sc->sc_kickpcu = 0; 1276 ATH_PCU_UNLOCK(sc); 1277 } 1278 1279 #ifdef IEEE80211_SUPPORT_SUPERG 1280 if (resched) 1281 ieee80211_ff_age_all(ic, 100); 1282 #endif 1283 1284 /* 1285 * Put the hardware to sleep again if we're done with it. 1286 */ 1287 ATH_LOCK(sc); 1288 ath_power_restore_power_state(sc); 1289 ATH_UNLOCK(sc); 1290 1291 /* 1292 * If we hit the maximum number of frames in this round, 1293 * reschedule for another immediate pass. This gives 1294 * the TX and TX completion routines time to run, which 1295 * will reduce latency. 1296 */ 1297 if (npkts >= ATH_RX_MAX) 1298 sc->sc_rx.recv_sched(sc, resched); 1299 1300 ATH_PCU_LOCK(sc); 1301 sc->sc_rxproc_cnt--; 1302 ATH_PCU_UNLOCK(sc); 1303 } 1304 #undef PA2DESC 1305 #undef ATH_RX_MAX 1306 1307 /* 1308 * Only run the RX proc if it's not already running. 1309 * Since this may get run as part of the reset/flush path, 1310 * the task can't clash with an existing, running tasklet. 1311 */ 1312 static void 1313 ath_legacy_rx_tasklet(void *arg, int npending) 1314 { 1315 struct ath_softc *sc = arg; 1316 struct epoch_tracker et; 1317 1318 ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending); 1319 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 1320 ATH_PCU_LOCK(sc); 1321 if (sc->sc_inreset_cnt > 0) { 1322 device_printf(sc->sc_dev, 1323 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 1324 ATH_PCU_UNLOCK(sc); 1325 return; 1326 } 1327 ATH_PCU_UNLOCK(sc); 1328 1329 NET_EPOCH_ENTER(et); 1330 ath_rx_proc(sc, 1); 1331 NET_EPOCH_EXIT(et); 1332 } 1333 1334 static void 1335 ath_legacy_flushrecv(struct ath_softc *sc) 1336 { 1337 struct epoch_tracker et; 1338 NET_EPOCH_ENTER(et); 1339 ath_rx_proc(sc, 0); 1340 NET_EPOCH_EXIT(et); 1341 } 1342 1343 static void 1344 ath_legacy_flush_rxpending(struct ath_softc *sc) 1345 { 1346 1347 /* XXX ATH_RX_LOCK_ASSERT(sc); */ 1348 1349 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) { 1350 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending); 1351 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1352 } 1353 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) { 1354 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending); 1355 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1356 } 1357 } 1358 1359 static int 1360 ath_legacy_flush_rxholdbf(struct ath_softc *sc) 1361 { 1362 struct ath_buf *bf; 1363 1364 /* XXX ATH_RX_LOCK_ASSERT(sc); */ 1365 /* 1366 * If there are RX holding buffers, free them here and return 1367 * them to the list. 1368 * 1369 * XXX should just verify that bf->bf_m is NULL, as it must 1370 * be at this point! 1371 */ 1372 bf = sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf; 1373 if (bf != NULL) { 1374 if (bf->bf_m != NULL) 1375 m_freem(bf->bf_m); 1376 bf->bf_m = NULL; 1377 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1378 (void) ath_rxbuf_init(sc, bf); 1379 } 1380 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = NULL; 1381 1382 bf = sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf; 1383 if (bf != NULL) { 1384 if (bf->bf_m != NULL) 1385 m_freem(bf->bf_m); 1386 bf->bf_m = NULL; 1387 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1388 (void) ath_rxbuf_init(sc, bf); 1389 } 1390 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf = NULL; 1391 1392 return (0); 1393 } 1394 1395 /* 1396 * Disable the receive h/w in preparation for a reset. 1397 */ 1398 static void 1399 ath_legacy_stoprecv(struct ath_softc *sc, int dodelay) 1400 { 1401 #define PA2DESC(_sc, _pa) \ 1402 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1403 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1404 struct ath_hal *ah = sc->sc_ah; 1405 1406 ATH_RX_LOCK(sc); 1407 1408 ath_hal_stoppcurecv(ah); /* disable PCU */ 1409 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 1410 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 1411 /* 1412 * TODO: see if this particular DELAY() is required; it may be 1413 * masking some missing FIFO flush or DMA sync. 1414 */ 1415 #if 0 1416 if (dodelay) 1417 #endif 1418 DELAY(3000); /* 3ms is long enough for 1 frame */ 1419 #ifdef ATH_DEBUG 1420 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 1421 struct ath_buf *bf; 1422 u_int ix; 1423 1424 device_printf(sc->sc_dev, 1425 "%s: rx queue %p, link %p\n", 1426 __func__, 1427 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP), 1428 sc->sc_rxlink); 1429 ix = 0; 1430 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1431 struct ath_desc *ds = bf->bf_desc; 1432 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 1433 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 1434 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1435 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 1436 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 1437 ix++; 1438 } 1439 } 1440 #endif 1441 1442 (void) ath_legacy_flush_rxpending(sc); 1443 (void) ath_legacy_flush_rxholdbf(sc); 1444 1445 sc->sc_rxlink = NULL; /* just in case */ 1446 1447 ATH_RX_UNLOCK(sc); 1448 #undef PA2DESC 1449 } 1450 1451 /* 1452 * XXX TODO: something was calling startrecv without calling 1453 * stoprecv. Let's figure out what/why. It was showing up 1454 * as a mbuf leak (rxpending) and ath_buf leak (holdbf.) 1455 */ 1456 1457 /* 1458 * Enable the receive h/w following a reset. 1459 */ 1460 static int 1461 ath_legacy_startrecv(struct ath_softc *sc) 1462 { 1463 struct ath_hal *ah = sc->sc_ah; 1464 struct ath_buf *bf; 1465 1466 ATH_RX_LOCK(sc); 1467 1468 /* 1469 * XXX should verify these are already all NULL! 1470 */ 1471 sc->sc_rxlink = NULL; 1472 (void) ath_legacy_flush_rxpending(sc); 1473 (void) ath_legacy_flush_rxholdbf(sc); 1474 1475 /* 1476 * Re-chain all of the buffers in the RX buffer list. 1477 */ 1478 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1479 int error = ath_rxbuf_init(sc, bf); 1480 if (error != 0) { 1481 DPRINTF(sc, ATH_DEBUG_RECV, 1482 "%s: ath_rxbuf_init failed %d\n", 1483 __func__, error); 1484 return error; 1485 } 1486 } 1487 1488 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1489 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1490 ath_hal_rxena(ah); /* enable recv descriptors */ 1491 ath_mode_init(sc); /* set filters, etc. */ 1492 ath_hal_startpcurecv(ah, (!! sc->sc_scanning)); /* re-enable PCU/DMA engine */ 1493 1494 ATH_RX_UNLOCK(sc); 1495 return 0; 1496 } 1497 1498 static int 1499 ath_legacy_dma_rxsetup(struct ath_softc *sc) 1500 { 1501 int error; 1502 1503 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 1504 "rx", sizeof(struct ath_desc), ath_rxbuf, 1); 1505 if (error != 0) 1506 return (error); 1507 1508 return (0); 1509 } 1510 1511 static int 1512 ath_legacy_dma_rxteardown(struct ath_softc *sc) 1513 { 1514 1515 if (sc->sc_rxdma.dd_desc_len != 0) 1516 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 1517 return (0); 1518 } 1519 1520 static void 1521 ath_legacy_recv_sched(struct ath_softc *sc, int dosched) 1522 { 1523 1524 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1525 } 1526 1527 static void 1528 ath_legacy_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE q, 1529 int dosched) 1530 { 1531 1532 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1533 } 1534 1535 void 1536 ath_recv_setup_legacy(struct ath_softc *sc) 1537 { 1538 1539 /* Sensible legacy defaults */ 1540 /* 1541 * XXX this should be changed to properly support the 1542 * exact RX descriptor size for each HAL. 1543 */ 1544 sc->sc_rx_statuslen = sizeof(struct ath_desc); 1545 1546 sc->sc_rx.recv_start = ath_legacy_startrecv; 1547 sc->sc_rx.recv_stop = ath_legacy_stoprecv; 1548 sc->sc_rx.recv_flush = ath_legacy_flushrecv; 1549 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet; 1550 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init; 1551 1552 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup; 1553 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown; 1554 sc->sc_rx.recv_sched = ath_legacy_recv_sched; 1555 sc->sc_rx.recv_sched_queue = ath_legacy_recv_sched_queue; 1556 }
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