1 /*-
2 * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 * 3. Neither the names of the above-listed copyright holders nor the names
16 * of any contributors may be used to endorse or promote products derived
17 * from this software without specific prior written permission.
18 *
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") version 2 as published by the Free
21 * Software Foundation.
22 *
23 * NO WARRANTY
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
35 *
36 * $FreeBSD: releng/6.4/sys/dev/ath/if_athvar.h 167694 2007-03-19 05:34:30Z sam $
37 */
38
39 /*
40 * Defintions for the Atheros Wireless LAN controller driver.
41 */
42 #ifndef _DEV_ATH_ATHVAR_H
43 #define _DEV_ATH_ATHVAR_H
44
45 #include <sys/taskqueue.h>
46
47 #include <contrib/dev/ath/ah.h>
48 #include <contrib/dev/ath/ah_desc.h>
49 #include <net80211/ieee80211_radiotap.h>
50 #include <dev/ath/if_athioctl.h>
51 #include <dev/ath/if_athrate.h>
52
53 #define ATH_TIMEOUT 1000
54
55 #ifndef ATH_RXBUF
56 #define ATH_RXBUF 40 /* number of RX buffers */
57 #endif
58 #ifndef ATH_TXBUF
59 #define ATH_TXBUF 100 /* number of TX buffers */
60 #endif
61 #define ATH_TXDESC 10 /* number of descriptors per buffer */
62 #define ATH_TXMAXTRY 11 /* max number of transmit attempts */
63 #define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */
64 #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */
65
66 #define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */
67 #define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */
68 #define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */
69
70 /*
71 * The key cache is used for h/w cipher state and also for
72 * tracking station state such as the current tx antenna.
73 * We also setup a mapping table between key cache slot indices
74 * and station state to short-circuit node lookups on rx.
75 * Different parts have different size key caches. We handle
76 * up to ATH_KEYMAX entries (could dynamically allocate state).
77 */
78 #define ATH_KEYMAX 128 /* max key cache size we handle */
79 #define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */
80
81 /* driver-specific node state */
82 struct ath_node {
83 struct ieee80211_node an_node; /* base class */
84 u_int32_t an_avgrssi; /* average rssi over all rx frames */
85 /* variable-length rate control state follows */
86 };
87 #define ATH_NODE(ni) ((struct ath_node *)(ni))
88 #define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni))
89
90 #define ATH_RSSI_LPF_LEN 10
91 #define ATH_RSSI_DUMMY_MARKER 0x127
92 #define ATH_EP_MUL(x, mul) ((x) * (mul))
93 #define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER))
94 #define ATH_LPF_RSSI(x, y, len) \
95 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
96 #define ATH_RSSI_LPF(x, y) do { \
97 if ((y) >= -20) \
98 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
99 } while (0)
100
101 struct ath_buf {
102 STAILQ_ENTRY(ath_buf) bf_list;
103 int bf_nseg;
104 int bf_flags; /* tx descriptor flags */
105 struct ath_desc *bf_desc; /* virtual addr of desc */
106 struct ath_desc_status bf_status; /* tx/rx status */
107 bus_addr_t bf_daddr; /* physical addr of desc */
108 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */
109 struct mbuf *bf_m; /* mbuf for buf */
110 struct ieee80211_node *bf_node; /* pointer to the node */
111 bus_size_t bf_mapsize;
112 #define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */
113 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER];
114 };
115 typedef STAILQ_HEAD(, ath_buf) ath_bufhead;
116
117 /*
118 * DMA state for tx/rx descriptors.
119 */
120 struct ath_descdma {
121 const char* dd_name;
122 struct ath_desc *dd_desc; /* descriptors */
123 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */
124 bus_size_t dd_desc_len; /* size of dd_desc */
125 bus_dma_segment_t dd_dseg;
126 bus_dma_tag_t dd_dmat; /* bus DMA tag */
127 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */
128 struct ath_buf *dd_bufptr; /* associated buffers */
129 };
130
131 /*
132 * Data transmit queue state. One of these exists for each
133 * hardware transmit queue. Packets sent to us from above
134 * are assigned to queues based on their priority. Not all
135 * devices support a complete set of hardware transmit queues.
136 * For those devices the array sc_ac2q will map multiple
137 * priorities to fewer hardware queues (typically all to one
138 * hardware queue).
139 */
140 struct ath_txq {
141 u_int axq_qnum; /* hardware q number */
142 u_int axq_depth; /* queue depth (stat only) */
143 u_int axq_intrcnt; /* interrupt count */
144 u_int32_t *axq_link; /* link ptr in last TX desc */
145 STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */
146 struct mtx axq_lock; /* lock on q and link */
147 char axq_name[12]; /* e.g. "ath0_txq4" */
148 };
149
150 #define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \
151 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \
152 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \
153 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \
154 } while (0)
155 #define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock)
156 #define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock)
157 #define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock)
158 #define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED)
159
160 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
161 STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \
162 (_tq)->axq_depth++; \
163 } while (0)
164 #define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \
165 STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \
166 (_tq)->axq_depth--; \
167 } while (0)
168
169 struct taskqueue;
170 struct ath_tx99;
171
172 struct ath_softc {
173 struct ifnet *sc_ifp; /* interface common */
174 struct ath_stats sc_stats; /* interface statistics */
175 struct ieee80211com sc_ic; /* IEEE 802.11 common */
176 int sc_debug;
177 u_int32_t sc_countrycode;
178 u_int32_t sc_regdomain;
179 void (*sc_recv_mgmt)(struct ieee80211com *,
180 struct mbuf *,
181 struct ieee80211_node *,
182 int, int, u_int32_t);
183 int (*sc_newstate)(struct ieee80211com *,
184 enum ieee80211_state, int);
185 void (*sc_node_free)(struct ieee80211_node *);
186 device_t sc_dev;
187 HAL_BUS_TAG sc_st; /* bus space tag */
188 HAL_BUS_HANDLE sc_sh; /* bus space handle */
189 bus_dma_tag_t sc_dmat; /* bus DMA tag */
190 struct mtx sc_mtx; /* master lock (recursive) */
191 struct taskqueue *sc_tq; /* private task queue */
192 struct proc *sc_tqproc;
193 struct ath_hal *sc_ah; /* Atheros HAL */
194 struct ath_ratectrl *sc_rc; /* tx rate control support */
195 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */
196 void (*sc_setdefantenna)(struct ath_softc *, u_int);
197 unsigned int sc_invalid : 1, /* disable hardware accesses */
198 sc_mrretry : 1, /* multi-rate retry support */
199 sc_softled : 1, /* enable LED gpio status */
200 sc_splitmic: 1, /* split TKIP MIC keys */
201 sc_needmib : 1, /* enable MIB stats intr */
202 sc_diversity : 1,/* enable rx diversity */
203 sc_hasveol : 1, /* tx VEOL support */
204 sc_ledstate: 1, /* LED on/off state */
205 sc_blinking: 1, /* LED blink operation active */
206 sc_mcastkey: 1, /* mcast key cache search */
207 sc_syncbeacon:1,/* sync/resync beacon timers */
208 sc_hasclrkey:1, /* CLR key supported */
209 sc_xchanmode: 1,/* extended channel mode */
210 sc_outdoor : 1;/* outdoor operation */
211 /* rate tables */
212 #define IEEE80211_MODE_HALF (IEEE80211_MODE_MAX+0)
213 #define IEEE80211_MODE_QUARTER (IEEE80211_MODE_MAX+1)
214 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX+2];
215 const HAL_RATE_TABLE *sc_currates; /* current rate table */
216 enum ieee80211_phymode sc_curmode; /* current phy mode */
217 HAL_OPMODE sc_opmode; /* current operating mode */
218 u_int16_t sc_curtxpow; /* current tx power limit */
219 HAL_CHANNEL sc_curchan; /* current h/w channel */
220 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */
221 struct {
222 u_int8_t ieeerate; /* IEEE rate */
223 u_int8_t rxflags; /* radiotap rx flags */
224 u_int8_t txflags; /* radiotap tx flags */
225 u_int16_t ledon; /* softled on time */
226 u_int16_t ledoff; /* softled off time */
227 } sc_hwmap[32]; /* h/w rate ix mappings */
228 u_int8_t sc_minrateix; /* min h/w rate index */
229 u_int8_t sc_mcastrix; /* mcast h/w rate index */
230 u_int8_t sc_protrix; /* protection rate index */
231 u_int sc_mcastrate; /* ieee rate for mcastrateix */
232 u_int sc_txantenna; /* tx antenna (fixed or auto) */
233 HAL_INT sc_imask; /* interrupt mask copy */
234 u_int sc_keymax; /* size of key cache */
235 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */
236
237 u_int sc_ledpin; /* GPIO pin for driving LED */
238 u_int sc_ledon; /* pin setting for LED on */
239 u_int sc_ledidle; /* idle polling interval */
240 int sc_ledevent; /* time of last LED event */
241 u_int8_t sc_rxrate; /* current rx rate for LED */
242 u_int8_t sc_txrate; /* current tx rate for LED */
243 u_int16_t sc_ledoff; /* off time for current blink */
244 struct callout sc_ledtimer; /* led off timer */
245
246 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */
247 u_int sc_rfsilentpol; /* pin setting for rfkill on */
248
249 struct bpf_if *sc_drvbpf;
250 union {
251 struct ath_tx_radiotap_header th;
252 u_int8_t pad[64];
253 } u_tx_rt;
254 int sc_tx_th_len;
255 union {
256 struct ath_rx_radiotap_header th;
257 u_int8_t pad[64];
258 } u_rx_rt;
259 int sc_rx_th_len;
260 u_int sc_monpass; /* frames to pass in mon.mode */
261
262 struct ath_descdma sc_rxdma; /* RX descriptos */
263 ath_bufhead sc_rxbuf; /* receive buffer */
264 u_int32_t *sc_rxlink; /* link ptr in last RX desc */
265 struct task sc_rxtask; /* rx int processing */
266 struct task sc_rxorntask; /* rxorn int processing */
267 u_int8_t sc_defant; /* current default antenna */
268 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/
269 u_int64_t sc_lastrx; /* tsf at last rx'd frame */
270
271 struct ath_descdma sc_txdma; /* TX descriptors */
272 ath_bufhead sc_txbuf; /* transmit buffer */
273 struct mtx sc_txbuflock; /* txbuf lock */
274 char sc_txname[12]; /* e.g. "ath0_buf" */
275 int sc_tx_timer; /* transmit timeout */
276 u_int sc_txqsetup; /* h/w queues setup */
277 u_int sc_txintrperiod;/* tx interrupt batching */
278 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
279 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */
280 struct task sc_txtask; /* tx int processing */
281
282 struct ath_descdma sc_bdma; /* beacon descriptors */
283 ath_bufhead sc_bbuf; /* beacon buffers */
284 u_int sc_bhalq; /* HAL q for outgoing beacons */
285 u_int sc_bmisscount; /* missed beacon transmits */
286 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */
287 struct ath_txq *sc_cabq; /* tx q for cab frames */
288 struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */
289 struct task sc_bmisstask; /* bmiss int processing */
290 struct task sc_bstucktask; /* stuck beacon processing */
291 enum {
292 OK, /* no change needed */
293 UPDATE, /* update pending */
294 COMMIT /* beacon sent, commit change */
295 } sc_updateslot; /* slot time update fsm */
296 struct ath_txq sc_mcastq; /* mcast xmits w/ ps sta's */
297
298 struct callout sc_cal_ch; /* callout handle for cals */
299 int sc_calinterval; /* current polling interval */
300 int sc_caltries; /* cals at current interval */
301 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */
302 struct callout sc_scan_ch; /* callout handle for scan */
303 struct callout sc_dfs_ch; /* callout handle for dfs */
304 };
305 #define sc_tx_th u_tx_rt.th
306 #define sc_rx_th u_rx_rt.th
307
308 #define ATH_LOCK_INIT(_sc) \
309 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
310 NULL, MTX_DEF | MTX_RECURSE)
311 #define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
312 #define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
313 #define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
314 #define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
315
316 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
317
318 #define ATH_TXBUF_LOCK_INIT(_sc) do { \
319 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \
320 device_get_nameunit((_sc)->sc_dev)); \
321 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \
322 } while (0)
323 #define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock)
324 #define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock)
325 #define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock)
326 #define ATH_TXBUF_LOCK_ASSERT(_sc) \
327 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED)
328
329 int ath_attach(u_int16_t, struct ath_softc *);
330 int ath_detach(struct ath_softc *);
331 void ath_resume(struct ath_softc *);
332 void ath_suspend(struct ath_softc *);
333 void ath_shutdown(struct ath_softc *);
334 void ath_intr(void *);
335
336 /*
337 * HAL definitions to comply with local coding convention.
338 */
339 #define ath_hal_detach(_ah) \
340 ((*(_ah)->ah_detach)((_ah)))
341 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \
342 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
343 #define ath_hal_getratetable(_ah, _mode) \
344 ((*(_ah)->ah_getRateTable)((_ah), (_mode)))
345 #define ath_hal_getmac(_ah, _mac) \
346 ((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
347 #define ath_hal_setmac(_ah, _mac) \
348 ((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
349 #define ath_hal_intrset(_ah, _mask) \
350 ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
351 #define ath_hal_intrget(_ah) \
352 ((*(_ah)->ah_getInterrupts)((_ah)))
353 #define ath_hal_intrpend(_ah) \
354 ((*(_ah)->ah_isInterruptPending)((_ah)))
355 #define ath_hal_getisr(_ah, _pmask) \
356 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
357 #define ath_hal_updatetxtriglevel(_ah, _inc) \
358 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
359 #define ath_hal_setpower(_ah, _mode) \
360 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE))
361 #define ath_hal_keycachesize(_ah) \
362 ((*(_ah)->ah_getKeyCacheSize)((_ah)))
363 #define ath_hal_keyreset(_ah, _ix) \
364 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
365 #define ath_hal_keyset(_ah, _ix, _pk, _mac) \
366 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
367 #define ath_hal_keyisvalid(_ah, _ix) \
368 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
369 #define ath_hal_keysetmac(_ah, _ix, _mac) \
370 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
371 #define ath_hal_getrxfilter(_ah) \
372 ((*(_ah)->ah_getRxFilter)((_ah)))
373 #define ath_hal_setrxfilter(_ah, _filter) \
374 ((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
375 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \
376 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
377 #define ath_hal_waitforbeacon(_ah, _bf) \
378 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
379 #define ath_hal_putrxbuf(_ah, _bufaddr) \
380 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr)))
381 #define ath_hal_gettsf32(_ah) \
382 ((*(_ah)->ah_getTsf32)((_ah)))
383 #define ath_hal_gettsf64(_ah) \
384 ((*(_ah)->ah_getTsf64)((_ah)))
385 #define ath_hal_resettsf(_ah) \
386 ((*(_ah)->ah_resetTsf)((_ah)))
387 #define ath_hal_rxena(_ah) \
388 ((*(_ah)->ah_enableReceive)((_ah)))
389 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \
390 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
391 #define ath_hal_gettxbuf(_ah, _q) \
392 ((*(_ah)->ah_getTxDP)((_ah), (_q)))
393 #define ath_hal_numtxpending(_ah, _q) \
394 ((*(_ah)->ah_numTxPending)((_ah), (_q)))
395 #define ath_hal_getrxbuf(_ah) \
396 ((*(_ah)->ah_getRxDP)((_ah)))
397 #define ath_hal_txstart(_ah, _q) \
398 ((*(_ah)->ah_startTxDma)((_ah), (_q)))
399 #define ath_hal_setchannel(_ah, _chan) \
400 ((*(_ah)->ah_setChannel)((_ah), (_chan)))
401 #define ath_hal_calibrate(_ah, _chan, _iqcal) \
402 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal)))
403 #define ath_hal_setledstate(_ah, _state) \
404 ((*(_ah)->ah_setLedState)((_ah), (_state)))
405 #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \
406 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
407 #define ath_hal_beaconreset(_ah) \
408 ((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
409 #define ath_hal_beacontimers(_ah, _bs) \
410 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs)))
411 #define ath_hal_setassocid(_ah, _bss, _associd) \
412 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
413 #define ath_hal_phydisable(_ah) \
414 ((*(_ah)->ah_phyDisable)((_ah)))
415 #define ath_hal_setopmode(_ah) \
416 ((*(_ah)->ah_setPCUConfig)((_ah)))
417 #define ath_hal_stoptxdma(_ah, _qnum) \
418 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
419 #define ath_hal_stoppcurecv(_ah) \
420 ((*(_ah)->ah_stopPcuReceive)((_ah)))
421 #define ath_hal_startpcurecv(_ah) \
422 ((*(_ah)->ah_startPcuReceive)((_ah)))
423 #define ath_hal_stopdmarecv(_ah) \
424 ((*(_ah)->ah_stopDmaReceive)((_ah)))
425 #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
426 ((*(_ah)->ah_getDiagState)((_ah), (_id), \
427 (_indata), (_insize), (_outdata), (_outsize)))
428 #define ath_hal_getfatalstate(_ah, _outdata, _outsize) \
429 ath_hal_getdiagstate(_ah, 29, NULL, 0, (void **)(_outdata), _outsize)
430 #define ath_hal_setuptxqueue(_ah, _type, _irq) \
431 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
432 #define ath_hal_resettxqueue(_ah, _q) \
433 ((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
434 #define ath_hal_releasetxqueue(_ah, _q) \
435 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
436 #define ath_hal_gettxqueueprops(_ah, _q, _qi) \
437 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
438 #define ath_hal_settxqueueprops(_ah, _q, _qi) \
439 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
440 #define ath_hal_getrfgain(_ah) \
441 ((*(_ah)->ah_getRfGain)((_ah)))
442 #define ath_hal_getdefantenna(_ah) \
443 ((*(_ah)->ah_getDefAntenna)((_ah)))
444 #define ath_hal_setdefantenna(_ah, _ant) \
445 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant)))
446 #define ath_hal_rxmonitor(_ah, _arg, _chan) \
447 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan)))
448 #define ath_hal_mibevent(_ah, _stats) \
449 ((*(_ah)->ah_procMibEvent)((_ah), (_stats)))
450 #define ath_hal_setslottime(_ah, _us) \
451 ((*(_ah)->ah_setSlotTime)((_ah), (_us)))
452 #define ath_hal_getslottime(_ah) \
453 ((*(_ah)->ah_getSlotTime)((_ah)))
454 #define ath_hal_setacktimeout(_ah, _us) \
455 ((*(_ah)->ah_setAckTimeout)((_ah), (_us)))
456 #define ath_hal_getacktimeout(_ah) \
457 ((*(_ah)->ah_getAckTimeout)((_ah)))
458 #define ath_hal_setctstimeout(_ah, _us) \
459 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us)))
460 #define ath_hal_getctstimeout(_ah) \
461 ((*(_ah)->ah_getCTSTimeout)((_ah)))
462 #define ath_hal_getcapability(_ah, _cap, _param, _result) \
463 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
464 #define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \
465 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status)))
466 #define ath_hal_ciphersupported(_ah, _cipher) \
467 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
468 #define ath_hal_getregdomain(_ah, _prd) \
469 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK)
470 #define ath_hal_setregdomain(_ah, _rd) \
471 ((*(_ah)->ah_setRegulatoryDomain)((_ah), (_rd), NULL))
472 #define ath_hal_getcountrycode(_ah, _pcc) \
473 (*(_pcc) = (_ah)->ah_countryCode)
474 #define ath_hal_hastkipsplit(_ah) \
475 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
476 #define ath_hal_gettkipsplit(_ah) \
477 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK)
478 #define ath_hal_settkipsplit(_ah, _v) \
479 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL)
480 #define ath_hal_hwphycounters(_ah) \
481 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK)
482 #define ath_hal_hasdiversity(_ah) \
483 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK)
484 #define ath_hal_getdiversity(_ah) \
485 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK)
486 #define ath_hal_setdiversity(_ah, _v) \
487 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL)
488 #define ath_hal_getantennaswitch(_ah) \
489 ((*(_ah)->ah_getAntennaSwitch)((_ah)))
490 #define ath_hal_setantennaswitch(_ah, _v) \
491 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v)))
492 #define ath_hal_getdiag(_ah, _pv) \
493 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK)
494 #define ath_hal_setdiag(_ah, _v) \
495 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL)
496 #define ath_hal_getnumtxqueues(_ah, _pv) \
497 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK)
498 #define ath_hal_hasveol(_ah) \
499 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK)
500 #define ath_hal_hastxpowlimit(_ah) \
501 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK)
502 #define ath_hal_settxpowlimit(_ah, _pow) \
503 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow)))
504 #define ath_hal_gettxpowlimit(_ah, _ppow) \
505 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK)
506 #define ath_hal_getmaxtxpow(_ah, _ppow) \
507 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK)
508 #define ath_hal_gettpscale(_ah, _scale) \
509 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK)
510 #define ath_hal_settpscale(_ah, _v) \
511 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL)
512 #define ath_hal_hastpc(_ah) \
513 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK)
514 #define ath_hal_gettpc(_ah) \
515 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK)
516 #define ath_hal_settpc(_ah, _v) \
517 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL)
518 #define ath_hal_hasbursting(_ah) \
519 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK)
520 #ifdef notyet
521 #define ath_hal_hasmcastkeysearch(_ah) \
522 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK)
523 #define ath_hal_getmcastkeysearch(_ah) \
524 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK)
525 #else
526 #define ath_hal_getmcastkeysearch(_ah) 0
527 #endif
528 #define ath_hal_hasrfsilent(_ah) \
529 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK)
530 #define ath_hal_getrfkill(_ah) \
531 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK)
532 #define ath_hal_setrfkill(_ah, _onoff) \
533 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL)
534 #define ath_hal_getrfsilent(_ah, _prfsilent) \
535 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK)
536 #define ath_hal_setrfsilent(_ah, _rfsilent) \
537 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL)
538 #define ath_hal_gettpack(_ah, _ptpack) \
539 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK)
540 #define ath_hal_settpack(_ah, _tpack) \
541 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL)
542 #define ath_hal_gettpcts(_ah, _ptpcts) \
543 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK)
544 #define ath_hal_settpcts(_ah, _tpcts) \
545 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL)
546 #if HAL_ABI_VERSION < 0x05120700
547 #define ath_hal_process_noisefloor(_ah)
548 #define ath_hal_getchannoise(_ah, _c) (-96)
549 #define HAL_CAP_TPC_ACK 100
550 #define HAL_CAP_TPC_CTS 101
551 #else
552 #define ath_hal_getchannoise(_ah, _c) \
553 ((*(_ah)->ah_getChanNoise)((_ah), (_c)))
554 #endif
555 #if HAL_ABI_VERSION < 0x05122200
556 #define HAL_TXQ_TXOKINT_ENABLE TXQ_FLAG_TXOKINT_ENABLE
557 #define HAL_TXQ_TXERRINT_ENABLE TXQ_FLAG_TXERRINT_ENABLE
558 #define HAL_TXQ_TXDESCINT_ENABLE TXQ_FLAG_TXDESCINT_ENABLE
559 #define HAL_TXQ_TXEOLINT_ENABLE TXQ_FLAG_TXEOLINT_ENABLE
560 #define HAL_TXQ_TXURNINT_ENABLE TXQ_FLAG_TXURNINT_ENABLE
561 #endif
562 #if HAL_ABI_VERSION < 0x06102501
563 #define ath_hal_ispublicsafetysku(ah) \
564 (((ah)->ah_regdomain == 0 && (ah)->ah_countryCode == 842) || \
565 (ah)->ah_regdomain == 0x12)
566 #endif
567 #if HAL_ABI_VERSION < 0x06122400
568 /* XXX yech, can't get to regdomain so just hack a compat shim */
569 #define ath_hal_isgsmsku(ah) \
570 ((ah)->ah_countryCode == 843)
571 #endif
572
573 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
574 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
575 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \
576 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs)))
577 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
578 _txr0, _txtr0, _keyix, _ant, _flags, \
579 _rtsrate, _rtsdura) \
580 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
581 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
582 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0))
583 #define ath_hal_setupxtxdesc(_ah, _ds, \
584 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
585 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
586 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
587 #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \
588 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0)))
589 #define ath_hal_txprocdesc(_ah, _ds, _ts) \
590 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts)))
591 #define ath_hal_gettxintrtxqs(_ah, _txqs) \
592 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs)))
593
594 #define ath_hal_gpioCfgOutput(_ah, _gpio) \
595 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio)))
596 #define ath_hal_gpioset(_ah, _gpio, _b) \
597 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
598 #define ath_hal_gpioget(_ah, _gpio) \
599 ((*(_ah)->ah_gpioGet)((_ah), (_gpio)))
600 #define ath_hal_gpiosetintr(_ah, _gpio, _b) \
601 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b)))
602
603 #define ath_hal_radar_wait(_ah, _chan) \
604 ((*(_ah)->ah_radarWait)((_ah), (_chan)))
605
606 #endif /* _DEV_ATH_ATHVAR_H */
Cache object: 7ac4aca4c1da2c43f29958e22e92433f
|