1 /* $NetBSD: midwayreg.h,v 1.6 1997/03/20 21:34:47 chuck Exp $ */
2 /* $DragonFly: src/sys/dev/atm/en/midwayreg.h,v 1.3 2005/02/01 00:51:49 joerg Exp $ */
3
4 /*
5 * m i d w a y r e g . h
6 *
7 * this file contains the description of the ENI ATM midway chip
8 * data structures. see midway.c for more details.
9 *
10 */
11
12 typedef u_int32_t pci_chipset_tag_t;
13
14 #define MID_SZTOB(X) ((X) * 256 * 4) /* size to bytes */
15 #define MID_BTOSZ(X) ((X) / 256 / 4) /* bytes to "size" */
16
17 #define MID_N_VC 1024 /* # of VCs we can use */
18 #define MID_NTX_CH 8 /* 8 transmit channels (shared) */
19 #define MID_ATMDATASZ 48 /* need data in 48 byte blocks */
20
21 /*
22 * card data structures, top down
23 *
24 * in order to have a portable driver, the netbsd guys will not let us
25 * use structs. we have a bus_space_handle_t which is the en_base address.
26 * everything else is an offset from that base. all card data must be
27 * accessed with bus_space_read_4()/bus_space_write_4():
28 *
29 * rv = bus_space_read_4(sc->en_memt, sc->en_base, BYTE_OFFSET);
30 * bus_space_write_4(sc->en_memt, sc->en_base, BYTE_OFFSET, VALUE);
31 *
32 * en_card: the whole card (prom + phy + midway + obmem)
33 * obmem contains: vci tab + dma queues (rx & tx) + service list + bufs
34 */
35
36 /* byte offsets from en_base of various items */
37 #define MID_PHYOFF 0x030000 /* PHY offset */
38 #define MID_MIDOFF 0x040000 /* midway regs offset */
39 #define MID_RAMOFF 0x200000 /* RAM offset */
40 #define MID_DRQOFF 0x204000 /* DRQ offset */
41 #define MID_DRQEND MID_DTQOFF /* DRQ end */
42 #define MID_DTQOFF 0x205000 /* DTQ offset */
43 #define MID_DTQEND MID_SLOFF /* DTQ end */
44 #define MID_SLOFF 0x206000 /* service list */
45 #define MID_SLEND MID_BUFOFF /* service list end */
46 #define MID_BUFOFF 0x207000 /* buffer area */
47 #define MID_PROBEOFF 0x21fffc /* start probe here */
48 #define MID_PROBSIZE 0x020000 /* 128 KB */
49 #define MID_MAXOFF 0x3ffffc /* max offset */
50
51 /*
52 * prom & phy: not defined here
53 */
54 #define MID_ADPMACOFF 0xffc0 /* mac address offset (adaptec only) */
55
56 /*
57 * midway regs (byte offsets from en_base)
58 */
59
60 #define MID_RESID 0x40000 /* write=reset reg, read=ID reg */
61
62 #define MID_VER(X) (((X) & 0xf0000000) >> 28) /* midway version # */
63 #define MID_MID(X) (((X) & 0x700) >> 8) /* motherboard ID */
64 #define MID_IS_SABRE(X) ((X) & 0x80) /* sabre controller? */
65 #define MID_IS_SUNI(X) ((X) & 0x40) /* SUNI? vs utopia */
66 #define MID_IS_UPIPE(X) ((X) & 0x20) /* utopia pipeline? */
67 #define MID_DID(X) ((X) & 0x1f) /* daughterboard ID */
68
69 #define MID_INTACK 0x40004 /* interrupt ACK */
70 #define MID_INTSTAT 0x40008 /* interrupt status */
71 #define MID_INTENA 0x4000c /* interrupt enable */
72
73 #define MID_TXCHAN(N) (1 << ((N) + 9)) /* ack/status/enable xmit channel bit*/
74 #define MID_INT_TX 0x1fe00 /* mask for any xmit interrupt */
75 #define MID_INT_DMA_OVR 0x00100 /* DMA overflow interrupt */
76 #define MID_INT_IDENT 0x00080 /* ident match error interrupt */
77 #define MID_INT_LERR 0x00040 /* LERR interrupt (sbus?) */
78 #define MID_INT_DMA_ERR 0x00020 /* DMA error interrupt */
79 #define MID_INT_DMA_RX 0x00010 /* DMA recv interrupt */
80 #define MID_INT_DMA_TX 0x00008 /* DMA xmit interrupt */
81 #define MID_INT_SERVICE 0x00004 /* service list interrupt */
82 #define MID_INT_SUNI 0x00002 /* SUNI interrupt */
83 #define MID_INT_STATS 0x00001 /* stats overflow interrupt */
84
85 #define MID_INT_ANY 0x1ffff /* any interrupt? */
86
87 #define MID_INTBITS "\2\21T7\20T6\17T5\16T4\15T3\14T2\13T1\12T0\11DMAOVR\10ID\7LERR\6DMAERR\5RXDMA\4TXDMA\3SERV\2SUNI\1STAT"
88
89 #define MID_MAST_CSR 0x40010 /* master CSR */
90
91 #define MID_IPL(X) (((X) & 0x1c0) >> 6) /* IPL */
92 #define MID_SETIPL(I) ((I) << 6)
93 #define MID_MCSR_TXLOCK 0x20 /* lock on xmit overflow mode */
94 /* NOTE: next 5 bits: write 1 means enable, write 0 means no change */
95 #define MID_MCSR_ENDMA 0x10 /* DMA enable */
96 #define MID_MCSR_ENTX 0x08 /* TX enable */
97 #define MID_MCSR_ENRX 0x04 /* RX enable */
98 #define MID_MCSR_W1MS 0x02 /* wait 1 msec */
99 #define MID_MCSR_W500US 0x01 /* wait 500 usec */
100
101 #define MID_MCSRBITS "\2\6LCK\5DMAON\4TXON\3RXON\2W1MS\1W500US"
102
103 #define MID_STAT 0x40014 /* stat register, clear on read */
104
105 #define MID_VTRASH(X) (((X) >> 16) & 0xffff)
106 /* # cells trashed due to VCI's mode */
107 #define MID_OTRASH(X) ((X) & 0xffff) /* # cells trashed due to overflow */
108
109 #define MID_SERV_WRITE 0x40018 /* 10 bit service write pointer (r/o) */
110 #define MID_DMA_ADDR 0x4001c /* VA of DMA (r/o) */
111
112 /* DMA queue pointers (bits 0 to 8) */
113 #define MID_DMA_WRRX 0x40020 /* write ptr. for DMA recv queue */
114 /* (for adaptor -> host xfers) */
115 #define MID_DMA_RDRX 0x40024 /* read ptr for DMA recv queue (r/o) */
116 /* (i.e. current adaptor->host xfer) */
117 #define MID_DMA_WRTX 0x40028 /* write ptr for DMA xmit queue */
118 /* (for host -> adaptor xfers) */
119 #define MID_DMA_RDTX 0x4002c /* read ptr for DMA xmit queue (r/o) */
120 /* (i.e. current host->adaptor xfer) */
121
122 /* xmit channel regs (1 per channel, MID_NTX_CH max channels) */
123
124 #define MIDX_PLACE(N) (0x40040+((N)*0x10)) /* xmit place */
125
126 #define MIDX_MKPLACE(SZ,LOC) ( ((SZ) << 11) | (LOC) )
127 #define MIDX_LOC(X) ((X) & 0x7ff) /* location in obmem */
128 #define MIDX_SZ(X) ((X) >> 11) /* (size of block / 256) in int32_t's*/
129 #define MIDX_BASE(X) \
130 (((MIDX_LOC(X) << MIDV_LOCTOPSHFT) * sizeof(u_int32_t)) + MID_RAMOFF)
131
132 /* the following two regs are word offsets in the block */
133 #define MIDX_READPTR(N) (0x40044+((N)*0x10)) /* xmit read pointer (r/o) */
134 #define MIDX_DESCSTART(N) (0x40048+((N)*0x10)) /* seg currently in DMA (r/o) */
135
136
137 /*
138 * obmem items
139 */
140
141 /*
142 * vci table in obmem (offset from MID_VCTOFF)
143 */
144
145 #define MID_VC(N) (MID_RAMOFF+((N)*0x10))
146
147 #define MIDV_TRASH 0x00000000 /* ignore VC */
148 #define MIDV_AAL5 0x80000000 /* do AAL5 on it */
149 #define MIDV_NOAAL 0x40000000 /* do per-cell stuff on it */
150 #define MIDV_MASK 0xc0000000 /* mode mask */
151 #define MIDV_SETMODE(VC,M) (((VC) & ~(MIDV_MASK)) | (M)) /* new mode */
152 #define MIDV_PTI 0x20000000 /* save PTI cells? */
153 #define MIDV_LOCTOPSHFT 8 /* shift to get top 11 bits of 19 */
154 #define MIDV_LOCSHIFT 18
155 #define MIDV_LOCMASK 0x7ff
156 #define MIDV_LOC(X) (((X) >> MIDV_LOCSHIFT) & MIDV_LOCMASK)
157 /* 11 most sig bits of addr */
158 #define MIDV_SZSHIFT 15
159 #define MIDV_SZ(X) (((X) >> MIDV_SZSHIFT) & 7)
160 /* size encoded the usual way */
161 #define MIDV_INSERVICE 0x1 /* in service list */
162
163 #define MID_DST_RP(N) (MID_VC(N)|0x4)
164
165 #define MIDV_DSTART_SHIFT 16 /* shift */
166 #define MIDV_DSTART(X) (((X) >> MIDV_DSTART_SHIFT) & 0x7fff)
167 #define MIDV_READP_MASK 0x7fff /* valid bits, (shift = 0) */
168
169 #define MID_WP_ST_CNT(N) (MID_VC(N)|0x8) /* write pointer/state/count */
170
171 #define MIDV_WRITEP_MASK 0x7fff0000 /* mask for write ptr. */
172 #define MIDV_WRITEP_SHIFT 16
173 #define MIDV_ST_IDLE 0x0000
174 #define MIDV_ST_TRASH 0xc000
175 #define MIDV_ST_REASS 0x4000
176 #define MIDV_CCOUNT 0x7ff /* cell count */
177
178 #define MID_CRC(N) (MID_VC(N)|0xc) /* CRC */
179
180 /*
181 * dma recv q.
182 */
183
184 #define MID_DMA_END (1 << 5) /* for both tx and rx */
185 #define MID_DMA_CNT(X) (((X) >> 16) & 0xffff)
186 #define MID_DMA_TXCHAN(X) (((X) >> 6) & 0x7)
187 #define MID_DMA_RXVCI(X) (((X) >> 6) & 0x3ff)
188 #define MID_DMA_TYPE(X) ((X) & 0xf)
189
190 #define MID_DRQ_N 512 /* # of descriptors */
191 #define MID_DRQ_A2REG(N) (((N) - MID_DRQOFF) >> 3)
192 /* convert byte offset to reg value */
193 #define MID_DRQ_REG2A(N) (((N) << 3) + MID_DRQOFF) /* and back */
194
195 /* note: format of word 1 of RXQ is different beween ENI and ADP cards */
196 #define MID_MK_RXQ_ENI(CNT,VC,END,TYPE) \
197 ( ((CNT) << 16)|((VC) << 6)|(END)|(TYPE) )
198
199 #define MID_MK_RXQ_ADP(CNT,VC,END,JK) \
200 ( ((CNT) << 12)|((VC) << 2)|((END) >> 4)|(((JK) != 0) ? 1 : 0))
201 /*
202 * dma xmit q.
203 */
204
205 #define MID_DTQ_N 512 /* # of descriptors */
206 #define MID_DTQ_A2REG(N) (((N) - MID_DTQOFF) >> 3)
207 /* convert byte offset to reg value */
208 #define MID_DTQ_REG2A(N) (((N) << 3) + MID_DTQOFF) /* and back */
209
210
211 /* note: format of word 1 of TXQ is different beween ENI and ADP cards */
212 #define MID_MK_TXQ_ENI(CNT,CHN,END,TYPE) \
213 ( ((CNT) << 16)|((CHN) << 6)|(END)|(TYPE) )
214
215 #define MID_MK_TXQ_ADP(CNT,CHN,END,JK) \
216 ( ((CNT) << 12)|((CHN) << 2)|((END) >> 4)|(((JK) != 0) ? 1 : 0) )
217
218 /*
219 * dma types
220 */
221
222 #define MIDDMA_JK 0x3 /* just kidding */
223 #define MIDDMA_BYTE 0x1 /* byte */
224 #define MIDDMA_2BYTE 0x2 /* 2 bytes */
225 #define MIDDMA_WORD 0x0 /* word */
226 #define MIDDMA_2WORD 0x7 /* 2 words */
227 #define MIDDMA_4WORD 0x4 /* 4 words */
228 #define MIDDMA_8WORD 0x5 /* 8 words */
229 #define MIDDMA_16WORD 0x6 /* 16 words!!! */
230 #define MIDDMA_2WMAYBE 0xf /* 2 words, maybe */
231 #define MIDDMA_4WMAYBE 0xc /* 4 words, maybe */
232 #define MIDDMA_8WMAYBE 0xd /* 8 words, maybe */
233 #define MIDDMA_16WMAYBE 0xe /* 16 words, maybe */
234
235 #define MIDDMA_MAYBE 0xc /* mask to detect WMAYBE dma code */
236 #define MIDDMA_MAXBURST (16 * sizeof(u_int32_t)) /* largest burst */
237
238 /*
239 * service list
240 */
241
242 #define MID_SL_N 1024 /* max # entries on slist */
243 #define MID_SL_A2REG(N) (((N) - MID_SLOFF) >> 2)
244 /* convert byte offset to reg value */
245 #define MID_SL_REG2A(N) (((N) << 2) + MID_SLOFF) /* and back */
246
247 /*
248 * data in the buffer area of obmem
249 */
250
251 /*
252 * recv buffer desc. (1 u_int32_t at start of buffer)
253 */
254
255 #define MID_RBD_SIZE 4 /* RBD size */
256 #define MID_CHDR_SIZE 4 /* on aal0, cell header size */
257 #define MID_RBD_ID(X) ((X) & 0xfe000000) /* get ID */
258 #define MID_RBD_STDID 0x36000000 /* standard ID */
259 #define MID_RBD_CLP 0x01000000 /* CLP: cell loss priority */
260 #define MID_RBD_CE 0x00010000 /* CE: congestion experienced */
261 #define MID_RBD_T 0x00001000 /* T: trashed due to overflow */
262 #define MID_RBD_CRCERR 0x00000800 /* CRC error */
263 #define MID_RBD_CNT(X) ((X) & 0x7ff) /* cell count */
264
265 /*
266 * xmit buffer desc. (2 u_int32_t's at start of buffer)
267 * (note we treat the PR & RATE as a single u_int8_t)
268 */
269
270 #define MID_TBD_SIZE 8
271 #define MID_TBD_MK1(AAL,PR_RATE,CNT) \
272 (MID_TBD_STDID|(AAL)|((PR_RATE) << 19)|(CNT))
273 #define MID_TBD_STDID 0xb0000000 /* standard ID */
274 #define MID_TBD_AAL5 0x08000000 /* AAL 5 */
275 #define MID_TBD_NOAAL5 0x00000000 /* not AAL 5 */
276
277 #define MID_TBD_MK2(VCI,PTI,CLP) \
278 (((VCI) << 4)|((PTI) << 1)|(CLP))
279
280 /*
281 * aal5 pdu tail, last 2 words of last cell of AAL5 frame
282 * (word 2 is CRC .. handled by hw)
283 */
284
285 #define MID_PDU_SIZE 8
286 #define MID_PDU_MK1(UU,CPI,LEN) \
287 (((UU) << 24)|((CPI) << 16)|(LEN))
288 #define MID_PDU_LEN(X) ((X) & 0xffff)
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