Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/bce/if_bce.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006-2014 QLogic Corporation 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * The following controllers are supported by this driver: 34 * BCM5706C A2, A3 35 * BCM5706S A2, A3 36 * BCM5708C B1, B2 37 * BCM5708S B1, B2 38 * BCM5709C A1, C0 39 * BCM5709S A1, C0 40 * BCM5716C C0 41 * BCM5716S C0 42 * 43 * The following controllers are not supported by this driver: 44 * BCM5706C A0, A1 (pre-production) 45 * BCM5706S A0, A1 (pre-production) 46 * BCM5708C A0, B0 (pre-production) 47 * BCM5708S A0, B0 (pre-production) 48 * BCM5709C A0 B0, B1, B2 (pre-production) 49 * BCM5709S A0, B0, B1, B2 (pre-production) 50 */ 51 52 #include "opt_bce.h" 53 54 #include <sys/param.h> 55 #include <sys/endian.h> 56 #include <sys/systm.h> 57 #include <sys/sockio.h> 58 #include <sys/lock.h> 59 #include <sys/mbuf.h> 60 #include <sys/malloc.h> 61 #include <sys/mutex.h> 62 #include <sys/kernel.h> 63 #include <sys/module.h> 64 #include <sys/socket.h> 65 #include <sys/sysctl.h> 66 #include <sys/queue.h> 67 68 #include <net/bpf.h> 69 #include <net/ethernet.h> 70 #include <net/if.h> 71 #include <net/if_var.h> 72 #include <net/if_arp.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 76 #include <net/if_types.h> 77 #include <net/if_vlan_var.h> 78 79 #include <netinet/in_systm.h> 80 #include <netinet/in.h> 81 #include <netinet/if_ether.h> 82 #include <netinet/ip.h> 83 #include <netinet/ip6.h> 84 #include <netinet/tcp.h> 85 #include <netinet/udp.h> 86 87 #include <machine/bus.h> 88 #include <machine/resource.h> 89 #include <sys/bus.h> 90 #include <sys/rman.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 #include "miidevs.h" 95 #include <dev/mii/brgphyreg.h> 96 97 #include <dev/pci/pcireg.h> 98 #include <dev/pci/pcivar.h> 99 100 #include "miibus_if.h" 101 102 #include <dev/bce/if_bcereg.h> 103 #include <dev/bce/if_bcefw.h> 104 105 /****************************************************************************/ 106 /* BCE Debug Options */ 107 /****************************************************************************/ 108 #ifdef BCE_DEBUG 109 u32 bce_debug = BCE_WARN; 110 111 /* 0 = Never */ 112 /* 1 = 1 in 2,147,483,648 */ 113 /* 256 = 1 in 8,388,608 */ 114 /* 2048 = 1 in 1,048,576 */ 115 /* 65536 = 1 in 32,768 */ 116 /* 1048576 = 1 in 2,048 */ 117 /* 268435456 = 1 in 8 */ 118 /* 536870912 = 1 in 4 */ 119 /* 1073741824 = 1 in 2 */ 120 121 /* Controls how often the l2_fhdr frame error check will fail. */ 122 int l2fhdr_error_sim_control = 0; 123 124 /* Controls how often the unexpected attention check will fail. */ 125 int unexpected_attention_sim_control = 0; 126 127 /* Controls how often to simulate an mbuf allocation failure. */ 128 int mbuf_alloc_failed_sim_control = 0; 129 130 /* Controls how often to simulate a DMA mapping failure. */ 131 int dma_map_addr_failed_sim_control = 0; 132 133 /* Controls how often to simulate a bootcode failure. */ 134 int bootcode_running_failure_sim_control = 0; 135 #endif 136 137 /****************************************************************************/ 138 /* PCI Device ID Table */ 139 /* */ 140 /* Used by bce_probe() to identify the devices supported by this driver. */ 141 /****************************************************************************/ 142 #define BCE_DEVDESC_MAX 64 143 144 static const struct bce_type bce_devs[] = { 145 /* BCM5706C Controllers and OEM boards. */ 146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 147 "HP NC370T Multifunction Gigabit Server Adapter" }, 148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 149 "HP NC370i Multifunction Gigabit Server Adapter" }, 150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070, 151 "HP NC380T PCIe DP Multifunc Gig Server Adapter" }, 152 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709, 153 "HP NC371i Multifunction Gigabit Server Adapter" }, 154 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 155 "QLogic NetXtreme II BCM5706 1000Base-T" }, 156 157 /* BCM5706S controllers and OEM boards. */ 158 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 159 "HP NC370F Multifunction Gigabit Server Adapter" }, 160 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 161 "QLogic NetXtreme II BCM5706 1000Base-SX" }, 162 163 /* BCM5708C controllers and OEM boards. */ 164 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037, 165 "HP NC373T PCIe Multifunction Gig Server Adapter" }, 166 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038, 167 "HP NC373i Multifunction Gigabit Server Adapter" }, 168 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045, 169 "HP NC374m PCIe Multifunction Adapter" }, 170 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 171 "QLogic NetXtreme II BCM5708 1000Base-T" }, 172 173 /* BCM5708S controllers and OEM boards. */ 174 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706, 175 "HP NC373m Multifunction Gigabit Server Adapter" }, 176 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b, 177 "HP NC373i Multifunction Gigabit Server Adapter" }, 178 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d, 179 "HP NC373F PCIe Multifunc Giga Server Adapter" }, 180 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 181 "QLogic NetXtreme II BCM5708 1000Base-SX" }, 182 183 /* BCM5709C controllers and OEM boards. */ 184 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055, 185 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 186 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059, 187 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" }, 188 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID, 189 "QLogic NetXtreme II BCM5709 1000Base-T" }, 190 191 /* BCM5709S controllers and OEM boards. */ 192 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d, 193 "HP NC382m DP 1GbE Multifunction BL-c Adapter" }, 194 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056, 195 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 196 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID, 197 "QLogic NetXtreme II BCM5709 1000Base-SX" }, 198 199 /* BCM5716 controllers and OEM boards. */ 200 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID, 201 "QLogic NetXtreme II BCM5716 1000Base-T" }, 202 { 0, 0, 0, 0, NULL } 203 }; 204 205 /****************************************************************************/ 206 /* Supported Flash NVRAM device data. */ 207 /****************************************************************************/ 208 static const struct flash_spec flash_table[] = 209 { 210 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE) 211 #define NONBUFFERED_FLAGS (BCE_NV_WREN) 212 213 /* Slow EEPROM */ 214 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 215 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 216 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 217 "EEPROM - slow"}, 218 /* Expansion entry 0001 */ 219 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 220 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 221 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 222 "Entry 0001"}, 223 /* Saifun SA25F010 (non-buffered flash) */ 224 /* strap, cfg1, & write1 need updates */ 225 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 226 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 227 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 228 "Non-buffered flash (128kB)"}, 229 /* Saifun SA25F020 (non-buffered flash) */ 230 /* strap, cfg1, & write1 need updates */ 231 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 232 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 233 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 234 "Non-buffered flash (256kB)"}, 235 /* Expansion entry 0100 */ 236 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 237 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 238 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 239 "Entry 0100"}, 240 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 241 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 242 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 243 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 244 "Entry 0101: ST M45PE10 (128kB non-buffered)"}, 245 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 246 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 247 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 248 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 249 "Entry 0110: ST M45PE20 (256kB non-buffered)"}, 250 /* Saifun SA25F005 (non-buffered flash) */ 251 /* strap, cfg1, & write1 need updates */ 252 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 253 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 254 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 255 "Non-buffered flash (64kB)"}, 256 /* Fast EEPROM */ 257 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 258 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 259 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 260 "EEPROM - fast"}, 261 /* Expansion entry 1001 */ 262 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 263 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 264 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 265 "Entry 1001"}, 266 /* Expansion entry 1010 */ 267 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 268 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 269 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 270 "Entry 1010"}, 271 /* ATMEL AT45DB011B (buffered flash) */ 272 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 273 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 274 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 275 "Buffered flash (128kB)"}, 276 /* Expansion entry 1100 */ 277 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 278 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 279 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 280 "Entry 1100"}, 281 /* Expansion entry 1101 */ 282 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 283 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 284 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 285 "Entry 1101"}, 286 /* Ateml Expansion entry 1110 */ 287 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 288 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 289 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 290 "Entry 1110 (Atmel)"}, 291 /* ATMEL AT45DB021B (buffered flash) */ 292 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 293 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 294 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 295 "Buffered flash (256kB)"}, 296 }; 297 298 /* 299 * The BCM5709 controllers transparently handle the 300 * differences between Atmel 264 byte pages and all 301 * flash devices which use 256 byte pages, so no 302 * logical-to-physical mapping is required in the 303 * driver. 304 */ 305 static const struct flash_spec flash_5709 = { 306 .flags = BCE_NV_BUFFERED, 307 .page_bits = BCM5709_FLASH_PAGE_BITS, 308 .page_size = BCM5709_FLASH_PAGE_SIZE, 309 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 310 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 311 .name = "5709/5716 buffered flash (256kB)", 312 }; 313 314 /****************************************************************************/ 315 /* FreeBSD device entry points. */ 316 /****************************************************************************/ 317 static int bce_probe (device_t); 318 static int bce_attach (device_t); 319 static int bce_detach (device_t); 320 static int bce_shutdown (device_t); 321 322 /****************************************************************************/ 323 /* BCE Debug Data Structure Dump Routines */ 324 /****************************************************************************/ 325 #ifdef BCE_DEBUG 326 static u32 bce_reg_rd (struct bce_softc *, u32); 327 static void bce_reg_wr (struct bce_softc *, u32, u32); 328 static void bce_reg_wr16 (struct bce_softc *, u32, u16); 329 static u32 bce_ctx_rd (struct bce_softc *, u32, u32); 330 static void bce_dump_enet (struct bce_softc *, struct mbuf *); 331 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 332 static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int); 333 static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int); 334 static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int); 335 static void bce_dump_txbd (struct bce_softc *, 336 int, struct tx_bd *); 337 static void bce_dump_rxbd (struct bce_softc *, 338 int, struct rx_bd *); 339 static void bce_dump_pgbd (struct bce_softc *, 340 int, struct rx_bd *); 341 static void bce_dump_l2fhdr (struct bce_softc *, 342 int, struct l2_fhdr *); 343 static void bce_dump_ctx (struct bce_softc *, u16); 344 static void bce_dump_ftqs (struct bce_softc *); 345 static void bce_dump_tx_chain (struct bce_softc *, u16, int); 346 static void bce_dump_rx_bd_chain (struct bce_softc *, u16, int); 347 static void bce_dump_pg_chain (struct bce_softc *, u16, int); 348 static void bce_dump_status_block (struct bce_softc *); 349 static void bce_dump_stats_block (struct bce_softc *); 350 static void bce_dump_driver_state (struct bce_softc *); 351 static void bce_dump_hw_state (struct bce_softc *); 352 static void bce_dump_shmem_state (struct bce_softc *); 353 static void bce_dump_mq_regs (struct bce_softc *); 354 static void bce_dump_bc_state (struct bce_softc *); 355 static void bce_dump_txp_state (struct bce_softc *, int); 356 static void bce_dump_rxp_state (struct bce_softc *, int); 357 static void bce_dump_tpat_state (struct bce_softc *, int); 358 static void bce_dump_cp_state (struct bce_softc *, int); 359 static void bce_dump_com_state (struct bce_softc *, int); 360 static void bce_dump_rv2p_state (struct bce_softc *); 361 static void bce_breakpoint (struct bce_softc *); 362 #endif /*BCE_DEBUG */ 363 364 /****************************************************************************/ 365 /* BCE Register/Memory Access Routines */ 366 /****************************************************************************/ 367 static u32 bce_reg_rd_ind (struct bce_softc *, u32); 368 static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 369 static void bce_shmem_wr (struct bce_softc *, u32, u32); 370 static u32 bce_shmem_rd (struct bce_softc *, u32); 371 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 372 static int bce_miibus_read_reg (device_t, int, int); 373 static int bce_miibus_write_reg (device_t, int, int, int); 374 static void bce_miibus_statchg (device_t); 375 376 #ifdef BCE_DEBUG 377 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS); 378 #ifdef BCE_NVRAM_WRITE_SUPPORT 379 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS); 380 #endif 381 #endif 382 383 /****************************************************************************/ 384 /* BCE NVRAM Access Routines */ 385 /****************************************************************************/ 386 static int bce_acquire_nvram_lock (struct bce_softc *); 387 static int bce_release_nvram_lock (struct bce_softc *); 388 static void bce_enable_nvram_access(struct bce_softc *); 389 static void bce_disable_nvram_access(struct bce_softc *); 390 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 391 static int bce_init_nvram (struct bce_softc *); 392 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 393 static int bce_nvram_test (struct bce_softc *); 394 #ifdef BCE_NVRAM_WRITE_SUPPORT 395 static int bce_enable_nvram_write (struct bce_softc *); 396 static void bce_disable_nvram_write(struct bce_softc *); 397 static int bce_nvram_erase_page (struct bce_softc *, u32); 398 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 399 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 400 #endif 401 402 /****************************************************************************/ 403 /* */ 404 /****************************************************************************/ 405 static void bce_get_rx_buffer_sizes(struct bce_softc *, int); 406 static void bce_get_media (struct bce_softc *); 407 static void bce_init_media (struct bce_softc *); 408 static u32 bce_get_rphy_link (struct bce_softc *); 409 static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 410 static int bce_dma_alloc (device_t); 411 static void bce_dma_free (struct bce_softc *); 412 static void bce_release_resources (struct bce_softc *); 413 414 /****************************************************************************/ 415 /* BCE Firmware Synchronization and Load */ 416 /****************************************************************************/ 417 static void bce_fw_cap_init (struct bce_softc *); 418 static int bce_fw_sync (struct bce_softc *, u32); 419 static void bce_load_rv2p_fw (struct bce_softc *, const u32 *, u32, 420 u32); 421 static void bce_load_cpu_fw (struct bce_softc *, 422 struct cpu_reg *, struct fw_info *); 423 static void bce_start_cpu (struct bce_softc *, struct cpu_reg *); 424 static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *); 425 static void bce_start_rxp_cpu (struct bce_softc *); 426 static void bce_init_rxp_cpu (struct bce_softc *); 427 static void bce_init_txp_cpu (struct bce_softc *); 428 static void bce_init_tpat_cpu (struct bce_softc *); 429 static void bce_init_cp_cpu (struct bce_softc *); 430 static void bce_init_com_cpu (struct bce_softc *); 431 static void bce_init_cpus (struct bce_softc *); 432 433 static void bce_print_adapter_info (struct bce_softc *); 434 static void bce_probe_pci_caps (device_t, struct bce_softc *); 435 static void bce_stop (struct bce_softc *); 436 static int bce_reset (struct bce_softc *, u32); 437 static int bce_chipinit (struct bce_softc *); 438 static int bce_blockinit (struct bce_softc *); 439 440 static int bce_init_tx_chain (struct bce_softc *); 441 static void bce_free_tx_chain (struct bce_softc *); 442 443 static int bce_get_rx_buf (struct bce_softc *, u16, u16, u32 *); 444 static int bce_init_rx_chain (struct bce_softc *); 445 static void bce_fill_rx_chain (struct bce_softc *); 446 static void bce_free_rx_chain (struct bce_softc *); 447 448 static int bce_get_pg_buf (struct bce_softc *, u16, u16); 449 static int bce_init_pg_chain (struct bce_softc *); 450 static void bce_fill_pg_chain (struct bce_softc *); 451 static void bce_free_pg_chain (struct bce_softc *); 452 453 static struct mbuf *bce_tso_setup (struct bce_softc *, 454 struct mbuf **, u16 *); 455 static int bce_tx_encap (struct bce_softc *, struct mbuf **); 456 static void bce_start_locked (struct ifnet *); 457 static void bce_start (struct ifnet *); 458 static int bce_ioctl (struct ifnet *, u_long, caddr_t); 459 static uint64_t bce_get_counter (struct ifnet *, ift_counter); 460 static void bce_watchdog (struct bce_softc *); 461 static int bce_ifmedia_upd (struct ifnet *); 462 static int bce_ifmedia_upd_locked (struct ifnet *); 463 static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 464 static void bce_ifmedia_sts_rphy (struct bce_softc *, struct ifmediareq *); 465 static void bce_init_locked (struct bce_softc *); 466 static void bce_init (void *); 467 static void bce_mgmt_init_locked (struct bce_softc *sc); 468 469 static int bce_init_ctx (struct bce_softc *); 470 static void bce_get_mac_addr (struct bce_softc *); 471 static void bce_set_mac_addr (struct bce_softc *); 472 static void bce_phy_intr (struct bce_softc *); 473 static inline u16 bce_get_hw_rx_cons (struct bce_softc *); 474 static void bce_rx_intr (struct bce_softc *); 475 static void bce_tx_intr (struct bce_softc *); 476 static void bce_disable_intr (struct bce_softc *); 477 static void bce_enable_intr (struct bce_softc *, int); 478 479 static void bce_intr (void *); 480 static void bce_set_rx_mode (struct bce_softc *); 481 static void bce_stats_update (struct bce_softc *); 482 static void bce_tick (void *); 483 static void bce_pulse (void *); 484 static void bce_add_sysctls (struct bce_softc *); 485 486 /****************************************************************************/ 487 /* FreeBSD device dispatch table. */ 488 /****************************************************************************/ 489 static device_method_t bce_methods[] = { 490 /* Device interface (device_if.h) */ 491 DEVMETHOD(device_probe, bce_probe), 492 DEVMETHOD(device_attach, bce_attach), 493 DEVMETHOD(device_detach, bce_detach), 494 DEVMETHOD(device_shutdown, bce_shutdown), 495 /* Supported by device interface but not used here. */ 496 /* DEVMETHOD(device_identify, bce_identify), */ 497 /* DEVMETHOD(device_suspend, bce_suspend), */ 498 /* DEVMETHOD(device_resume, bce_resume), */ 499 /* DEVMETHOD(device_quiesce, bce_quiesce), */ 500 501 /* MII interface (miibus_if.h) */ 502 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 503 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 504 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 505 /* Supported by MII interface but not used here. */ 506 /* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */ 507 /* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */ 508 509 DEVMETHOD_END 510 }; 511 512 static driver_t bce_driver = { 513 "bce", 514 bce_methods, 515 sizeof(struct bce_softc) 516 }; 517 518 MODULE_DEPEND(bce, pci, 1, 1, 1); 519 MODULE_DEPEND(bce, ether, 1, 1, 1); 520 MODULE_DEPEND(bce, miibus, 1, 1, 1); 521 522 DRIVER_MODULE(bce, pci, bce_driver, NULL, NULL); 523 DRIVER_MODULE(miibus, bce, miibus_driver, NULL, NULL); 524 MODULE_PNP_INFO("U16:vendor;U16:device;U16:#;U16:#;D:#", pci, bce, 525 bce_devs, nitems(bce_devs) - 1); 526 527 /****************************************************************************/ 528 /* Tunable device values */ 529 /****************************************************************************/ 530 static SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 531 "bce driver parameters"); 532 533 /* Allowable values are TRUE or FALSE */ 534 static int bce_verbose = TRUE; 535 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0, 536 "Verbose output enable/disable"); 537 538 /* Allowable values are TRUE or FALSE */ 539 static int bce_tso_enable = TRUE; 540 SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 541 "TSO Enable/Disable"); 542 543 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 544 /* ToDo: Add MSI-X support. */ 545 static int bce_msi_enable = 1; 546 SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 547 "MSI-X|MSI|INTx selector"); 548 549 /* Allowable values are 1, 2, 4, 8. */ 550 static int bce_rx_pages = DEFAULT_RX_PAGES; 551 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0, 552 "Receive buffer descriptor pages (1 page = 255 buffer descriptors)"); 553 554 /* Allowable values are 1, 2, 4, 8. */ 555 static int bce_tx_pages = DEFAULT_TX_PAGES; 556 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0, 557 "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)"); 558 559 /* Allowable values are TRUE or FALSE. */ 560 static int bce_hdr_split = TRUE; 561 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0, 562 "Frame header/payload splitting Enable/Disable"); 563 564 /* Allowable values are TRUE or FALSE. */ 565 static int bce_strict_rx_mtu = FALSE; 566 SYSCTL_UINT(_hw_bce, OID_AUTO, strict_rx_mtu, CTLFLAG_RDTUN, 567 &bce_strict_rx_mtu, 0, 568 "Enable/Disable strict RX frame size checking"); 569 570 /* Allowable values are 0 ... 100 */ 571 #ifdef BCE_DEBUG 572 /* Generate 1 interrupt for every transmit completion. */ 573 static int bce_tx_quick_cons_trip_int = 1; 574 #else 575 /* Generate 1 interrupt for every 20 transmit completions. */ 576 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT; 577 #endif 578 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN, 579 &bce_tx_quick_cons_trip_int, 0, 580 "Transmit BD trip point during interrupts"); 581 582 /* Allowable values are 0 ... 100 */ 583 /* Generate 1 interrupt for every transmit completion. */ 584 #ifdef BCE_DEBUG 585 static int bce_tx_quick_cons_trip = 1; 586 #else 587 /* Generate 1 interrupt for every 20 transmit completions. */ 588 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 589 #endif 590 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN, 591 &bce_tx_quick_cons_trip, 0, 592 "Transmit BD trip point"); 593 594 /* Allowable values are 0 ... 100 */ 595 #ifdef BCE_DEBUG 596 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 597 static int bce_tx_ticks_int = 0; 598 #else 599 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 600 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT; 601 #endif 602 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN, 603 &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt"); 604 605 /* Allowable values are 0 ... 100 */ 606 #ifdef BCE_DEBUG 607 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 608 static int bce_tx_ticks = 0; 609 #else 610 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 611 static int bce_tx_ticks = DEFAULT_TX_TICKS; 612 #endif 613 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN, 614 &bce_tx_ticks, 0, "Transmit ticks count"); 615 616 /* Allowable values are 1 ... 100 */ 617 #ifdef BCE_DEBUG 618 /* Generate 1 interrupt for every received frame. */ 619 static int bce_rx_quick_cons_trip_int = 1; 620 #else 621 /* Generate 1 interrupt for every 6 received frames. */ 622 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT; 623 #endif 624 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN, 625 &bce_rx_quick_cons_trip_int, 0, 626 "Receive BD trip point during interrupts"); 627 628 /* Allowable values are 1 ... 100 */ 629 #ifdef BCE_DEBUG 630 /* Generate 1 interrupt for every received frame. */ 631 static int bce_rx_quick_cons_trip = 1; 632 #else 633 /* Generate 1 interrupt for every 6 received frames. */ 634 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 635 #endif 636 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN, 637 &bce_rx_quick_cons_trip, 0, 638 "Receive BD trip point"); 639 640 /* Allowable values are 0 ... 100 */ 641 #ifdef BCE_DEBUG 642 /* Generate an int. if 0us have elapsed since the last received frame. */ 643 static int bce_rx_ticks_int = 0; 644 #else 645 /* Generate an int. if 18us have elapsed since the last received frame. */ 646 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 647 #endif 648 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN, 649 &bce_rx_ticks_int, 0, "Receive ticks count during interrupt"); 650 651 /* Allowable values are 0 ... 100 */ 652 #ifdef BCE_DEBUG 653 /* Generate an int. if 0us have elapsed since the last received frame. */ 654 static int bce_rx_ticks = 0; 655 #else 656 /* Generate an int. if 18us have elapsed since the last received frame. */ 657 static int bce_rx_ticks = DEFAULT_RX_TICKS; 658 #endif 659 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN, 660 &bce_rx_ticks, 0, "Receive ticks count"); 661 662 /****************************************************************************/ 663 /* Device probe function. */ 664 /* */ 665 /* Compares the device to the driver's list of supported devices and */ 666 /* reports back to the OS whether this is the right driver for the device. */ 667 /* */ 668 /* Returns: */ 669 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 670 /****************************************************************************/ 671 static int 672 bce_probe(device_t dev) 673 { 674 const struct bce_type *t; 675 struct bce_softc *sc; 676 char *descbuf; 677 u16 vid = 0, did = 0, svid = 0, sdid = 0; 678 679 t = bce_devs; 680 681 sc = device_get_softc(dev); 682 sc->bce_unit = device_get_unit(dev); 683 sc->bce_dev = dev; 684 685 /* Get the data for the device to be probed. */ 686 vid = pci_get_vendor(dev); 687 did = pci_get_device(dev); 688 svid = pci_get_subvendor(dev); 689 sdid = pci_get_subdevice(dev); 690 691 DBPRINT(sc, BCE_EXTREME_LOAD, 692 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 693 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 694 695 /* Look through the list of known devices for a match. */ 696 while(t->bce_name != NULL) { 697 if ((vid == t->bce_vid) && (did == t->bce_did) && 698 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 699 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 700 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 701 702 if (descbuf == NULL) 703 return(ENOMEM); 704 705 /* Print out the device identity. */ 706 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 707 t->bce_name, (((pci_read_config(dev, 708 PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 709 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 710 711 device_set_desc_copy(dev, descbuf); 712 free(descbuf, M_TEMP); 713 return(BUS_PROBE_DEFAULT); 714 } 715 t++; 716 } 717 718 return(ENXIO); 719 } 720 721 /****************************************************************************/ 722 /* PCI Capabilities Probe Function. */ 723 /* */ 724 /* Walks the PCI capabiites list for the device to find what features are */ 725 /* supported. */ 726 /* */ 727 /* Returns: */ 728 /* None. */ 729 /****************************************************************************/ 730 static void 731 bce_print_adapter_info(struct bce_softc *sc) 732 { 733 int i = 0; 734 735 DBENTER(BCE_VERBOSE_LOAD); 736 737 if (bce_verbose || bootverbose) { 738 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 739 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 740 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 741 742 /* Bus info. */ 743 if (sc->bce_flags & BCE_PCIE_FLAG) { 744 printf("Bus (PCIe x%d, ", sc->link_width); 745 switch (sc->link_speed) { 746 case 1: printf("2.5Gbps); "); break; 747 case 2: printf("5Gbps); "); break; 748 default: printf("Unknown link speed); "); 749 } 750 } else { 751 printf("Bus (PCI%s, %s, %dMHz); ", 752 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 753 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? 754 "32-bit" : "64-bit"), sc->bus_speed_mhz); 755 } 756 757 /* Firmware version and device features. */ 758 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (", 759 sc->bce_bc_ver, sc->rx_pages, sc->tx_pages, 760 (bce_hdr_split == TRUE ? sc->pg_pages: 0)); 761 762 if (bce_hdr_split == TRUE) { 763 printf("SPLT"); 764 i++; 765 } 766 767 if (sc->bce_flags & BCE_USING_MSI_FLAG) { 768 if (i > 0) printf("|"); 769 printf("MSI"); i++; 770 } 771 772 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 773 if (i > 0) printf("|"); 774 printf("MSI-X"); i++; 775 } 776 777 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 778 if (i > 0) printf("|"); 779 printf("2.5G"); i++; 780 } 781 782 if (sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) { 783 if (i > 0) printf("|"); 784 printf("Remote PHY(%s)", 785 sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG ? 786 "FIBER" : "TP"); i++; 787 } 788 789 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 790 if (i > 0) printf("|"); 791 printf("MFW); MFW (%s)\n", sc->bce_mfw_ver); 792 } else { 793 printf(")\n"); 794 } 795 796 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 797 sc->bce_rx_quick_cons_trip_int, 798 sc->bce_rx_quick_cons_trip, 799 sc->bce_rx_ticks_int, 800 sc->bce_rx_ticks, 801 sc->bce_tx_quick_cons_trip_int, 802 sc->bce_tx_quick_cons_trip, 803 sc->bce_tx_ticks_int, 804 sc->bce_tx_ticks); 805 } 806 807 DBEXIT(BCE_VERBOSE_LOAD); 808 } 809 810 /****************************************************************************/ 811 /* PCI Capabilities Probe Function. */ 812 /* */ 813 /* Walks the PCI capabiites list for the device to find what features are */ 814 /* supported. */ 815 /* */ 816 /* Returns: */ 817 /* None. */ 818 /****************************************************************************/ 819 static void 820 bce_probe_pci_caps(device_t dev, struct bce_softc *sc) 821 { 822 u32 reg; 823 824 DBENTER(BCE_VERBOSE_LOAD); 825 826 /* Check if PCI-X capability is enabled. */ 827 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) { 828 if (reg != 0) 829 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; 830 } 831 832 /* Check if PCIe capability is enabled. */ 833 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 834 if (reg != 0) { 835 u16 link_status = pci_read_config(dev, reg + 0x12, 2); 836 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = " 837 "0x%08X\n", link_status); 838 sc->link_speed = link_status & 0xf; 839 sc->link_width = (link_status >> 4) & 0x3f; 840 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG; 841 sc->bce_flags |= BCE_PCIE_FLAG; 842 } 843 } 844 845 /* Check if MSI capability is enabled. */ 846 if (pci_find_cap(dev, PCIY_MSI, ®) == 0) { 847 if (reg != 0) 848 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; 849 } 850 851 /* Check if MSI-X capability is enabled. */ 852 if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) { 853 if (reg != 0) 854 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; 855 } 856 857 DBEXIT(BCE_VERBOSE_LOAD); 858 } 859 860 /****************************************************************************/ 861 /* Load and validate user tunable settings. */ 862 /* */ 863 /* Returns: */ 864 /* Nothing. */ 865 /****************************************************************************/ 866 static void 867 bce_set_tunables(struct bce_softc *sc) 868 { 869 /* Set sysctl values for RX page count. */ 870 switch (bce_rx_pages) { 871 case 1: 872 /* fall-through */ 873 case 2: 874 /* fall-through */ 875 case 4: 876 /* fall-through */ 877 case 8: 878 sc->rx_pages = bce_rx_pages; 879 break; 880 default: 881 sc->rx_pages = DEFAULT_RX_PAGES; 882 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 883 "hw.bce.rx_pages! Setting default of %d.\n", 884 __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES); 885 } 886 887 /* ToDo: Consider allowing user setting for pg_pages. */ 888 sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES); 889 890 /* Set sysctl values for TX page count. */ 891 switch (bce_tx_pages) { 892 case 1: 893 /* fall-through */ 894 case 2: 895 /* fall-through */ 896 case 4: 897 /* fall-through */ 898 case 8: 899 sc->tx_pages = bce_tx_pages; 900 break; 901 default: 902 sc->tx_pages = DEFAULT_TX_PAGES; 903 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 904 "hw.bce.tx_pages! Setting default of %d.\n", 905 __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES); 906 } 907 908 /* 909 * Validate the TX trip point (i.e. the number of 910 * TX completions before a status block update is 911 * generated and an interrupt is asserted. 912 */ 913 if (bce_tx_quick_cons_trip_int <= 100) { 914 sc->bce_tx_quick_cons_trip_int = 915 bce_tx_quick_cons_trip_int; 916 } else { 917 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 918 "hw.bce.tx_quick_cons_trip_int! Setting default of %d.\n", 919 __FILE__, __LINE__, bce_tx_quick_cons_trip_int, 920 DEFAULT_TX_QUICK_CONS_TRIP_INT); 921 sc->bce_tx_quick_cons_trip_int = 922 DEFAULT_TX_QUICK_CONS_TRIP_INT; 923 } 924 925 if (bce_tx_quick_cons_trip <= 100) { 926 sc->bce_tx_quick_cons_trip = 927 bce_tx_quick_cons_trip; 928 } else { 929 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 930 "hw.bce.tx_quick_cons_trip! Setting default of %d.\n", 931 __FILE__, __LINE__, bce_tx_quick_cons_trip, 932 DEFAULT_TX_QUICK_CONS_TRIP); 933 sc->bce_tx_quick_cons_trip = 934 DEFAULT_TX_QUICK_CONS_TRIP; 935 } 936 937 /* 938 * Validate the TX ticks count (i.e. the maximum amount 939 * of time to wait after the last TX completion has 940 * occurred before a status block update is generated 941 * and an interrupt is asserted. 942 */ 943 if (bce_tx_ticks_int <= 100) { 944 sc->bce_tx_ticks_int = 945 bce_tx_ticks_int; 946 } else { 947 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 948 "hw.bce.tx_ticks_int! Setting default of %d.\n", 949 __FILE__, __LINE__, bce_tx_ticks_int, 950 DEFAULT_TX_TICKS_INT); 951 sc->bce_tx_ticks_int = 952 DEFAULT_TX_TICKS_INT; 953 } 954 955 if (bce_tx_ticks <= 100) { 956 sc->bce_tx_ticks = 957 bce_tx_ticks; 958 } else { 959 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 960 "hw.bce.tx_ticks! Setting default of %d.\n", 961 __FILE__, __LINE__, bce_tx_ticks, 962 DEFAULT_TX_TICKS); 963 sc->bce_tx_ticks = 964 DEFAULT_TX_TICKS; 965 } 966 967 /* 968 * Validate the RX trip point (i.e. the number of 969 * RX frames received before a status block update is 970 * generated and an interrupt is asserted. 971 */ 972 if (bce_rx_quick_cons_trip_int <= 100) { 973 sc->bce_rx_quick_cons_trip_int = 974 bce_rx_quick_cons_trip_int; 975 } else { 976 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 977 "hw.bce.rx_quick_cons_trip_int! Setting default of %d.\n", 978 __FILE__, __LINE__, bce_rx_quick_cons_trip_int, 979 DEFAULT_RX_QUICK_CONS_TRIP_INT); 980 sc->bce_rx_quick_cons_trip_int = 981 DEFAULT_RX_QUICK_CONS_TRIP_INT; 982 } 983 984 if (bce_rx_quick_cons_trip <= 100) { 985 sc->bce_rx_quick_cons_trip = 986 bce_rx_quick_cons_trip; 987 } else { 988 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 989 "hw.bce.rx_quick_cons_trip! Setting default of %d.\n", 990 __FILE__, __LINE__, bce_rx_quick_cons_trip, 991 DEFAULT_RX_QUICK_CONS_TRIP); 992 sc->bce_rx_quick_cons_trip = 993 DEFAULT_RX_QUICK_CONS_TRIP; 994 } 995 996 /* 997 * Validate the RX ticks count (i.e. the maximum amount 998 * of time to wait after the last RX frame has been 999 * received before a status block update is generated 1000 * and an interrupt is asserted. 1001 */ 1002 if (bce_rx_ticks_int <= 100) { 1003 sc->bce_rx_ticks_int = bce_rx_ticks_int; 1004 } else { 1005 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 1006 "hw.bce.rx_ticks_int! Setting default of %d.\n", 1007 __FILE__, __LINE__, bce_rx_ticks_int, 1008 DEFAULT_RX_TICKS_INT); 1009 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 1010 } 1011 1012 if (bce_rx_ticks <= 100) { 1013 sc->bce_rx_ticks = bce_rx_ticks; 1014 } else { 1015 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 1016 "hw.bce.rx_ticks! Setting default of %d.\n", 1017 __FILE__, __LINE__, bce_rx_ticks, 1018 DEFAULT_RX_TICKS); 1019 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1020 } 1021 1022 /* Disabling both RX ticks and RX trips will prevent interrupts. */ 1023 if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) { 1024 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and " 1025 "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n", 1026 __FILE__, __LINE__); 1027 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1028 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 1029 } 1030 1031 /* Disabling both TX ticks and TX trips will prevent interrupts. */ 1032 if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) { 1033 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and " 1034 "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n", 1035 __FILE__, __LINE__); 1036 sc->bce_tx_ticks = DEFAULT_TX_TICKS; 1037 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 1038 } 1039 } 1040 1041 /****************************************************************************/ 1042 /* Device attach function. */ 1043 /* */ 1044 /* Allocates device resources, performs secondary chip identification, */ 1045 /* resets and initializes the hardware, and initializes driver instance */ 1046 /* variables. */ 1047 /* */ 1048 /* Returns: */ 1049 /* 0 on success, positive value on failure. */ 1050 /****************************************************************************/ 1051 static int 1052 bce_attach(device_t dev) 1053 { 1054 struct bce_softc *sc; 1055 struct ifnet *ifp; 1056 u32 val; 1057 int count, error, rc = 0, rid; 1058 1059 sc = device_get_softc(dev); 1060 sc->bce_dev = dev; 1061 1062 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1063 1064 sc->bce_unit = device_get_unit(dev); 1065 1066 /* Set initial device and PHY flags */ 1067 sc->bce_flags = 0; 1068 sc->bce_phy_flags = 0; 1069 1070 bce_set_tunables(sc); 1071 1072 pci_enable_busmaster(dev); 1073 1074 /* Allocate PCI memory resources. */ 1075 rid = PCIR_BAR(0); 1076 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1077 &rid, RF_ACTIVE); 1078 1079 if (sc->bce_res_mem == NULL) { 1080 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 1081 __FILE__, __LINE__); 1082 rc = ENXIO; 1083 goto bce_attach_fail; 1084 } 1085 1086 /* Get various resource handles. */ 1087 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 1088 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 1089 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 1090 1091 bce_probe_pci_caps(dev, sc); 1092 1093 rid = 1; 1094 count = 0; 1095 #if 0 1096 /* Try allocating MSI-X interrupts. */ 1097 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) && 1098 (bce_msi_enable >= 2) && 1099 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1100 &rid, RF_ACTIVE)) != NULL)) { 1101 msi_needed = count = 1; 1102 1103 if (((error = pci_alloc_msix(dev, &count)) != 0) || 1104 (count != msi_needed)) { 1105 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d," 1106 "Received = %d, error = %d\n", __FILE__, __LINE__, 1107 msi_needed, count, error); 1108 count = 0; 1109 pci_release_msi(dev); 1110 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1111 sc->bce_res_irq); 1112 sc->bce_res_irq = NULL; 1113 } else { 1114 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n", 1115 __FUNCTION__); 1116 sc->bce_flags |= BCE_USING_MSIX_FLAG; 1117 } 1118 } 1119 #endif 1120 1121 /* Try allocating a MSI interrupt. */ 1122 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) && 1123 (bce_msi_enable >= 1) && (count == 0)) { 1124 count = 1; 1125 if ((error = pci_alloc_msi(dev, &count)) != 0) { 1126 BCE_PRINTF("%s(%d): MSI allocation failed! " 1127 "error = %d\n", __FILE__, __LINE__, error); 1128 count = 0; 1129 pci_release_msi(dev); 1130 } else { 1131 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI " 1132 "interrupt.\n", __FUNCTION__); 1133 sc->bce_flags |= BCE_USING_MSI_FLAG; 1134 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 1135 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG; 1136 rid = 1; 1137 } 1138 } 1139 1140 /* Try allocating a legacy interrupt. */ 1141 if (count == 0) { 1142 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n", 1143 __FUNCTION__); 1144 rid = 0; 1145 } 1146 1147 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1148 &rid, RF_ACTIVE | (count != 0 ? 0 : RF_SHAREABLE)); 1149 1150 /* Report any IRQ allocation errors. */ 1151 if (sc->bce_res_irq == NULL) { 1152 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 1153 __FILE__, __LINE__); 1154 rc = ENXIO; 1155 goto bce_attach_fail; 1156 } 1157 1158 /* Initialize mutex for the current device instance. */ 1159 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 1160 1161 /* 1162 * Configure byte swap and enable indirect register access. 1163 * Rely on CPU to do target byte swapping on big endian systems. 1164 * Access to registers outside of PCI configurtion space are not 1165 * valid until this is done. 1166 */ 1167 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 1168 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 1169 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 1170 1171 /* Save ASIC revsion info. */ 1172 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 1173 1174 /* Weed out any non-production controller revisions. */ 1175 switch(BCE_CHIP_ID(sc)) { 1176 case BCE_CHIP_ID_5706_A0: 1177 case BCE_CHIP_ID_5706_A1: 1178 case BCE_CHIP_ID_5708_A0: 1179 case BCE_CHIP_ID_5708_B0: 1180 case BCE_CHIP_ID_5709_A0: 1181 case BCE_CHIP_ID_5709_B0: 1182 case BCE_CHIP_ID_5709_B1: 1183 case BCE_CHIP_ID_5709_B2: 1184 BCE_PRINTF("%s(%d): Unsupported controller " 1185 "revision (%c%d)!\n", __FILE__, __LINE__, 1186 (((pci_read_config(dev, PCIR_REVID, 4) & 1187 0xf0) >> 4) + 'A'), (pci_read_config(dev, 1188 PCIR_REVID, 4) & 0xf)); 1189 rc = ENODEV; 1190 goto bce_attach_fail; 1191 } 1192 1193 /* 1194 * The embedded PCIe to PCI-X bridge (EPB) 1195 * in the 5708 cannot address memory above 1196 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 1197 */ 1198 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 1199 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 1200 else 1201 sc->max_bus_addr = BUS_SPACE_MAXADDR; 1202 1203 /* 1204 * Find the base address for shared memory access. 1205 * Newer versions of bootcode use a signature and offset 1206 * while older versions use a fixed address. 1207 */ 1208 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 1209 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 1210 /* Multi-port devices use different offsets in shared memory. */ 1211 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 + 1212 (pci_get_function(sc->bce_dev) << 2)); 1213 else 1214 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 1215 1216 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 1217 __FUNCTION__, sc->bce_shmem_base); 1218 1219 /* Fetch the bootcode revision. */ 1220 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV); 1221 for (int i = 0, j = 0; i < 3; i++) { 1222 u8 num; 1223 1224 num = (u8) (val >> (24 - (i * 8))); 1225 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 1226 if (num >= k || !skip0 || k == 1) { 1227 sc->bce_bc_ver[j++] = (num / k) + ''; 1228 skip0 = 0; 1229 } 1230 } 1231 1232 if (i != 2) 1233 sc->bce_bc_ver[j++] = '.'; 1234 } 1235 1236 /* Check if any management firwmare is enabled. */ 1237 val = bce_shmem_rd(sc, BCE_PORT_FEATURE); 1238 if (val & BCE_PORT_FEATURE_ASF_ENABLED) { 1239 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 1240 1241 /* Allow time for firmware to enter the running state. */ 1242 for (int i = 0; i < 30; i++) { 1243 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1244 if (val & BCE_CONDITION_MFW_RUN_MASK) 1245 break; 1246 DELAY(10000); 1247 } 1248 1249 /* Check if management firmware is running. */ 1250 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1251 val &= BCE_CONDITION_MFW_RUN_MASK; 1252 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) && 1253 (val != BCE_CONDITION_MFW_RUN_NONE)) { 1254 u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR); 1255 int i = 0; 1256 1257 /* Read the management firmware version string. */ 1258 for (int j = 0; j < 3; j++) { 1259 val = bce_reg_rd_ind(sc, addr + j * 4); 1260 val = bswap32(val); 1261 memcpy(&sc->bce_mfw_ver[i], &val, 4); 1262 i += 4; 1263 } 1264 } else { 1265 /* May cause firmware synchronization timeouts. */ 1266 BCE_PRINTF("%s(%d): Management firmware enabled " 1267 "but not running!\n", __FILE__, __LINE__); 1268 strcpy(sc->bce_mfw_ver, "NOT RUNNING!"); 1269 1270 /* ToDo: Any action the driver should take? */ 1271 } 1272 } 1273 1274 /* Get PCI bus information (speed and type). */ 1275 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 1276 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 1277 u32 clkreg; 1278 1279 sc->bce_flags |= BCE_PCIX_FLAG; 1280 1281 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 1282 1283 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 1284 switch (clkreg) { 1285 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 1286 sc->bus_speed_mhz = 133; 1287 break; 1288 1289 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 1290 sc->bus_speed_mhz = 100; 1291 break; 1292 1293 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 1294 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 1295 sc->bus_speed_mhz = 66; 1296 break; 1297 1298 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 1299 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 1300 sc->bus_speed_mhz = 50; 1301 break; 1302 1303 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 1304 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 1305 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 1306 sc->bus_speed_mhz = 33; 1307 break; 1308 } 1309 } else { 1310 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 1311 sc->bus_speed_mhz = 66; 1312 else 1313 sc->bus_speed_mhz = 33; 1314 } 1315 1316 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 1317 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 1318 1319 /* Find the media type for the adapter. */ 1320 bce_get_media(sc); 1321 1322 /* Reset controller and announce to bootcode that driver is present. */ 1323 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 1324 BCE_PRINTF("%s(%d): Controller reset failed!\n", 1325 __FILE__, __LINE__); 1326 rc = ENXIO; 1327 goto bce_attach_fail; 1328 } 1329 1330 /* Initialize the controller. */ 1331 if (bce_chipinit(sc)) { 1332 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 1333 __FILE__, __LINE__); 1334 rc = ENXIO; 1335 goto bce_attach_fail; 1336 } 1337 1338 /* Perform NVRAM test. */ 1339 if (bce_nvram_test(sc)) { 1340 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 1341 __FILE__, __LINE__); 1342 rc = ENXIO; 1343 goto bce_attach_fail; 1344 } 1345 1346 /* Fetch the permanent Ethernet MAC address. */ 1347 bce_get_mac_addr(sc); 1348 1349 /* Update statistics once every second. */ 1350 sc->bce_stats_ticks = 1000000 & 0xffff00; 1351 1352 /* Store data needed by PHY driver for backplane applications */ 1353 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 1354 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG); 1355 1356 /* Allocate DMA memory resources. */ 1357 if (bce_dma_alloc(dev)) { 1358 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 1359 __FILE__, __LINE__); 1360 rc = ENXIO; 1361 goto bce_attach_fail; 1362 } 1363 1364 /* Allocate an ifnet structure. */ 1365 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 1366 if (ifp == NULL) { 1367 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 1368 __FILE__, __LINE__); 1369 rc = ENXIO; 1370 goto bce_attach_fail; 1371 } 1372 1373 /* Initialize the ifnet interface. */ 1374 ifp->if_softc = sc; 1375 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1376 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1377 ifp->if_ioctl = bce_ioctl; 1378 ifp->if_start = bce_start; 1379 ifp->if_get_counter = bce_get_counter; 1380 ifp->if_init = bce_init; 1381 ifp->if_mtu = ETHERMTU; 1382 1383 if (bce_tso_enable) { 1384 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; 1385 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 | 1386 IFCAP_VLAN_HWTSO; 1387 } else { 1388 ifp->if_hwassist = BCE_IF_HWASSIST; 1389 ifp->if_capabilities = BCE_IF_CAPABILITIES; 1390 } 1391 1392 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 1393 ifp->if_capabilities |= IFCAP_LINKSTATE; 1394 1395 ifp->if_capenable = ifp->if_capabilities; 1396 1397 /* 1398 * Assume standard mbuf sizes for buffer allocation. 1399 * This may change later if the MTU size is set to 1400 * something other than 1500. 1401 */ 1402 bce_get_rx_buffer_sizes(sc, 1403 (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)); 1404 1405 /* Recalculate our buffer allocation sizes. */ 1406 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD_ALLOC; 1407 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1408 IFQ_SET_READY(&ifp->if_snd); 1409 1410 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1411 ifp->if_baudrate = IF_Mbps(2500ULL); 1412 else 1413 ifp->if_baudrate = IF_Mbps(1000); 1414 1415 /* Handle any special PHY initialization for SerDes PHYs. */ 1416 bce_init_media(sc); 1417 1418 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 1419 ifmedia_init(&sc->bce_ifmedia, IFM_IMASK, bce_ifmedia_upd, 1420 bce_ifmedia_sts); 1421 /* 1422 * We can't manually override remote PHY's link and assume 1423 * PHY port configuration(Fiber or TP) is not changed after 1424 * device attach. This may not be correct though. 1425 */ 1426 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) { 1427 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 1428 ifmedia_add(&sc->bce_ifmedia, 1429 IFM_ETHER | IFM_2500_SX, 0, NULL); 1430 ifmedia_add(&sc->bce_ifmedia, 1431 IFM_ETHER | IFM_2500_SX | IFM_FDX, 0, NULL); 1432 } 1433 ifmedia_add(&sc->bce_ifmedia, 1434 IFM_ETHER | IFM_1000_SX, 0, NULL); 1435 ifmedia_add(&sc->bce_ifmedia, 1436 IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL); 1437 } else { 1438 ifmedia_add(&sc->bce_ifmedia, 1439 IFM_ETHER | IFM_10_T, 0, NULL); 1440 ifmedia_add(&sc->bce_ifmedia, 1441 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1442 ifmedia_add(&sc->bce_ifmedia, 1443 IFM_ETHER | IFM_100_TX, 0, NULL); 1444 ifmedia_add(&sc->bce_ifmedia, 1445 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1446 ifmedia_add(&sc->bce_ifmedia, 1447 IFM_ETHER | IFM_1000_T, 0, NULL); 1448 ifmedia_add(&sc->bce_ifmedia, 1449 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1450 } 1451 ifmedia_add(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1452 ifmedia_set(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO); 1453 sc->bce_ifmedia.ifm_media = sc->bce_ifmedia.ifm_cur->ifm_media; 1454 } else { 1455 /* MII child bus by attaching the PHY. */ 1456 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd, 1457 bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr, 1458 MII_OFFSET_ANY, MIIF_DOPAUSE); 1459 if (rc != 0) { 1460 BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__, 1461 __LINE__); 1462 goto bce_attach_fail; 1463 } 1464 } 1465 1466 /* Attach to the Ethernet interface list. */ 1467 ether_ifattach(ifp, sc->eaddr); 1468 1469 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 1470 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 1471 1472 /* Hookup IRQ last. */ 1473 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, 1474 NULL, bce_intr, sc, &sc->bce_intrhand); 1475 1476 if (rc) { 1477 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 1478 __FILE__, __LINE__); 1479 bce_detach(dev); 1480 goto bce_attach_exit; 1481 } 1482 1483 /* 1484 * At this point we've acquired all the resources 1485 * we need to run so there's no turning back, we're 1486 * cleared for launch. 1487 */ 1488 1489 /* Print some important debugging info. */ 1490 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc)); 1491 1492 /* Add the supported sysctls to the kernel. */ 1493 bce_add_sysctls(sc); 1494 1495 BCE_LOCK(sc); 1496 1497 /* 1498 * The chip reset earlier notified the bootcode that 1499 * a driver is present. We now need to start our pulse 1500 * routine so that the bootcode is reminded that we're 1501 * still running. 1502 */ 1503 bce_pulse(sc); 1504 1505 bce_mgmt_init_locked(sc); 1506 BCE_UNLOCK(sc); 1507 1508 /* Finally, print some useful adapter info */ 1509 bce_print_adapter_info(sc); 1510 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n", 1511 __FUNCTION__, sc); 1512 1513 goto bce_attach_exit; 1514 1515 bce_attach_fail: 1516 bce_release_resources(sc); 1517 1518 bce_attach_exit: 1519 1520 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1521 1522 return(rc); 1523 } 1524 1525 /****************************************************************************/ 1526 /* Device detach function. */ 1527 /* */ 1528 /* Stops the controller, resets the controller, and releases resources. */ 1529 /* */ 1530 /* Returns: */ 1531 /* 0 on success, positive value on failure. */ 1532 /****************************************************************************/ 1533 static int 1534 bce_detach(device_t dev) 1535 { 1536 struct bce_softc *sc = device_get_softc(dev); 1537 struct ifnet *ifp; 1538 u32 msg; 1539 1540 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1541 1542 ifp = sc->bce_ifp; 1543 1544 /* Stop and reset the controller. */ 1545 BCE_LOCK(sc); 1546 1547 /* Stop the pulse so the bootcode can go to driver absent state. */ 1548 callout_stop(&sc->bce_pulse_callout); 1549 1550 bce_stop(sc); 1551 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1552 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1553 else 1554 msg = BCE_DRV_MSG_CODE_UNLOAD; 1555 bce_reset(sc, msg); 1556 1557 BCE_UNLOCK(sc); 1558 1559 ether_ifdetach(ifp); 1560 1561 /* If we have a child device on the MII bus remove it too. */ 1562 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 1563 ifmedia_removeall(&sc->bce_ifmedia); 1564 else { 1565 bus_generic_detach(dev); 1566 device_delete_child(dev, sc->bce_miibus); 1567 } 1568 1569 /* Release all remaining resources. */ 1570 bce_release_resources(sc); 1571 1572 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1573 1574 return(0); 1575 } 1576 1577 /****************************************************************************/ 1578 /* Device shutdown function. */ 1579 /* */ 1580 /* Stops and resets the controller. */ 1581 /* */ 1582 /* Returns: */ 1583 /* 0 on success, positive value on failure. */ 1584 /****************************************************************************/ 1585 static int 1586 bce_shutdown(device_t dev) 1587 { 1588 struct bce_softc *sc = device_get_softc(dev); 1589 u32 msg; 1590 1591 DBENTER(BCE_VERBOSE); 1592 1593 BCE_LOCK(sc); 1594 bce_stop(sc); 1595 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1596 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1597 else 1598 msg = BCE_DRV_MSG_CODE_UNLOAD; 1599 bce_reset(sc, msg); 1600 BCE_UNLOCK(sc); 1601 1602 DBEXIT(BCE_VERBOSE); 1603 1604 return (0); 1605 } 1606 1607 #ifdef BCE_DEBUG 1608 /****************************************************************************/ 1609 /* Register read. */ 1610 /* */ 1611 /* Returns: */ 1612 /* The value of the register. */ 1613 /****************************************************************************/ 1614 static u32 1615 bce_reg_rd(struct bce_softc *sc, u32 offset) 1616 { 1617 u32 val = REG_RD(sc, offset); 1618 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1619 __FUNCTION__, offset, val); 1620 return val; 1621 } 1622 1623 /****************************************************************************/ 1624 /* Register write (16 bit). */ 1625 /* */ 1626 /* Returns: */ 1627 /* Nothing. */ 1628 /****************************************************************************/ 1629 static void 1630 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val) 1631 { 1632 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n", 1633 __FUNCTION__, offset, val); 1634 REG_WR16(sc, offset, val); 1635 } 1636 1637 /****************************************************************************/ 1638 /* Register write. */ 1639 /* */ 1640 /* Returns: */ 1641 /* Nothing. */ 1642 /****************************************************************************/ 1643 static void 1644 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val) 1645 { 1646 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1647 __FUNCTION__, offset, val); 1648 REG_WR(sc, offset, val); 1649 } 1650 #endif 1651 1652 /****************************************************************************/ 1653 /* Indirect register read. */ 1654 /* */ 1655 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 1656 /* configuration space. Using this mechanism avoids issues with posted */ 1657 /* reads but is much slower than memory-mapped I/O. */ 1658 /* */ 1659 /* Returns: */ 1660 /* The value of the register. */ 1661 /****************************************************************************/ 1662 static u32 1663 bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 1664 { 1665 device_t dev; 1666 dev = sc->bce_dev; 1667 1668 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1669 #ifdef BCE_DEBUG 1670 { 1671 u32 val; 1672 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1673 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1674 __FUNCTION__, offset, val); 1675 return val; 1676 } 1677 #else 1678 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1679 #endif 1680 } 1681 1682 /****************************************************************************/ 1683 /* Indirect register write. */ 1684 /* */ 1685 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1686 /* configuration space. Using this mechanism avoids issues with posted */ 1687 /* writes but is muchh slower than memory-mapped I/O. */ 1688 /* */ 1689 /* Returns: */ 1690 /* Nothing. */ 1691 /****************************************************************************/ 1692 static void 1693 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 1694 { 1695 device_t dev; 1696 dev = sc->bce_dev; 1697 1698 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1699 __FUNCTION__, offset, val); 1700 1701 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1702 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 1703 } 1704 1705 /****************************************************************************/ 1706 /* Shared memory write. */ 1707 /* */ 1708 /* Writes NetXtreme II shared memory region. */ 1709 /* */ 1710 /* Returns: */ 1711 /* Nothing. */ 1712 /****************************************************************************/ 1713 static void 1714 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val) 1715 { 1716 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to " 1717 "0x%08X\n", __FUNCTION__, val, offset); 1718 1719 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val); 1720 } 1721 1722 /****************************************************************************/ 1723 /* Shared memory read. */ 1724 /* */ 1725 /* Reads NetXtreme II shared memory region. */ 1726 /* */ 1727 /* Returns: */ 1728 /* The 32 bit value read. */ 1729 /****************************************************************************/ 1730 static u32 1731 bce_shmem_rd(struct bce_softc *sc, u32 offset) 1732 { 1733 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset); 1734 1735 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from " 1736 "0x%08X\n", __FUNCTION__, val, offset); 1737 1738 return val; 1739 } 1740 1741 #ifdef BCE_DEBUG 1742 /****************************************************************************/ 1743 /* Context memory read. */ 1744 /* */ 1745 /* The NetXtreme II controller uses context memory to track connection */ 1746 /* information for L2 and higher network protocols. */ 1747 /* */ 1748 /* Returns: */ 1749 /* The requested 32 bit value of context memory. */ 1750 /****************************************************************************/ 1751 static u32 1752 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset) 1753 { 1754 u32 idx, offset, retry_cnt = 5, val; 1755 1756 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || 1757 cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID " 1758 "address: 0x%08X.\n", __FUNCTION__, cid_addr)); 1759 1760 offset = ctx_offset + cid_addr; 1761 1762 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1763 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ)); 1764 1765 for (idx = 0; idx < retry_cnt; idx++) { 1766 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1767 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0) 1768 break; 1769 DELAY(5); 1770 } 1771 1772 if (val & BCE_CTX_CTX_CTRL_READ_REQ) 1773 BCE_PRINTF("%s(%d); Unable to read CTX memory: " 1774 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1775 __FILE__, __LINE__, cid_addr, ctx_offset); 1776 1777 val = REG_RD(sc, BCE_CTX_CTX_DATA); 1778 } else { 1779 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1780 val = REG_RD(sc, BCE_CTX_DATA); 1781 } 1782 1783 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1784 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val); 1785 1786 return(val); 1787 } 1788 #endif 1789 1790 /****************************************************************************/ 1791 /* Context memory write. */ 1792 /* */ 1793 /* The NetXtreme II controller uses context memory to track connection */ 1794 /* information for L2 and higher network protocols. */ 1795 /* */ 1796 /* Returns: */ 1797 /* Nothing. */ 1798 /****************************************************************************/ 1799 static void 1800 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val) 1801 { 1802 u32 idx, offset = ctx_offset + cid_addr; 1803 u32 val, retry_cnt = 5; 1804 1805 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1806 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val); 1807 1808 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1809 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1810 __FUNCTION__, cid_addr)); 1811 1812 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1813 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val); 1814 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ)); 1815 1816 for (idx = 0; idx < retry_cnt; idx++) { 1817 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1818 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0) 1819 break; 1820 DELAY(5); 1821 } 1822 1823 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) 1824 BCE_PRINTF("%s(%d); Unable to write CTX memory: " 1825 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1826 __FILE__, __LINE__, cid_addr, ctx_offset); 1827 1828 } else { 1829 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1830 REG_WR(sc, BCE_CTX_DATA, ctx_val); 1831 } 1832 } 1833 1834 /****************************************************************************/ 1835 /* PHY register read. */ 1836 /* */ 1837 /* Implements register reads on the MII bus. */ 1838 /* */ 1839 /* Returns: */ 1840 /* The value of the register. */ 1841 /****************************************************************************/ 1842 static int 1843 bce_miibus_read_reg(device_t dev, int phy, int reg) 1844 { 1845 struct bce_softc *sc; 1846 u32 val; 1847 int i; 1848 1849 sc = device_get_softc(dev); 1850 1851 /* 1852 * The 5709S PHY is an IEEE Clause 45 PHY 1853 * with special mappings to work with IEEE 1854 * Clause 22 register accesses. 1855 */ 1856 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1857 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1858 reg += 0x10; 1859 } 1860 1861 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1862 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1863 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1864 1865 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1866 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1867 1868 DELAY(40); 1869 } 1870 1871 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1872 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1873 BCE_EMAC_MDIO_COMM_START_BUSY; 1874 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1875 1876 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1877 DELAY(10); 1878 1879 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1880 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1881 DELAY(5); 1882 1883 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1884 val &= BCE_EMAC_MDIO_COMM_DATA; 1885 1886 break; 1887 } 1888 } 1889 1890 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1891 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, " 1892 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1893 val = 0x0; 1894 } else { 1895 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1896 } 1897 1898 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1899 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1900 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1901 1902 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1903 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1904 1905 DELAY(40); 1906 } 1907 1908 DB_PRINT_PHY_REG(reg, val); 1909 return (val & 0xffff); 1910 } 1911 1912 /****************************************************************************/ 1913 /* PHY register write. */ 1914 /* */ 1915 /* Implements register writes on the MII bus. */ 1916 /* */ 1917 /* Returns: */ 1918 /* The value of the register. */ 1919 /****************************************************************************/ 1920 static int 1921 bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1922 { 1923 struct bce_softc *sc; 1924 u32 val1; 1925 int i; 1926 1927 sc = device_get_softc(dev); 1928 1929 DB_PRINT_PHY_REG(reg, val); 1930 1931 /* 1932 * The 5709S PHY is an IEEE Clause 45 PHY 1933 * with special mappings to work with IEEE 1934 * Clause 22 register accesses. 1935 */ 1936 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1937 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1938 reg += 0x10; 1939 } 1940 1941 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1942 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1943 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1944 1945 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1946 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1947 1948 DELAY(40); 1949 } 1950 1951 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1952 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1953 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1954 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 1955 1956 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1957 DELAY(10); 1958 1959 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1960 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1961 DELAY(5); 1962 break; 1963 } 1964 } 1965 1966 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 1967 BCE_PRINTF("%s(%d): PHY write timeout!\n", 1968 __FILE__, __LINE__); 1969 1970 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1971 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1972 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1973 1974 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1975 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1976 1977 DELAY(40); 1978 } 1979 1980 return 0; 1981 } 1982 1983 /****************************************************************************/ 1984 /* MII bus status change. */ 1985 /* */ 1986 /* Called by the MII bus driver when the PHY establishes link to set the */ 1987 /* MAC interface registers. */ 1988 /* */ 1989 /* Returns: */ 1990 /* Nothing. */ 1991 /****************************************************************************/ 1992 static void 1993 bce_miibus_statchg(device_t dev) 1994 { 1995 struct bce_softc *sc; 1996 struct mii_data *mii; 1997 struct ifmediareq ifmr; 1998 int media_active, media_status, val; 1999 2000 sc = device_get_softc(dev); 2001 2002 DBENTER(BCE_VERBOSE_PHY); 2003 2004 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 2005 bzero(&ifmr, sizeof(ifmr)); 2006 bce_ifmedia_sts_rphy(sc, &ifmr); 2007 media_active = ifmr.ifm_active; 2008 media_status = ifmr.ifm_status; 2009 } else { 2010 mii = device_get_softc(sc->bce_miibus); 2011 media_active = mii->mii_media_active; 2012 media_status = mii->mii_media_status; 2013 } 2014 2015 /* Ignore invalid media status. */ 2016 if ((media_status & (IFM_ACTIVE | IFM_AVALID)) != 2017 (IFM_ACTIVE | IFM_AVALID)) 2018 goto bce_miibus_statchg_exit; 2019 2020 val = REG_RD(sc, BCE_EMAC_MODE); 2021 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 2022 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 2023 BCE_EMAC_MODE_25G); 2024 2025 /* Set MII or GMII interface based on the PHY speed. */ 2026 switch (IFM_SUBTYPE(media_active)) { 2027 case IFM_10_T: 2028 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 2029 DBPRINT(sc, BCE_INFO_PHY, 2030 "Enabling 10Mb interface.\n"); 2031 val |= BCE_EMAC_MODE_PORT_MII_10; 2032 break; 2033 } 2034 /* fall-through */ 2035 case IFM_100_TX: 2036 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n"); 2037 val |= BCE_EMAC_MODE_PORT_MII; 2038 break; 2039 case IFM_2500_SX: 2040 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n"); 2041 val |= BCE_EMAC_MODE_25G; 2042 /* fall-through */ 2043 case IFM_1000_T: 2044 case IFM_1000_SX: 2045 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n"); 2046 val |= BCE_EMAC_MODE_PORT_GMII; 2047 break; 2048 default: 2049 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling " 2050 "default GMII interface.\n"); 2051 val |= BCE_EMAC_MODE_PORT_GMII; 2052 } 2053 2054 /* Set half or full duplex based on PHY settings. */ 2055 if ((IFM_OPTIONS(media_active) & IFM_FDX) == 0) { 2056 DBPRINT(sc, BCE_INFO_PHY, 2057 "Setting Half-Duplex interface.\n"); 2058 val |= BCE_EMAC_MODE_HALF_DUPLEX; 2059 } else 2060 DBPRINT(sc, BCE_INFO_PHY, 2061 "Setting Full-Duplex interface.\n"); 2062 2063 REG_WR(sc, BCE_EMAC_MODE, val); 2064 2065 if ((IFM_OPTIONS(media_active) & IFM_ETH_RXPAUSE) != 0) { 2066 DBPRINT(sc, BCE_INFO_PHY, 2067 "%s(): Enabling RX flow control.\n", __FUNCTION__); 2068 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2069 sc->bce_flags |= BCE_USING_RX_FLOW_CONTROL; 2070 } else { 2071 DBPRINT(sc, BCE_INFO_PHY, 2072 "%s(): Disabling RX flow control.\n", __FUNCTION__); 2073 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2074 sc->bce_flags &= ~BCE_USING_RX_FLOW_CONTROL; 2075 } 2076 2077 if ((IFM_OPTIONS(media_active) & IFM_ETH_TXPAUSE) != 0) { 2078 DBPRINT(sc, BCE_INFO_PHY, 2079 "%s(): Enabling TX flow control.\n", __FUNCTION__); 2080 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2081 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL; 2082 } else { 2083 DBPRINT(sc, BCE_INFO_PHY, 2084 "%s(): Disabling TX flow control.\n", __FUNCTION__); 2085 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2086 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL; 2087 } 2088 2089 /* ToDo: Update watermarks in bce_init_rx_context(). */ 2090 2091 bce_miibus_statchg_exit: 2092 DBEXIT(BCE_VERBOSE_PHY); 2093 } 2094 2095 /****************************************************************************/ 2096 /* Acquire NVRAM lock. */ 2097 /* */ 2098 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 2099 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2100 /* for use by the driver. */ 2101 /* */ 2102 /* Returns: */ 2103 /* 0 on success, positive value on failure. */ 2104 /****************************************************************************/ 2105 static int 2106 bce_acquire_nvram_lock(struct bce_softc *sc) 2107 { 2108 u32 val; 2109 int j, rc = 0; 2110 2111 DBENTER(BCE_VERBOSE_NVRAM); 2112 2113 /* Request access to the flash interface. */ 2114 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 2115 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2116 val = REG_RD(sc, BCE_NVM_SW_ARB); 2117 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 2118 break; 2119 2120 DELAY(5); 2121 } 2122 2123 if (j >= NVRAM_TIMEOUT_COUNT) { 2124 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 2125 rc = EBUSY; 2126 } 2127 2128 DBEXIT(BCE_VERBOSE_NVRAM); 2129 return (rc); 2130 } 2131 2132 /****************************************************************************/ 2133 /* Release NVRAM lock. */ 2134 /* */ 2135 /* When the caller is finished accessing NVRAM the lock must be released. */ 2136 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2137 /* for use by the driver. */ 2138 /* */ 2139 /* Returns: */ 2140 /* 0 on success, positive value on failure. */ 2141 /****************************************************************************/ 2142 static int 2143 bce_release_nvram_lock(struct bce_softc *sc) 2144 { 2145 u32 val; 2146 int j, rc = 0; 2147 2148 DBENTER(BCE_VERBOSE_NVRAM); 2149 2150 /* 2151 * Relinquish nvram interface. 2152 */ 2153 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 2154 2155 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2156 val = REG_RD(sc, BCE_NVM_SW_ARB); 2157 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 2158 break; 2159 2160 DELAY(5); 2161 } 2162 2163 if (j >= NVRAM_TIMEOUT_COUNT) { 2164 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n"); 2165 rc = EBUSY; 2166 } 2167 2168 DBEXIT(BCE_VERBOSE_NVRAM); 2169 return (rc); 2170 } 2171 2172 #ifdef BCE_NVRAM_WRITE_SUPPORT 2173 /****************************************************************************/ 2174 /* Enable NVRAM write access. */ 2175 /* */ 2176 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 2177 /* */ 2178 /* Returns: */ 2179 /* 0 on success, positive value on failure. */ 2180 /****************************************************************************/ 2181 static int 2182 bce_enable_nvram_write(struct bce_softc *sc) 2183 { 2184 u32 val; 2185 int rc = 0; 2186 2187 DBENTER(BCE_VERBOSE_NVRAM); 2188 2189 val = REG_RD(sc, BCE_MISC_CFG); 2190 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 2191 2192 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2193 int j; 2194 2195 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2196 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 2197 2198 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2199 DELAY(5); 2200 2201 val = REG_RD(sc, BCE_NVM_COMMAND); 2202 if (val & BCE_NVM_COMMAND_DONE) 2203 break; 2204 } 2205 2206 if (j >= NVRAM_TIMEOUT_COUNT) { 2207 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 2208 rc = EBUSY; 2209 } 2210 } 2211 2212 DBENTER(BCE_VERBOSE_NVRAM); 2213 return (rc); 2214 } 2215 2216 /****************************************************************************/ 2217 /* Disable NVRAM write access. */ 2218 /* */ 2219 /* When the caller is finished writing to NVRAM write access must be */ 2220 /* disabled. */ 2221 /* */ 2222 /* Returns: */ 2223 /* Nothing. */ 2224 /****************************************************************************/ 2225 static void 2226 bce_disable_nvram_write(struct bce_softc *sc) 2227 { 2228 u32 val; 2229 2230 DBENTER(BCE_VERBOSE_NVRAM); 2231 2232 val = REG_RD(sc, BCE_MISC_CFG); 2233 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 2234 2235 DBEXIT(BCE_VERBOSE_NVRAM); 2236 2237 } 2238 #endif 2239 2240 /****************************************************************************/ 2241 /* Enable NVRAM access. */ 2242 /* */ 2243 /* Before accessing NVRAM for read or write operations the caller must */ 2244 /* enabled NVRAM access. */ 2245 /* */ 2246 /* Returns: */ 2247 /* Nothing. */ 2248 /****************************************************************************/ 2249 static void 2250 bce_enable_nvram_access(struct bce_softc *sc) 2251 { 2252 u32 val; 2253 2254 DBENTER(BCE_VERBOSE_NVRAM); 2255 2256 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2257 /* Enable both bits, even on read. */ 2258 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val | 2259 BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 2260 2261 DBEXIT(BCE_VERBOSE_NVRAM); 2262 } 2263 2264 /****************************************************************************/ 2265 /* Disable NVRAM access. */ 2266 /* */ 2267 /* When the caller is finished accessing NVRAM access must be disabled. */ 2268 /* */ 2269 /* Returns: */ 2270 /* Nothing. */ 2271 /****************************************************************************/ 2272 static void 2273 bce_disable_nvram_access(struct bce_softc *sc) 2274 { 2275 u32 val; 2276 2277 DBENTER(BCE_VERBOSE_NVRAM); 2278 2279 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2280 2281 /* Disable both bits, even after read. */ 2282 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val & 2283 ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN)); 2284 2285 DBEXIT(BCE_VERBOSE_NVRAM); 2286 } 2287 2288 #ifdef BCE_NVRAM_WRITE_SUPPORT 2289 /****************************************************************************/ 2290 /* Erase NVRAM page before writing. */ 2291 /* */ 2292 /* Non-buffered flash parts require that a page be erased before it is */ 2293 /* written. */ 2294 /* */ 2295 /* Returns: */ 2296 /* 0 on success, positive value on failure. */ 2297 /****************************************************************************/ 2298 static int 2299 bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 2300 { 2301 u32 cmd; 2302 int j, rc = 0; 2303 2304 DBENTER(BCE_VERBOSE_NVRAM); 2305 2306 /* Buffered flash doesn't require an erase. */ 2307 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED) 2308 goto bce_nvram_erase_page_exit; 2309 2310 /* Build an erase command. */ 2311 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 2312 BCE_NVM_COMMAND_DOIT; 2313 2314 /* 2315 * Clear the DONE bit separately, set the NVRAM address to erase, 2316 * and issue the erase command. 2317 */ 2318 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2319 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2320 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2321 2322 /* Wait for completion. */ 2323 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2324 u32 val; 2325 2326 DELAY(5); 2327 2328 val = REG_RD(sc, BCE_NVM_COMMAND); 2329 if (val & BCE_NVM_COMMAND_DONE) 2330 break; 2331 } 2332 2333 if (j >= NVRAM_TIMEOUT_COUNT) { 2334 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 2335 rc = EBUSY; 2336 } 2337 2338 bce_nvram_erase_page_exit: 2339 DBEXIT(BCE_VERBOSE_NVRAM); 2340 return (rc); 2341 } 2342 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2343 2344 /****************************************************************************/ 2345 /* Read a dword (32 bits) from NVRAM. */ 2346 /* */ 2347 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 2348 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 2349 /* */ 2350 /* Returns: */ 2351 /* 0 on success and the 32 bit value read, positive value on failure. */ 2352 /****************************************************************************/ 2353 static int 2354 bce_nvram_read_dword(struct bce_softc *sc, 2355 u32 offset, u8 *ret_val, u32 cmd_flags) 2356 { 2357 u32 cmd; 2358 int i, rc = 0; 2359 2360 DBENTER(BCE_EXTREME_NVRAM); 2361 2362 /* Build the command word. */ 2363 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 2364 2365 /* Calculate the offset for buffered flash if translation is used. */ 2366 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2367 offset = ((offset / sc->bce_flash_info->page_size) << 2368 sc->bce_flash_info->page_bits) + 2369 (offset % sc->bce_flash_info->page_size); 2370 } 2371 2372 /* 2373 * Clear the DONE bit separately, set the address to read, 2374 * and issue the read. 2375 */ 2376 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2377 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2378 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2379 2380 /* Wait for completion. */ 2381 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 2382 u32 val; 2383 2384 DELAY(5); 2385 2386 val = REG_RD(sc, BCE_NVM_COMMAND); 2387 if (val & BCE_NVM_COMMAND_DONE) { 2388 val = REG_RD(sc, BCE_NVM_READ); 2389 2390 val = bce_be32toh(val); 2391 memcpy(ret_val, &val, 4); 2392 break; 2393 } 2394 } 2395 2396 /* Check for errors. */ 2397 if (i >= NVRAM_TIMEOUT_COUNT) { 2398 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at " 2399 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 2400 rc = EBUSY; 2401 } 2402 2403 DBEXIT(BCE_EXTREME_NVRAM); 2404 return(rc); 2405 } 2406 2407 #ifdef BCE_NVRAM_WRITE_SUPPORT 2408 /****************************************************************************/ 2409 /* Write a dword (32 bits) to NVRAM. */ 2410 /* */ 2411 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 2412 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 2413 /* enabled NVRAM write access. */ 2414 /* */ 2415 /* Returns: */ 2416 /* 0 on success, positive value on failure. */ 2417 /****************************************************************************/ 2418 static int 2419 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 2420 u32 cmd_flags) 2421 { 2422 u32 cmd, val32; 2423 int j, rc = 0; 2424 2425 DBENTER(BCE_VERBOSE_NVRAM); 2426 2427 /* Build the command word. */ 2428 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 2429 2430 /* Calculate the offset for buffered flash if translation is used. */ 2431 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2432 offset = ((offset / sc->bce_flash_info->page_size) << 2433 sc->bce_flash_info->page_bits) + 2434 (offset % sc->bce_flash_info->page_size); 2435 } 2436 2437 /* 2438 * Clear the DONE bit separately, convert NVRAM data to big-endian, 2439 * set the NVRAM address to write, and issue the write command 2440 */ 2441 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2442 memcpy(&val32, val, 4); 2443 val32 = htobe32(val32); 2444 REG_WR(sc, BCE_NVM_WRITE, val32); 2445 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2446 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2447 2448 /* Wait for completion. */ 2449 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2450 DELAY(5); 2451 2452 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 2453 break; 2454 } 2455 if (j >= NVRAM_TIMEOUT_COUNT) { 2456 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at " 2457 "offset 0x%08X\n", __FILE__, __LINE__, offset); 2458 rc = EBUSY; 2459 } 2460 2461 DBEXIT(BCE_VERBOSE_NVRAM); 2462 return (rc); 2463 } 2464 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2465 2466 /****************************************************************************/ 2467 /* Initialize NVRAM access. */ 2468 /* */ 2469 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 2470 /* access that device. */ 2471 /* */ 2472 /* Returns: */ 2473 /* 0 on success, positive value on failure. */ 2474 /****************************************************************************/ 2475 static int 2476 bce_init_nvram(struct bce_softc *sc) 2477 { 2478 u32 val; 2479 int j, entry_count, rc = 0; 2480 const struct flash_spec *flash; 2481 2482 DBENTER(BCE_VERBOSE_NVRAM); 2483 2484 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 2485 sc->bce_flash_info = &flash_5709; 2486 goto bce_init_nvram_get_flash_size; 2487 } 2488 2489 /* Determine the selected interface. */ 2490 val = REG_RD(sc, BCE_NVM_CFG1); 2491 2492 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 2493 2494 /* 2495 * Flash reconfiguration is required to support additional 2496 * NVRAM devices not directly supported in hardware. 2497 * Check if the flash interface was reconfigured 2498 * by the bootcode. 2499 */ 2500 2501 if (val & 0x40000000) { 2502 /* Flash interface reconfigured by bootcode. */ 2503 2504 DBPRINT(sc,BCE_INFO_LOAD, 2505 "bce_init_nvram(): Flash WAS reconfigured.\n"); 2506 2507 for (j = 0, flash = &flash_table[0]; j < entry_count; 2508 j++, flash++) { 2509 if ((val & FLASH_BACKUP_STRAP_MASK) == 2510 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 2511 sc->bce_flash_info = flash; 2512 break; 2513 } 2514 } 2515 } else { 2516 /* Flash interface not yet reconfigured. */ 2517 u32 mask; 2518 2519 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n", 2520 __FUNCTION__); 2521 2522 if (val & (1 << 23)) 2523 mask = FLASH_BACKUP_STRAP_MASK; 2524 else 2525 mask = FLASH_STRAP_MASK; 2526 2527 /* Look for the matching NVRAM device configuration data. */ 2528 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 2529 /* Check if the device matches any of the known devices. */ 2530 if ((val & mask) == (flash->strapping & mask)) { 2531 /* Found a device match. */ 2532 sc->bce_flash_info = flash; 2533 2534 /* Request access to the flash interface. */ 2535 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2536 return rc; 2537 2538 /* Reconfigure the flash interface. */ 2539 bce_enable_nvram_access(sc); 2540 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 2541 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 2542 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 2543 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 2544 bce_disable_nvram_access(sc); 2545 bce_release_nvram_lock(sc); 2546 2547 break; 2548 } 2549 } 2550 } 2551 2552 /* Check if a matching device was found. */ 2553 if (j == entry_count) { 2554 sc->bce_flash_info = NULL; 2555 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 2556 __FILE__, __LINE__); 2557 DBEXIT(BCE_VERBOSE_NVRAM); 2558 return (ENODEV); 2559 } 2560 2561 bce_init_nvram_get_flash_size: 2562 /* Write the flash config data to the shared memory interface. */ 2563 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2); 2564 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 2565 if (val) 2566 sc->bce_flash_size = val; 2567 else 2568 sc->bce_flash_size = sc->bce_flash_info->total_size; 2569 2570 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n", 2571 __FUNCTION__, sc->bce_flash_info->name, 2572 sc->bce_flash_info->total_size); 2573 2574 DBEXIT(BCE_VERBOSE_NVRAM); 2575 return rc; 2576 } 2577 2578 /****************************************************************************/ 2579 /* Read an arbitrary range of data from NVRAM. */ 2580 /* */ 2581 /* Prepares the NVRAM interface for access and reads the requested data */ 2582 /* into the supplied buffer. */ 2583 /* */ 2584 /* Returns: */ 2585 /* 0 on success and the data read, positive value on failure. */ 2586 /****************************************************************************/ 2587 static int 2588 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 2589 int buf_size) 2590 { 2591 int rc = 0; 2592 u32 cmd_flags, offset32, len32, extra; 2593 2594 DBENTER(BCE_VERBOSE_NVRAM); 2595 2596 if (buf_size == 0) 2597 goto bce_nvram_read_exit; 2598 2599 /* Request access to the flash interface. */ 2600 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2601 goto bce_nvram_read_exit; 2602 2603 /* Enable access to flash interface */ 2604 bce_enable_nvram_access(sc); 2605 2606 len32 = buf_size; 2607 offset32 = offset; 2608 extra = 0; 2609 2610 cmd_flags = 0; 2611 2612 if (offset32 & 3) { 2613 u8 buf[4]; 2614 u32 pre_len; 2615 2616 offset32 &= ~3; 2617 pre_len = 4 - (offset & 3); 2618 2619 if (pre_len >= len32) { 2620 pre_len = len32; 2621 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 2622 } 2623 else { 2624 cmd_flags = BCE_NVM_COMMAND_FIRST; 2625 } 2626 2627 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2628 2629 if (rc) 2630 return rc; 2631 2632 memcpy(ret_buf, buf + (offset & 3), pre_len); 2633 2634 offset32 += 4; 2635 ret_buf += pre_len; 2636 len32 -= pre_len; 2637 } 2638 2639 if (len32 & 3) { 2640 extra = 4 - (len32 & 3); 2641 len32 = (len32 + 4) & ~3; 2642 } 2643 2644 if (len32 == 4) { 2645 u8 buf[4]; 2646 2647 if (cmd_flags) 2648 cmd_flags = BCE_NVM_COMMAND_LAST; 2649 else 2650 cmd_flags = BCE_NVM_COMMAND_FIRST | 2651 BCE_NVM_COMMAND_LAST; 2652 2653 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2654 2655 memcpy(ret_buf, buf, 4 - extra); 2656 } 2657 else if (len32 > 0) { 2658 u8 buf[4]; 2659 2660 /* Read the first word. */ 2661 if (cmd_flags) 2662 cmd_flags = 0; 2663 else 2664 cmd_flags = BCE_NVM_COMMAND_FIRST; 2665 2666 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 2667 2668 /* Advance to the next dword. */ 2669 offset32 += 4; 2670 ret_buf += 4; 2671 len32 -= 4; 2672 2673 while (len32 > 4 && rc == 0) { 2674 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 2675 2676 /* Advance to the next dword. */ 2677 offset32 += 4; 2678 ret_buf += 4; 2679 len32 -= 4; 2680 } 2681 2682 if (rc) 2683 goto bce_nvram_read_locked_exit; 2684 2685 cmd_flags = BCE_NVM_COMMAND_LAST; 2686 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2687 2688 memcpy(ret_buf, buf, 4 - extra); 2689 } 2690 2691 bce_nvram_read_locked_exit: 2692 /* Disable access to flash interface and release the lock. */ 2693 bce_disable_nvram_access(sc); 2694 bce_release_nvram_lock(sc); 2695 2696 bce_nvram_read_exit: 2697 DBEXIT(BCE_VERBOSE_NVRAM); 2698 return rc; 2699 } 2700 2701 #ifdef BCE_NVRAM_WRITE_SUPPORT 2702 /****************************************************************************/ 2703 /* Write an arbitrary range of data from NVRAM. */ 2704 /* */ 2705 /* Prepares the NVRAM interface for write access and writes the requested */ 2706 /* data from the supplied buffer. The caller is responsible for */ 2707 /* calculating any appropriate CRCs. */ 2708 /* */ 2709 /* Returns: */ 2710 /* 0 on success, positive value on failure. */ 2711 /****************************************************************************/ 2712 static int 2713 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 2714 int buf_size) 2715 { 2716 u32 written, offset32, len32; 2717 u8 *buf, start[4], end[4]; 2718 int rc = 0; 2719 int align_start, align_end; 2720 2721 DBENTER(BCE_VERBOSE_NVRAM); 2722 2723 buf = data_buf; 2724 offset32 = offset; 2725 len32 = buf_size; 2726 align_start = align_end = 0; 2727 2728 if ((align_start = (offset32 & 3))) { 2729 offset32 &= ~3; 2730 len32 += align_start; 2731 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 2732 goto bce_nvram_write_exit; 2733 } 2734 2735 if (len32 & 3) { 2736 if ((len32 > 4) || !align_start) { 2737 align_end = 4 - (len32 & 3); 2738 len32 += align_end; 2739 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 2740 end, 4))) { 2741 goto bce_nvram_write_exit; 2742 } 2743 } 2744 } 2745 2746 if (align_start || align_end) { 2747 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 2748 if (buf == NULL) { 2749 rc = ENOMEM; 2750 goto bce_nvram_write_exit; 2751 } 2752 2753 if (align_start) { 2754 memcpy(buf, start, 4); 2755 } 2756 2757 if (align_end) { 2758 memcpy(buf + len32 - 4, end, 4); 2759 } 2760 memcpy(buf + align_start, data_buf, buf_size); 2761 } 2762 2763 written = 0; 2764 while ((written < len32) && (rc == 0)) { 2765 u32 page_start, page_end, data_start, data_end; 2766 u32 addr, cmd_flags; 2767 int i; 2768 u8 flash_buffer[264]; 2769 2770 /* Find the page_start addr */ 2771 page_start = offset32 + written; 2772 page_start -= (page_start % sc->bce_flash_info->page_size); 2773 /* Find the page_end addr */ 2774 page_end = page_start + sc->bce_flash_info->page_size; 2775 /* Find the data_start addr */ 2776 data_start = (written == 0) ? offset32 : page_start; 2777 /* Find the data_end addr */ 2778 data_end = (page_end > offset32 + len32) ? 2779 (offset32 + len32) : page_end; 2780 2781 /* Request access to the flash interface. */ 2782 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2783 goto bce_nvram_write_exit; 2784 2785 /* Enable access to flash interface */ 2786 bce_enable_nvram_access(sc); 2787 2788 cmd_flags = BCE_NVM_COMMAND_FIRST; 2789 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2790 int j; 2791 2792 /* Read the whole page into the buffer 2793 * (non-buffer flash only) */ 2794 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 2795 if (j == (sc->bce_flash_info->page_size - 4)) { 2796 cmd_flags |= BCE_NVM_COMMAND_LAST; 2797 } 2798 rc = bce_nvram_read_dword(sc, 2799 page_start + j, 2800 &flash_buffer[j], 2801 cmd_flags); 2802 2803 if (rc) 2804 goto bce_nvram_write_locked_exit; 2805 2806 cmd_flags = 0; 2807 } 2808 } 2809 2810 /* Enable writes to flash interface (unlock write-protect) */ 2811 if ((rc = bce_enable_nvram_write(sc)) != 0) 2812 goto bce_nvram_write_locked_exit; 2813 2814 /* Erase the page */ 2815 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 2816 goto bce_nvram_write_locked_exit; 2817 2818 /* Re-enable the write again for the actual write */ 2819 bce_enable_nvram_write(sc); 2820 2821 /* Loop to write back the buffer data from page_start to 2822 * data_start */ 2823 i = 0; 2824 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2825 for (addr = page_start; addr < data_start; 2826 addr += 4, i += 4) { 2827 rc = bce_nvram_write_dword(sc, addr, 2828 &flash_buffer[i], cmd_flags); 2829 2830 if (rc != 0) 2831 goto bce_nvram_write_locked_exit; 2832 2833 cmd_flags = 0; 2834 } 2835 } 2836 2837 /* Loop to write the new data from data_start to data_end */ 2838 for (addr = data_start; addr < data_end; addr += 4, i++) { 2839 if ((addr == page_end - 4) || 2840 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) && 2841 (addr == data_end - 4))) { 2842 cmd_flags |= BCE_NVM_COMMAND_LAST; 2843 } 2844 rc = bce_nvram_write_dword(sc, addr, buf, 2845 cmd_flags); 2846 2847 if (rc != 0) 2848 goto bce_nvram_write_locked_exit; 2849 2850 cmd_flags = 0; 2851 buf += 4; 2852 } 2853 2854 /* Loop to write back the buffer data from data_end 2855 * to page_end */ 2856 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2857 for (addr = data_end; addr < page_end; 2858 addr += 4, i += 4) { 2859 if (addr == page_end-4) { 2860 cmd_flags = BCE_NVM_COMMAND_LAST; 2861 } 2862 rc = bce_nvram_write_dword(sc, addr, 2863 &flash_buffer[i], cmd_flags); 2864 2865 if (rc != 0) 2866 goto bce_nvram_write_locked_exit; 2867 2868 cmd_flags = 0; 2869 } 2870 } 2871 2872 /* Disable writes to flash interface (lock write-protect) */ 2873 bce_disable_nvram_write(sc); 2874 2875 /* Disable access to flash interface */ 2876 bce_disable_nvram_access(sc); 2877 bce_release_nvram_lock(sc); 2878 2879 /* Increment written */ 2880 written += data_end - data_start; 2881 } 2882 2883 goto bce_nvram_write_exit; 2884 2885 bce_nvram_write_locked_exit: 2886 bce_disable_nvram_write(sc); 2887 bce_disable_nvram_access(sc); 2888 bce_release_nvram_lock(sc); 2889 2890 bce_nvram_write_exit: 2891 if (align_start || align_end) 2892 free(buf, M_DEVBUF); 2893 2894 DBEXIT(BCE_VERBOSE_NVRAM); 2895 return (rc); 2896 } 2897 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2898 2899 /****************************************************************************/ 2900 /* Verifies that NVRAM is accessible and contains valid data. */ 2901 /* */ 2902 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2903 /* correct. */ 2904 /* */ 2905 /* Returns: */ 2906 /* 0 on success, positive value on failure. */ 2907 /****************************************************************************/ 2908 static int 2909 bce_nvram_test(struct bce_softc *sc) 2910 { 2911 u32 buf[BCE_NVRAM_SIZE / 4]; 2912 u8 *data = (u8 *) buf; 2913 int rc = 0; 2914 u32 magic, csum; 2915 2916 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2917 2918 /* 2919 * Check that the device NVRAM is valid by reading 2920 * the magic value at offset 0. 2921 */ 2922 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) { 2923 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", 2924 __FILE__, __LINE__); 2925 goto bce_nvram_test_exit; 2926 } 2927 2928 /* 2929 * Verify that offset 0 of the NVRAM contains 2930 * a valid magic number. 2931 */ 2932 magic = bce_be32toh(buf[0]); 2933 if (magic != BCE_NVRAM_MAGIC) { 2934 rc = ENODEV; 2935 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! " 2936 "Expected: 0x%08X, Found: 0x%08X\n", 2937 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 2938 goto bce_nvram_test_exit; 2939 } 2940 2941 /* 2942 * Verify that the device NVRAM includes valid 2943 * configuration data. 2944 */ 2945 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) { 2946 BCE_PRINTF("%s(%d): Unable to read manufacturing " 2947 "Information from NVRAM!\n", __FILE__, __LINE__); 2948 goto bce_nvram_test_exit; 2949 } 2950 2951 csum = ether_crc32_le(data, 0x100); 2952 if (csum != BCE_CRC32_RESIDUAL) { 2953 rc = ENODEV; 2954 BCE_PRINTF("%s(%d): Invalid manufacturing information " 2955 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2956 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2957 goto bce_nvram_test_exit; 2958 } 2959 2960 csum = ether_crc32_le(data + 0x100, 0x100); 2961 if (csum != BCE_CRC32_RESIDUAL) { 2962 rc = ENODEV; 2963 BCE_PRINTF("%s(%d): Invalid feature configuration " 2964 "information NVRAM CRC! Expected: 0x%08X, " 2965 "Found: 08%08X\n", __FILE__, __LINE__, 2966 BCE_CRC32_RESIDUAL, csum); 2967 } 2968 2969 bce_nvram_test_exit: 2970 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2971 return rc; 2972 } 2973 2974 /****************************************************************************/ 2975 /* Calculates the size of the buffers to allocate based on the MTU. */ 2976 /* */ 2977 /* Returns: */ 2978 /* Nothing. */ 2979 /****************************************************************************/ 2980 static void 2981 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu) 2982 { 2983 DBENTER(BCE_VERBOSE_LOAD); 2984 2985 /* Use a single allocation type when header splitting enabled. */ 2986 if (bce_hdr_split == TRUE) { 2987 sc->rx_bd_mbuf_alloc_size = MHLEN; 2988 /* Make sure offset is 16 byte aligned for hardware. */ 2989 sc->rx_bd_mbuf_align_pad = 2990 roundup2(MSIZE - MHLEN, 16) - (MSIZE - MHLEN); 2991 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 2992 sc->rx_bd_mbuf_align_pad; 2993 } else { 2994 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2995 ETHER_CRC_LEN) > MCLBYTES) { 2996 /* Setup for jumbo RX buffer allocations. */ 2997 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES; 2998 sc->rx_bd_mbuf_align_pad = 2999 roundup2(MJUM9BYTES, 16) - MJUM9BYTES; 3000 sc->rx_bd_mbuf_data_len = 3001 sc->rx_bd_mbuf_alloc_size - 3002 sc->rx_bd_mbuf_align_pad; 3003 } else { 3004 /* Setup for standard RX buffer allocations. */ 3005 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 3006 sc->rx_bd_mbuf_align_pad = 3007 roundup2(MCLBYTES, 16) - MCLBYTES; 3008 sc->rx_bd_mbuf_data_len = 3009 sc->rx_bd_mbuf_alloc_size - 3010 sc->rx_bd_mbuf_align_pad; 3011 } 3012 } 3013 3014 // DBPRINT(sc, BCE_INFO_LOAD, 3015 DBPRINT(sc, BCE_WARN, 3016 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, " 3017 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__, 3018 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len, 3019 sc->rx_bd_mbuf_align_pad); 3020 3021 DBEXIT(BCE_VERBOSE_LOAD); 3022 } 3023 3024 /****************************************************************************/ 3025 /* Identifies the current media type of the controller and sets the PHY */ 3026 /* address. */ 3027 /* */ 3028 /* Returns: */ 3029 /* Nothing. */ 3030 /****************************************************************************/ 3031 static void 3032 bce_get_media(struct bce_softc *sc) 3033 { 3034 u32 val; 3035 3036 DBENTER(BCE_VERBOSE_PHY); 3037 3038 /* Assume PHY address for copper controllers. */ 3039 sc->bce_phy_addr = 1; 3040 3041 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3042 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL); 3043 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID; 3044 u32 strap; 3045 3046 /* 3047 * The BCM5709S is software configurable 3048 * for Copper or SerDes operation. 3049 */ 3050 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 3051 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3052 "for copper.\n"); 3053 goto bce_get_media_exit; 3054 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 3055 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3056 "for dual media.\n"); 3057 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3058 goto bce_get_media_exit; 3059 } 3060 3061 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 3062 strap = (val & 3063 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 3064 else 3065 strap = (val & 3066 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 3067 3068 if (pci_get_function(sc->bce_dev) == 0) { 3069 switch (strap) { 3070 case 0x4: 3071 case 0x5: 3072 case 0x6: 3073 DBPRINT(sc, BCE_INFO_LOAD, 3074 "BCM5709 s/w configured for SerDes.\n"); 3075 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3076 break; 3077 default: 3078 DBPRINT(sc, BCE_INFO_LOAD, 3079 "BCM5709 s/w configured for Copper.\n"); 3080 break; 3081 } 3082 } else { 3083 switch (strap) { 3084 case 0x1: 3085 case 0x2: 3086 case 0x4: 3087 DBPRINT(sc, BCE_INFO_LOAD, 3088 "BCM5709 s/w configured for SerDes.\n"); 3089 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3090 break; 3091 default: 3092 DBPRINT(sc, BCE_INFO_LOAD, 3093 "BCM5709 s/w configured for Copper.\n"); 3094 break; 3095 } 3096 } 3097 3098 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) 3099 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3100 3101 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 3102 sc->bce_flags |= BCE_NO_WOL_FLAG; 3103 3104 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 3105 sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG; 3106 3107 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 3108 /* 5708S/09S/16S use a separate PHY for SerDes. */ 3109 sc->bce_phy_addr = 2; 3110 3111 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 3112 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 3113 sc->bce_phy_flags |= 3114 BCE_PHY_2_5G_CAPABLE_FLAG; 3115 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb " 3116 "capable adapter\n"); 3117 } 3118 } 3119 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) || 3120 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) 3121 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG; 3122 3123 bce_get_media_exit: 3124 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY), 3125 "Using PHY address %d.\n", sc->bce_phy_addr); 3126 3127 DBEXIT(BCE_VERBOSE_PHY); 3128 } 3129 3130 /****************************************************************************/ 3131 /* Performs PHY initialization required before MII drivers access the */ 3132 /* device. */ 3133 /* */ 3134 /* Returns: */ 3135 /* Nothing. */ 3136 /****************************************************************************/ 3137 static void 3138 bce_init_media(struct bce_softc *sc) 3139 { 3140 if ((sc->bce_phy_flags & (BCE_PHY_IEEE_CLAUSE_45_FLAG | 3141 BCE_PHY_REMOTE_CAP_FLAG)) == BCE_PHY_IEEE_CLAUSE_45_FLAG) { 3142 /* 3143 * Configure 5709S/5716S PHYs to use traditional IEEE 3144 * Clause 22 method. Otherwise we have no way to attach 3145 * the PHY in mii(4) layer. PHY specific configuration 3146 * is done in mii layer. 3147 */ 3148 3149 /* Select auto-negotiation MMD of the PHY. */ 3150 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3151 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 3152 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3153 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 3154 3155 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */ 3156 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3157 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 3158 } 3159 } 3160 3161 /****************************************************************************/ 3162 /* Free any DMA memory owned by the driver. */ 3163 /* */ 3164 /* Scans through each data structure that requires DMA memory and frees */ 3165 /* the memory if allocated. */ 3166 /* */ 3167 /* Returns: */ 3168 /* Nothing. */ 3169 /****************************************************************************/ 3170 static void 3171 bce_dma_free(struct bce_softc *sc) 3172 { 3173 int i; 3174 3175 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3176 3177 /* Free, unmap, and destroy the status block. */ 3178 if (sc->status_block_paddr != 0) { 3179 bus_dmamap_unload( 3180 sc->status_tag, 3181 sc->status_map); 3182 sc->status_block_paddr = 0; 3183 } 3184 3185 if (sc->status_block != NULL) { 3186 bus_dmamem_free( 3187 sc->status_tag, 3188 sc->status_block, 3189 sc->status_map); 3190 sc->status_block = NULL; 3191 } 3192 3193 if (sc->status_tag != NULL) { 3194 bus_dma_tag_destroy(sc->status_tag); 3195 sc->status_tag = NULL; 3196 } 3197 3198 /* Free, unmap, and destroy the statistics block. */ 3199 if (sc->stats_block_paddr != 0) { 3200 bus_dmamap_unload( 3201 sc->stats_tag, 3202 sc->stats_map); 3203 sc->stats_block_paddr = 0; 3204 } 3205 3206 if (sc->stats_block != NULL) { 3207 bus_dmamem_free( 3208 sc->stats_tag, 3209 sc->stats_block, 3210 sc->stats_map); 3211 sc->stats_block = NULL; 3212 } 3213 3214 if (sc->stats_tag != NULL) { 3215 bus_dma_tag_destroy(sc->stats_tag); 3216 sc->stats_tag = NULL; 3217 } 3218 3219 /* Free, unmap and destroy all context memory pages. */ 3220 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3221 for (i = 0; i < sc->ctx_pages; i++ ) { 3222 if (sc->ctx_paddr[i] != 0) { 3223 bus_dmamap_unload( 3224 sc->ctx_tag, 3225 sc->ctx_map[i]); 3226 sc->ctx_paddr[i] = 0; 3227 } 3228 3229 if (sc->ctx_block[i] != NULL) { 3230 bus_dmamem_free( 3231 sc->ctx_tag, 3232 sc->ctx_block[i], 3233 sc->ctx_map[i]); 3234 sc->ctx_block[i] = NULL; 3235 } 3236 } 3237 3238 /* Destroy the context memory tag. */ 3239 if (sc->ctx_tag != NULL) { 3240 bus_dma_tag_destroy(sc->ctx_tag); 3241 sc->ctx_tag = NULL; 3242 } 3243 } 3244 3245 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 3246 for (i = 0; i < sc->tx_pages; i++ ) { 3247 if (sc->tx_bd_chain_paddr[i] != 0) { 3248 bus_dmamap_unload( 3249 sc->tx_bd_chain_tag, 3250 sc->tx_bd_chain_map[i]); 3251 sc->tx_bd_chain_paddr[i] = 0; 3252 } 3253 3254 if (sc->tx_bd_chain[i] != NULL) { 3255 bus_dmamem_free( 3256 sc->tx_bd_chain_tag, 3257 sc->tx_bd_chain[i], 3258 sc->tx_bd_chain_map[i]); 3259 sc->tx_bd_chain[i] = NULL; 3260 } 3261 } 3262 3263 /* Destroy the TX buffer descriptor tag. */ 3264 if (sc->tx_bd_chain_tag != NULL) { 3265 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 3266 sc->tx_bd_chain_tag = NULL; 3267 } 3268 3269 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 3270 for (i = 0; i < sc->rx_pages; i++ ) { 3271 if (sc->rx_bd_chain_paddr[i] != 0) { 3272 bus_dmamap_unload( 3273 sc->rx_bd_chain_tag, 3274 sc->rx_bd_chain_map[i]); 3275 sc->rx_bd_chain_paddr[i] = 0; 3276 } 3277 3278 if (sc->rx_bd_chain[i] != NULL) { 3279 bus_dmamem_free( 3280 sc->rx_bd_chain_tag, 3281 sc->rx_bd_chain[i], 3282 sc->rx_bd_chain_map[i]); 3283 sc->rx_bd_chain[i] = NULL; 3284 } 3285 } 3286 3287 /* Destroy the RX buffer descriptor tag. */ 3288 if (sc->rx_bd_chain_tag != NULL) { 3289 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 3290 sc->rx_bd_chain_tag = NULL; 3291 } 3292 3293 /* Free, unmap and destroy all page buffer descriptor chain pages. */ 3294 if (bce_hdr_split == TRUE) { 3295 for (i = 0; i < sc->pg_pages; i++ ) { 3296 if (sc->pg_bd_chain_paddr[i] != 0) { 3297 bus_dmamap_unload( 3298 sc->pg_bd_chain_tag, 3299 sc->pg_bd_chain_map[i]); 3300 sc->pg_bd_chain_paddr[i] = 0; 3301 } 3302 3303 if (sc->pg_bd_chain[i] != NULL) { 3304 bus_dmamem_free( 3305 sc->pg_bd_chain_tag, 3306 sc->pg_bd_chain[i], 3307 sc->pg_bd_chain_map[i]); 3308 sc->pg_bd_chain[i] = NULL; 3309 } 3310 } 3311 3312 /* Destroy the page buffer descriptor tag. */ 3313 if (sc->pg_bd_chain_tag != NULL) { 3314 bus_dma_tag_destroy(sc->pg_bd_chain_tag); 3315 sc->pg_bd_chain_tag = NULL; 3316 } 3317 } 3318 3319 /* Unload and destroy the TX mbuf maps. */ 3320 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 3321 if (sc->tx_mbuf_map[i] != NULL) { 3322 bus_dmamap_unload(sc->tx_mbuf_tag, 3323 sc->tx_mbuf_map[i]); 3324 bus_dmamap_destroy(sc->tx_mbuf_tag, 3325 sc->tx_mbuf_map[i]); 3326 sc->tx_mbuf_map[i] = NULL; 3327 } 3328 } 3329 3330 /* Destroy the TX mbuf tag. */ 3331 if (sc->tx_mbuf_tag != NULL) { 3332 bus_dma_tag_destroy(sc->tx_mbuf_tag); 3333 sc->tx_mbuf_tag = NULL; 3334 } 3335 3336 /* Unload and destroy the RX mbuf maps. */ 3337 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 3338 if (sc->rx_mbuf_map[i] != NULL) { 3339 bus_dmamap_unload(sc->rx_mbuf_tag, 3340 sc->rx_mbuf_map[i]); 3341 bus_dmamap_destroy(sc->rx_mbuf_tag, 3342 sc->rx_mbuf_map[i]); 3343 sc->rx_mbuf_map[i] = NULL; 3344 } 3345 } 3346 3347 /* Destroy the RX mbuf tag. */ 3348 if (sc->rx_mbuf_tag != NULL) { 3349 bus_dma_tag_destroy(sc->rx_mbuf_tag); 3350 sc->rx_mbuf_tag = NULL; 3351 } 3352 3353 /* Unload and destroy the page mbuf maps. */ 3354 if (bce_hdr_split == TRUE) { 3355 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 3356 if (sc->pg_mbuf_map[i] != NULL) { 3357 bus_dmamap_unload(sc->pg_mbuf_tag, 3358 sc->pg_mbuf_map[i]); 3359 bus_dmamap_destroy(sc->pg_mbuf_tag, 3360 sc->pg_mbuf_map[i]); 3361 sc->pg_mbuf_map[i] = NULL; 3362 } 3363 } 3364 3365 /* Destroy the page mbuf tag. */ 3366 if (sc->pg_mbuf_tag != NULL) { 3367 bus_dma_tag_destroy(sc->pg_mbuf_tag); 3368 sc->pg_mbuf_tag = NULL; 3369 } 3370 } 3371 3372 /* Destroy the parent tag */ 3373 if (sc->parent_tag != NULL) { 3374 bus_dma_tag_destroy(sc->parent_tag); 3375 sc->parent_tag = NULL; 3376 } 3377 3378 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3379 } 3380 3381 /****************************************************************************/ 3382 /* Get DMA memory from the OS. */ 3383 /* */ 3384 /* Validates that the OS has provided DMA buffers in response to a */ 3385 /* bus_dmamap_load() call and saves the physical address of those buffers. */ 3386 /* When the callback is used the OS will return 0 for the mapping function */ 3387 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 3388 /* failures back to the caller. */ 3389 /* */ 3390 /* Returns: */ 3391 /* Nothing. */ 3392 /****************************************************************************/ 3393 static void 3394 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3395 { 3396 bus_addr_t *busaddr = arg; 3397 3398 KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!", 3399 __FUNCTION__, nseg)); 3400 /* Simulate a mapping failure. */ 3401 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control), 3402 error = ENOMEM); 3403 3404 /* ToDo: How to increment debug sim_count variable here? */ 3405 3406 /* Check for an error and signal the caller that an error occurred. */ 3407 if (error) { 3408 *busaddr = 0; 3409 } else { 3410 *busaddr = segs->ds_addr; 3411 } 3412 } 3413 3414 /****************************************************************************/ 3415 /* Allocate any DMA memory needed by the driver. */ 3416 /* */ 3417 /* Allocates DMA memory needed for the various global structures needed by */ 3418 /* hardware. */ 3419 /* */ 3420 /* Memory alignment requirements: */ 3421 /* +-----------------+----------+----------+----------+----------+ */ 3422 /* | | 5706 | 5708 | 5709 | 5716 | */ 3423 /* +-----------------+----------+----------+----------+----------+ */ 3424 /* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3425 /* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3426 /* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */ 3427 /* |PG Buffers | none | none | none | none | */ 3428 /* |TX Buffers | none | none | none | none | */ 3429 /* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */ 3430 /* |Context Memory | | | | | */ 3431 /* +-----------------+----------+----------+----------+----------+ */ 3432 /* */ 3433 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */ 3434 /* */ 3435 /* Returns: */ 3436 /* 0 for success, positive value for failure. */ 3437 /****************************************************************************/ 3438 static int 3439 bce_dma_alloc(device_t dev) 3440 { 3441 struct bce_softc *sc; 3442 int i, error, rc = 0; 3443 bus_size_t max_size, max_seg_size; 3444 int max_segments; 3445 3446 sc = device_get_softc(dev); 3447 3448 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3449 3450 /* 3451 * Allocate the parent bus DMA tag appropriate for PCI. 3452 */ 3453 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY, 3454 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3455 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3456 &sc->parent_tag)) { 3457 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 3458 __FILE__, __LINE__); 3459 rc = ENOMEM; 3460 goto bce_dma_alloc_exit; 3461 } 3462 3463 /* 3464 * Create a DMA tag for the status block, allocate and clear the 3465 * memory, map the memory into DMA space, and fetch the physical 3466 * address of the block. 3467 */ 3468 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3469 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3470 NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ, 3471 0, NULL, NULL, &sc->status_tag)) { 3472 BCE_PRINTF("%s(%d): Could not allocate status block " 3473 "DMA tag!\n", __FILE__, __LINE__); 3474 rc = ENOMEM; 3475 goto bce_dma_alloc_exit; 3476 } 3477 3478 if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block, 3479 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3480 &sc->status_map)) { 3481 BCE_PRINTF("%s(%d): Could not allocate status block " 3482 "DMA memory!\n", __FILE__, __LINE__); 3483 rc = ENOMEM; 3484 goto bce_dma_alloc_exit; 3485 } 3486 3487 error = bus_dmamap_load(sc->status_tag, sc->status_map, 3488 sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr, 3489 &sc->status_block_paddr, BUS_DMA_NOWAIT); 3490 3491 if (error || sc->status_block_paddr == 0) { 3492 BCE_PRINTF("%s(%d): Could not map status block " 3493 "DMA memory!\n", __FILE__, __LINE__); 3494 rc = ENOMEM; 3495 goto bce_dma_alloc_exit; 3496 } 3497 3498 DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n", 3499 __FUNCTION__, (uintmax_t) sc->status_block_paddr); 3500 3501 /* 3502 * Create a DMA tag for the statistics block, allocate and clear the 3503 * memory, map the memory into DMA space, and fetch the physical 3504 * address of the block. 3505 */ 3506 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3507 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3508 NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ, 3509 0, NULL, NULL, &sc->stats_tag)) { 3510 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3511 "DMA tag!\n", __FILE__, __LINE__); 3512 rc = ENOMEM; 3513 goto bce_dma_alloc_exit; 3514 } 3515 3516 if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block, 3517 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) { 3518 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3519 "DMA memory!\n", __FILE__, __LINE__); 3520 rc = ENOMEM; 3521 goto bce_dma_alloc_exit; 3522 } 3523 3524 error = bus_dmamap_load(sc->stats_tag, sc->stats_map, 3525 sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr, 3526 &sc->stats_block_paddr, BUS_DMA_NOWAIT); 3527 3528 if (error || sc->stats_block_paddr == 0) { 3529 BCE_PRINTF("%s(%d): Could not map statistics block " 3530 "DMA memory!\n", __FILE__, __LINE__); 3531 rc = ENOMEM; 3532 goto bce_dma_alloc_exit; 3533 } 3534 3535 DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n", 3536 __FUNCTION__, (uintmax_t) sc->stats_block_paddr); 3537 3538 /* BCM5709 uses host memory as cache for context memory. */ 3539 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3540 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 3541 if (sc->ctx_pages == 0) 3542 sc->ctx_pages = 1; 3543 3544 DBRUNIF((sc->ctx_pages > 512), 3545 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n", 3546 __FILE__, __LINE__, sc->ctx_pages)); 3547 3548 /* 3549 * Create a DMA tag for the context pages, 3550 * allocate and clear the memory, map the 3551 * memory into DMA space, and fetch the 3552 * physical address of the block. 3553 */ 3554 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3555 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3556 NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE, 3557 0, NULL, NULL, &sc->ctx_tag)) { 3558 BCE_PRINTF("%s(%d): Could not allocate CTX " 3559 "DMA tag!\n", __FILE__, __LINE__); 3560 rc = ENOMEM; 3561 goto bce_dma_alloc_exit; 3562 } 3563 3564 for (i = 0; i < sc->ctx_pages; i++) { 3565 if(bus_dmamem_alloc(sc->ctx_tag, 3566 (void **)&sc->ctx_block[i], 3567 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3568 &sc->ctx_map[i])) { 3569 BCE_PRINTF("%s(%d): Could not allocate CTX " 3570 "DMA memory!\n", __FILE__, __LINE__); 3571 rc = ENOMEM; 3572 goto bce_dma_alloc_exit; 3573 } 3574 3575 error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i], 3576 sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr, 3577 &sc->ctx_paddr[i], BUS_DMA_NOWAIT); 3578 3579 if (error || sc->ctx_paddr[i] == 0) { 3580 BCE_PRINTF("%s(%d): Could not map CTX " 3581 "DMA memory!\n", __FILE__, __LINE__); 3582 rc = ENOMEM; 3583 goto bce_dma_alloc_exit; 3584 } 3585 3586 DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] " 3587 "= 0x%jX\n", __FUNCTION__, i, 3588 (uintmax_t) sc->ctx_paddr[i]); 3589 } 3590 } 3591 3592 /* 3593 * Create a DMA tag for the TX buffer descriptor chain, 3594 * allocate and clear the memory, and fetch the 3595 * physical address of the block. 3596 */ 3597 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY, 3598 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3599 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0, 3600 NULL, NULL, &sc->tx_bd_chain_tag)) { 3601 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3602 "chain DMA tag!\n", __FILE__, __LINE__); 3603 rc = ENOMEM; 3604 goto bce_dma_alloc_exit; 3605 } 3606 3607 for (i = 0; i < sc->tx_pages; i++) { 3608 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 3609 (void **)&sc->tx_bd_chain[i], 3610 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3611 &sc->tx_bd_chain_map[i])) { 3612 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3613 "chain DMA memory!\n", __FILE__, __LINE__); 3614 rc = ENOMEM; 3615 goto bce_dma_alloc_exit; 3616 } 3617 3618 error = bus_dmamap_load(sc->tx_bd_chain_tag, 3619 sc->tx_bd_chain_map[i], sc->tx_bd_chain[i], 3620 BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3621 &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3622 3623 if (error || sc->tx_bd_chain_paddr[i] == 0) { 3624 BCE_PRINTF("%s(%d): Could not map TX descriptor " 3625 "chain DMA memory!\n", __FILE__, __LINE__); 3626 rc = ENOMEM; 3627 goto bce_dma_alloc_exit; 3628 } 3629 3630 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = " 3631 "0x%jX\n", __FUNCTION__, i, 3632 (uintmax_t) sc->tx_bd_chain_paddr[i]); 3633 } 3634 3635 /* Check the required size before mapping to conserve resources. */ 3636 if (bce_tso_enable) { 3637 max_size = BCE_TSO_MAX_SIZE; 3638 max_segments = BCE_MAX_SEGMENTS; 3639 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 3640 } else { 3641 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 3642 max_segments = BCE_MAX_SEGMENTS; 3643 max_seg_size = MCLBYTES; 3644 } 3645 3646 /* Create a DMA tag for TX mbufs. */ 3647 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3648 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size, 3649 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) { 3650 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 3651 __FILE__, __LINE__); 3652 rc = ENOMEM; 3653 goto bce_dma_alloc_exit; 3654 } 3655 3656 /* Create DMA maps for the TX mbufs clusters. */ 3657 for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) { 3658 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 3659 &sc->tx_mbuf_map[i])) { 3660 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA " 3661 "map!\n", __FILE__, __LINE__); 3662 rc = ENOMEM; 3663 goto bce_dma_alloc_exit; 3664 } 3665 } 3666 3667 /* 3668 * Create a DMA tag for the RX buffer descriptor chain, 3669 * allocate and clear the memory, and fetch the physical 3670 * address of the blocks. 3671 */ 3672 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3673 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, 3674 sc->max_bus_addr, NULL, NULL, 3675 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ, 3676 0, NULL, NULL, &sc->rx_bd_chain_tag)) { 3677 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 3678 "DMA tag!\n", __FILE__, __LINE__); 3679 rc = ENOMEM; 3680 goto bce_dma_alloc_exit; 3681 } 3682 3683 for (i = 0; i < sc->rx_pages; i++) { 3684 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 3685 (void **)&sc->rx_bd_chain[i], 3686 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3687 &sc->rx_bd_chain_map[i])) { 3688 BCE_PRINTF("%s(%d): Could not allocate RX descriptor " 3689 "chain DMA memory!\n", __FILE__, __LINE__); 3690 rc = ENOMEM; 3691 goto bce_dma_alloc_exit; 3692 } 3693 3694 error = bus_dmamap_load(sc->rx_bd_chain_tag, 3695 sc->rx_bd_chain_map[i], sc->rx_bd_chain[i], 3696 BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3697 &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3698 3699 if (error || sc->rx_bd_chain_paddr[i] == 0) { 3700 BCE_PRINTF("%s(%d): Could not map RX descriptor " 3701 "chain DMA memory!\n", __FILE__, __LINE__); 3702 rc = ENOMEM; 3703 goto bce_dma_alloc_exit; 3704 } 3705 3706 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = " 3707 "0x%jX\n", __FUNCTION__, i, 3708 (uintmax_t) sc->rx_bd_chain_paddr[i]); 3709 } 3710 3711 /* 3712 * Create a DMA tag for RX mbufs. 3713 */ 3714 if (bce_hdr_split == TRUE) 3715 max_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ? 3716 MCLBYTES : sc->rx_bd_mbuf_alloc_size); 3717 else 3718 max_size = MJUM9BYTES; 3719 3720 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag " 3721 "(max size = 0x%jX)\n", __FUNCTION__, (uintmax_t)max_size); 3722 3723 if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN, 3724 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3725 max_size, 1, max_size, 0, NULL, NULL, &sc->rx_mbuf_tag)) { 3726 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 3727 __FILE__, __LINE__); 3728 rc = ENOMEM; 3729 goto bce_dma_alloc_exit; 3730 } 3731 3732 /* Create DMA maps for the RX mbuf clusters. */ 3733 for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) { 3734 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 3735 &sc->rx_mbuf_map[i])) { 3736 BCE_PRINTF("%s(%d): Unable to create RX mbuf " 3737 "DMA map!\n", __FILE__, __LINE__); 3738 rc = ENOMEM; 3739 goto bce_dma_alloc_exit; 3740 } 3741 } 3742 3743 if (bce_hdr_split == TRUE) { 3744 /* 3745 * Create a DMA tag for the page buffer descriptor chain, 3746 * allocate and clear the memory, and fetch the physical 3747 * address of the blocks. 3748 */ 3749 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3750 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr, 3751 NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ, 3752 0, NULL, NULL, &sc->pg_bd_chain_tag)) { 3753 BCE_PRINTF("%s(%d): Could not allocate page descriptor " 3754 "chain DMA tag!\n", __FILE__, __LINE__); 3755 rc = ENOMEM; 3756 goto bce_dma_alloc_exit; 3757 } 3758 3759 for (i = 0; i < sc->pg_pages; i++) { 3760 if (bus_dmamem_alloc(sc->pg_bd_chain_tag, 3761 (void **)&sc->pg_bd_chain[i], 3762 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3763 &sc->pg_bd_chain_map[i])) { 3764 BCE_PRINTF("%s(%d): Could not allocate page " 3765 "descriptor chain DMA memory!\n", 3766 __FILE__, __LINE__); 3767 rc = ENOMEM; 3768 goto bce_dma_alloc_exit; 3769 } 3770 3771 error = bus_dmamap_load(sc->pg_bd_chain_tag, 3772 sc->pg_bd_chain_map[i], sc->pg_bd_chain[i], 3773 BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr, 3774 &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3775 3776 if (error || sc->pg_bd_chain_paddr[i] == 0) { 3777 BCE_PRINTF("%s(%d): Could not map page descriptor " 3778 "chain DMA memory!\n", __FILE__, __LINE__); 3779 rc = ENOMEM; 3780 goto bce_dma_alloc_exit; 3781 } 3782 3783 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = " 3784 "0x%jX\n", __FUNCTION__, i, 3785 (uintmax_t) sc->pg_bd_chain_paddr[i]); 3786 } 3787 3788 /* 3789 * Create a DMA tag for page mbufs. 3790 */ 3791 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3792 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 3793 1, MCLBYTES, 0, NULL, NULL, &sc->pg_mbuf_tag)) { 3794 BCE_PRINTF("%s(%d): Could not allocate page mbuf " 3795 "DMA tag!\n", __FILE__, __LINE__); 3796 rc = ENOMEM; 3797 goto bce_dma_alloc_exit; 3798 } 3799 3800 /* Create DMA maps for the page mbuf clusters. */ 3801 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) { 3802 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT, 3803 &sc->pg_mbuf_map[i])) { 3804 BCE_PRINTF("%s(%d): Unable to create page mbuf " 3805 "DMA map!\n", __FILE__, __LINE__); 3806 rc = ENOMEM; 3807 goto bce_dma_alloc_exit; 3808 } 3809 } 3810 } 3811 3812 bce_dma_alloc_exit: 3813 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3814 return(rc); 3815 } 3816 3817 /****************************************************************************/ 3818 /* Release all resources used by the driver. */ 3819 /* */ 3820 /* Releases all resources acquired by the driver including interrupts, */ 3821 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 3822 /* */ 3823 /* Returns: */ 3824 /* Nothing. */ 3825 /****************************************************************************/ 3826 static void 3827 bce_release_resources(struct bce_softc *sc) 3828 { 3829 device_t dev; 3830 3831 DBENTER(BCE_VERBOSE_RESET); 3832 3833 dev = sc->bce_dev; 3834 3835 bce_dma_free(sc); 3836 3837 if (sc->bce_intrhand != NULL) { 3838 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 3839 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 3840 } 3841 3842 if (sc->bce_res_irq != NULL) { 3843 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 3844 bus_release_resource(dev, SYS_RES_IRQ, 3845 rman_get_rid(sc->bce_res_irq), sc->bce_res_irq); 3846 } 3847 3848 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) { 3849 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n"); 3850 pci_release_msi(dev); 3851 } 3852 3853 if (sc->bce_res_mem != NULL) { 3854 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 3855 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 3856 sc->bce_res_mem); 3857 } 3858 3859 if (sc->bce_ifp != NULL) { 3860 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 3861 if_free(sc->bce_ifp); 3862 } 3863 3864 if (mtx_initialized(&sc->bce_mtx)) 3865 BCE_LOCK_DESTROY(sc); 3866 3867 DBEXIT(BCE_VERBOSE_RESET); 3868 } 3869 3870 /****************************************************************************/ 3871 /* Firmware synchronization. */ 3872 /* */ 3873 /* Before performing certain events such as a chip reset, synchronize with */ 3874 /* the firmware first. */ 3875 /* */ 3876 /* Returns: */ 3877 /* 0 for success, positive value for failure. */ 3878 /****************************************************************************/ 3879 static int 3880 bce_fw_sync(struct bce_softc *sc, u32 msg_data) 3881 { 3882 int i, rc = 0; 3883 u32 val; 3884 3885 DBENTER(BCE_VERBOSE_RESET); 3886 3887 /* Don't waste any time if we've timed out before. */ 3888 if (sc->bce_fw_timed_out == TRUE) { 3889 rc = EBUSY; 3890 goto bce_fw_sync_exit; 3891 } 3892 3893 /* Increment the message sequence number. */ 3894 sc->bce_fw_wr_seq++; 3895 msg_data |= sc->bce_fw_wr_seq; 3896 3897 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = " 3898 "0x%08X\n", msg_data); 3899 3900 /* Send the message to the bootcode driver mailbox. */ 3901 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3902 3903 /* Wait for the bootcode to acknowledge the message. */ 3904 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 3905 /* Check for a response in the bootcode firmware mailbox. */ 3906 val = bce_shmem_rd(sc, BCE_FW_MB); 3907 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 3908 break; 3909 DELAY(1000); 3910 } 3911 3912 /* If we've timed out, tell bootcode that we've stopped waiting. */ 3913 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 3914 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 3915 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 3916 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 3917 3918 msg_data &= ~BCE_DRV_MSG_CODE; 3919 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 3920 3921 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3922 3923 sc->bce_fw_timed_out = TRUE; 3924 rc = EBUSY; 3925 } 3926 3927 bce_fw_sync_exit: 3928 DBEXIT(BCE_VERBOSE_RESET); 3929 return (rc); 3930 } 3931 3932 /****************************************************************************/ 3933 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 3934 /* */ 3935 /* Returns: */ 3936 /* Nothing. */ 3937 /****************************************************************************/ 3938 static void 3939 bce_load_rv2p_fw(struct bce_softc *sc, const u32 *rv2p_code, 3940 u32 rv2p_code_len, u32 rv2p_proc) 3941 { 3942 int i; 3943 u32 val; 3944 3945 DBENTER(BCE_VERBOSE_RESET); 3946 3947 /* Set the page size used by RV2P. */ 3948 if (rv2p_proc == RV2P_PROC2) { 3949 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE); 3950 } 3951 3952 for (i = 0; i < rv2p_code_len; i += 8) { 3953 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 3954 rv2p_code++; 3955 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 3956 rv2p_code++; 3957 3958 if (rv2p_proc == RV2P_PROC1) { 3959 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 3960 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 3961 } 3962 else { 3963 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 3964 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 3965 } 3966 } 3967 3968 /* Reset the processor, un-stall is done later. */ 3969 if (rv2p_proc == RV2P_PROC1) { 3970 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 3971 } 3972 else { 3973 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 3974 } 3975 3976 DBEXIT(BCE_VERBOSE_RESET); 3977 } 3978 3979 /****************************************************************************/ 3980 /* Load RISC processor firmware. */ 3981 /* */ 3982 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 3983 /* associated with a particular processor. */ 3984 /* */ 3985 /* Returns: */ 3986 /* Nothing. */ 3987 /****************************************************************************/ 3988 static void 3989 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 3990 struct fw_info *fw) 3991 { 3992 u32 offset; 3993 3994 DBENTER(BCE_VERBOSE_RESET); 3995 3996 bce_halt_cpu(sc, cpu_reg); 3997 3998 /* Load the Text area. */ 3999 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 4000 if (fw->text) { 4001 int j; 4002 4003 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 4004 REG_WR_IND(sc, offset, fw->text[j]); 4005 } 4006 } 4007 4008 /* Load the Data area. */ 4009 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 4010 if (fw->data) { 4011 int j; 4012 4013 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 4014 REG_WR_IND(sc, offset, fw->data[j]); 4015 } 4016 } 4017 4018 /* Load the SBSS area. */ 4019 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 4020 if (fw->sbss) { 4021 int j; 4022 4023 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 4024 REG_WR_IND(sc, offset, fw->sbss[j]); 4025 } 4026 } 4027 4028 /* Load the BSS area. */ 4029 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 4030 if (fw->bss) { 4031 int j; 4032 4033 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 4034 REG_WR_IND(sc, offset, fw->bss[j]); 4035 } 4036 } 4037 4038 /* Load the Read-Only area. */ 4039 offset = cpu_reg->spad_base + 4040 (fw->rodata_addr - cpu_reg->mips_view_base); 4041 if (fw->rodata) { 4042 int j; 4043 4044 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 4045 REG_WR_IND(sc, offset, fw->rodata[j]); 4046 } 4047 } 4048 4049 /* Clear the pre-fetch instruction and set the FW start address. */ 4050 REG_WR_IND(sc, cpu_reg->inst, 0); 4051 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 4052 4053 DBEXIT(BCE_VERBOSE_RESET); 4054 } 4055 4056 /****************************************************************************/ 4057 /* Starts the RISC processor. */ 4058 /* */ 4059 /* Assumes the CPU starting address has already been set. */ 4060 /* */ 4061 /* Returns: */ 4062 /* Nothing. */ 4063 /****************************************************************************/ 4064 static void 4065 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4066 { 4067 u32 val; 4068 4069 DBENTER(BCE_VERBOSE_RESET); 4070 4071 /* Start the CPU. */ 4072 val = REG_RD_IND(sc, cpu_reg->mode); 4073 val &= ~cpu_reg->mode_value_halt; 4074 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4075 REG_WR_IND(sc, cpu_reg->mode, val); 4076 4077 DBEXIT(BCE_VERBOSE_RESET); 4078 } 4079 4080 /****************************************************************************/ 4081 /* Halts the RISC processor. */ 4082 /* */ 4083 /* Returns: */ 4084 /* Nothing. */ 4085 /****************************************************************************/ 4086 static void 4087 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4088 { 4089 u32 val; 4090 4091 DBENTER(BCE_VERBOSE_RESET); 4092 4093 /* Halt the CPU. */ 4094 val = REG_RD_IND(sc, cpu_reg->mode); 4095 val |= cpu_reg->mode_value_halt; 4096 REG_WR_IND(sc, cpu_reg->mode, val); 4097 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4098 4099 DBEXIT(BCE_VERBOSE_RESET); 4100 } 4101 4102 /****************************************************************************/ 4103 /* Initialize the RX CPU. */ 4104 /* */ 4105 /* Returns: */ 4106 /* Nothing. */ 4107 /****************************************************************************/ 4108 static void 4109 bce_start_rxp_cpu(struct bce_softc *sc) 4110 { 4111 struct cpu_reg cpu_reg; 4112 4113 DBENTER(BCE_VERBOSE_RESET); 4114 4115 cpu_reg.mode = BCE_RXP_CPU_MODE; 4116 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4117 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4118 cpu_reg.state = BCE_RXP_CPU_STATE; 4119 cpu_reg.state_value_clear = 0xffffff; 4120 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4121 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4122 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4123 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4124 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4125 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4126 cpu_reg.mips_view_base = 0x8000000; 4127 4128 DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n"); 4129 bce_start_cpu(sc, &cpu_reg); 4130 4131 DBEXIT(BCE_VERBOSE_RESET); 4132 } 4133 4134 /****************************************************************************/ 4135 /* Initialize the RX CPU. */ 4136 /* */ 4137 /* Returns: */ 4138 /* Nothing. */ 4139 /****************************************************************************/ 4140 static void 4141 bce_init_rxp_cpu(struct bce_softc *sc) 4142 { 4143 struct cpu_reg cpu_reg; 4144 struct fw_info fw; 4145 4146 DBENTER(BCE_VERBOSE_RESET); 4147 4148 cpu_reg.mode = BCE_RXP_CPU_MODE; 4149 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4150 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4151 cpu_reg.state = BCE_RXP_CPU_STATE; 4152 cpu_reg.state_value_clear = 0xffffff; 4153 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4154 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4155 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4156 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4157 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4158 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4159 cpu_reg.mips_view_base = 0x8000000; 4160 4161 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4162 fw.ver_major = bce_RXP_b09FwReleaseMajor; 4163 fw.ver_minor = bce_RXP_b09FwReleaseMinor; 4164 fw.ver_fix = bce_RXP_b09FwReleaseFix; 4165 fw.start_addr = bce_RXP_b09FwStartAddr; 4166 4167 fw.text_addr = bce_RXP_b09FwTextAddr; 4168 fw.text_len = bce_RXP_b09FwTextLen; 4169 fw.text_index = 0; 4170 fw.text = bce_RXP_b09FwText; 4171 4172 fw.data_addr = bce_RXP_b09FwDataAddr; 4173 fw.data_len = bce_RXP_b09FwDataLen; 4174 fw.data_index = 0; 4175 fw.data = bce_RXP_b09FwData; 4176 4177 fw.sbss_addr = bce_RXP_b09FwSbssAddr; 4178 fw.sbss_len = bce_RXP_b09FwSbssLen; 4179 fw.sbss_index = 0; 4180 fw.sbss = bce_RXP_b09FwSbss; 4181 4182 fw.bss_addr = bce_RXP_b09FwBssAddr; 4183 fw.bss_len = bce_RXP_b09FwBssLen; 4184 fw.bss_index = 0; 4185 fw.bss = bce_RXP_b09FwBss; 4186 4187 fw.rodata_addr = bce_RXP_b09FwRodataAddr; 4188 fw.rodata_len = bce_RXP_b09FwRodataLen; 4189 fw.rodata_index = 0; 4190 fw.rodata = bce_RXP_b09FwRodata; 4191 } else { 4192 fw.ver_major = bce_RXP_b06FwReleaseMajor; 4193 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 4194 fw.ver_fix = bce_RXP_b06FwReleaseFix; 4195 fw.start_addr = bce_RXP_b06FwStartAddr; 4196 4197 fw.text_addr = bce_RXP_b06FwTextAddr; 4198 fw.text_len = bce_RXP_b06FwTextLen; 4199 fw.text_index = 0; 4200 fw.text = bce_RXP_b06FwText; 4201 4202 fw.data_addr = bce_RXP_b06FwDataAddr; 4203 fw.data_len = bce_RXP_b06FwDataLen; 4204 fw.data_index = 0; 4205 fw.data = bce_RXP_b06FwData; 4206 4207 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 4208 fw.sbss_len = bce_RXP_b06FwSbssLen; 4209 fw.sbss_index = 0; 4210 fw.sbss = bce_RXP_b06FwSbss; 4211 4212 fw.bss_addr = bce_RXP_b06FwBssAddr; 4213 fw.bss_len = bce_RXP_b06FwBssLen; 4214 fw.bss_index = 0; 4215 fw.bss = bce_RXP_b06FwBss; 4216 4217 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 4218 fw.rodata_len = bce_RXP_b06FwRodataLen; 4219 fw.rodata_index = 0; 4220 fw.rodata = bce_RXP_b06FwRodata; 4221 } 4222 4223 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 4224 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4225 4226 /* Delay RXP start until initialization is complete. */ 4227 4228 DBEXIT(BCE_VERBOSE_RESET); 4229 } 4230 4231 /****************************************************************************/ 4232 /* Initialize the TX CPU. */ 4233 /* */ 4234 /* Returns: */ 4235 /* Nothing. */ 4236 /****************************************************************************/ 4237 static void 4238 bce_init_txp_cpu(struct bce_softc *sc) 4239 { 4240 struct cpu_reg cpu_reg; 4241 struct fw_info fw; 4242 4243 DBENTER(BCE_VERBOSE_RESET); 4244 4245 cpu_reg.mode = BCE_TXP_CPU_MODE; 4246 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 4247 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 4248 cpu_reg.state = BCE_TXP_CPU_STATE; 4249 cpu_reg.state_value_clear = 0xffffff; 4250 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 4251 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 4252 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 4253 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 4254 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 4255 cpu_reg.spad_base = BCE_TXP_SCRATCH; 4256 cpu_reg.mips_view_base = 0x8000000; 4257 4258 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4259 fw.ver_major = bce_TXP_b09FwReleaseMajor; 4260 fw.ver_minor = bce_TXP_b09FwReleaseMinor; 4261 fw.ver_fix = bce_TXP_b09FwReleaseFix; 4262 fw.start_addr = bce_TXP_b09FwStartAddr; 4263 4264 fw.text_addr = bce_TXP_b09FwTextAddr; 4265 fw.text_len = bce_TXP_b09FwTextLen; 4266 fw.text_index = 0; 4267 fw.text = bce_TXP_b09FwText; 4268 4269 fw.data_addr = bce_TXP_b09FwDataAddr; 4270 fw.data_len = bce_TXP_b09FwDataLen; 4271 fw.data_index = 0; 4272 fw.data = bce_TXP_b09FwData; 4273 4274 fw.sbss_addr = bce_TXP_b09FwSbssAddr; 4275 fw.sbss_len = bce_TXP_b09FwSbssLen; 4276 fw.sbss_index = 0; 4277 fw.sbss = bce_TXP_b09FwSbss; 4278 4279 fw.bss_addr = bce_TXP_b09FwBssAddr; 4280 fw.bss_len = bce_TXP_b09FwBssLen; 4281 fw.bss_index = 0; 4282 fw.bss = bce_TXP_b09FwBss; 4283 4284 fw.rodata_addr = bce_TXP_b09FwRodataAddr; 4285 fw.rodata_len = bce_TXP_b09FwRodataLen; 4286 fw.rodata_index = 0; 4287 fw.rodata = bce_TXP_b09FwRodata; 4288 } else { 4289 fw.ver_major = bce_TXP_b06FwReleaseMajor; 4290 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 4291 fw.ver_fix = bce_TXP_b06FwReleaseFix; 4292 fw.start_addr = bce_TXP_b06FwStartAddr; 4293 4294 fw.text_addr = bce_TXP_b06FwTextAddr; 4295 fw.text_len = bce_TXP_b06FwTextLen; 4296 fw.text_index = 0; 4297 fw.text = bce_TXP_b06FwText; 4298 4299 fw.data_addr = bce_TXP_b06FwDataAddr; 4300 fw.data_len = bce_TXP_b06FwDataLen; 4301 fw.data_index = 0; 4302 fw.data = bce_TXP_b06FwData; 4303 4304 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 4305 fw.sbss_len = bce_TXP_b06FwSbssLen; 4306 fw.sbss_index = 0; 4307 fw.sbss = bce_TXP_b06FwSbss; 4308 4309 fw.bss_addr = bce_TXP_b06FwBssAddr; 4310 fw.bss_len = bce_TXP_b06FwBssLen; 4311 fw.bss_index = 0; 4312 fw.bss = bce_TXP_b06FwBss; 4313 4314 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 4315 fw.rodata_len = bce_TXP_b06FwRodataLen; 4316 fw.rodata_index = 0; 4317 fw.rodata = bce_TXP_b06FwRodata; 4318 } 4319 4320 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 4321 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4322 bce_start_cpu(sc, &cpu_reg); 4323 4324 DBEXIT(BCE_VERBOSE_RESET); 4325 } 4326 4327 /****************************************************************************/ 4328 /* Initialize the TPAT CPU. */ 4329 /* */ 4330 /* Returns: */ 4331 /* Nothing. */ 4332 /****************************************************************************/ 4333 static void 4334 bce_init_tpat_cpu(struct bce_softc *sc) 4335 { 4336 struct cpu_reg cpu_reg; 4337 struct fw_info fw; 4338 4339 DBENTER(BCE_VERBOSE_RESET); 4340 4341 cpu_reg.mode = BCE_TPAT_CPU_MODE; 4342 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 4343 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 4344 cpu_reg.state = BCE_TPAT_CPU_STATE; 4345 cpu_reg.state_value_clear = 0xffffff; 4346 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 4347 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 4348 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 4349 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 4350 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 4351 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 4352 cpu_reg.mips_view_base = 0x8000000; 4353 4354 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4355 fw.ver_major = bce_TPAT_b09FwReleaseMajor; 4356 fw.ver_minor = bce_TPAT_b09FwReleaseMinor; 4357 fw.ver_fix = bce_TPAT_b09FwReleaseFix; 4358 fw.start_addr = bce_TPAT_b09FwStartAddr; 4359 4360 fw.text_addr = bce_TPAT_b09FwTextAddr; 4361 fw.text_len = bce_TPAT_b09FwTextLen; 4362 fw.text_index = 0; 4363 fw.text = bce_TPAT_b09FwText; 4364 4365 fw.data_addr = bce_TPAT_b09FwDataAddr; 4366 fw.data_len = bce_TPAT_b09FwDataLen; 4367 fw.data_index = 0; 4368 fw.data = bce_TPAT_b09FwData; 4369 4370 fw.sbss_addr = bce_TPAT_b09FwSbssAddr; 4371 fw.sbss_len = bce_TPAT_b09FwSbssLen; 4372 fw.sbss_index = 0; 4373 fw.sbss = bce_TPAT_b09FwSbss; 4374 4375 fw.bss_addr = bce_TPAT_b09FwBssAddr; 4376 fw.bss_len = bce_TPAT_b09FwBssLen; 4377 fw.bss_index = 0; 4378 fw.bss = bce_TPAT_b09FwBss; 4379 4380 fw.rodata_addr = bce_TPAT_b09FwRodataAddr; 4381 fw.rodata_len = bce_TPAT_b09FwRodataLen; 4382 fw.rodata_index = 0; 4383 fw.rodata = bce_TPAT_b09FwRodata; 4384 } else { 4385 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 4386 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 4387 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 4388 fw.start_addr = bce_TPAT_b06FwStartAddr; 4389 4390 fw.text_addr = bce_TPAT_b06FwTextAddr; 4391 fw.text_len = bce_TPAT_b06FwTextLen; 4392 fw.text_index = 0; 4393 fw.text = bce_TPAT_b06FwText; 4394 4395 fw.data_addr = bce_TPAT_b06FwDataAddr; 4396 fw.data_len = bce_TPAT_b06FwDataLen; 4397 fw.data_index = 0; 4398 fw.data = bce_TPAT_b06FwData; 4399 4400 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 4401 fw.sbss_len = bce_TPAT_b06FwSbssLen; 4402 fw.sbss_index = 0; 4403 fw.sbss = bce_TPAT_b06FwSbss; 4404 4405 fw.bss_addr = bce_TPAT_b06FwBssAddr; 4406 fw.bss_len = bce_TPAT_b06FwBssLen; 4407 fw.bss_index = 0; 4408 fw.bss = bce_TPAT_b06FwBss; 4409 4410 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 4411 fw.rodata_len = bce_TPAT_b06FwRodataLen; 4412 fw.rodata_index = 0; 4413 fw.rodata = bce_TPAT_b06FwRodata; 4414 } 4415 4416 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 4417 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4418 bce_start_cpu(sc, &cpu_reg); 4419 4420 DBEXIT(BCE_VERBOSE_RESET); 4421 } 4422 4423 /****************************************************************************/ 4424 /* Initialize the CP CPU. */ 4425 /* */ 4426 /* Returns: */ 4427 /* Nothing. */ 4428 /****************************************************************************/ 4429 static void 4430 bce_init_cp_cpu(struct bce_softc *sc) 4431 { 4432 struct cpu_reg cpu_reg; 4433 struct fw_info fw; 4434 4435 DBENTER(BCE_VERBOSE_RESET); 4436 4437 cpu_reg.mode = BCE_CP_CPU_MODE; 4438 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT; 4439 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA; 4440 cpu_reg.state = BCE_CP_CPU_STATE; 4441 cpu_reg.state_value_clear = 0xffffff; 4442 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE; 4443 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK; 4444 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER; 4445 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION; 4446 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT; 4447 cpu_reg.spad_base = BCE_CP_SCRATCH; 4448 cpu_reg.mips_view_base = 0x8000000; 4449 4450 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4451 fw.ver_major = bce_CP_b09FwReleaseMajor; 4452 fw.ver_minor = bce_CP_b09FwReleaseMinor; 4453 fw.ver_fix = bce_CP_b09FwReleaseFix; 4454 fw.start_addr = bce_CP_b09FwStartAddr; 4455 4456 fw.text_addr = bce_CP_b09FwTextAddr; 4457 fw.text_len = bce_CP_b09FwTextLen; 4458 fw.text_index = 0; 4459 fw.text = bce_CP_b09FwText; 4460 4461 fw.data_addr = bce_CP_b09FwDataAddr; 4462 fw.data_len = bce_CP_b09FwDataLen; 4463 fw.data_index = 0; 4464 fw.data = bce_CP_b09FwData; 4465 4466 fw.sbss_addr = bce_CP_b09FwSbssAddr; 4467 fw.sbss_len = bce_CP_b09FwSbssLen; 4468 fw.sbss_index = 0; 4469 fw.sbss = bce_CP_b09FwSbss; 4470 4471 fw.bss_addr = bce_CP_b09FwBssAddr; 4472 fw.bss_len = bce_CP_b09FwBssLen; 4473 fw.bss_index = 0; 4474 fw.bss = bce_CP_b09FwBss; 4475 4476 fw.rodata_addr = bce_CP_b09FwRodataAddr; 4477 fw.rodata_len = bce_CP_b09FwRodataLen; 4478 fw.rodata_index = 0; 4479 fw.rodata = bce_CP_b09FwRodata; 4480 } else { 4481 fw.ver_major = bce_CP_b06FwReleaseMajor; 4482 fw.ver_minor = bce_CP_b06FwReleaseMinor; 4483 fw.ver_fix = bce_CP_b06FwReleaseFix; 4484 fw.start_addr = bce_CP_b06FwStartAddr; 4485 4486 fw.text_addr = bce_CP_b06FwTextAddr; 4487 fw.text_len = bce_CP_b06FwTextLen; 4488 fw.text_index = 0; 4489 fw.text = bce_CP_b06FwText; 4490 4491 fw.data_addr = bce_CP_b06FwDataAddr; 4492 fw.data_len = bce_CP_b06FwDataLen; 4493 fw.data_index = 0; 4494 fw.data = bce_CP_b06FwData; 4495 4496 fw.sbss_addr = bce_CP_b06FwSbssAddr; 4497 fw.sbss_len = bce_CP_b06FwSbssLen; 4498 fw.sbss_index = 0; 4499 fw.sbss = bce_CP_b06FwSbss; 4500 4501 fw.bss_addr = bce_CP_b06FwBssAddr; 4502 fw.bss_len = bce_CP_b06FwBssLen; 4503 fw.bss_index = 0; 4504 fw.bss = bce_CP_b06FwBss; 4505 4506 fw.rodata_addr = bce_CP_b06FwRodataAddr; 4507 fw.rodata_len = bce_CP_b06FwRodataLen; 4508 fw.rodata_index = 0; 4509 fw.rodata = bce_CP_b06FwRodata; 4510 } 4511 4512 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n"); 4513 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4514 bce_start_cpu(sc, &cpu_reg); 4515 4516 DBEXIT(BCE_VERBOSE_RESET); 4517 } 4518 4519 /****************************************************************************/ 4520 /* Initialize the COM CPU. */ 4521 /* */ 4522 /* Returns: */ 4523 /* Nothing. */ 4524 /****************************************************************************/ 4525 static void 4526 bce_init_com_cpu(struct bce_softc *sc) 4527 { 4528 struct cpu_reg cpu_reg; 4529 struct fw_info fw; 4530 4531 DBENTER(BCE_VERBOSE_RESET); 4532 4533 cpu_reg.mode = BCE_COM_CPU_MODE; 4534 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 4535 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 4536 cpu_reg.state = BCE_COM_CPU_STATE; 4537 cpu_reg.state_value_clear = 0xffffff; 4538 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 4539 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 4540 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 4541 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 4542 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 4543 cpu_reg.spad_base = BCE_COM_SCRATCH; 4544 cpu_reg.mips_view_base = 0x8000000; 4545 4546 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4547 fw.ver_major = bce_COM_b09FwReleaseMajor; 4548 fw.ver_minor = bce_COM_b09FwReleaseMinor; 4549 fw.ver_fix = bce_COM_b09FwReleaseFix; 4550 fw.start_addr = bce_COM_b09FwStartAddr; 4551 4552 fw.text_addr = bce_COM_b09FwTextAddr; 4553 fw.text_len = bce_COM_b09FwTextLen; 4554 fw.text_index = 0; 4555 fw.text = bce_COM_b09FwText; 4556 4557 fw.data_addr = bce_COM_b09FwDataAddr; 4558 fw.data_len = bce_COM_b09FwDataLen; 4559 fw.data_index = 0; 4560 fw.data = bce_COM_b09FwData; 4561 4562 fw.sbss_addr = bce_COM_b09FwSbssAddr; 4563 fw.sbss_len = bce_COM_b09FwSbssLen; 4564 fw.sbss_index = 0; 4565 fw.sbss = bce_COM_b09FwSbss; 4566 4567 fw.bss_addr = bce_COM_b09FwBssAddr; 4568 fw.bss_len = bce_COM_b09FwBssLen; 4569 fw.bss_index = 0; 4570 fw.bss = bce_COM_b09FwBss; 4571 4572 fw.rodata_addr = bce_COM_b09FwRodataAddr; 4573 fw.rodata_len = bce_COM_b09FwRodataLen; 4574 fw.rodata_index = 0; 4575 fw.rodata = bce_COM_b09FwRodata; 4576 } else { 4577 fw.ver_major = bce_COM_b06FwReleaseMajor; 4578 fw.ver_minor = bce_COM_b06FwReleaseMinor; 4579 fw.ver_fix = bce_COM_b06FwReleaseFix; 4580 fw.start_addr = bce_COM_b06FwStartAddr; 4581 4582 fw.text_addr = bce_COM_b06FwTextAddr; 4583 fw.text_len = bce_COM_b06FwTextLen; 4584 fw.text_index = 0; 4585 fw.text = bce_COM_b06FwText; 4586 4587 fw.data_addr = bce_COM_b06FwDataAddr; 4588 fw.data_len = bce_COM_b06FwDataLen; 4589 fw.data_index = 0; 4590 fw.data = bce_COM_b06FwData; 4591 4592 fw.sbss_addr = bce_COM_b06FwSbssAddr; 4593 fw.sbss_len = bce_COM_b06FwSbssLen; 4594 fw.sbss_index = 0; 4595 fw.sbss = bce_COM_b06FwSbss; 4596 4597 fw.bss_addr = bce_COM_b06FwBssAddr; 4598 fw.bss_len = bce_COM_b06FwBssLen; 4599 fw.bss_index = 0; 4600 fw.bss = bce_COM_b06FwBss; 4601 4602 fw.rodata_addr = bce_COM_b06FwRodataAddr; 4603 fw.rodata_len = bce_COM_b06FwRodataLen; 4604 fw.rodata_index = 0; 4605 fw.rodata = bce_COM_b06FwRodata; 4606 } 4607 4608 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 4609 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4610 bce_start_cpu(sc, &cpu_reg); 4611 4612 DBEXIT(BCE_VERBOSE_RESET); 4613 } 4614 4615 /****************************************************************************/ 4616 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */ 4617 /* */ 4618 /* Loads the firmware for each CPU and starts the CPU. */ 4619 /* */ 4620 /* Returns: */ 4621 /* Nothing. */ 4622 /****************************************************************************/ 4623 static void 4624 bce_init_cpus(struct bce_softc *sc) 4625 { 4626 DBENTER(BCE_VERBOSE_RESET); 4627 4628 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4629 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) { 4630 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1, 4631 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1); 4632 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2, 4633 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2); 4634 } else { 4635 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, 4636 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1); 4637 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, 4638 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2); 4639 } 4640 4641 } else { 4642 bce_load_rv2p_fw(sc, bce_rv2p_proc1, 4643 sizeof(bce_rv2p_proc1), RV2P_PROC1); 4644 bce_load_rv2p_fw(sc, bce_rv2p_proc2, 4645 sizeof(bce_rv2p_proc2), RV2P_PROC2); 4646 } 4647 4648 bce_init_rxp_cpu(sc); 4649 bce_init_txp_cpu(sc); 4650 bce_init_tpat_cpu(sc); 4651 bce_init_com_cpu(sc); 4652 bce_init_cp_cpu(sc); 4653 4654 DBEXIT(BCE_VERBOSE_RESET); 4655 } 4656 4657 /****************************************************************************/ 4658 /* Initialize context memory. */ 4659 /* */ 4660 /* Clears the memory associated with each Context ID (CID). */ 4661 /* */ 4662 /* Returns: */ 4663 /* Nothing. */ 4664 /****************************************************************************/ 4665 static int 4666 bce_init_ctx(struct bce_softc *sc) 4667 { 4668 u32 offset, val, vcid_addr; 4669 int i, j, rc, retry_cnt; 4670 4671 rc = 0; 4672 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4673 4674 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4675 retry_cnt = CTX_INIT_RETRY_COUNT; 4676 4677 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n"); 4678 4679 /* 4680 * BCM5709 context memory may be cached 4681 * in host memory so prepare the host memory 4682 * for access. 4683 */ 4684 val = BCE_CTX_COMMAND_ENABLED | 4685 BCE_CTX_COMMAND_MEM_INIT | (1 << 12); 4686 val |= (BCM_PAGE_BITS - 8) << 16; 4687 REG_WR(sc, BCE_CTX_COMMAND, val); 4688 4689 /* Wait for mem init command to complete. */ 4690 for (i = 0; i < retry_cnt; i++) { 4691 val = REG_RD(sc, BCE_CTX_COMMAND); 4692 if (!(val & BCE_CTX_COMMAND_MEM_INIT)) 4693 break; 4694 DELAY(2); 4695 } 4696 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) { 4697 BCE_PRINTF("%s(): Context memory initialization failed!\n", 4698 __FUNCTION__); 4699 rc = EBUSY; 4700 goto init_ctx_fail; 4701 } 4702 4703 for (i = 0; i < sc->ctx_pages; i++) { 4704 /* Set the physical address of the context memory. */ 4705 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0, 4706 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) | 4707 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID); 4708 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1, 4709 BCE_ADDR_HI(sc->ctx_paddr[i])); 4710 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i | 4711 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 4712 4713 /* Verify the context memory write was successful. */ 4714 for (j = 0; j < retry_cnt; j++) { 4715 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL); 4716 if ((val & 4717 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 4718 break; 4719 DELAY(5); 4720 } 4721 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) { 4722 BCE_PRINTF("%s(): Failed to initialize " 4723 "context page %d!\n", __FUNCTION__, i); 4724 rc = EBUSY; 4725 goto init_ctx_fail; 4726 } 4727 } 4728 } else { 4729 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n"); 4730 4731 /* 4732 * For the 5706/5708, context memory is local to 4733 * the controller, so initialize the controller 4734 * context memory. 4735 */ 4736 4737 vcid_addr = GET_CID_ADDR(96); 4738 while (vcid_addr) { 4739 vcid_addr -= PHY_CTX_SIZE; 4740 4741 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0); 4742 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4743 4744 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 4745 CTX_WR(sc, 0x00, offset, 0); 4746 } 4747 4748 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 4749 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4750 } 4751 } 4752 init_ctx_fail: 4753 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4754 return (rc); 4755 } 4756 4757 /****************************************************************************/ 4758 /* Fetch the permanent MAC address of the controller. */ 4759 /* */ 4760 /* Returns: */ 4761 /* Nothing. */ 4762 /****************************************************************************/ 4763 static void 4764 bce_get_mac_addr(struct bce_softc *sc) 4765 { 4766 u32 mac_lo = 0, mac_hi = 0; 4767 4768 DBENTER(BCE_VERBOSE_RESET); 4769 4770 /* 4771 * The NetXtreme II bootcode populates various NIC 4772 * power-on and runtime configuration items in a 4773 * shared memory area. The factory configured MAC 4774 * address is available from both NVRAM and the 4775 * shared memory area so we'll read the value from 4776 * shared memory for speed. 4777 */ 4778 4779 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER); 4780 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER); 4781 4782 if ((mac_lo == 0) && (mac_hi == 0)) { 4783 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 4784 __FILE__, __LINE__); 4785 } else { 4786 sc->eaddr[0] = (u_char)(mac_hi >> 8); 4787 sc->eaddr[1] = (u_char)(mac_hi >> 0); 4788 sc->eaddr[2] = (u_char)(mac_lo >> 24); 4789 sc->eaddr[3] = (u_char)(mac_lo >> 16); 4790 sc->eaddr[4] = (u_char)(mac_lo >> 8); 4791 sc->eaddr[5] = (u_char)(mac_lo >> 0); 4792 } 4793 4794 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet " 4795 "address = %6D\n", sc->eaddr, ":"); 4796 DBEXIT(BCE_VERBOSE_RESET); 4797 } 4798 4799 /****************************************************************************/ 4800 /* Program the MAC address. */ 4801 /* */ 4802 /* Returns: */ 4803 /* Nothing. */ 4804 /****************************************************************************/ 4805 static void 4806 bce_set_mac_addr(struct bce_softc *sc) 4807 { 4808 u32 val; 4809 u8 *mac_addr = sc->eaddr; 4810 4811 /* ToDo: Add support for setting multiple MAC addresses. */ 4812 4813 DBENTER(BCE_VERBOSE_RESET); 4814 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = " 4815 "%6D\n", sc->eaddr, ":"); 4816 4817 val = (mac_addr[0] << 8) | mac_addr[1]; 4818 4819 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 4820 4821 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 4822 (mac_addr[4] << 8) | mac_addr[5]; 4823 4824 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 4825 4826 DBEXIT(BCE_VERBOSE_RESET); 4827 } 4828 4829 /****************************************************************************/ 4830 /* Stop the controller. */ 4831 /* */ 4832 /* Returns: */ 4833 /* Nothing. */ 4834 /****************************************************************************/ 4835 static void 4836 bce_stop(struct bce_softc *sc) 4837 { 4838 struct ifnet *ifp; 4839 4840 DBENTER(BCE_VERBOSE_RESET); 4841 4842 BCE_LOCK_ASSERT(sc); 4843 4844 ifp = sc->bce_ifp; 4845 4846 callout_stop(&sc->bce_tick_callout); 4847 4848 /* Disable the transmit/receive blocks. */ 4849 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT); 4850 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4851 DELAY(20); 4852 4853 bce_disable_intr(sc); 4854 4855 /* Free RX buffers. */ 4856 if (bce_hdr_split == TRUE) { 4857 bce_free_pg_chain(sc); 4858 } 4859 bce_free_rx_chain(sc); 4860 4861 /* Free TX buffers. */ 4862 bce_free_tx_chain(sc); 4863 4864 sc->watchdog_timer = 0; 4865 4866 sc->bce_link_up = FALSE; 4867 4868 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4869 4870 DBEXIT(BCE_VERBOSE_RESET); 4871 } 4872 4873 static int 4874 bce_reset(struct bce_softc *sc, u32 reset_code) 4875 { 4876 u32 emac_mode_save, val; 4877 int i, rc = 0; 4878 static const u32 emac_mode_mask = BCE_EMAC_MODE_PORT | 4879 BCE_EMAC_MODE_HALF_DUPLEX | BCE_EMAC_MODE_25G; 4880 4881 DBENTER(BCE_VERBOSE_RESET); 4882 4883 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 4884 __FUNCTION__, reset_code); 4885 4886 /* 4887 * If ASF/IPMI is operational, then the EMAC Mode register already 4888 * contains appropriate values for the link settings that have 4889 * been auto-negotiated. Resetting the chip will clobber those 4890 * values. Save the important bits so we can restore them after 4891 * the reset. 4892 */ 4893 emac_mode_save = REG_RD(sc, BCE_EMAC_MODE) & emac_mode_mask; 4894 4895 /* Wait for pending PCI transactions to complete. */ 4896 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 4897 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 4898 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 4899 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 4900 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 4901 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4902 DELAY(5); 4903 4904 /* Disable DMA */ 4905 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4906 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 4907 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 4908 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 4909 } 4910 4911 /* Assume bootcode is running. */ 4912 sc->bce_fw_timed_out = FALSE; 4913 sc->bce_drv_cardiac_arrest = FALSE; 4914 4915 /* Give the firmware a chance to prepare for the reset. */ 4916 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 4917 if (rc) 4918 goto bce_reset_exit; 4919 4920 /* Set a firmware reminder that this is a soft reset. */ 4921 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC); 4922 4923 /* Dummy read to force the chip to complete all current transactions. */ 4924 val = REG_RD(sc, BCE_MISC_ID); 4925 4926 /* Chip reset. */ 4927 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4928 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET); 4929 REG_RD(sc, BCE_MISC_COMMAND); 4930 DELAY(5); 4931 4932 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4933 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4934 4935 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4); 4936 } else { 4937 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4938 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4939 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4940 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 4941 4942 /* Allow up to 30us for reset to complete. */ 4943 for (i = 0; i < 10; i++) { 4944 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 4945 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4946 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 4947 break; 4948 } 4949 DELAY(10); 4950 } 4951 4952 /* Check that reset completed successfully. */ 4953 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4954 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 4955 BCE_PRINTF("%s(%d): Reset failed!\n", 4956 __FILE__, __LINE__); 4957 rc = EBUSY; 4958 goto bce_reset_exit; 4959 } 4960 } 4961 4962 /* Make sure byte swapping is properly configured. */ 4963 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 4964 if (val != 0x01020304) { 4965 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 4966 __FILE__, __LINE__); 4967 rc = ENODEV; 4968 goto bce_reset_exit; 4969 } 4970 4971 /* Just completed a reset, assume that firmware is running again. */ 4972 sc->bce_fw_timed_out = FALSE; 4973 sc->bce_drv_cardiac_arrest = FALSE; 4974 4975 /* Wait for the firmware to finish its initialization. */ 4976 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 4977 if (rc) 4978 BCE_PRINTF("%s(%d): Firmware did not complete " 4979 "initialization!\n", __FILE__, __LINE__); 4980 /* Get firmware capabilities. */ 4981 bce_fw_cap_init(sc); 4982 4983 bce_reset_exit: 4984 /* Restore EMAC Mode bits needed to keep ASF/IPMI running. */ 4985 if (reset_code == BCE_DRV_MSG_CODE_RESET) { 4986 val = REG_RD(sc, BCE_EMAC_MODE); 4987 val = (val & ~emac_mode_mask) | emac_mode_save; 4988 REG_WR(sc, BCE_EMAC_MODE, val); 4989 } 4990 4991 DBEXIT(BCE_VERBOSE_RESET); 4992 return (rc); 4993 } 4994 4995 static int 4996 bce_chipinit(struct bce_softc *sc) 4997 { 4998 u32 val; 4999 int rc = 0; 5000 5001 DBENTER(BCE_VERBOSE_RESET); 5002 5003 bce_disable_intr(sc); 5004 5005 /* 5006 * Initialize DMA byte/word swapping, configure the number of DMA 5007 * channels and PCI clock compensation delay. 5008 */ 5009 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 5010 BCE_DMA_CONFIG_DATA_WORD_SWAP | 5011 #if BYTE_ORDER == BIG_ENDIAN 5012 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 5013 #endif 5014 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 5015 DMA_READ_CHANS << 12 | 5016 DMA_WRITE_CHANS << 16; 5017 5018 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 5019 5020 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 5021 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 5022 5023 /* 5024 * This setting resolves a problem observed on certain Intel PCI 5025 * chipsets that cannot handle multiple outstanding DMA operations. 5026 * See errata E9_5706A1_65. 5027 */ 5028 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 5029 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 5030 !(sc->bce_flags & BCE_PCIX_FLAG)) 5031 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 5032 5033 REG_WR(sc, BCE_DMA_CONFIG, val); 5034 5035 /* Enable the RX_V2P and Context state machines before access. */ 5036 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5037 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 5038 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 5039 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 5040 5041 /* Initialize context mapping and zero out the quick contexts. */ 5042 if ((rc = bce_init_ctx(sc)) != 0) 5043 goto bce_chipinit_exit; 5044 5045 /* Initialize the on-boards CPUs */ 5046 bce_init_cpus(sc); 5047 5048 /* Enable management frames (NC-SI) to flow to the MCP. */ 5049 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5050 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5051 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5052 } 5053 5054 /* Prepare NVRAM for access. */ 5055 if ((rc = bce_init_nvram(sc)) != 0) 5056 goto bce_chipinit_exit; 5057 5058 /* Set the kernel bypass block size */ 5059 val = REG_RD(sc, BCE_MQ_CONFIG); 5060 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 5061 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 5062 5063 /* Enable bins used on the 5709. */ 5064 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5065 val |= BCE_MQ_CONFIG_BIN_MQ_MODE; 5066 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1) 5067 val |= BCE_MQ_CONFIG_HALT_DIS; 5068 } 5069 5070 REG_WR(sc, BCE_MQ_CONFIG, val); 5071 5072 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 5073 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 5074 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 5075 5076 /* Set the page size and clear the RV2P processor stall bits. */ 5077 val = (BCM_PAGE_BITS - 8) << 24; 5078 REG_WR(sc, BCE_RV2P_CONFIG, val); 5079 5080 /* Configure page size. */ 5081 val = REG_RD(sc, BCE_TBDR_CONFIG); 5082 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 5083 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 5084 REG_WR(sc, BCE_TBDR_CONFIG, val); 5085 5086 /* Set the perfect match control register to default. */ 5087 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0); 5088 5089 bce_chipinit_exit: 5090 DBEXIT(BCE_VERBOSE_RESET); 5091 5092 return(rc); 5093 } 5094 5095 /****************************************************************************/ 5096 /* Initialize the controller in preparation to send/receive traffic. */ 5097 /* */ 5098 /* Returns: */ 5099 /* 0 for success, positive value for failure. */ 5100 /****************************************************************************/ 5101 static int 5102 bce_blockinit(struct bce_softc *sc) 5103 { 5104 u32 reg, val; 5105 int rc = 0; 5106 5107 DBENTER(BCE_VERBOSE_RESET); 5108 5109 /* Load the hardware default MAC address. */ 5110 bce_set_mac_addr(sc); 5111 5112 /* Set the Ethernet backoff seed value */ 5113 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 5114 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 5115 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 5116 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 5117 5118 sc->last_status_idx = 0; 5119 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 5120 5121 /* Set up link change interrupt generation. */ 5122 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 5123 5124 /* Program the physical address of the status block. */ 5125 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 5126 BCE_ADDR_LO(sc->status_block_paddr)); 5127 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 5128 BCE_ADDR_HI(sc->status_block_paddr)); 5129 5130 /* Program the physical address of the statistics block. */ 5131 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 5132 BCE_ADDR_LO(sc->stats_block_paddr)); 5133 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 5134 BCE_ADDR_HI(sc->stats_block_paddr)); 5135 5136 /* 5137 * Program various host coalescing parameters. 5138 * Trip points control how many BDs should be ready before generating 5139 * an interrupt while ticks control how long a BD can sit in the chain 5140 * before generating an interrupt. 5141 */ 5142 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 5143 (sc->bce_tx_quick_cons_trip_int << 16) | 5144 sc->bce_tx_quick_cons_trip); 5145 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 5146 (sc->bce_rx_quick_cons_trip_int << 16) | 5147 sc->bce_rx_quick_cons_trip); 5148 REG_WR(sc, BCE_HC_TX_TICKS, 5149 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 5150 REG_WR(sc, BCE_HC_RX_TICKS, 5151 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 5152 REG_WR(sc, BCE_HC_STATS_TICKS, sc->bce_stats_ticks & 0xffff00); 5153 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 5154 /* Not used for L2. */ 5155 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 0); 5156 REG_WR(sc, BCE_HC_COM_TICKS, 0); 5157 REG_WR(sc, BCE_HC_CMD_TICKS, 0); 5158 5159 /* Configure the Host Coalescing block. */ 5160 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 5161 BCE_HC_CONFIG_COLLECT_STATS; 5162 5163 #if 0 5164 /* ToDo: Add MSI-X support. */ 5165 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 5166 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) + 5167 BCE_HC_SB_CONFIG_1; 5168 5169 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL); 5170 5171 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE | 5172 BCE_HC_SB_CONFIG_1_ONE_SHOT); 5173 5174 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF, 5175 (sc->tx_quick_cons_trip_int << 16) | 5176 sc->tx_quick_cons_trip); 5177 5178 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF, 5179 (sc->tx_ticks_int << 16) | sc->tx_ticks); 5180 5181 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5182 } 5183 5184 /* 5185 * Tell the HC block to automatically set the 5186 * INT_MASK bit after an MSI/MSI-X interrupt 5187 * is generated so the driver doesn't have to. 5188 */ 5189 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG) 5190 val |= BCE_HC_CONFIG_ONE_SHOT; 5191 5192 /* Set the MSI-X status blocks to 128 byte boundaries. */ 5193 if (sc->bce_flags & BCE_USING_MSIX_FLAG) 5194 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5195 #endif 5196 5197 REG_WR(sc, BCE_HC_CONFIG, val); 5198 5199 /* Clear the internal statistics counters. */ 5200 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 5201 5202 /* Verify that bootcode is running. */ 5203 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE); 5204 5205 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control), 5206 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 5207 __FILE__, __LINE__); 5208 reg = 0); 5209 5210 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 5211 BCE_DEV_INFO_SIGNATURE_MAGIC) { 5212 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 5213 "Expected: 08%08X\n", __FILE__, __LINE__, 5214 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 5215 BCE_DEV_INFO_SIGNATURE_MAGIC); 5216 rc = ENODEV; 5217 goto bce_blockinit_exit; 5218 } 5219 5220 /* Enable DMA */ 5221 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5222 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 5223 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 5224 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 5225 } 5226 5227 /* Allow bootcode to apply additional fixes before enabling MAC. */ 5228 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | 5229 BCE_DRV_MSG_CODE_RESET); 5230 5231 /* Enable link state change interrupt generation. */ 5232 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 5233 5234 /* Enable the RXP. */ 5235 bce_start_rxp_cpu(sc); 5236 5237 /* Disable management frames (NC-SI) from flowing to the MCP. */ 5238 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5239 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) & 5240 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5241 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5242 } 5243 5244 /* Enable all remaining blocks in the MAC. */ 5245 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5246 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5247 BCE_MISC_ENABLE_DEFAULT_XI); 5248 else 5249 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5250 BCE_MISC_ENABLE_DEFAULT); 5251 5252 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 5253 DELAY(20); 5254 5255 /* Save the current host coalescing block settings. */ 5256 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND); 5257 5258 bce_blockinit_exit: 5259 DBEXIT(BCE_VERBOSE_RESET); 5260 5261 return (rc); 5262 } 5263 5264 /****************************************************************************/ 5265 /* Encapsulate an mbuf into the rx_bd chain. */ 5266 /* */ 5267 /* Returns: */ 5268 /* 0 for success, positive value for failure. */ 5269 /****************************************************************************/ 5270 static int 5271 bce_get_rx_buf(struct bce_softc *sc, u16 prod, u16 chain_prod, u32 *prod_bseq) 5272 { 5273 bus_dma_segment_t segs[1]; 5274 struct mbuf *m_new = NULL; 5275 struct rx_bd *rxbd; 5276 int nsegs, error, rc = 0; 5277 #ifdef BCE_DEBUG 5278 u16 debug_chain_prod = chain_prod; 5279 #endif 5280 5281 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5282 5283 /* Make sure the inputs are valid. */ 5284 DBRUNIF((chain_prod > MAX_RX_BD_ALLOC), 5285 BCE_PRINTF("%s(%d): RX producer out of range: " 5286 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5287 chain_prod, (u16)MAX_RX_BD_ALLOC)); 5288 5289 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5290 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, 5291 prod, chain_prod, *prod_bseq); 5292 5293 /* Update some debug statistic counters */ 5294 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 5295 sc->rx_low_watermark = sc->free_rx_bd); 5296 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 5297 sc->rx_empty_count++); 5298 5299 /* Simulate an mbuf allocation failure. */ 5300 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5301 sc->mbuf_alloc_failed_count++; 5302 sc->mbuf_alloc_failed_sim_count++; 5303 rc = ENOBUFS; 5304 goto bce_get_rx_buf_exit); 5305 5306 /* This is a new mbuf allocation. */ 5307 if (bce_hdr_split == TRUE) 5308 MGETHDR(m_new, M_NOWAIT, MT_DATA); 5309 else 5310 m_new = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, 5311 sc->rx_bd_mbuf_alloc_size); 5312 5313 if (m_new == NULL) { 5314 sc->mbuf_alloc_failed_count++; 5315 rc = ENOBUFS; 5316 goto bce_get_rx_buf_exit; 5317 } 5318 5319 DBRUN(sc->debug_rx_mbuf_alloc++); 5320 5321 /* Make sure we have a valid packet header. */ 5322 M_ASSERTPKTHDR(m_new); 5323 5324 /* Initialize the mbuf size and pad if necessary for alignment. */ 5325 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size; 5326 m_adj(m_new, sc->rx_bd_mbuf_align_pad); 5327 5328 /* ToDo: Consider calling m_fragment() to test error handling. */ 5329 5330 /* Map the mbuf cluster into device memory. */ 5331 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, 5332 sc->rx_mbuf_map[chain_prod], m_new, segs, &nsegs, BUS_DMA_NOWAIT); 5333 5334 /* Handle any mapping errors. */ 5335 if (error) { 5336 BCE_PRINTF("%s(%d): Error mapping mbuf into RX " 5337 "chain (%d)!\n", __FILE__, __LINE__, error); 5338 5339 sc->dma_map_addr_rx_failed_count++; 5340 m_freem(m_new); 5341 5342 DBRUN(sc->debug_rx_mbuf_alloc--); 5343 5344 rc = ENOBUFS; 5345 goto bce_get_rx_buf_exit; 5346 } 5347 5348 /* All mbufs must map to a single segment. */ 5349 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5350 __FUNCTION__, nsegs)); 5351 5352 /* Setup the rx_bd for the segment. */ 5353 rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)]; 5354 5355 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5356 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5357 rxbd->rx_bd_len = htole32(segs[0].ds_len); 5358 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5359 *prod_bseq += segs[0].ds_len; 5360 5361 /* Save the mbuf and update our counter. */ 5362 sc->rx_mbuf_ptr[chain_prod] = m_new; 5363 sc->free_rx_bd -= nsegs; 5364 5365 DBRUNMSG(BCE_INSANE_RECV, 5366 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs)); 5367 5368 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5369 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, prod, 5370 chain_prod, *prod_bseq); 5371 5372 bce_get_rx_buf_exit: 5373 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5374 5375 return(rc); 5376 } 5377 5378 /****************************************************************************/ 5379 /* Encapsulate an mbuf cluster into the page chain. */ 5380 /* */ 5381 /* Returns: */ 5382 /* 0 for success, positive value for failure. */ 5383 /****************************************************************************/ 5384 static int 5385 bce_get_pg_buf(struct bce_softc *sc, u16 prod, u16 prod_idx) 5386 { 5387 bus_dma_segment_t segs[1]; 5388 struct mbuf *m_new = NULL; 5389 struct rx_bd *pgbd; 5390 int error, nsegs, rc = 0; 5391 #ifdef BCE_DEBUG 5392 u16 debug_prod_idx = prod_idx; 5393 #endif 5394 5395 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5396 5397 /* Make sure the inputs are valid. */ 5398 DBRUNIF((prod_idx > MAX_PG_BD_ALLOC), 5399 BCE_PRINTF("%s(%d): page producer out of range: " 5400 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5401 prod_idx, (u16)MAX_PG_BD_ALLOC)); 5402 5403 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5404 "chain_prod = 0x%04X\n", __FUNCTION__, prod, prod_idx); 5405 5406 /* Update counters if we've hit a new low or run out of pages. */ 5407 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark), 5408 sc->pg_low_watermark = sc->free_pg_bd); 5409 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++); 5410 5411 /* Simulate an mbuf allocation failure. */ 5412 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5413 sc->mbuf_alloc_failed_count++; 5414 sc->mbuf_alloc_failed_sim_count++; 5415 rc = ENOBUFS; 5416 goto bce_get_pg_buf_exit); 5417 5418 /* This is a new mbuf allocation. */ 5419 m_new = m_getcl(M_NOWAIT, MT_DATA, 0); 5420 if (m_new == NULL) { 5421 sc->mbuf_alloc_failed_count++; 5422 rc = ENOBUFS; 5423 goto bce_get_pg_buf_exit; 5424 } 5425 5426 DBRUN(sc->debug_pg_mbuf_alloc++); 5427 5428 m_new->m_len = MCLBYTES; 5429 5430 /* ToDo: Consider calling m_fragment() to test error handling. */ 5431 5432 /* Map the mbuf cluster into device memory. */ 5433 error = bus_dmamap_load_mbuf_sg(sc->pg_mbuf_tag, 5434 sc->pg_mbuf_map[prod_idx], m_new, segs, &nsegs, BUS_DMA_NOWAIT); 5435 5436 /* Handle any mapping errors. */ 5437 if (error) { 5438 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n", 5439 __FILE__, __LINE__); 5440 5441 m_freem(m_new); 5442 DBRUN(sc->debug_pg_mbuf_alloc--); 5443 5444 rc = ENOBUFS; 5445 goto bce_get_pg_buf_exit; 5446 } 5447 5448 /* All mbufs must map to a single segment. */ 5449 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5450 __FUNCTION__, nsegs)); 5451 5452 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */ 5453 5454 /* 5455 * The page chain uses the same rx_bd data structure 5456 * as the receive chain but doesn't require a byte sequence (bseq). 5457 */ 5458 pgbd = &sc->pg_bd_chain[PG_PAGE(prod_idx)][PG_IDX(prod_idx)]; 5459 5460 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5461 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5462 pgbd->rx_bd_len = htole32(MCLBYTES); 5463 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5464 5465 /* Save the mbuf and update our counter. */ 5466 sc->pg_mbuf_ptr[prod_idx] = m_new; 5467 sc->free_pg_bd--; 5468 5469 DBRUNMSG(BCE_INSANE_RECV, 5470 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1)); 5471 5472 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5473 "prod_idx = 0x%04X\n", __FUNCTION__, prod, prod_idx); 5474 5475 bce_get_pg_buf_exit: 5476 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5477 5478 return(rc); 5479 } 5480 5481 /****************************************************************************/ 5482 /* Initialize the TX context memory. */ 5483 /* */ 5484 /* Returns: */ 5485 /* Nothing */ 5486 /****************************************************************************/ 5487 static void 5488 bce_init_tx_context(struct bce_softc *sc) 5489 { 5490 u32 val; 5491 5492 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5493 5494 /* Initialize the context ID for an L2 TX chain. */ 5495 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5496 /* Set the CID type to support an L2 connection. */ 5497 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI | 5498 BCE_L2CTX_TX_TYPE_SIZE_L2_XI; 5499 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val); 5500 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16); 5501 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5502 BCE_L2CTX_TX_CMD_TYPE_XI, val); 5503 5504 /* Point the hardware to the first page in the chain. */ 5505 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5506 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5507 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val); 5508 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5509 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5510 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val); 5511 } else { 5512 /* Set the CID type to support an L2 connection. */ 5513 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2; 5514 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val); 5515 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16); 5516 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val); 5517 5518 /* Point the hardware to the first page in the chain. */ 5519 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5520 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5521 BCE_L2CTX_TX_TBDR_BHADDR_HI, val); 5522 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5523 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5524 BCE_L2CTX_TX_TBDR_BHADDR_LO, val); 5525 } 5526 5527 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5528 } 5529 5530 /****************************************************************************/ 5531 /* Allocate memory and initialize the TX data structures. */ 5532 /* */ 5533 /* Returns: */ 5534 /* 0 for success, positive value for failure. */ 5535 /****************************************************************************/ 5536 static int 5537 bce_init_tx_chain(struct bce_softc *sc) 5538 { 5539 struct tx_bd *txbd; 5540 int i, rc = 0; 5541 5542 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5543 5544 /* Set the initial TX producer/consumer indices. */ 5545 sc->tx_prod = 0; 5546 sc->tx_cons = 0; 5547 sc->tx_prod_bseq = 0; 5548 sc->used_tx_bd = 0; 5549 sc->max_tx_bd = USABLE_TX_BD_ALLOC; 5550 DBRUN(sc->tx_hi_watermark = 0); 5551 DBRUN(sc->tx_full_count = 0); 5552 5553 /* 5554 * The NetXtreme II supports a linked-list structure called 5555 * a Buffer Descriptor Chain (or BD chain). A BD chain 5556 * consists of a series of 1 or more chain pages, each of which 5557 * consists of a fixed number of BD entries. 5558 * The last BD entry on each page is a pointer to the next page 5559 * in the chain, and the last pointer in the BD chain 5560 * points back to the beginning of the chain. 5561 */ 5562 5563 /* Set the TX next pointer chain entries. */ 5564 for (i = 0; i < sc->tx_pages; i++) { 5565 int j; 5566 5567 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 5568 5569 /* Check if we've reached the last page. */ 5570 if (i == (sc->tx_pages - 1)) 5571 j = 0; 5572 else 5573 j = i + 1; 5574 5575 txbd->tx_bd_haddr_hi = 5576 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 5577 txbd->tx_bd_haddr_lo = 5578 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 5579 } 5580 5581 bce_init_tx_context(sc); 5582 5583 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC)); 5584 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5585 5586 return(rc); 5587 } 5588 5589 /****************************************************************************/ 5590 /* Free memory and clear the TX data structures. */ 5591 /* */ 5592 /* Returns: */ 5593 /* Nothing. */ 5594 /****************************************************************************/ 5595 static void 5596 bce_free_tx_chain(struct bce_softc *sc) 5597 { 5598 int i; 5599 5600 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5601 5602 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 5603 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 5604 if (sc->tx_mbuf_ptr[i] != NULL) { 5605 if (sc->tx_mbuf_map[i] != NULL) 5606 bus_dmamap_sync(sc->tx_mbuf_tag, 5607 sc->tx_mbuf_map[i], 5608 BUS_DMASYNC_POSTWRITE); 5609 m_freem(sc->tx_mbuf_ptr[i]); 5610 sc->tx_mbuf_ptr[i] = NULL; 5611 DBRUN(sc->debug_tx_mbuf_alloc--); 5612 } 5613 } 5614 5615 /* Clear each TX chain page. */ 5616 for (i = 0; i < sc->tx_pages; i++) 5617 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 5618 5619 sc->used_tx_bd = 0; 5620 5621 /* Check if we lost any mbufs in the process. */ 5622 DBRUNIF((sc->debug_tx_mbuf_alloc), 5623 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 5624 "from tx chain!\n", __FILE__, __LINE__, 5625 sc->debug_tx_mbuf_alloc)); 5626 5627 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5628 } 5629 5630 /****************************************************************************/ 5631 /* Initialize the RX context memory. */ 5632 /* */ 5633 /* Returns: */ 5634 /* Nothing */ 5635 /****************************************************************************/ 5636 static void 5637 bce_init_rx_context(struct bce_softc *sc) 5638 { 5639 u32 val; 5640 5641 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5642 5643 /* Init the type, size, and BD cache levels for the RX context. */ 5644 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 5645 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | 5646 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT); 5647 5648 /* 5649 * Set the level for generating pause frames 5650 * when the number of available rx_bd's gets 5651 * too low (the low watermark) and the level 5652 * when pause frames can be stopped (the high 5653 * watermark). 5654 */ 5655 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5656 u32 lo_water, hi_water; 5657 5658 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) { 5659 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT; 5660 } else { 5661 lo_water = 0; 5662 } 5663 5664 if (lo_water >= USABLE_RX_BD_ALLOC) { 5665 lo_water = 0; 5666 } 5667 5668 hi_water = USABLE_RX_BD_ALLOC / 4; 5669 5670 if (hi_water <= lo_water) { 5671 lo_water = 0; 5672 } 5673 5674 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE; 5675 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE; 5676 5677 if (hi_water > 0xf) 5678 hi_water = 0xf; 5679 else if (hi_water == 0) 5680 lo_water = 0; 5681 5682 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) | 5683 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT); 5684 } 5685 5686 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val); 5687 5688 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 5689 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5690 val = REG_RD(sc, BCE_MQ_MAP_L2_5); 5691 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM); 5692 } 5693 5694 /* Point the hardware to the first page in the chain. */ 5695 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 5696 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val); 5697 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 5698 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val); 5699 5700 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5701 } 5702 5703 /****************************************************************************/ 5704 /* Allocate memory and initialize the RX data structures. */ 5705 /* */ 5706 /* Returns: */ 5707 /* 0 for success, positive value for failure. */ 5708 /****************************************************************************/ 5709 static int 5710 bce_init_rx_chain(struct bce_softc *sc) 5711 { 5712 struct rx_bd *rxbd; 5713 int i, rc = 0; 5714 5715 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5716 BCE_VERBOSE_CTX); 5717 5718 /* Initialize the RX producer and consumer indices. */ 5719 sc->rx_prod = 0; 5720 sc->rx_cons = 0; 5721 sc->rx_prod_bseq = 0; 5722 sc->free_rx_bd = USABLE_RX_BD_ALLOC; 5723 sc->max_rx_bd = USABLE_RX_BD_ALLOC; 5724 5725 /* Initialize the RX next pointer chain entries. */ 5726 for (i = 0; i < sc->rx_pages; i++) { 5727 int j; 5728 5729 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 5730 5731 /* Check if we've reached the last page. */ 5732 if (i == (sc->rx_pages - 1)) 5733 j = 0; 5734 else 5735 j = i + 1; 5736 5737 /* Setup the chain page pointers. */ 5738 rxbd->rx_bd_haddr_hi = 5739 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 5740 rxbd->rx_bd_haddr_lo = 5741 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 5742 } 5743 5744 /* Fill up the RX chain. */ 5745 bce_fill_rx_chain(sc); 5746 5747 DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC); 5748 DBRUN(sc->rx_empty_count = 0); 5749 for (i = 0; i < sc->rx_pages; i++) { 5750 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i], 5751 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5752 } 5753 5754 bce_init_rx_context(sc); 5755 5756 DBRUNMSG(BCE_EXTREME_RECV, 5757 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC)); 5758 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5759 BCE_VERBOSE_CTX); 5760 5761 /* ToDo: Are there possible failure modes here? */ 5762 5763 return(rc); 5764 } 5765 5766 /****************************************************************************/ 5767 /* Add mbufs to the RX chain until its full or an mbuf allocation error */ 5768 /* occurs. */ 5769 /* */ 5770 /* Returns: */ 5771 /* Nothing */ 5772 /****************************************************************************/ 5773 static void 5774 bce_fill_rx_chain(struct bce_softc *sc) 5775 { 5776 u16 prod, prod_idx; 5777 u32 prod_bseq; 5778 5779 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5780 BCE_VERBOSE_CTX); 5781 5782 /* Get the RX chain producer indices. */ 5783 prod = sc->rx_prod; 5784 prod_bseq = sc->rx_prod_bseq; 5785 5786 /* Keep filling the RX chain until it's full. */ 5787 while (sc->free_rx_bd > 0) { 5788 prod_idx = RX_CHAIN_IDX(prod); 5789 if (bce_get_rx_buf(sc, prod, prod_idx, &prod_bseq)) { 5790 /* Bail out if we can't add an mbuf to the chain. */ 5791 break; 5792 } 5793 prod = NEXT_RX_BD(prod); 5794 } 5795 5796 /* Save the RX chain producer indices. */ 5797 sc->rx_prod = prod; 5798 sc->rx_prod_bseq = prod_bseq; 5799 5800 /* We should never end up pointing to a next page pointer. */ 5801 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5802 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n", 5803 __FUNCTION__, rx_prod)); 5804 5805 /* Write the mailbox and tell the chip about the waiting rx_bd's. */ 5806 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX, prod); 5807 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ, prod_bseq); 5808 5809 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5810 BCE_VERBOSE_CTX); 5811 } 5812 5813 /****************************************************************************/ 5814 /* Free memory and clear the RX data structures. */ 5815 /* */ 5816 /* Returns: */ 5817 /* Nothing. */ 5818 /****************************************************************************/ 5819 static void 5820 bce_free_rx_chain(struct bce_softc *sc) 5821 { 5822 int i; 5823 5824 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5825 5826 /* Free any mbufs still in the RX mbuf chain. */ 5827 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 5828 if (sc->rx_mbuf_ptr[i] != NULL) { 5829 if (sc->rx_mbuf_map[i] != NULL) 5830 bus_dmamap_sync(sc->rx_mbuf_tag, 5831 sc->rx_mbuf_map[i], 5832 BUS_DMASYNC_POSTREAD); 5833 m_freem(sc->rx_mbuf_ptr[i]); 5834 sc->rx_mbuf_ptr[i] = NULL; 5835 DBRUN(sc->debug_rx_mbuf_alloc--); 5836 } 5837 } 5838 5839 /* Clear each RX chain page. */ 5840 for (i = 0; i < sc->rx_pages; i++) 5841 if (sc->rx_bd_chain[i] != NULL) 5842 bzero((char *)sc->rx_bd_chain[i], 5843 BCE_RX_CHAIN_PAGE_SZ); 5844 5845 sc->free_rx_bd = sc->max_rx_bd; 5846 5847 /* Check if we lost any mbufs in the process. */ 5848 DBRUNIF((sc->debug_rx_mbuf_alloc), 5849 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n", 5850 __FUNCTION__, sc->debug_rx_mbuf_alloc)); 5851 5852 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5853 } 5854 5855 /****************************************************************************/ 5856 /* Allocate memory and initialize the page data structures. */ 5857 /* Assumes that bce_init_rx_chain() has not already been called. */ 5858 /* */ 5859 /* Returns: */ 5860 /* 0 for success, positive value for failure. */ 5861 /****************************************************************************/ 5862 static int 5863 bce_init_pg_chain(struct bce_softc *sc) 5864 { 5865 struct rx_bd *pgbd; 5866 int i, rc = 0; 5867 u32 val; 5868 5869 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5870 BCE_VERBOSE_CTX); 5871 5872 /* Initialize the page producer and consumer indices. */ 5873 sc->pg_prod = 0; 5874 sc->pg_cons = 0; 5875 sc->free_pg_bd = USABLE_PG_BD_ALLOC; 5876 sc->max_pg_bd = USABLE_PG_BD_ALLOC; 5877 DBRUN(sc->pg_low_watermark = sc->max_pg_bd); 5878 DBRUN(sc->pg_empty_count = 0); 5879 5880 /* Initialize the page next pointer chain entries. */ 5881 for (i = 0; i < sc->pg_pages; i++) { 5882 int j; 5883 5884 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE]; 5885 5886 /* Check if we've reached the last page. */ 5887 if (i == (sc->pg_pages - 1)) 5888 j = 0; 5889 else 5890 j = i + 1; 5891 5892 /* Setup the chain page pointers. */ 5893 pgbd->rx_bd_haddr_hi = 5894 htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j])); 5895 pgbd->rx_bd_haddr_lo = 5896 htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j])); 5897 } 5898 5899 /* Setup the MQ BIN mapping for host_pg_bidx. */ 5900 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5901 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT); 5902 5903 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0); 5904 5905 /* Configure the rx_bd and page chain mbuf cluster size. */ 5906 val = (sc->rx_bd_mbuf_data_len << 16) | MCLBYTES; 5907 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val); 5908 5909 /* Configure the context reserved for jumbo support. */ 5910 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY, 5911 BCE_L2CTX_RX_RBDC_JUMBO_KEY); 5912 5913 /* Point the hardware to the first page in the page chain. */ 5914 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]); 5915 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val); 5916 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]); 5917 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val); 5918 5919 /* Fill up the page chain. */ 5920 bce_fill_pg_chain(sc); 5921 5922 for (i = 0; i < sc->pg_pages; i++) { 5923 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i], 5924 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5925 } 5926 5927 DBRUNMSG(BCE_EXTREME_RECV, 5928 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC)); 5929 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5930 BCE_VERBOSE_CTX); 5931 return(rc); 5932 } 5933 5934 /****************************************************************************/ 5935 /* Add mbufs to the page chain until its full or an mbuf allocation error */ 5936 /* occurs. */ 5937 /* */ 5938 /* Returns: */ 5939 /* Nothing */ 5940 /****************************************************************************/ 5941 static void 5942 bce_fill_pg_chain(struct bce_softc *sc) 5943 { 5944 u16 prod, prod_idx; 5945 5946 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5947 BCE_VERBOSE_CTX); 5948 5949 /* Get the page chain prodcuer index. */ 5950 prod = sc->pg_prod; 5951 5952 /* Keep filling the page chain until it's full. */ 5953 while (sc->free_pg_bd > 0) { 5954 prod_idx = PG_CHAIN_IDX(prod); 5955 if (bce_get_pg_buf(sc, prod, prod_idx)) { 5956 /* Bail out if we can't add an mbuf to the chain. */ 5957 break; 5958 } 5959 prod = NEXT_PG_BD(prod); 5960 } 5961 5962 /* Save the page chain producer index. */ 5963 sc->pg_prod = prod; 5964 5965 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5966 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n", 5967 __FUNCTION__, pg_prod)); 5968 5969 /* 5970 * Write the mailbox and tell the chip about 5971 * the new rx_bd's in the page chain. 5972 */ 5973 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_PG_BDIDX, 5974 prod); 5975 5976 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5977 BCE_VERBOSE_CTX); 5978 } 5979 5980 /****************************************************************************/ 5981 /* Free memory and clear the RX data structures. */ 5982 /* */ 5983 /* Returns: */ 5984 /* Nothing. */ 5985 /****************************************************************************/ 5986 static void 5987 bce_free_pg_chain(struct bce_softc *sc) 5988 { 5989 int i; 5990 5991 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5992 5993 /* Free any mbufs still in the mbuf page chain. */ 5994 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 5995 if (sc->pg_mbuf_ptr[i] != NULL) { 5996 if (sc->pg_mbuf_map[i] != NULL) 5997 bus_dmamap_sync(sc->pg_mbuf_tag, 5998 sc->pg_mbuf_map[i], 5999 BUS_DMASYNC_POSTREAD); 6000 m_freem(sc->pg_mbuf_ptr[i]); 6001 sc->pg_mbuf_ptr[i] = NULL; 6002 DBRUN(sc->debug_pg_mbuf_alloc--); 6003 } 6004 } 6005 6006 /* Clear each page chain pages. */ 6007 for (i = 0; i < sc->pg_pages; i++) 6008 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 6009 6010 sc->free_pg_bd = sc->max_pg_bd; 6011 6012 /* Check if we lost any mbufs in the process. */ 6013 DBRUNIF((sc->debug_pg_mbuf_alloc), 6014 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n", 6015 __FUNCTION__, sc->debug_pg_mbuf_alloc)); 6016 6017 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6018 } 6019 6020 static u32 6021 bce_get_rphy_link(struct bce_softc *sc) 6022 { 6023 u32 advertise, link; 6024 int fdpx; 6025 6026 advertise = 0; 6027 fdpx = 0; 6028 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) 6029 link = bce_shmem_rd(sc, BCE_RPHY_SERDES_LINK); 6030 else 6031 link = bce_shmem_rd(sc, BCE_RPHY_COPPER_LINK); 6032 if (link & BCE_NETLINK_ANEG_ENB) 6033 advertise |= BCE_NETLINK_ANEG_ENB; 6034 if (link & BCE_NETLINK_SPEED_10HALF) 6035 advertise |= BCE_NETLINK_SPEED_10HALF; 6036 if (link & BCE_NETLINK_SPEED_10FULL) { 6037 advertise |= BCE_NETLINK_SPEED_10FULL; 6038 fdpx++; 6039 } 6040 if (link & BCE_NETLINK_SPEED_100HALF) 6041 advertise |= BCE_NETLINK_SPEED_100HALF; 6042 if (link & BCE_NETLINK_SPEED_100FULL) { 6043 advertise |= BCE_NETLINK_SPEED_100FULL; 6044 fdpx++; 6045 } 6046 if (link & BCE_NETLINK_SPEED_1000HALF) 6047 advertise |= BCE_NETLINK_SPEED_1000HALF; 6048 if (link & BCE_NETLINK_SPEED_1000FULL) { 6049 advertise |= BCE_NETLINK_SPEED_1000FULL; 6050 fdpx++; 6051 } 6052 if (link & BCE_NETLINK_SPEED_2500HALF) 6053 advertise |= BCE_NETLINK_SPEED_2500HALF; 6054 if (link & BCE_NETLINK_SPEED_2500FULL) { 6055 advertise |= BCE_NETLINK_SPEED_2500FULL; 6056 fdpx++; 6057 } 6058 if (fdpx) 6059 advertise |= BCE_NETLINK_FC_PAUSE_SYM | 6060 BCE_NETLINK_FC_PAUSE_ASYM; 6061 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6062 advertise |= BCE_NETLINK_PHY_APP_REMOTE | 6063 BCE_NETLINK_ETH_AT_WIRESPEED; 6064 6065 return (advertise); 6066 } 6067 6068 /****************************************************************************/ 6069 /* Set media options. */ 6070 /* */ 6071 /* Returns: */ 6072 /* 0 for success, positive value for failure. */ 6073 /****************************************************************************/ 6074 static int 6075 bce_ifmedia_upd(struct ifnet *ifp) 6076 { 6077 struct bce_softc *sc = ifp->if_softc; 6078 int error; 6079 6080 DBENTER(BCE_VERBOSE); 6081 6082 BCE_LOCK(sc); 6083 error = bce_ifmedia_upd_locked(ifp); 6084 BCE_UNLOCK(sc); 6085 6086 DBEXIT(BCE_VERBOSE); 6087 return (error); 6088 } 6089 6090 /****************************************************************************/ 6091 /* Set media options. */ 6092 /* */ 6093 /* Returns: */ 6094 /* Nothing. */ 6095 /****************************************************************************/ 6096 static int 6097 bce_ifmedia_upd_locked(struct ifnet *ifp) 6098 { 6099 struct bce_softc *sc = ifp->if_softc; 6100 struct mii_data *mii; 6101 struct mii_softc *miisc; 6102 struct ifmedia *ifm; 6103 u32 link; 6104 int error, fdx; 6105 6106 DBENTER(BCE_VERBOSE_PHY); 6107 6108 error = 0; 6109 BCE_LOCK_ASSERT(sc); 6110 6111 sc->bce_link_up = FALSE; 6112 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 6113 ifm = &sc->bce_ifmedia; 6114 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 6115 return (EINVAL); 6116 link = 0; 6117 fdx = IFM_OPTIONS(ifm->ifm_media) & IFM_FDX; 6118 switch(IFM_SUBTYPE(ifm->ifm_media)) { 6119 case IFM_AUTO: 6120 /* 6121 * Check advertised link of remote PHY by reading 6122 * BCE_RPHY_SERDES_LINK or BCE_RPHY_COPPER_LINK. 6123 * Always use the same link type of remote PHY. 6124 */ 6125 link = bce_get_rphy_link(sc); 6126 break; 6127 case IFM_2500_SX: 6128 if ((sc->bce_phy_flags & 6129 (BCE_PHY_REMOTE_PORT_FIBER_FLAG | 6130 BCE_PHY_2_5G_CAPABLE_FLAG)) == 0) 6131 return (EINVAL); 6132 /* 6133 * XXX 6134 * Have to enable forced 2.5Gbps configuration. 6135 */ 6136 if (fdx != 0) 6137 link |= BCE_NETLINK_SPEED_2500FULL; 6138 else 6139 link |= BCE_NETLINK_SPEED_2500HALF; 6140 break; 6141 case IFM_1000_SX: 6142 if ((sc->bce_phy_flags & 6143 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6144 return (EINVAL); 6145 /* 6146 * XXX 6147 * Have to disable 2.5Gbps configuration. 6148 */ 6149 if (fdx != 0) 6150 link = BCE_NETLINK_SPEED_1000FULL; 6151 else 6152 link = BCE_NETLINK_SPEED_1000HALF; 6153 break; 6154 case IFM_1000_T: 6155 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6156 return (EINVAL); 6157 if (fdx != 0) 6158 link = BCE_NETLINK_SPEED_1000FULL; 6159 else 6160 link = BCE_NETLINK_SPEED_1000HALF; 6161 break; 6162 case IFM_100_TX: 6163 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6164 return (EINVAL); 6165 if (fdx != 0) 6166 link = BCE_NETLINK_SPEED_100FULL; 6167 else 6168 link = BCE_NETLINK_SPEED_100HALF; 6169 break; 6170 case IFM_10_T: 6171 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6172 return (EINVAL); 6173 if (fdx != 0) 6174 link = BCE_NETLINK_SPEED_10FULL; 6175 else 6176 link = BCE_NETLINK_SPEED_10HALF; 6177 break; 6178 default: 6179 return (EINVAL); 6180 } 6181 if (IFM_SUBTYPE(ifm->ifm_media) != IFM_AUTO) { 6182 /* 6183 * XXX 6184 * Advertise pause capability for full-duplex media. 6185 */ 6186 if (fdx != 0) 6187 link |= BCE_NETLINK_FC_PAUSE_SYM | 6188 BCE_NETLINK_FC_PAUSE_ASYM; 6189 if ((sc->bce_phy_flags & 6190 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6191 link |= BCE_NETLINK_PHY_APP_REMOTE | 6192 BCE_NETLINK_ETH_AT_WIRESPEED; 6193 } 6194 6195 bce_shmem_wr(sc, BCE_MB_ARGS_0, link); 6196 error = bce_fw_sync(sc, BCE_DRV_MSG_CODE_CMD_SET_LINK); 6197 } else { 6198 mii = device_get_softc(sc->bce_miibus); 6199 6200 /* Make sure the MII bus has been enumerated. */ 6201 if (mii) { 6202 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 6203 PHY_RESET(miisc); 6204 error = mii_mediachg(mii); 6205 } 6206 } 6207 6208 DBEXIT(BCE_VERBOSE_PHY); 6209 return (error); 6210 } 6211 6212 static void 6213 bce_ifmedia_sts_rphy(struct bce_softc *sc, struct ifmediareq *ifmr) 6214 { 6215 struct ifnet *ifp; 6216 u32 link; 6217 6218 ifp = sc->bce_ifp; 6219 BCE_LOCK_ASSERT(sc); 6220 6221 ifmr->ifm_status = IFM_AVALID; 6222 ifmr->ifm_active = IFM_ETHER; 6223 link = bce_shmem_rd(sc, BCE_LINK_STATUS); 6224 /* XXX Handle heart beat status? */ 6225 if ((link & BCE_LINK_STATUS_LINK_UP) != 0) 6226 ifmr->ifm_status |= IFM_ACTIVE; 6227 else { 6228 ifmr->ifm_active |= IFM_NONE; 6229 ifp->if_baudrate = 0; 6230 return; 6231 } 6232 switch (link & BCE_LINK_STATUS_SPEED_MASK) { 6233 case BCE_LINK_STATUS_10HALF: 6234 ifmr->ifm_active |= IFM_10_T | IFM_HDX; 6235 ifp->if_baudrate = IF_Mbps(10UL); 6236 break; 6237 case BCE_LINK_STATUS_10FULL: 6238 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 6239 ifp->if_baudrate = IF_Mbps(10UL); 6240 break; 6241 case BCE_LINK_STATUS_100HALF: 6242 ifmr->ifm_active |= IFM_100_TX | IFM_HDX; 6243 ifp->if_baudrate = IF_Mbps(100UL); 6244 break; 6245 case BCE_LINK_STATUS_100FULL: 6246 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 6247 ifp->if_baudrate = IF_Mbps(100UL); 6248 break; 6249 case BCE_LINK_STATUS_1000HALF: 6250 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6251 ifmr->ifm_active |= IFM_1000_T | IFM_HDX; 6252 else 6253 ifmr->ifm_active |= IFM_1000_SX | IFM_HDX; 6254 ifp->if_baudrate = IF_Mbps(1000UL); 6255 break; 6256 case BCE_LINK_STATUS_1000FULL: 6257 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6258 ifmr->ifm_active |= IFM_1000_T | IFM_FDX; 6259 else 6260 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 6261 ifp->if_baudrate = IF_Mbps(1000UL); 6262 break; 6263 case BCE_LINK_STATUS_2500HALF: 6264 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) { 6265 ifmr->ifm_active |= IFM_NONE; 6266 return; 6267 } else 6268 ifmr->ifm_active |= IFM_2500_SX | IFM_HDX; 6269 ifp->if_baudrate = IF_Mbps(2500UL); 6270 break; 6271 case BCE_LINK_STATUS_2500FULL: 6272 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) { 6273 ifmr->ifm_active |= IFM_NONE; 6274 return; 6275 } else 6276 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX; 6277 ifp->if_baudrate = IF_Mbps(2500UL); 6278 break; 6279 default: 6280 ifmr->ifm_active |= IFM_NONE; 6281 return; 6282 } 6283 6284 if ((link & BCE_LINK_STATUS_RX_FC_ENABLED) != 0) 6285 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 6286 if ((link & BCE_LINK_STATUS_TX_FC_ENABLED) != 0) 6287 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 6288 } 6289 6290 /****************************************************************************/ 6291 /* Reports current media status. */ 6292 /* */ 6293 /* Returns: */ 6294 /* Nothing. */ 6295 /****************************************************************************/ 6296 static void 6297 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 6298 { 6299 struct bce_softc *sc = ifp->if_softc; 6300 struct mii_data *mii; 6301 6302 DBENTER(BCE_VERBOSE_PHY); 6303 6304 BCE_LOCK(sc); 6305 6306 if ((ifp->if_flags & IFF_UP) == 0) { 6307 BCE_UNLOCK(sc); 6308 return; 6309 } 6310 6311 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 6312 bce_ifmedia_sts_rphy(sc, ifmr); 6313 else { 6314 mii = device_get_softc(sc->bce_miibus); 6315 mii_pollstat(mii); 6316 ifmr->ifm_active = mii->mii_media_active; 6317 ifmr->ifm_status = mii->mii_media_status; 6318 } 6319 6320 BCE_UNLOCK(sc); 6321 6322 DBEXIT(BCE_VERBOSE_PHY); 6323 } 6324 6325 /****************************************************************************/ 6326 /* Handles PHY generated interrupt events. */ 6327 /* */ 6328 /* Returns: */ 6329 /* Nothing. */ 6330 /****************************************************************************/ 6331 static void 6332 bce_phy_intr(struct bce_softc *sc) 6333 { 6334 u32 new_link_state, old_link_state; 6335 6336 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6337 6338 DBRUN(sc->phy_interrupts++); 6339 6340 new_link_state = sc->status_block->status_attn_bits & 6341 STATUS_ATTN_BITS_LINK_STATE; 6342 old_link_state = sc->status_block->status_attn_bits_ack & 6343 STATUS_ATTN_BITS_LINK_STATE; 6344 6345 /* Handle any changes if the link state has changed. */ 6346 if (new_link_state != old_link_state) { 6347 /* Update the status_attn_bits_ack field. */ 6348 if (new_link_state) { 6349 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 6350 STATUS_ATTN_BITS_LINK_STATE); 6351 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n", 6352 __FUNCTION__); 6353 } else { 6354 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 6355 STATUS_ATTN_BITS_LINK_STATE); 6356 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n", 6357 __FUNCTION__); 6358 } 6359 6360 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 6361 if (new_link_state) { 6362 if (bootverbose) 6363 if_printf(sc->bce_ifp, "link UP\n"); 6364 if_link_state_change(sc->bce_ifp, 6365 LINK_STATE_UP); 6366 } else { 6367 if (bootverbose) 6368 if_printf(sc->bce_ifp, "link DOWN\n"); 6369 if_link_state_change(sc->bce_ifp, 6370 LINK_STATE_DOWN); 6371 } 6372 } 6373 /* 6374 * Assume link is down and allow 6375 * tick routine to update the state 6376 * based on the actual media state. 6377 */ 6378 sc->bce_link_up = FALSE; 6379 callout_stop(&sc->bce_tick_callout); 6380 bce_tick(sc); 6381 } 6382 6383 /* Acknowledge the link change interrupt. */ 6384 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 6385 6386 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6387 } 6388 6389 /****************************************************************************/ 6390 /* Reads the receive consumer value from the status block (skipping over */ 6391 /* chain page pointer if necessary). */ 6392 /* */ 6393 /* Returns: */ 6394 /* hw_cons */ 6395 /****************************************************************************/ 6396 static inline u16 6397 bce_get_hw_rx_cons(struct bce_softc *sc) 6398 { 6399 u16 hw_cons; 6400 6401 rmb(); 6402 hw_cons = sc->status_block->status_rx_quick_consumer_index0; 6403 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6404 hw_cons++; 6405 6406 return hw_cons; 6407 } 6408 6409 /****************************************************************************/ 6410 /* Handles received frame interrupt events. */ 6411 /* */ 6412 /* Returns: */ 6413 /* Nothing. */ 6414 /****************************************************************************/ 6415 static void 6416 bce_rx_intr(struct bce_softc *sc) 6417 { 6418 struct ifnet *ifp = sc->bce_ifp; 6419 struct l2_fhdr *l2fhdr; 6420 struct ether_vlan_header *vh; 6421 unsigned int pkt_len; 6422 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons; 6423 u32 status; 6424 unsigned int rem_len; 6425 u16 sw_pg_cons, sw_pg_cons_idx; 6426 6427 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6428 DBRUN(sc->interrupts_rx++); 6429 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, " 6430 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6431 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6432 6433 /* Prepare the RX chain pages to be accessed by the host CPU. */ 6434 for (int i = 0; i < sc->rx_pages; i++) 6435 bus_dmamap_sync(sc->rx_bd_chain_tag, 6436 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6437 6438 /* Prepare the page chain pages to be accessed by the host CPU. */ 6439 if (bce_hdr_split == TRUE) { 6440 for (int i = 0; i < sc->pg_pages; i++) 6441 bus_dmamap_sync(sc->pg_bd_chain_tag, 6442 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6443 } 6444 6445 /* Get the hardware's view of the RX consumer index. */ 6446 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6447 6448 /* Get working copies of the driver's view of the consumer indices. */ 6449 sw_rx_cons = sc->rx_cons; 6450 sw_pg_cons = sc->pg_cons; 6451 6452 /* Update some debug statistics counters */ 6453 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 6454 sc->rx_low_watermark = sc->free_rx_bd); 6455 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 6456 sc->rx_empty_count++); 6457 6458 /* Scan through the receive chain as long as there is work to do */ 6459 /* ToDo: Consider setting a limit on the number of packets processed. */ 6460 rmb(); 6461 while (sw_rx_cons != hw_rx_cons) { 6462 struct mbuf *m0; 6463 6464 /* Convert the producer/consumer indices to an actual rx_bd index. */ 6465 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons); 6466 6467 /* Unmap the mbuf from DMA space. */ 6468 bus_dmamap_sync(sc->rx_mbuf_tag, 6469 sc->rx_mbuf_map[sw_rx_cons_idx], 6470 BUS_DMASYNC_POSTREAD); 6471 bus_dmamap_unload(sc->rx_mbuf_tag, 6472 sc->rx_mbuf_map[sw_rx_cons_idx]); 6473 6474 /* Remove the mbuf from the RX chain. */ 6475 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx]; 6476 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL; 6477 DBRUN(sc->debug_rx_mbuf_alloc--); 6478 sc->free_rx_bd++; 6479 6480 /* 6481 * Frames received on the NetXteme II are prepended 6482 * with an l2_fhdr structure which provides status 6483 * information about the received frame (including 6484 * VLAN tags and checksum info). The frames are 6485 * also automatically adjusted to word align the IP 6486 * header (i.e. two null bytes are inserted before 6487 * the Ethernet header). As a result the data 6488 * DMA'd by the controller into the mbuf looks 6489 * like this: 6490 * 6491 * +---------+-----+---------------------+-----+ 6492 * | l2_fhdr | pad | packet data | FCS | 6493 * +---------+-----+---------------------+-----+ 6494 * 6495 * The l2_fhdr needs to be checked and skipped and 6496 * the FCS needs to be stripped before sending the 6497 * packet up the stack. 6498 */ 6499 l2fhdr = mtod(m0, struct l2_fhdr *); 6500 6501 /* Get the packet data + FCS length and the status. */ 6502 pkt_len = l2fhdr->l2_fhdr_pkt_len; 6503 status = l2fhdr->l2_fhdr_status; 6504 6505 /* 6506 * Skip over the l2_fhdr and pad, resulting in the 6507 * following data in the mbuf: 6508 * +---------------------+-----+ 6509 * | packet data | FCS | 6510 * +---------------------+-----+ 6511 */ 6512 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN); 6513 6514 /* 6515 * When split header mode is used, an ethernet frame 6516 * may be split across the receive chain and the 6517 * page chain. If that occurs an mbuf cluster must be 6518 * reassembled from the individual mbuf pieces. 6519 */ 6520 if (bce_hdr_split == TRUE) { 6521 /* 6522 * Check whether the received frame fits in a single 6523 * mbuf or not (i.e. packet data + FCS <= 6524 * sc->rx_bd_mbuf_data_len bytes). 6525 */ 6526 if (pkt_len > m0->m_len) { 6527 /* 6528 * The received frame is larger than a single mbuf. 6529 * If the frame was a TCP frame then only the TCP 6530 * header is placed in the mbuf, the remaining 6531 * payload (including FCS) is placed in the page 6532 * chain, the SPLIT flag is set, and the header 6533 * length is placed in the IP checksum field. 6534 * If the frame is not a TCP frame then the mbuf 6535 * is filled and the remaining bytes are placed 6536 * in the page chain. 6537 */ 6538 6539 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large " 6540 "packet.\n", __FUNCTION__); 6541 DBRUN(sc->split_header_frames_rcvd++); 6542 6543 /* 6544 * When the page chain is enabled and the TCP 6545 * header has been split from the TCP payload, 6546 * the ip_xsum structure will reflect the length 6547 * of the TCP header, not the IP checksum. Set 6548 * the packet length of the mbuf accordingly. 6549 */ 6550 if (status & L2_FHDR_STATUS_SPLIT) { 6551 m0->m_len = l2fhdr->l2_fhdr_ip_xsum; 6552 DBRUN(sc->split_header_tcp_frames_rcvd++); 6553 } 6554 6555 rem_len = pkt_len - m0->m_len; 6556 6557 /* Pull mbufs off the page chain for any remaining data. */ 6558 while (rem_len > 0) { 6559 struct mbuf *m_pg; 6560 6561 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons); 6562 6563 /* Remove the mbuf from the page chain. */ 6564 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx]; 6565 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL; 6566 DBRUN(sc->debug_pg_mbuf_alloc--); 6567 sc->free_pg_bd++; 6568 6569 /* Unmap the page chain mbuf from DMA space. */ 6570 bus_dmamap_sync(sc->pg_mbuf_tag, 6571 sc->pg_mbuf_map[sw_pg_cons_idx], 6572 BUS_DMASYNC_POSTREAD); 6573 bus_dmamap_unload(sc->pg_mbuf_tag, 6574 sc->pg_mbuf_map[sw_pg_cons_idx]); 6575 6576 /* Adjust the mbuf length. */ 6577 if (rem_len < m_pg->m_len) { 6578 /* The mbuf chain is complete. */ 6579 m_pg->m_len = rem_len; 6580 rem_len = 0; 6581 } else { 6582 /* More packet data is waiting. */ 6583 rem_len -= m_pg->m_len; 6584 } 6585 6586 /* Concatenate the mbuf cluster to the mbuf. */ 6587 m_cat(m0, m_pg); 6588 6589 sw_pg_cons = NEXT_PG_BD(sw_pg_cons); 6590 } 6591 6592 /* Set the total packet length. */ 6593 m0->m_pkthdr.len = pkt_len; 6594 6595 } else { 6596 /* 6597 * The received packet is small and fits in a 6598 * single mbuf (i.e. the l2_fhdr + pad + packet + 6599 * FCS <= MHLEN). In other words, the packet is 6600 * 154 bytes or less in size. 6601 */ 6602 6603 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small " 6604 "packet.\n", __FUNCTION__); 6605 6606 /* Set the total packet length. */ 6607 m0->m_pkthdr.len = m0->m_len = pkt_len; 6608 } 6609 } else 6610 /* Set the total packet length. */ 6611 m0->m_pkthdr.len = m0->m_len = pkt_len; 6612 6613 /* Remove the trailing Ethernet FCS. */ 6614 m_adj(m0, -ETHER_CRC_LEN); 6615 6616 /* Check that the resulting mbuf chain is valid. */ 6617 DBRUN(m_sanity(m0, FALSE)); 6618 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) | 6619 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 6620 BCE_PRINTF("Invalid Ethernet frame size!\n"); 6621 m_print(m0, 128)); 6622 6623 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control), 6624 sc->l2fhdr_error_sim_count++; 6625 status = status | L2_FHDR_ERRORS_PHY_DECODE); 6626 6627 /* Check the received frame for errors. */ 6628 if (status & (L2_FHDR_ERRORS_BAD_CRC | 6629 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 6630 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 6631 /* Log the error and release the mbuf. */ 6632 sc->l2fhdr_error_count++; 6633 m_freem(m0); 6634 m0 = NULL; 6635 goto bce_rx_intr_next_rx; 6636 } 6637 6638 /* Send the packet to the appropriate interface. */ 6639 m0->m_pkthdr.rcvif = ifp; 6640 6641 /* Assume no hardware checksum. */ 6642 m0->m_pkthdr.csum_flags = 0; 6643 6644 /* Validate the checksum if offload enabled. */ 6645 if (ifp->if_capenable & IFCAP_RXCSUM) { 6646 /* Check for an IP datagram. */ 6647 if (!(status & L2_FHDR_STATUS_SPLIT) && 6648 (status & L2_FHDR_STATUS_IP_DATAGRAM)) { 6649 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 6650 DBRUN(sc->csum_offload_ip++); 6651 /* Check if the IP checksum is valid. */ 6652 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 6653 m0->m_pkthdr.csum_flags |= 6654 CSUM_IP_VALID; 6655 } 6656 6657 /* Check for a valid TCP/UDP frame. */ 6658 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 6659 L2_FHDR_STATUS_UDP_DATAGRAM)) { 6660 /* Check for a good TCP/UDP checksum. */ 6661 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 6662 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 6663 DBRUN(sc->csum_offload_tcp_udp++); 6664 m0->m_pkthdr.csum_data = 6665 l2fhdr->l2_fhdr_tcp_udp_xsum; 6666 m0->m_pkthdr.csum_flags |= 6667 (CSUM_DATA_VALID 6668 | CSUM_PSEUDO_HDR); 6669 } 6670 } 6671 } 6672 6673 /* Attach the VLAN tag. */ 6674 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 6675 !(sc->rx_mode & BCE_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 6676 DBRUN(sc->vlan_tagged_frames_rcvd++); 6677 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 6678 DBRUN(sc->vlan_tagged_frames_stripped++); 6679 m0->m_pkthdr.ether_vtag = 6680 l2fhdr->l2_fhdr_vlan_tag; 6681 m0->m_flags |= M_VLANTAG; 6682 } else { 6683 /* 6684 * bce(4) controllers can't disable VLAN 6685 * tag stripping if management firmware 6686 * (ASF/IPMI/UMP) is running. So we always 6687 * strip VLAN tag and manually reconstruct 6688 * the VLAN frame by appending stripped 6689 * VLAN tag in driver if VLAN tag stripping 6690 * was disabled. 6691 * 6692 * TODO: LLC SNAP handling. 6693 */ 6694 bcopy(mtod(m0, uint8_t *), 6695 mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN, 6696 ETHER_ADDR_LEN * 2); 6697 m0->m_data -= ETHER_VLAN_ENCAP_LEN; 6698 vh = mtod(m0, struct ether_vlan_header *); 6699 vh->evl_encap_proto = htons(ETHERTYPE_VLAN); 6700 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag); 6701 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN; 6702 m0->m_len += ETHER_VLAN_ENCAP_LEN; 6703 } 6704 } 6705 6706 /* Increment received packet statistics. */ 6707 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 6708 6709 bce_rx_intr_next_rx: 6710 sw_rx_cons = NEXT_RX_BD(sw_rx_cons); 6711 6712 /* If we have a packet, pass it up the stack */ 6713 if (m0) { 6714 /* Make sure we don't lose our place when we release the lock. */ 6715 sc->rx_cons = sw_rx_cons; 6716 sc->pg_cons = sw_pg_cons; 6717 6718 BCE_UNLOCK(sc); 6719 (*ifp->if_input)(ifp, m0); 6720 BCE_LOCK(sc); 6721 6722 /* Recover our place. */ 6723 sw_rx_cons = sc->rx_cons; 6724 sw_pg_cons = sc->pg_cons; 6725 } 6726 6727 /* Refresh hw_cons to see if there's new work */ 6728 if (sw_rx_cons == hw_rx_cons) 6729 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6730 } 6731 6732 /* No new packets. Refill the page chain. */ 6733 if (bce_hdr_split == TRUE) { 6734 sc->pg_cons = sw_pg_cons; 6735 bce_fill_pg_chain(sc); 6736 } 6737 6738 /* No new packets. Refill the RX chain. */ 6739 sc->rx_cons = sw_rx_cons; 6740 bce_fill_rx_chain(sc); 6741 6742 /* Prepare the page chain pages to be accessed by the NIC. */ 6743 for (int i = 0; i < sc->rx_pages; i++) 6744 bus_dmamap_sync(sc->rx_bd_chain_tag, 6745 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6746 6747 if (bce_hdr_split == TRUE) { 6748 for (int i = 0; i < sc->pg_pages; i++) 6749 bus_dmamap_sync(sc->pg_bd_chain_tag, 6750 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6751 } 6752 6753 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, " 6754 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6755 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6756 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6757 } 6758 6759 /****************************************************************************/ 6760 /* Reads the transmit consumer value from the status block (skipping over */ 6761 /* chain page pointer if necessary). */ 6762 /* */ 6763 /* Returns: */ 6764 /* hw_cons */ 6765 /****************************************************************************/ 6766 static inline u16 6767 bce_get_hw_tx_cons(struct bce_softc *sc) 6768 { 6769 u16 hw_cons; 6770 6771 mb(); 6772 hw_cons = sc->status_block->status_tx_quick_consumer_index0; 6773 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6774 hw_cons++; 6775 6776 return hw_cons; 6777 } 6778 6779 /****************************************************************************/ 6780 /* Handles transmit completion interrupt events. */ 6781 /* */ 6782 /* Returns: */ 6783 /* Nothing. */ 6784 /****************************************************************************/ 6785 static void 6786 bce_tx_intr(struct bce_softc *sc) 6787 { 6788 struct ifnet *ifp = sc->bce_ifp; 6789 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 6790 6791 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6792 DBRUN(sc->interrupts_tx++); 6793 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, " 6794 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6795 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6796 6797 BCE_LOCK_ASSERT(sc); 6798 6799 /* Get the hardware's view of the TX consumer index. */ 6800 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6801 sw_tx_cons = sc->tx_cons; 6802 6803 /* Prevent speculative reads of the status block. */ 6804 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6805 BUS_SPACE_BARRIER_READ); 6806 6807 /* Cycle through any completed TX chain page entries. */ 6808 while (sw_tx_cons != hw_tx_cons) { 6809 #ifdef BCE_DEBUG 6810 struct tx_bd *txbd = NULL; 6811 #endif 6812 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 6813 6814 DBPRINT(sc, BCE_INFO_SEND, 6815 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 6816 "sw_tx_chain_cons = 0x%04X\n", 6817 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 6818 6819 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC), 6820 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 6821 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 6822 (int) MAX_TX_BD_ALLOC); 6823 bce_breakpoint(sc)); 6824 6825 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 6826 [TX_IDX(sw_tx_chain_cons)]); 6827 6828 DBRUNIF((txbd == NULL), 6829 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 6830 __FILE__, __LINE__, sw_tx_chain_cons); 6831 bce_breakpoint(sc)); 6832 6833 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 6834 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 6835 6836 /* 6837 * Free the associated mbuf. Remember 6838 * that only the last tx_bd of a packet 6839 * has an mbuf pointer and DMA map. 6840 */ 6841 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 6842 /* Validate that this is the last tx_bd. */ 6843 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 6844 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 6845 "txmbuf == NULL!\n", __FILE__, __LINE__); 6846 bce_breakpoint(sc)); 6847 6848 DBRUNMSG(BCE_INFO_SEND, 6849 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 6850 "from tx_bd[0x%04X]\n", __FUNCTION__, 6851 sw_tx_chain_cons)); 6852 6853 /* Unmap the mbuf. */ 6854 bus_dmamap_unload(sc->tx_mbuf_tag, 6855 sc->tx_mbuf_map[sw_tx_chain_cons]); 6856 6857 /* Free the mbuf. */ 6858 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 6859 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 6860 DBRUN(sc->debug_tx_mbuf_alloc--); 6861 6862 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 6863 } 6864 6865 sc->used_tx_bd--; 6866 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 6867 6868 /* Refresh hw_cons to see if there's new work. */ 6869 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6870 6871 /* Prevent speculative reads of the status block. */ 6872 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6873 BUS_SPACE_BARRIER_READ); 6874 } 6875 6876 /* Clear the TX timeout timer. */ 6877 sc->watchdog_timer = 0; 6878 6879 /* Clear the tx hardware queue full flag. */ 6880 if (sc->used_tx_bd < sc->max_tx_bd) { 6881 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 6882 DBPRINT(sc, BCE_INFO_SEND, 6883 "%s(): Open TX chain! %d/%d (used/total)\n", 6884 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 6885 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6886 } 6887 6888 sc->tx_cons = sw_tx_cons; 6889 6890 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, " 6891 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6892 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6893 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6894 } 6895 6896 /****************************************************************************/ 6897 /* Disables interrupt generation. */ 6898 /* */ 6899 /* Returns: */ 6900 /* Nothing. */ 6901 /****************************************************************************/ 6902 static void 6903 bce_disable_intr(struct bce_softc *sc) 6904 { 6905 DBENTER(BCE_VERBOSE_INTR); 6906 6907 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 6908 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 6909 6910 DBEXIT(BCE_VERBOSE_INTR); 6911 } 6912 6913 /****************************************************************************/ 6914 /* Enables interrupt generation. */ 6915 /* */ 6916 /* Returns: */ 6917 /* Nothing. */ 6918 /****************************************************************************/ 6919 static void 6920 bce_enable_intr(struct bce_softc *sc, int coal_now) 6921 { 6922 DBENTER(BCE_VERBOSE_INTR); 6923 6924 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6925 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 6926 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 6927 6928 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6929 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 6930 6931 /* Force an immediate interrupt (whether there is new data or not). */ 6932 if (coal_now) 6933 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW); 6934 6935 DBEXIT(BCE_VERBOSE_INTR); 6936 } 6937 6938 /****************************************************************************/ 6939 /* Handles controller initialization. */ 6940 /* */ 6941 /* Returns: */ 6942 /* Nothing. */ 6943 /****************************************************************************/ 6944 static void 6945 bce_init_locked(struct bce_softc *sc) 6946 { 6947 struct ifnet *ifp; 6948 u32 ether_mtu = 0; 6949 6950 DBENTER(BCE_VERBOSE_RESET); 6951 6952 BCE_LOCK_ASSERT(sc); 6953 6954 ifp = sc->bce_ifp; 6955 6956 /* Check if the driver is still running and bail out if it is. */ 6957 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6958 goto bce_init_locked_exit; 6959 6960 bce_stop(sc); 6961 6962 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 6963 BCE_PRINTF("%s(%d): Controller reset failed!\n", 6964 __FILE__, __LINE__); 6965 goto bce_init_locked_exit; 6966 } 6967 6968 if (bce_chipinit(sc)) { 6969 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 6970 __FILE__, __LINE__); 6971 goto bce_init_locked_exit; 6972 } 6973 6974 if (bce_blockinit(sc)) { 6975 BCE_PRINTF("%s(%d): Block initialization failed!\n", 6976 __FILE__, __LINE__); 6977 goto bce_init_locked_exit; 6978 } 6979 6980 /* Load our MAC address. */ 6981 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 6982 bce_set_mac_addr(sc); 6983 6984 if (bce_hdr_split == FALSE) 6985 bce_get_rx_buffer_sizes(sc, ifp->if_mtu); 6986 /* 6987 * Calculate and program the hardware Ethernet MTU 6988 * size. Be generous on the receive if we have room 6989 * and allowed by the user. 6990 */ 6991 if (bce_strict_rx_mtu == TRUE) 6992 ether_mtu = ifp->if_mtu; 6993 else { 6994 if (bce_hdr_split == TRUE) { 6995 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len + MCLBYTES) 6996 ether_mtu = sc->rx_bd_mbuf_data_len + 6997 MCLBYTES; 6998 else 6999 ether_mtu = ifp->if_mtu; 7000 } else { 7001 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len) 7002 ether_mtu = sc->rx_bd_mbuf_data_len; 7003 else 7004 ether_mtu = ifp->if_mtu; 7005 } 7006 } 7007 7008 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 7009 7010 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", 7011 __FUNCTION__, ether_mtu); 7012 7013 /* Program the mtu, enabling jumbo frame support if necessary. */ 7014 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)) 7015 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, 7016 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 7017 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 7018 else 7019 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 7020 7021 /* Program appropriate promiscuous/multicast filtering. */ 7022 bce_set_rx_mode(sc); 7023 7024 if (bce_hdr_split == TRUE) { 7025 /* Init page buffer descriptor chain. */ 7026 bce_init_pg_chain(sc); 7027 } 7028 7029 /* Init RX buffer descriptor chain. */ 7030 bce_init_rx_chain(sc); 7031 7032 /* Init TX buffer descriptor chain. */ 7033 bce_init_tx_chain(sc); 7034 7035 /* Enable host interrupts. */ 7036 bce_enable_intr(sc, 1); 7037 7038 bce_ifmedia_upd_locked(ifp); 7039 7040 /* Let the OS know the driver is up and running. */ 7041 ifp->if_drv_flags |= IFF_DRV_RUNNING; 7042 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 7043 7044 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 7045 7046 bce_init_locked_exit: 7047 DBEXIT(BCE_VERBOSE_RESET); 7048 } 7049 7050 /****************************************************************************/ 7051 /* Initialize the controller just enough so that any management firmware */ 7052 /* running on the device will continue to operate correctly. */ 7053 /* */ 7054 /* Returns: */ 7055 /* Nothing. */ 7056 /****************************************************************************/ 7057 static void 7058 bce_mgmt_init_locked(struct bce_softc *sc) 7059 { 7060 struct ifnet *ifp; 7061 7062 DBENTER(BCE_VERBOSE_RESET); 7063 7064 BCE_LOCK_ASSERT(sc); 7065 7066 /* Bail out if management firmware is not running. */ 7067 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 7068 DBPRINT(sc, BCE_VERBOSE_SPECIAL, 7069 "No management firmware running...\n"); 7070 goto bce_mgmt_init_locked_exit; 7071 } 7072 7073 ifp = sc->bce_ifp; 7074 7075 /* Enable all critical blocks in the MAC. */ 7076 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 7077 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 7078 DELAY(20); 7079 7080 bce_ifmedia_upd_locked(ifp); 7081 7082 bce_mgmt_init_locked_exit: 7083 DBEXIT(BCE_VERBOSE_RESET); 7084 } 7085 7086 /****************************************************************************/ 7087 /* Handles controller initialization when called from an unlocked routine. */ 7088 /* */ 7089 /* Returns: */ 7090 /* Nothing. */ 7091 /****************************************************************************/ 7092 static void 7093 bce_init(void *xsc) 7094 { 7095 struct bce_softc *sc = xsc; 7096 7097 DBENTER(BCE_VERBOSE_RESET); 7098 7099 BCE_LOCK(sc); 7100 bce_init_locked(sc); 7101 BCE_UNLOCK(sc); 7102 7103 DBEXIT(BCE_VERBOSE_RESET); 7104 } 7105 7106 /****************************************************************************/ 7107 /* Modifies an mbuf for TSO on the hardware. */ 7108 /* */ 7109 /* Returns: */ 7110 /* Pointer to a modified mbuf. */ 7111 /****************************************************************************/ 7112 static struct mbuf * 7113 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags) 7114 { 7115 struct mbuf *m; 7116 struct ether_header *eh; 7117 struct ip *ip; 7118 struct tcphdr *th; 7119 u16 etype; 7120 int hdr_len __unused, ip_len __unused, ip_hlen = 0, tcp_hlen = 0; 7121 7122 DBRUN(sc->tso_frames_requested++); 7123 7124 ip_len = 0; 7125 /* Controller may modify mbuf chains. */ 7126 if (M_WRITABLE(*m_head) == 0) { 7127 m = m_dup(*m_head, M_NOWAIT); 7128 m_freem(*m_head); 7129 if (m == NULL) { 7130 sc->mbuf_alloc_failed_count++; 7131 *m_head = NULL; 7132 return (NULL); 7133 } 7134 *m_head = m; 7135 } 7136 7137 /* 7138 * For TSO the controller needs two pieces of info, 7139 * the MSS and the IP+TCP options length. 7140 */ 7141 m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip)); 7142 if (m == NULL) { 7143 *m_head = NULL; 7144 return (NULL); 7145 } 7146 eh = mtod(m, struct ether_header *); 7147 etype = ntohs(eh->ether_type); 7148 7149 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 7150 switch (etype) { 7151 case ETHERTYPE_IP: 7152 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7153 /* TSO only supported for TCP protocol. */ 7154 if (ip->ip_p != IPPROTO_TCP) { 7155 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 7156 __FILE__, __LINE__); 7157 m_freem(*m_head); 7158 *m_head = NULL; 7159 return (NULL); 7160 } 7161 7162 /* Get IP header length in bytes (min 20) */ 7163 ip_hlen = ip->ip_hl << 2; 7164 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen + 7165 sizeof(struct tcphdr)); 7166 if (m == NULL) { 7167 *m_head = NULL; 7168 return (NULL); 7169 } 7170 7171 /* Get the TCP header length in bytes (min 20) */ 7172 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7173 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 7174 tcp_hlen = (th->th_off << 2); 7175 7176 /* Make sure all IP/TCP options live in the same buffer. */ 7177 m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen + 7178 tcp_hlen); 7179 if (m == NULL) { 7180 *m_head = NULL; 7181 return (NULL); 7182 } 7183 7184 /* Clear IP header length and checksum, will be calc'd by h/w. */ 7185 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7186 ip_len = ip->ip_len; 7187 ip->ip_len = 0; 7188 ip->ip_sum = 0; 7189 break; 7190 case ETHERTYPE_IPV6: 7191 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 7192 __FILE__, __LINE__); 7193 m_freem(*m_head); 7194 *m_head = NULL; 7195 return (NULL); 7196 /* NOT REACHED */ 7197 default: 7198 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 7199 __FILE__, __LINE__); 7200 m_freem(*m_head); 7201 *m_head = NULL; 7202 return (NULL); 7203 } 7204 7205 hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen; 7206 7207 DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, " 7208 "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 7209 __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen, 7210 tcp_hlen, ip_len); 7211 7212 /* Set the LSO flag in the TX BD */ 7213 *flags |= TX_BD_FLAGS_SW_LSO; 7214 7215 /* Set the length of IP + TCP options (in 32 bit words) */ 7216 *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) - 7217 sizeof(struct tcphdr)) >> 2) << 8); 7218 7219 DBRUN(sc->tso_frames_completed++); 7220 return (*m_head); 7221 } 7222 7223 /****************************************************************************/ 7224 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 7225 /* memory visible to the controller. */ 7226 /* */ 7227 /* Returns: */ 7228 /* 0 for success, positive value for failure. */ 7229 /* Modified: */ 7230 /* m_head: May be set to NULL if MBUF is excessively fragmented. */ 7231 /****************************************************************************/ 7232 static int 7233 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 7234 { 7235 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 7236 bus_dmamap_t map; 7237 struct tx_bd *txbd = NULL; 7238 struct mbuf *m0; 7239 u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0; 7240 u32 prod_bseq; 7241 7242 #ifdef BCE_DEBUG 7243 u16 debug_prod; 7244 #endif 7245 7246 int i, error, nsegs, rc = 0; 7247 7248 DBENTER(BCE_VERBOSE_SEND); 7249 7250 /* Make sure we have room in the TX chain. */ 7251 if (sc->used_tx_bd >= sc->max_tx_bd) 7252 goto bce_tx_encap_exit; 7253 7254 /* Transfer any checksum offload flags to the bd. */ 7255 m0 = *m_head; 7256 if (m0->m_pkthdr.csum_flags) { 7257 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 7258 m0 = bce_tso_setup(sc, m_head, &flags); 7259 if (m0 == NULL) { 7260 DBRUN(sc->tso_frames_failed++); 7261 goto bce_tx_encap_exit; 7262 } 7263 mss = htole16(m0->m_pkthdr.tso_segsz); 7264 } else { 7265 if (m0->m_pkthdr.csum_flags & CSUM_IP) 7266 flags |= TX_BD_FLAGS_IP_CKSUM; 7267 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 7268 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 7269 } 7270 } 7271 7272 /* Transfer any VLAN tags to the bd. */ 7273 if (m0->m_flags & M_VLANTAG) { 7274 flags |= TX_BD_FLAGS_VLAN_TAG; 7275 vlan_tag = m0->m_pkthdr.ether_vtag; 7276 } 7277 7278 /* Map the mbuf into DMAable memory. */ 7279 prod = sc->tx_prod; 7280 chain_prod = TX_CHAIN_IDX(prod); 7281 map = sc->tx_mbuf_map[chain_prod]; 7282 7283 /* Map the mbuf into our DMA address space. */ 7284 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 7285 segs, &nsegs, BUS_DMA_NOWAIT); 7286 7287 /* Check if the DMA mapping was successful */ 7288 if (error == EFBIG) { 7289 sc->mbuf_frag_count++; 7290 7291 /* Try to defrag the mbuf. */ 7292 m0 = m_collapse(*m_head, M_NOWAIT, BCE_MAX_SEGMENTS); 7293 if (m0 == NULL) { 7294 /* Defrag was unsuccessful */ 7295 m_freem(*m_head); 7296 *m_head = NULL; 7297 sc->mbuf_alloc_failed_count++; 7298 rc = ENOBUFS; 7299 goto bce_tx_encap_exit; 7300 } 7301 7302 /* Defrag was successful, try mapping again */ 7303 *m_head = m0; 7304 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, 7305 map, m0, segs, &nsegs, BUS_DMA_NOWAIT); 7306 7307 /* Still getting an error after a defrag. */ 7308 if (error == ENOMEM) { 7309 /* Insufficient DMA buffers available. */ 7310 sc->dma_map_addr_tx_failed_count++; 7311 rc = error; 7312 goto bce_tx_encap_exit; 7313 } else if (error != 0) { 7314 /* Release it and return an error. */ 7315 BCE_PRINTF("%s(%d): Unknown error mapping mbuf into " 7316 "TX chain!\n", __FILE__, __LINE__); 7317 m_freem(m0); 7318 *m_head = NULL; 7319 sc->dma_map_addr_tx_failed_count++; 7320 rc = ENOBUFS; 7321 goto bce_tx_encap_exit; 7322 } 7323 } else if (error == ENOMEM) { 7324 /* Insufficient DMA buffers available. */ 7325 sc->dma_map_addr_tx_failed_count++; 7326 rc = error; 7327 goto bce_tx_encap_exit; 7328 } else if (error != 0) { 7329 m_freem(m0); 7330 *m_head = NULL; 7331 sc->dma_map_addr_tx_failed_count++; 7332 rc = error; 7333 goto bce_tx_encap_exit; 7334 } 7335 7336 /* Make sure there's room in the chain */ 7337 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 7338 bus_dmamap_unload(sc->tx_mbuf_tag, map); 7339 rc = ENOBUFS; 7340 goto bce_tx_encap_exit; 7341 } 7342 7343 /* prod points to an empty tx_bd at this point. */ 7344 prod_bseq = sc->tx_prod_bseq; 7345 7346 #ifdef BCE_DEBUG 7347 debug_prod = chain_prod; 7348 #endif 7349 7350 DBPRINT(sc, BCE_INFO_SEND, 7351 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, " 7352 "prod_bseq = 0x%08X\n", 7353 __FUNCTION__, prod, chain_prod, prod_bseq); 7354 7355 /* 7356 * Cycle through each mbuf segment that makes up 7357 * the outgoing frame, gathering the mapping info 7358 * for that segment and creating a tx_bd for 7359 * the mbuf. 7360 */ 7361 for (i = 0; i < nsegs ; i++) { 7362 chain_prod = TX_CHAIN_IDX(prod); 7363 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)] 7364 [TX_IDX(chain_prod)]; 7365 7366 txbd->tx_bd_haddr_lo = 7367 htole32(BCE_ADDR_LO(segs[i].ds_addr)); 7368 txbd->tx_bd_haddr_hi = 7369 htole32(BCE_ADDR_HI(segs[i].ds_addr)); 7370 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | 7371 htole16(segs[i].ds_len); 7372 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 7373 txbd->tx_bd_flags = htole16(flags); 7374 prod_bseq += segs[i].ds_len; 7375 if (i == 0) 7376 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 7377 prod = NEXT_TX_BD(prod); 7378 } 7379 7380 /* Set the END flag on the last TX buffer descriptor. */ 7381 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 7382 7383 DBRUNMSG(BCE_EXTREME_SEND, 7384 bce_dump_tx_chain(sc, debug_prod, nsegs)); 7385 7386 /* 7387 * Ensure that the mbuf pointer for this transmission 7388 * is placed at the array index of the last 7389 * descriptor in this chain. This is done 7390 * because a single map is used for all 7391 * segments of the mbuf and we don't want to 7392 * unload the map before all of the segments 7393 * have been freed. 7394 */ 7395 sc->tx_mbuf_ptr[chain_prod] = m0; 7396 sc->used_tx_bd += nsegs; 7397 7398 /* Update some debug statistic counters */ 7399 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 7400 sc->tx_hi_watermark = sc->used_tx_bd); 7401 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 7402 DBRUNIF(sc->debug_tx_mbuf_alloc++); 7403 7404 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1)); 7405 7406 /* prod points to the next free tx_bd at this point. */ 7407 sc->tx_prod = prod; 7408 sc->tx_prod_bseq = prod_bseq; 7409 7410 /* Tell the chip about the waiting TX frames. */ 7411 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + 7412 BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); 7413 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + 7414 BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); 7415 7416 bce_tx_encap_exit: 7417 DBEXIT(BCE_VERBOSE_SEND); 7418 return(rc); 7419 } 7420 7421 /****************************************************************************/ 7422 /* Main transmit routine when called from another routine with a lock. */ 7423 /* */ 7424 /* Returns: */ 7425 /* Nothing. */ 7426 /****************************************************************************/ 7427 static void 7428 bce_start_locked(struct ifnet *ifp) 7429 { 7430 struct bce_softc *sc = ifp->if_softc; 7431 struct mbuf *m_head = NULL; 7432 int count = 0; 7433 u16 tx_prod, tx_chain_prod __unused; 7434 7435 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7436 7437 BCE_LOCK_ASSERT(sc); 7438 7439 /* prod points to the next free tx_bd. */ 7440 tx_prod = sc->tx_prod; 7441 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 7442 7443 DBPRINT(sc, BCE_INFO_SEND, 7444 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 7445 "tx_prod_bseq = 0x%08X\n", 7446 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 7447 7448 /* If there's no link or the transmit queue is empty then just exit. */ 7449 if (sc->bce_link_up == FALSE) { 7450 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n", 7451 __FUNCTION__); 7452 goto bce_start_locked_exit; 7453 } 7454 7455 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 7456 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n", 7457 __FUNCTION__); 7458 goto bce_start_locked_exit; 7459 } 7460 7461 /* 7462 * Keep adding entries while there is space in the ring. 7463 */ 7464 while (sc->used_tx_bd < sc->max_tx_bd) { 7465 /* Check for any frames to send. */ 7466 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 7467 7468 /* Stop when the transmit queue is empty. */ 7469 if (m_head == NULL) 7470 break; 7471 7472 /* 7473 * Pack the data into the transmit ring. If we 7474 * don't have room, place the mbuf back at the 7475 * head of the queue and set the OACTIVE flag 7476 * to wait for the NIC to drain the chain. 7477 */ 7478 if (bce_tx_encap(sc, &m_head)) { 7479 if (m_head != NULL) 7480 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 7481 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 7482 DBPRINT(sc, BCE_INFO_SEND, 7483 "TX chain is closed for business! Total " 7484 "tx_bd used = %d\n", sc->used_tx_bd); 7485 break; 7486 } 7487 7488 count++; 7489 7490 /* Send a copy of the frame to any BPF listeners. */ 7491 ETHER_BPF_MTAP(ifp, m_head); 7492 } 7493 7494 /* Exit if no packets were dequeued. */ 7495 if (count == 0) { 7496 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were " 7497 "dequeued\n", __FUNCTION__); 7498 goto bce_start_locked_exit; 7499 } 7500 7501 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into " 7502 "send queue.\n", __FUNCTION__, count); 7503 7504 /* Set the tx timeout. */ 7505 sc->watchdog_timer = BCE_TX_TIMEOUT; 7506 7507 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID)); 7508 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc)); 7509 7510 bce_start_locked_exit: 7511 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7512 } 7513 7514 /****************************************************************************/ 7515 /* Main transmit routine when called from another routine without a lock. */ 7516 /* */ 7517 /* Returns: */ 7518 /* Nothing. */ 7519 /****************************************************************************/ 7520 static void 7521 bce_start(struct ifnet *ifp) 7522 { 7523 struct bce_softc *sc = ifp->if_softc; 7524 7525 DBENTER(BCE_VERBOSE_SEND); 7526 7527 BCE_LOCK(sc); 7528 bce_start_locked(ifp); 7529 BCE_UNLOCK(sc); 7530 7531 DBEXIT(BCE_VERBOSE_SEND); 7532 } 7533 7534 /****************************************************************************/ 7535 /* Handles any IOCTL calls from the operating system. */ 7536 /* */ 7537 /* Returns: */ 7538 /* 0 for success, positive value for failure. */ 7539 /****************************************************************************/ 7540 static int 7541 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 7542 { 7543 struct bce_softc *sc = ifp->if_softc; 7544 struct ifreq *ifr = (struct ifreq *) data; 7545 struct mii_data *mii; 7546 int mask, error = 0; 7547 7548 DBENTER(BCE_VERBOSE_MISC); 7549 7550 switch(command) { 7551 /* Set the interface MTU. */ 7552 case SIOCSIFMTU: 7553 /* Check that the MTU setting is supported. */ 7554 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 7555 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 7556 error = EINVAL; 7557 break; 7558 } 7559 7560 DBPRINT(sc, BCE_INFO_MISC, 7561 "SIOCSIFMTU: Changing MTU from %d to %d\n", 7562 (int) ifp->if_mtu, (int) ifr->ifr_mtu); 7563 7564 BCE_LOCK(sc); 7565 ifp->if_mtu = ifr->ifr_mtu; 7566 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7567 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7568 bce_init_locked(sc); 7569 } 7570 BCE_UNLOCK(sc); 7571 break; 7572 7573 /* Set interface flags. */ 7574 case SIOCSIFFLAGS: 7575 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 7576 7577 BCE_LOCK(sc); 7578 7579 /* Check if the interface is up. */ 7580 if (ifp->if_flags & IFF_UP) { 7581 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7582 /* Change promiscuous/multicast flags as necessary. */ 7583 bce_set_rx_mode(sc); 7584 } else { 7585 /* Start the HW */ 7586 bce_init_locked(sc); 7587 } 7588 } else { 7589 /* The interface is down, check if driver is running. */ 7590 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7591 bce_stop(sc); 7592 7593 /* If MFW is running, restart the controller a bit. */ 7594 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 7595 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 7596 bce_chipinit(sc); 7597 bce_mgmt_init_locked(sc); 7598 } 7599 } 7600 } 7601 7602 BCE_UNLOCK(sc); 7603 break; 7604 7605 /* Add/Delete multicast address */ 7606 case SIOCADDMULTI: 7607 case SIOCDELMULTI: 7608 DBPRINT(sc, BCE_VERBOSE_MISC, 7609 "Received SIOCADDMULTI/SIOCDELMULTI\n"); 7610 7611 BCE_LOCK(sc); 7612 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7613 bce_set_rx_mode(sc); 7614 BCE_UNLOCK(sc); 7615 7616 break; 7617 7618 /* Set/Get Interface media */ 7619 case SIOCSIFMEDIA: 7620 case SIOCGIFMEDIA: 7621 DBPRINT(sc, BCE_VERBOSE_MISC, 7622 "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 7623 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 7624 error = ifmedia_ioctl(ifp, ifr, &sc->bce_ifmedia, 7625 command); 7626 else { 7627 mii = device_get_softc(sc->bce_miibus); 7628 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 7629 command); 7630 } 7631 break; 7632 7633 /* Set interface capability */ 7634 case SIOCSIFCAP: 7635 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 7636 DBPRINT(sc, BCE_INFO_MISC, 7637 "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 7638 7639 /* Toggle the TX checksum capabilities enable flag. */ 7640 if (mask & IFCAP_TXCSUM && 7641 ifp->if_capabilities & IFCAP_TXCSUM) { 7642 ifp->if_capenable ^= IFCAP_TXCSUM; 7643 if (IFCAP_TXCSUM & ifp->if_capenable) 7644 ifp->if_hwassist |= BCE_IF_HWASSIST; 7645 else 7646 ifp->if_hwassist &= ~BCE_IF_HWASSIST; 7647 } 7648 7649 /* Toggle the RX checksum capabilities enable flag. */ 7650 if (mask & IFCAP_RXCSUM && 7651 ifp->if_capabilities & IFCAP_RXCSUM) 7652 ifp->if_capenable ^= IFCAP_RXCSUM; 7653 7654 /* Toggle the TSO capabilities enable flag. */ 7655 if (bce_tso_enable && (mask & IFCAP_TSO4) && 7656 ifp->if_capabilities & IFCAP_TSO4) { 7657 ifp->if_capenable ^= IFCAP_TSO4; 7658 if (IFCAP_TSO4 & ifp->if_capenable) 7659 ifp->if_hwassist |= CSUM_TSO; 7660 else 7661 ifp->if_hwassist &= ~CSUM_TSO; 7662 } 7663 7664 if (mask & IFCAP_VLAN_HWCSUM && 7665 ifp->if_capabilities & IFCAP_VLAN_HWCSUM) 7666 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 7667 7668 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 7669 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 7670 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 7671 /* 7672 * Don't actually disable VLAN tag stripping as 7673 * management firmware (ASF/IPMI/UMP) requires the 7674 * feature. If VLAN tag stripping is disabled driver 7675 * will manually reconstruct the VLAN frame by 7676 * appending stripped VLAN tag. 7677 */ 7678 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 7679 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { 7680 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 7681 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 7682 == 0) 7683 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 7684 } 7685 VLAN_CAPABILITIES(ifp); 7686 break; 7687 default: 7688 /* We don't know how to handle the IOCTL, pass it on. */ 7689 error = ether_ioctl(ifp, command, data); 7690 break; 7691 } 7692 7693 DBEXIT(BCE_VERBOSE_MISC); 7694 return(error); 7695 } 7696 7697 /****************************************************************************/ 7698 /* Transmit timeout handler. */ 7699 /* */ 7700 /* Returns: */ 7701 /* Nothing. */ 7702 /****************************************************************************/ 7703 static void 7704 bce_watchdog(struct bce_softc *sc) 7705 { 7706 uint32_t status; 7707 7708 DBENTER(BCE_EXTREME_SEND); 7709 7710 BCE_LOCK_ASSERT(sc); 7711 7712 status = 0; 7713 /* If the watchdog timer hasn't expired then just exit. */ 7714 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 7715 goto bce_watchdog_exit; 7716 7717 status = REG_RD(sc, BCE_EMAC_RX_STATUS); 7718 /* If pause frames are active then don't reset the hardware. */ 7719 if ((sc->bce_flags & BCE_USING_RX_FLOW_CONTROL) != 0) { 7720 if ((status & BCE_EMAC_RX_STATUS_FFED) != 0) { 7721 /* 7722 * If link partner has us in XOFF state then wait for 7723 * the condition to clear. 7724 */ 7725 sc->watchdog_timer = BCE_TX_TIMEOUT; 7726 goto bce_watchdog_exit; 7727 } else if ((status & BCE_EMAC_RX_STATUS_FF_RECEIVED) != 0 && 7728 (status & BCE_EMAC_RX_STATUS_N_RECEIVED) != 0) { 7729 /* 7730 * If we're not currently XOFF'ed but have recently 7731 * been XOFF'd/XON'd then assume that's delaying TX 7732 * this time around. 7733 */ 7734 sc->watchdog_timer = BCE_TX_TIMEOUT; 7735 goto bce_watchdog_exit; 7736 } 7737 /* 7738 * Any other condition is unexpected and the controller 7739 * should be reset. 7740 */ 7741 } 7742 7743 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 7744 __FILE__, __LINE__); 7745 7746 DBRUNMSG(BCE_INFO, 7747 bce_dump_driver_state(sc); 7748 bce_dump_status_block(sc); 7749 bce_dump_stats_block(sc); 7750 bce_dump_ftqs(sc); 7751 bce_dump_txp_state(sc, 0); 7752 bce_dump_rxp_state(sc, 0); 7753 bce_dump_tpat_state(sc, 0); 7754 bce_dump_cp_state(sc, 0); 7755 bce_dump_com_state(sc, 0)); 7756 7757 DBRUN(bce_breakpoint(sc)); 7758 7759 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7760 7761 bce_init_locked(sc); 7762 sc->watchdog_timeouts++; 7763 7764 bce_watchdog_exit: 7765 REG_WR(sc, BCE_EMAC_RX_STATUS, status); 7766 DBEXIT(BCE_EXTREME_SEND); 7767 } 7768 7769 /* 7770 * Interrupt handler. 7771 */ 7772 /****************************************************************************/ 7773 /* Main interrupt entry point. Verifies that the controller generated the */ 7774 /* interrupt and then calls a separate routine for handle the various */ 7775 /* interrupt causes (PHY, TX, RX). */ 7776 /* */ 7777 /* Returns: */ 7778 /* Nothing. */ 7779 /****************************************************************************/ 7780 static void 7781 bce_intr(void *xsc) 7782 { 7783 struct bce_softc *sc; 7784 struct ifnet *ifp; 7785 u32 status_attn_bits; 7786 u16 hw_rx_cons, hw_tx_cons; 7787 7788 sc = xsc; 7789 ifp = sc->bce_ifp; 7790 7791 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7792 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 7793 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc)); 7794 7795 BCE_LOCK(sc); 7796 7797 DBRUN(sc->interrupts_generated++); 7798 7799 /* Synchnorize before we read from interface's status block */ 7800 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD); 7801 7802 /* 7803 * If the hardware status block index matches the last value read 7804 * by the driver and we haven't asserted our interrupt then there's 7805 * nothing to do. This may only happen in case of INTx due to the 7806 * interrupt arriving at the CPU before the status block is updated. 7807 */ 7808 if ((sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) == 0 && 7809 sc->status_block->status_idx == sc->last_status_idx && 7810 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & 7811 BCE_PCICFG_MISC_STATUS_INTA_VALUE)) { 7812 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n", 7813 __FUNCTION__); 7814 goto bce_intr_exit; 7815 } 7816 7817 /* Ack the interrupt and stop others from occurring. */ 7818 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7819 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 7820 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7821 7822 /* Check if the hardware has finished any work. */ 7823 hw_rx_cons = bce_get_hw_rx_cons(sc); 7824 hw_tx_cons = bce_get_hw_tx_cons(sc); 7825 7826 /* Keep processing data as long as there is work to do. */ 7827 for (;;) { 7828 status_attn_bits = sc->status_block->status_attn_bits; 7829 7830 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control), 7831 BCE_PRINTF("Simulating unexpected status attention " 7832 "bit set."); 7833 sc->unexpected_attention_sim_count++; 7834 status_attn_bits = status_attn_bits | 7835 STATUS_ATTN_BITS_PARITY_ERROR); 7836 7837 /* Was it a link change interrupt? */ 7838 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 7839 (sc->status_block->status_attn_bits_ack & 7840 STATUS_ATTN_BITS_LINK_STATE)) { 7841 bce_phy_intr(sc); 7842 7843 /* Clear transient updates during link state change. */ 7844 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | 7845 BCE_HC_COMMAND_COAL_NOW_WO_INT); 7846 REG_RD(sc, BCE_HC_COMMAND); 7847 } 7848 7849 /* If any other attention is asserted, the chip is toast. */ 7850 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 7851 (sc->status_block->status_attn_bits_ack & 7852 ~STATUS_ATTN_BITS_LINK_STATE))) { 7853 sc->unexpected_attention_count++; 7854 7855 BCE_PRINTF("%s(%d): Fatal attention detected: " 7856 "0x%08X\n", __FILE__, __LINE__, 7857 sc->status_block->status_attn_bits); 7858 7859 DBRUNMSG(BCE_FATAL, 7860 if (unexpected_attention_sim_control == 0) 7861 bce_breakpoint(sc)); 7862 7863 bce_init_locked(sc); 7864 goto bce_intr_exit; 7865 } 7866 7867 /* Check for any completed RX frames. */ 7868 if (hw_rx_cons != sc->hw_rx_cons) 7869 bce_rx_intr(sc); 7870 7871 /* Check for any completed TX frames. */ 7872 if (hw_tx_cons != sc->hw_tx_cons) 7873 bce_tx_intr(sc); 7874 7875 /* Save status block index value for the next interrupt. */ 7876 sc->last_status_idx = sc->status_block->status_idx; 7877 7878 /* 7879 * Prevent speculative reads from getting 7880 * ahead of the status block. 7881 */ 7882 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 7883 BUS_SPACE_BARRIER_READ); 7884 7885 /* 7886 * If there's no work left then exit the 7887 * interrupt service routine. 7888 */ 7889 hw_rx_cons = bce_get_hw_rx_cons(sc); 7890 hw_tx_cons = bce_get_hw_tx_cons(sc); 7891 7892 if ((hw_rx_cons == sc->hw_rx_cons) && 7893 (hw_tx_cons == sc->hw_tx_cons)) 7894 break; 7895 } 7896 7897 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREREAD); 7898 7899 /* Re-enable interrupts. */ 7900 bce_enable_intr(sc, 0); 7901 7902 /* Handle any frames that arrived while handling the interrupt. */ 7903 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 7904 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 7905 bce_start_locked(ifp); 7906 7907 bce_intr_exit: 7908 BCE_UNLOCK(sc); 7909 7910 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7911 } 7912 7913 /****************************************************************************/ 7914 /* Programs the various packet receive modes (broadcast and multicast). */ 7915 /* */ 7916 /* Returns: */ 7917 /* Nothing. */ 7918 /****************************************************************************/ 7919 static u_int 7920 bce_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 7921 { 7922 u32 *hashes = arg; 7923 int h; 7924 7925 h = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0xFF; 7926 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 7927 7928 return (1); 7929 } 7930 7931 static void 7932 bce_set_rx_mode(struct bce_softc *sc) 7933 { 7934 struct ifnet *ifp; 7935 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 7936 u32 rx_mode, sort_mode; 7937 int i; 7938 7939 DBENTER(BCE_VERBOSE_MISC); 7940 7941 BCE_LOCK_ASSERT(sc); 7942 7943 ifp = sc->bce_ifp; 7944 7945 /* Initialize receive mode default settings. */ 7946 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 7947 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 7948 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 7949 7950 /* 7951 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 7952 * be enbled. 7953 */ 7954 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 7955 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 7956 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 7957 7958 /* 7959 * Check for promiscuous, all multicast, or selected 7960 * multicast address filtering. 7961 */ 7962 if (ifp->if_flags & IFF_PROMISC) { 7963 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 7964 7965 /* Enable promiscuous mode. */ 7966 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 7967 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 7968 } else if (ifp->if_flags & IFF_ALLMULTI) { 7969 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 7970 7971 /* Enable all multicast addresses. */ 7972 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 7973 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 7974 0xffffffff); 7975 } 7976 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 7977 } else { 7978 /* Accept one or more multicast(s). */ 7979 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 7980 if_foreach_llmaddr(ifp, bce_hash_maddr, hashes); 7981 7982 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 7983 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 7984 7985 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 7986 } 7987 7988 /* Only make changes if the recive mode has actually changed. */ 7989 if (rx_mode != sc->rx_mode) { 7990 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: " 7991 "0x%08X\n", rx_mode); 7992 7993 sc->rx_mode = rx_mode; 7994 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 7995 } 7996 7997 /* Disable and clear the existing sort before enabling a new sort. */ 7998 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 7999 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 8000 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 8001 8002 DBEXIT(BCE_VERBOSE_MISC); 8003 } 8004 8005 /****************************************************************************/ 8006 /* Called periodically to updates statistics from the controllers */ 8007 /* statistics block. */ 8008 /* */ 8009 /* Returns: */ 8010 /* Nothing. */ 8011 /****************************************************************************/ 8012 static void 8013 bce_stats_update(struct bce_softc *sc) 8014 { 8015 struct statistics_block *stats; 8016 8017 DBENTER(BCE_EXTREME_MISC); 8018 8019 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD); 8020 8021 stats = (struct statistics_block *) sc->stats_block; 8022 8023 /* 8024 * Update the sysctl statistics from the 8025 * hardware statistics. 8026 */ 8027 sc->stat_IfHCInOctets = 8028 ((u64) stats->stat_IfHCInOctets_hi << 32) + 8029 (u64) stats->stat_IfHCInOctets_lo; 8030 8031 sc->stat_IfHCInBadOctets = 8032 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 8033 (u64) stats->stat_IfHCInBadOctets_lo; 8034 8035 sc->stat_IfHCOutOctets = 8036 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 8037 (u64) stats->stat_IfHCOutOctets_lo; 8038 8039 sc->stat_IfHCOutBadOctets = 8040 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 8041 (u64) stats->stat_IfHCOutBadOctets_lo; 8042 8043 sc->stat_IfHCInUcastPkts = 8044 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 8045 (u64) stats->stat_IfHCInUcastPkts_lo; 8046 8047 sc->stat_IfHCInMulticastPkts = 8048 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 8049 (u64) stats->stat_IfHCInMulticastPkts_lo; 8050 8051 sc->stat_IfHCInBroadcastPkts = 8052 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 8053 (u64) stats->stat_IfHCInBroadcastPkts_lo; 8054 8055 sc->stat_IfHCOutUcastPkts = 8056 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 8057 (u64) stats->stat_IfHCOutUcastPkts_lo; 8058 8059 sc->stat_IfHCOutMulticastPkts = 8060 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 8061 (u64) stats->stat_IfHCOutMulticastPkts_lo; 8062 8063 sc->stat_IfHCOutBroadcastPkts = 8064 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 8065 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 8066 8067 /* ToDo: Preserve counters beyond 32 bits? */ 8068 /* ToDo: Read the statistics from auto-clear regs? */ 8069 8070 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 8071 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 8072 8073 sc->stat_Dot3StatsCarrierSenseErrors = 8074 stats->stat_Dot3StatsCarrierSenseErrors; 8075 8076 sc->stat_Dot3StatsFCSErrors = 8077 stats->stat_Dot3StatsFCSErrors; 8078 8079 sc->stat_Dot3StatsAlignmentErrors = 8080 stats->stat_Dot3StatsAlignmentErrors; 8081 8082 sc->stat_Dot3StatsSingleCollisionFrames = 8083 stats->stat_Dot3StatsSingleCollisionFrames; 8084 8085 sc->stat_Dot3StatsMultipleCollisionFrames = 8086 stats->stat_Dot3StatsMultipleCollisionFrames; 8087 8088 sc->stat_Dot3StatsDeferredTransmissions = 8089 stats->stat_Dot3StatsDeferredTransmissions; 8090 8091 sc->stat_Dot3StatsExcessiveCollisions = 8092 stats->stat_Dot3StatsExcessiveCollisions; 8093 8094 sc->stat_Dot3StatsLateCollisions = 8095 stats->stat_Dot3StatsLateCollisions; 8096 8097 sc->stat_EtherStatsCollisions = 8098 stats->stat_EtherStatsCollisions; 8099 8100 sc->stat_EtherStatsFragments = 8101 stats->stat_EtherStatsFragments; 8102 8103 sc->stat_EtherStatsJabbers = 8104 stats->stat_EtherStatsJabbers; 8105 8106 sc->stat_EtherStatsUndersizePkts = 8107 stats->stat_EtherStatsUndersizePkts; 8108 8109 sc->stat_EtherStatsOversizePkts = 8110 stats->stat_EtherStatsOversizePkts; 8111 8112 sc->stat_EtherStatsPktsRx64Octets = 8113 stats->stat_EtherStatsPktsRx64Octets; 8114 8115 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 8116 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 8117 8118 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 8119 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 8120 8121 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 8122 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 8123 8124 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 8125 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 8126 8127 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 8128 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 8129 8130 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 8131 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 8132 8133 sc->stat_EtherStatsPktsTx64Octets = 8134 stats->stat_EtherStatsPktsTx64Octets; 8135 8136 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 8137 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 8138 8139 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 8140 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 8141 8142 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 8143 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 8144 8145 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 8146 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 8147 8148 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 8149 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 8150 8151 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 8152 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 8153 8154 sc->stat_XonPauseFramesReceived = 8155 stats->stat_XonPauseFramesReceived; 8156 8157 sc->stat_XoffPauseFramesReceived = 8158 stats->stat_XoffPauseFramesReceived; 8159 8160 sc->stat_OutXonSent = 8161 stats->stat_OutXonSent; 8162 8163 sc->stat_OutXoffSent = 8164 stats->stat_OutXoffSent; 8165 8166 sc->stat_FlowControlDone = 8167 stats->stat_FlowControlDone; 8168 8169 sc->stat_MacControlFramesReceived = 8170 stats->stat_MacControlFramesReceived; 8171 8172 sc->stat_XoffStateEntered = 8173 stats->stat_XoffStateEntered; 8174 8175 sc->stat_IfInFramesL2FilterDiscards = 8176 stats->stat_IfInFramesL2FilterDiscards; 8177 8178 sc->stat_IfInRuleCheckerDiscards = 8179 stats->stat_IfInRuleCheckerDiscards; 8180 8181 sc->stat_IfInFTQDiscards = 8182 stats->stat_IfInFTQDiscards; 8183 8184 sc->stat_IfInMBUFDiscards = 8185 stats->stat_IfInMBUFDiscards; 8186 8187 sc->stat_IfInRuleCheckerP4Hit = 8188 stats->stat_IfInRuleCheckerP4Hit; 8189 8190 sc->stat_CatchupInRuleCheckerDiscards = 8191 stats->stat_CatchupInRuleCheckerDiscards; 8192 8193 sc->stat_CatchupInFTQDiscards = 8194 stats->stat_CatchupInFTQDiscards; 8195 8196 sc->stat_CatchupInMBUFDiscards = 8197 stats->stat_CatchupInMBUFDiscards; 8198 8199 sc->stat_CatchupInRuleCheckerP4Hit = 8200 stats->stat_CatchupInRuleCheckerP4Hit; 8201 8202 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 8203 8204 /* ToDo: Add additional statistics? */ 8205 8206 DBEXIT(BCE_EXTREME_MISC); 8207 } 8208 8209 static uint64_t 8210 bce_get_counter(struct ifnet *ifp, ift_counter cnt) 8211 { 8212 struct bce_softc *sc; 8213 uint64_t rv; 8214 8215 sc = if_getsoftc(ifp); 8216 8217 switch (cnt) { 8218 case IFCOUNTER_COLLISIONS: 8219 return (sc->stat_EtherStatsCollisions); 8220 case IFCOUNTER_IERRORS: 8221 return (sc->stat_EtherStatsUndersizePkts + 8222 sc->stat_EtherStatsOversizePkts + 8223 sc->stat_IfInMBUFDiscards + 8224 sc->stat_Dot3StatsAlignmentErrors + 8225 sc->stat_Dot3StatsFCSErrors + 8226 sc->stat_IfInRuleCheckerDiscards + 8227 sc->stat_IfInFTQDiscards + 8228 sc->l2fhdr_error_count + 8229 sc->com_no_buffers); 8230 case IFCOUNTER_OERRORS: 8231 rv = sc->stat_Dot3StatsExcessiveCollisions + 8232 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 8233 sc->stat_Dot3StatsLateCollisions + 8234 sc->watchdog_timeouts; 8235 /* 8236 * Certain controllers don't report 8237 * carrier sense errors correctly. 8238 * See errata E11_5708CA0_1165. 8239 */ 8240 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 8241 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 8242 rv += sc->stat_Dot3StatsCarrierSenseErrors; 8243 return (rv); 8244 default: 8245 return (if_get_counter_default(ifp, cnt)); 8246 } 8247 } 8248 8249 /****************************************************************************/ 8250 /* Periodic function to notify the bootcode that the driver is still */ 8251 /* present. */ 8252 /* */ 8253 /* Returns: */ 8254 /* Nothing. */ 8255 /****************************************************************************/ 8256 static void 8257 bce_pulse(void *xsc) 8258 { 8259 struct bce_softc *sc = xsc; 8260 u32 msg; 8261 8262 DBENTER(BCE_EXTREME_MISC); 8263 8264 BCE_LOCK_ASSERT(sc); 8265 8266 /* Tell the firmware that the driver is still running. */ 8267 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 8268 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg); 8269 8270 /* Update the bootcode condition. */ 8271 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 8272 8273 /* Report whether the bootcode still knows the driver is running. */ 8274 if (bce_verbose || bootverbose) { 8275 if (sc->bce_drv_cardiac_arrest == FALSE) { 8276 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) { 8277 sc->bce_drv_cardiac_arrest = TRUE; 8278 BCE_PRINTF("%s(): Warning: bootcode " 8279 "thinks driver is absent! " 8280 "(bc_state = 0x%08X)\n", 8281 __FUNCTION__, sc->bc_state); 8282 } 8283 } else { 8284 /* 8285 * Not supported by all bootcode versions. 8286 * (v5.0.11+ and v5.2.1+) Older bootcode 8287 * will require the driver to reset the 8288 * controller to clear this condition. 8289 */ 8290 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) { 8291 sc->bce_drv_cardiac_arrest = FALSE; 8292 BCE_PRINTF("%s(): Bootcode found the " 8293 "driver pulse! (bc_state = 0x%08X)\n", 8294 __FUNCTION__, sc->bc_state); 8295 } 8296 } 8297 } 8298 8299 /* Schedule the next pulse. */ 8300 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 8301 8302 DBEXIT(BCE_EXTREME_MISC); 8303 } 8304 8305 /****************************************************************************/ 8306 /* Periodic function to perform maintenance tasks. */ 8307 /* */ 8308 /* Returns: */ 8309 /* Nothing. */ 8310 /****************************************************************************/ 8311 static void 8312 bce_tick(void *xsc) 8313 { 8314 struct bce_softc *sc = xsc; 8315 struct mii_data *mii; 8316 struct ifnet *ifp; 8317 struct ifmediareq ifmr; 8318 8319 ifp = sc->bce_ifp; 8320 8321 DBENTER(BCE_EXTREME_MISC); 8322 8323 BCE_LOCK_ASSERT(sc); 8324 8325 /* Schedule the next tick. */ 8326 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 8327 8328 /* Update the statistics from the hardware statistics block. */ 8329 bce_stats_update(sc); 8330 8331 /* Ensure page and RX chains get refilled in low-memory situations. */ 8332 if (bce_hdr_split == TRUE) 8333 bce_fill_pg_chain(sc); 8334 bce_fill_rx_chain(sc); 8335 8336 /* Check that chip hasn't hung. */ 8337 bce_watchdog(sc); 8338 8339 /* If link is up already up then we're done. */ 8340 if (sc->bce_link_up == TRUE) 8341 goto bce_tick_exit; 8342 8343 /* Link is down. Check what the PHY's doing. */ 8344 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 8345 bzero(&ifmr, sizeof(ifmr)); 8346 bce_ifmedia_sts_rphy(sc, &ifmr); 8347 if ((ifmr.ifm_status & (IFM_ACTIVE | IFM_AVALID)) == 8348 (IFM_ACTIVE | IFM_AVALID)) { 8349 sc->bce_link_up = TRUE; 8350 bce_miibus_statchg(sc->bce_dev); 8351 } 8352 } else { 8353 mii = device_get_softc(sc->bce_miibus); 8354 mii_tick(mii); 8355 /* Check if the link has come up. */ 8356 if ((mii->mii_media_status & IFM_ACTIVE) && 8357 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) { 8358 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n", 8359 __FUNCTION__); 8360 sc->bce_link_up = TRUE; 8361 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 8362 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX || 8363 IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) && 8364 (bce_verbose || bootverbose)) 8365 BCE_PRINTF("Gigabit link up!\n"); 8366 } 8367 } 8368 if (sc->bce_link_up == TRUE) { 8369 /* Now that link is up, handle any outstanding TX traffic. */ 8370 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 8371 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found " 8372 "pending TX traffic.\n", __FUNCTION__); 8373 bce_start_locked(ifp); 8374 } 8375 } 8376 8377 bce_tick_exit: 8378 DBEXIT(BCE_EXTREME_MISC); 8379 } 8380 8381 static void 8382 bce_fw_cap_init(struct bce_softc *sc) 8383 { 8384 u32 ack, cap, link; 8385 8386 ack = 0; 8387 cap = bce_shmem_rd(sc, BCE_FW_CAP_MB); 8388 if ((cap & BCE_FW_CAP_SIGNATURE_MAGIC_MASK) != 8389 BCE_FW_CAP_SIGNATURE_MAGIC) 8390 return; 8391 if ((cap & (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) == 8392 (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) 8393 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC | 8394 BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN; 8395 if ((sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) != 0 && 8396 (cap & BCE_FW_CAP_REMOTE_PHY_CAP) != 0) { 8397 sc->bce_phy_flags &= ~BCE_PHY_REMOTE_PORT_FIBER_FLAG; 8398 sc->bce_phy_flags |= BCE_PHY_REMOTE_CAP_FLAG; 8399 link = bce_shmem_rd(sc, BCE_LINK_STATUS); 8400 if ((link & BCE_LINK_STATUS_SERDES_LINK) != 0) 8401 sc->bce_phy_flags |= BCE_PHY_REMOTE_PORT_FIBER_FLAG; 8402 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC | 8403 BCE_FW_CAP_REMOTE_PHY_CAP; 8404 } 8405 8406 if (ack != 0) 8407 bce_shmem_wr(sc, BCE_DRV_ACK_CAP_MB, ack); 8408 } 8409 8410 #ifdef BCE_DEBUG 8411 /****************************************************************************/ 8412 /* Allows the driver state to be dumped through the sysctl interface. */ 8413 /* */ 8414 /* Returns: */ 8415 /* 0 for success, positive value for failure. */ 8416 /****************************************************************************/ 8417 static int 8418 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 8419 { 8420 int error; 8421 int result; 8422 struct bce_softc *sc; 8423 8424 result = -1; 8425 error = sysctl_handle_int(oidp, &result, 0, req); 8426 8427 if (error || !req->newptr) 8428 return (error); 8429 8430 if (result == 1) { 8431 sc = (struct bce_softc *)arg1; 8432 bce_dump_driver_state(sc); 8433 } 8434 8435 return error; 8436 } 8437 8438 /****************************************************************************/ 8439 /* Allows the hardware state to be dumped through the sysctl interface. */ 8440 /* */ 8441 /* Returns: */ 8442 /* 0 for success, positive value for failure. */ 8443 /****************************************************************************/ 8444 static int 8445 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 8446 { 8447 int error; 8448 int result; 8449 struct bce_softc *sc; 8450 8451 result = -1; 8452 error = sysctl_handle_int(oidp, &result, 0, req); 8453 8454 if (error || !req->newptr) 8455 return (error); 8456 8457 if (result == 1) { 8458 sc = (struct bce_softc *)arg1; 8459 bce_dump_hw_state(sc); 8460 } 8461 8462 return error; 8463 } 8464 8465 /****************************************************************************/ 8466 /* Allows the status block to be dumped through the sysctl interface. */ 8467 /* */ 8468 /* Returns: */ 8469 /* 0 for success, positive value for failure. */ 8470 /****************************************************************************/ 8471 static int 8472 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS) 8473 { 8474 int error; 8475 int result; 8476 struct bce_softc *sc; 8477 8478 result = -1; 8479 error = sysctl_handle_int(oidp, &result, 0, req); 8480 8481 if (error || !req->newptr) 8482 return (error); 8483 8484 if (result == 1) { 8485 sc = (struct bce_softc *)arg1; 8486 bce_dump_status_block(sc); 8487 } 8488 8489 return error; 8490 } 8491 8492 /****************************************************************************/ 8493 /* Allows the stats block to be dumped through the sysctl interface. */ 8494 /* */ 8495 /* Returns: */ 8496 /* 0 for success, positive value for failure. */ 8497 /****************************************************************************/ 8498 static int 8499 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS) 8500 { 8501 int error; 8502 int result; 8503 struct bce_softc *sc; 8504 8505 result = -1; 8506 error = sysctl_handle_int(oidp, &result, 0, req); 8507 8508 if (error || !req->newptr) 8509 return (error); 8510 8511 if (result == 1) { 8512 sc = (struct bce_softc *)arg1; 8513 bce_dump_stats_block(sc); 8514 } 8515 8516 return error; 8517 } 8518 8519 /****************************************************************************/ 8520 /* Allows the stat counters to be cleared without unloading/reloading the */ 8521 /* driver. */ 8522 /* */ 8523 /* Returns: */ 8524 /* 0 for success, positive value for failure. */ 8525 /****************************************************************************/ 8526 static int 8527 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS) 8528 { 8529 int error; 8530 int result; 8531 struct bce_softc *sc; 8532 8533 result = -1; 8534 error = sysctl_handle_int(oidp, &result, 0, req); 8535 8536 if (error || !req->newptr) 8537 return (error); 8538 8539 if (result == 1) { 8540 sc = (struct bce_softc *)arg1; 8541 struct statistics_block *stats; 8542 8543 stats = (struct statistics_block *) sc->stats_block; 8544 bzero(stats, sizeof(struct statistics_block)); 8545 bus_dmamap_sync(sc->stats_tag, sc->stats_map, 8546 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 8547 8548 /* Clear the internal H/W statistics counters. */ 8549 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 8550 8551 /* Reset the driver maintained statistics. */ 8552 sc->interrupts_rx = 8553 sc->interrupts_tx = 0; 8554 sc->tso_frames_requested = 8555 sc->tso_frames_completed = 8556 sc->tso_frames_failed = 0; 8557 sc->rx_empty_count = 8558 sc->tx_full_count = 0; 8559 sc->rx_low_watermark = USABLE_RX_BD_ALLOC; 8560 sc->tx_hi_watermark = 0; 8561 sc->l2fhdr_error_count = 8562 sc->l2fhdr_error_sim_count = 0; 8563 sc->mbuf_alloc_failed_count = 8564 sc->mbuf_alloc_failed_sim_count = 0; 8565 sc->dma_map_addr_rx_failed_count = 8566 sc->dma_map_addr_tx_failed_count = 0; 8567 sc->mbuf_frag_count = 0; 8568 sc->csum_offload_tcp_udp = 8569 sc->csum_offload_ip = 0; 8570 sc->vlan_tagged_frames_rcvd = 8571 sc->vlan_tagged_frames_stripped = 0; 8572 sc->split_header_frames_rcvd = 8573 sc->split_header_tcp_frames_rcvd = 0; 8574 8575 /* Clear firmware maintained statistics. */ 8576 REG_WR_IND(sc, 0x120084, 0); 8577 } 8578 8579 return error; 8580 } 8581 8582 /****************************************************************************/ 8583 /* Allows the shared memory contents to be dumped through the sysctl . */ 8584 /* interface. */ 8585 /* */ 8586 /* Returns: */ 8587 /* 0 for success, positive value for failure. */ 8588 /****************************************************************************/ 8589 static int 8590 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS) 8591 { 8592 int error; 8593 int result; 8594 struct bce_softc *sc; 8595 8596 result = -1; 8597 error = sysctl_handle_int(oidp, &result, 0, req); 8598 8599 if (error || !req->newptr) 8600 return (error); 8601 8602 if (result == 1) { 8603 sc = (struct bce_softc *)arg1; 8604 bce_dump_shmem_state(sc); 8605 } 8606 8607 return error; 8608 } 8609 8610 /****************************************************************************/ 8611 /* Allows the bootcode state to be dumped through the sysctl interface. */ 8612 /* */ 8613 /* Returns: */ 8614 /* 0 for success, positive value for failure. */ 8615 /****************************************************************************/ 8616 static int 8617 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 8618 { 8619 int error; 8620 int result; 8621 struct bce_softc *sc; 8622 8623 result = -1; 8624 error = sysctl_handle_int(oidp, &result, 0, req); 8625 8626 if (error || !req->newptr) 8627 return (error); 8628 8629 if (result == 1) { 8630 sc = (struct bce_softc *)arg1; 8631 bce_dump_bc_state(sc); 8632 } 8633 8634 return error; 8635 } 8636 8637 /****************************************************************************/ 8638 /* Provides a sysctl interface to allow dumping the RX BD chain. */ 8639 /* */ 8640 /* Returns: */ 8641 /* 0 for success, positive value for failure. */ 8642 /****************************************************************************/ 8643 static int 8644 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS) 8645 { 8646 int error; 8647 int result; 8648 struct bce_softc *sc; 8649 8650 result = -1; 8651 error = sysctl_handle_int(oidp, &result, 0, req); 8652 8653 if (error || !req->newptr) 8654 return (error); 8655 8656 if (result == 1) { 8657 sc = (struct bce_softc *)arg1; 8658 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC); 8659 } 8660 8661 return error; 8662 } 8663 8664 /****************************************************************************/ 8665 /* Provides a sysctl interface to allow dumping the RX MBUF chain. */ 8666 /* */ 8667 /* Returns: */ 8668 /* 0 for success, positive value for failure. */ 8669 /****************************************************************************/ 8670 static int 8671 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS) 8672 { 8673 int error; 8674 int result; 8675 struct bce_softc *sc; 8676 8677 result = -1; 8678 error = sysctl_handle_int(oidp, &result, 0, req); 8679 8680 if (error || !req->newptr) 8681 return (error); 8682 8683 if (result == 1) { 8684 sc = (struct bce_softc *)arg1; 8685 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 8686 } 8687 8688 return error; 8689 } 8690 8691 /****************************************************************************/ 8692 /* Provides a sysctl interface to allow dumping the TX chain. */ 8693 /* */ 8694 /* Returns: */ 8695 /* 0 for success, positive value for failure. */ 8696 /****************************************************************************/ 8697 static int 8698 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 8699 { 8700 int error; 8701 int result; 8702 struct bce_softc *sc; 8703 8704 result = -1; 8705 error = sysctl_handle_int(oidp, &result, 0, req); 8706 8707 if (error || !req->newptr) 8708 return (error); 8709 8710 if (result == 1) { 8711 sc = (struct bce_softc *)arg1; 8712 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC); 8713 } 8714 8715 return error; 8716 } 8717 8718 /****************************************************************************/ 8719 /* Provides a sysctl interface to allow dumping the page chain. */ 8720 /* */ 8721 /* Returns: */ 8722 /* 0 for success, positive value for failure. */ 8723 /****************************************************************************/ 8724 static int 8725 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS) 8726 { 8727 int error; 8728 int result; 8729 struct bce_softc *sc; 8730 8731 result = -1; 8732 error = sysctl_handle_int(oidp, &result, 0, req); 8733 8734 if (error || !req->newptr) 8735 return (error); 8736 8737 if (result == 1) { 8738 sc = (struct bce_softc *)arg1; 8739 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC); 8740 } 8741 8742 return error; 8743 } 8744 8745 /****************************************************************************/ 8746 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */ 8747 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8748 /* */ 8749 /* Returns: */ 8750 /* 0 for success, positive value for failure. */ 8751 /****************************************************************************/ 8752 static int 8753 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS) 8754 { 8755 struct bce_softc *sc = (struct bce_softc *)arg1; 8756 int error; 8757 u32 result; 8758 u32 val[1]; 8759 u8 *data = (u8 *) val; 8760 8761 result = -1; 8762 error = sysctl_handle_int(oidp, &result, 0, req); 8763 if (error || (req->newptr == NULL)) 8764 return (error); 8765 8766 error = bce_nvram_read(sc, result, data, 4); 8767 8768 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0])); 8769 8770 return (error); 8771 } 8772 8773 /****************************************************************************/ 8774 /* Provides a sysctl interface to allow reading arbitrary registers in the */ 8775 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8776 /* */ 8777 /* Returns: */ 8778 /* 0 for success, positive value for failure. */ 8779 /****************************************************************************/ 8780 static int 8781 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 8782 { 8783 struct bce_softc *sc = (struct bce_softc *)arg1; 8784 int error; 8785 u32 val, result; 8786 8787 result = -1; 8788 error = sysctl_handle_int(oidp, &result, 0, req); 8789 if (error || (req->newptr == NULL)) 8790 return (error); 8791 8792 /* Make sure the register is accessible. */ 8793 if (result < 0x8000) { 8794 val = REG_RD(sc, result); 8795 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8796 } else if (result < 0x0280000) { 8797 val = REG_RD_IND(sc, result); 8798 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8799 } 8800 8801 return (error); 8802 } 8803 8804 /****************************************************************************/ 8805 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 8806 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8807 /* */ 8808 /* Returns: */ 8809 /* 0 for success, positive value for failure. */ 8810 /****************************************************************************/ 8811 static int 8812 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 8813 { 8814 struct bce_softc *sc; 8815 device_t dev; 8816 int error, result; 8817 u16 val; 8818 8819 result = -1; 8820 error = sysctl_handle_int(oidp, &result, 0, req); 8821 if (error || (req->newptr == NULL)) 8822 return (error); 8823 8824 /* Make sure the register is accessible. */ 8825 if (result < 0x20) { 8826 sc = (struct bce_softc *)arg1; 8827 dev = sc->bce_dev; 8828 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 8829 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 8830 } 8831 return (error); 8832 } 8833 8834 /****************************************************************************/ 8835 /* Provides a sysctl interface for dumping the nvram contents. */ 8836 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8837 /* */ 8838 /* Returns: */ 8839 /* 0 for success, positive errno for failure. */ 8840 /****************************************************************************/ 8841 static int 8842 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS) 8843 { 8844 struct bce_softc *sc = (struct bce_softc *)arg1; 8845 int error, i; 8846 8847 if (sc->nvram_buf == NULL) 8848 sc->nvram_buf = malloc(sc->bce_flash_size, 8849 M_TEMP, M_ZERO | M_WAITOK); 8850 8851 error = 0; 8852 if (req->oldlen == sc->bce_flash_size) { 8853 for (i = 0; i < sc->bce_flash_size && error == 0; i++) 8854 error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1); 8855 } 8856 8857 if (error == 0) 8858 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size); 8859 8860 return error; 8861 } 8862 8863 #ifdef BCE_NVRAM_WRITE_SUPPORT 8864 /****************************************************************************/ 8865 /* Provides a sysctl interface for writing to nvram. */ 8866 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8867 /* */ 8868 /* Returns: */ 8869 /* 0 for success, positive errno for failure. */ 8870 /****************************************************************************/ 8871 static int 8872 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS) 8873 { 8874 struct bce_softc *sc = (struct bce_softc *)arg1; 8875 int error; 8876 8877 if (sc->nvram_buf == NULL) 8878 sc->nvram_buf = malloc(sc->bce_flash_size, 8879 M_TEMP, M_ZERO | M_WAITOK); 8880 else 8881 bzero(sc->nvram_buf, sc->bce_flash_size); 8882 8883 error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size); 8884 if (error == 0) 8885 return (error); 8886 8887 if (req->newlen == sc->bce_flash_size) 8888 error = bce_nvram_write(sc, 0, sc->nvram_buf, 8889 sc->bce_flash_size); 8890 8891 return error; 8892 } 8893 #endif 8894 8895 /****************************************************************************/ 8896 /* Provides a sysctl interface to allow reading a CID. */ 8897 /* */ 8898 /* Returns: */ 8899 /* 0 for success, positive value for failure. */ 8900 /****************************************************************************/ 8901 static int 8902 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS) 8903 { 8904 struct bce_softc *sc; 8905 int error, result; 8906 8907 result = -1; 8908 error = sysctl_handle_int(oidp, &result, 0, req); 8909 if (error || (req->newptr == NULL)) 8910 return (error); 8911 8912 /* Make sure the register is accessible. */ 8913 if (result <= TX_CID) { 8914 sc = (struct bce_softc *)arg1; 8915 bce_dump_ctx(sc, result); 8916 } 8917 8918 return (error); 8919 } 8920 8921 /****************************************************************************/ 8922 /* Provides a sysctl interface to forcing the driver to dump state and */ 8923 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8924 /* */ 8925 /* Returns: */ 8926 /* 0 for success, positive value for failure. */ 8927 /****************************************************************************/ 8928 static int 8929 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 8930 { 8931 int error; 8932 int result; 8933 struct bce_softc *sc; 8934 8935 result = -1; 8936 error = sysctl_handle_int(oidp, &result, 0, req); 8937 8938 if (error || !req->newptr) 8939 return (error); 8940 8941 if (result == 1) { 8942 sc = (struct bce_softc *)arg1; 8943 bce_breakpoint(sc); 8944 } 8945 8946 return error; 8947 } 8948 #endif 8949 8950 /****************************************************************************/ 8951 /* Adds any sysctl parameters for tuning or debugging purposes. */ 8952 /* */ 8953 /* Returns: */ 8954 /* 0 for success, positive value for failure. */ 8955 /****************************************************************************/ 8956 static void 8957 bce_add_sysctls(struct bce_softc *sc) 8958 { 8959 struct sysctl_ctx_list *ctx; 8960 struct sysctl_oid_list *children; 8961 8962 DBENTER(BCE_VERBOSE_MISC); 8963 8964 ctx = device_get_sysctl_ctx(sc->bce_dev); 8965 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 8966 8967 #ifdef BCE_DEBUG 8968 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8969 "l2fhdr_error_sim_control", 8970 CTLFLAG_RW, &l2fhdr_error_sim_control, 8971 0, "Debug control to force l2fhdr errors"); 8972 8973 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8974 "l2fhdr_error_sim_count", 8975 CTLFLAG_RD, &sc->l2fhdr_error_sim_count, 8976 0, "Number of simulated l2_fhdr errors"); 8977 #endif 8978 8979 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8980 "l2fhdr_error_count", 8981 CTLFLAG_RD, &sc->l2fhdr_error_count, 8982 0, "Number of l2_fhdr errors"); 8983 8984 #ifdef BCE_DEBUG 8985 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8986 "mbuf_alloc_failed_sim_control", 8987 CTLFLAG_RW, &mbuf_alloc_failed_sim_control, 8988 0, "Debug control to force mbuf allocation failures"); 8989 8990 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8991 "mbuf_alloc_failed_sim_count", 8992 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count, 8993 0, "Number of simulated mbuf cluster allocation failures"); 8994 #endif 8995 8996 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8997 "mbuf_alloc_failed_count", 8998 CTLFLAG_RD, &sc->mbuf_alloc_failed_count, 8999 0, "Number of mbuf allocation failures"); 9000 9001 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9002 "mbuf_frag_count", 9003 CTLFLAG_RD, &sc->mbuf_frag_count, 9004 0, "Number of fragmented mbufs"); 9005 9006 #ifdef BCE_DEBUG 9007 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9008 "dma_map_addr_failed_sim_control", 9009 CTLFLAG_RW, &dma_map_addr_failed_sim_control, 9010 0, "Debug control to force DMA mapping failures"); 9011 9012 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */ 9013 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9014 "dma_map_addr_failed_sim_count", 9015 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count, 9016 0, "Number of simulated DMA mapping failures"); 9017 9018 #endif 9019 9020 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9021 "dma_map_addr_rx_failed_count", 9022 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count, 9023 0, "Number of RX DMA mapping failures"); 9024 9025 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9026 "dma_map_addr_tx_failed_count", 9027 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count, 9028 0, "Number of TX DMA mapping failures"); 9029 9030 #ifdef BCE_DEBUG 9031 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9032 "unexpected_attention_sim_control", 9033 CTLFLAG_RW, &unexpected_attention_sim_control, 9034 0, "Debug control to simulate unexpected attentions"); 9035 9036 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9037 "unexpected_attention_sim_count", 9038 CTLFLAG_RW, &sc->unexpected_attention_sim_count, 9039 0, "Number of simulated unexpected attentions"); 9040 #endif 9041 9042 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9043 "unexpected_attention_count", 9044 CTLFLAG_RW, &sc->unexpected_attention_count, 9045 0, "Number of unexpected attentions"); 9046 9047 #ifdef BCE_DEBUG 9048 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9049 "debug_bootcode_running_failure", 9050 CTLFLAG_RW, &bootcode_running_failure_sim_control, 9051 0, "Debug control to force bootcode running failures"); 9052 9053 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9054 "rx_low_watermark", 9055 CTLFLAG_RD, &sc->rx_low_watermark, 9056 0, "Lowest level of free rx_bd's"); 9057 9058 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9059 "rx_empty_count", 9060 CTLFLAG_RD, &sc->rx_empty_count, 9061 "Number of times the RX chain was empty"); 9062 9063 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9064 "tx_hi_watermark", 9065 CTLFLAG_RD, &sc->tx_hi_watermark, 9066 0, "Highest level of used tx_bd's"); 9067 9068 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9069 "tx_full_count", 9070 CTLFLAG_RD, &sc->tx_full_count, 9071 "Number of times the TX chain was full"); 9072 9073 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9074 "tso_frames_requested", 9075 CTLFLAG_RD, &sc->tso_frames_requested, 9076 "Number of TSO frames requested"); 9077 9078 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9079 "tso_frames_completed", 9080 CTLFLAG_RD, &sc->tso_frames_completed, 9081 "Number of TSO frames completed"); 9082 9083 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9084 "tso_frames_failed", 9085 CTLFLAG_RD, &sc->tso_frames_failed, 9086 "Number of TSO frames failed"); 9087 9088 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9089 "csum_offload_ip", 9090 CTLFLAG_RD, &sc->csum_offload_ip, 9091 "Number of IP checksum offload frames"); 9092 9093 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9094 "csum_offload_tcp_udp", 9095 CTLFLAG_RD, &sc->csum_offload_tcp_udp, 9096 "Number of TCP/UDP checksum offload frames"); 9097 9098 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9099 "vlan_tagged_frames_rcvd", 9100 CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd, 9101 "Number of VLAN tagged frames received"); 9102 9103 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9104 "vlan_tagged_frames_stripped", 9105 CTLFLAG_RD, &sc->vlan_tagged_frames_stripped, 9106 "Number of VLAN tagged frames stripped"); 9107 9108 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9109 "interrupts_rx", 9110 CTLFLAG_RD, &sc->interrupts_rx, 9111 "Number of RX interrupts"); 9112 9113 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9114 "interrupts_tx", 9115 CTLFLAG_RD, &sc->interrupts_tx, 9116 "Number of TX interrupts"); 9117 9118 if (bce_hdr_split == TRUE) { 9119 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9120 "split_header_frames_rcvd", 9121 CTLFLAG_RD, &sc->split_header_frames_rcvd, 9122 "Number of split header frames received"); 9123 9124 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9125 "split_header_tcp_frames_rcvd", 9126 CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd, 9127 "Number of split header TCP frames received"); 9128 } 9129 9130 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9131 "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 9132 (void *)sc, 0, 9133 bce_sysctl_nvram_dump, "S", ""); 9134 9135 #ifdef BCE_NVRAM_WRITE_SUPPORT 9136 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9137 "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR | CTLFLAG_NEEDGIANT, 9138 (void *)sc, 0, 9139 bce_sysctl_nvram_write, "S", ""); 9140 #endif 9141 #endif /* BCE_DEBUG */ 9142 9143 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9144 "stat_IfHcInOctets", 9145 CTLFLAG_RD, &sc->stat_IfHCInOctets, 9146 "Bytes received"); 9147 9148 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9149 "stat_IfHCInBadOctets", 9150 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 9151 "Bad bytes received"); 9152 9153 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9154 "stat_IfHCOutOctets", 9155 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 9156 "Bytes sent"); 9157 9158 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9159 "stat_IfHCOutBadOctets", 9160 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 9161 "Bad bytes sent"); 9162 9163 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9164 "stat_IfHCInUcastPkts", 9165 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 9166 "Unicast packets received"); 9167 9168 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9169 "stat_IfHCInMulticastPkts", 9170 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 9171 "Multicast packets received"); 9172 9173 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9174 "stat_IfHCInBroadcastPkts", 9175 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 9176 "Broadcast packets received"); 9177 9178 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9179 "stat_IfHCOutUcastPkts", 9180 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 9181 "Unicast packets sent"); 9182 9183 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9184 "stat_IfHCOutMulticastPkts", 9185 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 9186 "Multicast packets sent"); 9187 9188 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9189 "stat_IfHCOutBroadcastPkts", 9190 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 9191 "Broadcast packets sent"); 9192 9193 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9194 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 9195 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 9196 0, "Internal MAC transmit errors"); 9197 9198 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9199 "stat_Dot3StatsCarrierSenseErrors", 9200 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 9201 0, "Carrier sense errors"); 9202 9203 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9204 "stat_Dot3StatsFCSErrors", 9205 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 9206 0, "Frame check sequence errors"); 9207 9208 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9209 "stat_Dot3StatsAlignmentErrors", 9210 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 9211 0, "Alignment errors"); 9212 9213 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9214 "stat_Dot3StatsSingleCollisionFrames", 9215 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 9216 0, "Single Collision Frames"); 9217 9218 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9219 "stat_Dot3StatsMultipleCollisionFrames", 9220 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 9221 0, "Multiple Collision Frames"); 9222 9223 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9224 "stat_Dot3StatsDeferredTransmissions", 9225 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 9226 0, "Deferred Transmissions"); 9227 9228 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9229 "stat_Dot3StatsExcessiveCollisions", 9230 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 9231 0, "Excessive Collisions"); 9232 9233 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9234 "stat_Dot3StatsLateCollisions", 9235 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 9236 0, "Late Collisions"); 9237 9238 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9239 "stat_EtherStatsCollisions", 9240 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 9241 0, "Collisions"); 9242 9243 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9244 "stat_EtherStatsFragments", 9245 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 9246 0, "Fragments"); 9247 9248 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9249 "stat_EtherStatsJabbers", 9250 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 9251 0, "Jabbers"); 9252 9253 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9254 "stat_EtherStatsUndersizePkts", 9255 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 9256 0, "Undersize packets"); 9257 9258 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9259 "stat_EtherStatsOversizePkts", 9260 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts, 9261 0, "stat_EtherStatsOversizePkts"); 9262 9263 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9264 "stat_EtherStatsPktsRx64Octets", 9265 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 9266 0, "Bytes received in 64 byte packets"); 9267 9268 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9269 "stat_EtherStatsPktsRx65Octetsto127Octets", 9270 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 9271 0, "Bytes received in 65 to 127 byte packets"); 9272 9273 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9274 "stat_EtherStatsPktsRx128Octetsto255Octets", 9275 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 9276 0, "Bytes received in 128 to 255 byte packets"); 9277 9278 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9279 "stat_EtherStatsPktsRx256Octetsto511Octets", 9280 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 9281 0, "Bytes received in 256 to 511 byte packets"); 9282 9283 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9284 "stat_EtherStatsPktsRx512Octetsto1023Octets", 9285 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 9286 0, "Bytes received in 512 to 1023 byte packets"); 9287 9288 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9289 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 9290 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 9291 0, "Bytes received in 1024 t0 1522 byte packets"); 9292 9293 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9294 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 9295 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 9296 0, "Bytes received in 1523 to 9022 byte packets"); 9297 9298 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9299 "stat_EtherStatsPktsTx64Octets", 9300 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 9301 0, "Bytes sent in 64 byte packets"); 9302 9303 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9304 "stat_EtherStatsPktsTx65Octetsto127Octets", 9305 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 9306 0, "Bytes sent in 65 to 127 byte packets"); 9307 9308 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9309 "stat_EtherStatsPktsTx128Octetsto255Octets", 9310 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 9311 0, "Bytes sent in 128 to 255 byte packets"); 9312 9313 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9314 "stat_EtherStatsPktsTx256Octetsto511Octets", 9315 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 9316 0, "Bytes sent in 256 to 511 byte packets"); 9317 9318 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9319 "stat_EtherStatsPktsTx512Octetsto1023Octets", 9320 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 9321 0, "Bytes sent in 512 to 1023 byte packets"); 9322 9323 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9324 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 9325 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 9326 0, "Bytes sent in 1024 to 1522 byte packets"); 9327 9328 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9329 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 9330 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 9331 0, "Bytes sent in 1523 to 9022 byte packets"); 9332 9333 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9334 "stat_XonPauseFramesReceived", 9335 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 9336 0, "XON pause frames receved"); 9337 9338 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9339 "stat_XoffPauseFramesReceived", 9340 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 9341 0, "XOFF pause frames received"); 9342 9343 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9344 "stat_OutXonSent", 9345 CTLFLAG_RD, &sc->stat_OutXonSent, 9346 0, "XON pause frames sent"); 9347 9348 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9349 "stat_OutXoffSent", 9350 CTLFLAG_RD, &sc->stat_OutXoffSent, 9351 0, "XOFF pause frames sent"); 9352 9353 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9354 "stat_FlowControlDone", 9355 CTLFLAG_RD, &sc->stat_FlowControlDone, 9356 0, "Flow control done"); 9357 9358 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9359 "stat_MacControlFramesReceived", 9360 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 9361 0, "MAC control frames received"); 9362 9363 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9364 "stat_XoffStateEntered", 9365 CTLFLAG_RD, &sc->stat_XoffStateEntered, 9366 0, "XOFF state entered"); 9367 9368 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9369 "stat_IfInFramesL2FilterDiscards", 9370 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 9371 0, "Received L2 packets discarded"); 9372 9373 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9374 "stat_IfInRuleCheckerDiscards", 9375 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 9376 0, "Received packets discarded by rule"); 9377 9378 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9379 "stat_IfInFTQDiscards", 9380 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 9381 0, "Received packet FTQ discards"); 9382 9383 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9384 "stat_IfInMBUFDiscards", 9385 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 9386 0, "Received packets discarded due to lack " 9387 "of controller buffer memory"); 9388 9389 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9390 "stat_IfInRuleCheckerP4Hit", 9391 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 9392 0, "Received packets rule checker hits"); 9393 9394 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9395 "stat_CatchupInRuleCheckerDiscards", 9396 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 9397 0, "Received packets discarded in Catchup path"); 9398 9399 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9400 "stat_CatchupInFTQDiscards", 9401 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 9402 0, "Received packets discarded in FTQ in Catchup path"); 9403 9404 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9405 "stat_CatchupInMBUFDiscards", 9406 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 9407 0, "Received packets discarded in controller " 9408 "buffer memory in Catchup path"); 9409 9410 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9411 "stat_CatchupInRuleCheckerP4Hit", 9412 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 9413 0, "Received packets rule checker hits in Catchup path"); 9414 9415 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9416 "com_no_buffers", 9417 CTLFLAG_RD, &sc->com_no_buffers, 9418 0, "Valid packets received but no RX buffers available"); 9419 9420 #ifdef BCE_DEBUG 9421 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9422 "driver_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9423 (void *)sc, 0, 9424 bce_sysctl_driver_state, "I", "Drive state information"); 9425 9426 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9427 "hw_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9428 (void *)sc, 0, 9429 bce_sysctl_hw_state, "I", "Hardware state information"); 9430 9431 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9432 "status_block", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9433 (void *)sc, 0, 9434 bce_sysctl_status_block, "I", "Dump status block"); 9435 9436 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9437 "stats_block", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9438 (void *)sc, 0, 9439 bce_sysctl_stats_block, "I", "Dump statistics block"); 9440 9441 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9442 "stats_clear", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9443 (void *)sc, 0, 9444 bce_sysctl_stats_clear, "I", "Clear statistics block"); 9445 9446 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9447 "shmem_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9448 (void *)sc, 0, 9449 bce_sysctl_shmem_state, "I", "Shared memory state information"); 9450 9451 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9452 "bc_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9453 (void *)sc, 0, 9454 bce_sysctl_bc_state, "I", "Bootcode state information"); 9455 9456 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9457 "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9458 (void *)sc, 0, 9459 bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain"); 9460 9461 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9462 "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9463 (void *)sc, 0, 9464 bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain"); 9465 9466 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9467 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9468 (void *)sc, 0, 9469 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 9470 9471 if (bce_hdr_split == TRUE) { 9472 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9473 "dump_pg_chain", 9474 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9475 (void *)sc, 0, 9476 bce_sysctl_dump_pg_chain, "I", "Dump page chain"); 9477 } 9478 9479 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9480 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9481 (void *)sc, 0, 9482 bce_sysctl_dump_ctx, "I", "Dump context memory"); 9483 9484 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9485 "breakpoint", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9486 (void *)sc, 0, 9487 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 9488 9489 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9490 "reg_read", CTLTYPE_INT | CTLFLAG_RW| CTLFLAG_NEEDGIANT, 9491 (void *)sc, 0, 9492 bce_sysctl_reg_read, "I", "Register read"); 9493 9494 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9495 "nvram_read", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9496 (void *)sc, 0, 9497 bce_sysctl_nvram_read, "I", "NVRAM read"); 9498 9499 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9500 "phy_read", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9501 (void *)sc, 0, 9502 bce_sysctl_phy_read, "I", "PHY register read"); 9503 9504 #endif 9505 9506 DBEXIT(BCE_VERBOSE_MISC); 9507 } 9508 9509 /****************************************************************************/ 9510 /* BCE Debug Routines */ 9511 /****************************************************************************/ 9512 #ifdef BCE_DEBUG 9513 9514 /****************************************************************************/ 9515 /* Freezes the controller to allow for a cohesive state dump. */ 9516 /* */ 9517 /* Returns: */ 9518 /* Nothing. */ 9519 /****************************************************************************/ 9520 static __attribute__ ((noinline)) void 9521 bce_freeze_controller(struct bce_softc *sc) 9522 { 9523 u32 val; 9524 val = REG_RD(sc, BCE_MISC_COMMAND); 9525 val |= BCE_MISC_COMMAND_DISABLE_ALL; 9526 REG_WR(sc, BCE_MISC_COMMAND, val); 9527 } 9528 9529 /****************************************************************************/ 9530 /* Unfreezes the controller after a freeze operation. This may not always */ 9531 /* work and the controller will require a reset! */ 9532 /* */ 9533 /* Returns: */ 9534 /* Nothing. */ 9535 /****************************************************************************/ 9536 static __attribute__ ((noinline)) void 9537 bce_unfreeze_controller(struct bce_softc *sc) 9538 { 9539 u32 val; 9540 val = REG_RD(sc, BCE_MISC_COMMAND); 9541 val |= BCE_MISC_COMMAND_ENABLE_ALL; 9542 REG_WR(sc, BCE_MISC_COMMAND, val); 9543 } 9544 9545 /****************************************************************************/ 9546 /* Prints out Ethernet frame information from an mbuf. */ 9547 /* */ 9548 /* Partially decode an Ethernet frame to look at some important headers. */ 9549 /* */ 9550 /* Returns: */ 9551 /* Nothing. */ 9552 /****************************************************************************/ 9553 static __attribute__ ((noinline)) void 9554 bce_dump_enet(struct bce_softc *sc, struct mbuf *m) 9555 { 9556 struct ether_vlan_header *eh; 9557 u16 etype; 9558 int ehlen; 9559 struct ip *ip; 9560 struct tcphdr *th; 9561 struct udphdr *uh; 9562 struct arphdr *ah; 9563 9564 BCE_PRINTF( 9565 "-----------------------------" 9566 " Frame Decode " 9567 "-----------------------------\n"); 9568 9569 eh = mtod(m, struct ether_vlan_header *); 9570 9571 /* Handle VLAN encapsulation if present. */ 9572 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 9573 etype = ntohs(eh->evl_proto); 9574 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 9575 } else { 9576 etype = ntohs(eh->evl_encap_proto); 9577 ehlen = ETHER_HDR_LEN; 9578 } 9579 9580 /* ToDo: Add VLAN output. */ 9581 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n", 9582 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen); 9583 9584 switch (etype) { 9585 case ETHERTYPE_IP: 9586 ip = (struct ip *)(m->m_data + ehlen); 9587 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, " 9588 "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n", 9589 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr), 9590 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum)); 9591 9592 switch (ip->ip_p) { 9593 case IPPROTO_TCP: 9594 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9595 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = " 9596 "%d bytes, flags = 0x%b, csum = 0x%04X\n", 9597 ntohs(th->th_dport), ntohs(th->th_sport), 9598 (th->th_off << 2), th->th_flags, 9599 "\2\10CWR\07ECE\06URG\05ACK\04PSH\03RST" 9600 "\02SYN\01FIN", ntohs(th->th_sum)); 9601 break; 9602 case IPPROTO_UDP: 9603 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9604 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d " 9605 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport), 9606 ntohs(uh->uh_sport), ntohs(uh->uh_ulen), 9607 ntohs(uh->uh_sum)); 9608 break; 9609 case IPPROTO_ICMP: 9610 BCE_PRINTF("icmp:\n"); 9611 break; 9612 default: 9613 BCE_PRINTF("----: Other IP protocol.\n"); 9614 } 9615 break; 9616 case ETHERTYPE_IPV6: 9617 BCE_PRINTF("ipv6: No decode supported.\n"); 9618 break; 9619 case ETHERTYPE_ARP: 9620 BCE_PRINTF("-arp: "); 9621 ah = (struct arphdr *) (m->m_data + ehlen); 9622 switch (ntohs(ah->ar_op)) { 9623 case ARPOP_REVREQUEST: 9624 printf("reverse ARP request\n"); 9625 break; 9626 case ARPOP_REVREPLY: 9627 printf("reverse ARP reply\n"); 9628 break; 9629 case ARPOP_REQUEST: 9630 printf("ARP request\n"); 9631 break; 9632 case ARPOP_REPLY: 9633 printf("ARP reply\n"); 9634 break; 9635 default: 9636 printf("other ARP operation\n"); 9637 } 9638 break; 9639 default: 9640 BCE_PRINTF("----: Other protocol.\n"); 9641 } 9642 9643 BCE_PRINTF( 9644 "-----------------------------" 9645 "--------------" 9646 "-----------------------------\n"); 9647 } 9648 9649 /****************************************************************************/ 9650 /* Prints out information about an mbuf. */ 9651 /* */ 9652 /* Returns: */ 9653 /* Nothing. */ 9654 /****************************************************************************/ 9655 static __attribute__ ((noinline)) void 9656 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 9657 { 9658 struct mbuf *mp = m; 9659 9660 if (m == NULL) { 9661 BCE_PRINTF("mbuf: null pointer\n"); 9662 return; 9663 } 9664 9665 while (mp) { 9666 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, " 9667 "m_data = %p\n", mp, mp->m_len, mp->m_flags, 9668 "\2\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data); 9669 9670 if (mp->m_flags & M_PKTHDR) { 9671 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, " 9672 "csum_flags = %b\n", mp->m_pkthdr.len, 9673 mp->m_flags, M_FLAG_PRINTF, 9674 mp->m_pkthdr.csum_flags, CSUM_BITS); 9675 } 9676 9677 if (mp->m_flags & M_EXT) { 9678 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ", 9679 mp->m_ext.ext_buf, mp->m_ext.ext_size); 9680 switch (mp->m_ext.ext_type) { 9681 case EXT_CLUSTER: 9682 printf("EXT_CLUSTER\n"); break; 9683 case EXT_SFBUF: 9684 printf("EXT_SFBUF\n"); break; 9685 case EXT_JUMBO9: 9686 printf("EXT_JUMBO9\n"); break; 9687 case EXT_JUMBO16: 9688 printf("EXT_JUMBO16\n"); break; 9689 case EXT_PACKET: 9690 printf("EXT_PACKET\n"); break; 9691 case EXT_MBUF: 9692 printf("EXT_MBUF\n"); break; 9693 case EXT_NET_DRV: 9694 printf("EXT_NET_DRV\n"); break; 9695 case EXT_MOD_TYPE: 9696 printf("EXT_MDD_TYPE\n"); break; 9697 case EXT_DISPOSABLE: 9698 printf("EXT_DISPOSABLE\n"); break; 9699 case EXT_EXTREF: 9700 printf("EXT_EXTREF\n"); break; 9701 default: 9702 printf("UNKNOWN\n"); 9703 } 9704 } 9705 9706 mp = mp->m_next; 9707 } 9708 } 9709 9710 /****************************************************************************/ 9711 /* Prints out the mbufs in the TX mbuf chain. */ 9712 /* */ 9713 /* Returns: */ 9714 /* Nothing. */ 9715 /****************************************************************************/ 9716 static __attribute__ ((noinline)) void 9717 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9718 { 9719 struct mbuf *m; 9720 9721 BCE_PRINTF( 9722 "----------------------------" 9723 " tx mbuf data " 9724 "----------------------------\n"); 9725 9726 for (int i = 0; i < count; i++) { 9727 m = sc->tx_mbuf_ptr[chain_prod]; 9728 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod); 9729 bce_dump_mbuf(sc, m); 9730 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 9731 } 9732 9733 BCE_PRINTF( 9734 "----------------------------" 9735 "----------------" 9736 "----------------------------\n"); 9737 } 9738 9739 /****************************************************************************/ 9740 /* Prints out the mbufs in the RX mbuf chain. */ 9741 /* */ 9742 /* Returns: */ 9743 /* Nothing. */ 9744 /****************************************************************************/ 9745 static __attribute__ ((noinline)) void 9746 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9747 { 9748 struct mbuf *m; 9749 9750 BCE_PRINTF( 9751 "----------------------------" 9752 " rx mbuf data " 9753 "----------------------------\n"); 9754 9755 for (int i = 0; i < count; i++) { 9756 m = sc->rx_mbuf_ptr[chain_prod]; 9757 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 9758 bce_dump_mbuf(sc, m); 9759 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 9760 } 9761 9762 BCE_PRINTF( 9763 "----------------------------" 9764 "----------------" 9765 "----------------------------\n"); 9766 } 9767 9768 /****************************************************************************/ 9769 /* Prints out the mbufs in the mbuf page chain. */ 9770 /* */ 9771 /* Returns: */ 9772 /* Nothing. */ 9773 /****************************************************************************/ 9774 static __attribute__ ((noinline)) void 9775 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9776 { 9777 struct mbuf *m; 9778 9779 BCE_PRINTF( 9780 "----------------------------" 9781 " pg mbuf data " 9782 "----------------------------\n"); 9783 9784 for (int i = 0; i < count; i++) { 9785 m = sc->pg_mbuf_ptr[chain_prod]; 9786 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod); 9787 bce_dump_mbuf(sc, m); 9788 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod)); 9789 } 9790 9791 BCE_PRINTF( 9792 "----------------------------" 9793 "----------------" 9794 "----------------------------\n"); 9795 } 9796 9797 /****************************************************************************/ 9798 /* Prints out a tx_bd structure. */ 9799 /* */ 9800 /* Returns: */ 9801 /* Nothing. */ 9802 /****************************************************************************/ 9803 static __attribute__ ((noinline)) void 9804 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 9805 { 9806 int i = 0; 9807 9808 if (idx > MAX_TX_BD_ALLOC) 9809 /* Index out of range. */ 9810 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 9811 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 9812 /* TX Chain page pointer. */ 9813 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9814 "pointer\n", idx, txbd->tx_bd_haddr_hi, 9815 txbd->tx_bd_haddr_lo); 9816 else { 9817 /* Normal tx_bd entry. */ 9818 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, " 9819 "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = " 9820 "0x%04X (", idx, txbd->tx_bd_haddr_hi, 9821 txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes, 9822 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags); 9823 9824 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) { 9825 if (i>0) 9826 printf("|"); 9827 printf("CONN_FAULT"); 9828 i++; 9829 } 9830 9831 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) { 9832 if (i>0) 9833 printf("|"); 9834 printf("TCP_UDP_CKSUM"); 9835 i++; 9836 } 9837 9838 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) { 9839 if (i>0) 9840 printf("|"); 9841 printf("IP_CKSUM"); 9842 i++; 9843 } 9844 9845 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) { 9846 if (i>0) 9847 printf("|"); 9848 printf("VLAN"); 9849 i++; 9850 } 9851 9852 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) { 9853 if (i>0) 9854 printf("|"); 9855 printf("COAL_NOW"); 9856 i++; 9857 } 9858 9859 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) { 9860 if (i>0) 9861 printf("|"); 9862 printf("DONT_GEN_CRC"); 9863 i++; 9864 } 9865 9866 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) { 9867 if (i>0) 9868 printf("|"); 9869 printf("START"); 9870 i++; 9871 } 9872 9873 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) { 9874 if (i>0) 9875 printf("|"); 9876 printf("END"); 9877 i++; 9878 } 9879 9880 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) { 9881 if (i>0) 9882 printf("|"); 9883 printf("LSO"); 9884 i++; 9885 } 9886 9887 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) { 9888 if (i>0) 9889 printf("|"); 9890 printf("SW_OPTION=%d", ((txbd->tx_bd_flags & 9891 TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++; 9892 } 9893 9894 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) { 9895 if (i>0) 9896 printf("|"); 9897 printf("SW_FLAGS"); 9898 i++; 9899 } 9900 9901 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) { 9902 if (i>0) 9903 printf("|"); 9904 printf("SNAP)"); 9905 } else { 9906 printf(")\n"); 9907 } 9908 } 9909 } 9910 9911 /****************************************************************************/ 9912 /* Prints out a rx_bd structure. */ 9913 /* */ 9914 /* Returns: */ 9915 /* Nothing. */ 9916 /****************************************************************************/ 9917 static __attribute__ ((noinline)) void 9918 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 9919 { 9920 if (idx > MAX_RX_BD_ALLOC) 9921 /* Index out of range. */ 9922 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 9923 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 9924 /* RX Chain page pointer. */ 9925 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9926 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 9927 rxbd->rx_bd_haddr_lo); 9928 else 9929 /* Normal rx_bd entry. */ 9930 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 9931 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi, 9932 rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len, 9933 rxbd->rx_bd_flags); 9934 } 9935 9936 /****************************************************************************/ 9937 /* Prints out a rx_bd structure in the page chain. */ 9938 /* */ 9939 /* Returns: */ 9940 /* Nothing. */ 9941 /****************************************************************************/ 9942 static __attribute__ ((noinline)) void 9943 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd) 9944 { 9945 if (idx > MAX_PG_BD_ALLOC) 9946 /* Index out of range. */ 9947 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx); 9948 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE) 9949 /* Page Chain page pointer. */ 9950 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 9951 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo); 9952 else 9953 /* Normal rx_bd entry. */ 9954 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 9955 "flags = 0x%08X\n", idx, 9956 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo, 9957 pgbd->rx_bd_len, pgbd->rx_bd_flags); 9958 } 9959 9960 /****************************************************************************/ 9961 /* Prints out a l2_fhdr structure. */ 9962 /* */ 9963 /* Returns: */ 9964 /* Nothing. */ 9965 /****************************************************************************/ 9966 static __attribute__ ((noinline)) void 9967 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 9968 { 9969 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, " 9970 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, " 9971 "tcp_udp_xsum = 0x%04X\n", idx, 9972 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB, 9973 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, 9974 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); 9975 } 9976 9977 /****************************************************************************/ 9978 /* Prints out context memory info. (Only useful for CID 0 to 16.) */ 9979 /* */ 9980 /* Returns: */ 9981 /* Nothing. */ 9982 /****************************************************************************/ 9983 static __attribute__ ((noinline)) void 9984 bce_dump_ctx(struct bce_softc *sc, u16 cid) 9985 { 9986 if (cid > TX_CID) { 9987 BCE_PRINTF(" Unknown CID\n"); 9988 return; 9989 } 9990 9991 BCE_PRINTF( 9992 "----------------------------" 9993 " CTX Data " 9994 "----------------------------\n"); 9995 9996 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid); 9997 9998 if (cid == RX_CID) { 9999 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx " 10000 "producer index\n", 10001 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX)); 10002 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host " 10003 "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 10004 BCE_L2CTX_RX_HOST_BSEQ)); 10005 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n", 10006 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ)); 10007 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer " 10008 "descriptor address\n", 10009 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI)); 10010 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer " 10011 "descriptor address\n", 10012 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO)); 10013 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer " 10014 "index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10015 BCE_L2CTX_RX_NX_BDIDX)); 10016 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page " 10017 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10018 BCE_L2CTX_RX_HOST_PG_BDIDX)); 10019 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page " 10020 "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid), 10021 BCE_L2CTX_RX_PG_BUF_SIZE)); 10022 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page " 10023 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 10024 BCE_L2CTX_RX_NX_PG_BDHADDR_HI)); 10025 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page " 10026 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 10027 BCE_L2CTX_RX_NX_PG_BDHADDR_LO)); 10028 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page " 10029 "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10030 BCE_L2CTX_RX_NX_PG_BDIDX)); 10031 } else if (cid == TX_CID) { 10032 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10033 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n", 10034 CTX_RD(sc, GET_CID_ADDR(cid), 10035 BCE_L2CTX_TX_TYPE_XI)); 10036 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx " 10037 "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid), 10038 BCE_L2CTX_TX_CMD_TYPE_XI)); 10039 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) " 10040 "h/w buffer descriptor address\n", 10041 CTX_RD(sc, GET_CID_ADDR(cid), 10042 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI)); 10043 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) " 10044 "h/w buffer descriptor address\n", 10045 CTX_RD(sc, GET_CID_ADDR(cid), 10046 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI)); 10047 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) " 10048 "host producer index\n", 10049 CTX_RD(sc, GET_CID_ADDR(cid), 10050 BCE_L2CTX_TX_HOST_BIDX_XI)); 10051 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) " 10052 "host byte sequence\n", 10053 CTX_RD(sc, GET_CID_ADDR(cid), 10054 BCE_L2CTX_TX_HOST_BSEQ_XI)); 10055 } else { 10056 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n", 10057 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE)); 10058 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n", 10059 CTX_RD(sc, GET_CID_ADDR(cid), 10060 BCE_L2CTX_TX_CMD_TYPE)); 10061 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) " 10062 "h/w buffer descriptor address\n", 10063 CTX_RD(sc, GET_CID_ADDR(cid), 10064 BCE_L2CTX_TX_TBDR_BHADDR_HI)); 10065 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) " 10066 "h/w buffer descriptor address\n", 10067 CTX_RD(sc, GET_CID_ADDR(cid), 10068 BCE_L2CTX_TX_TBDR_BHADDR_LO)); 10069 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host " 10070 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10071 BCE_L2CTX_TX_HOST_BIDX)); 10072 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte " 10073 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 10074 BCE_L2CTX_TX_HOST_BSEQ)); 10075 } 10076 } 10077 10078 BCE_PRINTF( 10079 "----------------------------" 10080 " Raw CTX " 10081 "----------------------------\n"); 10082 10083 for (int i = 0x0; i < 0x300; i += 0x10) { 10084 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, 10085 CTX_RD(sc, GET_CID_ADDR(cid), i), 10086 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4), 10087 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8), 10088 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc)); 10089 } 10090 10091 BCE_PRINTF( 10092 "----------------------------" 10093 "----------------" 10094 "----------------------------\n"); 10095 } 10096 10097 /****************************************************************************/ 10098 /* Prints out the FTQ data. */ 10099 /* */ 10100 /* Returns: */ 10101 /* Nothing. */ 10102 /****************************************************************************/ 10103 static __attribute__ ((noinline)) void 10104 bce_dump_ftqs(struct bce_softc *sc) 10105 { 10106 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val; 10107 10108 BCE_PRINTF( 10109 "----------------------------" 10110 " FTQ Data " 10111 "----------------------------\n"); 10112 10113 BCE_PRINTF(" FTQ Command Control Depth_Now " 10114 "Max_Depth Valid_Cnt \n"); 10115 BCE_PRINTF(" ------- ---------- ---------- ---------- " 10116 "---------- ----------\n"); 10117 10118 /* Setup the generic statistic counters for the FTQ valid count. */ 10119 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) | 10120 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) | 10121 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) | 10122 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT); 10123 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10124 10125 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) | 10126 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) | 10127 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) | 10128 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT); 10129 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val); 10130 10131 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) | 10132 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) | 10133 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) | 10134 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT); 10135 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val); 10136 10137 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) | 10138 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) | 10139 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) | 10140 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT); 10141 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val); 10142 10143 /* Input queue to the Receive Lookup state machine */ 10144 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD); 10145 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL); 10146 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22; 10147 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12; 10148 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10149 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10150 cmd, ctl, cur_depth, max_depth, valid_cnt); 10151 10152 /* Input queue to the Receive Processor */ 10153 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD); 10154 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL); 10155 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22; 10156 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12; 10157 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10158 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10159 cmd, ctl, cur_depth, max_depth, valid_cnt); 10160 10161 /* Input queue to the Recevie Processor */ 10162 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD); 10163 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL); 10164 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22; 10165 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12; 10166 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10167 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10168 cmd, ctl, cur_depth, max_depth, valid_cnt); 10169 10170 /* Input queue to the Receive Virtual to Physical state machine */ 10171 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD); 10172 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL); 10173 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22; 10174 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12; 10175 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10176 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10177 cmd, ctl, cur_depth, max_depth, valid_cnt); 10178 10179 /* Input queue to the Recevie Virtual to Physical state machine */ 10180 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD); 10181 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL); 10182 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22; 10183 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12; 10184 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4); 10185 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10186 cmd, ctl, cur_depth, max_depth, valid_cnt); 10187 10188 /* Input queue to the Receive Virtual to Physical state machine */ 10189 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD); 10190 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL); 10191 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22; 10192 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12; 10193 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5); 10194 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10195 cmd, ctl, cur_depth, max_depth, valid_cnt); 10196 10197 /* Input queue to the Receive DMA state machine */ 10198 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD); 10199 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL); 10200 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10201 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10202 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6); 10203 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10204 cmd, ctl, cur_depth, max_depth, valid_cnt); 10205 10206 /* Input queue to the Transmit Scheduler state machine */ 10207 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD); 10208 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL); 10209 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22; 10210 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12; 10211 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7); 10212 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10213 cmd, ctl, cur_depth, max_depth, valid_cnt); 10214 10215 /* Input queue to the Transmit Buffer Descriptor state machine */ 10216 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD); 10217 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL); 10218 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22; 10219 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12; 10220 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8); 10221 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10222 cmd, ctl, cur_depth, max_depth, valid_cnt); 10223 10224 /* Input queue to the Transmit Processor */ 10225 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD); 10226 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL); 10227 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22; 10228 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12; 10229 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9); 10230 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10231 cmd, ctl, cur_depth, max_depth, valid_cnt); 10232 10233 /* Input queue to the Transmit DMA state machine */ 10234 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD); 10235 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL); 10236 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10237 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10238 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10); 10239 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10240 cmd, ctl, cur_depth, max_depth, valid_cnt); 10241 10242 /* Input queue to the Transmit Patch-Up Processor */ 10243 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD); 10244 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL); 10245 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22; 10246 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12; 10247 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11); 10248 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10249 cmd, ctl, cur_depth, max_depth, valid_cnt); 10250 10251 /* Input queue to the Transmit Assembler state machine */ 10252 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD); 10253 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL); 10254 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22; 10255 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12; 10256 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12); 10257 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10258 cmd, ctl, cur_depth, max_depth, valid_cnt); 10259 10260 /* Input queue to the Completion Processor */ 10261 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD); 10262 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL); 10263 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22; 10264 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12; 10265 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13); 10266 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10267 cmd, ctl, cur_depth, max_depth, valid_cnt); 10268 10269 /* Input queue to the Completion Processor */ 10270 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD); 10271 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL); 10272 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22; 10273 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12; 10274 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14); 10275 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10276 cmd, ctl, cur_depth, max_depth, valid_cnt); 10277 10278 /* Input queue to the Completion Processor */ 10279 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD); 10280 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL); 10281 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22; 10282 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12; 10283 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15); 10284 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10285 cmd, ctl, cur_depth, max_depth, valid_cnt); 10286 10287 /* Setup the generic statistic counters for the FTQ valid count. */ 10288 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) | 10289 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) | 10290 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT); 10291 10292 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 10293 val = val | 10294 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 10295 24); 10296 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10297 10298 /* Input queue to the Management Control Processor */ 10299 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD); 10300 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL); 10301 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10302 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10303 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10304 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10305 cmd, ctl, cur_depth, max_depth, valid_cnt); 10306 10307 /* Input queue to the Command Processor */ 10308 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD); 10309 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL); 10310 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10311 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10312 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10313 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10314 cmd, ctl, cur_depth, max_depth, valid_cnt); 10315 10316 /* Input queue to the Completion Scheduler state machine */ 10317 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD); 10318 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL); 10319 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22; 10320 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12; 10321 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10322 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10323 cmd, ctl, cur_depth, max_depth, valid_cnt); 10324 10325 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10326 /* Input queue to the RV2P Command Scheduler */ 10327 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD); 10328 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL); 10329 cur_depth = (ctl & 0xFFC00000) >> 22; 10330 max_depth = (ctl & 0x003FF000) >> 12; 10331 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10332 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10333 cmd, ctl, cur_depth, max_depth, valid_cnt); 10334 } 10335 10336 BCE_PRINTF( 10337 "----------------------------" 10338 "----------------" 10339 "----------------------------\n"); 10340 } 10341 10342 /****************************************************************************/ 10343 /* Prints out the TX chain. */ 10344 /* */ 10345 /* Returns: */ 10346 /* Nothing. */ 10347 /****************************************************************************/ 10348 static __attribute__ ((noinline)) void 10349 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count) 10350 { 10351 struct tx_bd *txbd; 10352 10353 /* First some info about the tx_bd chain structure. */ 10354 BCE_PRINTF( 10355 "----------------------------" 10356 " tx_bd chain " 10357 "----------------------------\n"); 10358 10359 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 10360 (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages); 10361 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 10362 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 10363 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC); 10364 10365 BCE_PRINTF( 10366 "----------------------------" 10367 " tx_bd data " 10368 "----------------------------\n"); 10369 10370 /* Now print out a decoded list of TX buffer descriptors. */ 10371 for (int i = 0; i < count; i++) { 10372 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 10373 bce_dump_txbd(sc, tx_prod, txbd); 10374 tx_prod++; 10375 } 10376 10377 BCE_PRINTF( 10378 "----------------------------" 10379 "----------------" 10380 "----------------------------\n"); 10381 } 10382 10383 /****************************************************************************/ 10384 /* Prints out the RX chain. */ 10385 /* */ 10386 /* Returns: */ 10387 /* Nothing. */ 10388 /****************************************************************************/ 10389 static __attribute__ ((noinline)) void 10390 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count) 10391 { 10392 struct rx_bd *rxbd; 10393 10394 /* First some info about the rx_bd chain structure. */ 10395 BCE_PRINTF( 10396 "----------------------------" 10397 " rx_bd chain " 10398 "----------------------------\n"); 10399 10400 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 10401 (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages); 10402 10403 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10404 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 10405 10406 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC); 10407 10408 BCE_PRINTF( 10409 "----------------------------" 10410 " rx_bd data " 10411 "----------------------------\n"); 10412 10413 /* Now print out the rx_bd's themselves. */ 10414 for (int i = 0; i < count; i++) { 10415 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 10416 bce_dump_rxbd(sc, rx_prod, rxbd); 10417 rx_prod = RX_CHAIN_IDX(rx_prod + 1); 10418 } 10419 10420 BCE_PRINTF( 10421 "----------------------------" 10422 "----------------" 10423 "----------------------------\n"); 10424 } 10425 10426 /****************************************************************************/ 10427 /* Prints out the page chain. */ 10428 /* */ 10429 /* Returns: */ 10430 /* Nothing. */ 10431 /****************************************************************************/ 10432 static __attribute__ ((noinline)) void 10433 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count) 10434 { 10435 struct rx_bd *pgbd; 10436 10437 /* First some info about the page chain structure. */ 10438 BCE_PRINTF( 10439 "----------------------------" 10440 " page chain " 10441 "----------------------------\n"); 10442 10443 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n", 10444 (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages); 10445 10446 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10447 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE); 10448 10449 BCE_PRINTF("total pg_bd = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC); 10450 10451 BCE_PRINTF( 10452 "----------------------------" 10453 " page data " 10454 "----------------------------\n"); 10455 10456 /* Now print out the rx_bd's themselves. */ 10457 for (int i = 0; i < count; i++) { 10458 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)]; 10459 bce_dump_pgbd(sc, pg_prod, pgbd); 10460 pg_prod = PG_CHAIN_IDX(pg_prod + 1); 10461 } 10462 10463 BCE_PRINTF( 10464 "----------------------------" 10465 "----------------" 10466 "----------------------------\n"); 10467 } 10468 10469 #define BCE_PRINT_RX_CONS(arg) \ 10470 if (sblk->status_rx_quick_consumer_index##arg) \ 10471 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \ 10472 sblk->status_rx_quick_consumer_index##arg, (u16) \ 10473 RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \ 10474 arg); 10475 10476 #define BCE_PRINT_TX_CONS(arg) \ 10477 if (sblk->status_tx_quick_consumer_index##arg) \ 10478 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \ 10479 sblk->status_tx_quick_consumer_index##arg, (u16) \ 10480 TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \ 10481 arg); 10482 10483 /****************************************************************************/ 10484 /* Prints out the status block from host memory. */ 10485 /* */ 10486 /* Returns: */ 10487 /* Nothing. */ 10488 /****************************************************************************/ 10489 static __attribute__ ((noinline)) void 10490 bce_dump_status_block(struct bce_softc *sc) 10491 { 10492 struct status_block *sblk; 10493 10494 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD); 10495 10496 sblk = sc->status_block; 10497 10498 BCE_PRINTF( 10499 "----------------------------" 10500 " Status Block " 10501 "----------------------------\n"); 10502 10503 /* Theses indices are used for normal L2 drivers. */ 10504 BCE_PRINTF(" 0x%08X - attn_bits\n", 10505 sblk->status_attn_bits); 10506 10507 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 10508 sblk->status_attn_bits_ack); 10509 10510 BCE_PRINT_RX_CONS(0); 10511 BCE_PRINT_TX_CONS(0) 10512 10513 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 10514 10515 /* Theses indices are not used for normal L2 drivers. */ 10516 BCE_PRINT_RX_CONS(1); BCE_PRINT_RX_CONS(2); BCE_PRINT_RX_CONS(3); 10517 BCE_PRINT_RX_CONS(4); BCE_PRINT_RX_CONS(5); BCE_PRINT_RX_CONS(6); 10518 BCE_PRINT_RX_CONS(7); BCE_PRINT_RX_CONS(8); BCE_PRINT_RX_CONS(9); 10519 BCE_PRINT_RX_CONS(10); BCE_PRINT_RX_CONS(11); BCE_PRINT_RX_CONS(12); 10520 BCE_PRINT_RX_CONS(13); BCE_PRINT_RX_CONS(14); BCE_PRINT_RX_CONS(15); 10521 10522 BCE_PRINT_TX_CONS(1); BCE_PRINT_TX_CONS(2); BCE_PRINT_TX_CONS(3); 10523 10524 if (sblk->status_completion_producer_index || 10525 sblk->status_cmd_consumer_index) 10526 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 10527 sblk->status_completion_producer_index, 10528 sblk->status_cmd_consumer_index); 10529 10530 BCE_PRINTF( 10531 "----------------------------" 10532 "----------------" 10533 "----------------------------\n"); 10534 } 10535 10536 #define BCE_PRINT_64BIT_STAT(arg) \ 10537 if (sblk->arg##_lo || sblk->arg##_hi) \ 10538 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \ 10539 sblk->arg##_lo, #arg); 10540 10541 #define BCE_PRINT_32BIT_STAT(arg) \ 10542 if (sblk->arg) \ 10543 BCE_PRINTF(" 0x%08X : %s\n", \ 10544 sblk->arg, #arg); 10545 10546 /****************************************************************************/ 10547 /* Prints out the statistics block from host memory. */ 10548 /* */ 10549 /* Returns: */ 10550 /* Nothing. */ 10551 /****************************************************************************/ 10552 static __attribute__ ((noinline)) void 10553 bce_dump_stats_block(struct bce_softc *sc) 10554 { 10555 struct statistics_block *sblk; 10556 10557 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD); 10558 10559 sblk = sc->stats_block; 10560 10561 BCE_PRINTF( 10562 "---------------" 10563 " Stats Block (All Stats Not Shown Are 0) " 10564 "---------------\n"); 10565 10566 BCE_PRINT_64BIT_STAT(stat_IfHCInOctets); 10567 BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets); 10568 BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets); 10569 BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets); 10570 BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts); 10571 BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts); 10572 BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts); 10573 BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts); 10574 BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts); 10575 BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts); 10576 BCE_PRINT_32BIT_STAT( 10577 stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 10578 BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors); 10579 BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors); 10580 BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors); 10581 BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames); 10582 BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames); 10583 BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions); 10584 BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions); 10585 BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions); 10586 BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions); 10587 BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments); 10588 BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers); 10589 BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts); 10590 BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts); 10591 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets); 10592 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets); 10593 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets); 10594 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets); 10595 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets); 10596 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets); 10597 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets); 10598 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets); 10599 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets); 10600 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets); 10601 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets); 10602 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets); 10603 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets); 10604 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets); 10605 BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived); 10606 BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived); 10607 BCE_PRINT_32BIT_STAT(stat_OutXonSent); 10608 BCE_PRINT_32BIT_STAT(stat_OutXoffSent); 10609 BCE_PRINT_32BIT_STAT(stat_FlowControlDone); 10610 BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived); 10611 BCE_PRINT_32BIT_STAT(stat_XoffStateEntered); 10612 BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards); 10613 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards); 10614 BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards); 10615 BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards); 10616 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit); 10617 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards); 10618 BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards); 10619 BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards); 10620 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit); 10621 10622 BCE_PRINTF( 10623 "----------------------------" 10624 "----------------" 10625 "----------------------------\n"); 10626 } 10627 10628 /****************************************************************************/ 10629 /* Prints out a summary of the driver state. */ 10630 /* */ 10631 /* Returns: */ 10632 /* Nothing. */ 10633 /****************************************************************************/ 10634 static __attribute__ ((noinline)) void 10635 bce_dump_driver_state(struct bce_softc *sc) 10636 { 10637 u32 val_hi, val_lo; 10638 10639 BCE_PRINTF( 10640 "-----------------------------" 10641 " Driver State " 10642 "-----------------------------\n"); 10643 10644 val_hi = BCE_ADDR_HI(sc); 10645 val_lo = BCE_ADDR_LO(sc); 10646 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual " 10647 "address\n", val_hi, val_lo); 10648 10649 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 10650 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 10651 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual " 10652 "address\n", val_hi, val_lo); 10653 10654 val_hi = BCE_ADDR_HI(sc->status_block); 10655 val_lo = BCE_ADDR_LO(sc->status_block); 10656 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block " 10657 "virtual address\n", val_hi, val_lo); 10658 10659 val_hi = BCE_ADDR_HI(sc->stats_block); 10660 val_lo = BCE_ADDR_LO(sc->stats_block); 10661 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block " 10662 "virtual address\n", val_hi, val_lo); 10663 10664 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 10665 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 10666 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain " 10667 "virtual adddress\n", val_hi, val_lo); 10668 10669 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 10670 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 10671 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain " 10672 "virtual address\n", val_hi, val_lo); 10673 10674 if (bce_hdr_split == TRUE) { 10675 val_hi = BCE_ADDR_HI(sc->pg_bd_chain); 10676 val_lo = BCE_ADDR_LO(sc->pg_bd_chain); 10677 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain " 10678 "virtual address\n", val_hi, val_lo); 10679 } 10680 10681 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 10682 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 10683 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain " 10684 "virtual address\n", val_hi, val_lo); 10685 10686 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 10687 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 10688 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain " 10689 "virtual address\n", val_hi, val_lo); 10690 10691 if (bce_hdr_split == TRUE) { 10692 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr); 10693 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr); 10694 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain " 10695 "virtual address\n", val_hi, val_lo); 10696 } 10697 10698 BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) " 10699 "h/w intrs\n", 10700 (long long unsigned int) sc->interrupts_generated); 10701 10702 BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) " 10703 "rx interrupts handled\n", 10704 (long long unsigned int) sc->interrupts_rx); 10705 10706 BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) " 10707 "tx interrupts handled\n", 10708 (long long unsigned int) sc->interrupts_tx); 10709 10710 BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) " 10711 "phy interrupts handled\n", 10712 (long long unsigned int) sc->phy_interrupts); 10713 10714 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) " 10715 "status block index\n", sc->last_status_idx); 10716 10717 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer " 10718 "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 10719 10720 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer " 10721 "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 10722 10723 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer " 10724 "byte seq index\n", sc->tx_prod_bseq); 10725 10726 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx " 10727 "mbufs allocated\n", sc->debug_tx_mbuf_alloc); 10728 10729 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used " 10730 "tx_bd's\n", sc->used_tx_bd); 10731 10732 BCE_PRINTF(" 0x%04X/0x%04X - (sc->tx_hi_watermark)/" 10733 "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd); 10734 10735 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer " 10736 "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 10737 10738 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer " 10739 "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 10740 10741 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer " 10742 "byte seq index\n", sc->rx_prod_bseq); 10743 10744 BCE_PRINTF(" 0x%04X/0x%04X - (sc->rx_low_watermark)/" 10745 "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd); 10746 10747 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx " 10748 "mbufs allocated\n", sc->debug_rx_mbuf_alloc); 10749 10750 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free " 10751 "rx_bd's\n", sc->free_rx_bd); 10752 10753 if (bce_hdr_split == TRUE) { 10754 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer " 10755 "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod)); 10756 10757 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer " 10758 "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons)); 10759 10760 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page " 10761 "mbufs allocated\n", sc->debug_pg_mbuf_alloc); 10762 } 10763 10764 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page " 10765 "rx_bd's\n", sc->free_pg_bd); 10766 10767 BCE_PRINTF(" 0x%04X/0x%04X - (sc->pg_low_watermark)/" 10768 "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd); 10769 10770 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) " 10771 "mbuf alloc failures\n", sc->mbuf_alloc_failed_count); 10772 10773 BCE_PRINTF(" 0x%08X - (sc->bce_flags) " 10774 "bce mac flags\n", sc->bce_flags); 10775 10776 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) " 10777 "bce phy flags\n", sc->bce_phy_flags); 10778 10779 BCE_PRINTF( 10780 "----------------------------" 10781 "----------------" 10782 "----------------------------\n"); 10783 } 10784 10785 /****************************************************************************/ 10786 /* Prints out the hardware state through a summary of important register, */ 10787 /* followed by a complete register dump. */ 10788 /* */ 10789 /* Returns: */ 10790 /* Nothing. */ 10791 /****************************************************************************/ 10792 static __attribute__ ((noinline)) void 10793 bce_dump_hw_state(struct bce_softc *sc) 10794 { 10795 u32 val; 10796 10797 BCE_PRINTF( 10798 "----------------------------" 10799 " Hardware State " 10800 "----------------------------\n"); 10801 10802 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10803 10804 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 10805 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 10806 val, BCE_MISC_ENABLE_STATUS_BITS); 10807 10808 val = REG_RD(sc, BCE_DMA_STATUS); 10809 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", 10810 val, BCE_DMA_STATUS); 10811 10812 val = REG_RD(sc, BCE_CTX_STATUS); 10813 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", 10814 val, BCE_CTX_STATUS); 10815 10816 val = REG_RD(sc, BCE_EMAC_STATUS); 10817 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", 10818 val, BCE_EMAC_STATUS); 10819 10820 val = REG_RD(sc, BCE_RPM_STATUS); 10821 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", 10822 val, BCE_RPM_STATUS); 10823 10824 /* ToDo: Create a #define for this constant. */ 10825 val = REG_RD(sc, 0x2004); 10826 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", 10827 val, 0x2004); 10828 10829 val = REG_RD(sc, BCE_RV2P_STATUS); 10830 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", 10831 val, BCE_RV2P_STATUS); 10832 10833 /* ToDo: Create a #define for this constant. */ 10834 val = REG_RD(sc, 0x2c04); 10835 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", 10836 val, 0x2c04); 10837 10838 val = REG_RD(sc, BCE_TBDR_STATUS); 10839 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", 10840 val, BCE_TBDR_STATUS); 10841 10842 val = REG_RD(sc, BCE_TDMA_STATUS); 10843 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", 10844 val, BCE_TDMA_STATUS); 10845 10846 val = REG_RD(sc, BCE_HC_STATUS); 10847 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", 10848 val, BCE_HC_STATUS); 10849 10850 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 10851 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 10852 val, BCE_TXP_CPU_STATE); 10853 10854 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 10855 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 10856 val, BCE_TPAT_CPU_STATE); 10857 10858 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 10859 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 10860 val, BCE_RXP_CPU_STATE); 10861 10862 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 10863 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 10864 val, BCE_COM_CPU_STATE); 10865 10866 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 10867 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", 10868 val, BCE_MCP_CPU_STATE); 10869 10870 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 10871 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 10872 val, BCE_CP_CPU_STATE); 10873 10874 BCE_PRINTF( 10875 "----------------------------" 10876 "----------------" 10877 "----------------------------\n"); 10878 10879 BCE_PRINTF( 10880 "----------------------------" 10881 " Register Dump " 10882 "----------------------------\n"); 10883 10884 for (int i = 0x400; i < 0x8000; i += 0x10) { 10885 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10886 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10887 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10888 } 10889 10890 BCE_PRINTF( 10891 "----------------------------" 10892 "----------------" 10893 "----------------------------\n"); 10894 } 10895 10896 /****************************************************************************/ 10897 /* Prints out the contentst of shared memory which is used for host driver */ 10898 /* to bootcode firmware communication. */ 10899 /* */ 10900 /* Returns: */ 10901 /* Nothing. */ 10902 /****************************************************************************/ 10903 static __attribute__ ((noinline)) void 10904 bce_dump_shmem_state(struct bce_softc *sc) 10905 { 10906 BCE_PRINTF( 10907 "----------------------------" 10908 " Hardware State " 10909 "----------------------------\n"); 10910 10911 BCE_PRINTF("0x%08X - Shared memory base address\n", 10912 sc->bce_shmem_base); 10913 BCE_PRINTF("%s - bootcode version\n", 10914 sc->bce_bc_ver); 10915 10916 BCE_PRINTF( 10917 "----------------------------" 10918 " Shared Mem " 10919 "----------------------------\n"); 10920 10921 for (int i = 0x0; i < 0x200; i += 0x10) { 10922 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10923 i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4), 10924 bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC)); 10925 } 10926 10927 BCE_PRINTF( 10928 "----------------------------" 10929 "----------------" 10930 "----------------------------\n"); 10931 } 10932 10933 /****************************************************************************/ 10934 /* Prints out the mailbox queue registers. */ 10935 /* */ 10936 /* Returns: */ 10937 /* Nothing. */ 10938 /****************************************************************************/ 10939 static __attribute__ ((noinline)) void 10940 bce_dump_mq_regs(struct bce_softc *sc) 10941 { 10942 BCE_PRINTF( 10943 "----------------------------" 10944 " MQ Regs " 10945 "----------------------------\n"); 10946 10947 BCE_PRINTF( 10948 "----------------------------" 10949 "----------------" 10950 "----------------------------\n"); 10951 10952 for (int i = 0x3c00; i < 0x4000; i += 0x10) { 10953 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10954 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10955 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10956 } 10957 10958 BCE_PRINTF( 10959 "----------------------------" 10960 "----------------" 10961 "----------------------------\n"); 10962 } 10963 10964 /****************************************************************************/ 10965 /* Prints out the bootcode state. */ 10966 /* */ 10967 /* Returns: */ 10968 /* Nothing. */ 10969 /****************************************************************************/ 10970 static __attribute__ ((noinline)) void 10971 bce_dump_bc_state(struct bce_softc *sc) 10972 { 10973 u32 val; 10974 10975 BCE_PRINTF( 10976 "----------------------------" 10977 " Bootcode State " 10978 "----------------------------\n"); 10979 10980 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10981 10982 val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE); 10983 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 10984 val, BCE_BC_RESET_TYPE); 10985 10986 val = bce_shmem_rd(sc, BCE_BC_STATE); 10987 BCE_PRINTF("0x%08X - (0x%06X) state\n", 10988 val, BCE_BC_STATE); 10989 10990 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 10991 BCE_PRINTF("0x%08X - (0x%06X) condition\n", 10992 val, BCE_BC_STATE_CONDITION); 10993 10994 val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD); 10995 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 10996 val, BCE_BC_STATE_DEBUG_CMD); 10997 10998 BCE_PRINTF( 10999 "----------------------------" 11000 "----------------" 11001 "----------------------------\n"); 11002 } 11003 11004 /****************************************************************************/ 11005 /* Prints out the TXP processor state. */ 11006 /* */ 11007 /* Returns: */ 11008 /* Nothing. */ 11009 /****************************************************************************/ 11010 static __attribute__ ((noinline)) void 11011 bce_dump_txp_state(struct bce_softc *sc, int regs) 11012 { 11013 u32 val; 11014 u32 fw_version[3]; 11015 11016 BCE_PRINTF( 11017 "----------------------------" 11018 " TXP State " 11019 "----------------------------\n"); 11020 11021 for (int i = 0; i < 3; i++) 11022 fw_version[i] = htonl(REG_RD_IND(sc, 11023 (BCE_TXP_SCRATCH + 0x10 + i * 4))); 11024 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11025 11026 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 11027 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", 11028 val, BCE_TXP_CPU_MODE); 11029 11030 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 11031 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 11032 val, BCE_TXP_CPU_STATE); 11033 11034 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 11035 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", 11036 val, BCE_TXP_CPU_EVENT_MASK); 11037 11038 if (regs) { 11039 BCE_PRINTF( 11040 "----------------------------" 11041 " Register Dump " 11042 "----------------------------\n"); 11043 11044 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 11045 /* Skip the big blank spaces */ 11046 if (i < 0x454000 && i > 0x5ffff) 11047 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11048 "0x%08X 0x%08X\n", i, 11049 REG_RD_IND(sc, i), 11050 REG_RD_IND(sc, i + 0x4), 11051 REG_RD_IND(sc, i + 0x8), 11052 REG_RD_IND(sc, i + 0xC)); 11053 } 11054 } 11055 11056 BCE_PRINTF( 11057 "----------------------------" 11058 "----------------" 11059 "----------------------------\n"); 11060 } 11061 11062 /****************************************************************************/ 11063 /* Prints out the RXP processor state. */ 11064 /* */ 11065 /* Returns: */ 11066 /* Nothing. */ 11067 /****************************************************************************/ 11068 static __attribute__ ((noinline)) void 11069 bce_dump_rxp_state(struct bce_softc *sc, int regs) 11070 { 11071 u32 val; 11072 u32 fw_version[3]; 11073 11074 BCE_PRINTF( 11075 "----------------------------" 11076 " RXP State " 11077 "----------------------------\n"); 11078 11079 for (int i = 0; i < 3; i++) 11080 fw_version[i] = htonl(REG_RD_IND(sc, 11081 (BCE_RXP_SCRATCH + 0x10 + i * 4))); 11082 11083 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11084 11085 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 11086 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", 11087 val, BCE_RXP_CPU_MODE); 11088 11089 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 11090 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 11091 val, BCE_RXP_CPU_STATE); 11092 11093 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 11094 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", 11095 val, BCE_RXP_CPU_EVENT_MASK); 11096 11097 if (regs) { 11098 BCE_PRINTF( 11099 "----------------------------" 11100 " Register Dump " 11101 "----------------------------\n"); 11102 11103 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 11104 /* Skip the big blank sapces */ 11105 if (i < 0xc5400 && i > 0xdffff) 11106 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11107 "0x%08X 0x%08X\n", i, 11108 REG_RD_IND(sc, i), 11109 REG_RD_IND(sc, i + 0x4), 11110 REG_RD_IND(sc, i + 0x8), 11111 REG_RD_IND(sc, i + 0xC)); 11112 } 11113 } 11114 11115 BCE_PRINTF( 11116 "----------------------------" 11117 "----------------" 11118 "----------------------------\n"); 11119 } 11120 11121 /****************************************************************************/ 11122 /* Prints out the TPAT processor state. */ 11123 /* */ 11124 /* Returns: */ 11125 /* Nothing. */ 11126 /****************************************************************************/ 11127 static __attribute__ ((noinline)) void 11128 bce_dump_tpat_state(struct bce_softc *sc, int regs) 11129 { 11130 u32 val; 11131 u32 fw_version[3]; 11132 11133 BCE_PRINTF( 11134 "----------------------------" 11135 " TPAT State " 11136 "----------------------------\n"); 11137 11138 for (int i = 0; i < 3; i++) 11139 fw_version[i] = htonl(REG_RD_IND(sc, 11140 (BCE_TPAT_SCRATCH + 0x410 + i * 4))); 11141 11142 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11143 11144 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 11145 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", 11146 val, BCE_TPAT_CPU_MODE); 11147 11148 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 11149 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 11150 val, BCE_TPAT_CPU_STATE); 11151 11152 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 11153 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", 11154 val, BCE_TPAT_CPU_EVENT_MASK); 11155 11156 if (regs) { 11157 BCE_PRINTF( 11158 "----------------------------" 11159 " Register Dump " 11160 "----------------------------\n"); 11161 11162 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 11163 /* Skip the big blank spaces */ 11164 if (i < 0x854000 && i > 0x9ffff) 11165 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11166 "0x%08X 0x%08X\n", i, 11167 REG_RD_IND(sc, i), 11168 REG_RD_IND(sc, i + 0x4), 11169 REG_RD_IND(sc, i + 0x8), 11170 REG_RD_IND(sc, i + 0xC)); 11171 } 11172 } 11173 11174 BCE_PRINTF( 11175 "----------------------------" 11176 "----------------" 11177 "----------------------------\n"); 11178 } 11179 11180 /****************************************************************************/ 11181 /* Prints out the Command Procesor (CP) state. */ 11182 /* */ 11183 /* Returns: */ 11184 /* Nothing. */ 11185 /****************************************************************************/ 11186 static __attribute__ ((noinline)) void 11187 bce_dump_cp_state(struct bce_softc *sc, int regs) 11188 { 11189 u32 val; 11190 u32 fw_version[3]; 11191 11192 BCE_PRINTF( 11193 "----------------------------" 11194 " CP State " 11195 "----------------------------\n"); 11196 11197 for (int i = 0; i < 3; i++) 11198 fw_version[i] = htonl(REG_RD_IND(sc, 11199 (BCE_CP_SCRATCH + 0x10 + i * 4))); 11200 11201 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11202 11203 val = REG_RD_IND(sc, BCE_CP_CPU_MODE); 11204 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", 11205 val, BCE_CP_CPU_MODE); 11206 11207 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 11208 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 11209 val, BCE_CP_CPU_STATE); 11210 11211 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK); 11212 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val, 11213 BCE_CP_CPU_EVENT_MASK); 11214 11215 if (regs) { 11216 BCE_PRINTF( 11217 "----------------------------" 11218 " Register Dump " 11219 "----------------------------\n"); 11220 11221 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) { 11222 /* Skip the big blank spaces */ 11223 if (i < 0x185400 && i > 0x19ffff) 11224 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11225 "0x%08X 0x%08X\n", i, 11226 REG_RD_IND(sc, i), 11227 REG_RD_IND(sc, i + 0x4), 11228 REG_RD_IND(sc, i + 0x8), 11229 REG_RD_IND(sc, i + 0xC)); 11230 } 11231 } 11232 11233 BCE_PRINTF( 11234 "----------------------------" 11235 "----------------" 11236 "----------------------------\n"); 11237 } 11238 11239 /****************************************************************************/ 11240 /* Prints out the Completion Procesor (COM) state. */ 11241 /* */ 11242 /* Returns: */ 11243 /* Nothing. */ 11244 /****************************************************************************/ 11245 static __attribute__ ((noinline)) void 11246 bce_dump_com_state(struct bce_softc *sc, int regs) 11247 { 11248 u32 val; 11249 u32 fw_version[4]; 11250 11251 BCE_PRINTF( 11252 "----------------------------" 11253 " COM State " 11254 "----------------------------\n"); 11255 11256 for (int i = 0; i < 3; i++) 11257 fw_version[i] = htonl(REG_RD_IND(sc, 11258 (BCE_COM_SCRATCH + 0x10 + i * 4))); 11259 11260 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11261 11262 val = REG_RD_IND(sc, BCE_COM_CPU_MODE); 11263 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", 11264 val, BCE_COM_CPU_MODE); 11265 11266 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 11267 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 11268 val, BCE_COM_CPU_STATE); 11269 11270 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK); 11271 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val, 11272 BCE_COM_CPU_EVENT_MASK); 11273 11274 if (regs) { 11275 BCE_PRINTF( 11276 "----------------------------" 11277 " Register Dump " 11278 "----------------------------\n"); 11279 11280 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) { 11281 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11282 "0x%08X 0x%08X\n", i, 11283 REG_RD_IND(sc, i), 11284 REG_RD_IND(sc, i + 0x4), 11285 REG_RD_IND(sc, i + 0x8), 11286 REG_RD_IND(sc, i + 0xC)); 11287 } 11288 } 11289 11290 BCE_PRINTF( 11291 "----------------------------" 11292 "----------------" 11293 "----------------------------\n"); 11294 } 11295 11296 /****************************************************************************/ 11297 /* Prints out the Receive Virtual 2 Physical (RV2P) state. */ 11298 /* */ 11299 /* Returns: */ 11300 /* Nothing. */ 11301 /****************************************************************************/ 11302 static __attribute__ ((noinline)) void 11303 bce_dump_rv2p_state(struct bce_softc *sc) 11304 { 11305 u32 val, pc1, pc2, fw_ver_high, fw_ver_low; 11306 11307 BCE_PRINTF( 11308 "----------------------------" 11309 " RV2P State " 11310 "----------------------------\n"); 11311 11312 /* Stall the RV2P processors. */ 11313 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11314 val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2; 11315 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11316 11317 /* Read the firmware version. */ 11318 val = 0x00000001; 11319 REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 11320 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11321 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11322 BCE_RV2P_INSTR_HIGH_HIGH; 11323 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n", 11324 fw_ver_high, fw_ver_low); 11325 11326 val = 0x00000001; 11327 REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 11328 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11329 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11330 BCE_RV2P_INSTR_HIGH_HIGH; 11331 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n", 11332 fw_ver_high, fw_ver_low); 11333 11334 /* Resume the RV2P processors. */ 11335 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11336 val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2); 11337 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11338 11339 /* Fetch the program counter value. */ 11340 val = 0x68007800; 11341 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11342 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11343 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11344 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11345 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1); 11346 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2); 11347 11348 /* Fetch the program counter value again to see if it is advancing. */ 11349 val = 0x68007800; 11350 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11351 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11352 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11353 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11354 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1); 11355 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2); 11356 11357 BCE_PRINTF( 11358 "----------------------------" 11359 "----------------" 11360 "----------------------------\n"); 11361 } 11362 11363 /****************************************************************************/ 11364 /* Prints out the driver state and then enters the debugger. */ 11365 /* */ 11366 /* Returns: */ 11367 /* Nothing. */ 11368 /****************************************************************************/ 11369 static __attribute__ ((noinline)) void 11370 bce_breakpoint(struct bce_softc *sc) 11371 { 11372 11373 /* 11374 * Unreachable code to silence compiler warnings 11375 * about unused functions. 11376 */ 11377 if (0) { 11378 bce_freeze_controller(sc); 11379 bce_unfreeze_controller(sc); 11380 bce_dump_enet(sc, NULL); 11381 bce_dump_txbd(sc, 0, NULL); 11382 bce_dump_rxbd(sc, 0, NULL); 11383 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC); 11384 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 11385 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC); 11386 bce_dump_l2fhdr(sc, 0, NULL); 11387 bce_dump_ctx(sc, RX_CID); 11388 bce_dump_ftqs(sc); 11389 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC); 11390 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC); 11391 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC); 11392 bce_dump_status_block(sc); 11393 bce_dump_stats_block(sc); 11394 bce_dump_driver_state(sc); 11395 bce_dump_hw_state(sc); 11396 bce_dump_bc_state(sc); 11397 bce_dump_txp_state(sc, 0); 11398 bce_dump_rxp_state(sc, 0); 11399 bce_dump_tpat_state(sc, 0); 11400 bce_dump_cp_state(sc, 0); 11401 bce_dump_com_state(sc, 0); 11402 bce_dump_rv2p_state(sc); 11403 bce_dump_pgbd(sc, 0, NULL); 11404 } 11405 11406 bce_dump_status_block(sc); 11407 bce_dump_driver_state(sc); 11408 11409 /* Call the debugger. */ 11410 breakpoint(); 11411 } 11412 #endif
Cache object: e0088769e9d9c23f5df00cd76f42b4be
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