Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/bce/if_bce.c
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1 /*- 2 * Copyright (c) 2006-2010 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written consent. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD: releng/7.4/sys/dev/bce/if_bce.c 215879 2010-11-26 19:48:27Z marius $"); 33 34 /* 35 * The following controllers are supported by this driver: 36 * BCM5706C A2, A3 37 * BCM5706S A2, A3 38 * BCM5708C B1, B2 39 * BCM5708S B1, B2 40 * BCM5709C A1, C0 41 * BCM5709S A1, C0 42 * BCM5716C C0 43 * BCM5716S C0 44 * 45 * The following controllers are not supported by this driver: 46 * BCM5706C A0, A1 (pre-production) 47 * BCM5706S A0, A1 (pre-production) 48 * BCM5708C A0, B0 (pre-production) 49 * BCM5708S A0, B0 (pre-production) 50 * BCM5709C A0 B0, B1, B2 (pre-production) 51 * BCM5709S A0, B0, B1, B2 (pre-production) 52 */ 53 54 #include "opt_bce.h" 55 56 #include <dev/bce/if_bcereg.h> 57 #include <dev/bce/if_bcefw.h> 58 59 /****************************************************************************/ 60 /* BCE Debug Options */ 61 /****************************************************************************/ 62 #ifdef BCE_DEBUG 63 u32 bce_debug = BCE_WARN; 64 65 /* 0 = Never */ 66 /* 1 = 1 in 2,147,483,648 */ 67 /* 256 = 1 in 8,388,608 */ 68 /* 2048 = 1 in 1,048,576 */ 69 /* 65536 = 1 in 32,768 */ 70 /* 1048576 = 1 in 2,048 */ 71 /* 268435456 = 1 in 8 */ 72 /* 536870912 = 1 in 4 */ 73 /* 1073741824 = 1 in 2 */ 74 75 /* Controls how often the l2_fhdr frame error check will fail. */ 76 int l2fhdr_error_sim_control = 0; 77 78 /* Controls how often the unexpected attention check will fail. */ 79 int unexpected_attention_sim_control = 0; 80 81 /* Controls how often to simulate an mbuf allocation failure. */ 82 int mbuf_alloc_failed_sim_control = 0; 83 84 /* Controls how often to simulate a DMA mapping failure. */ 85 int dma_map_addr_failed_sim_control = 0; 86 87 /* Controls how often to simulate a bootcode failure. */ 88 int bootcode_running_failure_sim_control = 0; 89 #endif 90 91 /****************************************************************************/ 92 /* BCE Build Time Options */ 93 /****************************************************************************/ 94 /* #define BCE_NVRAM_WRITE_SUPPORT 1 */ 95 96 97 /****************************************************************************/ 98 /* PCI Device ID Table */ 99 /* */ 100 /* Used by bce_probe() to identify the devices supported by this driver. */ 101 /****************************************************************************/ 102 #define BCE_DEVDESC_MAX 64 103 104 static struct bce_type bce_devs[] = { 105 /* BCM5706C Controllers and OEM boards. */ 106 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 107 "HP NC370T Multifunction Gigabit Server Adapter" }, 108 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 109 "HP NC370i Multifunction Gigabit Server Adapter" }, 110 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070, 111 "HP NC380T PCIe DP Multifunc Gig Server Adapter" }, 112 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709, 113 "HP NC371i Multifunction Gigabit Server Adapter" }, 114 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 115 "Broadcom NetXtreme II BCM5706 1000Base-T" }, 116 117 /* BCM5706S controllers and OEM boards. */ 118 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 119 "HP NC370F Multifunction Gigabit Server Adapter" }, 120 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 121 "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 122 123 /* BCM5708C controllers and OEM boards. */ 124 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037, 125 "HP NC373T PCIe Multifunction Gig Server Adapter" }, 126 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038, 127 "HP NC373i Multifunction Gigabit Server Adapter" }, 128 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045, 129 "HP NC374m PCIe Multifunction Adapter" }, 130 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 131 "Broadcom NetXtreme II BCM5708 1000Base-T" }, 132 133 /* BCM5708S controllers and OEM boards. */ 134 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706, 135 "HP NC373m Multifunction Gigabit Server Adapter" }, 136 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b, 137 "HP NC373i Multifunction Gigabit Server Adapter" }, 138 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d, 139 "HP NC373F PCIe Multifunc Giga Server Adapter" }, 140 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 141 "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 142 143 /* BCM5709C controllers and OEM boards. */ 144 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055, 145 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059, 147 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" }, 148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID, 149 "Broadcom NetXtreme II BCM5709 1000Base-T" }, 150 151 /* BCM5709S controllers and OEM boards. */ 152 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d, 153 "HP NC382m DP 1GbE Multifunction BL-c Adapter" }, 154 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056, 155 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 156 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID, 157 "Broadcom NetXtreme II BCM5709 1000Base-SX" }, 158 159 /* BCM5716 controllers and OEM boards. */ 160 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID, 161 "Broadcom NetXtreme II BCM5716 1000Base-T" }, 162 163 { 0, 0, 0, 0, NULL } 164 }; 165 166 167 /****************************************************************************/ 168 /* Supported Flash NVRAM device data. */ 169 /****************************************************************************/ 170 static struct flash_spec flash_table[] = 171 { 172 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE) 173 #define NONBUFFERED_FLAGS (BCE_NV_WREN) 174 175 /* Slow EEPROM */ 176 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 177 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 178 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 179 "EEPROM - slow"}, 180 /* Expansion entry 0001 */ 181 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 182 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 183 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 184 "Entry 0001"}, 185 /* Saifun SA25F010 (non-buffered flash) */ 186 /* strap, cfg1, & write1 need updates */ 187 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 189 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 190 "Non-buffered flash (128kB)"}, 191 /* Saifun SA25F020 (non-buffered flash) */ 192 /* strap, cfg1, & write1 need updates */ 193 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 194 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 195 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 196 "Non-buffered flash (256kB)"}, 197 /* Expansion entry 0100 */ 198 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 199 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 200 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 201 "Entry 0100"}, 202 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 203 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 204 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 205 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 206 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 207 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 208 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 209 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 210 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 211 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 212 /* Saifun SA25F005 (non-buffered flash) */ 213 /* strap, cfg1, & write1 need updates */ 214 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 215 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 216 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 217 "Non-buffered flash (64kB)"}, 218 /* Fast EEPROM */ 219 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 220 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 221 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 222 "EEPROM - fast"}, 223 /* Expansion entry 1001 */ 224 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 225 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 226 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 227 "Entry 1001"}, 228 /* Expansion entry 1010 */ 229 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 230 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 231 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 232 "Entry 1010"}, 233 /* ATMEL AT45DB011B (buffered flash) */ 234 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 235 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 236 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 237 "Buffered flash (128kB)"}, 238 /* Expansion entry 1100 */ 239 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 240 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 241 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 242 "Entry 1100"}, 243 /* Expansion entry 1101 */ 244 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 245 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 246 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 247 "Entry 1101"}, 248 /* Ateml Expansion entry 1110 */ 249 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 250 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 251 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 252 "Entry 1110 (Atmel)"}, 253 /* ATMEL AT45DB021B (buffered flash) */ 254 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 255 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 256 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 257 "Buffered flash (256kB)"}, 258 }; 259 260 /* 261 * The BCM5709 controllers transparently handle the 262 * differences between Atmel 264 byte pages and all 263 * flash devices which use 256 byte pages, so no 264 * logical-to-physical mapping is required in the 265 * driver. 266 */ 267 static struct flash_spec flash_5709 = { 268 .flags = BCE_NV_BUFFERED, 269 .page_bits = BCM5709_FLASH_PAGE_BITS, 270 .page_size = BCM5709_FLASH_PAGE_SIZE, 271 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 272 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 273 .name = "5709/5716 buffered flash (256kB)", 274 }; 275 276 277 /****************************************************************************/ 278 /* FreeBSD device entry points. */ 279 /****************************************************************************/ 280 static int bce_probe (device_t); 281 static int bce_attach (device_t); 282 static int bce_detach (device_t); 283 static int bce_shutdown (device_t); 284 285 286 /****************************************************************************/ 287 /* BCE Debug Data Structure Dump Routines */ 288 /****************************************************************************/ 289 #ifdef BCE_DEBUG 290 static u32 bce_reg_rd (struct bce_softc *, u32); 291 static void bce_reg_wr (struct bce_softc *, u32, u32); 292 static void bce_reg_wr16 (struct bce_softc *, u32, u16); 293 static u32 bce_ctx_rd (struct bce_softc *, u32, u32); 294 static void bce_dump_enet (struct bce_softc *, struct mbuf *); 295 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 296 static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int); 297 static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int); 298 #ifdef BCE_JUMBO_HDRSPLIT 299 static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int); 300 #endif 301 static void bce_dump_txbd (struct bce_softc *, 302 int, struct tx_bd *); 303 static void bce_dump_rxbd (struct bce_softc *, 304 int, struct rx_bd *); 305 #ifdef BCE_JUMBO_HDRSPLIT 306 static void bce_dump_pgbd (struct bce_softc *, 307 int, struct rx_bd *); 308 #endif 309 static void bce_dump_l2fhdr (struct bce_softc *, 310 int, struct l2_fhdr *); 311 static void bce_dump_ctx (struct bce_softc *, u16); 312 static void bce_dump_ftqs (struct bce_softc *); 313 static void bce_dump_tx_chain (struct bce_softc *, u16, int); 314 static void bce_dump_rx_bd_chain (struct bce_softc *, u16, int); 315 #ifdef BCE_JUMBO_HDRSPLIT 316 static void bce_dump_pg_chain (struct bce_softc *, u16, int); 317 #endif 318 static void bce_dump_status_block (struct bce_softc *); 319 static void bce_dump_stats_block (struct bce_softc *); 320 static void bce_dump_driver_state (struct bce_softc *); 321 static void bce_dump_hw_state (struct bce_softc *); 322 static void bce_dump_mq_regs (struct bce_softc *); 323 static void bce_dump_bc_state (struct bce_softc *); 324 static void bce_dump_txp_state (struct bce_softc *, int); 325 static void bce_dump_rxp_state (struct bce_softc *, int); 326 static void bce_dump_tpat_state (struct bce_softc *, int); 327 static void bce_dump_cp_state (struct bce_softc *, int); 328 static void bce_dump_com_state (struct bce_softc *, int); 329 static void bce_dump_rv2p_state (struct bce_softc *); 330 static void bce_breakpoint (struct bce_softc *); 331 #endif 332 333 334 /****************************************************************************/ 335 /* BCE Register/Memory Access Routines */ 336 /****************************************************************************/ 337 static u32 bce_reg_rd_ind (struct bce_softc *, u32); 338 static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 339 static void bce_shmem_wr (struct bce_softc *, u32, u32); 340 static u32 bce_shmem_rd (struct bce_softc *, u32); 341 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 342 static int bce_miibus_read_reg (device_t, int, int); 343 static int bce_miibus_write_reg (device_t, int, int, int); 344 static void bce_miibus_statchg (device_t); 345 346 347 /****************************************************************************/ 348 /* BCE NVRAM Access Routines */ 349 /****************************************************************************/ 350 static int bce_acquire_nvram_lock (struct bce_softc *); 351 static int bce_release_nvram_lock (struct bce_softc *); 352 static void bce_enable_nvram_access (struct bce_softc *); 353 static void bce_disable_nvram_access (struct bce_softc *); 354 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 355 static int bce_init_nvram (struct bce_softc *); 356 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 357 static int bce_nvram_test (struct bce_softc *); 358 #ifdef BCE_NVRAM_WRITE_SUPPORT 359 static int bce_enable_nvram_write (struct bce_softc *); 360 static void bce_disable_nvram_write (struct bce_softc *); 361 static int bce_nvram_erase_page (struct bce_softc *, u32); 362 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 363 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 364 #endif 365 366 /****************************************************************************/ 367 /* */ 368 /****************************************************************************/ 369 static void bce_get_media (struct bce_softc *); 370 static void bce_init_media (struct bce_softc *); 371 static void bce_dma_map_addr (void *, 372 bus_dma_segment_t *, int, int); 373 static int bce_dma_alloc (device_t); 374 static void bce_dma_free (struct bce_softc *); 375 static void bce_release_resources (struct bce_softc *); 376 377 /****************************************************************************/ 378 /* BCE Firmware Synchronization and Load */ 379 /****************************************************************************/ 380 static int bce_fw_sync (struct bce_softc *, u32); 381 static void bce_load_rv2p_fw (struct bce_softc *, u32 *, u32, u32); 382 static void bce_load_cpu_fw (struct bce_softc *, 383 struct cpu_reg *, struct fw_info *); 384 static void bce_start_cpu (struct bce_softc *, struct cpu_reg *); 385 static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *); 386 static void bce_start_rxp_cpu (struct bce_softc *); 387 static void bce_init_rxp_cpu (struct bce_softc *); 388 static void bce_init_txp_cpu (struct bce_softc *); 389 static void bce_init_tpat_cpu (struct bce_softc *); 390 static void bce_init_cp_cpu (struct bce_softc *); 391 static void bce_init_com_cpu (struct bce_softc *); 392 static void bce_init_cpus (struct bce_softc *); 393 394 static void bce_print_adapter_info (struct bce_softc *); 395 static void bce_probe_pci_caps (device_t, struct bce_softc *); 396 static void bce_stop (struct bce_softc *); 397 static int bce_reset (struct bce_softc *, u32); 398 static int bce_chipinit (struct bce_softc *); 399 static int bce_blockinit (struct bce_softc *); 400 401 static int bce_init_tx_chain (struct bce_softc *); 402 static void bce_free_tx_chain (struct bce_softc *); 403 404 static int bce_get_rx_buf (struct bce_softc *, 405 struct mbuf *, u16 *, u16 *, u32 *); 406 static int bce_init_rx_chain (struct bce_softc *); 407 static void bce_fill_rx_chain (struct bce_softc *); 408 static void bce_free_rx_chain (struct bce_softc *); 409 410 #ifdef BCE_JUMBO_HDRSPLIT 411 static int bce_get_pg_buf (struct bce_softc *, 412 struct mbuf *, u16 *, u16 *); 413 static int bce_init_pg_chain (struct bce_softc *); 414 static void bce_fill_pg_chain (struct bce_softc *); 415 static void bce_free_pg_chain (struct bce_softc *); 416 #endif 417 418 static struct mbuf *bce_tso_setup (struct bce_softc *, 419 struct mbuf **, u16 *); 420 static int bce_tx_encap (struct bce_softc *, struct mbuf **); 421 static void bce_start_locked (struct ifnet *); 422 static void bce_start (struct ifnet *); 423 static int bce_ioctl (struct ifnet *, u_long, caddr_t); 424 static void bce_watchdog (struct bce_softc *); 425 static int bce_ifmedia_upd (struct ifnet *); 426 static int bce_ifmedia_upd_locked (struct ifnet *); 427 static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 428 static void bce_init_locked (struct bce_softc *); 429 static void bce_init (void *); 430 static void bce_mgmt_init_locked (struct bce_softc *sc); 431 432 static int bce_init_ctx (struct bce_softc *); 433 static void bce_get_mac_addr (struct bce_softc *); 434 static void bce_set_mac_addr (struct bce_softc *); 435 static void bce_phy_intr (struct bce_softc *); 436 static inline u16 bce_get_hw_rx_cons (struct bce_softc *); 437 static void bce_rx_intr (struct bce_softc *); 438 static void bce_tx_intr (struct bce_softc *); 439 static void bce_disable_intr (struct bce_softc *); 440 static void bce_enable_intr (struct bce_softc *, int); 441 442 static void bce_intr (void *); 443 static void bce_set_rx_mode (struct bce_softc *); 444 static void bce_stats_update (struct bce_softc *); 445 static void bce_tick (void *); 446 static void bce_pulse (void *); 447 static void bce_add_sysctls (struct bce_softc *); 448 449 450 /****************************************************************************/ 451 /* FreeBSD device dispatch table. */ 452 /****************************************************************************/ 453 static device_method_t bce_methods[] = { 454 /* Device interface (device_if.h) */ 455 DEVMETHOD(device_probe, bce_probe), 456 DEVMETHOD(device_attach, bce_attach), 457 DEVMETHOD(device_detach, bce_detach), 458 DEVMETHOD(device_shutdown, bce_shutdown), 459 /* Supported by device interface but not used here. */ 460 /* DEVMETHOD(device_identify, bce_identify), */ 461 /* DEVMETHOD(device_suspend, bce_suspend), */ 462 /* DEVMETHOD(device_resume, bce_resume), */ 463 /* DEVMETHOD(device_quiesce, bce_quiesce), */ 464 465 /* Bus interface (bus_if.h) */ 466 DEVMETHOD(bus_print_child, bus_generic_print_child), 467 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 468 469 /* MII interface (miibus_if.h) */ 470 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 471 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 472 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 473 /* Supported by MII interface but not used here. */ 474 /* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */ 475 /* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */ 476 477 { 0, 0 } 478 }; 479 480 static driver_t bce_driver = { 481 "bce", 482 bce_methods, 483 sizeof(struct bce_softc) 484 }; 485 486 static devclass_t bce_devclass; 487 488 MODULE_DEPEND(bce, pci, 1, 1, 1); 489 MODULE_DEPEND(bce, ether, 1, 1, 1); 490 MODULE_DEPEND(bce, miibus, 1, 1, 1); 491 492 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0); 493 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0); 494 495 496 /****************************************************************************/ 497 /* Tunable device values */ 498 /****************************************************************************/ 499 SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters"); 500 501 /* Allowable values are TRUE or FALSE */ 502 static int bce_tso_enable = TRUE; 503 TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable); 504 SYSCTL_UINT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 505 "TSO Enable/Disable"); 506 507 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 508 /* ToDo: Add MSI-X support. */ 509 static int bce_msi_enable = 1; 510 TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable); 511 SYSCTL_UINT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 512 "MSI-X|MSI|INTx selector"); 513 514 /* ToDo: Add tunable to enable/disable strict MTU handling. */ 515 /* Currently allows "loose" RX MTU checking (i.e. sets the */ 516 /* H/W RX MTU to the size of the largest receive buffer, or */ 517 /* 2048 bytes). This will cause a UNH failure but is more */ 518 /* desireable from a functional perspective. */ 519 520 521 /****************************************************************************/ 522 /* Device probe function. */ 523 /* */ 524 /* Compares the device to the driver's list of supported devices and */ 525 /* reports back to the OS whether this is the right driver for the device. */ 526 /* */ 527 /* Returns: */ 528 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 529 /****************************************************************************/ 530 static int 531 bce_probe(device_t dev) 532 { 533 struct bce_type *t; 534 struct bce_softc *sc; 535 char *descbuf; 536 u16 vid = 0, did = 0, svid = 0, sdid = 0; 537 538 t = bce_devs; 539 540 sc = device_get_softc(dev); 541 bzero(sc, sizeof(struct bce_softc)); 542 sc->bce_unit = device_get_unit(dev); 543 sc->bce_dev = dev; 544 545 /* Get the data for the device to be probed. */ 546 vid = pci_get_vendor(dev); 547 did = pci_get_device(dev); 548 svid = pci_get_subvendor(dev); 549 sdid = pci_get_subdevice(dev); 550 551 DBPRINT(sc, BCE_EXTREME_LOAD, 552 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 553 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 554 555 /* Look through the list of known devices for a match. */ 556 while(t->bce_name != NULL) { 557 558 if ((vid == t->bce_vid) && (did == t->bce_did) && 559 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 560 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 561 562 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 563 564 if (descbuf == NULL) 565 return(ENOMEM); 566 567 /* Print out the device identity. */ 568 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 569 t->bce_name, (((pci_read_config(dev, 570 PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 571 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 572 573 device_set_desc_copy(dev, descbuf); 574 free(descbuf, M_TEMP); 575 return(BUS_PROBE_DEFAULT); 576 } 577 t++; 578 } 579 580 return(ENXIO); 581 } 582 583 584 /****************************************************************************/ 585 /* PCI Capabilities Probe Function. */ 586 /* */ 587 /* Walks the PCI capabiites list for the device to find what features are */ 588 /* supported. */ 589 /* */ 590 /* Returns: */ 591 /* None. */ 592 /****************************************************************************/ 593 static void 594 bce_print_adapter_info(struct bce_softc *sc) 595 { 596 int i = 0; 597 598 DBENTER(BCE_VERBOSE_LOAD); 599 600 if (bootverbose) { 601 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 602 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 603 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 604 605 606 /* Bus info. */ 607 if (sc->bce_flags & BCE_PCIE_FLAG) { 608 printf("Bus (PCIe x%d, ", sc->link_width); 609 switch (sc->link_speed) { 610 case 1: printf("2.5Gbps); "); break; 611 case 2: printf("5Gbps); "); break; 612 default: printf("Unknown link speed); "); 613 } 614 } else { 615 printf("Bus (PCI%s, %s, %dMHz); ", 616 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 617 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? 618 "32-bit" : "64-bit"), sc->bus_speed_mhz); 619 } 620 621 /* Firmware version and device features. */ 622 printf("B/C (%s); Flags (", sc->bce_bc_ver); 623 624 #ifdef BCE_JUMBO_HDRSPLIT 625 printf("SPLT"); 626 i++; 627 #endif 628 629 if (sc->bce_flags & BCE_USING_MSI_FLAG) { 630 if (i > 0) printf("|"); 631 printf("MSI"); i++; 632 } 633 634 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 635 if (i > 0) printf("|"); 636 printf("MSI-X"); i++; 637 } 638 639 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 640 if (i > 0) printf("|"); 641 printf("2.5G"); i++; 642 } 643 644 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 645 if (i > 0) printf("|"); 646 printf("MFW); MFW (%s)\n", sc->bce_mfw_ver); 647 } else { 648 printf(")\n"); 649 } 650 } 651 652 DBEXIT(BCE_VERBOSE_LOAD); 653 } 654 655 656 /****************************************************************************/ 657 /* PCI Capabilities Probe Function. */ 658 /* */ 659 /* Walks the PCI capabiites list for the device to find what features are */ 660 /* supported. */ 661 /* */ 662 /* Returns: */ 663 /* None. */ 664 /****************************************************************************/ 665 static void 666 bce_probe_pci_caps(device_t dev, struct bce_softc *sc) 667 { 668 u32 reg; 669 670 DBENTER(BCE_VERBOSE_LOAD); 671 672 /* Check if PCI-X capability is enabled. */ 673 if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) { 674 if (reg != 0) 675 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; 676 } 677 678 /* Check if PCIe capability is enabled. */ 679 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 680 if (reg != 0) { 681 u16 link_status = pci_read_config(dev, reg + 0x12, 2); 682 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = " 683 "0x%08X\n", link_status); 684 sc->link_speed = link_status & 0xf; 685 sc->link_width = (link_status >> 4) & 0x3f; 686 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG; 687 sc->bce_flags |= BCE_PCIE_FLAG; 688 } 689 } 690 691 /* Check if MSI capability is enabled. */ 692 if (pci_find_extcap(dev, PCIY_MSI, ®) == 0) { 693 if (reg != 0) 694 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; 695 } 696 697 /* Check if MSI-X capability is enabled. */ 698 if (pci_find_extcap(dev, PCIY_MSIX, ®) == 0) { 699 if (reg != 0) 700 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; 701 } 702 703 DBEXIT(BCE_VERBOSE_LOAD); 704 } 705 706 707 /****************************************************************************/ 708 /* Device attach function. */ 709 /* */ 710 /* Allocates device resources, performs secondary chip identification, */ 711 /* resets and initializes the hardware, and initializes driver instance */ 712 /* variables. */ 713 /* */ 714 /* Returns: */ 715 /* 0 on success, positive value on failure. */ 716 /****************************************************************************/ 717 static int 718 bce_attach(device_t dev) 719 { 720 struct bce_softc *sc; 721 struct ifnet *ifp; 722 u32 val; 723 int error, rid, rc = 0; 724 725 sc = device_get_softc(dev); 726 sc->bce_dev = dev; 727 728 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 729 730 sc->bce_unit = device_get_unit(dev); 731 732 /* Set initial device and PHY flags */ 733 sc->bce_flags = 0; 734 sc->bce_phy_flags = 0; 735 736 pci_enable_busmaster(dev); 737 738 /* Allocate PCI memory resources. */ 739 rid = PCIR_BAR(0); 740 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 741 &rid, RF_ACTIVE | PCI_RF_DENSE); 742 743 if (sc->bce_res_mem == NULL) { 744 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 745 __FILE__, __LINE__); 746 rc = ENXIO; 747 goto bce_attach_fail; 748 } 749 750 /* Get various resource handles. */ 751 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 752 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 753 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 754 755 bce_probe_pci_caps(dev, sc); 756 757 rid = 1; 758 #if 0 759 /* Try allocating MSI-X interrupts. */ 760 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) && 761 (bce_msi_enable >= 2) && 762 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 763 &rid, RF_ACTIVE)) != NULL)) { 764 765 msi_needed = sc->bce_msi_count = 1; 766 767 if (((error = pci_alloc_msix(dev, &sc->bce_msi_count)) != 0) || 768 (sc->bce_msi_count != msi_needed)) { 769 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d," 770 "Received = %d, error = %d\n", __FILE__, __LINE__, 771 msi_needed, sc->bce_msi_count, error); 772 sc->bce_msi_count = 0; 773 pci_release_msi(dev); 774 bus_release_resource(dev, SYS_RES_MEMORY, rid, 775 sc->bce_res_irq); 776 sc->bce_res_irq = NULL; 777 } else { 778 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n", 779 __FUNCTION__); 780 sc->bce_flags |= BCE_USING_MSIX_FLAG; 781 sc->bce_intr = bce_intr; 782 } 783 } 784 #endif 785 786 /* Try allocating a MSI interrupt. */ 787 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) && 788 (bce_msi_enable >= 1) && (sc->bce_msi_count == 0)) { 789 sc->bce_msi_count = 1; 790 if ((error = pci_alloc_msi(dev, &sc->bce_msi_count)) != 0) { 791 BCE_PRINTF("%s(%d): MSI allocation failed! " 792 "error = %d\n", __FILE__, __LINE__, error); 793 sc->bce_msi_count = 0; 794 pci_release_msi(dev); 795 } else { 796 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI " 797 "interrupt.\n", __FUNCTION__); 798 sc->bce_flags |= BCE_USING_MSI_FLAG; 799 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 800 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 801 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG; 802 sc->bce_irq_rid = 1; 803 sc->bce_intr = bce_intr; 804 } 805 } 806 807 /* Try allocating a legacy interrupt. */ 808 if (sc->bce_msi_count == 0) { 809 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n", 810 __FUNCTION__); 811 rid = 0; 812 sc->bce_intr = bce_intr; 813 } 814 815 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 816 &rid, RF_SHAREABLE | RF_ACTIVE); 817 818 sc->bce_irq_rid = rid; 819 820 /* Report any IRQ allocation errors. */ 821 if (sc->bce_res_irq == NULL) { 822 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 823 __FILE__, __LINE__); 824 rc = ENXIO; 825 goto bce_attach_fail; 826 } 827 828 /* Initialize mutex for the current device instance. */ 829 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 830 831 /* 832 * Configure byte swap and enable indirect register access. 833 * Rely on CPU to do target byte swapping on big endian systems. 834 * Access to registers outside of PCI configurtion space are not 835 * valid until this is done. 836 */ 837 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 838 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 839 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 840 841 /* Save ASIC revsion info. */ 842 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 843 844 /* Weed out any non-production controller revisions. */ 845 switch(BCE_CHIP_ID(sc)) { 846 case BCE_CHIP_ID_5706_A0: 847 case BCE_CHIP_ID_5706_A1: 848 case BCE_CHIP_ID_5708_A0: 849 case BCE_CHIP_ID_5708_B0: 850 case BCE_CHIP_ID_5709_A0: 851 case BCE_CHIP_ID_5709_B0: 852 case BCE_CHIP_ID_5709_B1: 853 case BCE_CHIP_ID_5709_B2: 854 BCE_PRINTF("%s(%d): Unsupported controller " 855 "revision (%c%d)!\n", __FILE__, __LINE__, 856 (((pci_read_config(dev, PCIR_REVID, 4) & 857 0xf0) >> 4) + 'A'), (pci_read_config(dev, 858 PCIR_REVID, 4) & 0xf)); 859 rc = ENODEV; 860 goto bce_attach_fail; 861 } 862 863 /* 864 * The embedded PCIe to PCI-X bridge (EPB) 865 * in the 5708 cannot address memory above 866 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 867 */ 868 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 869 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 870 else 871 sc->max_bus_addr = BUS_SPACE_MAXADDR; 872 873 /* 874 * Find the base address for shared memory access. 875 * Newer versions of bootcode use a signature and offset 876 * while older versions use a fixed address. 877 */ 878 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 879 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 880 /* Multi-port devices use different offsets in shared memory. */ 881 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 + 882 (pci_get_function(sc->bce_dev) << 2)); 883 else 884 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 885 886 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 887 __FUNCTION__, sc->bce_shmem_base); 888 889 /* Fetch the bootcode revision. */ 890 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV); 891 for (int i = 0, j = 0; i < 3; i++) { 892 u8 num; 893 894 num = (u8) (val >> (24 - (i * 8))); 895 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 896 if (num >= k || !skip0 || k == 1) { 897 sc->bce_bc_ver[j++] = (num / k) + ''; 898 skip0 = 0; 899 } 900 } 901 902 if (i != 2) 903 sc->bce_bc_ver[j++] = '.'; 904 } 905 906 /* Check if any management firwmare is enabled. */ 907 val = bce_shmem_rd(sc, BCE_PORT_FEATURE); 908 if (val & BCE_PORT_FEATURE_ASF_ENABLED) { 909 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 910 911 /* Allow time for firmware to enter the running state. */ 912 for (int i = 0; i < 30; i++) { 913 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 914 if (val & BCE_CONDITION_MFW_RUN_MASK) 915 break; 916 DELAY(10000); 917 } 918 919 /* Check if management firmware is running. */ 920 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 921 val &= BCE_CONDITION_MFW_RUN_MASK; 922 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) && 923 (val != BCE_CONDITION_MFW_RUN_NONE)) { 924 u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR); 925 int i = 0; 926 927 /* Read the management firmware version string. */ 928 for (int j = 0; j < 3; j++) { 929 val = bce_reg_rd_ind(sc, addr + j * 4); 930 val = bswap32(val); 931 memcpy(&sc->bce_mfw_ver[i], &val, 4); 932 i += 4; 933 } 934 } else { 935 /* May cause firmware synchronization timeouts. */ 936 BCE_PRINTF("%s(%d): Management firmware enabled " 937 "but not running!\n", __FILE__, __LINE__); 938 strcpy(sc->bce_mfw_ver, "NOT RUNNING!"); 939 940 /* ToDo: Any action the driver should take? */ 941 } 942 } 943 944 /* Get PCI bus information (speed and type). */ 945 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 946 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 947 u32 clkreg; 948 949 sc->bce_flags |= BCE_PCIX_FLAG; 950 951 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 952 953 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 954 switch (clkreg) { 955 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 956 sc->bus_speed_mhz = 133; 957 break; 958 959 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 960 sc->bus_speed_mhz = 100; 961 break; 962 963 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 964 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 965 sc->bus_speed_mhz = 66; 966 break; 967 968 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 969 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 970 sc->bus_speed_mhz = 50; 971 break; 972 973 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 974 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 975 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 976 sc->bus_speed_mhz = 33; 977 break; 978 } 979 } else { 980 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 981 sc->bus_speed_mhz = 66; 982 else 983 sc->bus_speed_mhz = 33; 984 } 985 986 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 987 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 988 989 /* Reset controller and announce to bootcode that driver is present. */ 990 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 991 BCE_PRINTF("%s(%d): Controller reset failed!\n", 992 __FILE__, __LINE__); 993 rc = ENXIO; 994 goto bce_attach_fail; 995 } 996 997 /* Initialize the controller. */ 998 if (bce_chipinit(sc)) { 999 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 1000 __FILE__, __LINE__); 1001 rc = ENXIO; 1002 goto bce_attach_fail; 1003 } 1004 1005 /* Perform NVRAM test. */ 1006 if (bce_nvram_test(sc)) { 1007 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 1008 __FILE__, __LINE__); 1009 rc = ENXIO; 1010 goto bce_attach_fail; 1011 } 1012 1013 /* Fetch the permanent Ethernet MAC address. */ 1014 bce_get_mac_addr(sc); 1015 1016 /* 1017 * Trip points control how many BDs 1018 * should be ready before generating an 1019 * interrupt while ticks control how long 1020 * a BD can sit in the chain before 1021 * generating an interrupt. Set the default 1022 * values for the RX and TX chains. 1023 */ 1024 1025 #ifdef BCE_DEBUG 1026 /* Force more frequent interrupts. */ 1027 sc->bce_tx_quick_cons_trip_int = 1; 1028 sc->bce_tx_quick_cons_trip = 1; 1029 sc->bce_tx_ticks_int = 0; 1030 sc->bce_tx_ticks = 0; 1031 1032 sc->bce_rx_quick_cons_trip_int = 1; 1033 sc->bce_rx_quick_cons_trip = 1; 1034 sc->bce_rx_ticks_int = 0; 1035 sc->bce_rx_ticks = 0; 1036 #else 1037 /* Improve throughput at the expense of increased latency. */ 1038 sc->bce_tx_quick_cons_trip_int = 20; 1039 sc->bce_tx_quick_cons_trip = 20; 1040 sc->bce_tx_ticks_int = 80; 1041 sc->bce_tx_ticks = 80; 1042 1043 sc->bce_rx_quick_cons_trip_int = 6; 1044 sc->bce_rx_quick_cons_trip = 6; 1045 sc->bce_rx_ticks_int = 18; 1046 sc->bce_rx_ticks = 18; 1047 #endif 1048 1049 /* Not used for L2. */ 1050 sc->bce_comp_prod_trip_int = 0; 1051 sc->bce_comp_prod_trip = 0; 1052 sc->bce_com_ticks_int = 0; 1053 sc->bce_com_ticks = 0; 1054 sc->bce_cmd_ticks_int = 0; 1055 sc->bce_cmd_ticks = 0; 1056 1057 /* Update statistics once every second. */ 1058 sc->bce_stats_ticks = 1000000 & 0xffff00; 1059 1060 /* Find the media type for the adapter. */ 1061 bce_get_media(sc); 1062 1063 /* Store data needed by PHY driver for backplane applications */ 1064 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 1065 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG); 1066 1067 /* Allocate DMA memory resources. */ 1068 if (bce_dma_alloc(dev)) { 1069 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 1070 __FILE__, __LINE__); 1071 rc = ENXIO; 1072 goto bce_attach_fail; 1073 } 1074 1075 /* Allocate an ifnet structure. */ 1076 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 1077 if (ifp == NULL) { 1078 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 1079 __FILE__, __LINE__); 1080 rc = ENXIO; 1081 goto bce_attach_fail; 1082 } 1083 1084 /* Initialize the ifnet interface. */ 1085 ifp->if_softc = sc; 1086 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1087 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1088 ifp->if_ioctl = bce_ioctl; 1089 ifp->if_start = bce_start; 1090 ifp->if_init = bce_init; 1091 ifp->if_mtu = ETHERMTU; 1092 1093 if (bce_tso_enable) { 1094 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; 1095 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 | 1096 IFCAP_VLAN_HWTSO; 1097 } else { 1098 ifp->if_hwassist = BCE_IF_HWASSIST; 1099 ifp->if_capabilities = BCE_IF_CAPABILITIES; 1100 } 1101 1102 ifp->if_capenable = ifp->if_capabilities; 1103 1104 /* 1105 * Assume standard mbuf sizes for buffer allocation. 1106 * This may change later if the MTU size is set to 1107 * something other than 1500. 1108 */ 1109 #ifdef BCE_JUMBO_HDRSPLIT 1110 sc->rx_bd_mbuf_alloc_size = MHLEN; 1111 /* Make sure offset is 16 byte aligned for hardware. */ 1112 sc->rx_bd_mbuf_align_pad = 1113 roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN); 1114 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 1115 sc->rx_bd_mbuf_align_pad; 1116 sc->pg_bd_mbuf_alloc_size = MCLBYTES; 1117 #else 1118 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 1119 sc->rx_bd_mbuf_align_pad = 1120 roundup2(MCLBYTES, 16) - MCLBYTES; 1121 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 1122 sc->rx_bd_mbuf_align_pad; 1123 #endif 1124 1125 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD; 1126 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1127 IFQ_SET_READY(&ifp->if_snd); 1128 1129 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1130 ifp->if_baudrate = IF_Mbps(2500ULL); 1131 else 1132 ifp->if_baudrate = IF_Mbps(1000); 1133 1134 /* Handle any special PHY initialization for SerDes PHYs. */ 1135 bce_init_media(sc); 1136 1137 /* MII child bus by attaching the PHY. */ 1138 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd, 1139 bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr, 1140 MII_OFFSET_ANY, MIIF_DOPAUSE | MIIF_FORCEPAUSE); 1141 if (rc != 0) { 1142 BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__, 1143 __LINE__); 1144 goto bce_attach_fail; 1145 } 1146 1147 /* Attach to the Ethernet interface list. */ 1148 ether_ifattach(ifp, sc->eaddr); 1149 1150 #if __FreeBSD_version < 500000 1151 callout_init(&sc->bce_tick_callout); 1152 callout_init(&sc->bce_pulse_callout); 1153 #else 1154 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 1155 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 1156 #endif 1157 1158 /* Hookup IRQ last. */ 1159 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, 1160 NULL, bce_intr, sc, &sc->bce_intrhand); 1161 1162 if (rc) { 1163 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 1164 __FILE__, __LINE__); 1165 bce_detach(dev); 1166 goto bce_attach_exit; 1167 } 1168 1169 /* 1170 * At this point we've acquired all the resources 1171 * we need to run so there's no turning back, we're 1172 * cleared for launch. 1173 */ 1174 1175 /* Print some important debugging info. */ 1176 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc)); 1177 1178 /* Add the supported sysctls to the kernel. */ 1179 bce_add_sysctls(sc); 1180 1181 BCE_LOCK(sc); 1182 1183 /* 1184 * The chip reset earlier notified the bootcode that 1185 * a driver is present. We now need to start our pulse 1186 * routine so that the bootcode is reminded that we're 1187 * still running. 1188 */ 1189 bce_pulse(sc); 1190 1191 bce_mgmt_init_locked(sc); 1192 BCE_UNLOCK(sc); 1193 1194 /* Finally, print some useful adapter info */ 1195 bce_print_adapter_info(sc); 1196 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n", 1197 __FUNCTION__, sc); 1198 1199 goto bce_attach_exit; 1200 1201 bce_attach_fail: 1202 bce_release_resources(sc); 1203 1204 bce_attach_exit: 1205 1206 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1207 1208 return(rc); 1209 } 1210 1211 1212 /****************************************************************************/ 1213 /* Device detach function. */ 1214 /* */ 1215 /* Stops the controller, resets the controller, and releases resources. */ 1216 /* */ 1217 /* Returns: */ 1218 /* 0 on success, positive value on failure. */ 1219 /****************************************************************************/ 1220 static int 1221 bce_detach(device_t dev) 1222 { 1223 struct bce_softc *sc = device_get_softc(dev); 1224 struct ifnet *ifp; 1225 u32 msg; 1226 1227 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1228 1229 ifp = sc->bce_ifp; 1230 1231 /* Stop and reset the controller. */ 1232 BCE_LOCK(sc); 1233 1234 /* Stop the pulse so the bootcode can go to driver absent state. */ 1235 callout_stop(&sc->bce_pulse_callout); 1236 1237 bce_stop(sc); 1238 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1239 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1240 else 1241 msg = BCE_DRV_MSG_CODE_UNLOAD; 1242 bce_reset(sc, msg); 1243 1244 BCE_UNLOCK(sc); 1245 1246 ether_ifdetach(ifp); 1247 1248 /* If we have a child device on the MII bus remove it too. */ 1249 bus_generic_detach(dev); 1250 device_delete_child(dev, sc->bce_miibus); 1251 1252 /* Release all remaining resources. */ 1253 bce_release_resources(sc); 1254 1255 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1256 1257 return(0); 1258 } 1259 1260 1261 /****************************************************************************/ 1262 /* Device shutdown function. */ 1263 /* */ 1264 /* Stops and resets the controller. */ 1265 /* */ 1266 /* Returns: */ 1267 /* 0 on success, positive value on failure. */ 1268 /****************************************************************************/ 1269 static int 1270 bce_shutdown(device_t dev) 1271 { 1272 struct bce_softc *sc = device_get_softc(dev); 1273 u32 msg; 1274 1275 DBENTER(BCE_VERBOSE); 1276 1277 BCE_LOCK(sc); 1278 bce_stop(sc); 1279 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1280 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1281 else 1282 msg = BCE_DRV_MSG_CODE_UNLOAD; 1283 bce_reset(sc, msg); 1284 BCE_UNLOCK(sc); 1285 1286 DBEXIT(BCE_VERBOSE); 1287 1288 return (0); 1289 } 1290 1291 1292 #ifdef BCE_DEBUG 1293 /****************************************************************************/ 1294 /* Register read. */ 1295 /* */ 1296 /* Returns: */ 1297 /* The value of the register. */ 1298 /****************************************************************************/ 1299 static u32 1300 bce_reg_rd(struct bce_softc *sc, u32 offset) 1301 { 1302 u32 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset); 1303 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1304 __FUNCTION__, offset, val); 1305 return val; 1306 } 1307 1308 1309 /****************************************************************************/ 1310 /* Register write (16 bit). */ 1311 /* */ 1312 /* Returns: */ 1313 /* Nothing. */ 1314 /****************************************************************************/ 1315 static void 1316 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val) 1317 { 1318 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n", 1319 __FUNCTION__, offset, val); 1320 bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val); 1321 } 1322 1323 1324 /****************************************************************************/ 1325 /* Register write. */ 1326 /* */ 1327 /* Returns: */ 1328 /* Nothing. */ 1329 /****************************************************************************/ 1330 static void 1331 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val) 1332 { 1333 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1334 __FUNCTION__, offset, val); 1335 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val); 1336 } 1337 #endif 1338 1339 /****************************************************************************/ 1340 /* Indirect register read. */ 1341 /* */ 1342 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 1343 /* configuration space. Using this mechanism avoids issues with posted */ 1344 /* reads but is much slower than memory-mapped I/O. */ 1345 /* */ 1346 /* Returns: */ 1347 /* The value of the register. */ 1348 /****************************************************************************/ 1349 static u32 1350 bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 1351 { 1352 device_t dev; 1353 dev = sc->bce_dev; 1354 1355 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1356 #ifdef BCE_DEBUG 1357 { 1358 u32 val; 1359 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1360 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1361 __FUNCTION__, offset, val); 1362 return val; 1363 } 1364 #else 1365 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1366 #endif 1367 } 1368 1369 1370 /****************************************************************************/ 1371 /* Indirect register write. */ 1372 /* */ 1373 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1374 /* configuration space. Using this mechanism avoids issues with posted */ 1375 /* writes but is muchh slower than memory-mapped I/O. */ 1376 /* */ 1377 /* Returns: */ 1378 /* Nothing. */ 1379 /****************************************************************************/ 1380 static void 1381 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 1382 { 1383 device_t dev; 1384 dev = sc->bce_dev; 1385 1386 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1387 __FUNCTION__, offset, val); 1388 1389 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1390 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 1391 } 1392 1393 1394 /****************************************************************************/ 1395 /* Shared memory write. */ 1396 /* */ 1397 /* Writes NetXtreme II shared memory region. */ 1398 /* */ 1399 /* Returns: */ 1400 /* Nothing. */ 1401 /****************************************************************************/ 1402 static void 1403 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val) 1404 { 1405 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to " 1406 "0x%08X\n", __FUNCTION__, val, offset); 1407 1408 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val); 1409 } 1410 1411 1412 /****************************************************************************/ 1413 /* Shared memory read. */ 1414 /* */ 1415 /* Reads NetXtreme II shared memory region. */ 1416 /* */ 1417 /* Returns: */ 1418 /* The 32 bit value read. */ 1419 /****************************************************************************/ 1420 static u32 1421 bce_shmem_rd(struct bce_softc *sc, u32 offset) 1422 { 1423 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset); 1424 1425 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from " 1426 "0x%08X\n", __FUNCTION__, val, offset); 1427 1428 return val; 1429 } 1430 1431 1432 #ifdef BCE_DEBUG 1433 /****************************************************************************/ 1434 /* Context memory read. */ 1435 /* */ 1436 /* The NetXtreme II controller uses context memory to track connection */ 1437 /* information for L2 and higher network protocols. */ 1438 /* */ 1439 /* Returns: */ 1440 /* The requested 32 bit value of context memory. */ 1441 /****************************************************************************/ 1442 static u32 1443 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset) 1444 { 1445 u32 idx, offset, retry_cnt = 5, val; 1446 1447 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || 1448 cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID " 1449 "address: 0x%08X.\n", __FUNCTION__, cid_addr)); 1450 1451 offset = ctx_offset + cid_addr; 1452 1453 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 1454 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 1455 1456 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ)); 1457 1458 for (idx = 0; idx < retry_cnt; idx++) { 1459 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1460 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0) 1461 break; 1462 DELAY(5); 1463 } 1464 1465 if (val & BCE_CTX_CTX_CTRL_READ_REQ) 1466 BCE_PRINTF("%s(%d); Unable to read CTX memory: " 1467 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1468 __FILE__, __LINE__, cid_addr, ctx_offset); 1469 1470 val = REG_RD(sc, BCE_CTX_CTX_DATA); 1471 } else { 1472 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1473 val = REG_RD(sc, BCE_CTX_DATA); 1474 } 1475 1476 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1477 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val); 1478 1479 return(val); 1480 } 1481 #endif 1482 1483 1484 /****************************************************************************/ 1485 /* Context memory write. */ 1486 /* */ 1487 /* The NetXtreme II controller uses context memory to track connection */ 1488 /* information for L2 and higher network protocols. */ 1489 /* */ 1490 /* Returns: */ 1491 /* Nothing. */ 1492 /****************************************************************************/ 1493 static void 1494 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val) 1495 { 1496 u32 idx, offset = ctx_offset + cid_addr; 1497 u32 val, retry_cnt = 5; 1498 1499 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1500 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val); 1501 1502 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1503 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1504 __FUNCTION__, cid_addr)); 1505 1506 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 1507 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 1508 1509 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val); 1510 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ)); 1511 1512 for (idx = 0; idx < retry_cnt; idx++) { 1513 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1514 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0) 1515 break; 1516 DELAY(5); 1517 } 1518 1519 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) 1520 BCE_PRINTF("%s(%d); Unable to write CTX memory: " 1521 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1522 __FILE__, __LINE__, cid_addr, ctx_offset); 1523 1524 } else { 1525 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1526 REG_WR(sc, BCE_CTX_DATA, ctx_val); 1527 } 1528 } 1529 1530 1531 /****************************************************************************/ 1532 /* PHY register read. */ 1533 /* */ 1534 /* Implements register reads on the MII bus. */ 1535 /* */ 1536 /* Returns: */ 1537 /* The value of the register. */ 1538 /****************************************************************************/ 1539 static int 1540 bce_miibus_read_reg(device_t dev, int phy, int reg) 1541 { 1542 struct bce_softc *sc; 1543 u32 val; 1544 int i; 1545 1546 sc = device_get_softc(dev); 1547 1548 /* Make sure we are accessing the correct PHY address. */ 1549 if (phy != sc->bce_phy_addr) { 1550 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d " 1551 "for PHY read!\n", phy); 1552 return(0); 1553 } 1554 1555 /* 1556 * The 5709S PHY is an IEEE Clause 45 PHY 1557 * with special mappings to work with IEEE 1558 * Clause 22 register accesses. 1559 */ 1560 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1561 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1562 reg += 0x10; 1563 } 1564 1565 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1566 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1567 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1568 1569 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1570 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1571 1572 DELAY(40); 1573 } 1574 1575 1576 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1577 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1578 BCE_EMAC_MDIO_COMM_START_BUSY; 1579 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1580 1581 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1582 DELAY(10); 1583 1584 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1585 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1586 DELAY(5); 1587 1588 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1589 val &= BCE_EMAC_MDIO_COMM_DATA; 1590 1591 break; 1592 } 1593 } 1594 1595 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1596 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, " 1597 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1598 val = 0x0; 1599 } else { 1600 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1601 } 1602 1603 1604 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1605 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1606 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1607 1608 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1609 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1610 1611 DELAY(40); 1612 } 1613 1614 DB_PRINT_PHY_REG(reg, val); 1615 return (val & 0xffff); 1616 1617 } 1618 1619 1620 /****************************************************************************/ 1621 /* PHY register write. */ 1622 /* */ 1623 /* Implements register writes on the MII bus. */ 1624 /* */ 1625 /* Returns: */ 1626 /* The value of the register. */ 1627 /****************************************************************************/ 1628 static int 1629 bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1630 { 1631 struct bce_softc *sc; 1632 u32 val1; 1633 int i; 1634 1635 sc = device_get_softc(dev); 1636 1637 /* Make sure we are accessing the correct PHY address. */ 1638 if (phy != sc->bce_phy_addr) { 1639 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d " 1640 "for PHY write!\n", phy); 1641 return(0); 1642 } 1643 1644 DB_PRINT_PHY_REG(reg, val); 1645 1646 /* 1647 * The 5709S PHY is an IEEE Clause 45 PHY 1648 * with special mappings to work with IEEE 1649 * Clause 22 register accesses. 1650 */ 1651 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1652 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1653 reg += 0x10; 1654 } 1655 1656 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1657 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1658 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1659 1660 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1661 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1662 1663 DELAY(40); 1664 } 1665 1666 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1667 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1668 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1669 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 1670 1671 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1672 DELAY(10); 1673 1674 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1675 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1676 DELAY(5); 1677 break; 1678 } 1679 } 1680 1681 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 1682 BCE_PRINTF("%s(%d): PHY write timeout!\n", 1683 __FILE__, __LINE__); 1684 1685 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1686 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1687 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1688 1689 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1690 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1691 1692 DELAY(40); 1693 } 1694 1695 return 0; 1696 } 1697 1698 1699 /****************************************************************************/ 1700 /* MII bus status change. */ 1701 /* */ 1702 /* Called by the MII bus driver when the PHY establishes link to set the */ 1703 /* MAC interface registers. */ 1704 /* */ 1705 /* Returns: */ 1706 /* Nothing. */ 1707 /****************************************************************************/ 1708 static void 1709 bce_miibus_statchg(device_t dev) 1710 { 1711 struct bce_softc *sc; 1712 struct mii_data *mii; 1713 int val; 1714 1715 sc = device_get_softc(dev); 1716 1717 DBENTER(BCE_VERBOSE_PHY); 1718 1719 mii = device_get_softc(sc->bce_miibus); 1720 1721 val = REG_RD(sc, BCE_EMAC_MODE); 1722 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 1723 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 1724 BCE_EMAC_MODE_25G); 1725 1726 /* Set MII or GMII interface based on the PHY speed. */ 1727 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1728 case IFM_10_T: 1729 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 1730 DBPRINT(sc, BCE_INFO_PHY, 1731 "Enabling 10Mb interface.\n"); 1732 val |= BCE_EMAC_MODE_PORT_MII_10; 1733 break; 1734 } 1735 /* fall-through */ 1736 case IFM_100_TX: 1737 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n"); 1738 val |= BCE_EMAC_MODE_PORT_MII; 1739 break; 1740 case IFM_2500_SX: 1741 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n"); 1742 val |= BCE_EMAC_MODE_25G; 1743 /* fall-through */ 1744 case IFM_1000_T: 1745 case IFM_1000_SX: 1746 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n"); 1747 val |= BCE_EMAC_MODE_PORT_GMII; 1748 break; 1749 default: 1750 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling " 1751 "default GMII interface.\n"); 1752 val |= BCE_EMAC_MODE_PORT_GMII; 1753 } 1754 1755 /* Set half or full duplex based on PHY settings. */ 1756 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 1757 DBPRINT(sc, BCE_INFO_PHY, 1758 "Setting Half-Duplex interface.\n"); 1759 val |= BCE_EMAC_MODE_HALF_DUPLEX; 1760 } else 1761 DBPRINT(sc, BCE_INFO_PHY, 1762 "Setting Full-Duplex interface.\n"); 1763 1764 REG_WR(sc, BCE_EMAC_MODE, val); 1765 1766 if ((mii->mii_media_active & IFM_ETH_RXPAUSE) != 0) { 1767 DBPRINT(sc, BCE_INFO_PHY, 1768 "%s(): Enabling RX flow control.\n", __FUNCTION__); 1769 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 1770 } else { 1771 DBPRINT(sc, BCE_INFO_PHY, 1772 "%s(): Disabling RX flow control.\n", __FUNCTION__); 1773 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 1774 } 1775 1776 if ((mii->mii_media_active & IFM_ETH_TXPAUSE) != 0) { 1777 DBPRINT(sc, BCE_INFO_PHY, 1778 "%s(): Enabling TX flow control.\n", __FUNCTION__); 1779 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 1780 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL; 1781 } else { 1782 DBPRINT(sc, BCE_INFO_PHY, 1783 "%s(): Disabling TX flow control.\n", __FUNCTION__); 1784 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 1785 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL; 1786 } 1787 1788 /* ToDo: Update watermarks in bce_init_rx_context(). */ 1789 1790 DBEXIT(BCE_VERBOSE_PHY); 1791 } 1792 1793 1794 /****************************************************************************/ 1795 /* Acquire NVRAM lock. */ 1796 /* */ 1797 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1798 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1799 /* for use by the driver. */ 1800 /* */ 1801 /* Returns: */ 1802 /* 0 on success, positive value on failure. */ 1803 /****************************************************************************/ 1804 static int 1805 bce_acquire_nvram_lock(struct bce_softc *sc) 1806 { 1807 u32 val; 1808 int j, rc = 0; 1809 1810 DBENTER(BCE_VERBOSE_NVRAM); 1811 1812 /* Request access to the flash interface. */ 1813 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 1814 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1815 val = REG_RD(sc, BCE_NVM_SW_ARB); 1816 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 1817 break; 1818 1819 DELAY(5); 1820 } 1821 1822 if (j >= NVRAM_TIMEOUT_COUNT) { 1823 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 1824 rc = EBUSY; 1825 } 1826 1827 DBEXIT(BCE_VERBOSE_NVRAM); 1828 return (rc); 1829 } 1830 1831 1832 /****************************************************************************/ 1833 /* Release NVRAM lock. */ 1834 /* */ 1835 /* When the caller is finished accessing NVRAM the lock must be released. */ 1836 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1837 /* for use by the driver. */ 1838 /* */ 1839 /* Returns: */ 1840 /* 0 on success, positive value on failure. */ 1841 /****************************************************************************/ 1842 static int 1843 bce_release_nvram_lock(struct bce_softc *sc) 1844 { 1845 u32 val; 1846 int j, rc = 0; 1847 1848 DBENTER(BCE_VERBOSE_NVRAM); 1849 1850 /* 1851 * Relinquish nvram interface. 1852 */ 1853 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 1854 1855 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1856 val = REG_RD(sc, BCE_NVM_SW_ARB); 1857 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 1858 break; 1859 1860 DELAY(5); 1861 } 1862 1863 if (j >= NVRAM_TIMEOUT_COUNT) { 1864 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n"); 1865 rc = EBUSY; 1866 } 1867 1868 DBEXIT(BCE_VERBOSE_NVRAM); 1869 return (rc); 1870 } 1871 1872 1873 #ifdef BCE_NVRAM_WRITE_SUPPORT 1874 /****************************************************************************/ 1875 /* Enable NVRAM write access. */ 1876 /* */ 1877 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1878 /* */ 1879 /* Returns: */ 1880 /* 0 on success, positive value on failure. */ 1881 /****************************************************************************/ 1882 static int 1883 bce_enable_nvram_write(struct bce_softc *sc) 1884 { 1885 u32 val; 1886 int rc = 0; 1887 1888 DBENTER(BCE_VERBOSE_NVRAM); 1889 1890 val = REG_RD(sc, BCE_MISC_CFG); 1891 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 1892 1893 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 1894 int j; 1895 1896 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1897 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 1898 1899 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1900 DELAY(5); 1901 1902 val = REG_RD(sc, BCE_NVM_COMMAND); 1903 if (val & BCE_NVM_COMMAND_DONE) 1904 break; 1905 } 1906 1907 if (j >= NVRAM_TIMEOUT_COUNT) { 1908 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 1909 rc = EBUSY; 1910 } 1911 } 1912 1913 DBENTER(BCE_VERBOSE_NVRAM); 1914 return (rc); 1915 } 1916 1917 1918 /****************************************************************************/ 1919 /* Disable NVRAM write access. */ 1920 /* */ 1921 /* When the caller is finished writing to NVRAM write access must be */ 1922 /* disabled. */ 1923 /* */ 1924 /* Returns: */ 1925 /* Nothing. */ 1926 /****************************************************************************/ 1927 static void 1928 bce_disable_nvram_write(struct bce_softc *sc) 1929 { 1930 u32 val; 1931 1932 DBENTER(BCE_VERBOSE_NVRAM); 1933 1934 val = REG_RD(sc, BCE_MISC_CFG); 1935 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 1936 1937 DBEXIT(BCE_VERBOSE_NVRAM); 1938 1939 } 1940 #endif 1941 1942 1943 /****************************************************************************/ 1944 /* Enable NVRAM access. */ 1945 /* */ 1946 /* Before accessing NVRAM for read or write operations the caller must */ 1947 /* enabled NVRAM access. */ 1948 /* */ 1949 /* Returns: */ 1950 /* Nothing. */ 1951 /****************************************************************************/ 1952 static void 1953 bce_enable_nvram_access(struct bce_softc *sc) 1954 { 1955 u32 val; 1956 1957 DBENTER(BCE_VERBOSE_NVRAM); 1958 1959 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 1960 /* Enable both bits, even on read. */ 1961 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val | 1962 BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 1963 1964 DBEXIT(BCE_VERBOSE_NVRAM); 1965 } 1966 1967 1968 /****************************************************************************/ 1969 /* Disable NVRAM access. */ 1970 /* */ 1971 /* When the caller is finished accessing NVRAM access must be disabled. */ 1972 /* */ 1973 /* Returns: */ 1974 /* Nothing. */ 1975 /****************************************************************************/ 1976 static void 1977 bce_disable_nvram_access(struct bce_softc *sc) 1978 { 1979 u32 val; 1980 1981 DBENTER(BCE_VERBOSE_NVRAM); 1982 1983 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 1984 1985 /* Disable both bits, even after read. */ 1986 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val & 1987 ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN)); 1988 1989 DBEXIT(BCE_VERBOSE_NVRAM); 1990 } 1991 1992 1993 #ifdef BCE_NVRAM_WRITE_SUPPORT 1994 /****************************************************************************/ 1995 /* Erase NVRAM page before writing. */ 1996 /* */ 1997 /* Non-buffered flash parts require that a page be erased before it is */ 1998 /* written. */ 1999 /* */ 2000 /* Returns: */ 2001 /* 0 on success, positive value on failure. */ 2002 /****************************************************************************/ 2003 static int 2004 bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 2005 { 2006 u32 cmd; 2007 int j, rc = 0; 2008 2009 DBENTER(BCE_VERBOSE_NVRAM); 2010 2011 /* Buffered flash doesn't require an erase. */ 2012 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED) 2013 goto bce_nvram_erase_page_exit; 2014 2015 /* Build an erase command. */ 2016 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 2017 BCE_NVM_COMMAND_DOIT; 2018 2019 /* 2020 * Clear the DONE bit separately, set the NVRAM adress to erase, 2021 * and issue the erase command. 2022 */ 2023 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2024 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2025 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2026 2027 /* Wait for completion. */ 2028 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2029 u32 val; 2030 2031 DELAY(5); 2032 2033 val = REG_RD(sc, BCE_NVM_COMMAND); 2034 if (val & BCE_NVM_COMMAND_DONE) 2035 break; 2036 } 2037 2038 if (j >= NVRAM_TIMEOUT_COUNT) { 2039 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 2040 rc = EBUSY; 2041 } 2042 2043 bce_nvram_erase_page_exit: 2044 DBEXIT(BCE_VERBOSE_NVRAM); 2045 return (rc); 2046 } 2047 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2048 2049 2050 /****************************************************************************/ 2051 /* Read a dword (32 bits) from NVRAM. */ 2052 /* */ 2053 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 2054 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 2055 /* */ 2056 /* Returns: */ 2057 /* 0 on success and the 32 bit value read, positive value on failure. */ 2058 /****************************************************************************/ 2059 static int 2060 bce_nvram_read_dword(struct bce_softc *sc, 2061 u32 offset, u8 *ret_val, u32 cmd_flags) 2062 { 2063 u32 cmd; 2064 int i, rc = 0; 2065 2066 DBENTER(BCE_EXTREME_NVRAM); 2067 2068 /* Build the command word. */ 2069 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 2070 2071 /* Calculate the offset for buffered flash if translation is used. */ 2072 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2073 offset = ((offset / sc->bce_flash_info->page_size) << 2074 sc->bce_flash_info->page_bits) + 2075 (offset % sc->bce_flash_info->page_size); 2076 } 2077 2078 /* 2079 * Clear the DONE bit separately, set the address to read, 2080 * and issue the read. 2081 */ 2082 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2083 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2084 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2085 2086 /* Wait for completion. */ 2087 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 2088 u32 val; 2089 2090 DELAY(5); 2091 2092 val = REG_RD(sc, BCE_NVM_COMMAND); 2093 if (val & BCE_NVM_COMMAND_DONE) { 2094 val = REG_RD(sc, BCE_NVM_READ); 2095 2096 val = bce_be32toh(val); 2097 memcpy(ret_val, &val, 4); 2098 break; 2099 } 2100 } 2101 2102 /* Check for errors. */ 2103 if (i >= NVRAM_TIMEOUT_COUNT) { 2104 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at " 2105 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 2106 rc = EBUSY; 2107 } 2108 2109 DBEXIT(BCE_EXTREME_NVRAM); 2110 return(rc); 2111 } 2112 2113 2114 #ifdef BCE_NVRAM_WRITE_SUPPORT 2115 /****************************************************************************/ 2116 /* Write a dword (32 bits) to NVRAM. */ 2117 /* */ 2118 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 2119 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 2120 /* enabled NVRAM write access. */ 2121 /* */ 2122 /* Returns: */ 2123 /* 0 on success, positive value on failure. */ 2124 /****************************************************************************/ 2125 static int 2126 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 2127 u32 cmd_flags) 2128 { 2129 u32 cmd, val32; 2130 int j, rc = 0; 2131 2132 DBENTER(BCE_VERBOSE_NVRAM); 2133 2134 /* Build the command word. */ 2135 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 2136 2137 /* Calculate the offset for buffered flash if translation is used. */ 2138 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2139 offset = ((offset / sc->bce_flash_info->page_size) << 2140 sc->bce_flash_info->page_bits) + 2141 (offset % sc->bce_flash_info->page_size); 2142 } 2143 2144 /* 2145 * Clear the DONE bit separately, convert NVRAM data to big-endian, 2146 * set the NVRAM address to write, and issue the write command 2147 */ 2148 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2149 memcpy(&val32, val, 4); 2150 val32 = htobe32(val32); 2151 REG_WR(sc, BCE_NVM_WRITE, val32); 2152 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2153 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2154 2155 /* Wait for completion. */ 2156 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2157 DELAY(5); 2158 2159 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 2160 break; 2161 } 2162 if (j >= NVRAM_TIMEOUT_COUNT) { 2163 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at " 2164 "offset 0x%08X\n", __FILE__, __LINE__, offset); 2165 rc = EBUSY; 2166 } 2167 2168 DBEXIT(BCE_VERBOSE_NVRAM); 2169 return (rc); 2170 } 2171 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2172 2173 2174 /****************************************************************************/ 2175 /* Initialize NVRAM access. */ 2176 /* */ 2177 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 2178 /* access that device. */ 2179 /* */ 2180 /* Returns: */ 2181 /* 0 on success, positive value on failure. */ 2182 /****************************************************************************/ 2183 static int 2184 bce_init_nvram(struct bce_softc *sc) 2185 { 2186 u32 val; 2187 int j, entry_count, rc = 0; 2188 struct flash_spec *flash; 2189 2190 DBENTER(BCE_VERBOSE_NVRAM); 2191 2192 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 2193 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 2194 sc->bce_flash_info = &flash_5709; 2195 goto bce_init_nvram_get_flash_size; 2196 } 2197 2198 /* Determine the selected interface. */ 2199 val = REG_RD(sc, BCE_NVM_CFG1); 2200 2201 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 2202 2203 /* 2204 * Flash reconfiguration is required to support additional 2205 * NVRAM devices not directly supported in hardware. 2206 * Check if the flash interface was reconfigured 2207 * by the bootcode. 2208 */ 2209 2210 if (val & 0x40000000) { 2211 /* Flash interface reconfigured by bootcode. */ 2212 2213 DBPRINT(sc,BCE_INFO_LOAD, 2214 "bce_init_nvram(): Flash WAS reconfigured.\n"); 2215 2216 for (j = 0, flash = &flash_table[0]; j < entry_count; 2217 j++, flash++) { 2218 if ((val & FLASH_BACKUP_STRAP_MASK) == 2219 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 2220 sc->bce_flash_info = flash; 2221 break; 2222 } 2223 } 2224 } else { 2225 /* Flash interface not yet reconfigured. */ 2226 u32 mask; 2227 2228 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n", 2229 __FUNCTION__); 2230 2231 if (val & (1 << 23)) 2232 mask = FLASH_BACKUP_STRAP_MASK; 2233 else 2234 mask = FLASH_STRAP_MASK; 2235 2236 /* Look for the matching NVRAM device configuration data. */ 2237 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 2238 2239 /* Check if the device matches any of the known devices. */ 2240 if ((val & mask) == (flash->strapping & mask)) { 2241 /* Found a device match. */ 2242 sc->bce_flash_info = flash; 2243 2244 /* Request access to the flash interface. */ 2245 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2246 return rc; 2247 2248 /* Reconfigure the flash interface. */ 2249 bce_enable_nvram_access(sc); 2250 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 2251 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 2252 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 2253 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 2254 bce_disable_nvram_access(sc); 2255 bce_release_nvram_lock(sc); 2256 2257 break; 2258 } 2259 } 2260 } 2261 2262 /* Check if a matching device was found. */ 2263 if (j == entry_count) { 2264 sc->bce_flash_info = NULL; 2265 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 2266 __FILE__, __LINE__); 2267 DBEXIT(BCE_VERBOSE_NVRAM); 2268 return (ENODEV); 2269 } 2270 2271 bce_init_nvram_get_flash_size: 2272 /* Write the flash config data to the shared memory interface. */ 2273 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2); 2274 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 2275 if (val) 2276 sc->bce_flash_size = val; 2277 else 2278 sc->bce_flash_size = sc->bce_flash_info->total_size; 2279 2280 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n", 2281 __FUNCTION__, sc->bce_flash_info->name, 2282 sc->bce_flash_info->total_size); 2283 2284 DBEXIT(BCE_VERBOSE_NVRAM); 2285 return rc; 2286 } 2287 2288 2289 /****************************************************************************/ 2290 /* Read an arbitrary range of data from NVRAM. */ 2291 /* */ 2292 /* Prepares the NVRAM interface for access and reads the requested data */ 2293 /* into the supplied buffer. */ 2294 /* */ 2295 /* Returns: */ 2296 /* 0 on success and the data read, positive value on failure. */ 2297 /****************************************************************************/ 2298 static int 2299 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 2300 int buf_size) 2301 { 2302 int rc = 0; 2303 u32 cmd_flags, offset32, len32, extra; 2304 2305 DBENTER(BCE_VERBOSE_NVRAM); 2306 2307 if (buf_size == 0) 2308 goto bce_nvram_read_exit; 2309 2310 /* Request access to the flash interface. */ 2311 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2312 goto bce_nvram_read_exit; 2313 2314 /* Enable access to flash interface */ 2315 bce_enable_nvram_access(sc); 2316 2317 len32 = buf_size; 2318 offset32 = offset; 2319 extra = 0; 2320 2321 cmd_flags = 0; 2322 2323 if (offset32 & 3) { 2324 u8 buf[4]; 2325 u32 pre_len; 2326 2327 offset32 &= ~3; 2328 pre_len = 4 - (offset & 3); 2329 2330 if (pre_len >= len32) { 2331 pre_len = len32; 2332 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 2333 } 2334 else { 2335 cmd_flags = BCE_NVM_COMMAND_FIRST; 2336 } 2337 2338 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2339 2340 if (rc) 2341 return rc; 2342 2343 memcpy(ret_buf, buf + (offset & 3), pre_len); 2344 2345 offset32 += 4; 2346 ret_buf += pre_len; 2347 len32 -= pre_len; 2348 } 2349 2350 if (len32 & 3) { 2351 extra = 4 - (len32 & 3); 2352 len32 = (len32 + 4) & ~3; 2353 } 2354 2355 if (len32 == 4) { 2356 u8 buf[4]; 2357 2358 if (cmd_flags) 2359 cmd_flags = BCE_NVM_COMMAND_LAST; 2360 else 2361 cmd_flags = BCE_NVM_COMMAND_FIRST | 2362 BCE_NVM_COMMAND_LAST; 2363 2364 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2365 2366 memcpy(ret_buf, buf, 4 - extra); 2367 } 2368 else if (len32 > 0) { 2369 u8 buf[4]; 2370 2371 /* Read the first word. */ 2372 if (cmd_flags) 2373 cmd_flags = 0; 2374 else 2375 cmd_flags = BCE_NVM_COMMAND_FIRST; 2376 2377 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 2378 2379 /* Advance to the next dword. */ 2380 offset32 += 4; 2381 ret_buf += 4; 2382 len32 -= 4; 2383 2384 while (len32 > 4 && rc == 0) { 2385 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 2386 2387 /* Advance to the next dword. */ 2388 offset32 += 4; 2389 ret_buf += 4; 2390 len32 -= 4; 2391 } 2392 2393 if (rc) 2394 goto bce_nvram_read_locked_exit; 2395 2396 cmd_flags = BCE_NVM_COMMAND_LAST; 2397 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2398 2399 memcpy(ret_buf, buf, 4 - extra); 2400 } 2401 2402 bce_nvram_read_locked_exit: 2403 /* Disable access to flash interface and release the lock. */ 2404 bce_disable_nvram_access(sc); 2405 bce_release_nvram_lock(sc); 2406 2407 bce_nvram_read_exit: 2408 DBEXIT(BCE_VERBOSE_NVRAM); 2409 return rc; 2410 } 2411 2412 2413 #ifdef BCE_NVRAM_WRITE_SUPPORT 2414 /****************************************************************************/ 2415 /* Write an arbitrary range of data from NVRAM. */ 2416 /* */ 2417 /* Prepares the NVRAM interface for write access and writes the requested */ 2418 /* data from the supplied buffer. The caller is responsible for */ 2419 /* calculating any appropriate CRCs. */ 2420 /* */ 2421 /* Returns: */ 2422 /* 0 on success, positive value on failure. */ 2423 /****************************************************************************/ 2424 static int 2425 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 2426 int buf_size) 2427 { 2428 u32 written, offset32, len32; 2429 u8 *buf, start[4], end[4]; 2430 int rc = 0; 2431 int align_start, align_end; 2432 2433 DBENTER(BCE_VERBOSE_NVRAM); 2434 2435 buf = data_buf; 2436 offset32 = offset; 2437 len32 = buf_size; 2438 align_start = align_end = 0; 2439 2440 if ((align_start = (offset32 & 3))) { 2441 offset32 &= ~3; 2442 len32 += align_start; 2443 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 2444 goto bce_nvram_write_exit; 2445 } 2446 2447 if (len32 & 3) { 2448 if ((len32 > 4) || !align_start) { 2449 align_end = 4 - (len32 & 3); 2450 len32 += align_end; 2451 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 2452 end, 4))) { 2453 goto bce_nvram_write_exit; 2454 } 2455 } 2456 } 2457 2458 if (align_start || align_end) { 2459 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 2460 if (buf == 0) { 2461 rc = ENOMEM; 2462 goto bce_nvram_write_exit; 2463 } 2464 2465 if (align_start) { 2466 memcpy(buf, start, 4); 2467 } 2468 2469 if (align_end) { 2470 memcpy(buf + len32 - 4, end, 4); 2471 } 2472 memcpy(buf + align_start, data_buf, buf_size); 2473 } 2474 2475 written = 0; 2476 while ((written < len32) && (rc == 0)) { 2477 u32 page_start, page_end, data_start, data_end; 2478 u32 addr, cmd_flags; 2479 int i; 2480 u8 flash_buffer[264]; 2481 2482 /* Find the page_start addr */ 2483 page_start = offset32 + written; 2484 page_start -= (page_start % sc->bce_flash_info->page_size); 2485 /* Find the page_end addr */ 2486 page_end = page_start + sc->bce_flash_info->page_size; 2487 /* Find the data_start addr */ 2488 data_start = (written == 0) ? offset32 : page_start; 2489 /* Find the data_end addr */ 2490 data_end = (page_end > offset32 + len32) ? 2491 (offset32 + len32) : page_end; 2492 2493 /* Request access to the flash interface. */ 2494 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2495 goto bce_nvram_write_exit; 2496 2497 /* Enable access to flash interface */ 2498 bce_enable_nvram_access(sc); 2499 2500 cmd_flags = BCE_NVM_COMMAND_FIRST; 2501 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2502 int j; 2503 2504 /* Read the whole page into the buffer 2505 * (non-buffer flash only) */ 2506 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 2507 if (j == (sc->bce_flash_info->page_size - 4)) { 2508 cmd_flags |= BCE_NVM_COMMAND_LAST; 2509 } 2510 rc = bce_nvram_read_dword(sc, 2511 page_start + j, 2512 &flash_buffer[j], 2513 cmd_flags); 2514 2515 if (rc) 2516 goto bce_nvram_write_locked_exit; 2517 2518 cmd_flags = 0; 2519 } 2520 } 2521 2522 /* Enable writes to flash interface (unlock write-protect) */ 2523 if ((rc = bce_enable_nvram_write(sc)) != 0) 2524 goto bce_nvram_write_locked_exit; 2525 2526 /* Erase the page */ 2527 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 2528 goto bce_nvram_write_locked_exit; 2529 2530 /* Re-enable the write again for the actual write */ 2531 bce_enable_nvram_write(sc); 2532 2533 /* Loop to write back the buffer data from page_start to 2534 * data_start */ 2535 i = 0; 2536 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2537 for (addr = page_start; addr < data_start; 2538 addr += 4, i += 4) { 2539 2540 rc = bce_nvram_write_dword(sc, addr, 2541 &flash_buffer[i], cmd_flags); 2542 2543 if (rc != 0) 2544 goto bce_nvram_write_locked_exit; 2545 2546 cmd_flags = 0; 2547 } 2548 } 2549 2550 /* Loop to write the new data from data_start to data_end */ 2551 for (addr = data_start; addr < data_end; addr += 4, i++) { 2552 if ((addr == page_end - 4) || 2553 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) && 2554 (addr == data_end - 4))) { 2555 2556 cmd_flags |= BCE_NVM_COMMAND_LAST; 2557 } 2558 rc = bce_nvram_write_dword(sc, addr, buf, 2559 cmd_flags); 2560 2561 if (rc != 0) 2562 goto bce_nvram_write_locked_exit; 2563 2564 cmd_flags = 0; 2565 buf += 4; 2566 } 2567 2568 /* Loop to write back the buffer data from data_end 2569 * to page_end */ 2570 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2571 for (addr = data_end; addr < page_end; 2572 addr += 4, i += 4) { 2573 2574 if (addr == page_end-4) { 2575 cmd_flags = BCE_NVM_COMMAND_LAST; 2576 } 2577 rc = bce_nvram_write_dword(sc, addr, 2578 &flash_buffer[i], cmd_flags); 2579 2580 if (rc != 0) 2581 goto bce_nvram_write_locked_exit; 2582 2583 cmd_flags = 0; 2584 } 2585 } 2586 2587 /* Disable writes to flash interface (lock write-protect) */ 2588 bce_disable_nvram_write(sc); 2589 2590 /* Disable access to flash interface */ 2591 bce_disable_nvram_access(sc); 2592 bce_release_nvram_lock(sc); 2593 2594 /* Increment written */ 2595 written += data_end - data_start; 2596 } 2597 2598 goto bce_nvram_write_exit; 2599 2600 bce_nvram_write_locked_exit: 2601 bce_disable_nvram_write(sc); 2602 bce_disable_nvram_access(sc); 2603 bce_release_nvram_lock(sc); 2604 2605 bce_nvram_write_exit: 2606 if (align_start || align_end) 2607 free(buf, M_DEVBUF); 2608 2609 DBEXIT(BCE_VERBOSE_NVRAM); 2610 return (rc); 2611 } 2612 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2613 2614 2615 /****************************************************************************/ 2616 /* Verifies that NVRAM is accessible and contains valid data. */ 2617 /* */ 2618 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2619 /* correct. */ 2620 /* */ 2621 /* Returns: */ 2622 /* 0 on success, positive value on failure. */ 2623 /****************************************************************************/ 2624 static int 2625 bce_nvram_test(struct bce_softc *sc) 2626 { 2627 u32 buf[BCE_NVRAM_SIZE / 4]; 2628 u8 *data = (u8 *) buf; 2629 int rc = 0; 2630 u32 magic, csum; 2631 2632 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2633 2634 /* 2635 * Check that the device NVRAM is valid by reading 2636 * the magic value at offset 0. 2637 */ 2638 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) { 2639 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", 2640 __FILE__, __LINE__); 2641 goto bce_nvram_test_exit; 2642 } 2643 2644 /* 2645 * Verify that offset 0 of the NVRAM contains 2646 * a valid magic number. 2647 */ 2648 magic = bce_be32toh(buf[0]); 2649 if (magic != BCE_NVRAM_MAGIC) { 2650 rc = ENODEV; 2651 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! " 2652 "Expected: 0x%08X, Found: 0x%08X\n", 2653 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 2654 goto bce_nvram_test_exit; 2655 } 2656 2657 /* 2658 * Verify that the device NVRAM includes valid 2659 * configuration data. 2660 */ 2661 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) { 2662 BCE_PRINTF("%s(%d): Unable to read manufacturing " 2663 "Information from NVRAM!\n", __FILE__, __LINE__); 2664 goto bce_nvram_test_exit; 2665 } 2666 2667 csum = ether_crc32_le(data, 0x100); 2668 if (csum != BCE_CRC32_RESIDUAL) { 2669 rc = ENODEV; 2670 BCE_PRINTF("%s(%d): Invalid manufacturing information " 2671 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2672 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2673 goto bce_nvram_test_exit; 2674 } 2675 2676 csum = ether_crc32_le(data + 0x100, 0x100); 2677 if (csum != BCE_CRC32_RESIDUAL) { 2678 rc = ENODEV; 2679 BCE_PRINTF("%s(%d): Invalid feature configuration " 2680 "information NVRAM CRC! Expected: 0x%08X, " 2681 "Found: 08%08X\n", __FILE__, __LINE__, 2682 BCE_CRC32_RESIDUAL, csum); 2683 } 2684 2685 bce_nvram_test_exit: 2686 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2687 return rc; 2688 } 2689 2690 2691 /****************************************************************************/ 2692 /* Identifies the current media type of the controller and sets the PHY */ 2693 /* address. */ 2694 /* */ 2695 /* Returns: */ 2696 /* Nothing. */ 2697 /****************************************************************************/ 2698 static void 2699 bce_get_media(struct bce_softc *sc) 2700 { 2701 u32 val; 2702 2703 DBENTER(BCE_VERBOSE_PHY); 2704 2705 /* Assume PHY address for copper controllers. */ 2706 sc->bce_phy_addr = 1; 2707 2708 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 2709 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL); 2710 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID; 2711 u32 strap; 2712 2713 /* 2714 * The BCM5709S is software configurable 2715 * for Copper or SerDes operation. 2716 */ 2717 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 2718 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 2719 "for copper.\n"); 2720 goto bce_get_media_exit; 2721 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 2722 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 2723 "for dual media.\n"); 2724 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2725 goto bce_get_media_exit; 2726 } 2727 2728 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 2729 strap = (val & 2730 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 2731 else 2732 strap = (val & 2733 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 2734 2735 if (pci_get_function(sc->bce_dev) == 0) { 2736 switch (strap) { 2737 case 0x4: 2738 case 0x5: 2739 case 0x6: 2740 DBPRINT(sc, BCE_INFO_LOAD, 2741 "BCM5709 s/w configured for SerDes.\n"); 2742 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2743 break; 2744 default: 2745 DBPRINT(sc, BCE_INFO_LOAD, 2746 "BCM5709 s/w configured for Copper.\n"); 2747 break; 2748 } 2749 } else { 2750 switch (strap) { 2751 case 0x1: 2752 case 0x2: 2753 case 0x4: 2754 DBPRINT(sc, BCE_INFO_LOAD, 2755 "BCM5709 s/w configured for SerDes.\n"); 2756 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2757 break; 2758 default: 2759 DBPRINT(sc, BCE_INFO_LOAD, 2760 "BCM5709 s/w configured for Copper.\n"); 2761 break; 2762 } 2763 } 2764 2765 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) 2766 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2767 2768 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 2769 2770 sc->bce_flags |= BCE_NO_WOL_FLAG; 2771 2772 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 2773 sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG; 2774 2775 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 2776 /* 5708S/09S/16S use a separate PHY for SerDes. */ 2777 sc->bce_phy_addr = 2; 2778 2779 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 2780 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 2781 sc->bce_phy_flags |= 2782 BCE_PHY_2_5G_CAPABLE_FLAG; 2783 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb " 2784 "capable adapter\n"); 2785 } 2786 } 2787 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) || 2788 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) 2789 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG; 2790 2791 bce_get_media_exit: 2792 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY), 2793 "Using PHY address %d.\n", sc->bce_phy_addr); 2794 2795 DBEXIT(BCE_VERBOSE_PHY); 2796 } 2797 2798 2799 /****************************************************************************/ 2800 /* Performs PHY initialization required before MII drivers access the */ 2801 /* device. */ 2802 /* */ 2803 /* Returns: */ 2804 /* Nothing. */ 2805 /****************************************************************************/ 2806 static void 2807 bce_init_media(struct bce_softc *sc) 2808 { 2809 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 2810 /* 2811 * Configure 5709S/5716S PHYs to use traditional IEEE 2812 * Clause 22 method. Otherwise we have no way to attach 2813 * the PHY in mii(4) layer. PHY specific configuration 2814 * is done in mii layer. 2815 */ 2816 2817 /* Select auto-negotiation MMD of the PHY. */ 2818 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 2819 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 2820 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 2821 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 2822 2823 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */ 2824 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 2825 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 2826 } 2827 } 2828 2829 2830 /****************************************************************************/ 2831 /* Free any DMA memory owned by the driver. */ 2832 /* */ 2833 /* Scans through each data structre that requires DMA memory and frees */ 2834 /* the memory if allocated. */ 2835 /* */ 2836 /* Returns: */ 2837 /* Nothing. */ 2838 /****************************************************************************/ 2839 static void 2840 bce_dma_free(struct bce_softc *sc) 2841 { 2842 int i; 2843 2844 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 2845 2846 /* Free, unmap, and destroy the status block. */ 2847 if (sc->status_block != NULL) { 2848 bus_dmamem_free( 2849 sc->status_tag, 2850 sc->status_block, 2851 sc->status_map); 2852 sc->status_block = NULL; 2853 } 2854 2855 if (sc->status_map != NULL) { 2856 bus_dmamap_unload( 2857 sc->status_tag, 2858 sc->status_map); 2859 bus_dmamap_destroy(sc->status_tag, 2860 sc->status_map); 2861 sc->status_map = NULL; 2862 } 2863 2864 if (sc->status_tag != NULL) { 2865 bus_dma_tag_destroy(sc->status_tag); 2866 sc->status_tag = NULL; 2867 } 2868 2869 2870 /* Free, unmap, and destroy the statistics block. */ 2871 if (sc->stats_block != NULL) { 2872 bus_dmamem_free( 2873 sc->stats_tag, 2874 sc->stats_block, 2875 sc->stats_map); 2876 sc->stats_block = NULL; 2877 } 2878 2879 if (sc->stats_map != NULL) { 2880 bus_dmamap_unload( 2881 sc->stats_tag, 2882 sc->stats_map); 2883 bus_dmamap_destroy(sc->stats_tag, 2884 sc->stats_map); 2885 sc->stats_map = NULL; 2886 } 2887 2888 if (sc->stats_tag != NULL) { 2889 bus_dma_tag_destroy(sc->stats_tag); 2890 sc->stats_tag = NULL; 2891 } 2892 2893 2894 /* Free, unmap and destroy all context memory pages. */ 2895 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 2896 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 2897 for (i = 0; i < sc->ctx_pages; i++ ) { 2898 if (sc->ctx_block[i] != NULL) { 2899 bus_dmamem_free( 2900 sc->ctx_tag, 2901 sc->ctx_block[i], 2902 sc->ctx_map[i]); 2903 sc->ctx_block[i] = NULL; 2904 } 2905 2906 if (sc->ctx_map[i] != NULL) { 2907 bus_dmamap_unload( 2908 sc->ctx_tag, 2909 sc->ctx_map[i]); 2910 bus_dmamap_destroy( 2911 sc->ctx_tag, 2912 sc->ctx_map[i]); 2913 sc->ctx_map[i] = NULL; 2914 } 2915 } 2916 2917 /* Destroy the context memory tag. */ 2918 if (sc->ctx_tag != NULL) { 2919 bus_dma_tag_destroy(sc->ctx_tag); 2920 sc->ctx_tag = NULL; 2921 } 2922 } 2923 2924 2925 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2926 for (i = 0; i < TX_PAGES; i++ ) { 2927 if (sc->tx_bd_chain[i] != NULL) { 2928 bus_dmamem_free( 2929 sc->tx_bd_chain_tag, 2930 sc->tx_bd_chain[i], 2931 sc->tx_bd_chain_map[i]); 2932 sc->tx_bd_chain[i] = NULL; 2933 } 2934 2935 if (sc->tx_bd_chain_map[i] != NULL) { 2936 bus_dmamap_unload( 2937 sc->tx_bd_chain_tag, 2938 sc->tx_bd_chain_map[i]); 2939 bus_dmamap_destroy( 2940 sc->tx_bd_chain_tag, 2941 sc->tx_bd_chain_map[i]); 2942 sc->tx_bd_chain_map[i] = NULL; 2943 } 2944 } 2945 2946 /* Destroy the TX buffer descriptor tag. */ 2947 if (sc->tx_bd_chain_tag != NULL) { 2948 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 2949 sc->tx_bd_chain_tag = NULL; 2950 } 2951 2952 2953 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2954 for (i = 0; i < RX_PAGES; i++ ) { 2955 if (sc->rx_bd_chain[i] != NULL) { 2956 bus_dmamem_free( 2957 sc->rx_bd_chain_tag, 2958 sc->rx_bd_chain[i], 2959 sc->rx_bd_chain_map[i]); 2960 sc->rx_bd_chain[i] = NULL; 2961 } 2962 2963 if (sc->rx_bd_chain_map[i] != NULL) { 2964 bus_dmamap_unload( 2965 sc->rx_bd_chain_tag, 2966 sc->rx_bd_chain_map[i]); 2967 bus_dmamap_destroy( 2968 sc->rx_bd_chain_tag, 2969 sc->rx_bd_chain_map[i]); 2970 sc->rx_bd_chain_map[i] = NULL; 2971 } 2972 } 2973 2974 /* Destroy the RX buffer descriptor tag. */ 2975 if (sc->rx_bd_chain_tag != NULL) { 2976 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 2977 sc->rx_bd_chain_tag = NULL; 2978 } 2979 2980 2981 #ifdef BCE_JUMBO_HDRSPLIT 2982 /* Free, unmap and destroy all page buffer descriptor chain pages. */ 2983 for (i = 0; i < PG_PAGES; i++ ) { 2984 if (sc->pg_bd_chain[i] != NULL) { 2985 bus_dmamem_free( 2986 sc->pg_bd_chain_tag, 2987 sc->pg_bd_chain[i], 2988 sc->pg_bd_chain_map[i]); 2989 sc->pg_bd_chain[i] = NULL; 2990 } 2991 2992 if (sc->pg_bd_chain_map[i] != NULL) { 2993 bus_dmamap_unload( 2994 sc->pg_bd_chain_tag, 2995 sc->pg_bd_chain_map[i]); 2996 bus_dmamap_destroy( 2997 sc->pg_bd_chain_tag, 2998 sc->pg_bd_chain_map[i]); 2999 sc->pg_bd_chain_map[i] = NULL; 3000 } 3001 } 3002 3003 /* Destroy the page buffer descriptor tag. */ 3004 if (sc->pg_bd_chain_tag != NULL) { 3005 bus_dma_tag_destroy(sc->pg_bd_chain_tag); 3006 sc->pg_bd_chain_tag = NULL; 3007 } 3008 #endif 3009 3010 3011 /* Unload and destroy the TX mbuf maps. */ 3012 for (i = 0; i < TOTAL_TX_BD; i++) { 3013 if (sc->tx_mbuf_map[i] != NULL) { 3014 bus_dmamap_unload(sc->tx_mbuf_tag, 3015 sc->tx_mbuf_map[i]); 3016 bus_dmamap_destroy(sc->tx_mbuf_tag, 3017 sc->tx_mbuf_map[i]); 3018 sc->tx_mbuf_map[i] = NULL; 3019 } 3020 } 3021 3022 /* Destroy the TX mbuf tag. */ 3023 if (sc->tx_mbuf_tag != NULL) { 3024 bus_dma_tag_destroy(sc->tx_mbuf_tag); 3025 sc->tx_mbuf_tag = NULL; 3026 } 3027 3028 /* Unload and destroy the RX mbuf maps. */ 3029 for (i = 0; i < TOTAL_RX_BD; i++) { 3030 if (sc->rx_mbuf_map[i] != NULL) { 3031 bus_dmamap_unload(sc->rx_mbuf_tag, 3032 sc->rx_mbuf_map[i]); 3033 bus_dmamap_destroy(sc->rx_mbuf_tag, 3034 sc->rx_mbuf_map[i]); 3035 sc->rx_mbuf_map[i] = NULL; 3036 } 3037 } 3038 3039 /* Destroy the RX mbuf tag. */ 3040 if (sc->rx_mbuf_tag != NULL) { 3041 bus_dma_tag_destroy(sc->rx_mbuf_tag); 3042 sc->rx_mbuf_tag = NULL; 3043 } 3044 3045 #ifdef BCE_JUMBO_HDRSPLIT 3046 /* Unload and destroy the page mbuf maps. */ 3047 for (i = 0; i < TOTAL_PG_BD; i++) { 3048 if (sc->pg_mbuf_map[i] != NULL) { 3049 bus_dmamap_unload(sc->pg_mbuf_tag, 3050 sc->pg_mbuf_map[i]); 3051 bus_dmamap_destroy(sc->pg_mbuf_tag, 3052 sc->pg_mbuf_map[i]); 3053 sc->pg_mbuf_map[i] = NULL; 3054 } 3055 } 3056 3057 /* Destroy the page mbuf tag. */ 3058 if (sc->pg_mbuf_tag != NULL) { 3059 bus_dma_tag_destroy(sc->pg_mbuf_tag); 3060 sc->pg_mbuf_tag = NULL; 3061 } 3062 #endif 3063 3064 /* Destroy the parent tag */ 3065 if (sc->parent_tag != NULL) { 3066 bus_dma_tag_destroy(sc->parent_tag); 3067 sc->parent_tag = NULL; 3068 } 3069 3070 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3071 } 3072 3073 3074 /****************************************************************************/ 3075 /* Get DMA memory from the OS. */ 3076 /* */ 3077 /* Validates that the OS has provided DMA buffers in response to a */ 3078 /* bus_dmamap_load() call and saves the physical address of those buffers. */ 3079 /* When the callback is used the OS will return 0 for the mapping function */ 3080 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 3081 /* failures back to the caller. */ 3082 /* */ 3083 /* Returns: */ 3084 /* Nothing. */ 3085 /****************************************************************************/ 3086 static void 3087 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3088 { 3089 bus_addr_t *busaddr = arg; 3090 3091 KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!", 3092 __FUNCTION__, nseg)); 3093 /* Simulate a mapping failure. */ 3094 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control), 3095 error = ENOMEM); 3096 3097 /* ToDo: How to increment debug sim_count variable here? */ 3098 3099 /* Check for an error and signal the caller that an error occurred. */ 3100 if (error) { 3101 *busaddr = 0; 3102 } else { 3103 *busaddr = segs->ds_addr; 3104 } 3105 3106 return; 3107 } 3108 3109 3110 /****************************************************************************/ 3111 /* Allocate any DMA memory needed by the driver. */ 3112 /* */ 3113 /* Allocates DMA memory needed for the various global structures needed by */ 3114 /* hardware. */ 3115 /* */ 3116 /* Memory alignment requirements: */ 3117 /* +-----------------+----------+----------+----------+----------+ */ 3118 /* | | 5706 | 5708 | 5709 | 5716 | */ 3119 /* +-----------------+----------+----------+----------+----------+ */ 3120 /* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3121 /* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3122 /* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */ 3123 /* |PG Buffers | none | none | none | none | */ 3124 /* |TX Buffers | none | none | none | none | */ 3125 /* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */ 3126 /* |Context Memory | | | | | */ 3127 /* +-----------------+----------+----------+----------+----------+ */ 3128 /* */ 3129 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */ 3130 /* */ 3131 /* Returns: */ 3132 /* 0 for success, positive value for failure. */ 3133 /****************************************************************************/ 3134 static int 3135 bce_dma_alloc(device_t dev) 3136 { 3137 struct bce_softc *sc; 3138 int i, error, rc = 0; 3139 bus_size_t max_size, max_seg_size; 3140 int max_segments; 3141 3142 sc = device_get_softc(dev); 3143 3144 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3145 3146 /* 3147 * Allocate the parent bus DMA tag appropriate for PCI. 3148 */ 3149 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY, 3150 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3151 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3152 &sc->parent_tag)) { 3153 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 3154 __FILE__, __LINE__); 3155 rc = ENOMEM; 3156 goto bce_dma_alloc_exit; 3157 } 3158 3159 /* 3160 * Create a DMA tag for the status block, allocate and clear the 3161 * memory, map the memory into DMA space, and fetch the physical 3162 * address of the block. 3163 */ 3164 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3165 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3166 NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ, 3167 0, NULL, NULL, &sc->status_tag)) { 3168 BCE_PRINTF("%s(%d): Could not allocate status block " 3169 "DMA tag!\n", __FILE__, __LINE__); 3170 rc = ENOMEM; 3171 goto bce_dma_alloc_exit; 3172 } 3173 3174 if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block, 3175 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3176 &sc->status_map)) { 3177 BCE_PRINTF("%s(%d): Could not allocate status block " 3178 "DMA memory!\n", __FILE__, __LINE__); 3179 rc = ENOMEM; 3180 goto bce_dma_alloc_exit; 3181 } 3182 3183 error = bus_dmamap_load(sc->status_tag, sc->status_map, 3184 sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr, 3185 &sc->status_block_paddr, BUS_DMA_NOWAIT); 3186 3187 if (error) { 3188 BCE_PRINTF("%s(%d): Could not map status block " 3189 "DMA memory!\n", __FILE__, __LINE__); 3190 rc = ENOMEM; 3191 goto bce_dma_alloc_exit; 3192 } 3193 3194 DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n", 3195 __FUNCTION__, (uintmax_t) sc->status_block_paddr); 3196 3197 /* 3198 * Create a DMA tag for the statistics block, allocate and clear the 3199 * memory, map the memory into DMA space, and fetch the physical 3200 * address of the block. 3201 */ 3202 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3203 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3204 NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ, 3205 0, NULL, NULL, &sc->stats_tag)) { 3206 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3207 "DMA tag!\n", __FILE__, __LINE__); 3208 rc = ENOMEM; 3209 goto bce_dma_alloc_exit; 3210 } 3211 3212 if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block, 3213 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) { 3214 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3215 "DMA memory!\n", __FILE__, __LINE__); 3216 rc = ENOMEM; 3217 goto bce_dma_alloc_exit; 3218 } 3219 3220 error = bus_dmamap_load(sc->stats_tag, sc->stats_map, 3221 sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr, 3222 &sc->stats_block_paddr, BUS_DMA_NOWAIT); 3223 3224 if(error) { 3225 BCE_PRINTF("%s(%d): Could not map statistics block " 3226 "DMA memory!\n", __FILE__, __LINE__); 3227 rc = ENOMEM; 3228 goto bce_dma_alloc_exit; 3229 } 3230 3231 DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n", 3232 __FUNCTION__, (uintmax_t) sc->stats_block_paddr); 3233 3234 /* BCM5709 uses host memory as cache for context memory. */ 3235 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 3236 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 3237 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 3238 if (sc->ctx_pages == 0) 3239 sc->ctx_pages = 1; 3240 3241 DBRUNIF((sc->ctx_pages > 512), 3242 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n", 3243 __FILE__, __LINE__, sc->ctx_pages)); 3244 3245 /* 3246 * Create a DMA tag for the context pages, 3247 * allocate and clear the memory, map the 3248 * memory into DMA space, and fetch the 3249 * physical address of the block. 3250 */ 3251 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3252 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3253 NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE, 3254 0, NULL, NULL, &sc->ctx_tag)) { 3255 BCE_PRINTF("%s(%d): Could not allocate CTX " 3256 "DMA tag!\n", __FILE__, __LINE__); 3257 rc = ENOMEM; 3258 goto bce_dma_alloc_exit; 3259 } 3260 3261 for (i = 0; i < sc->ctx_pages; i++) { 3262 3263 if(bus_dmamem_alloc(sc->ctx_tag, 3264 (void **)&sc->ctx_block[i], 3265 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3266 &sc->ctx_map[i])) { 3267 BCE_PRINTF("%s(%d): Could not allocate CTX " 3268 "DMA memory!\n", __FILE__, __LINE__); 3269 rc = ENOMEM; 3270 goto bce_dma_alloc_exit; 3271 } 3272 3273 error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i], 3274 sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr, 3275 &sc->ctx_paddr[i], BUS_DMA_NOWAIT); 3276 3277 if (error) { 3278 BCE_PRINTF("%s(%d): Could not map CTX " 3279 "DMA memory!\n", __FILE__, __LINE__); 3280 rc = ENOMEM; 3281 goto bce_dma_alloc_exit; 3282 } 3283 3284 DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] " 3285 "= 0x%jX\n", __FUNCTION__, i, 3286 (uintmax_t) sc->ctx_paddr[i]); 3287 } 3288 } 3289 3290 /* 3291 * Create a DMA tag for the TX buffer descriptor chain, 3292 * allocate and clear the memory, and fetch the 3293 * physical address of the block. 3294 */ 3295 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY, 3296 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3297 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0, 3298 NULL, NULL, &sc->tx_bd_chain_tag)) { 3299 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3300 "chain DMA tag!\n", __FILE__, __LINE__); 3301 rc = ENOMEM; 3302 goto bce_dma_alloc_exit; 3303 } 3304 3305 for (i = 0; i < TX_PAGES; i++) { 3306 3307 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 3308 (void **)&sc->tx_bd_chain[i], 3309 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3310 &sc->tx_bd_chain_map[i])) { 3311 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3312 "chain DMA memory!\n", __FILE__, __LINE__); 3313 rc = ENOMEM; 3314 goto bce_dma_alloc_exit; 3315 } 3316 3317 error = bus_dmamap_load(sc->tx_bd_chain_tag, 3318 sc->tx_bd_chain_map[i], sc->tx_bd_chain[i], 3319 BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3320 &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3321 3322 if (error) { 3323 BCE_PRINTF("%s(%d): Could not map TX descriptor " 3324 "chain DMA memory!\n", __FILE__, __LINE__); 3325 rc = ENOMEM; 3326 goto bce_dma_alloc_exit; 3327 } 3328 3329 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = " 3330 "0x%jX\n", __FUNCTION__, i, 3331 (uintmax_t) sc->tx_bd_chain_paddr[i]); 3332 } 3333 3334 /* Check the required size before mapping to conserve resources. */ 3335 if (bce_tso_enable) { 3336 max_size = BCE_TSO_MAX_SIZE; 3337 max_segments = BCE_MAX_SEGMENTS; 3338 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 3339 } else { 3340 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 3341 max_segments = BCE_MAX_SEGMENTS; 3342 max_seg_size = MCLBYTES; 3343 } 3344 3345 /* Create a DMA tag for TX mbufs. */ 3346 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3347 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size, 3348 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) { 3349 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 3350 __FILE__, __LINE__); 3351 rc = ENOMEM; 3352 goto bce_dma_alloc_exit; 3353 } 3354 3355 /* Create DMA maps for the TX mbufs clusters. */ 3356 for (i = 0; i < TOTAL_TX_BD; i++) { 3357 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 3358 &sc->tx_mbuf_map[i])) { 3359 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA " 3360 "map!\n", __FILE__, __LINE__); 3361 rc = ENOMEM; 3362 goto bce_dma_alloc_exit; 3363 } 3364 } 3365 3366 /* 3367 * Create a DMA tag for the RX buffer descriptor chain, 3368 * allocate and clear the memory, and fetch the physical 3369 * address of the blocks. 3370 */ 3371 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3372 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, 3373 sc->max_bus_addr, NULL, NULL, 3374 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ, 3375 0, NULL, NULL, &sc->rx_bd_chain_tag)) { 3376 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 3377 "DMA tag!\n", __FILE__, __LINE__); 3378 rc = ENOMEM; 3379 goto bce_dma_alloc_exit; 3380 } 3381 3382 for (i = 0; i < RX_PAGES; i++) { 3383 3384 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 3385 (void **)&sc->rx_bd_chain[i], 3386 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3387 &sc->rx_bd_chain_map[i])) { 3388 BCE_PRINTF("%s(%d): Could not allocate RX descriptor " 3389 "chain DMA memory!\n", __FILE__, __LINE__); 3390 rc = ENOMEM; 3391 goto bce_dma_alloc_exit; 3392 } 3393 3394 error = bus_dmamap_load(sc->rx_bd_chain_tag, 3395 sc->rx_bd_chain_map[i], sc->rx_bd_chain[i], 3396 BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3397 &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3398 3399 if (error) { 3400 BCE_PRINTF("%s(%d): Could not map RX descriptor " 3401 "chain DMA memory!\n", __FILE__, __LINE__); 3402 rc = ENOMEM; 3403 goto bce_dma_alloc_exit; 3404 } 3405 3406 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = " 3407 "0x%jX\n", __FUNCTION__, i, 3408 (uintmax_t) sc->rx_bd_chain_paddr[i]); 3409 } 3410 3411 /* 3412 * Create a DMA tag for RX mbufs. 3413 */ 3414 #ifdef BCE_JUMBO_HDRSPLIT 3415 max_size = max_seg_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ? 3416 MCLBYTES : sc->rx_bd_mbuf_alloc_size); 3417 #else 3418 max_size = max_seg_size = MJUM9BYTES; 3419 #endif 3420 max_segments = 1; 3421 3422 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag " 3423 "(max size = 0x%jX max segments = %d, max segment " 3424 "size = 0x%jX)\n", __FUNCTION__, (uintmax_t) max_size, 3425 max_segments, (uintmax_t) max_seg_size); 3426 3427 if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN, 3428 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3429 max_size, max_segments, max_seg_size, 0, NULL, NULL, 3430 &sc->rx_mbuf_tag)) { 3431 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 3432 __FILE__, __LINE__); 3433 rc = ENOMEM; 3434 goto bce_dma_alloc_exit; 3435 } 3436 3437 /* Create DMA maps for the RX mbuf clusters. */ 3438 for (i = 0; i < TOTAL_RX_BD; i++) { 3439 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 3440 &sc->rx_mbuf_map[i])) { 3441 BCE_PRINTF("%s(%d): Unable to create RX mbuf " 3442 "DMA map!\n", __FILE__, __LINE__); 3443 rc = ENOMEM; 3444 goto bce_dma_alloc_exit; 3445 } 3446 } 3447 3448 #ifdef BCE_JUMBO_HDRSPLIT 3449 /* 3450 * Create a DMA tag for the page buffer descriptor chain, 3451 * allocate and clear the memory, and fetch the physical 3452 * address of the blocks. 3453 */ 3454 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3455 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr, 3456 NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ, 3457 0, NULL, NULL, &sc->pg_bd_chain_tag)) { 3458 BCE_PRINTF("%s(%d): Could not allocate page descriptor " 3459 "chain DMA tag!\n", __FILE__, __LINE__); 3460 rc = ENOMEM; 3461 goto bce_dma_alloc_exit; 3462 } 3463 3464 for (i = 0; i < PG_PAGES; i++) { 3465 3466 if (bus_dmamem_alloc(sc->pg_bd_chain_tag, 3467 (void **)&sc->pg_bd_chain[i], 3468 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3469 &sc->pg_bd_chain_map[i])) { 3470 BCE_PRINTF("%s(%d): Could not allocate page " 3471 "descriptor chain DMA memory!\n", 3472 __FILE__, __LINE__); 3473 rc = ENOMEM; 3474 goto bce_dma_alloc_exit; 3475 } 3476 3477 error = bus_dmamap_load(sc->pg_bd_chain_tag, 3478 sc->pg_bd_chain_map[i], sc->pg_bd_chain[i], 3479 BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr, 3480 &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3481 3482 if (error) { 3483 BCE_PRINTF("%s(%d): Could not map page descriptor " 3484 "chain DMA memory!\n", __FILE__, __LINE__); 3485 rc = ENOMEM; 3486 goto bce_dma_alloc_exit; 3487 } 3488 3489 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = " 3490 "0x%jX\n", __FUNCTION__, i, 3491 (uintmax_t) sc->pg_bd_chain_paddr[i]); 3492 } 3493 3494 /* 3495 * Create a DMA tag for page mbufs. 3496 */ 3497 max_size = max_seg_size = ((sc->pg_bd_mbuf_alloc_size < MCLBYTES) ? 3498 MCLBYTES : sc->pg_bd_mbuf_alloc_size); 3499 3500 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3501 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3502 max_size, 1, max_seg_size, 0, NULL, NULL, &sc->pg_mbuf_tag)) { 3503 BCE_PRINTF("%s(%d): Could not allocate page mbuf " 3504 "DMA tag!\n", __FILE__, __LINE__); 3505 rc = ENOMEM; 3506 goto bce_dma_alloc_exit; 3507 } 3508 3509 /* Create DMA maps for the page mbuf clusters. */ 3510 for (i = 0; i < TOTAL_PG_BD; i++) { 3511 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT, 3512 &sc->pg_mbuf_map[i])) { 3513 BCE_PRINTF("%s(%d): Unable to create page mbuf " 3514 "DMA map!\n", __FILE__, __LINE__); 3515 rc = ENOMEM; 3516 goto bce_dma_alloc_exit; 3517 } 3518 } 3519 #endif 3520 3521 bce_dma_alloc_exit: 3522 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3523 return(rc); 3524 } 3525 3526 3527 /****************************************************************************/ 3528 /* Release all resources used by the driver. */ 3529 /* */ 3530 /* Releases all resources acquired by the driver including interrupts, */ 3531 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 3532 /* */ 3533 /* Returns: */ 3534 /* Nothing. */ 3535 /****************************************************************************/ 3536 static void 3537 bce_release_resources(struct bce_softc *sc) 3538 { 3539 device_t dev; 3540 3541 DBENTER(BCE_VERBOSE_RESET); 3542 3543 dev = sc->bce_dev; 3544 3545 bce_dma_free(sc); 3546 3547 if (sc->bce_intrhand != NULL) { 3548 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 3549 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 3550 } 3551 3552 if (sc->bce_res_irq != NULL) { 3553 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 3554 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid, 3555 sc->bce_res_irq); 3556 } 3557 3558 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) { 3559 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n"); 3560 pci_release_msi(dev); 3561 } 3562 3563 if (sc->bce_res_mem != NULL) { 3564 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 3565 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 3566 sc->bce_res_mem); 3567 } 3568 3569 if (sc->bce_ifp != NULL) { 3570 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 3571 if_free(sc->bce_ifp); 3572 } 3573 3574 if (mtx_initialized(&sc->bce_mtx)) 3575 BCE_LOCK_DESTROY(sc); 3576 3577 DBEXIT(BCE_VERBOSE_RESET); 3578 } 3579 3580 3581 /****************************************************************************/ 3582 /* Firmware synchronization. */ 3583 /* */ 3584 /* Before performing certain events such as a chip reset, synchronize with */ 3585 /* the firmware first. */ 3586 /* */ 3587 /* Returns: */ 3588 /* 0 for success, positive value for failure. */ 3589 /****************************************************************************/ 3590 static int 3591 bce_fw_sync(struct bce_softc *sc, u32 msg_data) 3592 { 3593 int i, rc = 0; 3594 u32 val; 3595 3596 DBENTER(BCE_VERBOSE_RESET); 3597 3598 /* Don't waste any time if we've timed out before. */ 3599 if (sc->bce_fw_timed_out == TRUE) { 3600 rc = EBUSY; 3601 goto bce_fw_sync_exit; 3602 } 3603 3604 /* Increment the message sequence number. */ 3605 sc->bce_fw_wr_seq++; 3606 msg_data |= sc->bce_fw_wr_seq; 3607 3608 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = " 3609 "0x%08X\n", msg_data); 3610 3611 /* Send the message to the bootcode driver mailbox. */ 3612 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3613 3614 /* Wait for the bootcode to acknowledge the message. */ 3615 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 3616 /* Check for a response in the bootcode firmware mailbox. */ 3617 val = bce_shmem_rd(sc, BCE_FW_MB); 3618 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 3619 break; 3620 DELAY(1000); 3621 } 3622 3623 /* If we've timed out, tell bootcode that we've stopped waiting. */ 3624 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 3625 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 3626 3627 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 3628 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 3629 3630 msg_data &= ~BCE_DRV_MSG_CODE; 3631 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 3632 3633 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3634 3635 sc->bce_fw_timed_out = TRUE; 3636 rc = EBUSY; 3637 } 3638 3639 bce_fw_sync_exit: 3640 DBEXIT(BCE_VERBOSE_RESET); 3641 return (rc); 3642 } 3643 3644 3645 /****************************************************************************/ 3646 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 3647 /* */ 3648 /* Returns: */ 3649 /* Nothing. */ 3650 /****************************************************************************/ 3651 static void 3652 bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code, 3653 u32 rv2p_code_len, u32 rv2p_proc) 3654 { 3655 int i; 3656 u32 val; 3657 3658 DBENTER(BCE_VERBOSE_RESET); 3659 3660 /* Set the page size used by RV2P. */ 3661 if (rv2p_proc == RV2P_PROC2) { 3662 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE); 3663 } 3664 3665 for (i = 0; i < rv2p_code_len; i += 8) { 3666 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 3667 rv2p_code++; 3668 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 3669 rv2p_code++; 3670 3671 if (rv2p_proc == RV2P_PROC1) { 3672 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 3673 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 3674 } 3675 else { 3676 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 3677 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 3678 } 3679 } 3680 3681 /* Reset the processor, un-stall is done later. */ 3682 if (rv2p_proc == RV2P_PROC1) { 3683 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 3684 } 3685 else { 3686 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 3687 } 3688 3689 DBEXIT(BCE_VERBOSE_RESET); 3690 } 3691 3692 3693 /****************************************************************************/ 3694 /* Load RISC processor firmware. */ 3695 /* */ 3696 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 3697 /* associated with a particular processor. */ 3698 /* */ 3699 /* Returns: */ 3700 /* Nothing. */ 3701 /****************************************************************************/ 3702 static void 3703 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 3704 struct fw_info *fw) 3705 { 3706 u32 offset; 3707 3708 DBENTER(BCE_VERBOSE_RESET); 3709 3710 bce_halt_cpu(sc, cpu_reg); 3711 3712 /* Load the Text area. */ 3713 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 3714 if (fw->text) { 3715 int j; 3716 3717 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 3718 REG_WR_IND(sc, offset, fw->text[j]); 3719 } 3720 } 3721 3722 /* Load the Data area. */ 3723 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 3724 if (fw->data) { 3725 int j; 3726 3727 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 3728 REG_WR_IND(sc, offset, fw->data[j]); 3729 } 3730 } 3731 3732 /* Load the SBSS area. */ 3733 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 3734 if (fw->sbss) { 3735 int j; 3736 3737 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 3738 REG_WR_IND(sc, offset, fw->sbss[j]); 3739 } 3740 } 3741 3742 /* Load the BSS area. */ 3743 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 3744 if (fw->bss) { 3745 int j; 3746 3747 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 3748 REG_WR_IND(sc, offset, fw->bss[j]); 3749 } 3750 } 3751 3752 /* Load the Read-Only area. */ 3753 offset = cpu_reg->spad_base + 3754 (fw->rodata_addr - cpu_reg->mips_view_base); 3755 if (fw->rodata) { 3756 int j; 3757 3758 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 3759 REG_WR_IND(sc, offset, fw->rodata[j]); 3760 } 3761 } 3762 3763 /* Clear the pre-fetch instruction and set the FW start address. */ 3764 REG_WR_IND(sc, cpu_reg->inst, 0); 3765 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 3766 3767 DBEXIT(BCE_VERBOSE_RESET); 3768 } 3769 3770 3771 /****************************************************************************/ 3772 /* Starts the RISC processor. */ 3773 /* */ 3774 /* Assumes the CPU starting address has already been set. */ 3775 /* */ 3776 /* Returns: */ 3777 /* Nothing. */ 3778 /****************************************************************************/ 3779 static void 3780 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 3781 { 3782 u32 val; 3783 3784 DBENTER(BCE_VERBOSE_RESET); 3785 3786 /* Start the CPU. */ 3787 val = REG_RD_IND(sc, cpu_reg->mode); 3788 val &= ~cpu_reg->mode_value_halt; 3789 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 3790 REG_WR_IND(sc, cpu_reg->mode, val); 3791 3792 DBEXIT(BCE_VERBOSE_RESET); 3793 } 3794 3795 3796 /****************************************************************************/ 3797 /* Halts the RISC processor. */ 3798 /* */ 3799 /* Returns: */ 3800 /* Nothing. */ 3801 /****************************************************************************/ 3802 static void 3803 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 3804 { 3805 u32 val; 3806 3807 DBENTER(BCE_VERBOSE_RESET); 3808 3809 /* Halt the CPU. */ 3810 val = REG_RD_IND(sc, cpu_reg->mode); 3811 val |= cpu_reg->mode_value_halt; 3812 REG_WR_IND(sc, cpu_reg->mode, val); 3813 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 3814 3815 DBEXIT(BCE_VERBOSE_RESET); 3816 } 3817 3818 3819 /****************************************************************************/ 3820 /* Initialize the RX CPU. */ 3821 /* */ 3822 /* Returns: */ 3823 /* Nothing. */ 3824 /****************************************************************************/ 3825 static void 3826 bce_start_rxp_cpu(struct bce_softc *sc) 3827 { 3828 struct cpu_reg cpu_reg; 3829 3830 DBENTER(BCE_VERBOSE_RESET); 3831 3832 cpu_reg.mode = BCE_RXP_CPU_MODE; 3833 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 3834 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 3835 cpu_reg.state = BCE_RXP_CPU_STATE; 3836 cpu_reg.state_value_clear = 0xffffff; 3837 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 3838 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 3839 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 3840 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 3841 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 3842 cpu_reg.spad_base = BCE_RXP_SCRATCH; 3843 cpu_reg.mips_view_base = 0x8000000; 3844 3845 DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n"); 3846 bce_start_cpu(sc, &cpu_reg); 3847 3848 DBEXIT(BCE_VERBOSE_RESET); 3849 } 3850 3851 3852 /****************************************************************************/ 3853 /* Initialize the RX CPU. */ 3854 /* */ 3855 /* Returns: */ 3856 /* Nothing. */ 3857 /****************************************************************************/ 3858 static void 3859 bce_init_rxp_cpu(struct bce_softc *sc) 3860 { 3861 struct cpu_reg cpu_reg; 3862 struct fw_info fw; 3863 3864 DBENTER(BCE_VERBOSE_RESET); 3865 3866 cpu_reg.mode = BCE_RXP_CPU_MODE; 3867 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 3868 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 3869 cpu_reg.state = BCE_RXP_CPU_STATE; 3870 cpu_reg.state_value_clear = 0xffffff; 3871 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 3872 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 3873 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 3874 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 3875 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 3876 cpu_reg.spad_base = BCE_RXP_SCRATCH; 3877 cpu_reg.mips_view_base = 0x8000000; 3878 3879 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 3880 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 3881 fw.ver_major = bce_RXP_b09FwReleaseMajor; 3882 fw.ver_minor = bce_RXP_b09FwReleaseMinor; 3883 fw.ver_fix = bce_RXP_b09FwReleaseFix; 3884 fw.start_addr = bce_RXP_b09FwStartAddr; 3885 3886 fw.text_addr = bce_RXP_b09FwTextAddr; 3887 fw.text_len = bce_RXP_b09FwTextLen; 3888 fw.text_index = 0; 3889 fw.text = bce_RXP_b09FwText; 3890 3891 fw.data_addr = bce_RXP_b09FwDataAddr; 3892 fw.data_len = bce_RXP_b09FwDataLen; 3893 fw.data_index = 0; 3894 fw.data = bce_RXP_b09FwData; 3895 3896 fw.sbss_addr = bce_RXP_b09FwSbssAddr; 3897 fw.sbss_len = bce_RXP_b09FwSbssLen; 3898 fw.sbss_index = 0; 3899 fw.sbss = bce_RXP_b09FwSbss; 3900 3901 fw.bss_addr = bce_RXP_b09FwBssAddr; 3902 fw.bss_len = bce_RXP_b09FwBssLen; 3903 fw.bss_index = 0; 3904 fw.bss = bce_RXP_b09FwBss; 3905 3906 fw.rodata_addr = bce_RXP_b09FwRodataAddr; 3907 fw.rodata_len = bce_RXP_b09FwRodataLen; 3908 fw.rodata_index = 0; 3909 fw.rodata = bce_RXP_b09FwRodata; 3910 } else { 3911 fw.ver_major = bce_RXP_b06FwReleaseMajor; 3912 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 3913 fw.ver_fix = bce_RXP_b06FwReleaseFix; 3914 fw.start_addr = bce_RXP_b06FwStartAddr; 3915 3916 fw.text_addr = bce_RXP_b06FwTextAddr; 3917 fw.text_len = bce_RXP_b06FwTextLen; 3918 fw.text_index = 0; 3919 fw.text = bce_RXP_b06FwText; 3920 3921 fw.data_addr = bce_RXP_b06FwDataAddr; 3922 fw.data_len = bce_RXP_b06FwDataLen; 3923 fw.data_index = 0; 3924 fw.data = bce_RXP_b06FwData; 3925 3926 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 3927 fw.sbss_len = bce_RXP_b06FwSbssLen; 3928 fw.sbss_index = 0; 3929 fw.sbss = bce_RXP_b06FwSbss; 3930 3931 fw.bss_addr = bce_RXP_b06FwBssAddr; 3932 fw.bss_len = bce_RXP_b06FwBssLen; 3933 fw.bss_index = 0; 3934 fw.bss = bce_RXP_b06FwBss; 3935 3936 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 3937 fw.rodata_len = bce_RXP_b06FwRodataLen; 3938 fw.rodata_index = 0; 3939 fw.rodata = bce_RXP_b06FwRodata; 3940 } 3941 3942 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 3943 bce_load_cpu_fw(sc, &cpu_reg, &fw); 3944 3945 /* Delay RXP start until initialization is complete. */ 3946 3947 DBEXIT(BCE_VERBOSE_RESET); 3948 } 3949 3950 3951 /****************************************************************************/ 3952 /* Initialize the TX CPU. */ 3953 /* */ 3954 /* Returns: */ 3955 /* Nothing. */ 3956 /****************************************************************************/ 3957 static void 3958 bce_init_txp_cpu(struct bce_softc *sc) 3959 { 3960 struct cpu_reg cpu_reg; 3961 struct fw_info fw; 3962 3963 DBENTER(BCE_VERBOSE_RESET); 3964 3965 cpu_reg.mode = BCE_TXP_CPU_MODE; 3966 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 3967 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 3968 cpu_reg.state = BCE_TXP_CPU_STATE; 3969 cpu_reg.state_value_clear = 0xffffff; 3970 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 3971 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 3972 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 3973 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 3974 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 3975 cpu_reg.spad_base = BCE_TXP_SCRATCH; 3976 cpu_reg.mips_view_base = 0x8000000; 3977 3978 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 3979 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 3980 fw.ver_major = bce_TXP_b09FwReleaseMajor; 3981 fw.ver_minor = bce_TXP_b09FwReleaseMinor; 3982 fw.ver_fix = bce_TXP_b09FwReleaseFix; 3983 fw.start_addr = bce_TXP_b09FwStartAddr; 3984 3985 fw.text_addr = bce_TXP_b09FwTextAddr; 3986 fw.text_len = bce_TXP_b09FwTextLen; 3987 fw.text_index = 0; 3988 fw.text = bce_TXP_b09FwText; 3989 3990 fw.data_addr = bce_TXP_b09FwDataAddr; 3991 fw.data_len = bce_TXP_b09FwDataLen; 3992 fw.data_index = 0; 3993 fw.data = bce_TXP_b09FwData; 3994 3995 fw.sbss_addr = bce_TXP_b09FwSbssAddr; 3996 fw.sbss_len = bce_TXP_b09FwSbssLen; 3997 fw.sbss_index = 0; 3998 fw.sbss = bce_TXP_b09FwSbss; 3999 4000 fw.bss_addr = bce_TXP_b09FwBssAddr; 4001 fw.bss_len = bce_TXP_b09FwBssLen; 4002 fw.bss_index = 0; 4003 fw.bss = bce_TXP_b09FwBss; 4004 4005 fw.rodata_addr = bce_TXP_b09FwRodataAddr; 4006 fw.rodata_len = bce_TXP_b09FwRodataLen; 4007 fw.rodata_index = 0; 4008 fw.rodata = bce_TXP_b09FwRodata; 4009 } else { 4010 fw.ver_major = bce_TXP_b06FwReleaseMajor; 4011 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 4012 fw.ver_fix = bce_TXP_b06FwReleaseFix; 4013 fw.start_addr = bce_TXP_b06FwStartAddr; 4014 4015 fw.text_addr = bce_TXP_b06FwTextAddr; 4016 fw.text_len = bce_TXP_b06FwTextLen; 4017 fw.text_index = 0; 4018 fw.text = bce_TXP_b06FwText; 4019 4020 fw.data_addr = bce_TXP_b06FwDataAddr; 4021 fw.data_len = bce_TXP_b06FwDataLen; 4022 fw.data_index = 0; 4023 fw.data = bce_TXP_b06FwData; 4024 4025 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 4026 fw.sbss_len = bce_TXP_b06FwSbssLen; 4027 fw.sbss_index = 0; 4028 fw.sbss = bce_TXP_b06FwSbss; 4029 4030 fw.bss_addr = bce_TXP_b06FwBssAddr; 4031 fw.bss_len = bce_TXP_b06FwBssLen; 4032 fw.bss_index = 0; 4033 fw.bss = bce_TXP_b06FwBss; 4034 4035 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 4036 fw.rodata_len = bce_TXP_b06FwRodataLen; 4037 fw.rodata_index = 0; 4038 fw.rodata = bce_TXP_b06FwRodata; 4039 } 4040 4041 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 4042 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4043 bce_start_cpu(sc, &cpu_reg); 4044 4045 DBEXIT(BCE_VERBOSE_RESET); 4046 } 4047 4048 4049 /****************************************************************************/ 4050 /* Initialize the TPAT CPU. */ 4051 /* */ 4052 /* Returns: */ 4053 /* Nothing. */ 4054 /****************************************************************************/ 4055 static void 4056 bce_init_tpat_cpu(struct bce_softc *sc) 4057 { 4058 struct cpu_reg cpu_reg; 4059 struct fw_info fw; 4060 4061 DBENTER(BCE_VERBOSE_RESET); 4062 4063 cpu_reg.mode = BCE_TPAT_CPU_MODE; 4064 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 4065 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 4066 cpu_reg.state = BCE_TPAT_CPU_STATE; 4067 cpu_reg.state_value_clear = 0xffffff; 4068 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 4069 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 4070 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 4071 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 4072 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 4073 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 4074 cpu_reg.mips_view_base = 0x8000000; 4075 4076 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4077 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4078 fw.ver_major = bce_TPAT_b09FwReleaseMajor; 4079 fw.ver_minor = bce_TPAT_b09FwReleaseMinor; 4080 fw.ver_fix = bce_TPAT_b09FwReleaseFix; 4081 fw.start_addr = bce_TPAT_b09FwStartAddr; 4082 4083 fw.text_addr = bce_TPAT_b09FwTextAddr; 4084 fw.text_len = bce_TPAT_b09FwTextLen; 4085 fw.text_index = 0; 4086 fw.text = bce_TPAT_b09FwText; 4087 4088 fw.data_addr = bce_TPAT_b09FwDataAddr; 4089 fw.data_len = bce_TPAT_b09FwDataLen; 4090 fw.data_index = 0; 4091 fw.data = bce_TPAT_b09FwData; 4092 4093 fw.sbss_addr = bce_TPAT_b09FwSbssAddr; 4094 fw.sbss_len = bce_TPAT_b09FwSbssLen; 4095 fw.sbss_index = 0; 4096 fw.sbss = bce_TPAT_b09FwSbss; 4097 4098 fw.bss_addr = bce_TPAT_b09FwBssAddr; 4099 fw.bss_len = bce_TPAT_b09FwBssLen; 4100 fw.bss_index = 0; 4101 fw.bss = bce_TPAT_b09FwBss; 4102 4103 fw.rodata_addr = bce_TPAT_b09FwRodataAddr; 4104 fw.rodata_len = bce_TPAT_b09FwRodataLen; 4105 fw.rodata_index = 0; 4106 fw.rodata = bce_TPAT_b09FwRodata; 4107 } else { 4108 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 4109 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 4110 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 4111 fw.start_addr = bce_TPAT_b06FwStartAddr; 4112 4113 fw.text_addr = bce_TPAT_b06FwTextAddr; 4114 fw.text_len = bce_TPAT_b06FwTextLen; 4115 fw.text_index = 0; 4116 fw.text = bce_TPAT_b06FwText; 4117 4118 fw.data_addr = bce_TPAT_b06FwDataAddr; 4119 fw.data_len = bce_TPAT_b06FwDataLen; 4120 fw.data_index = 0; 4121 fw.data = bce_TPAT_b06FwData; 4122 4123 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 4124 fw.sbss_len = bce_TPAT_b06FwSbssLen; 4125 fw.sbss_index = 0; 4126 fw.sbss = bce_TPAT_b06FwSbss; 4127 4128 fw.bss_addr = bce_TPAT_b06FwBssAddr; 4129 fw.bss_len = bce_TPAT_b06FwBssLen; 4130 fw.bss_index = 0; 4131 fw.bss = bce_TPAT_b06FwBss; 4132 4133 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 4134 fw.rodata_len = bce_TPAT_b06FwRodataLen; 4135 fw.rodata_index = 0; 4136 fw.rodata = bce_TPAT_b06FwRodata; 4137 } 4138 4139 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 4140 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4141 bce_start_cpu(sc, &cpu_reg); 4142 4143 DBEXIT(BCE_VERBOSE_RESET); 4144 } 4145 4146 4147 /****************************************************************************/ 4148 /* Initialize the CP CPU. */ 4149 /* */ 4150 /* Returns: */ 4151 /* Nothing. */ 4152 /****************************************************************************/ 4153 static void 4154 bce_init_cp_cpu(struct bce_softc *sc) 4155 { 4156 struct cpu_reg cpu_reg; 4157 struct fw_info fw; 4158 4159 DBENTER(BCE_VERBOSE_RESET); 4160 4161 cpu_reg.mode = BCE_CP_CPU_MODE; 4162 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT; 4163 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA; 4164 cpu_reg.state = BCE_CP_CPU_STATE; 4165 cpu_reg.state_value_clear = 0xffffff; 4166 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE; 4167 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK; 4168 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER; 4169 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION; 4170 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT; 4171 cpu_reg.spad_base = BCE_CP_SCRATCH; 4172 cpu_reg.mips_view_base = 0x8000000; 4173 4174 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4175 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4176 fw.ver_major = bce_CP_b09FwReleaseMajor; 4177 fw.ver_minor = bce_CP_b09FwReleaseMinor; 4178 fw.ver_fix = bce_CP_b09FwReleaseFix; 4179 fw.start_addr = bce_CP_b09FwStartAddr; 4180 4181 fw.text_addr = bce_CP_b09FwTextAddr; 4182 fw.text_len = bce_CP_b09FwTextLen; 4183 fw.text_index = 0; 4184 fw.text = bce_CP_b09FwText; 4185 4186 fw.data_addr = bce_CP_b09FwDataAddr; 4187 fw.data_len = bce_CP_b09FwDataLen; 4188 fw.data_index = 0; 4189 fw.data = bce_CP_b09FwData; 4190 4191 fw.sbss_addr = bce_CP_b09FwSbssAddr; 4192 fw.sbss_len = bce_CP_b09FwSbssLen; 4193 fw.sbss_index = 0; 4194 fw.sbss = bce_CP_b09FwSbss; 4195 4196 fw.bss_addr = bce_CP_b09FwBssAddr; 4197 fw.bss_len = bce_CP_b09FwBssLen; 4198 fw.bss_index = 0; 4199 fw.bss = bce_CP_b09FwBss; 4200 4201 fw.rodata_addr = bce_CP_b09FwRodataAddr; 4202 fw.rodata_len = bce_CP_b09FwRodataLen; 4203 fw.rodata_index = 0; 4204 fw.rodata = bce_CP_b09FwRodata; 4205 } else { 4206 fw.ver_major = bce_CP_b06FwReleaseMajor; 4207 fw.ver_minor = bce_CP_b06FwReleaseMinor; 4208 fw.ver_fix = bce_CP_b06FwReleaseFix; 4209 fw.start_addr = bce_CP_b06FwStartAddr; 4210 4211 fw.text_addr = bce_CP_b06FwTextAddr; 4212 fw.text_len = bce_CP_b06FwTextLen; 4213 fw.text_index = 0; 4214 fw.text = bce_CP_b06FwText; 4215 4216 fw.data_addr = bce_CP_b06FwDataAddr; 4217 fw.data_len = bce_CP_b06FwDataLen; 4218 fw.data_index = 0; 4219 fw.data = bce_CP_b06FwData; 4220 4221 fw.sbss_addr = bce_CP_b06FwSbssAddr; 4222 fw.sbss_len = bce_CP_b06FwSbssLen; 4223 fw.sbss_index = 0; 4224 fw.sbss = bce_CP_b06FwSbss; 4225 4226 fw.bss_addr = bce_CP_b06FwBssAddr; 4227 fw.bss_len = bce_CP_b06FwBssLen; 4228 fw.bss_index = 0; 4229 fw.bss = bce_CP_b06FwBss; 4230 4231 fw.rodata_addr = bce_CP_b06FwRodataAddr; 4232 fw.rodata_len = bce_CP_b06FwRodataLen; 4233 fw.rodata_index = 0; 4234 fw.rodata = bce_CP_b06FwRodata; 4235 } 4236 4237 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n"); 4238 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4239 bce_start_cpu(sc, &cpu_reg); 4240 4241 DBEXIT(BCE_VERBOSE_RESET); 4242 } 4243 4244 4245 /****************************************************************************/ 4246 /* Initialize the COM CPU. */ 4247 /* */ 4248 /* Returns: */ 4249 /* Nothing. */ 4250 /****************************************************************************/ 4251 static void 4252 bce_init_com_cpu(struct bce_softc *sc) 4253 { 4254 struct cpu_reg cpu_reg; 4255 struct fw_info fw; 4256 4257 DBENTER(BCE_VERBOSE_RESET); 4258 4259 cpu_reg.mode = BCE_COM_CPU_MODE; 4260 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 4261 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 4262 cpu_reg.state = BCE_COM_CPU_STATE; 4263 cpu_reg.state_value_clear = 0xffffff; 4264 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 4265 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 4266 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 4267 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 4268 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 4269 cpu_reg.spad_base = BCE_COM_SCRATCH; 4270 cpu_reg.mips_view_base = 0x8000000; 4271 4272 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4273 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4274 fw.ver_major = bce_COM_b09FwReleaseMajor; 4275 fw.ver_minor = bce_COM_b09FwReleaseMinor; 4276 fw.ver_fix = bce_COM_b09FwReleaseFix; 4277 fw.start_addr = bce_COM_b09FwStartAddr; 4278 4279 fw.text_addr = bce_COM_b09FwTextAddr; 4280 fw.text_len = bce_COM_b09FwTextLen; 4281 fw.text_index = 0; 4282 fw.text = bce_COM_b09FwText; 4283 4284 fw.data_addr = bce_COM_b09FwDataAddr; 4285 fw.data_len = bce_COM_b09FwDataLen; 4286 fw.data_index = 0; 4287 fw.data = bce_COM_b09FwData; 4288 4289 fw.sbss_addr = bce_COM_b09FwSbssAddr; 4290 fw.sbss_len = bce_COM_b09FwSbssLen; 4291 fw.sbss_index = 0; 4292 fw.sbss = bce_COM_b09FwSbss; 4293 4294 fw.bss_addr = bce_COM_b09FwBssAddr; 4295 fw.bss_len = bce_COM_b09FwBssLen; 4296 fw.bss_index = 0; 4297 fw.bss = bce_COM_b09FwBss; 4298 4299 fw.rodata_addr = bce_COM_b09FwRodataAddr; 4300 fw.rodata_len = bce_COM_b09FwRodataLen; 4301 fw.rodata_index = 0; 4302 fw.rodata = bce_COM_b09FwRodata; 4303 } else { 4304 fw.ver_major = bce_COM_b06FwReleaseMajor; 4305 fw.ver_minor = bce_COM_b06FwReleaseMinor; 4306 fw.ver_fix = bce_COM_b06FwReleaseFix; 4307 fw.start_addr = bce_COM_b06FwStartAddr; 4308 4309 fw.text_addr = bce_COM_b06FwTextAddr; 4310 fw.text_len = bce_COM_b06FwTextLen; 4311 fw.text_index = 0; 4312 fw.text = bce_COM_b06FwText; 4313 4314 fw.data_addr = bce_COM_b06FwDataAddr; 4315 fw.data_len = bce_COM_b06FwDataLen; 4316 fw.data_index = 0; 4317 fw.data = bce_COM_b06FwData; 4318 4319 fw.sbss_addr = bce_COM_b06FwSbssAddr; 4320 fw.sbss_len = bce_COM_b06FwSbssLen; 4321 fw.sbss_index = 0; 4322 fw.sbss = bce_COM_b06FwSbss; 4323 4324 fw.bss_addr = bce_COM_b06FwBssAddr; 4325 fw.bss_len = bce_COM_b06FwBssLen; 4326 fw.bss_index = 0; 4327 fw.bss = bce_COM_b06FwBss; 4328 4329 fw.rodata_addr = bce_COM_b06FwRodataAddr; 4330 fw.rodata_len = bce_COM_b06FwRodataLen; 4331 fw.rodata_index = 0; 4332 fw.rodata = bce_COM_b06FwRodata; 4333 } 4334 4335 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 4336 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4337 bce_start_cpu(sc, &cpu_reg); 4338 4339 DBEXIT(BCE_VERBOSE_RESET); 4340 } 4341 4342 4343 /****************************************************************************/ 4344 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */ 4345 /* */ 4346 /* Loads the firmware for each CPU and starts the CPU. */ 4347 /* */ 4348 /* Returns: */ 4349 /* Nothing. */ 4350 /****************************************************************************/ 4351 static void 4352 bce_init_cpus(struct bce_softc *sc) 4353 { 4354 DBENTER(BCE_VERBOSE_RESET); 4355 4356 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4357 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4358 4359 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) { 4360 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1, 4361 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1); 4362 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2, 4363 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2); 4364 } else { 4365 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, 4366 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1); 4367 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, 4368 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2); 4369 } 4370 4371 } else { 4372 bce_load_rv2p_fw(sc, bce_rv2p_proc1, 4373 sizeof(bce_rv2p_proc1), RV2P_PROC1); 4374 bce_load_rv2p_fw(sc, bce_rv2p_proc2, 4375 sizeof(bce_rv2p_proc2), RV2P_PROC2); 4376 } 4377 4378 bce_init_rxp_cpu(sc); 4379 bce_init_txp_cpu(sc); 4380 bce_init_tpat_cpu(sc); 4381 bce_init_com_cpu(sc); 4382 bce_init_cp_cpu(sc); 4383 4384 DBEXIT(BCE_VERBOSE_RESET); 4385 } 4386 4387 4388 /****************************************************************************/ 4389 /* Initialize context memory. */ 4390 /* */ 4391 /* Clears the memory associated with each Context ID (CID). */ 4392 /* */ 4393 /* Returns: */ 4394 /* Nothing. */ 4395 /****************************************************************************/ 4396 static int 4397 bce_init_ctx(struct bce_softc *sc) 4398 { 4399 u32 offset, val, vcid_addr; 4400 int i, j, rc, retry_cnt; 4401 4402 rc = 0; 4403 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4404 4405 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4406 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4407 retry_cnt = CTX_INIT_RETRY_COUNT; 4408 4409 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n"); 4410 4411 /* 4412 * BCM5709 context memory may be cached 4413 * in host memory so prepare the host memory 4414 * for access. 4415 */ 4416 val = BCE_CTX_COMMAND_ENABLED | 4417 BCE_CTX_COMMAND_MEM_INIT | (1 << 12); 4418 val |= (BCM_PAGE_BITS - 8) << 16; 4419 REG_WR(sc, BCE_CTX_COMMAND, val); 4420 4421 /* Wait for mem init command to complete. */ 4422 for (i = 0; i < retry_cnt; i++) { 4423 val = REG_RD(sc, BCE_CTX_COMMAND); 4424 if (!(val & BCE_CTX_COMMAND_MEM_INIT)) 4425 break; 4426 DELAY(2); 4427 } 4428 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) { 4429 BCE_PRINTF("%s(): Context memory initialization failed!\n", 4430 __FUNCTION__); 4431 rc = EBUSY; 4432 goto init_ctx_fail; 4433 } 4434 4435 for (i = 0; i < sc->ctx_pages; i++) { 4436 /* Set the physical address of the context memory. */ 4437 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0, 4438 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) | 4439 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID); 4440 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1, 4441 BCE_ADDR_HI(sc->ctx_paddr[i])); 4442 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i | 4443 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 4444 4445 /* Verify the context memory write was successful. */ 4446 for (j = 0; j < retry_cnt; j++) { 4447 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL); 4448 if ((val & 4449 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 4450 break; 4451 DELAY(5); 4452 } 4453 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) { 4454 BCE_PRINTF("%s(): Failed to initialize " 4455 "context page %d!\n", __FUNCTION__, i); 4456 rc = EBUSY; 4457 goto init_ctx_fail; 4458 } 4459 } 4460 } else { 4461 4462 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n"); 4463 4464 /* 4465 * For the 5706/5708, context memory is local to 4466 * the controller, so initialize the controller 4467 * context memory. 4468 */ 4469 4470 vcid_addr = GET_CID_ADDR(96); 4471 while (vcid_addr) { 4472 4473 vcid_addr -= PHY_CTX_SIZE; 4474 4475 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0); 4476 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4477 4478 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 4479 CTX_WR(sc, 0x00, offset, 0); 4480 } 4481 4482 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 4483 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4484 } 4485 4486 } 4487 init_ctx_fail: 4488 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4489 return (rc); 4490 } 4491 4492 4493 /****************************************************************************/ 4494 /* Fetch the permanent MAC address of the controller. */ 4495 /* */ 4496 /* Returns: */ 4497 /* Nothing. */ 4498 /****************************************************************************/ 4499 static void 4500 bce_get_mac_addr(struct bce_softc *sc) 4501 { 4502 u32 mac_lo = 0, mac_hi = 0; 4503 4504 DBENTER(BCE_VERBOSE_RESET); 4505 4506 /* 4507 * The NetXtreme II bootcode populates various NIC 4508 * power-on and runtime configuration items in a 4509 * shared memory area. The factory configured MAC 4510 * address is available from both NVRAM and the 4511 * shared memory area so we'll read the value from 4512 * shared memory for speed. 4513 */ 4514 4515 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER); 4516 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER); 4517 4518 if ((mac_lo == 0) && (mac_hi == 0)) { 4519 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 4520 __FILE__, __LINE__); 4521 } else { 4522 sc->eaddr[0] = (u_char)(mac_hi >> 8); 4523 sc->eaddr[1] = (u_char)(mac_hi >> 0); 4524 sc->eaddr[2] = (u_char)(mac_lo >> 24); 4525 sc->eaddr[3] = (u_char)(mac_lo >> 16); 4526 sc->eaddr[4] = (u_char)(mac_lo >> 8); 4527 sc->eaddr[5] = (u_char)(mac_lo >> 0); 4528 } 4529 4530 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet " 4531 "address = %6D\n", sc->eaddr, ":"); 4532 DBEXIT(BCE_VERBOSE_RESET); 4533 } 4534 4535 4536 /****************************************************************************/ 4537 /* Program the MAC address. */ 4538 /* */ 4539 /* Returns: */ 4540 /* Nothing. */ 4541 /****************************************************************************/ 4542 static void 4543 bce_set_mac_addr(struct bce_softc *sc) 4544 { 4545 u32 val; 4546 u8 *mac_addr = sc->eaddr; 4547 4548 /* ToDo: Add support for setting multiple MAC addresses. */ 4549 4550 DBENTER(BCE_VERBOSE_RESET); 4551 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = " 4552 "%6D\n", sc->eaddr, ":"); 4553 4554 val = (mac_addr[0] << 8) | mac_addr[1]; 4555 4556 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 4557 4558 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 4559 (mac_addr[4] << 8) | mac_addr[5]; 4560 4561 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 4562 4563 DBEXIT(BCE_VERBOSE_RESET); 4564 } 4565 4566 4567 /****************************************************************************/ 4568 /* Stop the controller. */ 4569 /* */ 4570 /* Returns: */ 4571 /* Nothing. */ 4572 /****************************************************************************/ 4573 static void 4574 bce_stop(struct bce_softc *sc) 4575 { 4576 struct ifnet *ifp; 4577 4578 DBENTER(BCE_VERBOSE_RESET); 4579 4580 BCE_LOCK_ASSERT(sc); 4581 4582 ifp = sc->bce_ifp; 4583 4584 callout_stop(&sc->bce_tick_callout); 4585 4586 /* Disable the transmit/receive blocks. */ 4587 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT); 4588 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4589 DELAY(20); 4590 4591 bce_disable_intr(sc); 4592 4593 /* Free RX buffers. */ 4594 #ifdef BCE_JUMBO_HDRSPLIT 4595 bce_free_pg_chain(sc); 4596 #endif 4597 bce_free_rx_chain(sc); 4598 4599 /* Free TX buffers. */ 4600 bce_free_tx_chain(sc); 4601 4602 sc->watchdog_timer = 0; 4603 4604 sc->bce_link_up = FALSE; 4605 4606 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4607 4608 DBEXIT(BCE_VERBOSE_RESET); 4609 } 4610 4611 4612 static int 4613 bce_reset(struct bce_softc *sc, u32 reset_code) 4614 { 4615 u32 val; 4616 int i, rc = 0; 4617 4618 DBENTER(BCE_VERBOSE_RESET); 4619 4620 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 4621 __FUNCTION__, reset_code); 4622 4623 /* Wait for pending PCI transactions to complete. */ 4624 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 4625 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 4626 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 4627 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 4628 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 4629 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4630 DELAY(5); 4631 4632 /* Disable DMA */ 4633 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4634 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4635 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 4636 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 4637 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 4638 } 4639 4640 /* Assume bootcode is running. */ 4641 sc->bce_fw_timed_out = FALSE; 4642 sc->bce_drv_cardiac_arrest = FALSE; 4643 4644 /* Give the firmware a chance to prepare for the reset. */ 4645 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 4646 if (rc) 4647 goto bce_reset_exit; 4648 4649 /* Set a firmware reminder that this is a soft reset. */ 4650 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC); 4651 4652 /* Dummy read to force the chip to complete all current transactions. */ 4653 val = REG_RD(sc, BCE_MISC_ID); 4654 4655 /* Chip reset. */ 4656 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4657 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4658 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET); 4659 REG_RD(sc, BCE_MISC_COMMAND); 4660 DELAY(5); 4661 4662 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4663 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4664 4665 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4); 4666 } else { 4667 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4668 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4669 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4670 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 4671 4672 /* Allow up to 30us for reset to complete. */ 4673 for (i = 0; i < 10; i++) { 4674 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 4675 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4676 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 4677 break; 4678 } 4679 DELAY(10); 4680 } 4681 4682 /* Check that reset completed successfully. */ 4683 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4684 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 4685 BCE_PRINTF("%s(%d): Reset failed!\n", 4686 __FILE__, __LINE__); 4687 rc = EBUSY; 4688 goto bce_reset_exit; 4689 } 4690 } 4691 4692 /* Make sure byte swapping is properly configured. */ 4693 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 4694 if (val != 0x01020304) { 4695 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 4696 __FILE__, __LINE__); 4697 rc = ENODEV; 4698 goto bce_reset_exit; 4699 } 4700 4701 /* Just completed a reset, assume that firmware is running again. */ 4702 sc->bce_fw_timed_out = FALSE; 4703 sc->bce_drv_cardiac_arrest = FALSE; 4704 4705 /* Wait for the firmware to finish its initialization. */ 4706 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 4707 if (rc) 4708 BCE_PRINTF("%s(%d): Firmware did not complete " 4709 "initialization!\n", __FILE__, __LINE__); 4710 4711 bce_reset_exit: 4712 DBEXIT(BCE_VERBOSE_RESET); 4713 return (rc); 4714 } 4715 4716 4717 static int 4718 bce_chipinit(struct bce_softc *sc) 4719 { 4720 u32 val; 4721 int rc = 0; 4722 4723 DBENTER(BCE_VERBOSE_RESET); 4724 4725 bce_disable_intr(sc); 4726 4727 /* 4728 * Initialize DMA byte/word swapping, configure the number of DMA 4729 * channels and PCI clock compensation delay. 4730 */ 4731 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 4732 BCE_DMA_CONFIG_DATA_WORD_SWAP | 4733 #if BYTE_ORDER == BIG_ENDIAN 4734 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 4735 #endif 4736 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 4737 DMA_READ_CHANS << 12 | 4738 DMA_WRITE_CHANS << 16; 4739 4740 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 4741 4742 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 4743 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 4744 4745 /* 4746 * This setting resolves a problem observed on certain Intel PCI 4747 * chipsets that cannot handle multiple outstanding DMA operations. 4748 * See errata E9_5706A1_65. 4749 */ 4750 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 4751 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 4752 !(sc->bce_flags & BCE_PCIX_FLAG)) 4753 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 4754 4755 REG_WR(sc, BCE_DMA_CONFIG, val); 4756 4757 /* Enable the RX_V2P and Context state machines before access. */ 4758 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 4759 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 4760 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 4761 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 4762 4763 /* Initialize context mapping and zero out the quick contexts. */ 4764 if ((rc = bce_init_ctx(sc)) != 0) 4765 goto bce_chipinit_exit; 4766 4767 /* Initialize the on-boards CPUs */ 4768 bce_init_cpus(sc); 4769 4770 /* Enable management frames (NC-SI) to flow to the MCP. */ 4771 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 4772 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 4773 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 4774 } 4775 4776 /* Prepare NVRAM for access. */ 4777 if ((rc = bce_init_nvram(sc)) != 0) 4778 goto bce_chipinit_exit; 4779 4780 /* Set the kernel bypass block size */ 4781 val = REG_RD(sc, BCE_MQ_CONFIG); 4782 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 4783 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 4784 4785 /* Enable bins used on the 5709. */ 4786 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4787 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4788 val |= BCE_MQ_CONFIG_BIN_MQ_MODE; 4789 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1) 4790 val |= BCE_MQ_CONFIG_HALT_DIS; 4791 } 4792 4793 REG_WR(sc, BCE_MQ_CONFIG, val); 4794 4795 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 4796 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 4797 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 4798 4799 /* Set the page size and clear the RV2P processor stall bits. */ 4800 val = (BCM_PAGE_BITS - 8) << 24; 4801 REG_WR(sc, BCE_RV2P_CONFIG, val); 4802 4803 /* Configure page size. */ 4804 val = REG_RD(sc, BCE_TBDR_CONFIG); 4805 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 4806 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 4807 REG_WR(sc, BCE_TBDR_CONFIG, val); 4808 4809 /* Set the perfect match control register to default. */ 4810 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0); 4811 4812 bce_chipinit_exit: 4813 DBEXIT(BCE_VERBOSE_RESET); 4814 4815 return(rc); 4816 } 4817 4818 4819 /****************************************************************************/ 4820 /* Initialize the controller in preparation to send/receive traffic. */ 4821 /* */ 4822 /* Returns: */ 4823 /* 0 for success, positive value for failure. */ 4824 /****************************************************************************/ 4825 static int 4826 bce_blockinit(struct bce_softc *sc) 4827 { 4828 u32 reg, val; 4829 int rc = 0; 4830 4831 DBENTER(BCE_VERBOSE_RESET); 4832 4833 /* Load the hardware default MAC address. */ 4834 bce_set_mac_addr(sc); 4835 4836 /* Set the Ethernet backoff seed value */ 4837 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 4838 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 4839 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 4840 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 4841 4842 sc->last_status_idx = 0; 4843 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 4844 4845 /* Set up link change interrupt generation. */ 4846 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 4847 4848 /* Program the physical address of the status block. */ 4849 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 4850 BCE_ADDR_LO(sc->status_block_paddr)); 4851 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 4852 BCE_ADDR_HI(sc->status_block_paddr)); 4853 4854 /* Program the physical address of the statistics block. */ 4855 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 4856 BCE_ADDR_LO(sc->stats_block_paddr)); 4857 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 4858 BCE_ADDR_HI(sc->stats_block_paddr)); 4859 4860 /* Program various host coalescing parameters. */ 4861 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 4862 (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip); 4863 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 4864 (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip); 4865 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 4866 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip); 4867 REG_WR(sc, BCE_HC_TX_TICKS, 4868 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 4869 REG_WR(sc, BCE_HC_RX_TICKS, 4870 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 4871 REG_WR(sc, BCE_HC_COM_TICKS, 4872 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks); 4873 REG_WR(sc, BCE_HC_CMD_TICKS, 4874 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks); 4875 REG_WR(sc, BCE_HC_STATS_TICKS, 4876 (sc->bce_stats_ticks & 0xffff00)); 4877 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 4878 4879 /* Configure the Host Coalescing block. */ 4880 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 4881 BCE_HC_CONFIG_COLLECT_STATS; 4882 4883 #if 0 4884 /* ToDo: Add MSI-X support. */ 4885 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 4886 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) + 4887 BCE_HC_SB_CONFIG_1; 4888 4889 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL); 4890 4891 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE | 4892 BCE_HC_SB_CONFIG_1_ONE_SHOT); 4893 4894 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF, 4895 (sc->tx_quick_cons_trip_int << 16) | 4896 sc->tx_quick_cons_trip); 4897 4898 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF, 4899 (sc->tx_ticks_int << 16) | sc->tx_ticks); 4900 4901 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 4902 } 4903 4904 /* 4905 * Tell the HC block to automatically set the 4906 * INT_MASK bit after an MSI/MSI-X interrupt 4907 * is generated so the driver doesn't have to. 4908 */ 4909 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG) 4910 val |= BCE_HC_CONFIG_ONE_SHOT; 4911 4912 /* Set the MSI-X status blocks to 128 byte boundaries. */ 4913 if (sc->bce_flags & BCE_USING_MSIX_FLAG) 4914 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 4915 #endif 4916 4917 REG_WR(sc, BCE_HC_CONFIG, val); 4918 4919 /* Clear the internal statistics counters. */ 4920 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 4921 4922 /* Verify that bootcode is running. */ 4923 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE); 4924 4925 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control), 4926 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 4927 __FILE__, __LINE__); 4928 reg = 0); 4929 4930 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 4931 BCE_DEV_INFO_SIGNATURE_MAGIC) { 4932 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 4933 "Expected: 08%08X\n", __FILE__, __LINE__, 4934 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 4935 BCE_DEV_INFO_SIGNATURE_MAGIC); 4936 rc = ENODEV; 4937 goto bce_blockinit_exit; 4938 } 4939 4940 /* Enable DMA */ 4941 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4942 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4943 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 4944 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 4945 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 4946 } 4947 4948 /* Allow bootcode to apply additional fixes before enabling MAC. */ 4949 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | 4950 BCE_DRV_MSG_CODE_RESET); 4951 4952 /* Enable link state change interrupt generation. */ 4953 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 4954 4955 /* Enable the RXP. */ 4956 bce_start_rxp_cpu(sc); 4957 4958 /* Disable management frames (NC-SI) from flowing to the MCP. */ 4959 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 4960 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) & 4961 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 4962 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 4963 } 4964 4965 /* Enable all remaining blocks in the MAC. */ 4966 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4967 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 4968 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 4969 BCE_MISC_ENABLE_DEFAULT_XI); 4970 else 4971 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 4972 BCE_MISC_ENABLE_DEFAULT); 4973 4974 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 4975 DELAY(20); 4976 4977 /* Save the current host coalescing block settings. */ 4978 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND); 4979 4980 bce_blockinit_exit: 4981 DBEXIT(BCE_VERBOSE_RESET); 4982 4983 return (rc); 4984 } 4985 4986 4987 /****************************************************************************/ 4988 /* Encapsulate an mbuf into the rx_bd chain. */ 4989 /* */ 4990 /* Returns: */ 4991 /* 0 for success, positive value for failure. */ 4992 /****************************************************************************/ 4993 static int 4994 bce_get_rx_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 4995 u16 *chain_prod, u32 *prod_bseq) 4996 { 4997 bus_dmamap_t map; 4998 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 4999 struct mbuf *m_new = NULL; 5000 struct rx_bd *rxbd; 5001 int nsegs, error, rc = 0; 5002 #ifdef BCE_DEBUG 5003 u16 debug_chain_prod = *chain_prod; 5004 #endif 5005 5006 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5007 5008 /* Make sure the inputs are valid. */ 5009 DBRUNIF((*chain_prod > MAX_RX_BD), 5010 BCE_PRINTF("%s(%d): RX producer out of range: " 5011 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5012 *chain_prod, (u16) MAX_RX_BD)); 5013 5014 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5015 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, 5016 *prod, *chain_prod, *prod_bseq); 5017 5018 /* Update some debug statistic counters */ 5019 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 5020 sc->rx_low_watermark = sc->free_rx_bd); 5021 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 5022 sc->rx_empty_count++); 5023 5024 /* Check whether this is a new mbuf allocation. */ 5025 if (m == NULL) { 5026 5027 /* Simulate an mbuf allocation failure. */ 5028 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5029 sc->mbuf_alloc_failed_count++; 5030 sc->mbuf_alloc_failed_sim_count++; 5031 rc = ENOBUFS; 5032 goto bce_get_rx_buf_exit); 5033 5034 /* This is a new mbuf allocation. */ 5035 #ifdef BCE_JUMBO_HDRSPLIT 5036 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 5037 #else 5038 if (sc->rx_bd_mbuf_alloc_size <= MCLBYTES) 5039 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 5040 else 5041 m_new = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, 5042 sc->rx_bd_mbuf_alloc_size); 5043 #endif 5044 5045 if (m_new == NULL) { 5046 sc->mbuf_alloc_failed_count++; 5047 rc = ENOBUFS; 5048 goto bce_get_rx_buf_exit; 5049 } 5050 5051 DBRUN(sc->debug_rx_mbuf_alloc++); 5052 } else { 5053 /* Reuse an existing mbuf. */ 5054 m_new = m; 5055 } 5056 5057 /* Make sure we have a valid packet header. */ 5058 M_ASSERTPKTHDR(m_new); 5059 5060 /* Initialize the mbuf size and pad if necessary for alignment. */ 5061 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size; 5062 m_adj(m_new, sc->rx_bd_mbuf_align_pad); 5063 5064 /* ToDo: Consider calling m_fragment() to test error handling. */ 5065 5066 /* Map the mbuf cluster into device memory. */ 5067 map = sc->rx_mbuf_map[*chain_prod]; 5068 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new, 5069 segs, &nsegs, BUS_DMA_NOWAIT); 5070 5071 /* Handle any mapping errors. */ 5072 if (error) { 5073 BCE_PRINTF("%s(%d): Error mapping mbuf into RX " 5074 "chain (%d)!\n", __FILE__, __LINE__, error); 5075 5076 sc->dma_map_addr_rx_failed_count++; 5077 m_freem(m_new); 5078 5079 DBRUN(sc->debug_rx_mbuf_alloc--); 5080 5081 rc = ENOBUFS; 5082 goto bce_get_rx_buf_exit; 5083 } 5084 5085 /* All mbufs must map to a single segment. */ 5086 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5087 __FUNCTION__, nsegs)); 5088 5089 /* Setup the rx_bd for the segment. */ 5090 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 5091 5092 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5093 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5094 rxbd->rx_bd_len = htole32(segs[0].ds_len); 5095 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5096 *prod_bseq += segs[0].ds_len; 5097 5098 /* Save the mbuf and update our counter. */ 5099 sc->rx_mbuf_ptr[*chain_prod] = m_new; 5100 sc->free_rx_bd -= nsegs; 5101 5102 DBRUNMSG(BCE_INSANE_RECV, 5103 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs)); 5104 5105 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5106 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", 5107 __FUNCTION__, *prod, *chain_prod, *prod_bseq); 5108 5109 bce_get_rx_buf_exit: 5110 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5111 5112 return(rc); 5113 } 5114 5115 5116 #ifdef BCE_JUMBO_HDRSPLIT 5117 /****************************************************************************/ 5118 /* Encapsulate an mbuf cluster into the page chain. */ 5119 /* */ 5120 /* Returns: */ 5121 /* 0 for success, positive value for failure. */ 5122 /****************************************************************************/ 5123 static int 5124 bce_get_pg_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 5125 u16 *prod_idx) 5126 { 5127 bus_dmamap_t map; 5128 bus_addr_t busaddr; 5129 struct mbuf *m_new = NULL; 5130 struct rx_bd *pgbd; 5131 int error, rc = 0; 5132 #ifdef BCE_DEBUG 5133 u16 debug_prod_idx = *prod_idx; 5134 #endif 5135 5136 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5137 5138 /* Make sure the inputs are valid. */ 5139 DBRUNIF((*prod_idx > MAX_PG_BD), 5140 BCE_PRINTF("%s(%d): page producer out of range: " 5141 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5142 *prod_idx, (u16) MAX_PG_BD)); 5143 5144 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5145 "chain_prod = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 5146 5147 /* Update counters if we've hit a new low or run out of pages. */ 5148 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark), 5149 sc->pg_low_watermark = sc->free_pg_bd); 5150 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++); 5151 5152 /* Check whether this is a new mbuf allocation. */ 5153 if (m == NULL) { 5154 5155 /* Simulate an mbuf allocation failure. */ 5156 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5157 sc->mbuf_alloc_failed_count++; 5158 sc->mbuf_alloc_failed_sim_count++; 5159 rc = ENOBUFS; 5160 goto bce_get_pg_buf_exit); 5161 5162 /* This is a new mbuf allocation. */ 5163 m_new = m_getcl(M_DONTWAIT, MT_DATA, 0); 5164 if (m_new == NULL) { 5165 sc->mbuf_alloc_failed_count++; 5166 rc = ENOBUFS; 5167 goto bce_get_pg_buf_exit; 5168 } 5169 5170 DBRUN(sc->debug_pg_mbuf_alloc++); 5171 } else { 5172 /* Reuse an existing mbuf. */ 5173 m_new = m; 5174 m_new->m_data = m_new->m_ext.ext_buf; 5175 } 5176 5177 m_new->m_len = sc->pg_bd_mbuf_alloc_size; 5178 5179 /* ToDo: Consider calling m_fragment() to test error handling. */ 5180 5181 /* Map the mbuf cluster into device memory. */ 5182 map = sc->pg_mbuf_map[*prod_idx]; 5183 error = bus_dmamap_load(sc->pg_mbuf_tag, map, mtod(m_new, void *), 5184 sc->pg_bd_mbuf_alloc_size, bce_dma_map_addr, 5185 &busaddr, BUS_DMA_NOWAIT); 5186 5187 /* Handle any mapping errors. */ 5188 if (error) { 5189 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n", 5190 __FILE__, __LINE__); 5191 5192 m_freem(m_new); 5193 DBRUN(sc->debug_pg_mbuf_alloc--); 5194 5195 rc = ENOBUFS; 5196 goto bce_get_pg_buf_exit; 5197 } 5198 5199 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */ 5200 5201 /* 5202 * The page chain uses the same rx_bd data structure 5203 * as the receive chain but doesn't require a byte sequence (bseq). 5204 */ 5205 pgbd = &sc->pg_bd_chain[PG_PAGE(*prod_idx)][PG_IDX(*prod_idx)]; 5206 5207 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(busaddr)); 5208 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(busaddr)); 5209 pgbd->rx_bd_len = htole32(sc->pg_bd_mbuf_alloc_size); 5210 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5211 5212 /* Save the mbuf and update our counter. */ 5213 sc->pg_mbuf_ptr[*prod_idx] = m_new; 5214 sc->free_pg_bd--; 5215 5216 DBRUNMSG(BCE_INSANE_RECV, 5217 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1)); 5218 5219 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5220 "prod_idx = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 5221 5222 bce_get_pg_buf_exit: 5223 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5224 5225 return(rc); 5226 } 5227 #endif /* BCE_JUMBO_HDRSPLIT */ 5228 5229 5230 /****************************************************************************/ 5231 /* Initialize the TX context memory. */ 5232 /* */ 5233 /* Returns: */ 5234 /* Nothing */ 5235 /****************************************************************************/ 5236 static void 5237 bce_init_tx_context(struct bce_softc *sc) 5238 { 5239 u32 val; 5240 5241 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5242 5243 /* Initialize the context ID for an L2 TX chain. */ 5244 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5245 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5246 /* Set the CID type to support an L2 connection. */ 5247 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI | 5248 BCE_L2CTX_TX_TYPE_SIZE_L2_XI; 5249 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val); 5250 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16); 5251 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5252 BCE_L2CTX_TX_CMD_TYPE_XI, val); 5253 5254 /* Point the hardware to the first page in the chain. */ 5255 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5256 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5257 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val); 5258 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5259 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5260 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val); 5261 } else { 5262 /* Set the CID type to support an L2 connection. */ 5263 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2; 5264 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val); 5265 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16); 5266 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val); 5267 5268 /* Point the hardware to the first page in the chain. */ 5269 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5270 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5271 BCE_L2CTX_TX_TBDR_BHADDR_HI, val); 5272 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5273 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5274 BCE_L2CTX_TX_TBDR_BHADDR_LO, val); 5275 } 5276 5277 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5278 } 5279 5280 5281 /****************************************************************************/ 5282 /* Allocate memory and initialize the TX data structures. */ 5283 /* */ 5284 /* Returns: */ 5285 /* 0 for success, positive value for failure. */ 5286 /****************************************************************************/ 5287 static int 5288 bce_init_tx_chain(struct bce_softc *sc) 5289 { 5290 struct tx_bd *txbd; 5291 int i, rc = 0; 5292 5293 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5294 5295 /* Set the initial TX producer/consumer indices. */ 5296 sc->tx_prod = 0; 5297 sc->tx_cons = 0; 5298 sc->tx_prod_bseq = 0; 5299 sc->used_tx_bd = 0; 5300 sc->max_tx_bd = USABLE_TX_BD; 5301 DBRUN(sc->tx_hi_watermark = 0); 5302 DBRUN(sc->tx_full_count = 0); 5303 5304 /* 5305 * The NetXtreme II supports a linked-list structre called 5306 * a Buffer Descriptor Chain (or BD chain). A BD chain 5307 * consists of a series of 1 or more chain pages, each of which 5308 * consists of a fixed number of BD entries. 5309 * The last BD entry on each page is a pointer to the next page 5310 * in the chain, and the last pointer in the BD chain 5311 * points back to the beginning of the chain. 5312 */ 5313 5314 /* Set the TX next pointer chain entries. */ 5315 for (i = 0; i < TX_PAGES; i++) { 5316 int j; 5317 5318 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 5319 5320 /* Check if we've reached the last page. */ 5321 if (i == (TX_PAGES - 1)) 5322 j = 0; 5323 else 5324 j = i + 1; 5325 5326 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 5327 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 5328 } 5329 5330 bce_init_tx_context(sc); 5331 5332 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD)); 5333 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5334 5335 return(rc); 5336 } 5337 5338 5339 /****************************************************************************/ 5340 /* Free memory and clear the TX data structures. */ 5341 /* */ 5342 /* Returns: */ 5343 /* Nothing. */ 5344 /****************************************************************************/ 5345 static void 5346 bce_free_tx_chain(struct bce_softc *sc) 5347 { 5348 int i; 5349 5350 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5351 5352 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 5353 for (i = 0; i < TOTAL_TX_BD; i++) { 5354 if (sc->tx_mbuf_ptr[i] != NULL) { 5355 if (sc->tx_mbuf_map[i] != NULL) 5356 bus_dmamap_sync(sc->tx_mbuf_tag, 5357 sc->tx_mbuf_map[i], 5358 BUS_DMASYNC_POSTWRITE); 5359 m_freem(sc->tx_mbuf_ptr[i]); 5360 sc->tx_mbuf_ptr[i] = NULL; 5361 DBRUN(sc->debug_tx_mbuf_alloc--); 5362 } 5363 } 5364 5365 /* Clear each TX chain page. */ 5366 for (i = 0; i < TX_PAGES; i++) 5367 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 5368 5369 sc->used_tx_bd = 0; 5370 5371 /* Check if we lost any mbufs in the process. */ 5372 DBRUNIF((sc->debug_tx_mbuf_alloc), 5373 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 5374 "from tx chain!\n", __FILE__, __LINE__, 5375 sc->debug_tx_mbuf_alloc)); 5376 5377 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5378 } 5379 5380 5381 /****************************************************************************/ 5382 /* Initialize the RX context memory. */ 5383 /* */ 5384 /* Returns: */ 5385 /* Nothing */ 5386 /****************************************************************************/ 5387 static void 5388 bce_init_rx_context(struct bce_softc *sc) 5389 { 5390 u32 val; 5391 5392 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5393 5394 /* Init the type, size, and BD cache levels for the RX context. */ 5395 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 5396 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | 5397 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT); 5398 5399 /* 5400 * Set the level for generating pause frames 5401 * when the number of available rx_bd's gets 5402 * too low (the low watermark) and the level 5403 * when pause frames can be stopped (the high 5404 * watermark). 5405 */ 5406 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5407 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5408 u32 lo_water, hi_water; 5409 5410 if (sc->bce_flags && BCE_USING_TX_FLOW_CONTROL) { 5411 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT; 5412 } else { 5413 lo_water = 0; 5414 } 5415 5416 if (lo_water >= USABLE_RX_BD) { 5417 lo_water = 0; 5418 } 5419 5420 hi_water = USABLE_RX_BD / 4; 5421 5422 if (hi_water <= lo_water) { 5423 lo_water = 0; 5424 } 5425 5426 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE; 5427 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE; 5428 5429 if (hi_water > 0xf) 5430 hi_water = 0xf; 5431 else if (hi_water == 0) 5432 lo_water = 0; 5433 5434 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) | 5435 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT); 5436 } 5437 5438 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val); 5439 5440 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 5441 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5442 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5443 val = REG_RD(sc, BCE_MQ_MAP_L2_5); 5444 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM); 5445 } 5446 5447 /* Point the hardware to the first page in the chain. */ 5448 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 5449 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val); 5450 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 5451 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val); 5452 5453 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5454 } 5455 5456 5457 /****************************************************************************/ 5458 /* Allocate memory and initialize the RX data structures. */ 5459 /* */ 5460 /* Returns: */ 5461 /* 0 for success, positive value for failure. */ 5462 /****************************************************************************/ 5463 static int 5464 bce_init_rx_chain(struct bce_softc *sc) 5465 { 5466 struct rx_bd *rxbd; 5467 int i, rc = 0; 5468 5469 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5470 BCE_VERBOSE_CTX); 5471 5472 /* Initialize the RX producer and consumer indices. */ 5473 sc->rx_prod = 0; 5474 sc->rx_cons = 0; 5475 sc->rx_prod_bseq = 0; 5476 sc->free_rx_bd = USABLE_RX_BD; 5477 sc->max_rx_bd = USABLE_RX_BD; 5478 5479 /* Initialize the RX next pointer chain entries. */ 5480 for (i = 0; i < RX_PAGES; i++) { 5481 int j; 5482 5483 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 5484 5485 /* Check if we've reached the last page. */ 5486 if (i == (RX_PAGES - 1)) 5487 j = 0; 5488 else 5489 j = i + 1; 5490 5491 /* Setup the chain page pointers. */ 5492 rxbd->rx_bd_haddr_hi = 5493 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 5494 rxbd->rx_bd_haddr_lo = 5495 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 5496 } 5497 5498 /* Fill up the RX chain. */ 5499 bce_fill_rx_chain(sc); 5500 5501 DBRUN(sc->rx_low_watermark = USABLE_RX_BD); 5502 DBRUN(sc->rx_empty_count = 0); 5503 for (i = 0; i < RX_PAGES; i++) { 5504 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i], 5505 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5506 } 5507 5508 bce_init_rx_context(sc); 5509 5510 DBRUNMSG(BCE_EXTREME_RECV, bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD)); 5511 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5512 BCE_VERBOSE_CTX); 5513 5514 /* ToDo: Are there possible failure modes here? */ 5515 5516 return(rc); 5517 } 5518 5519 5520 /****************************************************************************/ 5521 /* Add mbufs to the RX chain until its full or an mbuf allocation error */ 5522 /* occurs. */ 5523 /* */ 5524 /* Returns: */ 5525 /* Nothing */ 5526 /****************************************************************************/ 5527 static void 5528 bce_fill_rx_chain(struct bce_softc *sc) 5529 { 5530 u16 prod, prod_idx; 5531 u32 prod_bseq; 5532 5533 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5534 BCE_VERBOSE_CTX); 5535 5536 /* Get the RX chain producer indices. */ 5537 prod = sc->rx_prod; 5538 prod_bseq = sc->rx_prod_bseq; 5539 5540 /* Keep filling the RX chain until it's full. */ 5541 while (sc->free_rx_bd > 0) { 5542 prod_idx = RX_CHAIN_IDX(prod); 5543 if (bce_get_rx_buf(sc, NULL, &prod, &prod_idx, &prod_bseq)) { 5544 /* Bail out if we can't add an mbuf to the chain. */ 5545 break; 5546 } 5547 prod = NEXT_RX_BD(prod); 5548 } 5549 5550 /* Save the RX chain producer indices. */ 5551 sc->rx_prod = prod; 5552 sc->rx_prod_bseq = prod_bseq; 5553 5554 /* We should never end up pointing to a next page pointer. */ 5555 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5556 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n", 5557 __FUNCTION__, sc->rx_prod)); 5558 5559 /* Write the mailbox and tell the chip about the waiting rx_bd's. */ 5560 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + 5561 BCE_L2MQ_RX_HOST_BDIDX, sc->rx_prod); 5562 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + 5563 BCE_L2MQ_RX_HOST_BSEQ, sc->rx_prod_bseq); 5564 5565 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5566 BCE_VERBOSE_CTX); 5567 } 5568 5569 5570 /****************************************************************************/ 5571 /* Free memory and clear the RX data structures. */ 5572 /* */ 5573 /* Returns: */ 5574 /* Nothing. */ 5575 /****************************************************************************/ 5576 static void 5577 bce_free_rx_chain(struct bce_softc *sc) 5578 { 5579 int i; 5580 5581 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5582 5583 /* Free any mbufs still in the RX mbuf chain. */ 5584 for (i = 0; i < TOTAL_RX_BD; i++) { 5585 if (sc->rx_mbuf_ptr[i] != NULL) { 5586 if (sc->rx_mbuf_map[i] != NULL) 5587 bus_dmamap_sync(sc->rx_mbuf_tag, 5588 sc->rx_mbuf_map[i], 5589 BUS_DMASYNC_POSTREAD); 5590 m_freem(sc->rx_mbuf_ptr[i]); 5591 sc->rx_mbuf_ptr[i] = NULL; 5592 DBRUN(sc->debug_rx_mbuf_alloc--); 5593 } 5594 } 5595 5596 /* Clear each RX chain page. */ 5597 for (i = 0; i < RX_PAGES; i++) 5598 if (sc->rx_bd_chain[i] != NULL) { 5599 bzero((char *)sc->rx_bd_chain[i], 5600 BCE_RX_CHAIN_PAGE_SZ); 5601 } 5602 5603 sc->free_rx_bd = sc->max_rx_bd; 5604 5605 /* Check if we lost any mbufs in the process. */ 5606 DBRUNIF((sc->debug_rx_mbuf_alloc), 5607 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n", 5608 __FUNCTION__, sc->debug_rx_mbuf_alloc)); 5609 5610 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5611 } 5612 5613 5614 #ifdef BCE_JUMBO_HDRSPLIT 5615 /****************************************************************************/ 5616 /* Allocate memory and initialize the page data structures. */ 5617 /* Assumes that bce_init_rx_chain() has not already been called. */ 5618 /* */ 5619 /* Returns: */ 5620 /* 0 for success, positive value for failure. */ 5621 /****************************************************************************/ 5622 static int 5623 bce_init_pg_chain(struct bce_softc *sc) 5624 { 5625 struct rx_bd *pgbd; 5626 int i, rc = 0; 5627 u32 val; 5628 5629 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5630 BCE_VERBOSE_CTX); 5631 5632 /* Initialize the page producer and consumer indices. */ 5633 sc->pg_prod = 0; 5634 sc->pg_cons = 0; 5635 sc->free_pg_bd = USABLE_PG_BD; 5636 sc->max_pg_bd = USABLE_PG_BD; 5637 DBRUN(sc->pg_low_watermark = sc->max_pg_bd); 5638 DBRUN(sc->pg_empty_count = 0); 5639 5640 /* Initialize the page next pointer chain entries. */ 5641 for (i = 0; i < PG_PAGES; i++) { 5642 int j; 5643 5644 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE]; 5645 5646 /* Check if we've reached the last page. */ 5647 if (i == (PG_PAGES - 1)) 5648 j = 0; 5649 else 5650 j = i + 1; 5651 5652 /* Setup the chain page pointers. */ 5653 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j])); 5654 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j])); 5655 } 5656 5657 /* Setup the MQ BIN mapping for host_pg_bidx. */ 5658 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5659 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 5660 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT); 5661 5662 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0); 5663 5664 /* Configure the rx_bd and page chain mbuf cluster size. */ 5665 val = (sc->rx_bd_mbuf_data_len << 16) | sc->pg_bd_mbuf_alloc_size; 5666 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val); 5667 5668 /* Configure the context reserved for jumbo support. */ 5669 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY, 5670 BCE_L2CTX_RX_RBDC_JUMBO_KEY); 5671 5672 /* Point the hardware to the first page in the page chain. */ 5673 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]); 5674 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val); 5675 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]); 5676 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val); 5677 5678 /* Fill up the page chain. */ 5679 bce_fill_pg_chain(sc); 5680 5681 for (i = 0; i < PG_PAGES; i++) { 5682 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i], 5683 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5684 } 5685 5686 DBRUNMSG(BCE_EXTREME_RECV, bce_dump_pg_chain(sc, 0, TOTAL_PG_BD)); 5687 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5688 BCE_VERBOSE_CTX); 5689 return(rc); 5690 } 5691 5692 5693 /****************************************************************************/ 5694 /* Add mbufs to the page chain until its full or an mbuf allocation error */ 5695 /* occurs. */ 5696 /* */ 5697 /* Returns: */ 5698 /* Nothing */ 5699 /****************************************************************************/ 5700 static void 5701 bce_fill_pg_chain(struct bce_softc *sc) 5702 { 5703 u16 prod, prod_idx; 5704 5705 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5706 BCE_VERBOSE_CTX); 5707 5708 /* Get the page chain prodcuer index. */ 5709 prod = sc->pg_prod; 5710 5711 /* Keep filling the page chain until it's full. */ 5712 while (sc->free_pg_bd > 0) { 5713 prod_idx = PG_CHAIN_IDX(prod); 5714 if (bce_get_pg_buf(sc, NULL, &prod, &prod_idx)) { 5715 /* Bail out if we can't add an mbuf to the chain. */ 5716 break; 5717 } 5718 prod = NEXT_PG_BD(prod); 5719 } 5720 5721 /* Save the page chain producer index. */ 5722 sc->pg_prod = prod; 5723 5724 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5725 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n", 5726 __FUNCTION__, sc->pg_prod)); 5727 5728 /* 5729 * Write the mailbox and tell the chip about 5730 * the new rx_bd's in the page chain. 5731 */ 5732 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + 5733 BCE_L2MQ_RX_HOST_PG_BDIDX, sc->pg_prod); 5734 5735 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5736 BCE_VERBOSE_CTX); 5737 } 5738 5739 5740 /****************************************************************************/ 5741 /* Free memory and clear the RX data structures. */ 5742 /* */ 5743 /* Returns: */ 5744 /* Nothing. */ 5745 /****************************************************************************/ 5746 static void 5747 bce_free_pg_chain(struct bce_softc *sc) 5748 { 5749 int i; 5750 5751 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5752 5753 /* Free any mbufs still in the mbuf page chain. */ 5754 for (i = 0; i < TOTAL_PG_BD; i++) { 5755 if (sc->pg_mbuf_ptr[i] != NULL) { 5756 if (sc->pg_mbuf_map[i] != NULL) 5757 bus_dmamap_sync(sc->pg_mbuf_tag, 5758 sc->pg_mbuf_map[i], 5759 BUS_DMASYNC_POSTREAD); 5760 m_freem(sc->pg_mbuf_ptr[i]); 5761 sc->pg_mbuf_ptr[i] = NULL; 5762 DBRUN(sc->debug_pg_mbuf_alloc--); 5763 } 5764 } 5765 5766 /* Clear each page chain pages. */ 5767 for (i = 0; i < PG_PAGES; i++) 5768 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 5769 5770 sc->free_pg_bd = sc->max_pg_bd; 5771 5772 /* Check if we lost any mbufs in the process. */ 5773 DBRUNIF((sc->debug_pg_mbuf_alloc), 5774 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n", 5775 __FUNCTION__, sc->debug_pg_mbuf_alloc)); 5776 5777 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5778 } 5779 #endif /* BCE_JUMBO_HDRSPLIT */ 5780 5781 5782 /****************************************************************************/ 5783 /* Set media options. */ 5784 /* */ 5785 /* Returns: */ 5786 /* 0 for success, positive value for failure. */ 5787 /****************************************************************************/ 5788 static int 5789 bce_ifmedia_upd(struct ifnet *ifp) 5790 { 5791 struct bce_softc *sc = ifp->if_softc; 5792 int error; 5793 5794 DBENTER(BCE_VERBOSE); 5795 5796 BCE_LOCK(sc); 5797 error = bce_ifmedia_upd_locked(ifp); 5798 BCE_UNLOCK(sc); 5799 5800 DBEXIT(BCE_VERBOSE); 5801 return (error); 5802 } 5803 5804 5805 /****************************************************************************/ 5806 /* Set media options. */ 5807 /* */ 5808 /* Returns: */ 5809 /* Nothing. */ 5810 /****************************************************************************/ 5811 static int 5812 bce_ifmedia_upd_locked(struct ifnet *ifp) 5813 { 5814 struct bce_softc *sc = ifp->if_softc; 5815 struct mii_data *mii; 5816 int error; 5817 5818 DBENTER(BCE_VERBOSE_PHY); 5819 5820 error = 0; 5821 BCE_LOCK_ASSERT(sc); 5822 5823 mii = device_get_softc(sc->bce_miibus); 5824 5825 /* Make sure the MII bus has been enumerated. */ 5826 if (mii) { 5827 sc->bce_link_up = FALSE; 5828 if (mii->mii_instance) { 5829 struct mii_softc *miisc; 5830 5831 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 5832 mii_phy_reset(miisc); 5833 } 5834 error = mii_mediachg(mii); 5835 } 5836 5837 DBEXIT(BCE_VERBOSE_PHY); 5838 return (error); 5839 } 5840 5841 5842 /****************************************************************************/ 5843 /* Reports current media status. */ 5844 /* */ 5845 /* Returns: */ 5846 /* Nothing. */ 5847 /****************************************************************************/ 5848 static void 5849 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5850 { 5851 struct bce_softc *sc = ifp->if_softc; 5852 struct mii_data *mii; 5853 5854 DBENTER(BCE_VERBOSE_PHY); 5855 5856 BCE_LOCK(sc); 5857 5858 if ((ifp->if_flags & IFF_UP) == 0) { 5859 BCE_UNLOCK(sc); 5860 return; 5861 } 5862 mii = device_get_softc(sc->bce_miibus); 5863 5864 mii_pollstat(mii); 5865 ifmr->ifm_active = mii->mii_media_active; 5866 ifmr->ifm_status = mii->mii_media_status; 5867 5868 BCE_UNLOCK(sc); 5869 5870 DBEXIT(BCE_VERBOSE_PHY); 5871 } 5872 5873 5874 /****************************************************************************/ 5875 /* Handles PHY generated interrupt events. */ 5876 /* */ 5877 /* Returns: */ 5878 /* Nothing. */ 5879 /****************************************************************************/ 5880 static void 5881 bce_phy_intr(struct bce_softc *sc) 5882 { 5883 u32 new_link_state, old_link_state; 5884 5885 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 5886 5887 DBRUN(sc->phy_interrupts++); 5888 5889 new_link_state = sc->status_block->status_attn_bits & 5890 STATUS_ATTN_BITS_LINK_STATE; 5891 old_link_state = sc->status_block->status_attn_bits_ack & 5892 STATUS_ATTN_BITS_LINK_STATE; 5893 5894 /* Handle any changes if the link state has changed. */ 5895 if (new_link_state != old_link_state) { 5896 5897 /* Update the status_attn_bits_ack field. */ 5898 if (new_link_state) { 5899 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 5900 STATUS_ATTN_BITS_LINK_STATE); 5901 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n", 5902 __FUNCTION__); 5903 } 5904 else { 5905 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 5906 STATUS_ATTN_BITS_LINK_STATE); 5907 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n", 5908 __FUNCTION__); 5909 } 5910 5911 /* 5912 * Assume link is down and allow 5913 * tick routine to update the state 5914 * based on the actual media state. 5915 */ 5916 sc->bce_link_up = FALSE; 5917 callout_stop(&sc->bce_tick_callout); 5918 bce_tick(sc); 5919 } 5920 5921 /* Acknowledge the link change interrupt. */ 5922 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 5923 5924 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 5925 } 5926 5927 5928 /****************************************************************************/ 5929 /* Reads the receive consumer value from the status block (skipping over */ 5930 /* chain page pointer if necessary). */ 5931 /* */ 5932 /* Returns: */ 5933 /* hw_cons */ 5934 /****************************************************************************/ 5935 static inline u16 5936 bce_get_hw_rx_cons(struct bce_softc *sc) 5937 { 5938 u16 hw_cons; 5939 5940 rmb(); 5941 hw_cons = sc->status_block->status_rx_quick_consumer_index0; 5942 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 5943 hw_cons++; 5944 5945 return hw_cons; 5946 } 5947 5948 /****************************************************************************/ 5949 /* Handles received frame interrupt events. */ 5950 /* */ 5951 /* Returns: */ 5952 /* Nothing. */ 5953 /****************************************************************************/ 5954 static void 5955 bce_rx_intr(struct bce_softc *sc) 5956 { 5957 struct ifnet *ifp = sc->bce_ifp; 5958 struct l2_fhdr *l2fhdr; 5959 struct ether_vlan_header *vh; 5960 unsigned int pkt_len; 5961 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons; 5962 u32 status; 5963 #ifdef BCE_JUMBO_HDRSPLIT 5964 unsigned int rem_len; 5965 u16 sw_pg_cons, sw_pg_cons_idx; 5966 #endif 5967 5968 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 5969 DBRUN(sc->interrupts_rx++); 5970 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, " 5971 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 5972 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 5973 5974 /* Prepare the RX chain pages to be accessed by the host CPU. */ 5975 for (int i = 0; i < RX_PAGES; i++) 5976 bus_dmamap_sync(sc->rx_bd_chain_tag, 5977 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 5978 5979 #ifdef BCE_JUMBO_HDRSPLIT 5980 /* Prepare the page chain pages to be accessed by the host CPU. */ 5981 for (int i = 0; i < PG_PAGES; i++) 5982 bus_dmamap_sync(sc->pg_bd_chain_tag, 5983 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 5984 #endif 5985 5986 /* Get the hardware's view of the RX consumer index. */ 5987 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 5988 5989 /* Get working copies of the driver's view of the consumer indices. */ 5990 sw_rx_cons = sc->rx_cons; 5991 5992 #ifdef BCE_JUMBO_HDRSPLIT 5993 sw_pg_cons = sc->pg_cons; 5994 #endif 5995 5996 /* Update some debug statistics counters */ 5997 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 5998 sc->rx_low_watermark = sc->free_rx_bd); 5999 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 6000 sc->rx_empty_count++); 6001 6002 /* Scan through the receive chain as long as there is work to do */ 6003 /* ToDo: Consider setting a limit on the number of packets processed. */ 6004 rmb(); 6005 while (sw_rx_cons != hw_rx_cons) { 6006 struct mbuf *m0; 6007 6008 /* Convert the producer/consumer indices to an actual rx_bd index. */ 6009 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons); 6010 6011 /* Unmap the mbuf from DMA space. */ 6012 bus_dmamap_sync(sc->rx_mbuf_tag, 6013 sc->rx_mbuf_map[sw_rx_cons_idx], 6014 BUS_DMASYNC_POSTREAD); 6015 bus_dmamap_unload(sc->rx_mbuf_tag, 6016 sc->rx_mbuf_map[sw_rx_cons_idx]); 6017 6018 /* Remove the mbuf from the RX chain. */ 6019 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx]; 6020 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL; 6021 DBRUN(sc->debug_rx_mbuf_alloc--); 6022 sc->free_rx_bd++; 6023 6024 if(m0 == NULL) { 6025 DBPRINT(sc, BCE_EXTREME_RECV, 6026 "%s(): Oops! Empty mbuf pointer " 6027 "found in sc->rx_mbuf_ptr[0x%04X]!\n", 6028 __FUNCTION__, sw_rx_cons_idx); 6029 goto bce_rx_int_next_rx; 6030 } 6031 6032 /* 6033 * Frames received on the NetXteme II are prepended 6034 * with an l2_fhdr structure which provides status 6035 * information about the received frame (including 6036 * VLAN tags and checksum info). The frames are 6037 * also automatically adjusted to align the IP 6038 * header (i.e. two null bytes are inserted before 6039 * the Ethernet header). As a result the data 6040 * DMA'd by the controller into the mbuf looks 6041 * like this: 6042 * 6043 * +---------+-----+---------------------+-----+ 6044 * | l2_fhdr | pad | packet data | FCS | 6045 * +---------+-----+---------------------+-----+ 6046 * 6047 * The l2_fhdr needs to be checked and skipped and 6048 * the FCS needs to be stripped before sending the 6049 * packet up the stack. 6050 */ 6051 l2fhdr = mtod(m0, struct l2_fhdr *); 6052 6053 /* Get the packet data + FCS length and the status. */ 6054 pkt_len = l2fhdr->l2_fhdr_pkt_len; 6055 status = l2fhdr->l2_fhdr_status; 6056 6057 /* 6058 * Skip over the l2_fhdr and pad, resulting in the 6059 * following data in the mbuf: 6060 * +---------------------+-----+ 6061 * | packet data | FCS | 6062 * +---------------------+-----+ 6063 */ 6064 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN); 6065 6066 #ifdef BCE_JUMBO_HDRSPLIT 6067 /* 6068 * Check whether the received frame fits in a single 6069 * mbuf or not (i.e. packet data + FCS <= 6070 * sc->rx_bd_mbuf_data_len bytes). 6071 */ 6072 if (pkt_len > m0->m_len) { 6073 /* 6074 * The received frame is larger than a single mbuf. 6075 * If the frame was a TCP frame then only the TCP 6076 * header is placed in the mbuf, the remaining 6077 * payload (including FCS) is placed in the page 6078 * chain, the SPLIT flag is set, and the header 6079 * length is placed in the IP checksum field. 6080 * If the frame is not a TCP frame then the mbuf 6081 * is filled and the remaining bytes are placed 6082 * in the page chain. 6083 */ 6084 6085 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large " 6086 "packet.\n", __FUNCTION__); 6087 6088 /* 6089 * When the page chain is enabled and the TCP 6090 * header has been split from the TCP payload, 6091 * the ip_xsum structure will reflect the length 6092 * of the TCP header, not the IP checksum. Set 6093 * the packet length of the mbuf accordingly. 6094 */ 6095 if (status & L2_FHDR_STATUS_SPLIT) 6096 m0->m_len = l2fhdr->l2_fhdr_ip_xsum; 6097 6098 rem_len = pkt_len - m0->m_len; 6099 6100 /* Pull mbufs off the page chain for the remaining data. */ 6101 while (rem_len > 0) { 6102 struct mbuf *m_pg; 6103 6104 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons); 6105 6106 /* Remove the mbuf from the page chain. */ 6107 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx]; 6108 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL; 6109 DBRUN(sc->debug_pg_mbuf_alloc--); 6110 sc->free_pg_bd++; 6111 6112 /* Unmap the page chain mbuf from DMA space. */ 6113 bus_dmamap_sync(sc->pg_mbuf_tag, 6114 sc->pg_mbuf_map[sw_pg_cons_idx], 6115 BUS_DMASYNC_POSTREAD); 6116 bus_dmamap_unload(sc->pg_mbuf_tag, 6117 sc->pg_mbuf_map[sw_pg_cons_idx]); 6118 6119 /* Adjust the mbuf length. */ 6120 if (rem_len < m_pg->m_len) { 6121 /* The mbuf chain is complete. */ 6122 m_pg->m_len = rem_len; 6123 rem_len = 0; 6124 } else { 6125 /* More packet data is waiting. */ 6126 rem_len -= m_pg->m_len; 6127 } 6128 6129 /* Concatenate the mbuf cluster to the mbuf. */ 6130 m_cat(m0, m_pg); 6131 6132 sw_pg_cons = NEXT_PG_BD(sw_pg_cons); 6133 } 6134 6135 /* Set the total packet length. */ 6136 m0->m_pkthdr.len = pkt_len; 6137 6138 } else { 6139 /* 6140 * The received packet is small and fits in a 6141 * single mbuf (i.e. the l2_fhdr + pad + packet + 6142 * FCS <= MHLEN). In other words, the packet is 6143 * 154 bytes or less in size. 6144 */ 6145 6146 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small " 6147 "packet.\n", __FUNCTION__); 6148 6149 /* Set the total packet length. */ 6150 m0->m_pkthdr.len = m0->m_len = pkt_len; 6151 } 6152 #else 6153 /* Set the total packet length. */ 6154 m0->m_pkthdr.len = m0->m_len = pkt_len; 6155 #endif 6156 6157 /* Remove the trailing Ethernet FCS. */ 6158 m_adj(m0, -ETHER_CRC_LEN); 6159 6160 /* Check that the resulting mbuf chain is valid. */ 6161 DBRUN(m_sanity(m0, FALSE)); 6162 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) | 6163 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 6164 BCE_PRINTF("Invalid Ethernet frame size!\n"); 6165 m_print(m0, 128)); 6166 6167 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control), 6168 sc->l2fhdr_error_sim_count++; 6169 status = status | L2_FHDR_ERRORS_PHY_DECODE); 6170 6171 /* Check the received frame for errors. */ 6172 if (status & (L2_FHDR_ERRORS_BAD_CRC | 6173 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 6174 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 6175 6176 /* Log the error and release the mbuf. */ 6177 ifp->if_ierrors++; 6178 sc->l2fhdr_error_count++; 6179 6180 m_freem(m0); 6181 m0 = NULL; 6182 goto bce_rx_int_next_rx; 6183 } 6184 6185 /* Send the packet to the appropriate interface. */ 6186 m0->m_pkthdr.rcvif = ifp; 6187 6188 /* Assume no hardware checksum. */ 6189 m0->m_pkthdr.csum_flags = 0; 6190 6191 /* Validate the checksum if offload enabled. */ 6192 if (ifp->if_capenable & IFCAP_RXCSUM) { 6193 6194 /* Check for an IP datagram. */ 6195 if (!(status & L2_FHDR_STATUS_SPLIT) && 6196 (status & L2_FHDR_STATUS_IP_DATAGRAM)) { 6197 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 6198 DBRUN(sc->csum_offload_ip++); 6199 /* Check if the IP checksum is valid. */ 6200 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 6201 m0->m_pkthdr.csum_flags |= 6202 CSUM_IP_VALID; 6203 } 6204 6205 /* Check for a valid TCP/UDP frame. */ 6206 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 6207 L2_FHDR_STATUS_UDP_DATAGRAM)) { 6208 6209 /* Check for a good TCP/UDP checksum. */ 6210 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 6211 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 6212 DBRUN(sc->csum_offload_tcp_udp++); 6213 m0->m_pkthdr.csum_data = 6214 l2fhdr->l2_fhdr_tcp_udp_xsum; 6215 m0->m_pkthdr.csum_flags |= 6216 (CSUM_DATA_VALID 6217 | CSUM_PSEUDO_HDR); 6218 } 6219 } 6220 } 6221 6222 /* Attach the VLAN tag. */ 6223 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { 6224 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 6225 #if __FreeBSD_version < 700000 6226 VLAN_INPUT_TAG(ifp, m0, 6227 l2fhdr->l2_fhdr_vlan_tag, continue); 6228 #else 6229 m0->m_pkthdr.ether_vtag = 6230 l2fhdr->l2_fhdr_vlan_tag; 6231 m0->m_flags |= M_VLANTAG; 6232 #endif 6233 } else { 6234 /* 6235 * bce(4) controllers can't disable VLAN 6236 * tag stripping if management firmware 6237 * (ASF/IPMI/UMP) is running. So we always 6238 * strip VLAN tag and manually reconstruct 6239 * the VLAN frame by appending stripped 6240 * VLAN tag in driver if VLAN tag stripping 6241 * was disabled. 6242 * 6243 * TODO: LLC SNAP handling. 6244 */ 6245 bcopy(mtod(m0, uint8_t *), 6246 mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN, 6247 ETHER_ADDR_LEN * 2); 6248 m0->m_data -= ETHER_VLAN_ENCAP_LEN; 6249 vh = mtod(m0, struct ether_vlan_header *); 6250 vh->evl_encap_proto = htons(ETHERTYPE_VLAN); 6251 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag); 6252 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN; 6253 m0->m_len += ETHER_VLAN_ENCAP_LEN; 6254 } 6255 } 6256 6257 /* Increment received packet statistics. */ 6258 ifp->if_ipackets++; 6259 6260 bce_rx_int_next_rx: 6261 sw_rx_cons = NEXT_RX_BD(sw_rx_cons); 6262 6263 /* If we have a packet, pass it up the stack */ 6264 if (m0) { 6265 /* Make sure we don't lose our place when we release the lock. */ 6266 sc->rx_cons = sw_rx_cons; 6267 #ifdef BCE_JUMBO_HDRSPLIT 6268 sc->pg_cons = sw_pg_cons; 6269 #endif 6270 6271 BCE_UNLOCK(sc); 6272 (*ifp->if_input)(ifp, m0); 6273 BCE_LOCK(sc); 6274 6275 /* Recover our place. */ 6276 sw_rx_cons = sc->rx_cons; 6277 #ifdef BCE_JUMBO_HDRSPLIT 6278 sw_pg_cons = sc->pg_cons; 6279 #endif 6280 } 6281 6282 /* Refresh hw_cons to see if there's new work */ 6283 if (sw_rx_cons == hw_rx_cons) 6284 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6285 } 6286 6287 #ifdef BCE_JUMBO_HDRSPLIT 6288 /* No new packets. Refill the page chain. */ 6289 sc->pg_cons = sw_pg_cons; 6290 bce_fill_pg_chain(sc); 6291 #endif 6292 6293 /* No new packets. Refill the RX chain. */ 6294 sc->rx_cons = sw_rx_cons; 6295 bce_fill_rx_chain(sc); 6296 6297 /* Prepare the page chain pages to be accessed by the NIC. */ 6298 for (int i = 0; i < RX_PAGES; i++) 6299 bus_dmamap_sync(sc->rx_bd_chain_tag, 6300 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6301 6302 #ifdef BCE_JUMBO_HDRSPLIT 6303 for (int i = 0; i < PG_PAGES; i++) 6304 bus_dmamap_sync(sc->pg_bd_chain_tag, 6305 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6306 #endif 6307 6308 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, " 6309 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6310 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6311 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6312 } 6313 6314 6315 /****************************************************************************/ 6316 /* Reads the transmit consumer value from the status block (skipping over */ 6317 /* chain page pointer if necessary). */ 6318 /* */ 6319 /* Returns: */ 6320 /* hw_cons */ 6321 /****************************************************************************/ 6322 static inline u16 6323 bce_get_hw_tx_cons(struct bce_softc *sc) 6324 { 6325 u16 hw_cons; 6326 6327 mb(); 6328 hw_cons = sc->status_block->status_tx_quick_consumer_index0; 6329 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6330 hw_cons++; 6331 6332 return hw_cons; 6333 } 6334 6335 6336 /****************************************************************************/ 6337 /* Handles transmit completion interrupt events. */ 6338 /* */ 6339 /* Returns: */ 6340 /* Nothing. */ 6341 /****************************************************************************/ 6342 static void 6343 bce_tx_intr(struct bce_softc *sc) 6344 { 6345 struct ifnet *ifp = sc->bce_ifp; 6346 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 6347 6348 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6349 DBRUN(sc->interrupts_tx++); 6350 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, " 6351 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6352 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6353 6354 BCE_LOCK_ASSERT(sc); 6355 6356 /* Get the hardware's view of the TX consumer index. */ 6357 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6358 sw_tx_cons = sc->tx_cons; 6359 6360 /* Prevent speculative reads of the status block. */ 6361 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6362 BUS_SPACE_BARRIER_READ); 6363 6364 /* Cycle through any completed TX chain page entries. */ 6365 while (sw_tx_cons != hw_tx_cons) { 6366 #ifdef BCE_DEBUG 6367 struct tx_bd *txbd = NULL; 6368 #endif 6369 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 6370 6371 DBPRINT(sc, BCE_INFO_SEND, 6372 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 6373 "sw_tx_chain_cons = 0x%04X\n", 6374 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 6375 6376 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 6377 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 6378 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 6379 (int) MAX_TX_BD); 6380 bce_breakpoint(sc)); 6381 6382 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 6383 [TX_IDX(sw_tx_chain_cons)]); 6384 6385 DBRUNIF((txbd == NULL), 6386 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 6387 __FILE__, __LINE__, sw_tx_chain_cons); 6388 bce_breakpoint(sc)); 6389 6390 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 6391 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 6392 6393 /* 6394 * Free the associated mbuf. Remember 6395 * that only the last tx_bd of a packet 6396 * has an mbuf pointer and DMA map. 6397 */ 6398 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 6399 6400 /* Validate that this is the last tx_bd. */ 6401 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 6402 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 6403 "txmbuf == NULL!\n", __FILE__, __LINE__); 6404 bce_breakpoint(sc)); 6405 6406 DBRUNMSG(BCE_INFO_SEND, 6407 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 6408 "from tx_bd[0x%04X]\n", __FUNCTION__, 6409 sw_tx_chain_cons)); 6410 6411 /* Unmap the mbuf. */ 6412 bus_dmamap_unload(sc->tx_mbuf_tag, 6413 sc->tx_mbuf_map[sw_tx_chain_cons]); 6414 6415 /* Free the mbuf. */ 6416 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 6417 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 6418 DBRUN(sc->debug_tx_mbuf_alloc--); 6419 6420 ifp->if_opackets++; 6421 } 6422 6423 sc->used_tx_bd--; 6424 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 6425 6426 /* Refresh hw_cons to see if there's new work. */ 6427 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6428 6429 /* Prevent speculative reads of the status block. */ 6430 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6431 BUS_SPACE_BARRIER_READ); 6432 } 6433 6434 /* Clear the TX timeout timer. */ 6435 sc->watchdog_timer = 0; 6436 6437 /* Clear the tx hardware queue full flag. */ 6438 if (sc->used_tx_bd < sc->max_tx_bd) { 6439 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 6440 DBPRINT(sc, BCE_INFO_SEND, 6441 "%s(): Open TX chain! %d/%d (used/total)\n", 6442 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 6443 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6444 } 6445 6446 sc->tx_cons = sw_tx_cons; 6447 6448 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, " 6449 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6450 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6451 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6452 } 6453 6454 6455 /****************************************************************************/ 6456 /* Disables interrupt generation. */ 6457 /* */ 6458 /* Returns: */ 6459 /* Nothing. */ 6460 /****************************************************************************/ 6461 static void 6462 bce_disable_intr(struct bce_softc *sc) 6463 { 6464 DBENTER(BCE_VERBOSE_INTR); 6465 6466 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 6467 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 6468 6469 DBEXIT(BCE_VERBOSE_INTR); 6470 } 6471 6472 6473 /****************************************************************************/ 6474 /* Enables interrupt generation. */ 6475 /* */ 6476 /* Returns: */ 6477 /* Nothing. */ 6478 /****************************************************************************/ 6479 static void 6480 bce_enable_intr(struct bce_softc *sc, int coal_now) 6481 { 6482 DBENTER(BCE_VERBOSE_INTR); 6483 6484 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6485 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 6486 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 6487 6488 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6489 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 6490 6491 /* Force an immediate interrupt (whether there is new data or not). */ 6492 if (coal_now) 6493 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW); 6494 6495 DBEXIT(BCE_VERBOSE_INTR); 6496 } 6497 6498 6499 /****************************************************************************/ 6500 /* Handles controller initialization. */ 6501 /* */ 6502 /* Returns: */ 6503 /* Nothing. */ 6504 /****************************************************************************/ 6505 static void 6506 bce_init_locked(struct bce_softc *sc) 6507 { 6508 struct ifnet *ifp; 6509 u32 ether_mtu = 0; 6510 6511 DBENTER(BCE_VERBOSE_RESET); 6512 6513 BCE_LOCK_ASSERT(sc); 6514 6515 ifp = sc->bce_ifp; 6516 6517 /* Check if the driver is still running and bail out if it is. */ 6518 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6519 goto bce_init_locked_exit; 6520 6521 bce_stop(sc); 6522 6523 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 6524 BCE_PRINTF("%s(%d): Controller reset failed!\n", 6525 __FILE__, __LINE__); 6526 goto bce_init_locked_exit; 6527 } 6528 6529 if (bce_chipinit(sc)) { 6530 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 6531 __FILE__, __LINE__); 6532 goto bce_init_locked_exit; 6533 } 6534 6535 if (bce_blockinit(sc)) { 6536 BCE_PRINTF("%s(%d): Block initialization failed!\n", 6537 __FILE__, __LINE__); 6538 goto bce_init_locked_exit; 6539 } 6540 6541 /* Load our MAC address. */ 6542 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 6543 bce_set_mac_addr(sc); 6544 6545 /* 6546 * Calculate and program the hardware Ethernet MTU 6547 * size. Be generous on the receive if we have room. 6548 */ 6549 #ifdef BCE_JUMBO_HDRSPLIT 6550 if (ifp->if_mtu <= (sc->rx_bd_mbuf_data_len + 6551 sc->pg_bd_mbuf_alloc_size)) 6552 ether_mtu = sc->rx_bd_mbuf_data_len + 6553 sc->pg_bd_mbuf_alloc_size; 6554 #else 6555 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len) 6556 ether_mtu = sc->rx_bd_mbuf_data_len; 6557 #endif 6558 else 6559 ether_mtu = ifp->if_mtu; 6560 6561 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 6562 6563 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", 6564 __FUNCTION__, ether_mtu); 6565 6566 /* Program the mtu, enabling jumbo frame support if necessary. */ 6567 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)) 6568 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, 6569 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 6570 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 6571 else 6572 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 6573 6574 DBPRINT(sc, BCE_INFO_LOAD, 6575 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bce_mbuf_data_len = %d, " 6576 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__, 6577 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len, 6578 sc->rx_bd_mbuf_align_pad); 6579 6580 /* Program appropriate promiscuous/multicast filtering. */ 6581 bce_set_rx_mode(sc); 6582 6583 #ifdef BCE_JUMBO_HDRSPLIT 6584 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_mbuf_alloc_size = %d\n", 6585 __FUNCTION__, sc->pg_bd_mbuf_alloc_size); 6586 6587 /* Init page buffer descriptor chain. */ 6588 bce_init_pg_chain(sc); 6589 #endif 6590 6591 /* Init RX buffer descriptor chain. */ 6592 bce_init_rx_chain(sc); 6593 6594 /* Init TX buffer descriptor chain. */ 6595 bce_init_tx_chain(sc); 6596 6597 /* Enable host interrupts. */ 6598 bce_enable_intr(sc, 1); 6599 6600 bce_ifmedia_upd_locked(ifp); 6601 6602 /* Let the OS know the driver is up and running. */ 6603 ifp->if_drv_flags |= IFF_DRV_RUNNING; 6604 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6605 6606 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 6607 6608 bce_init_locked_exit: 6609 DBEXIT(BCE_VERBOSE_RESET); 6610 } 6611 6612 6613 /****************************************************************************/ 6614 /* Initialize the controller just enough so that any management firmware */ 6615 /* running on the device will continue to operate correctly. */ 6616 /* */ 6617 /* Returns: */ 6618 /* Nothing. */ 6619 /****************************************************************************/ 6620 static void 6621 bce_mgmt_init_locked(struct bce_softc *sc) 6622 { 6623 struct ifnet *ifp; 6624 6625 DBENTER(BCE_VERBOSE_RESET); 6626 6627 BCE_LOCK_ASSERT(sc); 6628 6629 /* Bail out if management firmware is not running. */ 6630 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 6631 DBPRINT(sc, BCE_VERBOSE_SPECIAL, 6632 "No management firmware running...\n"); 6633 goto bce_mgmt_init_locked_exit; 6634 } 6635 6636 ifp = sc->bce_ifp; 6637 6638 /* Enable all critical blocks in the MAC. */ 6639 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 6640 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 6641 DELAY(20); 6642 6643 bce_ifmedia_upd_locked(ifp); 6644 6645 bce_mgmt_init_locked_exit: 6646 DBEXIT(BCE_VERBOSE_RESET); 6647 } 6648 6649 6650 /****************************************************************************/ 6651 /* Handles controller initialization when called from an unlocked routine. */ 6652 /* */ 6653 /* Returns: */ 6654 /* Nothing. */ 6655 /****************************************************************************/ 6656 static void 6657 bce_init(void *xsc) 6658 { 6659 struct bce_softc *sc = xsc; 6660 6661 DBENTER(BCE_VERBOSE_RESET); 6662 6663 BCE_LOCK(sc); 6664 bce_init_locked(sc); 6665 BCE_UNLOCK(sc); 6666 6667 DBEXIT(BCE_VERBOSE_RESET); 6668 } 6669 6670 6671 /****************************************************************************/ 6672 /* Modifies an mbuf for TSO on the hardware. */ 6673 /* */ 6674 /* Returns: */ 6675 /* Pointer to a modified mbuf. */ 6676 /****************************************************************************/ 6677 static struct mbuf * 6678 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags) 6679 { 6680 struct mbuf *m; 6681 struct ether_header *eh; 6682 struct ip *ip; 6683 struct tcphdr *th; 6684 u16 etype; 6685 int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0; 6686 6687 DBRUN(sc->tso_frames_requested++); 6688 6689 /* Controller may modify mbuf chains. */ 6690 if (M_WRITABLE(*m_head) == 0) { 6691 m = m_dup(*m_head, M_DONTWAIT); 6692 m_freem(*m_head); 6693 if (m == NULL) { 6694 sc->mbuf_alloc_failed_count++; 6695 *m_head = NULL; 6696 return (NULL); 6697 } 6698 *m_head = m; 6699 } 6700 6701 /* 6702 * For TSO the controller needs two pieces of info, 6703 * the MSS and the IP+TCP options length. 6704 */ 6705 m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip)); 6706 if (m == NULL) { 6707 *m_head = NULL; 6708 return (NULL); 6709 } 6710 eh = mtod(m, struct ether_header *); 6711 etype = ntohs(eh->ether_type); 6712 6713 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 6714 switch (etype) { 6715 case ETHERTYPE_IP: 6716 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 6717 /* TSO only supported for TCP protocol. */ 6718 if (ip->ip_p != IPPROTO_TCP) { 6719 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 6720 __FILE__, __LINE__); 6721 m_freem(*m_head); 6722 *m_head = NULL; 6723 return (NULL); 6724 } 6725 6726 /* Get IP header length in bytes (min 20) */ 6727 ip_hlen = ip->ip_hl << 2; 6728 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen + 6729 sizeof(struct tcphdr)); 6730 if (m == NULL) { 6731 *m_head = NULL; 6732 return (NULL); 6733 } 6734 6735 /* Get the TCP header length in bytes (min 20) */ 6736 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 6737 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 6738 tcp_hlen = (th->th_off << 2); 6739 6740 /* Make sure all IP/TCP options live in the same buffer. */ 6741 m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen + 6742 tcp_hlen); 6743 if (m == NULL) { 6744 *m_head = NULL; 6745 return (NULL); 6746 } 6747 6748 /* IP header length and checksum will be calc'd by hardware */ 6749 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 6750 ip_len = ip->ip_len; 6751 ip->ip_len = 0; 6752 ip->ip_sum = 0; 6753 break; 6754 case ETHERTYPE_IPV6: 6755 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 6756 __FILE__, __LINE__); 6757 m_freem(*m_head); 6758 *m_head = NULL; 6759 return (NULL); 6760 /* NOT REACHED */ 6761 default: 6762 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 6763 __FILE__, __LINE__); 6764 m_freem(*m_head); 6765 *m_head = NULL; 6766 return (NULL); 6767 } 6768 6769 hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen; 6770 6771 DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, " 6772 "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 6773 __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen, 6774 tcp_hlen, ip_len); 6775 6776 /* Set the LSO flag in the TX BD */ 6777 *flags |= TX_BD_FLAGS_SW_LSO; 6778 6779 /* Set the length of IP + TCP options (in 32 bit words) */ 6780 *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) - 6781 sizeof(struct tcphdr)) >> 2) << 8); 6782 6783 DBRUN(sc->tso_frames_completed++); 6784 return (*m_head); 6785 } 6786 6787 6788 /****************************************************************************/ 6789 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 6790 /* memory visible to the controller. */ 6791 /* */ 6792 /* Returns: */ 6793 /* 0 for success, positive value for failure. */ 6794 /* Modified: */ 6795 /* m_head: May be set to NULL if MBUF is excessively fragmented. */ 6796 /****************************************************************************/ 6797 static int 6798 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 6799 { 6800 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 6801 bus_dmamap_t map; 6802 struct tx_bd *txbd = NULL; 6803 struct mbuf *m0; 6804 u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0; 6805 u32 prod_bseq; 6806 6807 #ifdef BCE_DEBUG 6808 u16 debug_prod; 6809 #endif 6810 6811 int i, error, nsegs, rc = 0; 6812 6813 DBENTER(BCE_VERBOSE_SEND); 6814 6815 /* Make sure we have room in the TX chain. */ 6816 if (sc->used_tx_bd >= sc->max_tx_bd) 6817 goto bce_tx_encap_exit; 6818 6819 /* Transfer any checksum offload flags to the bd. */ 6820 m0 = *m_head; 6821 if (m0->m_pkthdr.csum_flags) { 6822 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 6823 m0 = bce_tso_setup(sc, m_head, &flags); 6824 if (m0 == NULL) { 6825 DBRUN(sc->tso_frames_failed++); 6826 goto bce_tx_encap_exit; 6827 } 6828 mss = htole16(m0->m_pkthdr.tso_segsz); 6829 } else { 6830 if (m0->m_pkthdr.csum_flags & CSUM_IP) 6831 flags |= TX_BD_FLAGS_IP_CKSUM; 6832 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 6833 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 6834 } 6835 } 6836 6837 /* Transfer any VLAN tags to the bd. */ 6838 if (m0->m_flags & M_VLANTAG) { 6839 flags |= TX_BD_FLAGS_VLAN_TAG; 6840 vlan_tag = m0->m_pkthdr.ether_vtag; 6841 } 6842 6843 /* Map the mbuf into DMAable memory. */ 6844 prod = sc->tx_prod; 6845 chain_prod = TX_CHAIN_IDX(prod); 6846 map = sc->tx_mbuf_map[chain_prod]; 6847 6848 /* Map the mbuf into our DMA address space. */ 6849 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 6850 segs, &nsegs, BUS_DMA_NOWAIT); 6851 6852 /* Check if the DMA mapping was successful */ 6853 if (error == EFBIG) { 6854 sc->mbuf_frag_count++; 6855 6856 /* Try to defrag the mbuf. */ 6857 m0 = m_collapse(*m_head, M_DONTWAIT, BCE_MAX_SEGMENTS); 6858 if (m0 == NULL) { 6859 /* Defrag was unsuccessful */ 6860 m_freem(*m_head); 6861 *m_head = NULL; 6862 sc->mbuf_alloc_failed_count++; 6863 rc = ENOBUFS; 6864 goto bce_tx_encap_exit; 6865 } 6866 6867 /* Defrag was successful, try mapping again */ 6868 *m_head = m0; 6869 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, 6870 map, m0, segs, &nsegs, BUS_DMA_NOWAIT); 6871 6872 /* Still getting an error after a defrag. */ 6873 if (error == ENOMEM) { 6874 /* Insufficient DMA buffers available. */ 6875 sc->dma_map_addr_tx_failed_count++; 6876 rc = error; 6877 goto bce_tx_encap_exit; 6878 } else if (error != 0) { 6879 /* Release it and return an error. */ 6880 BCE_PRINTF("%s(%d): Unknown error mapping mbuf into " 6881 "TX chain!\n", __FILE__, __LINE__); 6882 m_freem(m0); 6883 *m_head = NULL; 6884 sc->dma_map_addr_tx_failed_count++; 6885 rc = ENOBUFS; 6886 goto bce_tx_encap_exit; 6887 } 6888 } else if (error == ENOMEM) { 6889 /* Insufficient DMA buffers available. */ 6890 sc->dma_map_addr_tx_failed_count++; 6891 rc = error; 6892 goto bce_tx_encap_exit; 6893 } else if (error != 0) { 6894 m_freem(m0); 6895 *m_head = NULL; 6896 sc->dma_map_addr_tx_failed_count++; 6897 rc = error; 6898 goto bce_tx_encap_exit; 6899 } 6900 6901 /* Make sure there's room in the chain */ 6902 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 6903 bus_dmamap_unload(sc->tx_mbuf_tag, map); 6904 rc = ENOBUFS; 6905 goto bce_tx_encap_exit; 6906 } 6907 6908 /* prod points to an empty tx_bd at this point. */ 6909 prod_bseq = sc->tx_prod_bseq; 6910 6911 #ifdef BCE_DEBUG 6912 debug_prod = chain_prod; 6913 #endif 6914 6915 DBPRINT(sc, BCE_INFO_SEND, 6916 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, " 6917 "prod_bseq = 0x%08X\n", 6918 __FUNCTION__, prod, chain_prod, prod_bseq); 6919 6920 /* 6921 * Cycle through each mbuf segment that makes up 6922 * the outgoing frame, gathering the mapping info 6923 * for that segment and creating a tx_bd for 6924 * the mbuf. 6925 */ 6926 for (i = 0; i < nsegs ; i++) { 6927 6928 chain_prod = TX_CHAIN_IDX(prod); 6929 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)] 6930 [TX_IDX(chain_prod)]; 6931 6932 txbd->tx_bd_haddr_lo = 6933 htole32(BCE_ADDR_LO(segs[i].ds_addr)); 6934 txbd->tx_bd_haddr_hi = 6935 htole32(BCE_ADDR_HI(segs[i].ds_addr)); 6936 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | 6937 htole16(segs[i].ds_len); 6938 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 6939 txbd->tx_bd_flags = htole16(flags); 6940 prod_bseq += segs[i].ds_len; 6941 if (i == 0) 6942 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 6943 prod = NEXT_TX_BD(prod); 6944 } 6945 6946 /* Set the END flag on the last TX buffer descriptor. */ 6947 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 6948 6949 DBRUNMSG(BCE_EXTREME_SEND, 6950 bce_dump_tx_chain(sc, debug_prod, nsegs)); 6951 6952 /* 6953 * Ensure that the mbuf pointer for this transmission 6954 * is placed at the array index of the last 6955 * descriptor in this chain. This is done 6956 * because a single map is used for all 6957 * segments of the mbuf and we don't want to 6958 * unload the map before all of the segments 6959 * have been freed. 6960 */ 6961 sc->tx_mbuf_ptr[chain_prod] = m0; 6962 sc->used_tx_bd += nsegs; 6963 6964 /* Update some debug statistic counters */ 6965 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 6966 sc->tx_hi_watermark = sc->used_tx_bd); 6967 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 6968 DBRUNIF(sc->debug_tx_mbuf_alloc++); 6969 6970 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1)); 6971 6972 /* prod points to the next free tx_bd at this point. */ 6973 sc->tx_prod = prod; 6974 sc->tx_prod_bseq = prod_bseq; 6975 6976 /* Tell the chip about the waiting TX frames. */ 6977 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + 6978 BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); 6979 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + 6980 BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); 6981 6982 bce_tx_encap_exit: 6983 DBEXIT(BCE_VERBOSE_SEND); 6984 return(rc); 6985 } 6986 6987 6988 /****************************************************************************/ 6989 /* Main transmit routine when called from another routine with a lock. */ 6990 /* */ 6991 /* Returns: */ 6992 /* Nothing. */ 6993 /****************************************************************************/ 6994 static void 6995 bce_start_locked(struct ifnet *ifp) 6996 { 6997 struct bce_softc *sc = ifp->if_softc; 6998 struct mbuf *m_head = NULL; 6999 int count = 0; 7000 u16 tx_prod, tx_chain_prod; 7001 7002 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7003 7004 BCE_LOCK_ASSERT(sc); 7005 7006 /* prod points to the next free tx_bd. */ 7007 tx_prod = sc->tx_prod; 7008 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 7009 7010 DBPRINT(sc, BCE_INFO_SEND, 7011 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 7012 "tx_prod_bseq = 0x%08X\n", 7013 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 7014 7015 /* If there's no link or the transmit queue is empty then just exit. */ 7016 if (sc->bce_link_up == FALSE) { 7017 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n", 7018 __FUNCTION__); 7019 goto bce_start_locked_exit; 7020 } 7021 7022 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 7023 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n", 7024 __FUNCTION__); 7025 goto bce_start_locked_exit; 7026 } 7027 7028 /* 7029 * Keep adding entries while there is space in the ring. 7030 */ 7031 while (sc->used_tx_bd < sc->max_tx_bd) { 7032 7033 /* Check for any frames to send. */ 7034 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 7035 7036 /* Stop when the transmit queue is empty. */ 7037 if (m_head == NULL) 7038 break; 7039 7040 /* 7041 * Pack the data into the transmit ring. If we 7042 * don't have room, place the mbuf back at the 7043 * head of the queue and set the OACTIVE flag 7044 * to wait for the NIC to drain the chain. 7045 */ 7046 if (bce_tx_encap(sc, &m_head)) { 7047 if (m_head != NULL) 7048 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 7049 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 7050 DBPRINT(sc, BCE_INFO_SEND, 7051 "TX chain is closed for business! Total " 7052 "tx_bd used = %d\n", sc->used_tx_bd); 7053 break; 7054 } 7055 7056 count++; 7057 7058 /* Send a copy of the frame to any BPF listeners. */ 7059 ETHER_BPF_MTAP(ifp, m_head); 7060 } 7061 7062 /* Exit if no packets were dequeued. */ 7063 if (count == 0) { 7064 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were " 7065 "dequeued\n", __FUNCTION__); 7066 goto bce_start_locked_exit; 7067 } 7068 7069 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into " 7070 "send queue.\n", __FUNCTION__, count); 7071 7072 /* Set the tx timeout. */ 7073 sc->watchdog_timer = BCE_TX_TIMEOUT; 7074 7075 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID)); 7076 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc)); 7077 7078 bce_start_locked_exit: 7079 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7080 return; 7081 } 7082 7083 7084 /****************************************************************************/ 7085 /* Main transmit routine when called from another routine without a lock. */ 7086 /* */ 7087 /* Returns: */ 7088 /* Nothing. */ 7089 /****************************************************************************/ 7090 static void 7091 bce_start(struct ifnet *ifp) 7092 { 7093 struct bce_softc *sc = ifp->if_softc; 7094 7095 DBENTER(BCE_VERBOSE_SEND); 7096 7097 BCE_LOCK(sc); 7098 bce_start_locked(ifp); 7099 BCE_UNLOCK(sc); 7100 7101 DBEXIT(BCE_VERBOSE_SEND); 7102 } 7103 7104 7105 /****************************************************************************/ 7106 /* Handles any IOCTL calls from the operating system. */ 7107 /* */ 7108 /* Returns: */ 7109 /* 0 for success, positive value for failure. */ 7110 /****************************************************************************/ 7111 static int 7112 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 7113 { 7114 struct bce_softc *sc = ifp->if_softc; 7115 struct ifreq *ifr = (struct ifreq *) data; 7116 struct mii_data *mii; 7117 int mask, error = 0, reinit; 7118 7119 DBENTER(BCE_VERBOSE_MISC); 7120 7121 switch(command) { 7122 7123 /* Set the interface MTU. */ 7124 case SIOCSIFMTU: 7125 /* Check that the MTU setting is supported. */ 7126 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 7127 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 7128 error = EINVAL; 7129 break; 7130 } 7131 7132 DBPRINT(sc, BCE_INFO_MISC, 7133 "SIOCSIFMTU: Changing MTU from %d to %d\n", 7134 (int) ifp->if_mtu, (int) ifr->ifr_mtu); 7135 7136 BCE_LOCK(sc); 7137 ifp->if_mtu = ifr->ifr_mtu; 7138 reinit = 0; 7139 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7140 /* 7141 * Because allocation size is used in RX 7142 * buffer allocation, stop controller if 7143 * it is already running. 7144 */ 7145 bce_stop(sc); 7146 reinit = 1; 7147 } 7148 #ifdef BCE_JUMBO_HDRSPLIT 7149 /* No buffer allocation size changes are necessary. */ 7150 #else 7151 /* Recalculate our buffer allocation sizes. */ 7152 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 7153 ETHER_CRC_LEN) > MCLBYTES) { 7154 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES; 7155 sc->rx_bd_mbuf_align_pad = 7156 roundup2(MJUM9BYTES, 16) - MJUM9BYTES; 7157 sc->rx_bd_mbuf_data_len = 7158 sc->rx_bd_mbuf_alloc_size - 7159 sc->rx_bd_mbuf_align_pad; 7160 } else { 7161 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 7162 sc->rx_bd_mbuf_align_pad = 7163 roundup2(MCLBYTES, 16) - MCLBYTES; 7164 sc->rx_bd_mbuf_data_len = 7165 sc->rx_bd_mbuf_alloc_size - 7166 sc->rx_bd_mbuf_align_pad; 7167 } 7168 #endif 7169 7170 if (reinit != 0) 7171 bce_init_locked(sc); 7172 BCE_UNLOCK(sc); 7173 break; 7174 7175 /* Set interface flags. */ 7176 case SIOCSIFFLAGS: 7177 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 7178 7179 BCE_LOCK(sc); 7180 7181 /* Check if the interface is up. */ 7182 if (ifp->if_flags & IFF_UP) { 7183 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7184 /* Change promiscuous/multicast flags as necessary. */ 7185 bce_set_rx_mode(sc); 7186 } else { 7187 /* Start the HW */ 7188 bce_init_locked(sc); 7189 } 7190 } else { 7191 /* The interface is down, check if driver is running. */ 7192 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7193 bce_stop(sc); 7194 7195 /* If MFW is running, restart the controller a bit. */ 7196 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 7197 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 7198 bce_chipinit(sc); 7199 bce_mgmt_init_locked(sc); 7200 } 7201 } 7202 } 7203 7204 BCE_UNLOCK(sc); 7205 break; 7206 7207 /* Add/Delete multicast address */ 7208 case SIOCADDMULTI: 7209 case SIOCDELMULTI: 7210 DBPRINT(sc, BCE_VERBOSE_MISC, 7211 "Received SIOCADDMULTI/SIOCDELMULTI\n"); 7212 7213 BCE_LOCK(sc); 7214 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7215 bce_set_rx_mode(sc); 7216 BCE_UNLOCK(sc); 7217 7218 break; 7219 7220 /* Set/Get Interface media */ 7221 case SIOCSIFMEDIA: 7222 case SIOCGIFMEDIA: 7223 DBPRINT(sc, BCE_VERBOSE_MISC, 7224 "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 7225 7226 mii = device_get_softc(sc->bce_miibus); 7227 error = ifmedia_ioctl(ifp, ifr, 7228 &mii->mii_media, command); 7229 break; 7230 7231 /* Set interface capability */ 7232 case SIOCSIFCAP: 7233 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 7234 DBPRINT(sc, BCE_INFO_MISC, 7235 "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 7236 7237 /* Toggle the TX checksum capabilities enable flag. */ 7238 if (mask & IFCAP_TXCSUM && 7239 ifp->if_capabilities & IFCAP_TXCSUM) { 7240 ifp->if_capenable ^= IFCAP_TXCSUM; 7241 if (IFCAP_TXCSUM & ifp->if_capenable) 7242 ifp->if_hwassist |= BCE_IF_HWASSIST; 7243 else 7244 ifp->if_hwassist &= ~BCE_IF_HWASSIST; 7245 } 7246 7247 /* Toggle the RX checksum capabilities enable flag. */ 7248 if (mask & IFCAP_RXCSUM && 7249 ifp->if_capabilities & IFCAP_RXCSUM) 7250 ifp->if_capenable ^= IFCAP_RXCSUM; 7251 7252 /* Toggle the TSO capabilities enable flag. */ 7253 if (bce_tso_enable && (mask & IFCAP_TSO4) && 7254 ifp->if_capabilities & IFCAP_TSO4) { 7255 ifp->if_capenable ^= IFCAP_TSO4; 7256 if (IFCAP_TSO4 & ifp->if_capenable) 7257 ifp->if_hwassist |= CSUM_TSO; 7258 else 7259 ifp->if_hwassist &= ~CSUM_TSO; 7260 } 7261 7262 if (mask & IFCAP_VLAN_HWCSUM && 7263 ifp->if_capabilities & IFCAP_VLAN_HWCSUM) 7264 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 7265 7266 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 7267 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 7268 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 7269 /* 7270 * Don't actually disable VLAN tag stripping as 7271 * management firmware (ASF/IPMI/UMP) requires the 7272 * feature. If VLAN tag stripping is disabled driver 7273 * will manually reconstruct the VLAN frame by 7274 * appending stripped VLAN tag. 7275 */ 7276 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 7277 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { 7278 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 7279 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 7280 == 0) 7281 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 7282 } 7283 VLAN_CAPABILITIES(ifp); 7284 break; 7285 default: 7286 /* We don't know how to handle the IOCTL, pass it on. */ 7287 error = ether_ioctl(ifp, command, data); 7288 break; 7289 } 7290 7291 DBEXIT(BCE_VERBOSE_MISC); 7292 return(error); 7293 } 7294 7295 7296 /****************************************************************************/ 7297 /* Transmit timeout handler. */ 7298 /* */ 7299 /* Returns: */ 7300 /* Nothing. */ 7301 /****************************************************************************/ 7302 static void 7303 bce_watchdog(struct bce_softc *sc) 7304 { 7305 DBENTER(BCE_EXTREME_SEND); 7306 7307 BCE_LOCK_ASSERT(sc); 7308 7309 /* If the watchdog timer hasn't expired then just exit. */ 7310 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 7311 goto bce_watchdog_exit; 7312 7313 /* If pause frames are active then don't reset the hardware. */ 7314 /* ToDo: Should we reset the timer here? */ 7315 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED) 7316 goto bce_watchdog_exit; 7317 7318 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 7319 __FILE__, __LINE__); 7320 7321 DBRUNMSG(BCE_INFO, 7322 bce_dump_driver_state(sc); 7323 bce_dump_status_block(sc); 7324 bce_dump_stats_block(sc); 7325 bce_dump_ftqs(sc); 7326 bce_dump_txp_state(sc, 0); 7327 bce_dump_rxp_state(sc, 0); 7328 bce_dump_tpat_state(sc, 0); 7329 bce_dump_cp_state(sc, 0); 7330 bce_dump_com_state(sc, 0)); 7331 7332 DBRUN(bce_breakpoint(sc)); 7333 7334 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7335 7336 bce_init_locked(sc); 7337 sc->bce_ifp->if_oerrors++; 7338 7339 bce_watchdog_exit: 7340 DBEXIT(BCE_EXTREME_SEND); 7341 } 7342 7343 7344 /* 7345 * Interrupt handler. 7346 */ 7347 /****************************************************************************/ 7348 /* Main interrupt entry point. Verifies that the controller generated the */ 7349 /* interrupt and then calls a separate routine for handle the various */ 7350 /* interrupt causes (PHY, TX, RX). */ 7351 /* */ 7352 /* Returns: */ 7353 /* 0 for success, positive value for failure. */ 7354 /****************************************************************************/ 7355 static void 7356 bce_intr(void *xsc) 7357 { 7358 struct bce_softc *sc; 7359 struct ifnet *ifp; 7360 u32 status_attn_bits; 7361 u16 hw_rx_cons, hw_tx_cons; 7362 7363 sc = xsc; 7364 ifp = sc->bce_ifp; 7365 7366 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7367 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 7368 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc)); 7369 7370 BCE_LOCK(sc); 7371 7372 DBRUN(sc->interrupts_generated++); 7373 7374 /* Synchnorize before we read from interface's status block */ 7375 bus_dmamap_sync(sc->status_tag, sc->status_map, 7376 BUS_DMASYNC_POSTREAD); 7377 7378 /* 7379 * If the hardware status block index 7380 * matches the last value read by the 7381 * driver and we haven't asserted our 7382 * interrupt then there's nothing to do. 7383 */ 7384 if ((sc->status_block->status_idx == sc->last_status_idx) && 7385 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & 7386 BCE_PCICFG_MISC_STATUS_INTA_VALUE)) { 7387 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n", 7388 __FUNCTION__); 7389 goto bce_intr_exit; 7390 } 7391 7392 /* Ack the interrupt and stop others from occuring. */ 7393 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7394 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 7395 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7396 7397 /* Check if the hardware has finished any work. */ 7398 hw_rx_cons = bce_get_hw_rx_cons(sc); 7399 hw_tx_cons = bce_get_hw_tx_cons(sc); 7400 7401 /* Keep processing data as long as there is work to do. */ 7402 for (;;) { 7403 7404 status_attn_bits = sc->status_block->status_attn_bits; 7405 7406 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control), 7407 BCE_PRINTF("Simulating unexpected status attention " 7408 "bit set."); 7409 sc->unexpected_attention_sim_count++; 7410 status_attn_bits = status_attn_bits | 7411 STATUS_ATTN_BITS_PARITY_ERROR); 7412 7413 /* Was it a link change interrupt? */ 7414 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 7415 (sc->status_block->status_attn_bits_ack & 7416 STATUS_ATTN_BITS_LINK_STATE)) { 7417 bce_phy_intr(sc); 7418 7419 /* Clear transient updates during link state change. */ 7420 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | 7421 BCE_HC_COMMAND_COAL_NOW_WO_INT); 7422 REG_RD(sc, BCE_HC_COMMAND); 7423 } 7424 7425 /* If any other attention is asserted, the chip is toast. */ 7426 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 7427 (sc->status_block->status_attn_bits_ack & 7428 ~STATUS_ATTN_BITS_LINK_STATE))) { 7429 7430 sc->unexpected_attention_count++; 7431 7432 BCE_PRINTF("%s(%d): Fatal attention detected: " 7433 "0x%08X\n", __FILE__, __LINE__, 7434 sc->status_block->status_attn_bits); 7435 7436 DBRUNMSG(BCE_FATAL, 7437 if (unexpected_attention_sim_control == 0) 7438 bce_breakpoint(sc)); 7439 7440 bce_init_locked(sc); 7441 goto bce_intr_exit; 7442 } 7443 7444 /* Check for any completed RX frames. */ 7445 if (hw_rx_cons != sc->hw_rx_cons) 7446 bce_rx_intr(sc); 7447 7448 /* Check for any completed TX frames. */ 7449 if (hw_tx_cons != sc->hw_tx_cons) 7450 bce_tx_intr(sc); 7451 7452 /* Save status block index value for the next interrupt. */ 7453 sc->last_status_idx = sc->status_block->status_idx; 7454 7455 /* 7456 * Prevent speculative reads from getting 7457 * ahead of the status block. 7458 */ 7459 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 7460 BUS_SPACE_BARRIER_READ); 7461 7462 /* 7463 * If there's no work left then exit the 7464 * interrupt service routine. 7465 */ 7466 hw_rx_cons = bce_get_hw_rx_cons(sc); 7467 hw_tx_cons = bce_get_hw_tx_cons(sc); 7468 7469 if ((hw_rx_cons == sc->hw_rx_cons) && 7470 (hw_tx_cons == sc->hw_tx_cons)) 7471 break; 7472 7473 } 7474 7475 bus_dmamap_sync(sc->status_tag, sc->status_map, 7476 BUS_DMASYNC_PREREAD); 7477 7478 /* Re-enable interrupts. */ 7479 bce_enable_intr(sc, 0); 7480 7481 /* Handle any frames that arrived while handling the interrupt. */ 7482 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 7483 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 7484 bce_start_locked(ifp); 7485 7486 bce_intr_exit: 7487 BCE_UNLOCK(sc); 7488 7489 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7490 } 7491 7492 7493 /****************************************************************************/ 7494 /* Programs the various packet receive modes (broadcast and multicast). */ 7495 /* */ 7496 /* Returns: */ 7497 /* Nothing. */ 7498 /****************************************************************************/ 7499 static void 7500 bce_set_rx_mode(struct bce_softc *sc) 7501 { 7502 struct ifnet *ifp; 7503 struct ifmultiaddr *ifma; 7504 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 7505 u32 rx_mode, sort_mode; 7506 int h, i; 7507 7508 DBENTER(BCE_VERBOSE_MISC); 7509 7510 BCE_LOCK_ASSERT(sc); 7511 7512 ifp = sc->bce_ifp; 7513 7514 /* Initialize receive mode default settings. */ 7515 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 7516 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 7517 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 7518 7519 /* 7520 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 7521 * be enbled. 7522 */ 7523 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 7524 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 7525 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 7526 7527 /* 7528 * Check for promiscuous, all multicast, or selected 7529 * multicast address filtering. 7530 */ 7531 if (ifp->if_flags & IFF_PROMISC) { 7532 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 7533 7534 /* Enable promiscuous mode. */ 7535 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 7536 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 7537 } else if (ifp->if_flags & IFF_ALLMULTI) { 7538 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 7539 7540 /* Enable all multicast addresses. */ 7541 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 7542 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff); 7543 } 7544 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 7545 } else { 7546 /* Accept one or more multicast(s). */ 7547 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 7548 7549 IF_ADDR_LOCK(ifp); 7550 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 7551 if (ifma->ifma_addr->sa_family != AF_LINK) 7552 continue; 7553 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 7554 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 7555 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 7556 } 7557 IF_ADDR_UNLOCK(ifp); 7558 7559 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 7560 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 7561 7562 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 7563 } 7564 7565 /* Only make changes if the recive mode has actually changed. */ 7566 if (rx_mode != sc->rx_mode) { 7567 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: " 7568 "0x%08X\n", rx_mode); 7569 7570 sc->rx_mode = rx_mode; 7571 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 7572 } 7573 7574 /* Disable and clear the exisitng sort before enabling a new sort. */ 7575 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 7576 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 7577 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 7578 7579 DBEXIT(BCE_VERBOSE_MISC); 7580 } 7581 7582 7583 /****************************************************************************/ 7584 /* Called periodically to updates statistics from the controllers */ 7585 /* statistics block. */ 7586 /* */ 7587 /* Returns: */ 7588 /* Nothing. */ 7589 /****************************************************************************/ 7590 static void 7591 bce_stats_update(struct bce_softc *sc) 7592 { 7593 struct ifnet *ifp; 7594 struct statistics_block *stats; 7595 7596 DBENTER(BCE_EXTREME_MISC); 7597 7598 ifp = sc->bce_ifp; 7599 7600 stats = (struct statistics_block *) sc->stats_block; 7601 7602 /* 7603 * Certain controllers don't report 7604 * carrier sense errors correctly. 7605 * See errata E11_5708CA0_1165. 7606 */ 7607 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 7608 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 7609 ifp->if_oerrors += 7610 (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 7611 7612 /* 7613 * Update the sysctl statistics from the 7614 * hardware statistics. 7615 */ 7616 sc->stat_IfHCInOctets = 7617 ((u64) stats->stat_IfHCInOctets_hi << 32) + 7618 (u64) stats->stat_IfHCInOctets_lo; 7619 7620 sc->stat_IfHCInBadOctets = 7621 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 7622 (u64) stats->stat_IfHCInBadOctets_lo; 7623 7624 sc->stat_IfHCOutOctets = 7625 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 7626 (u64) stats->stat_IfHCOutOctets_lo; 7627 7628 sc->stat_IfHCOutBadOctets = 7629 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 7630 (u64) stats->stat_IfHCOutBadOctets_lo; 7631 7632 sc->stat_IfHCInUcastPkts = 7633 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 7634 (u64) stats->stat_IfHCInUcastPkts_lo; 7635 7636 sc->stat_IfHCInMulticastPkts = 7637 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 7638 (u64) stats->stat_IfHCInMulticastPkts_lo; 7639 7640 sc->stat_IfHCInBroadcastPkts = 7641 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 7642 (u64) stats->stat_IfHCInBroadcastPkts_lo; 7643 7644 sc->stat_IfHCOutUcastPkts = 7645 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 7646 (u64) stats->stat_IfHCOutUcastPkts_lo; 7647 7648 sc->stat_IfHCOutMulticastPkts = 7649 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 7650 (u64) stats->stat_IfHCOutMulticastPkts_lo; 7651 7652 sc->stat_IfHCOutBroadcastPkts = 7653 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 7654 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 7655 7656 /* ToDo: Preserve counters beyond 32 bits? */ 7657 /* ToDo: Read the statistics from auto-clear regs? */ 7658 7659 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 7660 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 7661 7662 sc->stat_Dot3StatsCarrierSenseErrors = 7663 stats->stat_Dot3StatsCarrierSenseErrors; 7664 7665 sc->stat_Dot3StatsFCSErrors = 7666 stats->stat_Dot3StatsFCSErrors; 7667 7668 sc->stat_Dot3StatsAlignmentErrors = 7669 stats->stat_Dot3StatsAlignmentErrors; 7670 7671 sc->stat_Dot3StatsSingleCollisionFrames = 7672 stats->stat_Dot3StatsSingleCollisionFrames; 7673 7674 sc->stat_Dot3StatsMultipleCollisionFrames = 7675 stats->stat_Dot3StatsMultipleCollisionFrames; 7676 7677 sc->stat_Dot3StatsDeferredTransmissions = 7678 stats->stat_Dot3StatsDeferredTransmissions; 7679 7680 sc->stat_Dot3StatsExcessiveCollisions = 7681 stats->stat_Dot3StatsExcessiveCollisions; 7682 7683 sc->stat_Dot3StatsLateCollisions = 7684 stats->stat_Dot3StatsLateCollisions; 7685 7686 sc->stat_EtherStatsCollisions = 7687 stats->stat_EtherStatsCollisions; 7688 7689 sc->stat_EtherStatsFragments = 7690 stats->stat_EtherStatsFragments; 7691 7692 sc->stat_EtherStatsJabbers = 7693 stats->stat_EtherStatsJabbers; 7694 7695 sc->stat_EtherStatsUndersizePkts = 7696 stats->stat_EtherStatsUndersizePkts; 7697 7698 sc->stat_EtherStatsOversizePkts = 7699 stats->stat_EtherStatsOversizePkts; 7700 7701 sc->stat_EtherStatsPktsRx64Octets = 7702 stats->stat_EtherStatsPktsRx64Octets; 7703 7704 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 7705 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 7706 7707 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 7708 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 7709 7710 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 7711 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 7712 7713 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 7714 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 7715 7716 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 7717 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 7718 7719 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 7720 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 7721 7722 sc->stat_EtherStatsPktsTx64Octets = 7723 stats->stat_EtherStatsPktsTx64Octets; 7724 7725 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 7726 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 7727 7728 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 7729 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 7730 7731 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 7732 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 7733 7734 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 7735 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 7736 7737 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 7738 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 7739 7740 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 7741 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 7742 7743 sc->stat_XonPauseFramesReceived = 7744 stats->stat_XonPauseFramesReceived; 7745 7746 sc->stat_XoffPauseFramesReceived = 7747 stats->stat_XoffPauseFramesReceived; 7748 7749 sc->stat_OutXonSent = 7750 stats->stat_OutXonSent; 7751 7752 sc->stat_OutXoffSent = 7753 stats->stat_OutXoffSent; 7754 7755 sc->stat_FlowControlDone = 7756 stats->stat_FlowControlDone; 7757 7758 sc->stat_MacControlFramesReceived = 7759 stats->stat_MacControlFramesReceived; 7760 7761 sc->stat_XoffStateEntered = 7762 stats->stat_XoffStateEntered; 7763 7764 sc->stat_IfInFramesL2FilterDiscards = 7765 stats->stat_IfInFramesL2FilterDiscards; 7766 7767 sc->stat_IfInRuleCheckerDiscards = 7768 stats->stat_IfInRuleCheckerDiscards; 7769 7770 sc->stat_IfInFTQDiscards = 7771 stats->stat_IfInFTQDiscards; 7772 7773 sc->stat_IfInMBUFDiscards = 7774 stats->stat_IfInMBUFDiscards; 7775 7776 sc->stat_IfInRuleCheckerP4Hit = 7777 stats->stat_IfInRuleCheckerP4Hit; 7778 7779 sc->stat_CatchupInRuleCheckerDiscards = 7780 stats->stat_CatchupInRuleCheckerDiscards; 7781 7782 sc->stat_CatchupInFTQDiscards = 7783 stats->stat_CatchupInFTQDiscards; 7784 7785 sc->stat_CatchupInMBUFDiscards = 7786 stats->stat_CatchupInMBUFDiscards; 7787 7788 sc->stat_CatchupInRuleCheckerP4Hit = 7789 stats->stat_CatchupInRuleCheckerP4Hit; 7790 7791 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 7792 7793 /* 7794 * Update the interface statistics from the 7795 * hardware statistics. 7796 */ 7797 ifp->if_collisions = 7798 (u_long) sc->stat_EtherStatsCollisions; 7799 7800 /* ToDo: This method loses soft errors. */ 7801 ifp->if_ierrors = 7802 (u_long) sc->stat_EtherStatsUndersizePkts + 7803 (u_long) sc->stat_EtherStatsOversizePkts + 7804 (u_long) sc->stat_IfInMBUFDiscards + 7805 (u_long) sc->stat_Dot3StatsAlignmentErrors + 7806 (u_long) sc->stat_Dot3StatsFCSErrors + 7807 (u_long) sc->stat_IfInRuleCheckerDiscards + 7808 (u_long) sc->stat_IfInFTQDiscards + 7809 (u_long) sc->com_no_buffers; 7810 7811 /* ToDo: This method loses soft errors. */ 7812 ifp->if_oerrors = 7813 (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 7814 (u_long) sc->stat_Dot3StatsExcessiveCollisions + 7815 (u_long) sc->stat_Dot3StatsLateCollisions; 7816 7817 /* ToDo: Add additional statistics? */ 7818 7819 DBEXIT(BCE_EXTREME_MISC); 7820 } 7821 7822 7823 /****************************************************************************/ 7824 /* Periodic function to notify the bootcode that the driver is still */ 7825 /* present. */ 7826 /* */ 7827 /* Returns: */ 7828 /* Nothing. */ 7829 /****************************************************************************/ 7830 static void 7831 bce_pulse(void *xsc) 7832 { 7833 struct bce_softc *sc = xsc; 7834 u32 msg; 7835 7836 DBENTER(BCE_EXTREME_MISC); 7837 7838 BCE_LOCK_ASSERT(sc); 7839 7840 /* Tell the firmware that the driver is still running. */ 7841 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 7842 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg); 7843 7844 /* Update the bootcode condition. */ 7845 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 7846 7847 /* Report whether the bootcode still knows the driver is running. */ 7848 if (bootverbose) { 7849 if (sc->bce_drv_cardiac_arrest == FALSE) { 7850 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) { 7851 sc->bce_drv_cardiac_arrest = TRUE; 7852 BCE_PRINTF("%s(): Warning: bootcode " 7853 "thinks driver is absent! " 7854 "(bc_state = 0x%08X)\n", 7855 __FUNCTION__, sc->bc_state); 7856 } 7857 } else { 7858 /* 7859 * Not supported by all bootcode versions. 7860 * (v5.0.11+ and v5.2.1+) Older bootcode 7861 * will require the driver to reset the 7862 * controller to clear this condition. 7863 */ 7864 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) { 7865 sc->bce_drv_cardiac_arrest = FALSE; 7866 BCE_PRINTF("%s(): Bootcode found the " 7867 "driver pulse! (bc_state = 0x%08X)\n", 7868 __FUNCTION__, sc->bc_state); 7869 } 7870 } 7871 } 7872 7873 7874 /* Schedule the next pulse. */ 7875 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 7876 7877 DBEXIT(BCE_EXTREME_MISC); 7878 } 7879 7880 7881 /****************************************************************************/ 7882 /* Periodic function to perform maintenance tasks. */ 7883 /* */ 7884 /* Returns: */ 7885 /* Nothing. */ 7886 /****************************************************************************/ 7887 static void 7888 bce_tick(void *xsc) 7889 { 7890 struct bce_softc *sc = xsc; 7891 struct mii_data *mii; 7892 struct ifnet *ifp; 7893 7894 ifp = sc->bce_ifp; 7895 7896 DBENTER(BCE_EXTREME_MISC); 7897 7898 BCE_LOCK_ASSERT(sc); 7899 7900 /* Schedule the next tick. */ 7901 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 7902 7903 /* Update the statistics from the hardware statistics block. */ 7904 bce_stats_update(sc); 7905 7906 /* Top off the receive and page chains. */ 7907 #ifdef BCE_JUMBO_HDRSPLIT 7908 bce_fill_pg_chain(sc); 7909 #endif 7910 bce_fill_rx_chain(sc); 7911 7912 /* Check that chip hasn't hung. */ 7913 bce_watchdog(sc); 7914 7915 /* If link is up already up then we're done. */ 7916 if (sc->bce_link_up == TRUE) 7917 goto bce_tick_exit; 7918 7919 /* Link is down. Check what the PHY's doing. */ 7920 mii = device_get_softc(sc->bce_miibus); 7921 mii_tick(mii); 7922 7923 /* Check if the link has come up. */ 7924 if ((mii->mii_media_status & IFM_ACTIVE) && 7925 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) { 7926 DBPRINT(sc, BCE_VERBOSE_MISC, 7927 "%s(): Link up!\n", __FUNCTION__); 7928 sc->bce_link_up = TRUE; 7929 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 7930 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX || 7931 IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) && 7932 bootverbose) 7933 BCE_PRINTF("Gigabit link up!\n"); 7934 7935 /* Now that link is up, handle any outstanding TX traffic. */ 7936 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 7937 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found " 7938 "pending TX traffic.\n", __FUNCTION__); 7939 bce_start_locked(ifp); 7940 } 7941 } 7942 7943 bce_tick_exit: 7944 DBEXIT(BCE_EXTREME_MISC); 7945 return; 7946 } 7947 7948 7949 #ifdef BCE_DEBUG 7950 /****************************************************************************/ 7951 /* Allows the driver state to be dumped through the sysctl interface. */ 7952 /* */ 7953 /* Returns: */ 7954 /* 0 for success, positive value for failure. */ 7955 /****************************************************************************/ 7956 static int 7957 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 7958 { 7959 int error; 7960 int result; 7961 struct bce_softc *sc; 7962 7963 result = -1; 7964 error = sysctl_handle_int(oidp, &result, 0, req); 7965 7966 if (error || !req->newptr) 7967 return (error); 7968 7969 if (result == 1) { 7970 sc = (struct bce_softc *)arg1; 7971 bce_dump_driver_state(sc); 7972 } 7973 7974 return error; 7975 } 7976 7977 7978 /****************************************************************************/ 7979 /* Allows the hardware state to be dumped through the sysctl interface. */ 7980 /* */ 7981 /* Returns: */ 7982 /* 0 for success, positive value for failure. */ 7983 /****************************************************************************/ 7984 static int 7985 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 7986 { 7987 int error; 7988 int result; 7989 struct bce_softc *sc; 7990 7991 result = -1; 7992 error = sysctl_handle_int(oidp, &result, 0, req); 7993 7994 if (error || !req->newptr) 7995 return (error); 7996 7997 if (result == 1) { 7998 sc = (struct bce_softc *)arg1; 7999 bce_dump_hw_state(sc); 8000 } 8001 8002 return error; 8003 } 8004 8005 8006 /****************************************************************************/ 8007 /* Allows the status block to be dumped through the sysctl interface. */ 8008 /* */ 8009 /* Returns: */ 8010 /* 0 for success, positive value for failure. */ 8011 /****************************************************************************/ 8012 static int 8013 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS) 8014 { 8015 int error; 8016 int result; 8017 struct bce_softc *sc; 8018 8019 result = -1; 8020 error = sysctl_handle_int(oidp, &result, 0, req); 8021 8022 if (error || !req->newptr) 8023 return (error); 8024 8025 if (result == 1) { 8026 sc = (struct bce_softc *)arg1; 8027 bce_dump_status_block(sc); 8028 } 8029 8030 return error; 8031 } 8032 8033 8034 /****************************************************************************/ 8035 /* Allows the stats block to be dumped through the sysctl interface. */ 8036 /* */ 8037 /* Returns: */ 8038 /* 0 for success, positive value for failure. */ 8039 /****************************************************************************/ 8040 static int 8041 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS) 8042 { 8043 int error; 8044 int result; 8045 struct bce_softc *sc; 8046 8047 result = -1; 8048 error = sysctl_handle_int(oidp, &result, 0, req); 8049 8050 if (error || !req->newptr) 8051 return (error); 8052 8053 if (result == 1) { 8054 sc = (struct bce_softc *)arg1; 8055 bce_dump_stats_block(sc); 8056 } 8057 8058 return error; 8059 } 8060 8061 8062 /****************************************************************************/ 8063 /* Allows the stat counters to be cleared without unloading/reloading the */ 8064 /* driver. */ 8065 /* */ 8066 /* Returns: */ 8067 /* 0 for success, positive value for failure. */ 8068 /****************************************************************************/ 8069 static int 8070 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS) 8071 { 8072 int error; 8073 int result; 8074 struct bce_softc *sc; 8075 8076 result = -1; 8077 error = sysctl_handle_int(oidp, &result, 0, req); 8078 8079 if (error || !req->newptr) 8080 return (error); 8081 8082 if (result == 1) { 8083 sc = (struct bce_softc *)arg1; 8084 8085 /* Clear the internal H/W statistics counters. */ 8086 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 8087 8088 /* Reset the driver maintained statistics. */ 8089 sc->interrupts_rx = 8090 sc->interrupts_tx = 0; 8091 sc->tso_frames_requested = 8092 sc->tso_frames_completed = 8093 sc->tso_frames_failed = 0; 8094 sc->rx_empty_count = 8095 sc->tx_full_count = 0; 8096 sc->rx_low_watermark = USABLE_RX_BD; 8097 sc->tx_hi_watermark = 0; 8098 sc->l2fhdr_error_count = 8099 sc->l2fhdr_error_sim_count = 0; 8100 sc->mbuf_alloc_failed_count = 8101 sc->mbuf_alloc_failed_sim_count = 0; 8102 sc->dma_map_addr_rx_failed_count = 8103 sc->dma_map_addr_tx_failed_count = 0; 8104 sc->mbuf_frag_count = 0; 8105 sc->csum_offload_tcp_udp = 8106 sc->csum_offload_ip = 0; 8107 sc->vlan_tagged_frames_rcvd = 8108 sc->vlan_tagged_frames_stripped = 0; 8109 8110 /* Clear firmware maintained statistics. */ 8111 REG_WR_IND(sc, 0x120084, 0); 8112 } 8113 8114 return error; 8115 } 8116 8117 8118 /****************************************************************************/ 8119 /* Allows the bootcode state to be dumped through the sysctl interface. */ 8120 /* */ 8121 /* Returns: */ 8122 /* 0 for success, positive value for failure. */ 8123 /****************************************************************************/ 8124 static int 8125 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 8126 { 8127 int error; 8128 int result; 8129 struct bce_softc *sc; 8130 8131 result = -1; 8132 error = sysctl_handle_int(oidp, &result, 0, req); 8133 8134 if (error || !req->newptr) 8135 return (error); 8136 8137 if (result == 1) { 8138 sc = (struct bce_softc *)arg1; 8139 bce_dump_bc_state(sc); 8140 } 8141 8142 return error; 8143 } 8144 8145 8146 /****************************************************************************/ 8147 /* Provides a sysctl interface to allow dumping the RX BD chain. */ 8148 /* */ 8149 /* Returns: */ 8150 /* 0 for success, positive value for failure. */ 8151 /****************************************************************************/ 8152 static int 8153 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS) 8154 { 8155 int error; 8156 int result; 8157 struct bce_softc *sc; 8158 8159 result = -1; 8160 error = sysctl_handle_int(oidp, &result, 0, req); 8161 8162 if (error || !req->newptr) 8163 return (error); 8164 8165 if (result == 1) { 8166 sc = (struct bce_softc *)arg1; 8167 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD); 8168 } 8169 8170 return error; 8171 } 8172 8173 8174 /****************************************************************************/ 8175 /* Provides a sysctl interface to allow dumping the RX MBUF chain. */ 8176 /* */ 8177 /* Returns: */ 8178 /* 0 for success, positive value for failure. */ 8179 /****************************************************************************/ 8180 static int 8181 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS) 8182 { 8183 int error; 8184 int result; 8185 struct bce_softc *sc; 8186 8187 result = -1; 8188 error = sysctl_handle_int(oidp, &result, 0, req); 8189 8190 if (error || !req->newptr) 8191 return (error); 8192 8193 if (result == 1) { 8194 sc = (struct bce_softc *)arg1; 8195 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD); 8196 } 8197 8198 return error; 8199 } 8200 8201 8202 /****************************************************************************/ 8203 /* Provides a sysctl interface to allow dumping the TX chain. */ 8204 /* */ 8205 /* Returns: */ 8206 /* 0 for success, positive value for failure. */ 8207 /****************************************************************************/ 8208 static int 8209 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 8210 { 8211 int error; 8212 int result; 8213 struct bce_softc *sc; 8214 8215 result = -1; 8216 error = sysctl_handle_int(oidp, &result, 0, req); 8217 8218 if (error || !req->newptr) 8219 return (error); 8220 8221 if (result == 1) { 8222 sc = (struct bce_softc *)arg1; 8223 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD); 8224 } 8225 8226 return error; 8227 } 8228 8229 8230 #ifdef BCE_JUMBO_HDRSPLIT 8231 /****************************************************************************/ 8232 /* Provides a sysctl interface to allow dumping the page chain. */ 8233 /* */ 8234 /* Returns: */ 8235 /* 0 for success, positive value for failure. */ 8236 /****************************************************************************/ 8237 static int 8238 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS) 8239 { 8240 int error; 8241 int result; 8242 struct bce_softc *sc; 8243 8244 result = -1; 8245 error = sysctl_handle_int(oidp, &result, 0, req); 8246 8247 if (error || !req->newptr) 8248 return (error); 8249 8250 if (result == 1) { 8251 sc = (struct bce_softc *)arg1; 8252 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD); 8253 } 8254 8255 return error; 8256 } 8257 #endif 8258 8259 /****************************************************************************/ 8260 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */ 8261 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8262 /* */ 8263 /* Returns: */ 8264 /* 0 for success, positive value for failure. */ 8265 /****************************************************************************/ 8266 static int 8267 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS) 8268 { 8269 struct bce_softc *sc = (struct bce_softc *)arg1; 8270 int error; 8271 u32 result; 8272 u32 val[1]; 8273 u8 *data = (u8 *) val; 8274 8275 result = -1; 8276 error = sysctl_handle_int(oidp, &result, 0, req); 8277 if (error || (req->newptr == NULL)) 8278 return (error); 8279 8280 bce_nvram_read(sc, result, data, 4); 8281 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0])); 8282 8283 return (error); 8284 } 8285 8286 8287 /****************************************************************************/ 8288 /* Provides a sysctl interface to allow reading arbitrary registers in the */ 8289 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8290 /* */ 8291 /* Returns: */ 8292 /* 0 for success, positive value for failure. */ 8293 /****************************************************************************/ 8294 static int 8295 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 8296 { 8297 struct bce_softc *sc = (struct bce_softc *)arg1; 8298 int error; 8299 u32 val, result; 8300 8301 result = -1; 8302 error = sysctl_handle_int(oidp, &result, 0, req); 8303 if (error || (req->newptr == NULL)) 8304 return (error); 8305 8306 /* Make sure the register is accessible. */ 8307 if (result < 0x8000) { 8308 val = REG_RD(sc, result); 8309 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8310 } else if (result < 0x0280000) { 8311 val = REG_RD_IND(sc, result); 8312 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8313 } 8314 8315 return (error); 8316 } 8317 8318 8319 /****************************************************************************/ 8320 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 8321 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8322 /* */ 8323 /* Returns: */ 8324 /* 0 for success, positive value for failure. */ 8325 /****************************************************************************/ 8326 static int 8327 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 8328 { 8329 struct bce_softc *sc; 8330 device_t dev; 8331 int error, result; 8332 u16 val; 8333 8334 result = -1; 8335 error = sysctl_handle_int(oidp, &result, 0, req); 8336 if (error || (req->newptr == NULL)) 8337 return (error); 8338 8339 /* Make sure the register is accessible. */ 8340 if (result < 0x20) { 8341 sc = (struct bce_softc *)arg1; 8342 dev = sc->bce_dev; 8343 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 8344 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 8345 } 8346 return (error); 8347 } 8348 8349 8350 /****************************************************************************/ 8351 /* Provides a sysctl interface to allow reading a CID. */ 8352 /* */ 8353 /* Returns: */ 8354 /* 0 for success, positive value for failure. */ 8355 /****************************************************************************/ 8356 static int 8357 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS) 8358 { 8359 struct bce_softc *sc; 8360 int error, result; 8361 8362 result = -1; 8363 error = sysctl_handle_int(oidp, &result, 0, req); 8364 if (error || (req->newptr == NULL)) 8365 return (error); 8366 8367 /* Make sure the register is accessible. */ 8368 if (result <= TX_CID) { 8369 sc = (struct bce_softc *)arg1; 8370 bce_dump_ctx(sc, result); 8371 } 8372 8373 return (error); 8374 } 8375 8376 8377 /****************************************************************************/ 8378 /* Provides a sysctl interface to forcing the driver to dump state and */ 8379 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8380 /* */ 8381 /* Returns: */ 8382 /* 0 for success, positive value for failure. */ 8383 /****************************************************************************/ 8384 static int 8385 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 8386 { 8387 int error; 8388 int result; 8389 struct bce_softc *sc; 8390 8391 result = -1; 8392 error = sysctl_handle_int(oidp, &result, 0, req); 8393 8394 if (error || !req->newptr) 8395 return (error); 8396 8397 if (result == 1) { 8398 sc = (struct bce_softc *)arg1; 8399 bce_breakpoint(sc); 8400 } 8401 8402 return error; 8403 } 8404 #endif 8405 8406 8407 /****************************************************************************/ 8408 /* Adds any sysctl parameters for tuning or debugging purposes. */ 8409 /* */ 8410 /* Returns: */ 8411 /* 0 for success, positive value for failure. */ 8412 /****************************************************************************/ 8413 static void 8414 bce_add_sysctls(struct bce_softc *sc) 8415 { 8416 struct sysctl_ctx_list *ctx; 8417 struct sysctl_oid_list *children; 8418 8419 DBENTER(BCE_VERBOSE_MISC); 8420 8421 ctx = device_get_sysctl_ctx(sc->bce_dev); 8422 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 8423 8424 #ifdef BCE_DEBUG 8425 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8426 "l2fhdr_error_sim_control", 8427 CTLFLAG_RW, &l2fhdr_error_sim_control, 8428 0, "Debug control to force l2fhdr errors"); 8429 8430 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8431 "l2fhdr_error_sim_count", 8432 CTLFLAG_RD, &sc->l2fhdr_error_sim_count, 8433 0, "Number of simulated l2_fhdr errors"); 8434 #endif 8435 8436 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8437 "l2fhdr_error_count", 8438 CTLFLAG_RD, &sc->l2fhdr_error_count, 8439 0, "Number of l2_fhdr errors"); 8440 8441 #ifdef BCE_DEBUG 8442 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8443 "mbuf_alloc_failed_sim_control", 8444 CTLFLAG_RW, &mbuf_alloc_failed_sim_control, 8445 0, "Debug control to force mbuf allocation failures"); 8446 8447 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8448 "mbuf_alloc_failed_sim_count", 8449 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count, 8450 0, "Number of simulated mbuf cluster allocation failures"); 8451 #endif 8452 8453 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8454 "mbuf_alloc_failed_count", 8455 CTLFLAG_RD, &sc->mbuf_alloc_failed_count, 8456 0, "Number of mbuf allocation failures"); 8457 8458 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8459 "mbuf_frag_count", 8460 CTLFLAG_RD, &sc->mbuf_frag_count, 8461 0, "Number of fragmented mbufs"); 8462 8463 #ifdef BCE_DEBUG 8464 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8465 "dma_map_addr_failed_sim_control", 8466 CTLFLAG_RW, &dma_map_addr_failed_sim_control, 8467 0, "Debug control to force DMA mapping failures"); 8468 8469 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */ 8470 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8471 "dma_map_addr_failed_sim_count", 8472 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count, 8473 0, "Number of simulated DMA mapping failures"); 8474 8475 #endif 8476 8477 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8478 "dma_map_addr_rx_failed_count", 8479 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count, 8480 0, "Number of RX DMA mapping failures"); 8481 8482 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8483 "dma_map_addr_tx_failed_count", 8484 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count, 8485 0, "Number of TX DMA mapping failures"); 8486 8487 #ifdef BCE_DEBUG 8488 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8489 "unexpected_attention_sim_control", 8490 CTLFLAG_RW, &unexpected_attention_sim_control, 8491 0, "Debug control to simulate unexpected attentions"); 8492 8493 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8494 "unexpected_attention_sim_count", 8495 CTLFLAG_RW, &sc->unexpected_attention_sim_count, 8496 0, "Number of simulated unexpected attentions"); 8497 #endif 8498 8499 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8500 "unexpected_attention_count", 8501 CTLFLAG_RW, &sc->unexpected_attention_count, 8502 0, "Number of unexpected attentions"); 8503 8504 #ifdef BCE_DEBUG 8505 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8506 "debug_bootcode_running_failure", 8507 CTLFLAG_RW, &bootcode_running_failure_sim_control, 8508 0, "Debug control to force bootcode running failures"); 8509 8510 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8511 "rx_low_watermark", 8512 CTLFLAG_RD, &sc->rx_low_watermark, 8513 0, "Lowest level of free rx_bd's"); 8514 8515 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8516 "rx_empty_count", 8517 CTLFLAG_RD, &sc->rx_empty_count, 8518 0, "Number of times the RX chain was empty"); 8519 8520 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8521 "tx_hi_watermark", 8522 CTLFLAG_RD, &sc->tx_hi_watermark, 8523 0, "Highest level of used tx_bd's"); 8524 8525 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8526 "tx_full_count", 8527 CTLFLAG_RD, &sc->tx_full_count, 8528 0, "Number of times the TX chain was full"); 8529 8530 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8531 "tso_frames_requested", 8532 CTLFLAG_RD, &sc->tso_frames_requested, 8533 0, "Number of TSO frames requested"); 8534 8535 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8536 "tso_frames_completed", 8537 CTLFLAG_RD, &sc->tso_frames_completed, 8538 0, "Number of TSO frames completed"); 8539 8540 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8541 "tso_frames_failed", 8542 CTLFLAG_RD, &sc->tso_frames_failed, 8543 0, "Number of TSO frames failed"); 8544 8545 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8546 "csum_offload_ip", 8547 CTLFLAG_RD, &sc->csum_offload_ip, 8548 0, "Number of IP checksum offload frames"); 8549 8550 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8551 "csum_offload_tcp_udp", 8552 CTLFLAG_RD, &sc->csum_offload_tcp_udp, 8553 0, "Number of TCP/UDP checksum offload frames"); 8554 8555 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8556 "vlan_tagged_frames_rcvd", 8557 CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd, 8558 0, "Number of VLAN tagged frames received"); 8559 8560 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8561 "vlan_tagged_frames_stripped", 8562 CTLFLAG_RD, &sc->vlan_tagged_frames_stripped, 8563 0, "Number of VLAN tagged frames stripped"); 8564 8565 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8566 "interrupts_rx", 8567 CTLFLAG_RD, &sc->interrupts_rx, 8568 0, "Number of RX interrupts"); 8569 8570 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8571 "interrupts_tx", 8572 CTLFLAG_RD, &sc->interrupts_tx, 8573 0, "Number of TX interrupts"); 8574 #endif 8575 8576 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8577 "stat_IfHcInOctets", 8578 CTLFLAG_RD, &sc->stat_IfHCInOctets, 8579 "Bytes received"); 8580 8581 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8582 "stat_IfHCInBadOctets", 8583 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 8584 "Bad bytes received"); 8585 8586 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8587 "stat_IfHCOutOctets", 8588 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 8589 "Bytes sent"); 8590 8591 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8592 "stat_IfHCOutBadOctets", 8593 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 8594 "Bad bytes sent"); 8595 8596 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8597 "stat_IfHCInUcastPkts", 8598 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 8599 "Unicast packets received"); 8600 8601 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8602 "stat_IfHCInMulticastPkts", 8603 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 8604 "Multicast packets received"); 8605 8606 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8607 "stat_IfHCInBroadcastPkts", 8608 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 8609 "Broadcast packets received"); 8610 8611 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8612 "stat_IfHCOutUcastPkts", 8613 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 8614 "Unicast packets sent"); 8615 8616 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8617 "stat_IfHCOutMulticastPkts", 8618 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 8619 "Multicast packets sent"); 8620 8621 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8622 "stat_IfHCOutBroadcastPkts", 8623 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 8624 "Broadcast packets sent"); 8625 8626 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8627 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 8628 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 8629 0, "Internal MAC transmit errors"); 8630 8631 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8632 "stat_Dot3StatsCarrierSenseErrors", 8633 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 8634 0, "Carrier sense errors"); 8635 8636 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8637 "stat_Dot3StatsFCSErrors", 8638 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 8639 0, "Frame check sequence errors"); 8640 8641 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8642 "stat_Dot3StatsAlignmentErrors", 8643 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 8644 0, "Alignment errors"); 8645 8646 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8647 "stat_Dot3StatsSingleCollisionFrames", 8648 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 8649 0, "Single Collision Frames"); 8650 8651 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8652 "stat_Dot3StatsMultipleCollisionFrames", 8653 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 8654 0, "Multiple Collision Frames"); 8655 8656 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8657 "stat_Dot3StatsDeferredTransmissions", 8658 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 8659 0, "Deferred Transmissions"); 8660 8661 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8662 "stat_Dot3StatsExcessiveCollisions", 8663 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 8664 0, "Excessive Collisions"); 8665 8666 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8667 "stat_Dot3StatsLateCollisions", 8668 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 8669 0, "Late Collisions"); 8670 8671 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8672 "stat_EtherStatsCollisions", 8673 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 8674 0, "Collisions"); 8675 8676 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8677 "stat_EtherStatsFragments", 8678 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 8679 0, "Fragments"); 8680 8681 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8682 "stat_EtherStatsJabbers", 8683 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 8684 0, "Jabbers"); 8685 8686 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8687 "stat_EtherStatsUndersizePkts", 8688 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 8689 0, "Undersize packets"); 8690 8691 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8692 "stat_EtherStatsOversizePkts", 8693 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts, 8694 0, "stat_EtherStatsOversizePkts"); 8695 8696 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8697 "stat_EtherStatsPktsRx64Octets", 8698 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 8699 0, "Bytes received in 64 byte packets"); 8700 8701 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8702 "stat_EtherStatsPktsRx65Octetsto127Octets", 8703 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 8704 0, "Bytes received in 65 to 127 byte packets"); 8705 8706 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8707 "stat_EtherStatsPktsRx128Octetsto255Octets", 8708 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 8709 0, "Bytes received in 128 to 255 byte packets"); 8710 8711 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8712 "stat_EtherStatsPktsRx256Octetsto511Octets", 8713 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 8714 0, "Bytes received in 256 to 511 byte packets"); 8715 8716 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8717 "stat_EtherStatsPktsRx512Octetsto1023Octets", 8718 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 8719 0, "Bytes received in 512 to 1023 byte packets"); 8720 8721 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8722 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 8723 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 8724 0, "Bytes received in 1024 t0 1522 byte packets"); 8725 8726 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8727 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 8728 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 8729 0, "Bytes received in 1523 to 9022 byte packets"); 8730 8731 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8732 "stat_EtherStatsPktsTx64Octets", 8733 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 8734 0, "Bytes sent in 64 byte packets"); 8735 8736 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8737 "stat_EtherStatsPktsTx65Octetsto127Octets", 8738 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 8739 0, "Bytes sent in 65 to 127 byte packets"); 8740 8741 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8742 "stat_EtherStatsPktsTx128Octetsto255Octets", 8743 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 8744 0, "Bytes sent in 128 to 255 byte packets"); 8745 8746 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8747 "stat_EtherStatsPktsTx256Octetsto511Octets", 8748 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 8749 0, "Bytes sent in 256 to 511 byte packets"); 8750 8751 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8752 "stat_EtherStatsPktsTx512Octetsto1023Octets", 8753 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 8754 0, "Bytes sent in 512 to 1023 byte packets"); 8755 8756 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8757 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 8758 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 8759 0, "Bytes sent in 1024 to 1522 byte packets"); 8760 8761 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8762 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 8763 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 8764 0, "Bytes sent in 1523 to 9022 byte packets"); 8765 8766 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8767 "stat_XonPauseFramesReceived", 8768 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 8769 0, "XON pause frames receved"); 8770 8771 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8772 "stat_XoffPauseFramesReceived", 8773 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 8774 0, "XOFF pause frames received"); 8775 8776 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8777 "stat_OutXonSent", 8778 CTLFLAG_RD, &sc->stat_OutXonSent, 8779 0, "XON pause frames sent"); 8780 8781 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8782 "stat_OutXoffSent", 8783 CTLFLAG_RD, &sc->stat_OutXoffSent, 8784 0, "XOFF pause frames sent"); 8785 8786 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8787 "stat_FlowControlDone", 8788 CTLFLAG_RD, &sc->stat_FlowControlDone, 8789 0, "Flow control done"); 8790 8791 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8792 "stat_MacControlFramesReceived", 8793 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 8794 0, "MAC control frames received"); 8795 8796 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8797 "stat_XoffStateEntered", 8798 CTLFLAG_RD, &sc->stat_XoffStateEntered, 8799 0, "XOFF state entered"); 8800 8801 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8802 "stat_IfInFramesL2FilterDiscards", 8803 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 8804 0, "Received L2 packets discarded"); 8805 8806 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8807 "stat_IfInRuleCheckerDiscards", 8808 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 8809 0, "Received packets discarded by rule"); 8810 8811 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8812 "stat_IfInFTQDiscards", 8813 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 8814 0, "Received packet FTQ discards"); 8815 8816 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8817 "stat_IfInMBUFDiscards", 8818 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 8819 0, "Received packets discarded due to lack " 8820 "of controller buffer memory"); 8821 8822 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8823 "stat_IfInRuleCheckerP4Hit", 8824 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 8825 0, "Received packets rule checker hits"); 8826 8827 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8828 "stat_CatchupInRuleCheckerDiscards", 8829 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 8830 0, "Received packets discarded in Catchup path"); 8831 8832 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8833 "stat_CatchupInFTQDiscards", 8834 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 8835 0, "Received packets discarded in FTQ in Catchup path"); 8836 8837 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8838 "stat_CatchupInMBUFDiscards", 8839 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 8840 0, "Received packets discarded in controller " 8841 "buffer memory in Catchup path"); 8842 8843 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8844 "stat_CatchupInRuleCheckerP4Hit", 8845 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 8846 0, "Received packets rule checker hits in Catchup path"); 8847 8848 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8849 "com_no_buffers", 8850 CTLFLAG_RD, &sc->com_no_buffers, 8851 0, "Valid packets received but no RX buffers available"); 8852 8853 #ifdef BCE_DEBUG 8854 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8855 "driver_state", CTLTYPE_INT | CTLFLAG_RW, 8856 (void *)sc, 0, 8857 bce_sysctl_driver_state, "I", "Drive state information"); 8858 8859 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8860 "hw_state", CTLTYPE_INT | CTLFLAG_RW, 8861 (void *)sc, 0, 8862 bce_sysctl_hw_state, "I", "Hardware state information"); 8863 8864 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8865 "status_block", CTLTYPE_INT | CTLFLAG_RW, 8866 (void *)sc, 0, 8867 bce_sysctl_status_block, "I", "Dump status block"); 8868 8869 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8870 "stats_block", CTLTYPE_INT | CTLFLAG_RW, 8871 (void *)sc, 0, 8872 bce_sysctl_stats_block, "I", "Dump statistics block"); 8873 8874 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8875 "stats_clear", CTLTYPE_INT | CTLFLAG_RW, 8876 (void *)sc, 0, 8877 bce_sysctl_stats_clear, "I", "Clear statistics block"); 8878 8879 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8880 "bc_state", CTLTYPE_INT | CTLFLAG_RW, 8881 (void *)sc, 0, 8882 bce_sysctl_bc_state, "I", "Bootcode state information"); 8883 8884 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8885 "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW, 8886 (void *)sc, 0, 8887 bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain"); 8888 8889 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8890 "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW, 8891 (void *)sc, 0, 8892 bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain"); 8893 8894 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8895 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW, 8896 (void *)sc, 0, 8897 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 8898 8899 #ifdef BCE_JUMBO_HDRSPLIT 8900 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8901 "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW, 8902 (void *)sc, 0, 8903 bce_sysctl_dump_pg_chain, "I", "Dump page chain"); 8904 #endif 8905 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8906 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW, 8907 (void *)sc, 0, 8908 bce_sysctl_dump_ctx, "I", "Dump context memory"); 8909 8910 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8911 "breakpoint", CTLTYPE_INT | CTLFLAG_RW, 8912 (void *)sc, 0, 8913 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 8914 8915 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8916 "reg_read", CTLTYPE_INT | CTLFLAG_RW, 8917 (void *)sc, 0, 8918 bce_sysctl_reg_read, "I", "Register read"); 8919 8920 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8921 "nvram_read", CTLTYPE_INT | CTLFLAG_RW, 8922 (void *)sc, 0, 8923 bce_sysctl_nvram_read, "I", "NVRAM read"); 8924 8925 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8926 "phy_read", CTLTYPE_INT | CTLFLAG_RW, 8927 (void *)sc, 0, 8928 bce_sysctl_phy_read, "I", "PHY register read"); 8929 8930 #endif 8931 8932 DBEXIT(BCE_VERBOSE_MISC); 8933 } 8934 8935 8936 /****************************************************************************/ 8937 /* BCE Debug Routines */ 8938 /****************************************************************************/ 8939 #ifdef BCE_DEBUG 8940 8941 /****************************************************************************/ 8942 /* Freezes the controller to allow for a cohesive state dump. */ 8943 /* */ 8944 /* Returns: */ 8945 /* Nothing. */ 8946 /****************************************************************************/ 8947 static __attribute__ ((noinline)) void 8948 bce_freeze_controller(struct bce_softc *sc) 8949 { 8950 u32 val; 8951 val = REG_RD(sc, BCE_MISC_COMMAND); 8952 val |= BCE_MISC_COMMAND_DISABLE_ALL; 8953 REG_WR(sc, BCE_MISC_COMMAND, val); 8954 } 8955 8956 8957 /****************************************************************************/ 8958 /* Unfreezes the controller after a freeze operation. This may not always */ 8959 /* work and the controller will require a reset! */ 8960 /* */ 8961 /* Returns: */ 8962 /* Nothing. */ 8963 /****************************************************************************/ 8964 static __attribute__ ((noinline)) void 8965 bce_unfreeze_controller(struct bce_softc *sc) 8966 { 8967 u32 val; 8968 val = REG_RD(sc, BCE_MISC_COMMAND); 8969 val |= BCE_MISC_COMMAND_ENABLE_ALL; 8970 REG_WR(sc, BCE_MISC_COMMAND, val); 8971 } 8972 8973 8974 /****************************************************************************/ 8975 /* Prints out Ethernet frame information from an mbuf. */ 8976 /* */ 8977 /* Partially decode an Ethernet frame to look at some important headers. */ 8978 /* */ 8979 /* Returns: */ 8980 /* Nothing. */ 8981 /****************************************************************************/ 8982 static __attribute__ ((noinline)) void 8983 bce_dump_enet(struct bce_softc *sc, struct mbuf *m) 8984 { 8985 struct ether_vlan_header *eh; 8986 u16 etype; 8987 int ehlen; 8988 struct ip *ip; 8989 struct tcphdr *th; 8990 struct udphdr *uh; 8991 struct arphdr *ah; 8992 8993 BCE_PRINTF( 8994 "-----------------------------" 8995 " Frame Decode " 8996 "-----------------------------\n"); 8997 8998 eh = mtod(m, struct ether_vlan_header *); 8999 9000 /* Handle VLAN encapsulation if present. */ 9001 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 9002 etype = ntohs(eh->evl_proto); 9003 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 9004 } else { 9005 etype = ntohs(eh->evl_encap_proto); 9006 ehlen = ETHER_HDR_LEN; 9007 } 9008 9009 /* ToDo: Add VLAN output. */ 9010 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n", 9011 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen); 9012 9013 switch (etype) { 9014 case ETHERTYPE_IP: 9015 ip = (struct ip *)(m->m_data + ehlen); 9016 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, " 9017 "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n", 9018 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr), 9019 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum)); 9020 9021 switch (ip->ip_p) { 9022 case IPPROTO_TCP: 9023 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9024 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = " 9025 "%d bytes, flags = 0x%b, csum = 0x%04X\n", 9026 ntohs(th->th_dport), ntohs(th->th_sport), 9027 (th->th_off << 2), th->th_flags, 9028 "\2\10CWR\07ECE\06URG\05ACK\04PSH\03RST" 9029 "\02SYN\01FIN", ntohs(th->th_sum)); 9030 break; 9031 case IPPROTO_UDP: 9032 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9033 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d " 9034 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport), 9035 ntohs(uh->uh_sport), ntohs(uh->uh_ulen), 9036 ntohs(uh->uh_sum)); 9037 break; 9038 case IPPROTO_ICMP: 9039 BCE_PRINTF("icmp:\n"); 9040 break; 9041 default: 9042 BCE_PRINTF("----: Other IP protocol.\n"); 9043 } 9044 break; 9045 case ETHERTYPE_IPV6: 9046 BCE_PRINTF("ipv6: No decode supported.\n"); 9047 break; 9048 case ETHERTYPE_ARP: 9049 BCE_PRINTF("-arp: "); 9050 ah = (struct arphdr *) (m->m_data + ehlen); 9051 switch (ntohs(ah->ar_op)) { 9052 case ARPOP_REVREQUEST: 9053 printf("reverse ARP request\n"); 9054 break; 9055 case ARPOP_REVREPLY: 9056 printf("reverse ARP reply\n"); 9057 break; 9058 case ARPOP_REQUEST: 9059 printf("ARP request\n"); 9060 break; 9061 case ARPOP_REPLY: 9062 printf("ARP reply\n"); 9063 break; 9064 default: 9065 printf("other ARP operation\n"); 9066 } 9067 break; 9068 default: 9069 BCE_PRINTF("----: Other protocol.\n"); 9070 } 9071 9072 BCE_PRINTF( 9073 "-----------------------------" 9074 "--------------" 9075 "-----------------------------\n"); 9076 } 9077 9078 9079 /****************************************************************************/ 9080 /* Prints out information about an mbuf. */ 9081 /* */ 9082 /* Returns: */ 9083 /* Nothing. */ 9084 /****************************************************************************/ 9085 static __attribute__ ((noinline)) void 9086 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 9087 { 9088 struct mbuf *mp = m; 9089 9090 if (m == NULL) { 9091 BCE_PRINTF("mbuf: null pointer\n"); 9092 return; 9093 } 9094 9095 while (mp) { 9096 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, " 9097 "m_data = %p\n", mp, mp->m_len, mp->m_flags, 9098 "\2\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data); 9099 9100 if (mp->m_flags & M_PKTHDR) { 9101 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, " 9102 "csum_flags = %b\n", mp->m_pkthdr.len, 9103 mp->m_flags, "\2\12M_BCAST\13M_MCAST\14M_FRAG" 9104 "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG" 9105 "\22M_PROMISC\23M_NOFREE", 9106 mp->m_pkthdr.csum_flags, 9107 "\2\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS" 9108 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED" 9109 "\12CSUM_IP_VALID\13CSUM_DATA_VALID" 9110 "\14CSUM_PSEUDO_HDR"); 9111 } 9112 9113 if (mp->m_flags & M_EXT) { 9114 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ", 9115 mp->m_ext.ext_buf, mp->m_ext.ext_size); 9116 switch (mp->m_ext.ext_type) { 9117 case EXT_CLUSTER: 9118 printf("EXT_CLUSTER\n"); break; 9119 case EXT_SFBUF: 9120 printf("EXT_SFBUF\n"); break; 9121 case EXT_JUMBO9: 9122 printf("EXT_JUMBO9\n"); break; 9123 case EXT_JUMBO16: 9124 printf("EXT_JUMBO16\n"); break; 9125 case EXT_PACKET: 9126 printf("EXT_PACKET\n"); break; 9127 case EXT_MBUF: 9128 printf("EXT_MBUF\n"); break; 9129 case EXT_NET_DRV: 9130 printf("EXT_NET_DRV\n"); break; 9131 case EXT_MOD_TYPE: 9132 printf("EXT_MDD_TYPE\n"); break; 9133 case EXT_DISPOSABLE: 9134 printf("EXT_DISPOSABLE\n"); break; 9135 case EXT_EXTREF: 9136 printf("EXT_EXTREF\n"); break; 9137 default: 9138 printf("UNKNOWN\n"); 9139 } 9140 } 9141 9142 mp = mp->m_next; 9143 } 9144 } 9145 9146 9147 /****************************************************************************/ 9148 /* Prints out the mbufs in the TX mbuf chain. */ 9149 /* */ 9150 /* Returns: */ 9151 /* Nothing. */ 9152 /****************************************************************************/ 9153 static __attribute__ ((noinline)) void 9154 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9155 { 9156 struct mbuf *m; 9157 9158 BCE_PRINTF( 9159 "----------------------------" 9160 " tx mbuf data " 9161 "----------------------------\n"); 9162 9163 for (int i = 0; i < count; i++) { 9164 m = sc->tx_mbuf_ptr[chain_prod]; 9165 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod); 9166 bce_dump_mbuf(sc, m); 9167 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 9168 } 9169 9170 BCE_PRINTF( 9171 "----------------------------" 9172 "----------------" 9173 "----------------------------\n"); 9174 } 9175 9176 9177 /****************************************************************************/ 9178 /* Prints out the mbufs in the RX mbuf chain. */ 9179 /* */ 9180 /* Returns: */ 9181 /* Nothing. */ 9182 /****************************************************************************/ 9183 static __attribute__ ((noinline)) void 9184 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9185 { 9186 struct mbuf *m; 9187 9188 BCE_PRINTF( 9189 "----------------------------" 9190 " rx mbuf data " 9191 "----------------------------\n"); 9192 9193 for (int i = 0; i < count; i++) { 9194 m = sc->rx_mbuf_ptr[chain_prod]; 9195 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 9196 bce_dump_mbuf(sc, m); 9197 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 9198 } 9199 9200 9201 BCE_PRINTF( 9202 "----------------------------" 9203 "----------------" 9204 "----------------------------\n"); 9205 } 9206 9207 9208 #ifdef BCE_JUMBO_HDRSPLIT 9209 /****************************************************************************/ 9210 /* Prints out the mbufs in the mbuf page chain. */ 9211 /* */ 9212 /* Returns: */ 9213 /* Nothing. */ 9214 /****************************************************************************/ 9215 static __attribute__ ((noinline)) void 9216 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9217 { 9218 struct mbuf *m; 9219 9220 BCE_PRINTF( 9221 "----------------------------" 9222 " pg mbuf data " 9223 "----------------------------\n"); 9224 9225 for (int i = 0; i < count; i++) { 9226 m = sc->pg_mbuf_ptr[chain_prod]; 9227 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod); 9228 bce_dump_mbuf(sc, m); 9229 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod)); 9230 } 9231 9232 9233 BCE_PRINTF( 9234 "----------------------------" 9235 "----------------" 9236 "----------------------------\n"); 9237 } 9238 #endif 9239 9240 9241 /****************************************************************************/ 9242 /* Prints out a tx_bd structure. */ 9243 /* */ 9244 /* Returns: */ 9245 /* Nothing. */ 9246 /****************************************************************************/ 9247 static __attribute__ ((noinline)) void 9248 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 9249 { 9250 int i = 0; 9251 9252 if (idx > MAX_TX_BD) 9253 /* Index out of range. */ 9254 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 9255 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 9256 /* TX Chain page pointer. */ 9257 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9258 "pointer\n", idx, txbd->tx_bd_haddr_hi, 9259 txbd->tx_bd_haddr_lo); 9260 else { 9261 /* Normal tx_bd entry. */ 9262 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, " 9263 "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = " 9264 "0x%04X (", idx, txbd->tx_bd_haddr_hi, 9265 txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes, 9266 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags); 9267 9268 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) { 9269 if (i>0) 9270 printf("|"); 9271 printf("CONN_FAULT"); 9272 i++; 9273 } 9274 9275 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) { 9276 if (i>0) 9277 printf("|"); 9278 printf("TCP_UDP_CKSUM"); 9279 i++; 9280 } 9281 9282 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) { 9283 if (i>0) 9284 printf("|"); 9285 printf("IP_CKSUM"); 9286 i++; 9287 } 9288 9289 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) { 9290 if (i>0) 9291 printf("|"); 9292 printf("VLAN"); 9293 i++; 9294 } 9295 9296 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) { 9297 if (i>0) 9298 printf("|"); 9299 printf("COAL_NOW"); 9300 i++; 9301 } 9302 9303 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) { 9304 if (i>0) 9305 printf("|"); 9306 printf("DONT_GEN_CRC"); 9307 i++; 9308 } 9309 9310 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) { 9311 if (i>0) 9312 printf("|"); 9313 printf("START"); 9314 i++; 9315 } 9316 9317 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) { 9318 if (i>0) 9319 printf("|"); 9320 printf("END"); 9321 i++; 9322 } 9323 9324 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) { 9325 if (i>0) 9326 printf("|"); 9327 printf("LSO"); 9328 i++; 9329 } 9330 9331 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) { 9332 if (i>0) 9333 printf("|"); 9334 printf("SW_OPTION=%d", ((txbd->tx_bd_flags & 9335 TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++; 9336 } 9337 9338 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) { 9339 if (i>0) 9340 printf("|"); 9341 printf("SW_FLAGS"); 9342 i++; 9343 } 9344 9345 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) { 9346 if (i>0) 9347 printf("|"); 9348 printf("SNAP)"); 9349 } else { 9350 printf(")\n"); 9351 } 9352 } 9353 } 9354 9355 9356 /****************************************************************************/ 9357 /* Prints out a rx_bd structure. */ 9358 /* */ 9359 /* Returns: */ 9360 /* Nothing. */ 9361 /****************************************************************************/ 9362 static __attribute__ ((noinline)) void 9363 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 9364 { 9365 if (idx > MAX_RX_BD) 9366 /* Index out of range. */ 9367 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 9368 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 9369 /* RX Chain page pointer. */ 9370 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9371 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 9372 rxbd->rx_bd_haddr_lo); 9373 else 9374 /* Normal rx_bd entry. */ 9375 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 9376 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi, 9377 rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len, 9378 rxbd->rx_bd_flags); 9379 } 9380 9381 9382 #ifdef BCE_JUMBO_HDRSPLIT 9383 /****************************************************************************/ 9384 /* Prints out a rx_bd structure in the page chain. */ 9385 /* */ 9386 /* Returns: */ 9387 /* Nothing. */ 9388 /****************************************************************************/ 9389 static __attribute__ ((noinline)) void 9390 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd) 9391 { 9392 if (idx > MAX_PG_BD) 9393 /* Index out of range. */ 9394 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx); 9395 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE) 9396 /* Page Chain page pointer. */ 9397 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 9398 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo); 9399 else 9400 /* Normal rx_bd entry. */ 9401 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 9402 "flags = 0x%08X\n", idx, 9403 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo, 9404 pgbd->rx_bd_len, pgbd->rx_bd_flags); 9405 } 9406 #endif 9407 9408 9409 /****************************************************************************/ 9410 /* Prints out a l2_fhdr structure. */ 9411 /* */ 9412 /* Returns: */ 9413 /* Nothing. */ 9414 /****************************************************************************/ 9415 static __attribute__ ((noinline)) void 9416 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 9417 { 9418 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, " 9419 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, " 9420 "tcp_udp_xsum = 0x%04X\n", idx, 9421 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB, 9422 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, 9423 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); 9424 } 9425 9426 9427 /****************************************************************************/ 9428 /* Prints out context memory info. (Only useful for CID 0 to 16.) */ 9429 /* */ 9430 /* Returns: */ 9431 /* Nothing. */ 9432 /****************************************************************************/ 9433 static __attribute__ ((noinline)) void 9434 bce_dump_ctx(struct bce_softc *sc, u16 cid) 9435 { 9436 if (cid > TX_CID) { 9437 BCE_PRINTF(" Unknown CID\n"); 9438 return; 9439 } 9440 9441 BCE_PRINTF( 9442 "----------------------------" 9443 " CTX Data " 9444 "----------------------------\n"); 9445 9446 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid); 9447 9448 if (cid == RX_CID) { 9449 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx " 9450 "producer index\n", 9451 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX)); 9452 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host " 9453 "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 9454 BCE_L2CTX_RX_HOST_BSEQ)); 9455 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n", 9456 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ)); 9457 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer " 9458 "descriptor address\n", 9459 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI)); 9460 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer " 9461 "descriptor address\n", 9462 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO)); 9463 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer " 9464 "index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9465 BCE_L2CTX_RX_NX_BDIDX)); 9466 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page " 9467 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9468 BCE_L2CTX_RX_HOST_PG_BDIDX)); 9469 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page " 9470 "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid), 9471 BCE_L2CTX_RX_PG_BUF_SIZE)); 9472 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page " 9473 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 9474 BCE_L2CTX_RX_NX_PG_BDHADDR_HI)); 9475 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page " 9476 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 9477 BCE_L2CTX_RX_NX_PG_BDHADDR_LO)); 9478 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page " 9479 "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9480 BCE_L2CTX_RX_NX_PG_BDIDX)); 9481 } else if (cid == TX_CID) { 9482 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 9483 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 9484 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n", 9485 CTX_RD(sc, GET_CID_ADDR(cid), 9486 BCE_L2CTX_TX_TYPE_XI)); 9487 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx " 9488 "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid), 9489 BCE_L2CTX_TX_CMD_TYPE_XI)); 9490 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) " 9491 "h/w buffer descriptor address\n", 9492 CTX_RD(sc, GET_CID_ADDR(cid), 9493 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI)); 9494 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) " 9495 "h/w buffer descriptor address\n", 9496 CTX_RD(sc, GET_CID_ADDR(cid), 9497 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI)); 9498 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) " 9499 "host producer index\n", 9500 CTX_RD(sc, GET_CID_ADDR(cid), 9501 BCE_L2CTX_TX_HOST_BIDX_XI)); 9502 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) " 9503 "host byte sequence\n", 9504 CTX_RD(sc, GET_CID_ADDR(cid), 9505 BCE_L2CTX_TX_HOST_BSEQ_XI)); 9506 } else { 9507 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n", 9508 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE)); 9509 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n", 9510 CTX_RD(sc, GET_CID_ADDR(cid), 9511 BCE_L2CTX_TX_CMD_TYPE)); 9512 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) " 9513 "h/w buffer descriptor address\n", 9514 CTX_RD(sc, GET_CID_ADDR(cid), 9515 BCE_L2CTX_TX_TBDR_BHADDR_HI)); 9516 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) " 9517 "h/w buffer descriptor address\n", 9518 CTX_RD(sc, GET_CID_ADDR(cid), 9519 BCE_L2CTX_TX_TBDR_BHADDR_LO)); 9520 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host " 9521 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9522 BCE_L2CTX_TX_HOST_BIDX)); 9523 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte " 9524 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 9525 BCE_L2CTX_TX_HOST_BSEQ)); 9526 } 9527 } 9528 9529 BCE_PRINTF( 9530 "----------------------------" 9531 " Raw CTX " 9532 "----------------------------\n"); 9533 9534 for (int i = 0x0; i < 0x300; i += 0x10) { 9535 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, 9536 CTX_RD(sc, GET_CID_ADDR(cid), i), 9537 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4), 9538 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8), 9539 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc)); 9540 } 9541 9542 9543 BCE_PRINTF( 9544 "----------------------------" 9545 "----------------" 9546 "----------------------------\n"); 9547 } 9548 9549 9550 /****************************************************************************/ 9551 /* Prints out the FTQ data. */ 9552 /* */ 9553 /* Returns: */ 9554 /* Nothing. */ 9555 /****************************************************************************/ 9556 static __attribute__ ((noinline)) void 9557 bce_dump_ftqs(struct bce_softc *sc) 9558 { 9559 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val; 9560 9561 BCE_PRINTF( 9562 "----------------------------" 9563 " FTQ Data " 9564 "----------------------------\n"); 9565 9566 BCE_PRINTF(" FTQ Command Control Depth_Now " 9567 "Max_Depth Valid_Cnt \n"); 9568 BCE_PRINTF(" ------- ---------- ---------- ---------- " 9569 "---------- ----------\n"); 9570 9571 /* Setup the generic statistic counters for the FTQ valid count. */ 9572 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) | 9573 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) | 9574 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) | 9575 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT); 9576 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 9577 9578 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) | 9579 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) | 9580 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) | 9581 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT); 9582 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val); 9583 9584 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) | 9585 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) | 9586 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) | 9587 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT); 9588 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val); 9589 9590 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) | 9591 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) | 9592 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) | 9593 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT); 9594 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val); 9595 9596 /* Input queue to the Receive Lookup state machine */ 9597 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD); 9598 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL); 9599 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22; 9600 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12; 9601 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 9602 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9603 cmd, ctl, cur_depth, max_depth, valid_cnt); 9604 9605 /* Input queue to the Receive Processor */ 9606 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD); 9607 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL); 9608 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22; 9609 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12; 9610 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 9611 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9612 cmd, ctl, cur_depth, max_depth, valid_cnt); 9613 9614 /* Input queue to the Recevie Processor */ 9615 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD); 9616 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL); 9617 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22; 9618 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12; 9619 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 9620 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9621 cmd, ctl, cur_depth, max_depth, valid_cnt); 9622 9623 /* Input queue to the Receive Virtual to Physical state machine */ 9624 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD); 9625 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL); 9626 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22; 9627 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12; 9628 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 9629 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9630 cmd, ctl, cur_depth, max_depth, valid_cnt); 9631 9632 /* Input queue to the Recevie Virtual to Physical state machine */ 9633 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD); 9634 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL); 9635 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22; 9636 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12; 9637 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4); 9638 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9639 cmd, ctl, cur_depth, max_depth, valid_cnt); 9640 9641 /* Input queue to the Receive Virtual to Physical state machine */ 9642 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD); 9643 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL); 9644 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22; 9645 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12; 9646 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5); 9647 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9648 cmd, ctl, cur_depth, max_depth, valid_cnt); 9649 9650 /* Input queue to the Receive DMA state machine */ 9651 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD); 9652 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL); 9653 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22; 9654 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12; 9655 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6); 9656 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9657 cmd, ctl, cur_depth, max_depth, valid_cnt); 9658 9659 /* Input queue to the Transmit Scheduler state machine */ 9660 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD); 9661 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL); 9662 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22; 9663 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12; 9664 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7); 9665 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9666 cmd, ctl, cur_depth, max_depth, valid_cnt); 9667 9668 /* Input queue to the Transmit Buffer Descriptor state machine */ 9669 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD); 9670 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL); 9671 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22; 9672 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12; 9673 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8); 9674 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9675 cmd, ctl, cur_depth, max_depth, valid_cnt); 9676 9677 /* Input queue to the Transmit Processor */ 9678 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD); 9679 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL); 9680 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22; 9681 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12; 9682 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9); 9683 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9684 cmd, ctl, cur_depth, max_depth, valid_cnt); 9685 9686 /* Input queue to the Transmit DMA state machine */ 9687 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD); 9688 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL); 9689 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22; 9690 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12; 9691 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10); 9692 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9693 cmd, ctl, cur_depth, max_depth, valid_cnt); 9694 9695 /* Input queue to the Transmit Patch-Up Processor */ 9696 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD); 9697 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL); 9698 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22; 9699 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12; 9700 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11); 9701 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9702 cmd, ctl, cur_depth, max_depth, valid_cnt); 9703 9704 /* Input queue to the Transmit Assembler state machine */ 9705 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD); 9706 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL); 9707 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22; 9708 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12; 9709 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12); 9710 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9711 cmd, ctl, cur_depth, max_depth, valid_cnt); 9712 9713 /* Input queue to the Completion Processor */ 9714 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD); 9715 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL); 9716 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22; 9717 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12; 9718 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13); 9719 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9720 cmd, ctl, cur_depth, max_depth, valid_cnt); 9721 9722 /* Input queue to the Completion Processor */ 9723 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD); 9724 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL); 9725 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22; 9726 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12; 9727 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14); 9728 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9729 cmd, ctl, cur_depth, max_depth, valid_cnt); 9730 9731 /* Input queue to the Completion Processor */ 9732 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD); 9733 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL); 9734 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22; 9735 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12; 9736 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15); 9737 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9738 cmd, ctl, cur_depth, max_depth, valid_cnt); 9739 9740 /* Setup the generic statistic counters for the FTQ valid count. */ 9741 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) | 9742 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) | 9743 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT); 9744 9745 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 9746 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 9747 val = val | 9748 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 9749 24); 9750 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 9751 9752 /* Input queue to the Management Control Processor */ 9753 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD); 9754 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL); 9755 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22; 9756 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12; 9757 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 9758 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9759 cmd, ctl, cur_depth, max_depth, valid_cnt); 9760 9761 /* Input queue to the Command Processor */ 9762 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD); 9763 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL); 9764 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22; 9765 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12; 9766 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 9767 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9768 cmd, ctl, cur_depth, max_depth, valid_cnt); 9769 9770 /* Input queue to the Completion Scheduler state machine */ 9771 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD); 9772 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL); 9773 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22; 9774 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12; 9775 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 9776 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9777 cmd, ctl, cur_depth, max_depth, valid_cnt); 9778 9779 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 9780 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 9781 /* Input queue to the RV2P Command Scheduler */ 9782 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD); 9783 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL); 9784 cur_depth = (ctl & 0xFFC00000) >> 22; 9785 max_depth = (ctl & 0x003FF000) >> 12; 9786 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 9787 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9788 cmd, ctl, cur_depth, max_depth, valid_cnt); 9789 } 9790 9791 BCE_PRINTF( 9792 "----------------------------" 9793 "----------------" 9794 "----------------------------\n"); 9795 } 9796 9797 9798 /****************************************************************************/ 9799 /* Prints out the TX chain. */ 9800 /* */ 9801 /* Returns: */ 9802 /* Nothing. */ 9803 /****************************************************************************/ 9804 static __attribute__ ((noinline)) void 9805 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count) 9806 { 9807 struct tx_bd *txbd; 9808 9809 /* First some info about the tx_bd chain structure. */ 9810 BCE_PRINTF( 9811 "----------------------------" 9812 " tx_bd chain " 9813 "----------------------------\n"); 9814 9815 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 9816 (u32) BCM_PAGE_SIZE, (u32) TX_PAGES); 9817 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 9818 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 9819 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD); 9820 9821 BCE_PRINTF( 9822 "----------------------------" 9823 " tx_bd data " 9824 "----------------------------\n"); 9825 9826 /* Now print out a decoded list of TX buffer descriptors. */ 9827 for (int i = 0; i < count; i++) { 9828 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 9829 bce_dump_txbd(sc, tx_prod, txbd); 9830 tx_prod++; 9831 } 9832 9833 BCE_PRINTF( 9834 "----------------------------" 9835 "----------------" 9836 "----------------------------\n"); 9837 } 9838 9839 9840 /****************************************************************************/ 9841 /* Prints out the RX chain. */ 9842 /* */ 9843 /* Returns: */ 9844 /* Nothing. */ 9845 /****************************************************************************/ 9846 static __attribute__ ((noinline)) void 9847 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count) 9848 { 9849 struct rx_bd *rxbd; 9850 9851 /* First some info about the rx_bd chain structure. */ 9852 BCE_PRINTF( 9853 "----------------------------" 9854 " rx_bd chain " 9855 "----------------------------\n"); 9856 9857 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 9858 (u32) BCM_PAGE_SIZE, (u32) RX_PAGES); 9859 9860 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 9861 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 9862 9863 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD); 9864 9865 BCE_PRINTF( 9866 "----------------------------" 9867 " rx_bd data " 9868 "----------------------------\n"); 9869 9870 /* Now print out the rx_bd's themselves. */ 9871 for (int i = 0; i < count; i++) { 9872 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 9873 bce_dump_rxbd(sc, rx_prod, rxbd); 9874 rx_prod = RX_CHAIN_IDX(rx_prod + 1); 9875 } 9876 9877 BCE_PRINTF( 9878 "----------------------------" 9879 "----------------" 9880 "----------------------------\n"); 9881 } 9882 9883 9884 #ifdef BCE_JUMBO_HDRSPLIT 9885 /****************************************************************************/ 9886 /* Prints out the page chain. */ 9887 /* */ 9888 /* Returns: */ 9889 /* Nothing. */ 9890 /****************************************************************************/ 9891 static __attribute__ ((noinline)) void 9892 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count) 9893 { 9894 struct rx_bd *pgbd; 9895 9896 /* First some info about the page chain structure. */ 9897 BCE_PRINTF( 9898 "----------------------------" 9899 " page chain " 9900 "----------------------------\n"); 9901 9902 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n", 9903 (u32) BCM_PAGE_SIZE, (u32) PG_PAGES); 9904 9905 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 9906 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE); 9907 9908 BCE_PRINTF("total rx_bd = 0x%08X, max_pg_bd = 0x%08X\n", 9909 (u32) TOTAL_PG_BD, (u32) MAX_PG_BD); 9910 9911 BCE_PRINTF( 9912 "----------------------------" 9913 " page data " 9914 "----------------------------\n"); 9915 9916 /* Now print out the rx_bd's themselves. */ 9917 for (int i = 0; i < count; i++) { 9918 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)]; 9919 bce_dump_pgbd(sc, pg_prod, pgbd); 9920 pg_prod = PG_CHAIN_IDX(pg_prod + 1); 9921 } 9922 9923 BCE_PRINTF( 9924 "----------------------------" 9925 "----------------" 9926 "----------------------------\n"); 9927 } 9928 #endif 9929 9930 9931 #define BCE_PRINT_RX_CONS(arg) \ 9932 if (sblk->status_rx_quick_consumer_index##arg) \ 9933 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \ 9934 sblk->status_rx_quick_consumer_index##arg, (u16) \ 9935 RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \ 9936 arg); 9937 9938 9939 #define BCE_PRINT_TX_CONS(arg) \ 9940 if (sblk->status_tx_quick_consumer_index##arg) \ 9941 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \ 9942 sblk->status_tx_quick_consumer_index##arg, (u16) \ 9943 TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \ 9944 arg); 9945 9946 /****************************************************************************/ 9947 /* Prints out the status block from host memory. */ 9948 /* */ 9949 /* Returns: */ 9950 /* Nothing. */ 9951 /****************************************************************************/ 9952 static __attribute__ ((noinline)) void 9953 bce_dump_status_block(struct bce_softc *sc) 9954 { 9955 struct status_block *sblk; 9956 9957 sblk = sc->status_block; 9958 9959 BCE_PRINTF( 9960 "----------------------------" 9961 " Status Block " 9962 "----------------------------\n"); 9963 9964 /* Theses indices are used for normal L2 drivers. */ 9965 BCE_PRINTF(" 0x%08X - attn_bits\n", 9966 sblk->status_attn_bits); 9967 9968 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 9969 sblk->status_attn_bits_ack); 9970 9971 BCE_PRINT_RX_CONS(0); 9972 BCE_PRINT_TX_CONS(0) 9973 9974 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 9975 9976 /* Theses indices are not used for normal L2 drivers. */ 9977 BCE_PRINT_RX_CONS(1); BCE_PRINT_RX_CONS(2); BCE_PRINT_RX_CONS(3); 9978 BCE_PRINT_RX_CONS(4); BCE_PRINT_RX_CONS(5); BCE_PRINT_RX_CONS(6); 9979 BCE_PRINT_RX_CONS(7); BCE_PRINT_RX_CONS(8); BCE_PRINT_RX_CONS(9); 9980 BCE_PRINT_RX_CONS(10); BCE_PRINT_RX_CONS(11); BCE_PRINT_RX_CONS(12); 9981 BCE_PRINT_RX_CONS(13); BCE_PRINT_RX_CONS(14); BCE_PRINT_RX_CONS(15); 9982 9983 BCE_PRINT_TX_CONS(1); BCE_PRINT_TX_CONS(2); BCE_PRINT_TX_CONS(3); 9984 9985 if (sblk->status_completion_producer_index || 9986 sblk->status_cmd_consumer_index) 9987 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 9988 sblk->status_completion_producer_index, 9989 sblk->status_cmd_consumer_index); 9990 9991 BCE_PRINTF( 9992 "----------------------------" 9993 "----------------" 9994 "----------------------------\n"); 9995 } 9996 9997 9998 #define BCE_PRINT_64BIT_STAT(arg) \ 9999 if (sblk->arg##_lo || sblk->arg##_hi) \ 10000 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \ 10001 sblk->arg##_lo, #arg); 10002 10003 #define BCE_PRINT_32BIT_STAT(arg) \ 10004 if (sblk->arg) \ 10005 BCE_PRINTF(" 0x%08X : %s\n", \ 10006 sblk->arg, #arg); 10007 10008 /****************************************************************************/ 10009 /* Prints out the statistics block from host memory. */ 10010 /* */ 10011 /* Returns: */ 10012 /* Nothing. */ 10013 /****************************************************************************/ 10014 static __attribute__ ((noinline)) void 10015 bce_dump_stats_block(struct bce_softc *sc) 10016 { 10017 struct statistics_block *sblk; 10018 10019 sblk = sc->stats_block; 10020 10021 BCE_PRINTF( 10022 "---------------" 10023 " Stats Block (All Stats Not Shown Are 0) " 10024 "---------------\n"); 10025 10026 BCE_PRINT_64BIT_STAT(stat_IfHCInOctets); 10027 BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets); 10028 BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets); 10029 BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets); 10030 BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts); 10031 BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts); 10032 BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts); 10033 BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts); 10034 BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts); 10035 BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts); 10036 BCE_PRINT_32BIT_STAT( 10037 stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 10038 BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors); 10039 BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors); 10040 BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors); 10041 BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames); 10042 BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames); 10043 BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions); 10044 BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions); 10045 BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions); 10046 BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions); 10047 BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments); 10048 BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers); 10049 BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts); 10050 BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts); 10051 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets); 10052 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets); 10053 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets); 10054 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets); 10055 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets); 10056 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets); 10057 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets); 10058 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets); 10059 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets); 10060 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets); 10061 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets); 10062 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets); 10063 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets); 10064 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets); 10065 BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived); 10066 BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived); 10067 BCE_PRINT_32BIT_STAT(stat_OutXonSent); 10068 BCE_PRINT_32BIT_STAT(stat_OutXoffSent); 10069 BCE_PRINT_32BIT_STAT(stat_FlowControlDone); 10070 BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived); 10071 BCE_PRINT_32BIT_STAT(stat_XoffStateEntered); 10072 BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards); 10073 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards); 10074 BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards); 10075 BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards); 10076 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit); 10077 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards); 10078 BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards); 10079 BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards); 10080 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit); 10081 10082 BCE_PRINTF( 10083 "----------------------------" 10084 "----------------" 10085 "----------------------------\n"); 10086 } 10087 10088 10089 /****************************************************************************/ 10090 /* Prints out a summary of the driver state. */ 10091 /* */ 10092 /* Returns: */ 10093 /* Nothing. */ 10094 /****************************************************************************/ 10095 static __attribute__ ((noinline)) void 10096 bce_dump_driver_state(struct bce_softc *sc) 10097 { 10098 u32 val_hi, val_lo; 10099 10100 BCE_PRINTF( 10101 "-----------------------------" 10102 " Driver State " 10103 "-----------------------------\n"); 10104 10105 val_hi = BCE_ADDR_HI(sc); 10106 val_lo = BCE_ADDR_LO(sc); 10107 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual " 10108 "address\n", val_hi, val_lo); 10109 10110 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 10111 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 10112 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual " 10113 "address\n", val_hi, val_lo); 10114 10115 val_hi = BCE_ADDR_HI(sc->status_block); 10116 val_lo = BCE_ADDR_LO(sc->status_block); 10117 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block " 10118 "virtual address\n", val_hi, val_lo); 10119 10120 val_hi = BCE_ADDR_HI(sc->stats_block); 10121 val_lo = BCE_ADDR_LO(sc->stats_block); 10122 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block " 10123 "virtual address\n", val_hi, val_lo); 10124 10125 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 10126 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 10127 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain " 10128 "virtual adddress\n", val_hi, val_lo); 10129 10130 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 10131 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 10132 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain " 10133 "virtual address\n", val_hi, val_lo); 10134 10135 #ifdef BCE_JUMBO_HDRSPLIT 10136 val_hi = BCE_ADDR_HI(sc->pg_bd_chain); 10137 val_lo = BCE_ADDR_LO(sc->pg_bd_chain); 10138 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain " 10139 "virtual address\n", val_hi, val_lo); 10140 #endif 10141 10142 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 10143 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 10144 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain " 10145 "virtual address\n", val_hi, val_lo); 10146 10147 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 10148 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 10149 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain " 10150 "virtual address\n", val_hi, val_lo); 10151 10152 #ifdef BCE_JUMBO_HDRSPLIT 10153 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr); 10154 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr); 10155 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain " 10156 "virtual address\n", val_hi, val_lo); 10157 #endif 10158 10159 BCE_PRINTF(" 0x%08X - (sc->interrupts_generated) " 10160 "h/w intrs\n", sc->interrupts_generated); 10161 10162 BCE_PRINTF(" 0x%08X - (sc->interrupts_rx) " 10163 "rx interrupts handled\n", sc->interrupts_rx); 10164 10165 BCE_PRINTF(" 0x%08X - (sc->interrupts_tx) " 10166 "tx interrupts handled\n", sc->interrupts_tx); 10167 10168 BCE_PRINTF(" 0x%08X - (sc->phy_interrupts) " 10169 "phy interrupts handled\n", sc->phy_interrupts); 10170 10171 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) " 10172 "status block index\n", sc->last_status_idx); 10173 10174 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer " 10175 "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 10176 10177 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer " 10178 "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 10179 10180 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer " 10181 "byte seq index\n", sc->tx_prod_bseq); 10182 10183 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx " 10184 "mbufs allocated\n", sc->debug_tx_mbuf_alloc); 10185 10186 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used " 10187 "tx_bd's\n", sc->used_tx_bd); 10188 10189 BCE_PRINTF("0x%08X/%08X - (sc->tx_hi_watermark) tx hi " 10190 "watermark\n", sc->tx_hi_watermark, sc->max_tx_bd); 10191 10192 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer " 10193 "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 10194 10195 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer " 10196 "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 10197 10198 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer " 10199 "byte seq index\n", sc->rx_prod_bseq); 10200 10201 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx " 10202 "mbufs allocated\n", sc->debug_rx_mbuf_alloc); 10203 10204 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free " 10205 "rx_bd's\n", sc->free_rx_bd); 10206 10207 #ifdef BCE_JUMBO_HDRSPLIT 10208 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer " 10209 "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod)); 10210 10211 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer " 10212 "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons)); 10213 10214 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page " 10215 "mbufs allocated\n", sc->debug_pg_mbuf_alloc); 10216 10217 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page " 10218 "rx_bd's\n", sc->free_pg_bd); 10219 10220 BCE_PRINTF("0x%08X/%08X - (sc->pg_low_watermark) page low " 10221 "watermark\n", sc->pg_low_watermark, sc->max_pg_bd); 10222 #endif 10223 10224 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) " 10225 "mbuf alloc failures\n", sc->mbuf_alloc_failed_count); 10226 10227 BCE_PRINTF(" 0x%08X - (sc->bce_flags) " 10228 "bce mac flags\n", sc->bce_flags); 10229 10230 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) " 10231 "bce phy flags\n", sc->bce_phy_flags); 10232 10233 BCE_PRINTF( 10234 "----------------------------" 10235 "----------------" 10236 "----------------------------\n"); 10237 } 10238 10239 10240 /****************************************************************************/ 10241 /* Prints out the hardware state through a summary of important register, */ 10242 /* followed by a complete register dump. */ 10243 /* */ 10244 /* Returns: */ 10245 /* Nothing. */ 10246 /****************************************************************************/ 10247 static __attribute__ ((noinline)) void 10248 bce_dump_hw_state(struct bce_softc *sc) 10249 { 10250 u32 val; 10251 10252 BCE_PRINTF( 10253 "----------------------------" 10254 " Hardware State " 10255 "----------------------------\n"); 10256 10257 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10258 10259 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 10260 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 10261 val, BCE_MISC_ENABLE_STATUS_BITS); 10262 10263 val = REG_RD(sc, BCE_DMA_STATUS); 10264 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", 10265 val, BCE_DMA_STATUS); 10266 10267 val = REG_RD(sc, BCE_CTX_STATUS); 10268 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", 10269 val, BCE_CTX_STATUS); 10270 10271 val = REG_RD(sc, BCE_EMAC_STATUS); 10272 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", 10273 val, BCE_EMAC_STATUS); 10274 10275 val = REG_RD(sc, BCE_RPM_STATUS); 10276 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", 10277 val, BCE_RPM_STATUS); 10278 10279 /* ToDo: Create a #define for this constant. */ 10280 val = REG_RD(sc, 0x2004); 10281 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", 10282 val, 0x2004); 10283 10284 val = REG_RD(sc, BCE_RV2P_STATUS); 10285 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", 10286 val, BCE_RV2P_STATUS); 10287 10288 /* ToDo: Create a #define for this constant. */ 10289 val = REG_RD(sc, 0x2c04); 10290 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", 10291 val, 0x2c04); 10292 10293 val = REG_RD(sc, BCE_TBDR_STATUS); 10294 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", 10295 val, BCE_TBDR_STATUS); 10296 10297 val = REG_RD(sc, BCE_TDMA_STATUS); 10298 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", 10299 val, BCE_TDMA_STATUS); 10300 10301 val = REG_RD(sc, BCE_HC_STATUS); 10302 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", 10303 val, BCE_HC_STATUS); 10304 10305 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 10306 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 10307 val, BCE_TXP_CPU_STATE); 10308 10309 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 10310 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 10311 val, BCE_TPAT_CPU_STATE); 10312 10313 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 10314 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 10315 val, BCE_RXP_CPU_STATE); 10316 10317 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 10318 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 10319 val, BCE_COM_CPU_STATE); 10320 10321 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 10322 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", 10323 val, BCE_MCP_CPU_STATE); 10324 10325 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 10326 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 10327 val, BCE_CP_CPU_STATE); 10328 10329 BCE_PRINTF( 10330 "----------------------------" 10331 "----------------" 10332 "----------------------------\n"); 10333 10334 BCE_PRINTF( 10335 "----------------------------" 10336 " Register Dump " 10337 "----------------------------\n"); 10338 10339 for (int i = 0x400; i < 0x8000; i += 0x10) { 10340 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10341 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10342 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10343 } 10344 10345 BCE_PRINTF( 10346 "----------------------------" 10347 "----------------" 10348 "----------------------------\n"); 10349 } 10350 10351 10352 /****************************************************************************/ 10353 /* Prints out the mailbox queue registers. */ 10354 /* */ 10355 /* Returns: */ 10356 /* Nothing. */ 10357 /****************************************************************************/ 10358 static __attribute__ ((noinline)) void 10359 bce_dump_mq_regs(struct bce_softc *sc) 10360 { 10361 BCE_PRINTF( 10362 "----------------------------" 10363 " MQ Regs " 10364 "----------------------------\n"); 10365 10366 BCE_PRINTF( 10367 "----------------------------" 10368 "----------------" 10369 "----------------------------\n"); 10370 10371 for (int i = 0x3c00; i < 0x4000; i += 0x10) { 10372 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10373 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10374 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10375 } 10376 10377 BCE_PRINTF( 10378 "----------------------------" 10379 "----------------" 10380 "----------------------------\n"); 10381 } 10382 10383 10384 /****************************************************************************/ 10385 /* Prints out the bootcode state. */ 10386 /* */ 10387 /* Returns: */ 10388 /* Nothing. */ 10389 /****************************************************************************/ 10390 static __attribute__ ((noinline)) void 10391 bce_dump_bc_state(struct bce_softc *sc) 10392 { 10393 u32 val; 10394 10395 BCE_PRINTF( 10396 "----------------------------" 10397 " Bootcode State " 10398 "----------------------------\n"); 10399 10400 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10401 10402 val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE); 10403 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 10404 val, BCE_BC_RESET_TYPE); 10405 10406 val = bce_shmem_rd(sc, BCE_BC_STATE); 10407 BCE_PRINTF("0x%08X - (0x%06X) state\n", 10408 val, BCE_BC_STATE); 10409 10410 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 10411 BCE_PRINTF("0x%08X - (0x%06X) condition\n", 10412 val, BCE_BC_STATE_CONDITION); 10413 10414 val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD); 10415 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 10416 val, BCE_BC_STATE_DEBUG_CMD); 10417 10418 BCE_PRINTF( 10419 "----------------------------" 10420 "----------------" 10421 "----------------------------\n"); 10422 } 10423 10424 10425 /****************************************************************************/ 10426 /* Prints out the TXP processor state. */ 10427 /* */ 10428 /* Returns: */ 10429 /* Nothing. */ 10430 /****************************************************************************/ 10431 static __attribute__ ((noinline)) void 10432 bce_dump_txp_state(struct bce_softc *sc, int regs) 10433 { 10434 u32 val; 10435 u32 fw_version[3]; 10436 10437 BCE_PRINTF( 10438 "----------------------------" 10439 " TXP State " 10440 "----------------------------\n"); 10441 10442 for (int i = 0; i < 3; i++) 10443 fw_version[i] = htonl(REG_RD_IND(sc, 10444 (BCE_TXP_SCRATCH + 0x10 + i * 4))); 10445 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10446 10447 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 10448 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", 10449 val, BCE_TXP_CPU_MODE); 10450 10451 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 10452 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 10453 val, BCE_TXP_CPU_STATE); 10454 10455 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 10456 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", 10457 val, BCE_TXP_CPU_EVENT_MASK); 10458 10459 if (regs) { 10460 BCE_PRINTF( 10461 "----------------------------" 10462 " Register Dump " 10463 "----------------------------\n"); 10464 10465 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 10466 /* Skip the big blank spaces */ 10467 if (i < 0x454000 && i > 0x5ffff) 10468 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 10469 "0x%08X 0x%08X\n", i, 10470 REG_RD_IND(sc, i), 10471 REG_RD_IND(sc, i + 0x4), 10472 REG_RD_IND(sc, i + 0x8), 10473 REG_RD_IND(sc, i + 0xC)); 10474 } 10475 } 10476 10477 BCE_PRINTF( 10478 "----------------------------" 10479 "----------------" 10480 "----------------------------\n"); 10481 } 10482 10483 10484 /****************************************************************************/ 10485 /* Prints out the RXP processor state. */ 10486 /* */ 10487 /* Returns: */ 10488 /* Nothing. */ 10489 /****************************************************************************/ 10490 static __attribute__ ((noinline)) void 10491 bce_dump_rxp_state(struct bce_softc *sc, int regs) 10492 { 10493 u32 val; 10494 u32 fw_version[3]; 10495 10496 BCE_PRINTF( 10497 "----------------------------" 10498 " RXP State " 10499 "----------------------------\n"); 10500 10501 for (int i = 0; i < 3; i++) 10502 fw_version[i] = htonl(REG_RD_IND(sc, 10503 (BCE_RXP_SCRATCH + 0x10 + i * 4))); 10504 10505 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10506 10507 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 10508 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", 10509 val, BCE_RXP_CPU_MODE); 10510 10511 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 10512 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 10513 val, BCE_RXP_CPU_STATE); 10514 10515 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 10516 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", 10517 val, BCE_RXP_CPU_EVENT_MASK); 10518 10519 if (regs) { 10520 BCE_PRINTF( 10521 "----------------------------" 10522 " Register Dump " 10523 "----------------------------\n"); 10524 10525 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 10526 /* Skip the big blank sapces */ 10527 if (i < 0xc5400 && i > 0xdffff) 10528 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 10529 "0x%08X 0x%08X\n", i, 10530 REG_RD_IND(sc, i), 10531 REG_RD_IND(sc, i + 0x4), 10532 REG_RD_IND(sc, i + 0x8), 10533 REG_RD_IND(sc, i + 0xC)); 10534 } 10535 } 10536 10537 BCE_PRINTF( 10538 "----------------------------" 10539 "----------------" 10540 "----------------------------\n"); 10541 } 10542 10543 10544 /****************************************************************************/ 10545 /* Prints out the TPAT processor state. */ 10546 /* */ 10547 /* Returns: */ 10548 /* Nothing. */ 10549 /****************************************************************************/ 10550 static __attribute__ ((noinline)) void 10551 bce_dump_tpat_state(struct bce_softc *sc, int regs) 10552 { 10553 u32 val; 10554 u32 fw_version[3]; 10555 10556 BCE_PRINTF( 10557 "----------------------------" 10558 " TPAT State " 10559 "----------------------------\n"); 10560 10561 for (int i = 0; i < 3; i++) 10562 fw_version[i] = htonl(REG_RD_IND(sc, 10563 (BCE_TPAT_SCRATCH + 0x410 + i * 4))); 10564 10565 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10566 10567 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 10568 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", 10569 val, BCE_TPAT_CPU_MODE); 10570 10571 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 10572 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 10573 val, BCE_TPAT_CPU_STATE); 10574 10575 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 10576 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", 10577 val, BCE_TPAT_CPU_EVENT_MASK); 10578 10579 if (regs) { 10580 BCE_PRINTF( 10581 "----------------------------" 10582 " Register Dump " 10583 "----------------------------\n"); 10584 10585 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 10586 /* Skip the big blank spaces */ 10587 if (i < 0x854000 && i > 0x9ffff) 10588 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 10589 "0x%08X 0x%08X\n", i, 10590 REG_RD_IND(sc, i), 10591 REG_RD_IND(sc, i + 0x4), 10592 REG_RD_IND(sc, i + 0x8), 10593 REG_RD_IND(sc, i + 0xC)); 10594 } 10595 } 10596 10597 BCE_PRINTF( 10598 "----------------------------" 10599 "----------------" 10600 "----------------------------\n"); 10601 } 10602 10603 10604 /****************************************************************************/ 10605 /* Prints out the Command Procesor (CP) state. */ 10606 /* */ 10607 /* Returns: */ 10608 /* Nothing. */ 10609 /****************************************************************************/ 10610 static __attribute__ ((noinline)) void 10611 bce_dump_cp_state(struct bce_softc *sc, int regs) 10612 { 10613 u32 val; 10614 u32 fw_version[3]; 10615 10616 BCE_PRINTF( 10617 "----------------------------" 10618 " CP State " 10619 "----------------------------\n"); 10620 10621 for (int i = 0; i < 3; i++) 10622 fw_version[i] = htonl(REG_RD_IND(sc, 10623 (BCE_CP_SCRATCH + 0x10 + i * 4))); 10624 10625 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10626 10627 val = REG_RD_IND(sc, BCE_CP_CPU_MODE); 10628 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", 10629 val, BCE_CP_CPU_MODE); 10630 10631 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 10632 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 10633 val, BCE_CP_CPU_STATE); 10634 10635 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK); 10636 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val, 10637 BCE_CP_CPU_EVENT_MASK); 10638 10639 if (regs) { 10640 BCE_PRINTF( 10641 "----------------------------" 10642 " Register Dump " 10643 "----------------------------\n"); 10644 10645 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) { 10646 /* Skip the big blank spaces */ 10647 if (i < 0x185400 && i > 0x19ffff) 10648 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 10649 "0x%08X 0x%08X\n", i, 10650 REG_RD_IND(sc, i), 10651 REG_RD_IND(sc, i + 0x4), 10652 REG_RD_IND(sc, i + 0x8), 10653 REG_RD_IND(sc, i + 0xC)); 10654 } 10655 } 10656 10657 BCE_PRINTF( 10658 "----------------------------" 10659 "----------------" 10660 "----------------------------\n"); 10661 } 10662 10663 10664 /****************************************************************************/ 10665 /* Prints out the Completion Procesor (COM) state. */ 10666 /* */ 10667 /* Returns: */ 10668 /* Nothing. */ 10669 /****************************************************************************/ 10670 static __attribute__ ((noinline)) void 10671 bce_dump_com_state(struct bce_softc *sc, int regs) 10672 { 10673 u32 val; 10674 u32 fw_version[4]; 10675 10676 BCE_PRINTF( 10677 "----------------------------" 10678 " COM State " 10679 "----------------------------\n"); 10680 10681 for (int i = 0; i < 3; i++) 10682 fw_version[i] = htonl(REG_RD_IND(sc, 10683 (BCE_COM_SCRATCH + 0x10 + i * 4))); 10684 10685 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10686 10687 val = REG_RD_IND(sc, BCE_COM_CPU_MODE); 10688 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", 10689 val, BCE_COM_CPU_MODE); 10690 10691 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 10692 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 10693 val, BCE_COM_CPU_STATE); 10694 10695 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK); 10696 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val, 10697 BCE_COM_CPU_EVENT_MASK); 10698 10699 if (regs) { 10700 BCE_PRINTF( 10701 "----------------------------" 10702 " Register Dump " 10703 "----------------------------\n"); 10704 10705 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) { 10706 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 10707 "0x%08X 0x%08X\n", i, 10708 REG_RD_IND(sc, i), 10709 REG_RD_IND(sc, i + 0x4), 10710 REG_RD_IND(sc, i + 0x8), 10711 REG_RD_IND(sc, i + 0xC)); 10712 } 10713 } 10714 10715 BCE_PRINTF( 10716 "----------------------------" 10717 "----------------" 10718 "----------------------------\n"); 10719 } 10720 10721 10722 /****************************************************************************/ 10723 /* Prints out the Receive Virtual 2 Physical (RV2P) state. */ 10724 /* */ 10725 /* Returns: */ 10726 /* Nothing. */ 10727 /****************************************************************************/ 10728 static __attribute__ ((noinline)) void 10729 bce_dump_rv2p_state(struct bce_softc *sc) 10730 { 10731 u32 val, pc1, pc2, fw_ver_high, fw_ver_low; 10732 10733 BCE_PRINTF( 10734 "----------------------------" 10735 " RV2P State " 10736 "----------------------------\n"); 10737 10738 /* Stall the RV2P processors. */ 10739 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 10740 val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2; 10741 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 10742 10743 /* Read the firmware version. */ 10744 val = 0x00000001; 10745 REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 10746 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 10747 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 10748 BCE_RV2P_INSTR_HIGH_HIGH; 10749 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n", 10750 fw_ver_high, fw_ver_low); 10751 10752 val = 0x00000001; 10753 REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 10754 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 10755 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 10756 BCE_RV2P_INSTR_HIGH_HIGH; 10757 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n", 10758 fw_ver_high, fw_ver_low); 10759 10760 /* Resume the RV2P processors. */ 10761 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 10762 val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2); 10763 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 10764 10765 /* Fetch the program counter value. */ 10766 val = 0x68007800; 10767 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 10768 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 10769 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 10770 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 10771 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1); 10772 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2); 10773 10774 /* Fetch the program counter value again to see if it is advancing. */ 10775 val = 0x68007800; 10776 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 10777 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 10778 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 10779 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 10780 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1); 10781 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2); 10782 10783 BCE_PRINTF( 10784 "----------------------------" 10785 "----------------" 10786 "----------------------------\n"); 10787 } 10788 10789 10790 /****************************************************************************/ 10791 /* Prints out the driver state and then enters the debugger. */ 10792 /* */ 10793 /* Returns: */ 10794 /* Nothing. */ 10795 /****************************************************************************/ 10796 static __attribute__ ((noinline)) void 10797 bce_breakpoint(struct bce_softc *sc) 10798 { 10799 10800 /* 10801 * Unreachable code to silence compiler warnings 10802 * about unused functions. 10803 */ 10804 if (0) { 10805 bce_freeze_controller(sc); 10806 bce_unfreeze_controller(sc); 10807 bce_dump_enet(sc, NULL); 10808 bce_dump_txbd(sc, 0, NULL); 10809 bce_dump_rxbd(sc, 0, NULL); 10810 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 10811 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD); 10812 bce_dump_l2fhdr(sc, 0, NULL); 10813 bce_dump_ctx(sc, RX_CID); 10814 bce_dump_ftqs(sc); 10815 bce_dump_tx_chain(sc, 0, USABLE_TX_BD); 10816 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD); 10817 bce_dump_status_block(sc); 10818 bce_dump_stats_block(sc); 10819 bce_dump_driver_state(sc); 10820 bce_dump_hw_state(sc); 10821 bce_dump_bc_state(sc); 10822 bce_dump_txp_state(sc, 0); 10823 bce_dump_rxp_state(sc, 0); 10824 bce_dump_tpat_state(sc, 0); 10825 bce_dump_cp_state(sc, 0); 10826 bce_dump_com_state(sc, 0); 10827 bce_dump_rv2p_state(sc); 10828 10829 #ifdef BCE_JUMBO_HDRSPLIT 10830 bce_dump_pgbd(sc, 0, NULL); 10831 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD); 10832 bce_dump_pg_chain(sc, 0, USABLE_PG_BD); 10833 #endif 10834 } 10835 10836 bce_dump_status_block(sc); 10837 bce_dump_driver_state(sc); 10838 10839 /* Call the debugger. */ 10840 breakpoint(); 10841 10842 return; 10843 } 10844 #endif 10845
Cache object: 0f69c471cac37c7a7ed4fd039148db41
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