FreeBSD/Linux Kernel Cross Reference
sys/dev/bfe/if_bfe.c
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
5 * and Duncan Barclay<dmlb@dmlb.org>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/endian.h>
36 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/mbuf.h>
39 #include <sys/module.h>
40 #include <sys/rman.h>
41 #include <sys/socket.h>
42 #include <sys/sockio.h>
43 #include <sys/sysctl.h>
44
45 #include <net/bpf.h>
46 #include <net/if.h>
47 #include <net/if_var.h>
48 #include <net/ethernet.h>
49 #include <net/if_dl.h>
50 #include <net/if_media.h>
51 #include <net/if_types.h>
52 #include <net/if_vlan_var.h>
53
54 #include <dev/mii/mii.h>
55 #include <dev/mii/miivar.h>
56
57 #include <dev/pci/pcireg.h>
58 #include <dev/pci/pcivar.h>
59
60 #include <machine/bus.h>
61
62 #include <dev/bfe/if_bfereg.h>
63
64 MODULE_DEPEND(bfe, pci, 1, 1, 1);
65 MODULE_DEPEND(bfe, ether, 1, 1, 1);
66 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
67
68 /* "device miibus" required. See GENERIC if you get errors here. */
69 #include "miibus_if.h"
70
71 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
72
73 static struct bfe_type bfe_devs[] = {
74 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401,
75 "Broadcom BCM4401 Fast Ethernet" },
76 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0,
77 "Broadcom BCM4401-B0 Fast Ethernet" },
78 { 0, 0, NULL }
79 };
80
81 static int bfe_probe (device_t);
82 static int bfe_attach (device_t);
83 static int bfe_detach (device_t);
84 static int bfe_suspend (device_t);
85 static int bfe_resume (device_t);
86 static void bfe_release_resources (struct bfe_softc *);
87 static void bfe_intr (void *);
88 static int bfe_encap (struct bfe_softc *, struct mbuf **);
89 static void bfe_start (struct ifnet *);
90 static void bfe_start_locked (struct ifnet *);
91 static int bfe_ioctl (struct ifnet *, u_long, caddr_t);
92 static void bfe_init (void *);
93 static void bfe_init_locked (void *);
94 static void bfe_stop (struct bfe_softc *);
95 static void bfe_watchdog (struct bfe_softc *);
96 static int bfe_shutdown (device_t);
97 static void bfe_tick (void *);
98 static void bfe_txeof (struct bfe_softc *);
99 static void bfe_rxeof (struct bfe_softc *);
100 static void bfe_set_rx_mode (struct bfe_softc *);
101 static int bfe_list_rx_init (struct bfe_softc *);
102 static void bfe_list_tx_init (struct bfe_softc *);
103 static void bfe_discard_buf (struct bfe_softc *, int);
104 static int bfe_list_newbuf (struct bfe_softc *, int);
105 static void bfe_rx_ring_free (struct bfe_softc *);
106
107 static void bfe_pci_setup (struct bfe_softc *, u_int32_t);
108 static int bfe_ifmedia_upd (struct ifnet *);
109 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *);
110 static int bfe_miibus_readreg (device_t, int, int);
111 static int bfe_miibus_writereg (device_t, int, int, int);
112 static void bfe_miibus_statchg (device_t);
113 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t,
114 u_long, const int);
115 static void bfe_get_config (struct bfe_softc *sc);
116 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *);
117 static void bfe_stats_update (struct bfe_softc *);
118 static void bfe_clear_stats (struct bfe_softc *);
119 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*);
120 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t);
121 static int bfe_resetphy (struct bfe_softc *);
122 static int bfe_setupphy (struct bfe_softc *);
123 static void bfe_chip_reset (struct bfe_softc *);
124 static void bfe_chip_halt (struct bfe_softc *);
125 static void bfe_core_reset (struct bfe_softc *);
126 static void bfe_core_disable (struct bfe_softc *);
127 static int bfe_dma_alloc (struct bfe_softc *);
128 static void bfe_dma_free (struct bfe_softc *sc);
129 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int);
130 static void bfe_cam_write (struct bfe_softc *, u_char *, int);
131 static int sysctl_bfe_stats (SYSCTL_HANDLER_ARGS);
132
133 static device_method_t bfe_methods[] = {
134 /* Device interface */
135 DEVMETHOD(device_probe, bfe_probe),
136 DEVMETHOD(device_attach, bfe_attach),
137 DEVMETHOD(device_detach, bfe_detach),
138 DEVMETHOD(device_shutdown, bfe_shutdown),
139 DEVMETHOD(device_suspend, bfe_suspend),
140 DEVMETHOD(device_resume, bfe_resume),
141
142 /* MII interface */
143 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
144 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
145 DEVMETHOD(miibus_statchg, bfe_miibus_statchg),
146
147 DEVMETHOD_END
148 };
149
150 static driver_t bfe_driver = {
151 "bfe",
152 bfe_methods,
153 sizeof(struct bfe_softc)
154 };
155
156 DRIVER_MODULE(bfe, pci, bfe_driver, 0, 0);
157 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, bfe, bfe_devs,
158 nitems(bfe_devs) - 1);
159 DRIVER_MODULE(miibus, bfe, miibus_driver, 0, 0);
160
161 /*
162 * Probe for a Broadcom 4401 chip.
163 */
164 static int
165 bfe_probe(device_t dev)
166 {
167 struct bfe_type *t;
168
169 t = bfe_devs;
170
171 while (t->bfe_name != NULL) {
172 if (pci_get_vendor(dev) == t->bfe_vid &&
173 pci_get_device(dev) == t->bfe_did) {
174 device_set_desc(dev, t->bfe_name);
175 return (BUS_PROBE_DEFAULT);
176 }
177 t++;
178 }
179
180 return (ENXIO);
181 }
182
183 struct bfe_dmamap_arg {
184 bus_addr_t bfe_busaddr;
185 };
186
187 static int
188 bfe_dma_alloc(struct bfe_softc *sc)
189 {
190 struct bfe_dmamap_arg ctx;
191 struct bfe_rx_data *rd;
192 struct bfe_tx_data *td;
193 int error, i;
194
195 /*
196 * parent tag. Apparently the chip cannot handle any DMA address
197 * greater than 1GB.
198 */
199 error = bus_dma_tag_create(bus_get_dma_tag(sc->bfe_dev), /* parent */
200 1, 0, /* alignment, boundary */
201 BFE_DMA_MAXADDR, /* lowaddr */
202 BUS_SPACE_MAXADDR, /* highaddr */
203 NULL, NULL, /* filter, filterarg */
204 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
205 0, /* nsegments */
206 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
207 0, /* flags */
208 NULL, NULL, /* lockfunc, lockarg */
209 &sc->bfe_parent_tag);
210 if (error != 0) {
211 device_printf(sc->bfe_dev, "cannot create parent DMA tag.\n");
212 goto fail;
213 }
214
215 /* Create tag for Tx ring. */
216 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
217 BFE_TX_RING_ALIGN, 0, /* alignment, boundary */
218 BUS_SPACE_MAXADDR, /* lowaddr */
219 BUS_SPACE_MAXADDR, /* highaddr */
220 NULL, NULL, /* filter, filterarg */
221 BFE_TX_LIST_SIZE, /* maxsize */
222 1, /* nsegments */
223 BFE_TX_LIST_SIZE, /* maxsegsize */
224 0, /* flags */
225 NULL, NULL, /* lockfunc, lockarg */
226 &sc->bfe_tx_tag);
227 if (error != 0) {
228 device_printf(sc->bfe_dev, "cannot create Tx ring DMA tag.\n");
229 goto fail;
230 }
231
232 /* Create tag for Rx ring. */
233 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
234 BFE_RX_RING_ALIGN, 0, /* alignment, boundary */
235 BUS_SPACE_MAXADDR, /* lowaddr */
236 BUS_SPACE_MAXADDR, /* highaddr */
237 NULL, NULL, /* filter, filterarg */
238 BFE_RX_LIST_SIZE, /* maxsize */
239 1, /* nsegments */
240 BFE_RX_LIST_SIZE, /* maxsegsize */
241 0, /* flags */
242 NULL, NULL, /* lockfunc, lockarg */
243 &sc->bfe_rx_tag);
244 if (error != 0) {
245 device_printf(sc->bfe_dev, "cannot create Rx ring DMA tag.\n");
246 goto fail;
247 }
248
249 /* Create tag for Tx buffers. */
250 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
251 1, 0, /* alignment, boundary */
252 BUS_SPACE_MAXADDR, /* lowaddr */
253 BUS_SPACE_MAXADDR, /* highaddr */
254 NULL, NULL, /* filter, filterarg */
255 MCLBYTES * BFE_MAXTXSEGS, /* maxsize */
256 BFE_MAXTXSEGS, /* nsegments */
257 MCLBYTES, /* maxsegsize */
258 0, /* flags */
259 NULL, NULL, /* lockfunc, lockarg */
260 &sc->bfe_txmbuf_tag);
261 if (error != 0) {
262 device_printf(sc->bfe_dev,
263 "cannot create Tx buffer DMA tag.\n");
264 goto fail;
265 }
266
267 /* Create tag for Rx buffers. */
268 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
269 1, 0, /* alignment, boundary */
270 BUS_SPACE_MAXADDR, /* lowaddr */
271 BUS_SPACE_MAXADDR, /* highaddr */
272 NULL, NULL, /* filter, filterarg */
273 MCLBYTES, /* maxsize */
274 1, /* nsegments */
275 MCLBYTES, /* maxsegsize */
276 0, /* flags */
277 NULL, NULL, /* lockfunc, lockarg */
278 &sc->bfe_rxmbuf_tag);
279 if (error != 0) {
280 device_printf(sc->bfe_dev,
281 "cannot create Rx buffer DMA tag.\n");
282 goto fail;
283 }
284
285 /* Allocate DMA'able memory and load DMA map. */
286 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
287 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_tx_map);
288 if (error != 0) {
289 device_printf(sc->bfe_dev,
290 "cannot allocate DMA'able memory for Tx ring.\n");
291 goto fail;
292 }
293 ctx.bfe_busaddr = 0;
294 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
295 sc->bfe_tx_list, BFE_TX_LIST_SIZE, bfe_dma_map, &ctx,
296 BUS_DMA_NOWAIT);
297 if (error != 0 || ctx.bfe_busaddr == 0) {
298 device_printf(sc->bfe_dev,
299 "cannot load DMA'able memory for Tx ring.\n");
300 goto fail;
301 }
302 sc->bfe_tx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
303
304 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
305 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_rx_map);
306 if (error != 0) {
307 device_printf(sc->bfe_dev,
308 "cannot allocate DMA'able memory for Rx ring.\n");
309 goto fail;
310 }
311 ctx.bfe_busaddr = 0;
312 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
313 sc->bfe_rx_list, BFE_RX_LIST_SIZE, bfe_dma_map, &ctx,
314 BUS_DMA_NOWAIT);
315 if (error != 0 || ctx.bfe_busaddr == 0) {
316 device_printf(sc->bfe_dev,
317 "cannot load DMA'able memory for Rx ring.\n");
318 goto fail;
319 }
320 sc->bfe_rx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
321
322 /* Create DMA maps for Tx buffers. */
323 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
324 td = &sc->bfe_tx_ring[i];
325 td->bfe_mbuf = NULL;
326 td->bfe_map = NULL;
327 error = bus_dmamap_create(sc->bfe_txmbuf_tag, 0, &td->bfe_map);
328 if (error != 0) {
329 device_printf(sc->bfe_dev,
330 "cannot create DMA map for Tx.\n");
331 goto fail;
332 }
333 }
334
335 /* Create spare DMA map for Rx buffers. */
336 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &sc->bfe_rx_sparemap);
337 if (error != 0) {
338 device_printf(sc->bfe_dev, "cannot create spare DMA map for Rx.\n");
339 goto fail;
340 }
341 /* Create DMA maps for Rx buffers. */
342 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
343 rd = &sc->bfe_rx_ring[i];
344 rd->bfe_mbuf = NULL;
345 rd->bfe_map = NULL;
346 rd->bfe_ctrl = 0;
347 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &rd->bfe_map);
348 if (error != 0) {
349 device_printf(sc->bfe_dev,
350 "cannot create DMA map for Rx.\n");
351 goto fail;
352 }
353 }
354
355 fail:
356 return (error);
357 }
358
359 static void
360 bfe_dma_free(struct bfe_softc *sc)
361 {
362 struct bfe_tx_data *td;
363 struct bfe_rx_data *rd;
364 int i;
365
366 /* Tx ring. */
367 if (sc->bfe_tx_tag != NULL) {
368 if (sc->bfe_tx_dma != 0)
369 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
370 if (sc->bfe_tx_list != NULL)
371 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
372 sc->bfe_tx_map);
373 sc->bfe_tx_dma = 0;
374 sc->bfe_tx_list = NULL;
375 bus_dma_tag_destroy(sc->bfe_tx_tag);
376 sc->bfe_tx_tag = NULL;
377 }
378
379 /* Rx ring. */
380 if (sc->bfe_rx_tag != NULL) {
381 if (sc->bfe_rx_dma != 0)
382 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
383 if (sc->bfe_rx_list != NULL)
384 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
385 sc->bfe_rx_map);
386 sc->bfe_rx_dma = 0;
387 sc->bfe_rx_list = NULL;
388 bus_dma_tag_destroy(sc->bfe_rx_tag);
389 sc->bfe_rx_tag = NULL;
390 }
391
392 /* Tx buffers. */
393 if (sc->bfe_txmbuf_tag != NULL) {
394 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
395 td = &sc->bfe_tx_ring[i];
396 if (td->bfe_map != NULL) {
397 bus_dmamap_destroy(sc->bfe_txmbuf_tag,
398 td->bfe_map);
399 td->bfe_map = NULL;
400 }
401 }
402 bus_dma_tag_destroy(sc->bfe_txmbuf_tag);
403 sc->bfe_txmbuf_tag = NULL;
404 }
405
406 /* Rx buffers. */
407 if (sc->bfe_rxmbuf_tag != NULL) {
408 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
409 rd = &sc->bfe_rx_ring[i];
410 if (rd->bfe_map != NULL) {
411 bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
412 rd->bfe_map);
413 rd->bfe_map = NULL;
414 }
415 }
416 if (sc->bfe_rx_sparemap != NULL) {
417 bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
418 sc->bfe_rx_sparemap);
419 sc->bfe_rx_sparemap = NULL;
420 }
421 bus_dma_tag_destroy(sc->bfe_rxmbuf_tag);
422 sc->bfe_rxmbuf_tag = NULL;
423 }
424
425 if (sc->bfe_parent_tag != NULL) {
426 bus_dma_tag_destroy(sc->bfe_parent_tag);
427 sc->bfe_parent_tag = NULL;
428 }
429 }
430
431 static int
432 bfe_attach(device_t dev)
433 {
434 struct ifnet *ifp = NULL;
435 struct bfe_softc *sc;
436 int error = 0, rid;
437
438 sc = device_get_softc(dev);
439 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
440 MTX_DEF);
441 callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0);
442
443 sc->bfe_dev = dev;
444
445 /*
446 * Map control/status registers.
447 */
448 pci_enable_busmaster(dev);
449
450 rid = PCIR_BAR(0);
451 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
452 RF_ACTIVE);
453 if (sc->bfe_res == NULL) {
454 device_printf(dev, "couldn't map memory\n");
455 error = ENXIO;
456 goto fail;
457 }
458
459 /* Allocate interrupt */
460 rid = 0;
461
462 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
463 RF_SHAREABLE | RF_ACTIVE);
464 if (sc->bfe_irq == NULL) {
465 device_printf(dev, "couldn't map interrupt\n");
466 error = ENXIO;
467 goto fail;
468 }
469
470 if (bfe_dma_alloc(sc) != 0) {
471 device_printf(dev, "failed to allocate DMA resources\n");
472 error = ENXIO;
473 goto fail;
474 }
475
476 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
477 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
478 "stats", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
479 sysctl_bfe_stats, "I", "Statistics");
480
481 /* Set up ifnet structure */
482 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER);
483 if (ifp == NULL) {
484 device_printf(dev, "failed to if_alloc()\n");
485 error = ENOSPC;
486 goto fail;
487 }
488 ifp->if_softc = sc;
489 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
490 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
491 ifp->if_ioctl = bfe_ioctl;
492 ifp->if_start = bfe_start;
493 ifp->if_init = bfe_init;
494 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN);
495 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN;
496 IFQ_SET_READY(&ifp->if_snd);
497
498 bfe_get_config(sc);
499
500 /* Reset the chip and turn on the PHY */
501 BFE_LOCK(sc);
502 bfe_chip_reset(sc);
503 BFE_UNLOCK(sc);
504
505 error = mii_attach(dev, &sc->bfe_miibus, ifp, bfe_ifmedia_upd,
506 bfe_ifmedia_sts, BMSR_DEFCAPMASK, sc->bfe_phyaddr, MII_OFFSET_ANY,
507 0);
508 if (error != 0) {
509 device_printf(dev, "attaching PHYs failed\n");
510 goto fail;
511 }
512
513 ether_ifattach(ifp, sc->bfe_enaddr);
514
515 /*
516 * Tell the upper layer(s) we support long frames.
517 */
518 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
519 ifp->if_capabilities |= IFCAP_VLAN_MTU;
520 ifp->if_capenable |= IFCAP_VLAN_MTU;
521
522 /*
523 * Hook interrupt last to avoid having to lock softc
524 */
525 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE,
526 NULL, bfe_intr, sc, &sc->bfe_intrhand);
527
528 if (error) {
529 device_printf(dev, "couldn't set up irq\n");
530 goto fail;
531 }
532 fail:
533 if (error != 0)
534 bfe_detach(dev);
535 return (error);
536 }
537
538 static int
539 bfe_detach(device_t dev)
540 {
541 struct bfe_softc *sc;
542 struct ifnet *ifp;
543
544 sc = device_get_softc(dev);
545
546 ifp = sc->bfe_ifp;
547
548 if (device_is_attached(dev)) {
549 BFE_LOCK(sc);
550 sc->bfe_flags |= BFE_FLAG_DETACH;
551 bfe_stop(sc);
552 BFE_UNLOCK(sc);
553 callout_drain(&sc->bfe_stat_co);
554 if (ifp != NULL)
555 ether_ifdetach(ifp);
556 }
557
558 BFE_LOCK(sc);
559 bfe_chip_reset(sc);
560 BFE_UNLOCK(sc);
561
562 bus_generic_detach(dev);
563 if (sc->bfe_miibus != NULL)
564 device_delete_child(dev, sc->bfe_miibus);
565
566 bfe_release_resources(sc);
567 bfe_dma_free(sc);
568 mtx_destroy(&sc->bfe_mtx);
569
570 return (0);
571 }
572
573 /*
574 * Stop all chip I/O so that the kernel's probe routines don't
575 * get confused by errant DMAs when rebooting.
576 */
577 static int
578 bfe_shutdown(device_t dev)
579 {
580 struct bfe_softc *sc;
581
582 sc = device_get_softc(dev);
583 BFE_LOCK(sc);
584 bfe_stop(sc);
585
586 BFE_UNLOCK(sc);
587
588 return (0);
589 }
590
591 static int
592 bfe_suspend(device_t dev)
593 {
594 struct bfe_softc *sc;
595
596 sc = device_get_softc(dev);
597 BFE_LOCK(sc);
598 bfe_stop(sc);
599 BFE_UNLOCK(sc);
600
601 return (0);
602 }
603
604 static int
605 bfe_resume(device_t dev)
606 {
607 struct bfe_softc *sc;
608 struct ifnet *ifp;
609
610 sc = device_get_softc(dev);
611 ifp = sc->bfe_ifp;
612 BFE_LOCK(sc);
613 bfe_chip_reset(sc);
614 if (ifp->if_flags & IFF_UP) {
615 bfe_init_locked(sc);
616 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
617 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
618 bfe_start_locked(ifp);
619 }
620 BFE_UNLOCK(sc);
621
622 return (0);
623 }
624
625 static int
626 bfe_miibus_readreg(device_t dev, int phy, int reg)
627 {
628 struct bfe_softc *sc;
629 u_int32_t ret;
630
631 sc = device_get_softc(dev);
632 bfe_readphy(sc, reg, &ret);
633
634 return (ret);
635 }
636
637 static int
638 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
639 {
640 struct bfe_softc *sc;
641
642 sc = device_get_softc(dev);
643 bfe_writephy(sc, reg, val);
644
645 return (0);
646 }
647
648 static void
649 bfe_miibus_statchg(device_t dev)
650 {
651 struct bfe_softc *sc;
652 struct mii_data *mii;
653 u_int32_t val;
654 #ifdef notyet
655 u_int32_t flow;
656 #endif
657
658 sc = device_get_softc(dev);
659 mii = device_get_softc(sc->bfe_miibus);
660
661 sc->bfe_flags &= ~BFE_FLAG_LINK;
662 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
663 (IFM_ACTIVE | IFM_AVALID)) {
664 switch (IFM_SUBTYPE(mii->mii_media_active)) {
665 case IFM_10_T:
666 case IFM_100_TX:
667 sc->bfe_flags |= BFE_FLAG_LINK;
668 break;
669 default:
670 break;
671 }
672 }
673
674 /* XXX Should stop Rx/Tx engine prior to touching MAC. */
675 val = CSR_READ_4(sc, BFE_TX_CTRL);
676 val &= ~BFE_TX_DUPLEX;
677 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
678 val |= BFE_TX_DUPLEX;
679 #ifdef notyet
680 flow = CSR_READ_4(sc, BFE_RXCONF);
681 flow &= ~BFE_RXCONF_FLOW;
682 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
683 IFM_ETH_RXPAUSE) != 0)
684 flow |= BFE_RXCONF_FLOW;
685 CSR_WRITE_4(sc, BFE_RXCONF, flow);
686 /*
687 * It seems that the hardware has Tx pause issues
688 * so enable only Rx pause.
689 */
690 flow = CSR_READ_4(sc, BFE_MAC_FLOW);
691 flow &= ~BFE_FLOW_PAUSE_ENAB;
692 CSR_WRITE_4(sc, BFE_MAC_FLOW, flow);
693 #endif
694 }
695 CSR_WRITE_4(sc, BFE_TX_CTRL, val);
696 }
697
698 static void
699 bfe_tx_ring_free(struct bfe_softc *sc)
700 {
701 int i;
702
703 for(i = 0; i < BFE_TX_LIST_CNT; i++) {
704 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
705 bus_dmamap_sync(sc->bfe_txmbuf_tag,
706 sc->bfe_tx_ring[i].bfe_map, BUS_DMASYNC_POSTWRITE);
707 bus_dmamap_unload(sc->bfe_txmbuf_tag,
708 sc->bfe_tx_ring[i].bfe_map);
709 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
710 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
711 }
712 }
713 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
714 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
715 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
716 }
717
718 static void
719 bfe_rx_ring_free(struct bfe_softc *sc)
720 {
721 int i;
722
723 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
724 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
725 bus_dmamap_sync(sc->bfe_rxmbuf_tag,
726 sc->bfe_rx_ring[i].bfe_map, BUS_DMASYNC_POSTREAD);
727 bus_dmamap_unload(sc->bfe_rxmbuf_tag,
728 sc->bfe_rx_ring[i].bfe_map);
729 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
730 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
731 }
732 }
733 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
734 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
735 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
736 }
737
738 static int
739 bfe_list_rx_init(struct bfe_softc *sc)
740 {
741 struct bfe_rx_data *rd;
742 int i;
743
744 sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
745 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
746 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
747 rd = &sc->bfe_rx_ring[i];
748 rd->bfe_mbuf = NULL;
749 rd->bfe_ctrl = 0;
750 if (bfe_list_newbuf(sc, i) != 0)
751 return (ENOBUFS);
752 }
753
754 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
755 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
756 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
757
758 return (0);
759 }
760
761 static void
762 bfe_list_tx_init(struct bfe_softc *sc)
763 {
764 int i;
765
766 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
767 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
768 for (i = 0; i < BFE_TX_LIST_CNT; i++)
769 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
770
771 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
772 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
773 }
774
775 static void
776 bfe_discard_buf(struct bfe_softc *sc, int c)
777 {
778 struct bfe_rx_data *r;
779 struct bfe_desc *d;
780
781 r = &sc->bfe_rx_ring[c];
782 d = &sc->bfe_rx_list[c];
783 d->bfe_ctrl = htole32(r->bfe_ctrl);
784 }
785
786 static int
787 bfe_list_newbuf(struct bfe_softc *sc, int c)
788 {
789 struct bfe_rxheader *rx_header;
790 struct bfe_desc *d;
791 struct bfe_rx_data *r;
792 struct mbuf *m;
793 bus_dma_segment_t segs[1];
794 bus_dmamap_t map;
795 u_int32_t ctrl;
796 int nsegs;
797
798 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
799 if (m == NULL)
800 return (ENOBUFS);
801 m->m_len = m->m_pkthdr.len = MCLBYTES;
802
803 if (bus_dmamap_load_mbuf_sg(sc->bfe_rxmbuf_tag, sc->bfe_rx_sparemap,
804 m, segs, &nsegs, 0) != 0) {
805 m_freem(m);
806 return (ENOBUFS);
807 }
808
809 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
810 r = &sc->bfe_rx_ring[c];
811 if (r->bfe_mbuf != NULL) {
812 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map,
813 BUS_DMASYNC_POSTREAD);
814 bus_dmamap_unload(sc->bfe_rxmbuf_tag, r->bfe_map);
815 }
816 map = r->bfe_map;
817 r->bfe_map = sc->bfe_rx_sparemap;
818 sc->bfe_rx_sparemap = map;
819 r->bfe_mbuf = m;
820
821 rx_header = mtod(m, struct bfe_rxheader *);
822 rx_header->len = 0;
823 rx_header->flags = 0;
824 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, BUS_DMASYNC_PREREAD);
825
826 ctrl = segs[0].ds_len & BFE_DESC_LEN;
827 KASSERT(ctrl > ETHER_MAX_LEN + 32, ("%s: buffer size too small(%d)!",
828 __func__, ctrl));
829 if (c == BFE_RX_LIST_CNT - 1)
830 ctrl |= BFE_DESC_EOT;
831 r->bfe_ctrl = ctrl;
832
833 d = &sc->bfe_rx_list[c];
834 d->bfe_ctrl = htole32(ctrl);
835 /* The chip needs all addresses to be added to BFE_PCI_DMA. */
836 d->bfe_addr = htole32(BFE_ADDR_LO(segs[0].ds_addr) + BFE_PCI_DMA);
837
838 return (0);
839 }
840
841 static void
842 bfe_get_config(struct bfe_softc *sc)
843 {
844 u_int8_t eeprom[128];
845
846 bfe_read_eeprom(sc, eeprom);
847
848 sc->bfe_enaddr[0] = eeprom[79];
849 sc->bfe_enaddr[1] = eeprom[78];
850 sc->bfe_enaddr[2] = eeprom[81];
851 sc->bfe_enaddr[3] = eeprom[80];
852 sc->bfe_enaddr[4] = eeprom[83];
853 sc->bfe_enaddr[5] = eeprom[82];
854
855 sc->bfe_phyaddr = eeprom[90] & 0x1f;
856 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
857
858 sc->bfe_core_unit = 0;
859 sc->bfe_dma_offset = BFE_PCI_DMA;
860 }
861
862 static void
863 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores)
864 {
865 u_int32_t bar_orig, val;
866
867 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
868 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
869
870 val = CSR_READ_4(sc, BFE_SBINTVEC);
871 val |= cores;
872 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
873
874 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
875 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
876 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
877
878 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
879 }
880
881 static void
882 bfe_clear_stats(struct bfe_softc *sc)
883 {
884 uint32_t reg;
885
886 BFE_LOCK_ASSERT(sc);
887
888 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
889 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
890 CSR_READ_4(sc, reg);
891 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
892 CSR_READ_4(sc, reg);
893 }
894
895 static int
896 bfe_resetphy(struct bfe_softc *sc)
897 {
898 u_int32_t val;
899
900 bfe_writephy(sc, 0, BMCR_RESET);
901 DELAY(100);
902 bfe_readphy(sc, 0, &val);
903 if (val & BMCR_RESET) {
904 device_printf(sc->bfe_dev, "PHY Reset would not complete.\n");
905 return (ENXIO);
906 }
907 return (0);
908 }
909
910 static void
911 bfe_chip_halt(struct bfe_softc *sc)
912 {
913 BFE_LOCK_ASSERT(sc);
914 /* disable interrupts - not that it actually does..*/
915 CSR_WRITE_4(sc, BFE_IMASK, 0);
916 CSR_READ_4(sc, BFE_IMASK);
917
918 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
919 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
920
921 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
922 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
923 DELAY(10);
924 }
925
926 static void
927 bfe_chip_reset(struct bfe_softc *sc)
928 {
929 u_int32_t val;
930
931 BFE_LOCK_ASSERT(sc);
932
933 /* Set the interrupt vector for the enet core */
934 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
935
936 /* is core up? */
937 val = CSR_READ_4(sc, BFE_SBTMSLOW) &
938 (BFE_RESET | BFE_REJECT | BFE_CLOCK);
939 if (val == BFE_CLOCK) {
940 /* It is, so shut it down */
941 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
942 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
943 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
944 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
945 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
946 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE,
947 100, 0);
948 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
949 }
950
951 bfe_core_reset(sc);
952 bfe_clear_stats(sc);
953
954 /*
955 * We want the phy registers to be accessible even when
956 * the driver is "downed" so initialize MDC preamble, frequency,
957 * and whether internal or external phy here.
958 */
959
960 /* 4402 has 62.5Mhz SB clock and internal phy */
961 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
962
963 /* Internal or external PHY? */
964 val = CSR_READ_4(sc, BFE_DEVCTRL);
965 if (!(val & BFE_IPP))
966 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
967 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
968 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
969 DELAY(100);
970 }
971
972 /* Enable CRC32 generation and set proper LED modes */
973 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
974
975 /* Reset or clear powerdown control bit */
976 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
977
978 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
979 BFE_LAZY_FC_MASK));
980
981 /*
982 * We don't want lazy interrupts, so just send them at
983 * the end of a frame, please
984 */
985 BFE_OR(sc, BFE_RCV_LAZY, 0);
986
987 /* Set max lengths, accounting for VLAN tags */
988 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
989 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
990
991 /* Set watermark XXX - magic */
992 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
993
994 /*
995 * Initialise DMA channels
996 * - not forgetting dma addresses need to be added to BFE_PCI_DMA
997 */
998 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
999 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
1000
1001 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
1002 BFE_RX_CTRL_ENABLE);
1003 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
1004
1005 bfe_resetphy(sc);
1006 bfe_setupphy(sc);
1007 }
1008
1009 static void
1010 bfe_core_disable(struct bfe_softc *sc)
1011 {
1012 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
1013 return;
1014
1015 /*
1016 * Set reject, wait for it set, then wait for the core to stop
1017 * being busy, then set reset and reject and enable the clocks.
1018 */
1019 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
1020 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
1021 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
1022 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
1023 BFE_RESET));
1024 CSR_READ_4(sc, BFE_SBTMSLOW);
1025 DELAY(10);
1026 /* Leave reset and reject set */
1027 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
1028 DELAY(10);
1029 }
1030
1031 static void
1032 bfe_core_reset(struct bfe_softc *sc)
1033 {
1034 u_int32_t val;
1035
1036 /* Disable the core */
1037 bfe_core_disable(sc);
1038
1039 /* and bring it back up */
1040 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
1041 CSR_READ_4(sc, BFE_SBTMSLOW);
1042 DELAY(10);
1043
1044 /* Chip bug, clear SERR, IB and TO if they are set. */
1045 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
1046 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
1047 val = CSR_READ_4(sc, BFE_SBIMSTATE);
1048 if (val & (BFE_IBE | BFE_TO))
1049 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
1050
1051 /* Clear reset and allow it to move through the core */
1052 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
1053 CSR_READ_4(sc, BFE_SBTMSLOW);
1054 DELAY(10);
1055
1056 /* Leave the clock set */
1057 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
1058 CSR_READ_4(sc, BFE_SBTMSLOW);
1059 DELAY(10);
1060 }
1061
1062 static void
1063 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
1064 {
1065 u_int32_t val;
1066
1067 val = ((u_int32_t) data[2]) << 24;
1068 val |= ((u_int32_t) data[3]) << 16;
1069 val |= ((u_int32_t) data[4]) << 8;
1070 val |= ((u_int32_t) data[5]);
1071 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
1072 val = (BFE_CAM_HI_VALID |
1073 (((u_int32_t) data[0]) << 8) |
1074 (((u_int32_t) data[1])));
1075 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
1076 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
1077 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT)));
1078 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
1079 }
1080
1081 static u_int
1082 bfe_write_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1083 {
1084 struct bfe_softc *sc = arg;
1085
1086 bfe_cam_write(sc, LLADDR(sdl), cnt + 1);
1087
1088 return (1);
1089 }
1090
1091 static void
1092 bfe_set_rx_mode(struct bfe_softc *sc)
1093 {
1094 struct ifnet *ifp = sc->bfe_ifp;
1095 u_int32_t val;
1096
1097 BFE_LOCK_ASSERT(sc);
1098
1099 val = CSR_READ_4(sc, BFE_RXCONF);
1100
1101 if (ifp->if_flags & IFF_PROMISC)
1102 val |= BFE_RXCONF_PROMISC;
1103 else
1104 val &= ~BFE_RXCONF_PROMISC;
1105
1106 if (ifp->if_flags & IFF_BROADCAST)
1107 val &= ~BFE_RXCONF_DBCAST;
1108 else
1109 val |= BFE_RXCONF_DBCAST;
1110
1111 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
1112 bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), 0);
1113
1114 if (ifp->if_flags & IFF_ALLMULTI)
1115 val |= BFE_RXCONF_ALLMULTI;
1116 else {
1117 val &= ~BFE_RXCONF_ALLMULTI;
1118 if_foreach_llmaddr(ifp, bfe_write_maddr, sc);
1119 }
1120
1121 CSR_WRITE_4(sc, BFE_RXCONF, val);
1122 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
1123 }
1124
1125 static void
1126 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1127 {
1128 struct bfe_dmamap_arg *ctx;
1129
1130 if (error != 0)
1131 return;
1132
1133 KASSERT(nseg == 1, ("%s : %d segments returned!", __func__, nseg));
1134
1135 ctx = (struct bfe_dmamap_arg *)arg;
1136 ctx->bfe_busaddr = segs[0].ds_addr;
1137 }
1138
1139 static void
1140 bfe_release_resources(struct bfe_softc *sc)
1141 {
1142
1143 if (sc->bfe_intrhand != NULL)
1144 bus_teardown_intr(sc->bfe_dev, sc->bfe_irq, sc->bfe_intrhand);
1145
1146 if (sc->bfe_irq != NULL)
1147 bus_release_resource(sc->bfe_dev, SYS_RES_IRQ, 0, sc->bfe_irq);
1148
1149 if (sc->bfe_res != NULL)
1150 bus_release_resource(sc->bfe_dev, SYS_RES_MEMORY, PCIR_BAR(0),
1151 sc->bfe_res);
1152
1153 if (sc->bfe_ifp != NULL)
1154 if_free(sc->bfe_ifp);
1155 }
1156
1157 static void
1158 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data)
1159 {
1160 long i;
1161 u_int16_t *ptr = (u_int16_t *)data;
1162
1163 for(i = 0; i < 128; i += 2)
1164 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
1165 }
1166
1167 static int
1168 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit,
1169 u_long timeout, const int clear)
1170 {
1171 u_long i;
1172
1173 for (i = 0; i < timeout; i++) {
1174 u_int32_t val = CSR_READ_4(sc, reg);
1175
1176 if (clear && !(val & bit))
1177 break;
1178 if (!clear && (val & bit))
1179 break;
1180 DELAY(10);
1181 }
1182 if (i == timeout) {
1183 device_printf(sc->bfe_dev,
1184 "BUG! Timeout waiting for bit %08x of register "
1185 "%x to %s.\n", bit, reg, (clear ? "clear" : "set"));
1186 return (-1);
1187 }
1188 return (0);
1189 }
1190
1191 static int
1192 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val)
1193 {
1194 int err;
1195
1196 /* Clear MII ISR */
1197 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1198 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1199 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
1200 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1201 (reg << BFE_MDIO_RA_SHIFT) |
1202 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
1203 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1204 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
1205
1206 return (err);
1207 }
1208
1209 static int
1210 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val)
1211 {
1212 int status;
1213
1214 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1215 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1216 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1217 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1218 (reg << BFE_MDIO_RA_SHIFT) |
1219 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1220 (val & BFE_MDIO_DATA_DATA)));
1221 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1222
1223 return (status);
1224 }
1225
1226 /*
1227 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1228 * twice
1229 */
1230 static int
1231 bfe_setupphy(struct bfe_softc *sc)
1232 {
1233 u_int32_t val;
1234
1235 /* Enable activity LED */
1236 bfe_readphy(sc, 26, &val);
1237 bfe_writephy(sc, 26, val & 0x7fff);
1238 bfe_readphy(sc, 26, &val);
1239
1240 /* Enable traffic meter LED mode */
1241 bfe_readphy(sc, 27, &val);
1242 bfe_writephy(sc, 27, val | (1 << 6));
1243
1244 return (0);
1245 }
1246
1247 static void
1248 bfe_stats_update(struct bfe_softc *sc)
1249 {
1250 struct bfe_hw_stats *stats;
1251 struct ifnet *ifp;
1252 uint32_t mib[BFE_MIB_CNT];
1253 uint32_t reg, *val;
1254
1255 BFE_LOCK_ASSERT(sc);
1256
1257 val = mib;
1258 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
1259 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1260 *val++ = CSR_READ_4(sc, reg);
1261 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1262 *val++ = CSR_READ_4(sc, reg);
1263
1264 ifp = sc->bfe_ifp;
1265 stats = &sc->bfe_stats;
1266 /* Tx stat. */
1267 stats->tx_good_octets += mib[MIB_TX_GOOD_O];
1268 stats->tx_good_frames += mib[MIB_TX_GOOD_P];
1269 stats->tx_octets += mib[MIB_TX_O];
1270 stats->tx_frames += mib[MIB_TX_P];
1271 stats->tx_bcast_frames += mib[MIB_TX_BCAST];
1272 stats->tx_mcast_frames += mib[MIB_TX_MCAST];
1273 stats->tx_pkts_64 += mib[MIB_TX_64];
1274 stats->tx_pkts_65_127 += mib[MIB_TX_65_127];
1275 stats->tx_pkts_128_255 += mib[MIB_TX_128_255];
1276 stats->tx_pkts_256_511 += mib[MIB_TX_256_511];
1277 stats->tx_pkts_512_1023 += mib[MIB_TX_512_1023];
1278 stats->tx_pkts_1024_max += mib[MIB_TX_1024_MAX];
1279 stats->tx_jabbers += mib[MIB_TX_JABBER];
1280 stats->tx_oversize_frames += mib[MIB_TX_OSIZE];
1281 stats->tx_frag_frames += mib[MIB_TX_FRAG];
1282 stats->tx_underruns += mib[MIB_TX_URUNS];
1283 stats->tx_colls += mib[MIB_TX_TCOLS];
1284 stats->tx_single_colls += mib[MIB_TX_SCOLS];
1285 stats->tx_multi_colls += mib[MIB_TX_MCOLS];
1286 stats->tx_excess_colls += mib[MIB_TX_ECOLS];
1287 stats->tx_late_colls += mib[MIB_TX_LCOLS];
1288 stats->tx_deferrals += mib[MIB_TX_DEFERED];
1289 stats->tx_carrier_losts += mib[MIB_TX_CLOST];
1290 stats->tx_pause_frames += mib[MIB_TX_PAUSE];
1291 /* Rx stat. */
1292 stats->rx_good_octets += mib[MIB_RX_GOOD_O];
1293 stats->rx_good_frames += mib[MIB_RX_GOOD_P];
1294 stats->rx_octets += mib[MIB_RX_O];
1295 stats->rx_frames += mib[MIB_RX_P];
1296 stats->rx_bcast_frames += mib[MIB_RX_BCAST];
1297 stats->rx_mcast_frames += mib[MIB_RX_MCAST];
1298 stats->rx_pkts_64 += mib[MIB_RX_64];
1299 stats->rx_pkts_65_127 += mib[MIB_RX_65_127];
1300 stats->rx_pkts_128_255 += mib[MIB_RX_128_255];
1301 stats->rx_pkts_256_511 += mib[MIB_RX_256_511];
1302 stats->rx_pkts_512_1023 += mib[MIB_RX_512_1023];
1303 stats->rx_pkts_1024_max += mib[MIB_RX_1024_MAX];
1304 stats->rx_jabbers += mib[MIB_RX_JABBER];
1305 stats->rx_oversize_frames += mib[MIB_RX_OSIZE];
1306 stats->rx_frag_frames += mib[MIB_RX_FRAG];
1307 stats->rx_missed_frames += mib[MIB_RX_MISS];
1308 stats->rx_crc_align_errs += mib[MIB_RX_CRCA];
1309 stats->rx_runts += mib[MIB_RX_USIZE];
1310 stats->rx_crc_errs += mib[MIB_RX_CRC];
1311 stats->rx_align_errs += mib[MIB_RX_ALIGN];
1312 stats->rx_symbol_errs += mib[MIB_RX_SYM];
1313 stats->rx_pause_frames += mib[MIB_RX_PAUSE];
1314 stats->rx_control_frames += mib[MIB_RX_NPAUSE];
1315
1316 /* Update counters in ifnet. */
1317 if_inc_counter(ifp, IFCOUNTER_OPACKETS, (u_long)mib[MIB_TX_GOOD_P]);
1318 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (u_long)mib[MIB_TX_TCOLS]);
1319 if_inc_counter(ifp, IFCOUNTER_OERRORS, (u_long)mib[MIB_TX_URUNS] +
1320 (u_long)mib[MIB_TX_ECOLS] +
1321 (u_long)mib[MIB_TX_DEFERED] +
1322 (u_long)mib[MIB_TX_CLOST]);
1323
1324 if_inc_counter(ifp, IFCOUNTER_IPACKETS, (u_long)mib[MIB_RX_GOOD_P]);
1325
1326 if_inc_counter(ifp, IFCOUNTER_IERRORS, mib[MIB_RX_JABBER] +
1327 mib[MIB_RX_MISS] +
1328 mib[MIB_RX_CRCA] +
1329 mib[MIB_RX_USIZE] +
1330 mib[MIB_RX_CRC] +
1331 mib[MIB_RX_ALIGN] +
1332 mib[MIB_RX_SYM]);
1333 }
1334
1335 static void
1336 bfe_txeof(struct bfe_softc *sc)
1337 {
1338 struct bfe_tx_data *r;
1339 struct ifnet *ifp;
1340 int i, chipidx;
1341
1342 BFE_LOCK_ASSERT(sc);
1343
1344 ifp = sc->bfe_ifp;
1345
1346 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1347 chipidx /= sizeof(struct bfe_desc);
1348
1349 i = sc->bfe_tx_cons;
1350 if (i == chipidx)
1351 return;
1352 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
1353 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1354 /* Go through the mbufs and free those that have been transmitted */
1355 for (; i != chipidx; BFE_INC(i, BFE_TX_LIST_CNT)) {
1356 r = &sc->bfe_tx_ring[i];
1357 sc->bfe_tx_cnt--;
1358 if (r->bfe_mbuf == NULL)
1359 continue;
1360 bus_dmamap_sync(sc->bfe_txmbuf_tag, r->bfe_map,
1361 BUS_DMASYNC_POSTWRITE);
1362 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
1363
1364 m_freem(r->bfe_mbuf);
1365 r->bfe_mbuf = NULL;
1366 }
1367
1368 if (i != sc->bfe_tx_cons) {
1369 /* we freed up some mbufs */
1370 sc->bfe_tx_cons = i;
1371 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1372 }
1373
1374 if (sc->bfe_tx_cnt == 0)
1375 sc->bfe_watchdog_timer = 0;
1376 }
1377
1378 /* Pass a received packet up the stack */
1379 static void
1380 bfe_rxeof(struct bfe_softc *sc)
1381 {
1382 struct mbuf *m;
1383 struct ifnet *ifp;
1384 struct bfe_rxheader *rxheader;
1385 struct bfe_rx_data *r;
1386 int cons, prog;
1387 u_int32_t status, current, len, flags;
1388
1389 BFE_LOCK_ASSERT(sc);
1390 cons = sc->bfe_rx_cons;
1391 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1392 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1393
1394 ifp = sc->bfe_ifp;
1395
1396 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
1397 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1398
1399 for (prog = 0; current != cons; prog++,
1400 BFE_INC(cons, BFE_RX_LIST_CNT)) {
1401 r = &sc->bfe_rx_ring[cons];
1402 m = r->bfe_mbuf;
1403 /*
1404 * Rx status should be read from mbuf such that we can't
1405 * delay bus_dmamap_sync(9). This hardware limiation
1406 * results in inefficient mbuf usage as bfe(4) couldn't
1407 * reuse mapped buffer from errored frame.
1408 */
1409 if (bfe_list_newbuf(sc, cons) != 0) {
1410 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1411 bfe_discard_buf(sc, cons);
1412 continue;
1413 }
1414 rxheader = mtod(m, struct bfe_rxheader*);
1415 len = le16toh(rxheader->len);
1416 flags = le16toh(rxheader->flags);
1417
1418 /* Remove CRC bytes. */
1419 len -= ETHER_CRC_LEN;
1420
1421 /* flag an error and try again */
1422 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
1423 m_freem(m);
1424 continue;
1425 }
1426
1427 /* Make sure to skip header bytes written by hardware. */
1428 m_adj(m, BFE_RX_OFFSET);
1429 m->m_len = m->m_pkthdr.len = len;
1430
1431 m->m_pkthdr.rcvif = ifp;
1432 BFE_UNLOCK(sc);
1433 (*ifp->if_input)(ifp, m);
1434 BFE_LOCK(sc);
1435 }
1436
1437 if (prog > 0) {
1438 sc->bfe_rx_cons = cons;
1439 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
1440 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1441 }
1442 }
1443
1444 static void
1445 bfe_intr(void *xsc)
1446 {
1447 struct bfe_softc *sc = xsc;
1448 struct ifnet *ifp;
1449 u_int32_t istat;
1450
1451 ifp = sc->bfe_ifp;
1452
1453 BFE_LOCK(sc);
1454
1455 istat = CSR_READ_4(sc, BFE_ISTAT);
1456
1457 /*
1458 * Defer unsolicited interrupts - This is necessary because setting the
1459 * chips interrupt mask register to 0 doesn't actually stop the
1460 * interrupts
1461 */
1462 istat &= BFE_IMASK_DEF;
1463 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1464 CSR_READ_4(sc, BFE_ISTAT);
1465
1466 /* not expecting this interrupt, disregard it */
1467 if (istat == 0 || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1468 BFE_UNLOCK(sc);
1469 return;
1470 }
1471
1472 /* A packet was received */
1473 if (istat & BFE_ISTAT_RX)
1474 bfe_rxeof(sc);
1475
1476 /* A packet was sent */
1477 if (istat & BFE_ISTAT_TX)
1478 bfe_txeof(sc);
1479
1480 if (istat & BFE_ISTAT_ERRORS) {
1481 if (istat & BFE_ISTAT_DSCE) {
1482 device_printf(sc->bfe_dev, "Descriptor Error\n");
1483 bfe_stop(sc);
1484 BFE_UNLOCK(sc);
1485 return;
1486 }
1487
1488 if (istat & BFE_ISTAT_DPE) {
1489 device_printf(sc->bfe_dev,
1490 "Descriptor Protocol Error\n");
1491 bfe_stop(sc);
1492 BFE_UNLOCK(sc);
1493 return;
1494 }
1495 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1496 bfe_init_locked(sc);
1497 }
1498
1499 /* We have packets pending, fire them out */
1500 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1501 bfe_start_locked(ifp);
1502
1503 BFE_UNLOCK(sc);
1504 }
1505
1506 static int
1507 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head)
1508 {
1509 struct bfe_desc *d;
1510 struct bfe_tx_data *r, *r1;
1511 struct mbuf *m;
1512 bus_dmamap_t map;
1513 bus_dma_segment_t txsegs[BFE_MAXTXSEGS];
1514 uint32_t cur, si;
1515 int error, i, nsegs;
1516
1517 BFE_LOCK_ASSERT(sc);
1518
1519 M_ASSERTPKTHDR((*m_head));
1520
1521 si = cur = sc->bfe_tx_prod;
1522 r = &sc->bfe_tx_ring[cur];
1523 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, *m_head,
1524 txsegs, &nsegs, 0);
1525 if (error == EFBIG) {
1526 m = m_collapse(*m_head, M_NOWAIT, BFE_MAXTXSEGS);
1527 if (m == NULL) {
1528 m_freem(*m_head);
1529 *m_head = NULL;
1530 return (ENOMEM);
1531 }
1532 *m_head = m;
1533 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map,
1534 *m_head, txsegs, &nsegs, 0);
1535 if (error != 0) {
1536 m_freem(*m_head);
1537 *m_head = NULL;
1538 return (error);
1539 }
1540 } else if (error != 0)
1541 return (error);
1542 if (nsegs == 0) {
1543 m_freem(*m_head);
1544 *m_head = NULL;
1545 return (EIO);
1546 }
1547
1548 if (sc->bfe_tx_cnt + nsegs > BFE_TX_LIST_CNT - 1) {
1549 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
1550 return (ENOBUFS);
1551 }
1552
1553 for (i = 0; i < nsegs; i++) {
1554 d = &sc->bfe_tx_list[cur];
1555 d->bfe_ctrl = htole32(txsegs[i].ds_len & BFE_DESC_LEN);
1556 d->bfe_ctrl |= htole32(BFE_DESC_IOC);
1557 if (cur == BFE_TX_LIST_CNT - 1)
1558 /*
1559 * Tell the chip to wrap to the start of
1560 * the descriptor list.
1561 */
1562 d->bfe_ctrl |= htole32(BFE_DESC_EOT);
1563 /* The chip needs all addresses to be added to BFE_PCI_DMA. */
1564 d->bfe_addr = htole32(BFE_ADDR_LO(txsegs[i].ds_addr) +
1565 BFE_PCI_DMA);
1566 BFE_INC(cur, BFE_TX_LIST_CNT);
1567 }
1568
1569 /* Update producer index. */
1570 sc->bfe_tx_prod = cur;
1571
1572 /* Set EOF on the last descriptor. */
1573 cur = (cur + BFE_TX_LIST_CNT - 1) % BFE_TX_LIST_CNT;
1574 d = &sc->bfe_tx_list[cur];
1575 d->bfe_ctrl |= htole32(BFE_DESC_EOF);
1576
1577 /* Lastly set SOF on the first descriptor to avoid races. */
1578 d = &sc->bfe_tx_list[si];
1579 d->bfe_ctrl |= htole32(BFE_DESC_SOF);
1580
1581 r1 = &sc->bfe_tx_ring[cur];
1582 map = r->bfe_map;
1583 r->bfe_map = r1->bfe_map;
1584 r1->bfe_map = map;
1585 r1->bfe_mbuf = *m_head;
1586 sc->bfe_tx_cnt += nsegs;
1587
1588 bus_dmamap_sync(sc->bfe_txmbuf_tag, map, BUS_DMASYNC_PREWRITE);
1589
1590 return (0);
1591 }
1592
1593 /*
1594 * Set up to transmit a packet.
1595 */
1596 static void
1597 bfe_start(struct ifnet *ifp)
1598 {
1599 BFE_LOCK((struct bfe_softc *)ifp->if_softc);
1600 bfe_start_locked(ifp);
1601 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc);
1602 }
1603
1604 /*
1605 * Set up to transmit a packet. The softc is already locked.
1606 */
1607 static void
1608 bfe_start_locked(struct ifnet *ifp)
1609 {
1610 struct bfe_softc *sc;
1611 struct mbuf *m_head;
1612 int queued;
1613
1614 sc = ifp->if_softc;
1615
1616 BFE_LOCK_ASSERT(sc);
1617
1618 /*
1619 * Not much point trying to send if the link is down
1620 * or we have nothing to send.
1621 */
1622 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1623 IFF_DRV_RUNNING || (sc->bfe_flags & BFE_FLAG_LINK) == 0)
1624 return;
1625
1626 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1627 sc->bfe_tx_cnt < BFE_TX_LIST_CNT - 1;) {
1628 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1629 if (m_head == NULL)
1630 break;
1631
1632 /*
1633 * Pack the data into the tx ring. If we dont have
1634 * enough room, let the chip drain the ring.
1635 */
1636 if (bfe_encap(sc, &m_head)) {
1637 if (m_head == NULL)
1638 break;
1639 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1640 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1641 break;
1642 }
1643
1644 queued++;
1645
1646 /*
1647 * If there's a BPF listener, bounce a copy of this frame
1648 * to him.
1649 */
1650 BPF_MTAP(ifp, m_head);
1651 }
1652
1653 if (queued) {
1654 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
1655 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1656 /* Transmit - twice due to apparent hardware bug */
1657 CSR_WRITE_4(sc, BFE_DMATX_PTR,
1658 sc->bfe_tx_prod * sizeof(struct bfe_desc));
1659 /*
1660 * XXX It seems the following write is not necessary
1661 * to kick Tx command. What might be required would be
1662 * a way flushing PCI posted write. Reading the register
1663 * back ensures the flush operation. In addition,
1664 * hardware will execute PCI posted write in the long
1665 * run and watchdog timer for the kick command was set
1666 * to 5 seconds. Therefore I think the second write
1667 * access is not necessary or could be replaced with
1668 * read operation.
1669 */
1670 CSR_WRITE_4(sc, BFE_DMATX_PTR,
1671 sc->bfe_tx_prod * sizeof(struct bfe_desc));
1672
1673 /*
1674 * Set a timeout in case the chip goes out to lunch.
1675 */
1676 sc->bfe_watchdog_timer = 5;
1677 }
1678 }
1679
1680 static void
1681 bfe_init(void *xsc)
1682 {
1683 BFE_LOCK((struct bfe_softc *)xsc);
1684 bfe_init_locked(xsc);
1685 BFE_UNLOCK((struct bfe_softc *)xsc);
1686 }
1687
1688 static void
1689 bfe_init_locked(void *xsc)
1690 {
1691 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1692 struct ifnet *ifp = sc->bfe_ifp;
1693 struct mii_data *mii;
1694
1695 BFE_LOCK_ASSERT(sc);
1696
1697 mii = device_get_softc(sc->bfe_miibus);
1698
1699 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1700 return;
1701
1702 bfe_stop(sc);
1703 bfe_chip_reset(sc);
1704
1705 if (bfe_list_rx_init(sc) == ENOBUFS) {
1706 device_printf(sc->bfe_dev,
1707 "%s: Not enough memory for list buffers\n", __func__);
1708 bfe_stop(sc);
1709 return;
1710 }
1711 bfe_list_tx_init(sc);
1712
1713 bfe_set_rx_mode(sc);
1714
1715 /* Enable the chip and core */
1716 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1717 /* Enable interrupts */
1718 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1719
1720 /* Clear link state and change media. */
1721 sc->bfe_flags &= ~BFE_FLAG_LINK;
1722 mii_mediachg(mii);
1723
1724 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1725 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1726
1727 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
1728 }
1729
1730 /*
1731 * Set media options.
1732 */
1733 static int
1734 bfe_ifmedia_upd(struct ifnet *ifp)
1735 {
1736 struct bfe_softc *sc;
1737 struct mii_data *mii;
1738 struct mii_softc *miisc;
1739 int error;
1740
1741 sc = ifp->if_softc;
1742 BFE_LOCK(sc);
1743
1744 mii = device_get_softc(sc->bfe_miibus);
1745 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1746 PHY_RESET(miisc);
1747 error = mii_mediachg(mii);
1748 BFE_UNLOCK(sc);
1749
1750 return (error);
1751 }
1752
1753 /*
1754 * Report current media status.
1755 */
1756 static void
1757 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1758 {
1759 struct bfe_softc *sc = ifp->if_softc;
1760 struct mii_data *mii;
1761
1762 BFE_LOCK(sc);
1763 mii = device_get_softc(sc->bfe_miibus);
1764 mii_pollstat(mii);
1765 ifmr->ifm_active = mii->mii_media_active;
1766 ifmr->ifm_status = mii->mii_media_status;
1767 BFE_UNLOCK(sc);
1768 }
1769
1770 static int
1771 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1772 {
1773 struct bfe_softc *sc = ifp->if_softc;
1774 struct ifreq *ifr = (struct ifreq *) data;
1775 struct mii_data *mii;
1776 int error = 0;
1777
1778 switch (command) {
1779 case SIOCSIFFLAGS:
1780 BFE_LOCK(sc);
1781 if (ifp->if_flags & IFF_UP) {
1782 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1783 bfe_set_rx_mode(sc);
1784 else if ((sc->bfe_flags & BFE_FLAG_DETACH) == 0)
1785 bfe_init_locked(sc);
1786 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1787 bfe_stop(sc);
1788 BFE_UNLOCK(sc);
1789 break;
1790 case SIOCADDMULTI:
1791 case SIOCDELMULTI:
1792 BFE_LOCK(sc);
1793 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1794 bfe_set_rx_mode(sc);
1795 BFE_UNLOCK(sc);
1796 break;
1797 case SIOCGIFMEDIA:
1798 case SIOCSIFMEDIA:
1799 mii = device_get_softc(sc->bfe_miibus);
1800 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1801 break;
1802 default:
1803 error = ether_ioctl(ifp, command, data);
1804 break;
1805 }
1806
1807 return (error);
1808 }
1809
1810 static void
1811 bfe_watchdog(struct bfe_softc *sc)
1812 {
1813 struct ifnet *ifp;
1814
1815 BFE_LOCK_ASSERT(sc);
1816
1817 if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer)
1818 return;
1819
1820 ifp = sc->bfe_ifp;
1821
1822 device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n");
1823
1824 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1825 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1826 bfe_init_locked(sc);
1827
1828 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1829 bfe_start_locked(ifp);
1830 }
1831
1832 static void
1833 bfe_tick(void *xsc)
1834 {
1835 struct bfe_softc *sc = xsc;
1836 struct mii_data *mii;
1837
1838 BFE_LOCK_ASSERT(sc);
1839
1840 mii = device_get_softc(sc->bfe_miibus);
1841 mii_tick(mii);
1842 bfe_stats_update(sc);
1843 bfe_watchdog(sc);
1844 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
1845 }
1846
1847 /*
1848 * Stop the adapter and free any mbufs allocated to the
1849 * RX and TX lists.
1850 */
1851 static void
1852 bfe_stop(struct bfe_softc *sc)
1853 {
1854 struct ifnet *ifp;
1855
1856 BFE_LOCK_ASSERT(sc);
1857
1858 ifp = sc->bfe_ifp;
1859 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1860 sc->bfe_flags &= ~BFE_FLAG_LINK;
1861 callout_stop(&sc->bfe_stat_co);
1862 sc->bfe_watchdog_timer = 0;
1863
1864 bfe_chip_halt(sc);
1865 bfe_tx_ring_free(sc);
1866 bfe_rx_ring_free(sc);
1867 }
1868
1869 static int
1870 sysctl_bfe_stats(SYSCTL_HANDLER_ARGS)
1871 {
1872 struct bfe_softc *sc;
1873 struct bfe_hw_stats *stats;
1874 int error, result;
1875
1876 result = -1;
1877 error = sysctl_handle_int(oidp, &result, 0, req);
1878
1879 if (error != 0 || req->newptr == NULL)
1880 return (error);
1881
1882 if (result != 1)
1883 return (error);
1884
1885 sc = (struct bfe_softc *)arg1;
1886 stats = &sc->bfe_stats;
1887
1888 printf("%s statistics:\n", device_get_nameunit(sc->bfe_dev));
1889 printf("Transmit good octets : %ju\n",
1890 (uintmax_t)stats->tx_good_octets);
1891 printf("Transmit good frames : %ju\n",
1892 (uintmax_t)stats->tx_good_frames);
1893 printf("Transmit octets : %ju\n",
1894 (uintmax_t)stats->tx_octets);
1895 printf("Transmit frames : %ju\n",
1896 (uintmax_t)stats->tx_frames);
1897 printf("Transmit broadcast frames : %ju\n",
1898 (uintmax_t)stats->tx_bcast_frames);
1899 printf("Transmit multicast frames : %ju\n",
1900 (uintmax_t)stats->tx_mcast_frames);
1901 printf("Transmit frames 64 bytes : %ju\n",
1902 (uint64_t)stats->tx_pkts_64);
1903 printf("Transmit frames 65 to 127 bytes : %ju\n",
1904 (uint64_t)stats->tx_pkts_65_127);
1905 printf("Transmit frames 128 to 255 bytes : %ju\n",
1906 (uint64_t)stats->tx_pkts_128_255);
1907 printf("Transmit frames 256 to 511 bytes : %ju\n",
1908 (uint64_t)stats->tx_pkts_256_511);
1909 printf("Transmit frames 512 to 1023 bytes : %ju\n",
1910 (uint64_t)stats->tx_pkts_512_1023);
1911 printf("Transmit frames 1024 to max bytes : %ju\n",
1912 (uint64_t)stats->tx_pkts_1024_max);
1913 printf("Transmit jabber errors : %u\n", stats->tx_jabbers);
1914 printf("Transmit oversized frames : %ju\n",
1915 (uint64_t)stats->tx_oversize_frames);
1916 printf("Transmit fragmented frames : %ju\n",
1917 (uint64_t)stats->tx_frag_frames);
1918 printf("Transmit underruns : %u\n", stats->tx_colls);
1919 printf("Transmit total collisions : %u\n", stats->tx_single_colls);
1920 printf("Transmit single collisions : %u\n", stats->tx_single_colls);
1921 printf("Transmit multiple collisions : %u\n", stats->tx_multi_colls);
1922 printf("Transmit excess collisions : %u\n", stats->tx_excess_colls);
1923 printf("Transmit late collisions : %u\n", stats->tx_late_colls);
1924 printf("Transmit deferrals : %u\n", stats->tx_deferrals);
1925 printf("Transmit carrier losts : %u\n", stats->tx_carrier_losts);
1926 printf("Transmit pause frames : %u\n", stats->tx_pause_frames);
1927
1928 printf("Receive good octets : %ju\n",
1929 (uintmax_t)stats->rx_good_octets);
1930 printf("Receive good frames : %ju\n",
1931 (uintmax_t)stats->rx_good_frames);
1932 printf("Receive octets : %ju\n",
1933 (uintmax_t)stats->rx_octets);
1934 printf("Receive frames : %ju\n",
1935 (uintmax_t)stats->rx_frames);
1936 printf("Receive broadcast frames : %ju\n",
1937 (uintmax_t)stats->rx_bcast_frames);
1938 printf("Receive multicast frames : %ju\n",
1939 (uintmax_t)stats->rx_mcast_frames);
1940 printf("Receive frames 64 bytes : %ju\n",
1941 (uint64_t)stats->rx_pkts_64);
1942 printf("Receive frames 65 to 127 bytes : %ju\n",
1943 (uint64_t)stats->rx_pkts_65_127);
1944 printf("Receive frames 128 to 255 bytes : %ju\n",
1945 (uint64_t)stats->rx_pkts_128_255);
1946 printf("Receive frames 256 to 511 bytes : %ju\n",
1947 (uint64_t)stats->rx_pkts_256_511);
1948 printf("Receive frames 512 to 1023 bytes : %ju\n",
1949 (uint64_t)stats->rx_pkts_512_1023);
1950 printf("Receive frames 1024 to max bytes : %ju\n",
1951 (uint64_t)stats->rx_pkts_1024_max);
1952 printf("Receive jabber errors : %u\n", stats->rx_jabbers);
1953 printf("Receive oversized frames : %ju\n",
1954 (uint64_t)stats->rx_oversize_frames);
1955 printf("Receive fragmented frames : %ju\n",
1956 (uint64_t)stats->rx_frag_frames);
1957 printf("Receive missed frames : %u\n", stats->rx_missed_frames);
1958 printf("Receive CRC align errors : %u\n", stats->rx_crc_align_errs);
1959 printf("Receive undersized frames : %u\n", stats->rx_runts);
1960 printf("Receive CRC errors : %u\n", stats->rx_crc_errs);
1961 printf("Receive align errors : %u\n", stats->rx_align_errs);
1962 printf("Receive symbol errors : %u\n", stats->rx_symbol_errs);
1963 printf("Receive pause frames : %u\n", stats->rx_pause_frames);
1964 printf("Receive control frames : %u\n", stats->rx_control_frames);
1965
1966 return (error);
1967 }
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