The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/bfe/if_bfe.c

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    1 /*-
    2  * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
    3  * and Duncan Barclay<dmlb@dmlb.org>
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 
   28 #include <sys/cdefs.h>
   29 __FBSDID("$FreeBSD: releng/10.1/sys/dev/bfe/if_bfe.c 243857 2012-12-04 09:32:43Z glebius $");
   30 
   31 #include <sys/param.h>
   32 #include <sys/systm.h>
   33 #include <sys/bus.h>
   34 #include <sys/endian.h>
   35 #include <sys/kernel.h>
   36 #include <sys/malloc.h>
   37 #include <sys/mbuf.h>
   38 #include <sys/module.h>
   39 #include <sys/rman.h>
   40 #include <sys/socket.h>
   41 #include <sys/sockio.h>
   42 #include <sys/sysctl.h>
   43 
   44 #include <net/bpf.h>
   45 #include <net/if.h>
   46 #include <net/ethernet.h>
   47 #include <net/if_dl.h>
   48 #include <net/if_media.h>
   49 #include <net/if_types.h>
   50 #include <net/if_vlan_var.h>
   51 
   52 #include <dev/mii/mii.h>
   53 #include <dev/mii/miivar.h>
   54 
   55 #include <dev/pci/pcireg.h>
   56 #include <dev/pci/pcivar.h>
   57 
   58 #include <machine/bus.h>
   59 
   60 #include <dev/bfe/if_bfereg.h>
   61 
   62 MODULE_DEPEND(bfe, pci, 1, 1, 1);
   63 MODULE_DEPEND(bfe, ether, 1, 1, 1);
   64 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
   65 
   66 /* "device miibus" required.  See GENERIC if you get errors here. */
   67 #include "miibus_if.h"
   68 
   69 #define BFE_DEVDESC_MAX         64      /* Maximum device description length */
   70 
   71 static struct bfe_type bfe_devs[] = {
   72         { BCOM_VENDORID, BCOM_DEVICEID_BCM4401,
   73                 "Broadcom BCM4401 Fast Ethernet" },
   74         { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0,
   75                 "Broadcom BCM4401-B0 Fast Ethernet" },
   76                 { 0, 0, NULL }
   77 };
   78 
   79 static int  bfe_probe                           (device_t);
   80 static int  bfe_attach                          (device_t);
   81 static int  bfe_detach                          (device_t);
   82 static int  bfe_suspend                         (device_t);
   83 static int  bfe_resume                          (device_t);
   84 static void bfe_release_resources       (struct bfe_softc *);
   85 static void bfe_intr                            (void *);
   86 static int  bfe_encap                           (struct bfe_softc *, struct mbuf **);
   87 static void bfe_start                           (struct ifnet *);
   88 static void bfe_start_locked                    (struct ifnet *);
   89 static int  bfe_ioctl                           (struct ifnet *, u_long, caddr_t);
   90 static void bfe_init                            (void *);
   91 static void bfe_init_locked                     (void *);
   92 static void bfe_stop                            (struct bfe_softc *);
   93 static void bfe_watchdog                        (struct bfe_softc *);
   94 static int  bfe_shutdown                        (device_t);
   95 static void bfe_tick                            (void *);
   96 static void bfe_txeof                           (struct bfe_softc *);
   97 static void bfe_rxeof                           (struct bfe_softc *);
   98 static void bfe_set_rx_mode                     (struct bfe_softc *);
   99 static int  bfe_list_rx_init            (struct bfe_softc *);
  100 static void bfe_list_tx_init            (struct bfe_softc *);
  101 static void bfe_discard_buf             (struct bfe_softc *, int);
  102 static int  bfe_list_newbuf                     (struct bfe_softc *, int);
  103 static void bfe_rx_ring_free            (struct bfe_softc *);
  104 
  105 static void bfe_pci_setup                       (struct bfe_softc *, u_int32_t);
  106 static int  bfe_ifmedia_upd                     (struct ifnet *);
  107 static void bfe_ifmedia_sts                     (struct ifnet *, struct ifmediareq *);
  108 static int  bfe_miibus_readreg          (device_t, int, int);
  109 static int  bfe_miibus_writereg         (device_t, int, int, int);
  110 static void bfe_miibus_statchg          (device_t);
  111 static int  bfe_wait_bit                        (struct bfe_softc *, u_int32_t, u_int32_t,
  112                 u_long, const int);
  113 static void bfe_get_config                      (struct bfe_softc *sc);
  114 static void bfe_read_eeprom                     (struct bfe_softc *, u_int8_t *);
  115 static void bfe_stats_update            (struct bfe_softc *);
  116 static void bfe_clear_stats                     (struct bfe_softc *);
  117 static int  bfe_readphy                         (struct bfe_softc *, u_int32_t, u_int32_t*);
  118 static int  bfe_writephy                        (struct bfe_softc *, u_int32_t, u_int32_t);
  119 static int  bfe_resetphy                        (struct bfe_softc *);
  120 static int  bfe_setupphy                        (struct bfe_softc *);
  121 static void bfe_chip_reset                      (struct bfe_softc *);
  122 static void bfe_chip_halt                       (struct bfe_softc *);
  123 static void bfe_core_reset                      (struct bfe_softc *);
  124 static void bfe_core_disable            (struct bfe_softc *);
  125 static int  bfe_dma_alloc                       (struct bfe_softc *);
  126 static void bfe_dma_free                (struct bfe_softc *sc);
  127 static void bfe_dma_map                         (void *, bus_dma_segment_t *, int, int);
  128 static void bfe_cam_write                       (struct bfe_softc *, u_char *, int);
  129 static int  sysctl_bfe_stats            (SYSCTL_HANDLER_ARGS);
  130 
  131 static device_method_t bfe_methods[] = {
  132         /* Device interface */
  133         DEVMETHOD(device_probe,         bfe_probe),
  134         DEVMETHOD(device_attach,        bfe_attach),
  135         DEVMETHOD(device_detach,        bfe_detach),
  136         DEVMETHOD(device_shutdown,      bfe_shutdown),
  137         DEVMETHOD(device_suspend,       bfe_suspend),
  138         DEVMETHOD(device_resume,        bfe_resume),
  139 
  140         /* MII interface */
  141         DEVMETHOD(miibus_readreg,       bfe_miibus_readreg),
  142         DEVMETHOD(miibus_writereg,      bfe_miibus_writereg),
  143         DEVMETHOD(miibus_statchg,       bfe_miibus_statchg),
  144 
  145         DEVMETHOD_END
  146 };
  147 
  148 static driver_t bfe_driver = {
  149         "bfe",
  150         bfe_methods,
  151         sizeof(struct bfe_softc)
  152 };
  153 
  154 static devclass_t bfe_devclass;
  155 
  156 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
  157 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
  158 
  159 /*
  160  * Probe for a Broadcom 4401 chip.
  161  */
  162 static int
  163 bfe_probe(device_t dev)
  164 {
  165         struct bfe_type *t;
  166 
  167         t = bfe_devs;
  168 
  169         while (t->bfe_name != NULL) {
  170                 if (pci_get_vendor(dev) == t->bfe_vid &&
  171                     pci_get_device(dev) == t->bfe_did) {
  172                         device_set_desc(dev, t->bfe_name);
  173                         return (BUS_PROBE_DEFAULT);
  174                 }
  175                 t++;
  176         }
  177 
  178         return (ENXIO);
  179 }
  180 
  181 struct bfe_dmamap_arg {
  182         bus_addr_t      bfe_busaddr;
  183 };
  184 
  185 static int
  186 bfe_dma_alloc(struct bfe_softc *sc)
  187 {
  188         struct bfe_dmamap_arg ctx;
  189         struct bfe_rx_data *rd;
  190         struct bfe_tx_data *td;
  191         int error, i;
  192 
  193         /*
  194          * parent tag.  Apparently the chip cannot handle any DMA address
  195          * greater than 1GB.
  196          */
  197         error = bus_dma_tag_create(bus_get_dma_tag(sc->bfe_dev), /* parent */
  198             1, 0,                       /* alignment, boundary */
  199             BFE_DMA_MAXADDR,            /* lowaddr */
  200             BUS_SPACE_MAXADDR,          /* highaddr */
  201             NULL, NULL,                 /* filter, filterarg */
  202             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
  203             0,                          /* nsegments */
  204             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
  205             0,                          /* flags */
  206             NULL, NULL,                 /* lockfunc, lockarg */
  207             &sc->bfe_parent_tag);
  208         if (error != 0) {
  209                 device_printf(sc->bfe_dev, "cannot create parent DMA tag.\n");
  210                 goto fail;
  211         }
  212 
  213         /* Create tag for Tx ring. */
  214         error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
  215             BFE_TX_RING_ALIGN, 0,       /* alignment, boundary */
  216             BUS_SPACE_MAXADDR,          /* lowaddr */
  217             BUS_SPACE_MAXADDR,          /* highaddr */
  218             NULL, NULL,                 /* filter, filterarg */
  219             BFE_TX_LIST_SIZE,           /* maxsize */
  220             1,                          /* nsegments */
  221             BFE_TX_LIST_SIZE,           /* maxsegsize */
  222             0,                          /* flags */
  223             NULL, NULL,                 /* lockfunc, lockarg */
  224             &sc->bfe_tx_tag);
  225         if (error != 0) {
  226                 device_printf(sc->bfe_dev, "cannot create Tx ring DMA tag.\n");
  227                 goto fail;
  228         }
  229 
  230         /* Create tag for Rx ring. */
  231         error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
  232             BFE_RX_RING_ALIGN, 0,       /* alignment, boundary */
  233             BUS_SPACE_MAXADDR,          /* lowaddr */
  234             BUS_SPACE_MAXADDR,          /* highaddr */
  235             NULL, NULL,                 /* filter, filterarg */
  236             BFE_RX_LIST_SIZE,           /* maxsize */
  237             1,                          /* nsegments */
  238             BFE_RX_LIST_SIZE,           /* maxsegsize */
  239             0,                          /* flags */
  240             NULL, NULL,                 /* lockfunc, lockarg */
  241             &sc->bfe_rx_tag);
  242         if (error != 0) {
  243                 device_printf(sc->bfe_dev, "cannot create Rx ring DMA tag.\n");
  244                 goto fail;
  245         }
  246 
  247         /* Create tag for Tx buffers. */
  248         error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
  249             1, 0,                       /* alignment, boundary */
  250             BUS_SPACE_MAXADDR,          /* lowaddr */
  251             BUS_SPACE_MAXADDR,          /* highaddr */
  252             NULL, NULL,                 /* filter, filterarg */
  253             MCLBYTES * BFE_MAXTXSEGS,   /* maxsize */
  254             BFE_MAXTXSEGS,              /* nsegments */
  255             MCLBYTES,                   /* maxsegsize */
  256             0,                          /* flags */
  257             NULL, NULL,                 /* lockfunc, lockarg */
  258             &sc->bfe_txmbuf_tag);
  259         if (error != 0) {
  260                 device_printf(sc->bfe_dev,
  261                     "cannot create Tx buffer DMA tag.\n");
  262                 goto fail;
  263         }
  264 
  265         /* Create tag for Rx buffers. */
  266         error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
  267             1, 0,                       /* alignment, boundary */
  268             BUS_SPACE_MAXADDR,          /* lowaddr */
  269             BUS_SPACE_MAXADDR,          /* highaddr */
  270             NULL, NULL,                 /* filter, filterarg */
  271             MCLBYTES,                   /* maxsize */
  272             1,                          /* nsegments */
  273             MCLBYTES,                   /* maxsegsize */
  274             0,                          /* flags */
  275             NULL, NULL,                 /* lockfunc, lockarg */
  276             &sc->bfe_rxmbuf_tag);
  277         if (error != 0) {
  278                 device_printf(sc->bfe_dev,
  279                     "cannot create Rx buffer DMA tag.\n");
  280                 goto fail;
  281         }
  282 
  283         /* Allocate DMA'able memory and load DMA map. */
  284         error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
  285           BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_tx_map);
  286         if (error != 0) {
  287                 device_printf(sc->bfe_dev,
  288                     "cannot allocate DMA'able memory for Tx ring.\n");
  289                 goto fail;
  290         }
  291         ctx.bfe_busaddr = 0;
  292         error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
  293             sc->bfe_tx_list, BFE_TX_LIST_SIZE, bfe_dma_map, &ctx,
  294             BUS_DMA_NOWAIT);
  295         if (error != 0 || ctx.bfe_busaddr == 0) {
  296                 device_printf(sc->bfe_dev,
  297                     "cannot load DMA'able memory for Tx ring.\n");
  298                 goto fail;
  299         }
  300         sc->bfe_tx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
  301 
  302         error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
  303           BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_rx_map);
  304         if (error != 0) {
  305                 device_printf(sc->bfe_dev,
  306                     "cannot allocate DMA'able memory for Rx ring.\n");
  307                 goto fail;
  308         }
  309         ctx.bfe_busaddr = 0;
  310         error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
  311             sc->bfe_rx_list, BFE_RX_LIST_SIZE, bfe_dma_map, &ctx,
  312             BUS_DMA_NOWAIT);
  313         if (error != 0 || ctx.bfe_busaddr == 0) {
  314                 device_printf(sc->bfe_dev,
  315                     "cannot load DMA'able memory for Rx ring.\n");
  316                 goto fail;
  317         }
  318         sc->bfe_rx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
  319 
  320         /* Create DMA maps for Tx buffers. */
  321         for (i = 0; i < BFE_TX_LIST_CNT; i++) {
  322                 td = &sc->bfe_tx_ring[i];
  323                 td->bfe_mbuf = NULL;
  324                 td->bfe_map = NULL;
  325                 error = bus_dmamap_create(sc->bfe_txmbuf_tag, 0, &td->bfe_map);
  326                 if (error != 0) {
  327                         device_printf(sc->bfe_dev,
  328                             "cannot create DMA map for Tx.\n");
  329                         goto fail;
  330                 }
  331         }
  332 
  333         /* Create spare DMA map for Rx buffers. */
  334         error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &sc->bfe_rx_sparemap);
  335         if (error != 0) {
  336                 device_printf(sc->bfe_dev, "cannot create spare DMA map for Rx.\n");
  337                 goto fail;
  338         }
  339         /* Create DMA maps for Rx buffers. */
  340         for (i = 0; i < BFE_RX_LIST_CNT; i++) {
  341                 rd = &sc->bfe_rx_ring[i];
  342                 rd->bfe_mbuf = NULL;
  343                 rd->bfe_map = NULL;
  344                 rd->bfe_ctrl = 0;
  345                 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &rd->bfe_map);
  346                 if (error != 0) {
  347                         device_printf(sc->bfe_dev,
  348                             "cannot create DMA map for Rx.\n");
  349                         goto fail;
  350                 }
  351         }
  352 
  353 fail:
  354         return (error);
  355 }
  356 
  357 static void
  358 bfe_dma_free(struct bfe_softc *sc)
  359 {
  360         struct bfe_tx_data *td;
  361         struct bfe_rx_data *rd;
  362         int i;
  363 
  364         /* Tx ring. */
  365         if (sc->bfe_tx_tag != NULL) {
  366                 if (sc->bfe_tx_map != NULL)
  367                         bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
  368                 if (sc->bfe_tx_map != NULL && sc->bfe_tx_list != NULL)
  369                         bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
  370                             sc->bfe_tx_map);
  371                 sc->bfe_tx_map = NULL;
  372                 sc->bfe_tx_list = NULL;
  373                 bus_dma_tag_destroy(sc->bfe_tx_tag);
  374                 sc->bfe_tx_tag = NULL;
  375         }
  376 
  377         /* Rx ring. */
  378         if (sc->bfe_rx_tag != NULL) {
  379                 if (sc->bfe_rx_map != NULL)
  380                         bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
  381                 if (sc->bfe_rx_map != NULL && sc->bfe_rx_list != NULL)
  382                         bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
  383                             sc->bfe_rx_map);
  384                 sc->bfe_rx_map = NULL;
  385                 sc->bfe_rx_list = NULL;
  386                 bus_dma_tag_destroy(sc->bfe_rx_tag);
  387                 sc->bfe_rx_tag = NULL;
  388         }
  389 
  390         /* Tx buffers. */
  391         if (sc->bfe_txmbuf_tag != NULL) {
  392                 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
  393                         td = &sc->bfe_tx_ring[i];
  394                         if (td->bfe_map != NULL) {
  395                                 bus_dmamap_destroy(sc->bfe_txmbuf_tag,
  396                                     td->bfe_map);
  397                                 td->bfe_map = NULL;
  398                         }
  399                 }
  400                 bus_dma_tag_destroy(sc->bfe_txmbuf_tag);
  401                 sc->bfe_txmbuf_tag = NULL;
  402         }
  403 
  404         /* Rx buffers. */
  405         if (sc->bfe_rxmbuf_tag != NULL) {
  406                 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
  407                         rd = &sc->bfe_rx_ring[i];
  408                         if (rd->bfe_map != NULL) {
  409                                 bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
  410                                     rd->bfe_map);
  411                                 rd->bfe_map = NULL;
  412                         }
  413                 }
  414                 if (sc->bfe_rx_sparemap != NULL) {
  415                         bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
  416                             sc->bfe_rx_sparemap);
  417                         sc->bfe_rx_sparemap = NULL;
  418                 }
  419                 bus_dma_tag_destroy(sc->bfe_rxmbuf_tag);
  420                 sc->bfe_rxmbuf_tag = NULL;
  421         }
  422 
  423         if (sc->bfe_parent_tag != NULL) {
  424                 bus_dma_tag_destroy(sc->bfe_parent_tag);
  425                 sc->bfe_parent_tag = NULL;
  426         }
  427 }
  428 
  429 static int
  430 bfe_attach(device_t dev)
  431 {
  432         struct ifnet *ifp = NULL;
  433         struct bfe_softc *sc;
  434         int error = 0, rid;
  435 
  436         sc = device_get_softc(dev);
  437         mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
  438                         MTX_DEF);
  439         callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0);
  440 
  441         sc->bfe_dev = dev;
  442 
  443         /*
  444          * Map control/status registers.
  445          */
  446         pci_enable_busmaster(dev);
  447 
  448         rid = PCIR_BAR(0);
  449         sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
  450                         RF_ACTIVE);
  451         if (sc->bfe_res == NULL) {
  452                 device_printf(dev, "couldn't map memory\n");
  453                 error = ENXIO;
  454                 goto fail;
  455         }
  456 
  457         /* Allocate interrupt */
  458         rid = 0;
  459 
  460         sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
  461                         RF_SHAREABLE | RF_ACTIVE);
  462         if (sc->bfe_irq == NULL) {
  463                 device_printf(dev, "couldn't map interrupt\n");
  464                 error = ENXIO;
  465                 goto fail;
  466         }
  467 
  468         if (bfe_dma_alloc(sc) != 0) {
  469                 device_printf(dev, "failed to allocate DMA resources\n");
  470                 error = ENXIO;
  471                 goto fail;
  472         }
  473 
  474         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
  475             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
  476             "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_bfe_stats,
  477             "I", "Statistics");
  478 
  479         /* Set up ifnet structure */
  480         ifp = sc->bfe_ifp = if_alloc(IFT_ETHER);
  481         if (ifp == NULL) {
  482                 device_printf(dev, "failed to if_alloc()\n");
  483                 error = ENOSPC;
  484                 goto fail;
  485         }
  486         ifp->if_softc = sc;
  487         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
  488         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
  489         ifp->if_ioctl = bfe_ioctl;
  490         ifp->if_start = bfe_start;
  491         ifp->if_init = bfe_init;
  492         IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN);
  493         ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN;
  494         IFQ_SET_READY(&ifp->if_snd);
  495 
  496         bfe_get_config(sc);
  497 
  498         /* Reset the chip and turn on the PHY */
  499         BFE_LOCK(sc);
  500         bfe_chip_reset(sc);
  501         BFE_UNLOCK(sc);
  502 
  503         error = mii_attach(dev, &sc->bfe_miibus, ifp, bfe_ifmedia_upd,
  504             bfe_ifmedia_sts, BMSR_DEFCAPMASK, sc->bfe_phyaddr, MII_OFFSET_ANY,
  505             0);
  506         if (error != 0) {
  507                 device_printf(dev, "attaching PHYs failed\n");
  508                 goto fail;
  509         }
  510 
  511         ether_ifattach(ifp, sc->bfe_enaddr);
  512 
  513         /*
  514          * Tell the upper layer(s) we support long frames.
  515          */
  516         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
  517         ifp->if_capabilities |= IFCAP_VLAN_MTU;
  518         ifp->if_capenable |= IFCAP_VLAN_MTU;
  519 
  520         /*
  521          * Hook interrupt last to avoid having to lock softc
  522          */
  523         error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE,
  524                         NULL, bfe_intr, sc, &sc->bfe_intrhand);
  525 
  526         if (error) {
  527                 device_printf(dev, "couldn't set up irq\n");
  528                 goto fail;
  529         }
  530 fail:
  531         if (error != 0)
  532                 bfe_detach(dev);
  533         return (error);
  534 }
  535 
  536 static int
  537 bfe_detach(device_t dev)
  538 {
  539         struct bfe_softc *sc;
  540         struct ifnet *ifp;
  541 
  542         sc = device_get_softc(dev);
  543 
  544         ifp = sc->bfe_ifp;
  545 
  546         if (device_is_attached(dev)) {
  547                 BFE_LOCK(sc);
  548                 sc->bfe_flags |= BFE_FLAG_DETACH;
  549                 bfe_stop(sc);
  550                 BFE_UNLOCK(sc);
  551                 callout_drain(&sc->bfe_stat_co);
  552                 if (ifp != NULL)
  553                         ether_ifdetach(ifp);
  554         }
  555 
  556         BFE_LOCK(sc);
  557         bfe_chip_reset(sc);
  558         BFE_UNLOCK(sc);
  559 
  560         bus_generic_detach(dev);
  561         if (sc->bfe_miibus != NULL)
  562                 device_delete_child(dev, sc->bfe_miibus);
  563 
  564         bfe_release_resources(sc);
  565         bfe_dma_free(sc);
  566         mtx_destroy(&sc->bfe_mtx);
  567 
  568         return (0);
  569 }
  570 
  571 /*
  572  * Stop all chip I/O so that the kernel's probe routines don't
  573  * get confused by errant DMAs when rebooting.
  574  */
  575 static int
  576 bfe_shutdown(device_t dev)
  577 {
  578         struct bfe_softc *sc;
  579 
  580         sc = device_get_softc(dev);
  581         BFE_LOCK(sc);
  582         bfe_stop(sc);
  583 
  584         BFE_UNLOCK(sc);
  585 
  586         return (0);
  587 }
  588 
  589 static int
  590 bfe_suspend(device_t dev)
  591 {
  592         struct bfe_softc *sc;
  593 
  594         sc = device_get_softc(dev);
  595         BFE_LOCK(sc);
  596         bfe_stop(sc);
  597         BFE_UNLOCK(sc);
  598 
  599         return (0);
  600 }
  601 
  602 static int
  603 bfe_resume(device_t dev)
  604 {
  605         struct bfe_softc *sc;
  606         struct ifnet *ifp;
  607 
  608         sc = device_get_softc(dev);
  609         ifp = sc->bfe_ifp;
  610         BFE_LOCK(sc);
  611         bfe_chip_reset(sc);
  612         if (ifp->if_flags & IFF_UP) {
  613                 bfe_init_locked(sc);
  614                 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
  615                     !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
  616                         bfe_start_locked(ifp);
  617         }
  618         BFE_UNLOCK(sc);
  619 
  620         return (0);
  621 }
  622 
  623 static int
  624 bfe_miibus_readreg(device_t dev, int phy, int reg)
  625 {
  626         struct bfe_softc *sc;
  627         u_int32_t ret;
  628 
  629         sc = device_get_softc(dev);
  630         bfe_readphy(sc, reg, &ret);
  631 
  632         return (ret);
  633 }
  634 
  635 static int
  636 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
  637 {
  638         struct bfe_softc *sc;
  639 
  640         sc = device_get_softc(dev);
  641         bfe_writephy(sc, reg, val);
  642 
  643         return (0);
  644 }
  645 
  646 static void
  647 bfe_miibus_statchg(device_t dev)
  648 {
  649         struct bfe_softc *sc;
  650         struct mii_data *mii;
  651         u_int32_t val, flow;
  652 
  653         sc = device_get_softc(dev);
  654         mii = device_get_softc(sc->bfe_miibus);
  655 
  656         sc->bfe_flags &= ~BFE_FLAG_LINK;
  657         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
  658             (IFM_ACTIVE | IFM_AVALID)) {
  659                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
  660                 case IFM_10_T:
  661                 case IFM_100_TX:
  662                         sc->bfe_flags |= BFE_FLAG_LINK;
  663                         break;
  664                 default:
  665                         break;
  666                 }
  667         }
  668 
  669         /* XXX Should stop Rx/Tx engine prior to touching MAC. */
  670         val = CSR_READ_4(sc, BFE_TX_CTRL);
  671         val &= ~BFE_TX_DUPLEX;
  672         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
  673                 val |= BFE_TX_DUPLEX;
  674                 flow = 0;
  675 #ifdef notyet
  676                 flow = CSR_READ_4(sc, BFE_RXCONF);
  677                 flow &= ~BFE_RXCONF_FLOW;
  678                 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
  679                     IFM_ETH_RXPAUSE) != 0)
  680                         flow |= BFE_RXCONF_FLOW;
  681                 CSR_WRITE_4(sc, BFE_RXCONF, flow);
  682                 /*
  683                  * It seems that the hardware has Tx pause issues
  684                  * so enable only Rx pause.
  685                  */
  686                 flow = CSR_READ_4(sc, BFE_MAC_FLOW);
  687                 flow &= ~BFE_FLOW_PAUSE_ENAB;
  688                 CSR_WRITE_4(sc, BFE_MAC_FLOW, flow);
  689 #endif
  690         }
  691         CSR_WRITE_4(sc, BFE_TX_CTRL, val);
  692 }
  693 
  694 static void
  695 bfe_tx_ring_free(struct bfe_softc *sc)
  696 {
  697         int i;
  698 
  699         for(i = 0; i < BFE_TX_LIST_CNT; i++) {
  700                 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
  701                         bus_dmamap_sync(sc->bfe_txmbuf_tag,
  702                             sc->bfe_tx_ring[i].bfe_map, BUS_DMASYNC_POSTWRITE);
  703                         bus_dmamap_unload(sc->bfe_txmbuf_tag,
  704                             sc->bfe_tx_ring[i].bfe_map);
  705                         m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
  706                         sc->bfe_tx_ring[i].bfe_mbuf = NULL;
  707                 }
  708         }
  709         bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
  710         bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
  711             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
  712 }
  713 
  714 static void
  715 bfe_rx_ring_free(struct bfe_softc *sc)
  716 {
  717         int i;
  718 
  719         for (i = 0; i < BFE_RX_LIST_CNT; i++) {
  720                 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
  721                         bus_dmamap_sync(sc->bfe_rxmbuf_tag,
  722                             sc->bfe_rx_ring[i].bfe_map, BUS_DMASYNC_POSTREAD);
  723                         bus_dmamap_unload(sc->bfe_rxmbuf_tag,
  724                             sc->bfe_rx_ring[i].bfe_map);
  725                         m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
  726                         sc->bfe_rx_ring[i].bfe_mbuf = NULL;
  727                 }
  728         }
  729         bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
  730         bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
  731             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
  732 }
  733 
  734 static int
  735 bfe_list_rx_init(struct bfe_softc *sc)
  736 {
  737         struct bfe_rx_data *rd;
  738         int i;
  739 
  740         sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
  741         bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
  742         for (i = 0; i < BFE_RX_LIST_CNT; i++) {
  743                 rd = &sc->bfe_rx_ring[i];
  744                 rd->bfe_mbuf = NULL;
  745                 rd->bfe_ctrl = 0;
  746                 if (bfe_list_newbuf(sc, i) != 0)
  747                         return (ENOBUFS);
  748         }
  749 
  750         bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
  751             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
  752         CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
  753 
  754         return (0);
  755 }
  756 
  757 static void
  758 bfe_list_tx_init(struct bfe_softc *sc)
  759 {
  760         int i;
  761 
  762         sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
  763         bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
  764         for (i = 0; i < BFE_TX_LIST_CNT; i++)
  765                 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
  766 
  767         bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
  768             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
  769 }
  770 
  771 static void
  772 bfe_discard_buf(struct bfe_softc *sc, int c)
  773 {
  774         struct bfe_rx_data *r;
  775         struct bfe_desc *d;
  776 
  777         r = &sc->bfe_rx_ring[c];
  778         d = &sc->bfe_rx_list[c];
  779         d->bfe_ctrl = htole32(r->bfe_ctrl);
  780 }
  781 
  782 static int
  783 bfe_list_newbuf(struct bfe_softc *sc, int c)
  784 {
  785         struct bfe_rxheader *rx_header;
  786         struct bfe_desc *d;
  787         struct bfe_rx_data *r;
  788         struct mbuf *m;
  789         bus_dma_segment_t segs[1];
  790         bus_dmamap_t map;
  791         u_int32_t ctrl;
  792         int nsegs;
  793 
  794         m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
  795         m->m_len = m->m_pkthdr.len = MCLBYTES;
  796 
  797         if (bus_dmamap_load_mbuf_sg(sc->bfe_rxmbuf_tag, sc->bfe_rx_sparemap,
  798             m, segs, &nsegs, 0) != 0) {
  799                 m_freem(m);
  800                 return (ENOBUFS);
  801         }
  802 
  803         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
  804         r = &sc->bfe_rx_ring[c];
  805         if (r->bfe_mbuf != NULL) {
  806                 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map,
  807                     BUS_DMASYNC_POSTREAD);
  808                 bus_dmamap_unload(sc->bfe_rxmbuf_tag, r->bfe_map);
  809         }
  810         map = r->bfe_map;
  811         r->bfe_map = sc->bfe_rx_sparemap;
  812         sc->bfe_rx_sparemap = map;
  813         r->bfe_mbuf = m;
  814 
  815         rx_header = mtod(m, struct bfe_rxheader *);
  816         rx_header->len = 0;
  817         rx_header->flags = 0;
  818         bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, BUS_DMASYNC_PREREAD);
  819         
  820         ctrl = segs[0].ds_len & BFE_DESC_LEN;
  821         KASSERT(ctrl > ETHER_MAX_LEN + 32, ("%s: buffer size too small(%d)!",
  822             __func__, ctrl));
  823         if (c == BFE_RX_LIST_CNT - 1)
  824                 ctrl |= BFE_DESC_EOT;
  825         r->bfe_ctrl = ctrl;
  826 
  827         d = &sc->bfe_rx_list[c];
  828         d->bfe_ctrl = htole32(ctrl);
  829         /* The chip needs all addresses to be added to BFE_PCI_DMA. */
  830         d->bfe_addr = htole32(BFE_ADDR_LO(segs[0].ds_addr) + BFE_PCI_DMA);
  831 
  832         return (0);
  833 }
  834 
  835 static void
  836 bfe_get_config(struct bfe_softc *sc)
  837 {
  838         u_int8_t eeprom[128];
  839 
  840         bfe_read_eeprom(sc, eeprom);
  841 
  842         sc->bfe_enaddr[0] = eeprom[79];
  843         sc->bfe_enaddr[1] = eeprom[78];
  844         sc->bfe_enaddr[2] = eeprom[81];
  845         sc->bfe_enaddr[3] = eeprom[80];
  846         sc->bfe_enaddr[4] = eeprom[83];
  847         sc->bfe_enaddr[5] = eeprom[82];
  848 
  849         sc->bfe_phyaddr = eeprom[90] & 0x1f;
  850         sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
  851 
  852         sc->bfe_core_unit = 0;
  853         sc->bfe_dma_offset = BFE_PCI_DMA;
  854 }
  855 
  856 static void
  857 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores)
  858 {
  859         u_int32_t bar_orig, pci_rev, val;
  860 
  861         bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
  862         pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
  863         pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
  864 
  865         val = CSR_READ_4(sc, BFE_SBINTVEC);
  866         val |= cores;
  867         CSR_WRITE_4(sc, BFE_SBINTVEC, val);
  868 
  869         val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
  870         val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
  871         CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
  872 
  873         pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
  874 }
  875 
  876 static void
  877 bfe_clear_stats(struct bfe_softc *sc)
  878 {
  879         uint32_t reg;
  880 
  881         BFE_LOCK_ASSERT(sc);
  882 
  883         CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
  884         for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
  885                 CSR_READ_4(sc, reg);
  886         for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
  887                 CSR_READ_4(sc, reg);
  888 }
  889 
  890 static int
  891 bfe_resetphy(struct bfe_softc *sc)
  892 {
  893         u_int32_t val;
  894 
  895         bfe_writephy(sc, 0, BMCR_RESET);
  896         DELAY(100);
  897         bfe_readphy(sc, 0, &val);
  898         if (val & BMCR_RESET) {
  899                 device_printf(sc->bfe_dev, "PHY Reset would not complete.\n");
  900                 return (ENXIO);
  901         }
  902         return (0);
  903 }
  904 
  905 static void
  906 bfe_chip_halt(struct bfe_softc *sc)
  907 {
  908         BFE_LOCK_ASSERT(sc);
  909         /* disable interrupts - not that it actually does..*/
  910         CSR_WRITE_4(sc, BFE_IMASK, 0);
  911         CSR_READ_4(sc, BFE_IMASK);
  912 
  913         CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
  914         bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
  915 
  916         CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
  917         CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
  918         DELAY(10);
  919 }
  920 
  921 static void
  922 bfe_chip_reset(struct bfe_softc *sc)
  923 {
  924         u_int32_t val;
  925 
  926         BFE_LOCK_ASSERT(sc);
  927 
  928         /* Set the interrupt vector for the enet core */
  929         bfe_pci_setup(sc, BFE_INTVEC_ENET0);
  930 
  931         /* is core up? */
  932         val = CSR_READ_4(sc, BFE_SBTMSLOW) &
  933             (BFE_RESET | BFE_REJECT | BFE_CLOCK);
  934         if (val == BFE_CLOCK) {
  935                 /* It is, so shut it down */
  936                 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
  937                 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
  938                 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
  939                 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
  940                 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
  941                         bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE,
  942                             100, 0);
  943                 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
  944         }
  945 
  946         bfe_core_reset(sc);
  947         bfe_clear_stats(sc);
  948 
  949         /*
  950          * We want the phy registers to be accessible even when
  951          * the driver is "downed" so initialize MDC preamble, frequency,
  952          * and whether internal or external phy here.
  953          */
  954 
  955         /* 4402 has 62.5Mhz SB clock and internal phy */
  956         CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
  957 
  958         /* Internal or external PHY? */
  959         val = CSR_READ_4(sc, BFE_DEVCTRL);
  960         if (!(val & BFE_IPP))
  961                 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
  962         else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
  963                 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
  964                 DELAY(100);
  965         }
  966 
  967         /* Enable CRC32 generation and set proper LED modes */
  968         BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
  969 
  970         /* Reset or clear powerdown control bit  */
  971         BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
  972 
  973         CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
  974                                 BFE_LAZY_FC_MASK));
  975 
  976         /*
  977          * We don't want lazy interrupts, so just send them at
  978          * the end of a frame, please
  979          */
  980         BFE_OR(sc, BFE_RCV_LAZY, 0);
  981 
  982         /* Set max lengths, accounting for VLAN tags */
  983         CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
  984         CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
  985 
  986         /* Set watermark XXX - magic */
  987         CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
  988 
  989         /*
  990          * Initialise DMA channels
  991          * - not forgetting dma addresses need to be added to BFE_PCI_DMA
  992          */
  993         CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
  994         CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
  995 
  996         CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
  997                         BFE_RX_CTRL_ENABLE);
  998         CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
  999 
 1000         bfe_resetphy(sc);
 1001         bfe_setupphy(sc);
 1002 }
 1003 
 1004 static void
 1005 bfe_core_disable(struct bfe_softc *sc)
 1006 {
 1007         if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
 1008                 return;
 1009 
 1010         /*
 1011          * Set reject, wait for it set, then wait for the core to stop
 1012          * being busy, then set reset and reject and enable the clocks.
 1013          */
 1014         CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
 1015         bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
 1016         bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
 1017         CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
 1018                                 BFE_RESET));
 1019         CSR_READ_4(sc, BFE_SBTMSLOW);
 1020         DELAY(10);
 1021         /* Leave reset and reject set */
 1022         CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
 1023         DELAY(10);
 1024 }
 1025 
 1026 static void
 1027 bfe_core_reset(struct bfe_softc *sc)
 1028 {
 1029         u_int32_t val;
 1030 
 1031         /* Disable the core */
 1032         bfe_core_disable(sc);
 1033 
 1034         /* and bring it back up */
 1035         CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
 1036         CSR_READ_4(sc, BFE_SBTMSLOW);
 1037         DELAY(10);
 1038 
 1039         /* Chip bug, clear SERR, IB and TO if they are set. */
 1040         if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
 1041                 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
 1042         val = CSR_READ_4(sc, BFE_SBIMSTATE);
 1043         if (val & (BFE_IBE | BFE_TO))
 1044                 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
 1045 
 1046         /* Clear reset and allow it to move through the core */
 1047         CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
 1048         CSR_READ_4(sc, BFE_SBTMSLOW);
 1049         DELAY(10);
 1050 
 1051         /* Leave the clock set */
 1052         CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
 1053         CSR_READ_4(sc, BFE_SBTMSLOW);
 1054         DELAY(10);
 1055 }
 1056 
 1057 static void
 1058 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
 1059 {
 1060         u_int32_t val;
 1061 
 1062         val  = ((u_int32_t) data[2]) << 24;
 1063         val |= ((u_int32_t) data[3]) << 16;
 1064         val |= ((u_int32_t) data[4]) <<  8;
 1065         val |= ((u_int32_t) data[5]);
 1066         CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
 1067         val = (BFE_CAM_HI_VALID |
 1068                         (((u_int32_t) data[0]) << 8) |
 1069                         (((u_int32_t) data[1])));
 1070         CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
 1071         CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
 1072                                 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT)));
 1073         bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
 1074 }
 1075 
 1076 static void
 1077 bfe_set_rx_mode(struct bfe_softc *sc)
 1078 {
 1079         struct ifnet *ifp = sc->bfe_ifp;
 1080         struct ifmultiaddr  *ifma;
 1081         u_int32_t val;
 1082         int i = 0;
 1083 
 1084         BFE_LOCK_ASSERT(sc);
 1085 
 1086         val = CSR_READ_4(sc, BFE_RXCONF);
 1087 
 1088         if (ifp->if_flags & IFF_PROMISC)
 1089                 val |= BFE_RXCONF_PROMISC;
 1090         else
 1091                 val &= ~BFE_RXCONF_PROMISC;
 1092 
 1093         if (ifp->if_flags & IFF_BROADCAST)
 1094                 val &= ~BFE_RXCONF_DBCAST;
 1095         else
 1096                 val |= BFE_RXCONF_DBCAST;
 1097 
 1098 
 1099         CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
 1100         bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++);
 1101 
 1102         if (ifp->if_flags & IFF_ALLMULTI)
 1103                 val |= BFE_RXCONF_ALLMULTI;
 1104         else {
 1105                 val &= ~BFE_RXCONF_ALLMULTI;
 1106                 if_maddr_rlock(ifp);
 1107                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 1108                         if (ifma->ifma_addr->sa_family != AF_LINK)
 1109                                 continue;
 1110                         bfe_cam_write(sc,
 1111                             LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++);
 1112                 }
 1113                 if_maddr_runlock(ifp);
 1114         }
 1115 
 1116         CSR_WRITE_4(sc, BFE_RXCONF, val);
 1117         BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
 1118 }
 1119 
 1120 static void
 1121 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 1122 {
 1123         struct bfe_dmamap_arg *ctx;
 1124 
 1125         if (error != 0)
 1126                 return;
 1127 
 1128         KASSERT(nseg == 1, ("%s : %d segments returned!", __func__, nseg));
 1129 
 1130         ctx = (struct bfe_dmamap_arg *)arg;
 1131         ctx->bfe_busaddr = segs[0].ds_addr;
 1132 }
 1133 
 1134 static void
 1135 bfe_release_resources(struct bfe_softc *sc)
 1136 {
 1137 
 1138         if (sc->bfe_intrhand != NULL)
 1139                 bus_teardown_intr(sc->bfe_dev, sc->bfe_irq, sc->bfe_intrhand);
 1140 
 1141         if (sc->bfe_irq != NULL)
 1142                 bus_release_resource(sc->bfe_dev, SYS_RES_IRQ, 0, sc->bfe_irq);
 1143 
 1144         if (sc->bfe_res != NULL)
 1145                 bus_release_resource(sc->bfe_dev, SYS_RES_MEMORY, PCIR_BAR(0),
 1146                     sc->bfe_res);
 1147 
 1148         if (sc->bfe_ifp != NULL)
 1149                 if_free(sc->bfe_ifp);
 1150 }
 1151 
 1152 static void
 1153 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data)
 1154 {
 1155         long i;
 1156         u_int16_t *ptr = (u_int16_t *)data;
 1157 
 1158         for(i = 0; i < 128; i += 2)
 1159                 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
 1160 }
 1161 
 1162 static int
 1163 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit,
 1164                 u_long timeout, const int clear)
 1165 {
 1166         u_long i;
 1167 
 1168         for (i = 0; i < timeout; i++) {
 1169                 u_int32_t val = CSR_READ_4(sc, reg);
 1170 
 1171                 if (clear && !(val & bit))
 1172                         break;
 1173                 if (!clear && (val & bit))
 1174                         break;
 1175                 DELAY(10);
 1176         }
 1177         if (i == timeout) {
 1178                 device_printf(sc->bfe_dev,
 1179                     "BUG!  Timeout waiting for bit %08x of register "
 1180                     "%x to %s.\n", bit, reg, (clear ? "clear" : "set"));
 1181                 return (-1);
 1182         }
 1183         return (0);
 1184 }
 1185 
 1186 static int
 1187 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val)
 1188 {
 1189         int err;
 1190 
 1191         /* Clear MII ISR */
 1192         CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
 1193         CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
 1194                                 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
 1195                                 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
 1196                                 (reg << BFE_MDIO_RA_SHIFT) |
 1197                                 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
 1198         err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
 1199         *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
 1200 
 1201         return (err);
 1202 }
 1203 
 1204 static int
 1205 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val)
 1206 {
 1207         int status;
 1208 
 1209         CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
 1210         CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
 1211                                 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
 1212                                 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
 1213                                 (reg << BFE_MDIO_RA_SHIFT) |
 1214                                 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
 1215                                 (val & BFE_MDIO_DATA_DATA)));
 1216         status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
 1217 
 1218         return (status);
 1219 }
 1220 
 1221 /*
 1222  * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
 1223  * twice
 1224  */
 1225 static int
 1226 bfe_setupphy(struct bfe_softc *sc)
 1227 {
 1228         u_int32_t val;
 1229 
 1230         /* Enable activity LED */
 1231         bfe_readphy(sc, 26, &val);
 1232         bfe_writephy(sc, 26, val & 0x7fff);
 1233         bfe_readphy(sc, 26, &val);
 1234 
 1235         /* Enable traffic meter LED mode */
 1236         bfe_readphy(sc, 27, &val);
 1237         bfe_writephy(sc, 27, val | (1 << 6));
 1238 
 1239         return (0);
 1240 }
 1241 
 1242 static void
 1243 bfe_stats_update(struct bfe_softc *sc)
 1244 {
 1245         struct bfe_hw_stats *stats;
 1246         struct ifnet *ifp;
 1247         uint32_t mib[BFE_MIB_CNT];
 1248         uint32_t reg, *val;
 1249 
 1250         BFE_LOCK_ASSERT(sc);
 1251 
 1252         val = mib;
 1253         CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
 1254         for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
 1255                 *val++ = CSR_READ_4(sc, reg);
 1256         for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
 1257                 *val++ = CSR_READ_4(sc, reg);
 1258 
 1259         ifp = sc->bfe_ifp;
 1260         stats = &sc->bfe_stats;
 1261         /* Tx stat. */
 1262         stats->tx_good_octets += mib[MIB_TX_GOOD_O];
 1263         stats->tx_good_frames += mib[MIB_TX_GOOD_P];
 1264         stats->tx_octets += mib[MIB_TX_O];
 1265         stats->tx_frames += mib[MIB_TX_P];
 1266         stats->tx_bcast_frames += mib[MIB_TX_BCAST];
 1267         stats->tx_mcast_frames += mib[MIB_TX_MCAST];
 1268         stats->tx_pkts_64 += mib[MIB_TX_64];
 1269         stats->tx_pkts_65_127 += mib[MIB_TX_65_127];
 1270         stats->tx_pkts_128_255 += mib[MIB_TX_128_255];
 1271         stats->tx_pkts_256_511 += mib[MIB_TX_256_511];
 1272         stats->tx_pkts_512_1023 += mib[MIB_TX_512_1023];
 1273         stats->tx_pkts_1024_max += mib[MIB_TX_1024_MAX];
 1274         stats->tx_jabbers += mib[MIB_TX_JABBER];
 1275         stats->tx_oversize_frames += mib[MIB_TX_OSIZE];
 1276         stats->tx_frag_frames += mib[MIB_TX_FRAG];
 1277         stats->tx_underruns += mib[MIB_TX_URUNS];
 1278         stats->tx_colls += mib[MIB_TX_TCOLS];
 1279         stats->tx_single_colls += mib[MIB_TX_SCOLS];
 1280         stats->tx_multi_colls += mib[MIB_TX_MCOLS];
 1281         stats->tx_excess_colls += mib[MIB_TX_ECOLS];
 1282         stats->tx_late_colls += mib[MIB_TX_LCOLS];
 1283         stats->tx_deferrals += mib[MIB_TX_DEFERED];
 1284         stats->tx_carrier_losts += mib[MIB_TX_CLOST];
 1285         stats->tx_pause_frames += mib[MIB_TX_PAUSE];
 1286         /* Rx stat. */
 1287         stats->rx_good_octets += mib[MIB_RX_GOOD_O];
 1288         stats->rx_good_frames += mib[MIB_RX_GOOD_P];
 1289         stats->rx_octets += mib[MIB_RX_O];
 1290         stats->rx_frames += mib[MIB_RX_P];
 1291         stats->rx_bcast_frames += mib[MIB_RX_BCAST];
 1292         stats->rx_mcast_frames += mib[MIB_RX_MCAST];
 1293         stats->rx_pkts_64 += mib[MIB_RX_64];
 1294         stats->rx_pkts_65_127 += mib[MIB_RX_65_127];
 1295         stats->rx_pkts_128_255 += mib[MIB_RX_128_255];
 1296         stats->rx_pkts_256_511 += mib[MIB_RX_256_511];
 1297         stats->rx_pkts_512_1023 += mib[MIB_RX_512_1023];
 1298         stats->rx_pkts_1024_max += mib[MIB_RX_1024_MAX];
 1299         stats->rx_jabbers += mib[MIB_RX_JABBER];
 1300         stats->rx_oversize_frames += mib[MIB_RX_OSIZE];
 1301         stats->rx_frag_frames += mib[MIB_RX_FRAG];
 1302         stats->rx_missed_frames += mib[MIB_RX_MISS];
 1303         stats->rx_crc_align_errs += mib[MIB_RX_CRCA];
 1304         stats->rx_runts += mib[MIB_RX_USIZE];
 1305         stats->rx_crc_errs += mib[MIB_RX_CRC];
 1306         stats->rx_align_errs += mib[MIB_RX_ALIGN];
 1307         stats->rx_symbol_errs += mib[MIB_RX_SYM];
 1308         stats->rx_pause_frames += mib[MIB_RX_PAUSE];
 1309         stats->rx_control_frames += mib[MIB_RX_NPAUSE];
 1310 
 1311         /* Update counters in ifnet. */
 1312         ifp->if_opackets += (u_long)mib[MIB_TX_GOOD_P];
 1313         ifp->if_collisions += (u_long)mib[MIB_TX_TCOLS];
 1314         ifp->if_oerrors += (u_long)mib[MIB_TX_URUNS] +
 1315             (u_long)mib[MIB_TX_ECOLS] +
 1316             (u_long)mib[MIB_TX_DEFERED] +
 1317             (u_long)mib[MIB_TX_CLOST];
 1318 
 1319         ifp->if_ipackets += (u_long)mib[MIB_RX_GOOD_P];
 1320 
 1321         ifp->if_ierrors += mib[MIB_RX_JABBER] +
 1322             mib[MIB_RX_MISS] +
 1323             mib[MIB_RX_CRCA] +
 1324             mib[MIB_RX_USIZE] +
 1325             mib[MIB_RX_CRC] +
 1326             mib[MIB_RX_ALIGN] +
 1327             mib[MIB_RX_SYM];
 1328 }
 1329 
 1330 static void
 1331 bfe_txeof(struct bfe_softc *sc)
 1332 {
 1333         struct bfe_tx_data *r;
 1334         struct ifnet *ifp;
 1335         int i, chipidx;
 1336 
 1337         BFE_LOCK_ASSERT(sc);
 1338 
 1339         ifp = sc->bfe_ifp;
 1340 
 1341         chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
 1342         chipidx /= sizeof(struct bfe_desc);
 1343 
 1344         i = sc->bfe_tx_cons;
 1345         if (i == chipidx)
 1346                 return;
 1347         bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
 1348             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 1349         /* Go through the mbufs and free those that have been transmitted */
 1350         for (; i != chipidx; BFE_INC(i, BFE_TX_LIST_CNT)) {
 1351                 r = &sc->bfe_tx_ring[i];
 1352                 sc->bfe_tx_cnt--;
 1353                 if (r->bfe_mbuf == NULL)
 1354                         continue;
 1355                 bus_dmamap_sync(sc->bfe_txmbuf_tag, r->bfe_map,
 1356                     BUS_DMASYNC_POSTWRITE);
 1357                 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
 1358 
 1359                 m_freem(r->bfe_mbuf);
 1360                 r->bfe_mbuf = NULL;
 1361         }
 1362 
 1363         if (i != sc->bfe_tx_cons) {
 1364                 /* we freed up some mbufs */
 1365                 sc->bfe_tx_cons = i;
 1366                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 1367         }
 1368 
 1369         if (sc->bfe_tx_cnt == 0)
 1370                 sc->bfe_watchdog_timer = 0;
 1371 }
 1372 
 1373 /* Pass a received packet up the stack */
 1374 static void
 1375 bfe_rxeof(struct bfe_softc *sc)
 1376 {
 1377         struct mbuf *m;
 1378         struct ifnet *ifp;
 1379         struct bfe_rxheader *rxheader;
 1380         struct bfe_rx_data *r;
 1381         int cons, prog;
 1382         u_int32_t status, current, len, flags;
 1383 
 1384         BFE_LOCK_ASSERT(sc);
 1385         cons = sc->bfe_rx_cons;
 1386         status = CSR_READ_4(sc, BFE_DMARX_STAT);
 1387         current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
 1388 
 1389         ifp = sc->bfe_ifp;
 1390 
 1391         bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
 1392             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 1393 
 1394         for (prog = 0; current != cons; prog++,
 1395             BFE_INC(cons, BFE_RX_LIST_CNT)) {
 1396                 r = &sc->bfe_rx_ring[cons];
 1397                 m = r->bfe_mbuf;
 1398                 /*
 1399                  * Rx status should be read from mbuf such that we can't
 1400                  * delay bus_dmamap_sync(9). This hardware limiation
 1401                  * results in inefficent mbuf usage as bfe(4) couldn't
 1402                  * reuse mapped buffer from errored frame. 
 1403                  */
 1404                 if (bfe_list_newbuf(sc, cons) != 0) {
 1405                         ifp->if_iqdrops++;
 1406                         bfe_discard_buf(sc, cons);
 1407                         continue;
 1408                 }
 1409                 rxheader = mtod(m, struct bfe_rxheader*);
 1410                 len = le16toh(rxheader->len);
 1411                 flags = le16toh(rxheader->flags);
 1412 
 1413                 /* Remove CRC bytes. */
 1414                 len -= ETHER_CRC_LEN;
 1415 
 1416                 /* flag an error and try again */
 1417                 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
 1418                         m_freem(m);
 1419                         continue;
 1420                 }
 1421 
 1422                 /* Make sure to skip header bytes written by hardware. */
 1423                 m_adj(m, BFE_RX_OFFSET);
 1424                 m->m_len = m->m_pkthdr.len = len;
 1425 
 1426                 m->m_pkthdr.rcvif = ifp;
 1427                 BFE_UNLOCK(sc);
 1428                 (*ifp->if_input)(ifp, m);
 1429                 BFE_LOCK(sc);
 1430         }
 1431 
 1432         if (prog > 0) {
 1433                 sc->bfe_rx_cons = cons;
 1434                 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
 1435                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 1436         }
 1437 }
 1438 
 1439 static void
 1440 bfe_intr(void *xsc)
 1441 {
 1442         struct bfe_softc *sc = xsc;
 1443         struct ifnet *ifp;
 1444         u_int32_t istat;
 1445 
 1446         ifp = sc->bfe_ifp;
 1447 
 1448         BFE_LOCK(sc);
 1449 
 1450         istat = CSR_READ_4(sc, BFE_ISTAT);
 1451 
 1452         /*
 1453          * Defer unsolicited interrupts - This is necessary because setting the
 1454          * chips interrupt mask register to 0 doesn't actually stop the
 1455          * interrupts
 1456          */
 1457         istat &= BFE_IMASK_DEF;
 1458         CSR_WRITE_4(sc, BFE_ISTAT, istat);
 1459         CSR_READ_4(sc, BFE_ISTAT);
 1460 
 1461         /* not expecting this interrupt, disregard it */
 1462         if (istat == 0 || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
 1463                 BFE_UNLOCK(sc);
 1464                 return;
 1465         }
 1466 
 1467         /* A packet was received */
 1468         if (istat & BFE_ISTAT_RX)
 1469                 bfe_rxeof(sc);
 1470 
 1471         /* A packet was sent */
 1472         if (istat & BFE_ISTAT_TX)
 1473                 bfe_txeof(sc);
 1474 
 1475         if (istat & BFE_ISTAT_ERRORS) {
 1476 
 1477                 if (istat & BFE_ISTAT_DSCE) {
 1478                         device_printf(sc->bfe_dev, "Descriptor Error\n");
 1479                         bfe_stop(sc);
 1480                         BFE_UNLOCK(sc);
 1481                         return;
 1482                 }
 1483 
 1484                 if (istat & BFE_ISTAT_DPE) {
 1485                         device_printf(sc->bfe_dev,
 1486                             "Descriptor Protocol Error\n");
 1487                         bfe_stop(sc);
 1488                         BFE_UNLOCK(sc);
 1489                         return;
 1490                 }
 1491                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 1492                 bfe_init_locked(sc);
 1493         }
 1494 
 1495         /* We have packets pending, fire them out */
 1496         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
 1497                 bfe_start_locked(ifp);
 1498 
 1499         BFE_UNLOCK(sc);
 1500 }
 1501 
 1502 static int
 1503 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head)
 1504 {
 1505         struct bfe_desc *d;
 1506         struct bfe_tx_data *r, *r1;
 1507         struct mbuf *m;
 1508         bus_dmamap_t map;
 1509         bus_dma_segment_t txsegs[BFE_MAXTXSEGS];
 1510         uint32_t cur, si;
 1511         int error, i, nsegs;
 1512 
 1513         BFE_LOCK_ASSERT(sc);
 1514 
 1515         M_ASSERTPKTHDR((*m_head));
 1516 
 1517         si = cur = sc->bfe_tx_prod;
 1518         r = &sc->bfe_tx_ring[cur];
 1519         error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, *m_head,
 1520             txsegs, &nsegs, 0);
 1521         if (error == EFBIG) {
 1522                 m = m_collapse(*m_head, M_NOWAIT, BFE_MAXTXSEGS);
 1523                 if (m == NULL) {
 1524                         m_freem(*m_head);
 1525                         *m_head = NULL;
 1526                         return (ENOMEM);
 1527                 }
 1528                 *m_head = m;
 1529                 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map,
 1530                     *m_head, txsegs, &nsegs, 0);
 1531                 if (error != 0) {
 1532                         m_freem(*m_head);
 1533                         *m_head = NULL;
 1534                         return (error);
 1535                 }
 1536         } else if (error != 0)
 1537                 return (error);
 1538         if (nsegs == 0) {
 1539                 m_freem(*m_head);
 1540                 *m_head = NULL;
 1541                 return (EIO);
 1542         }
 1543 
 1544         if (sc->bfe_tx_cnt + nsegs > BFE_TX_LIST_CNT - 1) {
 1545                 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
 1546                 return (ENOBUFS);
 1547         }
 1548 
 1549         for (i = 0; i < nsegs; i++) {
 1550                 d = &sc->bfe_tx_list[cur];
 1551                 d->bfe_ctrl = htole32(txsegs[i].ds_len & BFE_DESC_LEN);
 1552                 d->bfe_ctrl |= htole32(BFE_DESC_IOC);
 1553                 if (cur == BFE_TX_LIST_CNT - 1)
 1554                         /*
 1555                          * Tell the chip to wrap to the start of
 1556                          * the descriptor list.
 1557                          */
 1558                         d->bfe_ctrl |= htole32(BFE_DESC_EOT);
 1559                 /* The chip needs all addresses to be added to BFE_PCI_DMA. */
 1560                 d->bfe_addr = htole32(BFE_ADDR_LO(txsegs[i].ds_addr) +
 1561                     BFE_PCI_DMA);
 1562                 BFE_INC(cur, BFE_TX_LIST_CNT);
 1563         }
 1564 
 1565         /* Update producer index. */
 1566         sc->bfe_tx_prod = cur;
 1567 
 1568         /* Set EOF on the last descriptor. */
 1569         cur = (cur + BFE_TX_LIST_CNT - 1) % BFE_TX_LIST_CNT;
 1570         d = &sc->bfe_tx_list[cur];
 1571         d->bfe_ctrl |= htole32(BFE_DESC_EOF);
 1572 
 1573         /* Lastly set SOF on the first descriptor to avoid races. */
 1574         d = &sc->bfe_tx_list[si];
 1575         d->bfe_ctrl |= htole32(BFE_DESC_SOF);
 1576 
 1577         r1 = &sc->bfe_tx_ring[cur];
 1578         map = r->bfe_map;
 1579         r->bfe_map = r1->bfe_map;
 1580         r1->bfe_map = map;
 1581         r1->bfe_mbuf = *m_head;
 1582         sc->bfe_tx_cnt += nsegs;
 1583 
 1584         bus_dmamap_sync(sc->bfe_txmbuf_tag, map, BUS_DMASYNC_PREWRITE);
 1585 
 1586         return (0);
 1587 }
 1588 
 1589 /*
 1590  * Set up to transmit a packet.
 1591  */
 1592 static void
 1593 bfe_start(struct ifnet *ifp)
 1594 {
 1595         BFE_LOCK((struct bfe_softc *)ifp->if_softc);
 1596         bfe_start_locked(ifp);
 1597         BFE_UNLOCK((struct bfe_softc *)ifp->if_softc);
 1598 }
 1599 
 1600 /*
 1601  * Set up to transmit a packet. The softc is already locked.
 1602  */
 1603 static void
 1604 bfe_start_locked(struct ifnet *ifp)
 1605 {
 1606         struct bfe_softc *sc;
 1607         struct mbuf *m_head;
 1608         int queued;
 1609 
 1610         sc = ifp->if_softc;
 1611 
 1612         BFE_LOCK_ASSERT(sc);
 1613 
 1614         /*
 1615          * Not much point trying to send if the link is down
 1616          * or we have nothing to send.
 1617          */
 1618         if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
 1619             IFF_DRV_RUNNING || (sc->bfe_flags & BFE_FLAG_LINK) == 0)
 1620                 return;
 1621 
 1622         for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
 1623             sc->bfe_tx_cnt < BFE_TX_LIST_CNT - 1;) {
 1624                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
 1625                 if (m_head == NULL)
 1626                         break;
 1627 
 1628                 /*
 1629                  * Pack the data into the tx ring.  If we dont have
 1630                  * enough room, let the chip drain the ring.
 1631                  */
 1632                 if (bfe_encap(sc, &m_head)) {
 1633                         if (m_head == NULL)
 1634                                 break;
 1635                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
 1636                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 1637                         break;
 1638                 }
 1639 
 1640                 queued++;
 1641 
 1642                 /*
 1643                  * If there's a BPF listener, bounce a copy of this frame
 1644                  * to him.
 1645                  */
 1646                 BPF_MTAP(ifp, m_head);
 1647         }
 1648 
 1649         if (queued) {
 1650                 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
 1651                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 1652                 /* Transmit - twice due to apparent hardware bug */
 1653                 CSR_WRITE_4(sc, BFE_DMATX_PTR,
 1654                     sc->bfe_tx_prod * sizeof(struct bfe_desc));
 1655                 /*
 1656                  * XXX It seems the following write is not necessary
 1657                  * to kick Tx command. What might be required would be
 1658                  * a way flushing PCI posted write. Reading the register
 1659                  * back ensures the flush operation. In addition,
 1660                  * hardware will execute PCI posted write in the long
 1661                  * run and watchdog timer for the kick command was set
 1662                  * to 5 seconds. Therefore I think the second write
 1663                  * access is not necessary or could be replaced with
 1664                  * read operation.
 1665                  */
 1666                 CSR_WRITE_4(sc, BFE_DMATX_PTR,
 1667                     sc->bfe_tx_prod * sizeof(struct bfe_desc));
 1668 
 1669                 /*
 1670                  * Set a timeout in case the chip goes out to lunch.
 1671                  */
 1672                 sc->bfe_watchdog_timer = 5;
 1673         }
 1674 }
 1675 
 1676 static void
 1677 bfe_init(void *xsc)
 1678 {
 1679         BFE_LOCK((struct bfe_softc *)xsc);
 1680         bfe_init_locked(xsc);
 1681         BFE_UNLOCK((struct bfe_softc *)xsc);
 1682 }
 1683 
 1684 static void
 1685 bfe_init_locked(void *xsc)
 1686 {
 1687         struct bfe_softc *sc = (struct bfe_softc*)xsc;
 1688         struct ifnet *ifp = sc->bfe_ifp;
 1689         struct mii_data *mii;
 1690 
 1691         BFE_LOCK_ASSERT(sc);
 1692 
 1693         mii = device_get_softc(sc->bfe_miibus);
 1694 
 1695         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
 1696                 return;
 1697 
 1698         bfe_stop(sc);
 1699         bfe_chip_reset(sc);
 1700 
 1701         if (bfe_list_rx_init(sc) == ENOBUFS) {
 1702                 device_printf(sc->bfe_dev,
 1703                     "%s: Not enough memory for list buffers\n", __func__);
 1704                 bfe_stop(sc);
 1705                 return;
 1706         }
 1707         bfe_list_tx_init(sc);
 1708 
 1709         bfe_set_rx_mode(sc);
 1710 
 1711         /* Enable the chip and core */
 1712         BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
 1713         /* Enable interrupts */
 1714         CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
 1715 
 1716         /* Clear link state and change media. */
 1717         sc->bfe_flags &= ~BFE_FLAG_LINK;
 1718         mii_mediachg(mii);
 1719 
 1720         ifp->if_drv_flags |= IFF_DRV_RUNNING;
 1721         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 1722 
 1723         callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
 1724 }
 1725 
 1726 /*
 1727  * Set media options.
 1728  */
 1729 static int
 1730 bfe_ifmedia_upd(struct ifnet *ifp)
 1731 {
 1732         struct bfe_softc *sc;
 1733         struct mii_data *mii;
 1734         struct mii_softc *miisc;
 1735         int error;
 1736 
 1737         sc = ifp->if_softc;
 1738         BFE_LOCK(sc);
 1739 
 1740         mii = device_get_softc(sc->bfe_miibus);
 1741         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 1742                 PHY_RESET(miisc);
 1743         error = mii_mediachg(mii);
 1744         BFE_UNLOCK(sc);
 1745 
 1746         return (error);
 1747 }
 1748 
 1749 /*
 1750  * Report current media status.
 1751  */
 1752 static void
 1753 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 1754 {
 1755         struct bfe_softc *sc = ifp->if_softc;
 1756         struct mii_data *mii;
 1757 
 1758         BFE_LOCK(sc);
 1759         mii = device_get_softc(sc->bfe_miibus);
 1760         mii_pollstat(mii);
 1761         ifmr->ifm_active = mii->mii_media_active;
 1762         ifmr->ifm_status = mii->mii_media_status;
 1763         BFE_UNLOCK(sc);
 1764 }
 1765 
 1766 static int
 1767 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 1768 {
 1769         struct bfe_softc *sc = ifp->if_softc;
 1770         struct ifreq *ifr = (struct ifreq *) data;
 1771         struct mii_data *mii;
 1772         int error = 0;
 1773 
 1774         switch (command) {
 1775         case SIOCSIFFLAGS:
 1776                 BFE_LOCK(sc);
 1777                 if (ifp->if_flags & IFF_UP) {
 1778                         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
 1779                                 bfe_set_rx_mode(sc);
 1780                         else if ((sc->bfe_flags & BFE_FLAG_DETACH) == 0)
 1781                                 bfe_init_locked(sc);
 1782                 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
 1783                         bfe_stop(sc);
 1784                 BFE_UNLOCK(sc);
 1785                 break;
 1786         case SIOCADDMULTI:
 1787         case SIOCDELMULTI:
 1788                 BFE_LOCK(sc);
 1789                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
 1790                         bfe_set_rx_mode(sc);
 1791                 BFE_UNLOCK(sc);
 1792                 break;
 1793         case SIOCGIFMEDIA:
 1794         case SIOCSIFMEDIA:
 1795                 mii = device_get_softc(sc->bfe_miibus);
 1796                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
 1797                 break;
 1798         default:
 1799                 error = ether_ioctl(ifp, command, data);
 1800                 break;
 1801         }
 1802 
 1803         return (error);
 1804 }
 1805 
 1806 static void
 1807 bfe_watchdog(struct bfe_softc *sc)
 1808 {
 1809         struct ifnet *ifp;
 1810 
 1811         BFE_LOCK_ASSERT(sc);
 1812 
 1813         if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer)
 1814                 return;
 1815 
 1816         ifp = sc->bfe_ifp;
 1817 
 1818         device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n");
 1819 
 1820         ifp->if_oerrors++;
 1821         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 1822         bfe_init_locked(sc);
 1823 
 1824         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
 1825                 bfe_start_locked(ifp);
 1826 }
 1827 
 1828 static void
 1829 bfe_tick(void *xsc)
 1830 {
 1831         struct bfe_softc *sc = xsc;
 1832         struct mii_data *mii;
 1833 
 1834         BFE_LOCK_ASSERT(sc);
 1835 
 1836         mii = device_get_softc(sc->bfe_miibus);
 1837         mii_tick(mii);
 1838         bfe_stats_update(sc);
 1839         bfe_watchdog(sc);
 1840         callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
 1841 }
 1842 
 1843 /*
 1844  * Stop the adapter and free any mbufs allocated to the
 1845  * RX and TX lists.
 1846  */
 1847 static void
 1848 bfe_stop(struct bfe_softc *sc)
 1849 {
 1850         struct ifnet *ifp;
 1851 
 1852         BFE_LOCK_ASSERT(sc);
 1853 
 1854         ifp = sc->bfe_ifp;
 1855         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
 1856         sc->bfe_flags &= ~BFE_FLAG_LINK;
 1857         callout_stop(&sc->bfe_stat_co);
 1858         sc->bfe_watchdog_timer = 0;
 1859 
 1860         bfe_chip_halt(sc);
 1861         bfe_tx_ring_free(sc);
 1862         bfe_rx_ring_free(sc);
 1863 }
 1864 
 1865 static int
 1866 sysctl_bfe_stats(SYSCTL_HANDLER_ARGS)
 1867 {
 1868         struct bfe_softc *sc;
 1869         struct bfe_hw_stats *stats;
 1870         int error, result;
 1871 
 1872         result = -1;
 1873         error = sysctl_handle_int(oidp, &result, 0, req);
 1874 
 1875         if (error != 0 || req->newptr == NULL)
 1876                 return (error);
 1877 
 1878         if (result != 1)
 1879                 return (error);
 1880 
 1881         sc = (struct bfe_softc *)arg1;
 1882         stats = &sc->bfe_stats;
 1883 
 1884         printf("%s statistics:\n", device_get_nameunit(sc->bfe_dev));
 1885         printf("Transmit good octets : %ju\n",
 1886             (uintmax_t)stats->tx_good_octets);
 1887         printf("Transmit good frames : %ju\n",
 1888             (uintmax_t)stats->tx_good_frames);
 1889         printf("Transmit octets : %ju\n",
 1890             (uintmax_t)stats->tx_octets);
 1891         printf("Transmit frames : %ju\n",
 1892             (uintmax_t)stats->tx_frames);
 1893         printf("Transmit broadcast frames : %ju\n",
 1894             (uintmax_t)stats->tx_bcast_frames);
 1895         printf("Transmit multicast frames : %ju\n",
 1896             (uintmax_t)stats->tx_mcast_frames);
 1897         printf("Transmit frames 64 bytes : %ju\n",
 1898             (uint64_t)stats->tx_pkts_64);
 1899         printf("Transmit frames 65 to 127 bytes : %ju\n",
 1900             (uint64_t)stats->tx_pkts_65_127);
 1901         printf("Transmit frames 128 to 255 bytes : %ju\n",
 1902             (uint64_t)stats->tx_pkts_128_255);
 1903         printf("Transmit frames 256 to 511 bytes : %ju\n",
 1904             (uint64_t)stats->tx_pkts_256_511);
 1905         printf("Transmit frames 512 to 1023 bytes : %ju\n",
 1906             (uint64_t)stats->tx_pkts_512_1023);
 1907         printf("Transmit frames 1024 to max bytes : %ju\n",
 1908             (uint64_t)stats->tx_pkts_1024_max);
 1909         printf("Transmit jabber errors : %u\n", stats->tx_jabbers);
 1910         printf("Transmit oversized frames : %ju\n",
 1911             (uint64_t)stats->tx_oversize_frames);
 1912         printf("Transmit fragmented frames : %ju\n",
 1913             (uint64_t)stats->tx_frag_frames);
 1914         printf("Transmit underruns : %u\n", stats->tx_colls);
 1915         printf("Transmit total collisions : %u\n", stats->tx_single_colls);
 1916         printf("Transmit single collisions : %u\n", stats->tx_single_colls);
 1917         printf("Transmit multiple collisions : %u\n", stats->tx_multi_colls);
 1918         printf("Transmit excess collisions : %u\n", stats->tx_excess_colls);
 1919         printf("Transmit late collisions : %u\n", stats->tx_late_colls);
 1920         printf("Transmit deferrals : %u\n", stats->tx_deferrals);
 1921         printf("Transmit carrier losts : %u\n", stats->tx_carrier_losts);
 1922         printf("Transmit pause frames : %u\n", stats->tx_pause_frames);
 1923 
 1924         printf("Receive good octets : %ju\n",
 1925             (uintmax_t)stats->rx_good_octets);
 1926         printf("Receive good frames : %ju\n",
 1927             (uintmax_t)stats->rx_good_frames);
 1928         printf("Receive octets : %ju\n",
 1929             (uintmax_t)stats->rx_octets);
 1930         printf("Receive frames : %ju\n",
 1931             (uintmax_t)stats->rx_frames);
 1932         printf("Receive broadcast frames : %ju\n",
 1933             (uintmax_t)stats->rx_bcast_frames);
 1934         printf("Receive multicast frames : %ju\n",
 1935             (uintmax_t)stats->rx_mcast_frames);
 1936         printf("Receive frames 64 bytes : %ju\n",
 1937             (uint64_t)stats->rx_pkts_64);
 1938         printf("Receive frames 65 to 127 bytes : %ju\n",
 1939             (uint64_t)stats->rx_pkts_65_127);
 1940         printf("Receive frames 128 to 255 bytes : %ju\n",
 1941             (uint64_t)stats->rx_pkts_128_255);
 1942         printf("Receive frames 256 to 511 bytes : %ju\n",
 1943             (uint64_t)stats->rx_pkts_256_511);
 1944         printf("Receive frames 512 to 1023 bytes : %ju\n",
 1945             (uint64_t)stats->rx_pkts_512_1023);
 1946         printf("Receive frames 1024 to max bytes : %ju\n",
 1947             (uint64_t)stats->rx_pkts_1024_max);
 1948         printf("Receive jabber errors : %u\n", stats->rx_jabbers);
 1949         printf("Receive oversized frames : %ju\n",
 1950             (uint64_t)stats->rx_oversize_frames);
 1951         printf("Receive fragmented frames : %ju\n",
 1952             (uint64_t)stats->rx_frag_frames);
 1953         printf("Receive missed frames : %u\n", stats->rx_missed_frames);
 1954         printf("Receive CRC align errors : %u\n", stats->rx_crc_align_errs);
 1955         printf("Receive undersized frames : %u\n", stats->rx_runts);
 1956         printf("Receive CRC errors : %u\n", stats->rx_crc_errs);
 1957         printf("Receive align errors : %u\n", stats->rx_align_errs);
 1958         printf("Receive symbol errors : %u\n", stats->rx_symbol_errs);
 1959         printf("Receive pause frames : %u\n", stats->rx_pause_frames);
 1960         printf("Receive control frames : %u\n", stats->rx_control_frames);
 1961 
 1962         return (error);
 1963 }

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