Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/bfe/if_bfe.c
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1 /* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * Modifications for FreeBSD-stable by Edwin Groothuis 5 * <edwin at mavetju.org 6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>> 7 */ 8 9 /* 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/sockio.h> 39 #include <sys/mbuf.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/socket.h> 43 #include <sys/queue.h> 44 45 #include <net/if.h> 46 #include <net/if_arp.h> 47 #include <net/ethernet.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 51 #include <net/bpf.h> 52 53 #include <net/if_types.h> 54 #include <net/if_vlan_var.h> 55 56 #include <netinet/in_systm.h> 57 #include <netinet/in.h> 58 #include <netinet/ip.h> 59 60 #include <machine/clock.h> /* for DELAY */ 61 #include <machine/bus_memio.h> 62 #include <machine/bus.h> 63 #include <machine/resource.h> 64 #include <sys/bus.h> 65 #include <sys/rman.h> 66 67 #if __FreeBSD_version < 500000 68 #include <pci/pcireg.h> 69 #include <pci/pcivar.h> 70 #endif 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 #if __FreeBSD_version > 500000 75 #include "miidevs.h" 76 77 #include <dev/pci/pcireg.h> 78 #include <dev/pci/pcivar.h> 79 #endif 80 81 #include <dev/bfe/if_bfereg.h> 82 83 MODULE_DEPEND(bfe, pci, 1, 1, 1); 84 MODULE_DEPEND(bfe, ether, 1, 1, 1); 85 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 86 87 /* "controller miibus0" required. See GENERIC if you get errors here. */ 88 #include "miibus_if.h" 89 90 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 91 92 static struct bfe_type bfe_devs[] = { 93 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 94 "Broadcom BCM4401 Fast Ethernet" }, 95 { 0, 0, NULL } 96 }; 97 98 static int bfe_probe (device_t); 99 static int bfe_attach (device_t); 100 static int bfe_detach (device_t); 101 static void bfe_release_resources (struct bfe_softc *); 102 static void bfe_intr (void *); 103 static void bfe_start (struct ifnet *); 104 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 105 static void bfe_init (void *); 106 static void bfe_stop (struct bfe_softc *); 107 static void bfe_watchdog (struct ifnet *); 108 static void bfe_shutdown (device_t); 109 static void bfe_tick (void *); 110 static void bfe_txeof (struct bfe_softc *); 111 static void bfe_rxeof (struct bfe_softc *); 112 static void bfe_set_rx_mode (struct bfe_softc *); 113 static int bfe_list_rx_init (struct bfe_softc *); 114 static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 115 static void bfe_rx_ring_free (struct bfe_softc *); 116 117 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 118 static int bfe_ifmedia_upd (struct ifnet *); 119 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 120 static int bfe_miibus_readreg (device_t, int, int); 121 static int bfe_miibus_writereg (device_t, int, int, int); 122 static void bfe_miibus_statchg (device_t); 123 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 124 u_long, const int); 125 static void bfe_get_config (struct bfe_softc *sc); 126 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 127 static void bfe_stats_update (struct bfe_softc *); 128 static void bfe_clear_stats (struct bfe_softc *); 129 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 130 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 131 static int bfe_resetphy (struct bfe_softc *); 132 static int bfe_setupphy (struct bfe_softc *); 133 static void bfe_chip_reset (struct bfe_softc *); 134 static void bfe_chip_halt (struct bfe_softc *); 135 static void bfe_core_reset (struct bfe_softc *); 136 static void bfe_core_disable (struct bfe_softc *); 137 static int bfe_dma_alloc (device_t); 138 static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 139 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 140 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 141 142 static device_method_t bfe_methods[] = { 143 /* Device interface */ 144 DEVMETHOD(device_probe, bfe_probe), 145 DEVMETHOD(device_attach, bfe_attach), 146 DEVMETHOD(device_detach, bfe_detach), 147 DEVMETHOD(device_shutdown, bfe_shutdown), 148 149 /* bus interface */ 150 DEVMETHOD(bus_print_child, bus_generic_print_child), 151 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 152 153 /* MII interface */ 154 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 155 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 156 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 157 158 { 0, 0 } 159 }; 160 161 static driver_t bfe_driver = { 162 "bfe", 163 bfe_methods, 164 sizeof(struct bfe_softc) 165 }; 166 167 static devclass_t bfe_devclass; 168 169 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 170 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 171 172 /* 173 * Probe for a Broadcom 4401 chip. 174 */ 175 static int 176 bfe_probe(device_t dev) 177 { 178 struct bfe_type *t; 179 struct bfe_softc *sc; 180 181 t = bfe_devs; 182 183 sc = device_get_softc(dev); 184 bzero(sc, sizeof(struct bfe_softc)); 185 sc->bfe_unit = device_get_unit(dev); 186 sc->bfe_dev = dev; 187 188 while(t->bfe_name != NULL) { 189 if ((pci_get_vendor(dev) == t->bfe_vid) && 190 (pci_get_device(dev) == t->bfe_did)) { 191 device_set_desc_copy(dev, t->bfe_name); 192 return (0); 193 } 194 t++; 195 } 196 197 return (ENXIO); 198 } 199 200 static int 201 bfe_dma_alloc(device_t dev) 202 { 203 struct bfe_softc *sc; 204 int error, i; 205 206 sc = device_get_softc(dev); 207 208 /* parent tag */ 209 error = bus_dma_tag_create(NULL, /* parent */ 210 PAGE_SIZE, 0, /* alignment, boundary */ 211 BUS_SPACE_MAXADDR, /* lowaddr */ 212 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 213 NULL, NULL, /* filter, filterarg */ 214 MAXBSIZE, /* maxsize */ 215 BUS_SPACE_UNRESTRICTED, /* num of segments */ 216 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 217 BUS_DMA_ALLOCNOW, /* flags */ 218 #if __FreeBSD_version > 500000 219 NULL, NULL, /* lockfunc, lockarg */ 220 #endif 221 &sc->bfe_parent_tag); 222 223 /* tag for TX ring */ 224 error = bus_dma_tag_create(sc->bfe_parent_tag, 225 BFE_TX_LIST_SIZE, BFE_TX_LIST_SIZE, 226 BUS_SPACE_MAXADDR, 227 BUS_SPACE_MAXADDR, 228 NULL, NULL, 229 BFE_TX_LIST_SIZE, 230 1, 231 BUS_SPACE_MAXSIZE_32BIT, 232 0, 233 #if __FreeBSD_version > 500000 234 NULL, NULL, 235 #endif 236 &sc->bfe_tx_tag); 237 if (error) { 238 device_printf(dev, "could not allocate dma tag\n"); 239 return (ENOMEM); 240 } 241 242 /* tag for RX ring */ 243 error = bus_dma_tag_create(sc->bfe_parent_tag, 244 BFE_RX_LIST_SIZE, BFE_RX_LIST_SIZE, 245 BUS_SPACE_MAXADDR, 246 BUS_SPACE_MAXADDR, 247 NULL, NULL, 248 BFE_RX_LIST_SIZE, 249 1, 250 BUS_SPACE_MAXSIZE_32BIT, 251 0, 252 #if __FreeBSD_version > 500000 253 NULL, NULL, 254 #endif 255 &sc->bfe_rx_tag); 256 257 if (error) { 258 device_printf(dev, "could not allocate dma tag\n"); 259 return (ENOMEM); 260 } 261 262 /* tag for mbufs */ 263 error = bus_dma_tag_create(sc->bfe_parent_tag, 264 ETHER_ALIGN, 0, 265 BUS_SPACE_MAXADDR, 266 BUS_SPACE_MAXADDR, 267 NULL, NULL, 268 MCLBYTES, 269 1, 270 BUS_SPACE_MAXSIZE_32BIT, 271 0, 272 #if __FreeBSD_version > 500000 273 NULL, NULL, 274 #endif 275 &sc->bfe_tag); 276 277 if (error) { 278 device_printf(dev, "could not allocate dma tag\n"); 279 return (ENOMEM); 280 } 281 282 /* pre allocate dmamaps for RX list */ 283 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 284 error = bus_dmamap_create(sc->bfe_tag, 0, 285 &sc->bfe_rx_ring[i].bfe_map); 286 if (error) { 287 device_printf(dev, "cannot create DMA map for RX\n"); 288 return (ENOMEM); 289 } 290 } 291 292 /* pre allocate dmamaps for TX list */ 293 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 294 error = bus_dmamap_create(sc->bfe_tag, 0, 295 &sc->bfe_tx_ring[i].bfe_map); 296 if (error) { 297 device_printf(dev, "cannot create DMA map for TX\n"); 298 return (ENOMEM); 299 } 300 } 301 302 /* Alloc dma for rx ring */ 303 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 304 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 305 306 if(error) 307 return (ENOMEM); 308 309 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 310 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 311 sc->bfe_rx_list, sizeof(struct bfe_desc), 312 bfe_dma_map, &sc->bfe_rx_dma, 0); 313 314 if(error) 315 return (ENOMEM); 316 317 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 318 319 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 320 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 321 if (error) 322 return (ENOMEM); 323 324 325 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 326 sc->bfe_tx_list, sizeof(struct bfe_desc), 327 bfe_dma_map, &sc->bfe_tx_dma, 0); 328 if(error) 329 return (ENOMEM); 330 331 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 332 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 333 334 return (0); 335 } 336 337 static int 338 bfe_attach(device_t dev) 339 { 340 struct ifnet *ifp; 341 struct bfe_softc *sc; 342 int unit, error = 0, rid; 343 344 sc = device_get_softc(dev); 345 346 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 347 MTX_DEF | MTX_RECURSE); 348 349 unit = device_get_unit(dev); 350 sc->bfe_dev = dev; 351 sc->bfe_unit = unit; 352 353 /* 354 * Handle power management nonsense. 355 */ 356 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 357 u_int32_t membase, irq; 358 359 /* Save important PCI config data. */ 360 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 361 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 362 363 /* Reset the power state. */ 364 printf("bfe%d: chip is is in D%d power mode -- setting to D0\n", 365 sc->bfe_unit, pci_get_powerstate(dev)); 366 367 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 368 369 /* Restore PCI config data. */ 370 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 371 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 372 } 373 374 /* 375 * Map control/status registers. 376 */ 377 pci_enable_busmaster(dev); 378 379 rid = BFE_PCI_MEMLO; 380 sc->bfe_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1, 381 RF_ACTIVE); 382 if (sc->bfe_res == NULL) { 383 printf ("bfe%d: couldn't map memory\n", unit); 384 error = ENXIO; 385 goto fail; 386 } 387 388 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 389 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 390 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 391 392 /* Allocate interrupt */ 393 rid = 0; 394 395 sc->bfe_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 396 RF_SHAREABLE | RF_ACTIVE); 397 if (sc->bfe_irq == NULL) { 398 printf("bfe%d: couldn't map interrupt\n", unit); 399 error = ENXIO; 400 goto fail; 401 } 402 403 if (bfe_dma_alloc(dev)) { 404 printf("bfe%d: failed to allocate DMA resources\n", 405 sc->bfe_unit); 406 bfe_release_resources(sc); 407 error = ENXIO; 408 goto fail; 409 } 410 411 /* Set up ifnet structure */ 412 ifp = &sc->arpcom.ac_if; 413 ifp->if_softc = sc; 414 ifp->if_unit = sc->bfe_unit; 415 ifp->if_name = "bfe"; 416 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 417 ifp->if_ioctl = bfe_ioctl; 418 ifp->if_output = ether_output; 419 ifp->if_start = bfe_start; 420 ifp->if_watchdog = bfe_watchdog; 421 ifp->if_init = bfe_init; 422 ifp->if_mtu = ETHERMTU; 423 ifp->if_baudrate = 100000000; 424 ifp->if_snd.ifq_maxlen = BFE_TX_QLEN; 425 426 bfe_get_config(sc); 427 428 printf("bfe%d: Ethernet address: %6D\n", unit, 429 sc->arpcom.ac_enaddr, ":"); 430 431 /* Reset the chip and turn on the PHY */ 432 bfe_chip_reset(sc); 433 434 if (mii_phy_probe(dev, &sc->bfe_miibus, 435 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 436 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 437 error = ENXIO; 438 goto fail; 439 } 440 441 #if __FreeBSD_version > 500000 442 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 443 #else 444 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 445 #endif 446 callout_handle_init(&sc->bfe_stat_ch); 447 448 /* 449 * Tell the upper layer(s) we support long frames. 450 */ 451 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 452 #if __FreeBSD_version >= 500000 453 ifp->if_capabilities |= IFCAP_VLAN_MTU; 454 ifp->if_capenable |= IFCAP_VLAN_MTU; 455 #endif 456 457 /* 458 * Hook interrupt last to avoid having to lock softc 459 */ 460 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET, 461 bfe_intr, sc, &sc->bfe_intrhand); 462 463 if (error) { 464 bfe_release_resources(sc); 465 printf("bfe%d: couldn't set up irq\n", unit); 466 goto fail; 467 } 468 fail: 469 if(error) 470 bfe_release_resources(sc); 471 return (error); 472 } 473 474 static int 475 bfe_detach(device_t dev) 476 { 477 struct bfe_softc *sc; 478 struct ifnet *ifp; 479 BFE_VAR(s); 480 481 sc = device_get_softc(dev); 482 483 #if __FreeBSD_version > 500000 484 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 485 #endif 486 BFE_LOCK(scp); 487 488 ifp = &sc->arpcom.ac_if; 489 490 if (device_is_attached(dev)) { 491 bfe_stop(sc); 492 #if __FreeBSD_version > 500000 493 ether_ifdetach(ifp); 494 #else 495 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 496 #endif 497 } 498 499 bfe_chip_reset(sc); 500 501 bus_generic_detach(dev); 502 if(sc->bfe_miibus != NULL) 503 device_delete_child(dev, sc->bfe_miibus); 504 505 bfe_release_resources(sc); 506 BFE_UNLOCK(sc); 507 mtx_destroy(&sc->bfe_mtx); 508 509 return (0); 510 } 511 512 /* 513 * Stop all chip I/O so that the kernel's probe routines don't 514 * get confused by errant DMAs when rebooting. 515 */ 516 static void 517 bfe_shutdown(device_t dev) 518 { 519 struct bfe_softc *sc; 520 BFE_VAR(s); 521 522 sc = device_get_softc(dev); 523 BFE_LOCK(sc); 524 bfe_stop(sc); 525 526 BFE_UNLOCK(sc); 527 return; 528 } 529 530 static int 531 bfe_miibus_readreg(device_t dev, int phy, int reg) 532 { 533 struct bfe_softc *sc; 534 u_int32_t ret; 535 536 sc = device_get_softc(dev); 537 if(phy != sc->bfe_phyaddr) 538 return (0); 539 bfe_readphy(sc, reg, &ret); 540 541 return (ret); 542 } 543 544 static int 545 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 546 { 547 struct bfe_softc *sc; 548 549 sc = device_get_softc(dev); 550 if(phy != sc->bfe_phyaddr) 551 return (0); 552 bfe_writephy(sc, reg, val); 553 554 return (0); 555 } 556 557 static void 558 bfe_miibus_statchg(device_t dev) 559 { 560 return; 561 } 562 563 static void 564 bfe_tx_ring_free(struct bfe_softc *sc) 565 { 566 int i; 567 568 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 569 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 570 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 571 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 572 bus_dmamap_unload(sc->bfe_tag, 573 sc->bfe_tx_ring[i].bfe_map); 574 bus_dmamap_destroy(sc->bfe_tag, 575 sc->bfe_tx_ring[i].bfe_map); 576 } 577 } 578 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 579 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 580 } 581 582 static void 583 bfe_rx_ring_free(struct bfe_softc *sc) 584 { 585 int i; 586 587 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 588 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 589 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 590 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 591 bus_dmamap_unload(sc->bfe_tag, 592 sc->bfe_rx_ring[i].bfe_map); 593 bus_dmamap_destroy(sc->bfe_tag, 594 sc->bfe_rx_ring[i].bfe_map); 595 } 596 } 597 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 598 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 599 } 600 601 602 static int 603 bfe_list_rx_init(struct bfe_softc *sc) 604 { 605 int i; 606 607 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 608 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 609 return (ENOBUFS); 610 } 611 612 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 613 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 614 615 sc->bfe_rx_cons = 0; 616 617 return (0); 618 } 619 620 static int 621 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 622 { 623 struct bfe_rxheader *rx_header; 624 struct bfe_desc *d; 625 struct bfe_data *r; 626 u_int32_t ctrl; 627 628 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 629 return (EINVAL); 630 631 if(m == NULL) { 632 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 633 if(m == NULL) 634 return (ENOBUFS); 635 m->m_len = m->m_pkthdr.len = MCLBYTES; 636 } 637 else 638 m->m_data = m->m_ext.ext_buf; 639 640 rx_header = mtod(m, struct bfe_rxheader *); 641 rx_header->len = 0; 642 rx_header->flags = 0; 643 644 /* Map the mbuf into DMA */ 645 sc->bfe_rx_cnt = c; 646 d = &sc->bfe_rx_list[c]; 647 r = &sc->bfe_rx_ring[c]; 648 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 649 MCLBYTES, bfe_dma_map_desc, d, 0); 650 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 651 652 ctrl = ETHER_MAX_LEN + 32; 653 654 if(c == BFE_RX_LIST_CNT - 1) 655 ctrl |= BFE_DESC_EOT; 656 657 d->bfe_ctrl = ctrl; 658 r->bfe_mbuf = m; 659 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 660 return (0); 661 } 662 663 static void 664 bfe_get_config(struct bfe_softc *sc) 665 { 666 u_int8_t eeprom[128]; 667 668 bfe_read_eeprom(sc, eeprom); 669 670 sc->arpcom.ac_enaddr[0] = eeprom[79]; 671 sc->arpcom.ac_enaddr[1] = eeprom[78]; 672 sc->arpcom.ac_enaddr[2] = eeprom[81]; 673 sc->arpcom.ac_enaddr[3] = eeprom[80]; 674 sc->arpcom.ac_enaddr[4] = eeprom[83]; 675 sc->arpcom.ac_enaddr[5] = eeprom[82]; 676 677 sc->bfe_phyaddr = eeprom[90] & 0x1f; 678 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 679 680 sc->bfe_core_unit = 0; 681 sc->bfe_dma_offset = BFE_PCI_DMA; 682 } 683 684 static void 685 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 686 { 687 u_int32_t bar_orig, pci_rev, val; 688 689 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 690 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 691 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 692 693 val = CSR_READ_4(sc, BFE_SBINTVEC); 694 val |= cores; 695 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 696 697 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 698 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 699 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 700 701 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 702 } 703 704 static void 705 bfe_clear_stats(struct bfe_softc *sc) 706 { 707 u_long reg; 708 BFE_VAR(s); 709 710 BFE_LOCK(sc); 711 712 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 713 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 714 CSR_READ_4(sc, reg); 715 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 716 CSR_READ_4(sc, reg); 717 718 BFE_UNLOCK(sc); 719 } 720 721 static int 722 bfe_resetphy(struct bfe_softc *sc) 723 { 724 u_int32_t val; 725 BFE_VAR(s); 726 727 BFE_LOCK(sc); 728 bfe_writephy(sc, 0, BMCR_RESET); 729 DELAY(100); 730 bfe_readphy(sc, 0, &val); 731 if (val & BMCR_RESET) { 732 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 733 BFE_UNLOCK(sc); 734 return (ENXIO); 735 } 736 BFE_UNLOCK(sc); 737 return (0); 738 } 739 740 static void 741 bfe_chip_halt(struct bfe_softc *sc) 742 { 743 BFE_VAR(s); 744 745 BFE_LOCK(sc); 746 /* disable interrupts - not that it actually does..*/ 747 CSR_WRITE_4(sc, BFE_IMASK, 0); 748 CSR_READ_4(sc, BFE_IMASK); 749 750 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 751 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 752 753 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 754 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 755 DELAY(10); 756 757 BFE_UNLOCK(sc); 758 } 759 760 static void 761 bfe_chip_reset(struct bfe_softc *sc) 762 { 763 u_int32_t val; 764 BFE_VAR(s); 765 766 BFE_LOCK(sc); 767 768 /* Set the interrupt vector for the enet core */ 769 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 770 771 /* is core up? */ 772 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 773 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 774 if (val == BFE_CLOCK) { 775 /* It is, so shut it down */ 776 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 777 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 778 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 779 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 780 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 781 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 782 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 783 100, 0); 784 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 785 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 786 } 787 788 bfe_core_reset(sc); 789 bfe_clear_stats(sc); 790 791 /* 792 * We want the phy registers to be accessible even when 793 * the driver is "downed" so initialize MDC preamble, frequency, 794 * and whether internal or external phy here. 795 */ 796 797 /* 4402 has 62.5Mhz SB clock and internal phy */ 798 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 799 800 /* Internal or external PHY? */ 801 val = CSR_READ_4(sc, BFE_DEVCTRL); 802 if(!(val & BFE_IPP)) 803 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 804 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 805 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 806 DELAY(100); 807 } 808 809 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB); 810 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 811 BFE_LAZY_FC_MASK)); 812 813 /* 814 * We don't want lazy interrupts, so just send them at 815 * the end of a frame, please 816 */ 817 BFE_OR(sc, BFE_RCV_LAZY, 0); 818 819 /* Set max lengths, accounting for VLAN tags */ 820 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 821 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 822 823 /* Set watermark XXX - magic */ 824 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 825 826 /* 827 * Initialise DMA channels 828 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 829 */ 830 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 831 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 832 833 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 834 BFE_RX_CTRL_ENABLE); 835 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 836 837 bfe_resetphy(sc); 838 bfe_setupphy(sc); 839 840 BFE_UNLOCK(sc); 841 } 842 843 static void 844 bfe_core_disable(struct bfe_softc *sc) 845 { 846 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 847 return; 848 849 /* 850 * Set reject, wait for it set, then wait for the core to stop 851 * being busy, then set reset and reject and enable the clocks. 852 */ 853 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 854 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 855 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 856 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 857 BFE_RESET)); 858 CSR_READ_4(sc, BFE_SBTMSLOW); 859 DELAY(10); 860 /* Leave reset and reject set */ 861 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 862 DELAY(10); 863 } 864 865 static void 866 bfe_core_reset(struct bfe_softc *sc) 867 { 868 u_int32_t val; 869 870 /* Disable the core */ 871 bfe_core_disable(sc); 872 873 /* and bring it back up */ 874 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 875 CSR_READ_4(sc, BFE_SBTMSLOW); 876 DELAY(10); 877 878 /* Chip bug, clear SERR, IB and TO if they are set. */ 879 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 880 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 881 val = CSR_READ_4(sc, BFE_SBIMSTATE); 882 if (val & (BFE_IBE | BFE_TO)) 883 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 884 885 /* Clear reset and allow it to move through the core */ 886 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 887 CSR_READ_4(sc, BFE_SBTMSLOW); 888 DELAY(10); 889 890 /* Leave the clock set */ 891 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 892 CSR_READ_4(sc, BFE_SBTMSLOW); 893 DELAY(10); 894 } 895 896 static void 897 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 898 { 899 u_int32_t val; 900 901 val = ((u_int32_t) data[2]) << 24; 902 val |= ((u_int32_t) data[3]) << 16; 903 val |= ((u_int32_t) data[4]) << 8; 904 val |= ((u_int32_t) data[5]); 905 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 906 val = (BFE_CAM_HI_VALID | 907 (((u_int32_t) data[0]) << 8) | 908 (((u_int32_t) data[1]))); 909 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 910 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 911 (index << BFE_CAM_INDEX_SHIFT))); 912 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 913 } 914 915 static void 916 bfe_set_rx_mode(struct bfe_softc *sc) 917 { 918 struct ifnet *ifp = &sc->arpcom.ac_if; 919 struct ifmultiaddr *ifma; 920 u_int32_t val; 921 int i = 0; 922 923 val = CSR_READ_4(sc, BFE_RXCONF); 924 925 if (ifp->if_flags & IFF_PROMISC) 926 val |= BFE_RXCONF_PROMISC; 927 else 928 val &= ~BFE_RXCONF_PROMISC; 929 930 if (ifp->if_flags & IFF_BROADCAST) 931 val &= ~BFE_RXCONF_DBCAST; 932 else 933 val |= BFE_RXCONF_DBCAST; 934 935 936 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 937 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 938 939 if (ifp->if_flags & IFF_ALLMULTI) 940 val |= BFE_RXCONF_ALLMULTI; 941 else { 942 val &= ~BFE_RXCONF_ALLMULTI; 943 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 944 ifma = ifma->ifma_link.le_next) { 945 if (ifma->ifma_addr->sa_family != AF_LINK) 946 continue; 947 bfe_cam_write(sc, 948 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 949 } 950 } 951 952 CSR_WRITE_4(sc, BFE_RXCONF, val); 953 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 954 } 955 956 static void 957 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 958 { 959 u_int32_t *ptr; 960 961 ptr = arg; 962 *ptr = segs->ds_addr; 963 } 964 965 static void 966 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 967 { 968 struct bfe_desc *d; 969 970 d = arg; 971 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 972 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 973 } 974 975 static void 976 bfe_release_resources(struct bfe_softc *sc) 977 { 978 device_t dev; 979 int i; 980 981 dev = sc->bfe_dev; 982 983 if (sc->bfe_vpd_prodname != NULL) 984 free(sc->bfe_vpd_prodname, M_DEVBUF); 985 986 if (sc->bfe_vpd_readonly != NULL) 987 free(sc->bfe_vpd_readonly, M_DEVBUF); 988 989 if (sc->bfe_intrhand != NULL) 990 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 991 992 if (sc->bfe_irq != NULL) 993 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 994 995 if (sc->bfe_res != NULL) 996 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 997 998 if(sc->bfe_tx_tag != NULL) { 999 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 1000 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 1001 sc->bfe_tx_map); 1002 bus_dma_tag_destroy(sc->bfe_tx_tag); 1003 sc->bfe_tx_tag = NULL; 1004 } 1005 1006 if(sc->bfe_rx_tag != NULL) { 1007 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 1008 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 1009 sc->bfe_rx_map); 1010 bus_dma_tag_destroy(sc->bfe_rx_tag); 1011 sc->bfe_rx_tag = NULL; 1012 } 1013 1014 if(sc->bfe_tag != NULL) { 1015 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 1016 bus_dmamap_destroy(sc->bfe_tag, 1017 sc->bfe_tx_ring[i].bfe_map); 1018 } 1019 bus_dma_tag_destroy(sc->bfe_tag); 1020 sc->bfe_tag = NULL; 1021 } 1022 1023 if(sc->bfe_parent_tag != NULL) 1024 bus_dma_tag_destroy(sc->bfe_parent_tag); 1025 1026 return; 1027 } 1028 1029 static void 1030 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 1031 { 1032 long i; 1033 u_int16_t *ptr = (u_int16_t *)data; 1034 1035 for(i = 0; i < 128; i += 2) 1036 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 1037 } 1038 1039 static int 1040 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1041 u_long timeout, const int clear) 1042 { 1043 u_long i; 1044 1045 for (i = 0; i < timeout; i++) { 1046 u_int32_t val = CSR_READ_4(sc, reg); 1047 1048 if (clear && !(val & bit)) 1049 break; 1050 if (!clear && (val & bit)) 1051 break; 1052 DELAY(10); 1053 } 1054 if (i == timeout) { 1055 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1056 "%x to %s.\n", sc->bfe_unit, bit, reg, 1057 (clear ? "clear" : "set")); 1058 return (-1); 1059 } 1060 return (0); 1061 } 1062 1063 static int 1064 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1065 { 1066 int err; 1067 BFE_VAR(s); 1068 1069 BFE_LOCK(sc); 1070 /* Clear MII ISR */ 1071 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1072 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1073 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1074 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1075 (reg << BFE_MDIO_RA_SHIFT) | 1076 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1077 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1078 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1079 1080 BFE_UNLOCK(sc); 1081 return (err); 1082 } 1083 1084 static int 1085 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1086 { 1087 int status; 1088 BFE_VAR(s); 1089 1090 BFE_LOCK(sc); 1091 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1092 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1093 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1094 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1095 (reg << BFE_MDIO_RA_SHIFT) | 1096 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1097 (val & BFE_MDIO_DATA_DATA))); 1098 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1099 BFE_UNLOCK(sc); 1100 1101 return (status); 1102 } 1103 1104 /* 1105 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1106 * twice 1107 */ 1108 static int 1109 bfe_setupphy(struct bfe_softc *sc) 1110 { 1111 u_int32_t val; 1112 BFE_VAR(s); 1113 BFE_LOCK(sc); 1114 1115 /* Enable activity LED */ 1116 bfe_readphy(sc, 26, &val); 1117 bfe_writephy(sc, 26, val & 0x7fff); 1118 bfe_readphy(sc, 26, &val); 1119 1120 /* Enable traffic meter LED mode */ 1121 bfe_readphy(sc, 27, &val); 1122 bfe_writephy(sc, 27, val | (1 << 6)); 1123 1124 BFE_UNLOCK(sc); 1125 return (0); 1126 } 1127 1128 static void 1129 bfe_stats_update(struct bfe_softc *sc) 1130 { 1131 u_long reg; 1132 u_int32_t *val; 1133 1134 val = &sc->bfe_hwstats.tx_good_octets; 1135 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1136 *val++ += CSR_READ_4(sc, reg); 1137 } 1138 val = &sc->bfe_hwstats.rx_good_octets; 1139 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1140 *val++ += CSR_READ_4(sc, reg); 1141 } 1142 } 1143 1144 static void 1145 bfe_txeof(struct bfe_softc *sc) 1146 { 1147 struct ifnet *ifp; 1148 int i, chipidx; 1149 BFE_VAR(s); 1150 1151 BFE_LOCK(sc); 1152 1153 ifp = &sc->arpcom.ac_if; 1154 1155 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1156 chipidx /= sizeof(struct bfe_desc); 1157 1158 i = sc->bfe_tx_cons; 1159 /* Go through the mbufs and free those that have been transmitted */ 1160 while(i != chipidx) { 1161 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1162 if(r->bfe_mbuf != NULL) { 1163 ifp->if_opackets++; 1164 m_freem(r->bfe_mbuf); 1165 r->bfe_mbuf = NULL; 1166 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1167 } 1168 sc->bfe_tx_cnt--; 1169 BFE_INC(i, BFE_TX_LIST_CNT); 1170 } 1171 1172 if(i != sc->bfe_tx_cons) { 1173 /* we freed up some mbufs */ 1174 sc->bfe_tx_cons = i; 1175 ifp->if_flags &= ~IFF_OACTIVE; 1176 } 1177 if(sc->bfe_tx_cnt == 0) 1178 ifp->if_timer = 0; 1179 else 1180 ifp->if_timer = 5; 1181 1182 BFE_UNLOCK(sc); 1183 } 1184 1185 /* Pass a received packet up the stack */ 1186 static void 1187 bfe_rxeof(struct bfe_softc *sc) 1188 { 1189 struct mbuf *m; 1190 struct ifnet *ifp; 1191 struct bfe_rxheader *rxheader; 1192 struct bfe_data *r; 1193 int cons; 1194 u_int32_t status, current, len, flags; 1195 BFE_VAR(s); 1196 1197 BFE_LOCK(sc); 1198 cons = sc->bfe_rx_cons; 1199 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1200 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1201 1202 ifp = &sc->arpcom.ac_if; 1203 1204 while(current != cons) { 1205 r = &sc->bfe_rx_ring[cons]; 1206 m = r->bfe_mbuf; 1207 rxheader = mtod(m, struct bfe_rxheader*); 1208 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1209 len = rxheader->len; 1210 r->bfe_mbuf = NULL; 1211 1212 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1213 flags = rxheader->flags; 1214 1215 len -= ETHER_CRC_LEN; 1216 1217 /* flag an error and try again */ 1218 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1219 ifp->if_ierrors++; 1220 if (flags & BFE_RX_FLAG_SERR) 1221 ifp->if_collisions++; 1222 bfe_list_newbuf(sc, cons, m); 1223 BFE_INC(cons, BFE_RX_LIST_CNT); 1224 continue; 1225 } 1226 1227 /* Go past the rx header */ 1228 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1229 m_adj(m, BFE_RX_OFFSET); 1230 m->m_len = m->m_pkthdr.len = len; 1231 } else { 1232 bfe_list_newbuf(sc, cons, m); 1233 ifp->if_ierrors++; 1234 BFE_INC(cons, BFE_RX_LIST_CNT); 1235 continue; 1236 } 1237 1238 ifp->if_ipackets++; 1239 m->m_pkthdr.rcvif = ifp; 1240 1241 #if __FreeBSD_version > 500000 1242 (*ifp->if_input)(ifp, m); 1243 #else 1244 ether_input(ifp, NULL, m); 1245 #endif 1246 BFE_INC(cons, BFE_RX_LIST_CNT); 1247 } 1248 sc->bfe_rx_cons = cons; 1249 BFE_UNLOCK(sc); 1250 } 1251 1252 static void 1253 bfe_intr(void *xsc) 1254 { 1255 struct bfe_softc *sc = xsc; 1256 struct ifnet *ifp; 1257 u_int32_t istat, imask, flag; 1258 BFE_VAR(s); 1259 1260 ifp = &sc->arpcom.ac_if; 1261 1262 BFE_LOCK(sc); 1263 1264 istat = CSR_READ_4(sc, BFE_ISTAT); 1265 imask = CSR_READ_4(sc, BFE_IMASK); 1266 1267 /* 1268 * Defer unsolicited interrupts - This is necessary because setting the 1269 * chips interrupt mask register to 0 doesn't actually stop the 1270 * interrupts 1271 */ 1272 istat &= imask; 1273 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1274 CSR_READ_4(sc, BFE_ISTAT); 1275 1276 /* not expecting this interrupt, disregard it */ 1277 if(istat == 0) { 1278 BFE_UNLOCK(sc); 1279 return; 1280 } 1281 1282 if(istat & BFE_ISTAT_ERRORS) { 1283 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1284 if(flag & BFE_STAT_EMASK) 1285 ifp->if_oerrors++; 1286 1287 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1288 if(flag & BFE_RX_FLAG_ERRORS) 1289 ifp->if_ierrors++; 1290 1291 ifp->if_flags &= ~IFF_RUNNING; 1292 bfe_init(sc); 1293 } 1294 1295 /* A packet was received */ 1296 if(istat & BFE_ISTAT_RX) 1297 bfe_rxeof(sc); 1298 1299 /* A packet was sent */ 1300 if(istat & BFE_ISTAT_TX) 1301 bfe_txeof(sc); 1302 1303 /* We have packets pending, fire them out */ 1304 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1305 bfe_start(ifp); 1306 1307 BFE_UNLOCK(sc); 1308 } 1309 1310 static int 1311 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1312 { 1313 struct bfe_desc *d = NULL; 1314 struct bfe_data *r = NULL; 1315 struct mbuf *m; 1316 u_int32_t frag, cur, cnt = 0; 1317 #if __FreeBSD_version > 500000 1318 int chainlen = 0; 1319 #endif 1320 1321 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1322 return (ENOBUFS); 1323 1324 #if __FreeBSD_version > 500000 1325 /* 1326 * Count the number of frags in this chain to see if 1327 * we need to m_defrag. Since the descriptor list is shared 1328 * by all packets, we'll m_defrag long chains so that they 1329 * do not use up the entire list, even if they would fit. 1330 */ 1331 for(m = m_head; m != NULL; m = m->m_next) 1332 chainlen++; 1333 1334 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1335 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1336 m = m_defrag(m_head, M_DONTWAIT); 1337 if (m == NULL) 1338 return (ENOBUFS); 1339 m_head = m; 1340 } 1341 #endif 1342 1343 /* 1344 * Start packing the mbufs in this chain into 1345 * the fragment pointers. Stop when we run out 1346 * of fragments or hit the end of the mbuf chain. 1347 */ 1348 m = m_head; 1349 cur = frag = *txidx; 1350 cnt = 0; 1351 1352 for(m = m_head; m != NULL; m = m->m_next) { 1353 if(m->m_len != 0) { 1354 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1355 return (ENOBUFS); 1356 1357 d = &sc->bfe_tx_list[cur]; 1358 r = &sc->bfe_tx_ring[cur]; 1359 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1360 /* always intterupt on completion */ 1361 d->bfe_ctrl |= BFE_DESC_IOC; 1362 if(cnt == 0) 1363 /* Set start of frame */ 1364 d->bfe_ctrl |= BFE_DESC_SOF; 1365 if(cur == BFE_TX_LIST_CNT - 1) 1366 /* 1367 * Tell the chip to wrap to the start of 1368 * the descriptor list 1369 */ 1370 d->bfe_ctrl |= BFE_DESC_EOT; 1371 1372 bus_dmamap_load(sc->bfe_tag, 1373 r->bfe_map, mtod(m, void*), m->m_len, 1374 bfe_dma_map_desc, d, 0); 1375 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1376 BUS_DMASYNC_PREREAD); 1377 1378 frag = cur; 1379 BFE_INC(cur, BFE_TX_LIST_CNT); 1380 cnt++; 1381 } 1382 } 1383 1384 if (m != NULL) 1385 return (ENOBUFS); 1386 1387 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1388 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1389 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1390 1391 *txidx = cur; 1392 sc->bfe_tx_cnt += cnt; 1393 return (0); 1394 } 1395 1396 /* 1397 * Set up to transmit a packet 1398 */ 1399 static void 1400 bfe_start(struct ifnet *ifp) 1401 { 1402 struct bfe_softc *sc; 1403 struct mbuf *m_head = NULL; 1404 int idx; 1405 BFE_VAR(s); 1406 1407 sc = ifp->if_softc; 1408 idx = sc->bfe_tx_prod; 1409 1410 BFE_LOCK(sc); 1411 1412 /* 1413 * Not much point trying to send if the link is down 1414 * or we have nothing to send. 1415 */ 1416 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) { 1417 BFE_UNLOCK(sc); 1418 return; 1419 } 1420 1421 if (ifp->if_flags & IFF_OACTIVE) { 1422 BFE_UNLOCK(sc); 1423 return; 1424 } 1425 1426 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1427 IF_DEQUEUE(&ifp->if_snd, m_head); 1428 if(m_head == NULL) 1429 break; 1430 1431 /* 1432 * Pack the data into the tx ring. If we dont have 1433 * enough room, let the chip drain the ring. 1434 */ 1435 if(bfe_encap(sc, m_head, &idx)) { 1436 IF_PREPEND(&ifp->if_snd, m_head); 1437 ifp->if_flags |= IFF_OACTIVE; 1438 break; 1439 } 1440 1441 /* 1442 * If there's a BPF listener, bounce a copy of this frame 1443 * to him. 1444 */ 1445 BPF_MTAP(ifp, m_head); 1446 } 1447 1448 sc->bfe_tx_prod = idx; 1449 /* Transmit - twice due to apparent hardware bug */ 1450 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1451 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1452 1453 /* 1454 * Set a timeout in case the chip goes out to lunch. 1455 */ 1456 ifp->if_timer = 5; 1457 BFE_UNLOCK(sc); 1458 } 1459 1460 static void 1461 bfe_init(void *xsc) 1462 { 1463 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1464 struct ifnet *ifp = &sc->arpcom.ac_if; 1465 BFE_VAR(s); 1466 1467 BFE_LOCK(sc); 1468 1469 if (ifp->if_flags & IFF_RUNNING) { 1470 BFE_UNLOCK(sc); 1471 return; 1472 } 1473 1474 bfe_stop(sc); 1475 bfe_chip_reset(sc); 1476 1477 if (bfe_list_rx_init(sc) == ENOBUFS) { 1478 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1479 sc->bfe_unit); 1480 bfe_stop(sc); 1481 return; 1482 } 1483 1484 bfe_set_rx_mode(sc); 1485 1486 /* Enable the chip and core */ 1487 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1488 /* Enable interrupts */ 1489 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1490 1491 bfe_ifmedia_upd(ifp); 1492 ifp->if_flags |= IFF_RUNNING; 1493 ifp->if_flags &= ~IFF_OACTIVE; 1494 1495 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1496 BFE_UNLOCK(sc); 1497 } 1498 1499 /* 1500 * Set media options. 1501 */ 1502 static int 1503 bfe_ifmedia_upd(struct ifnet *ifp) 1504 { 1505 struct bfe_softc *sc; 1506 struct mii_data *mii; 1507 BFE_VAR(s); 1508 1509 sc = ifp->if_softc; 1510 1511 BFE_LOCK(sc); 1512 1513 mii = device_get_softc(sc->bfe_miibus); 1514 sc->bfe_link = 0; 1515 if (mii->mii_instance) { 1516 struct mii_softc *miisc; 1517 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1518 miisc = LIST_NEXT(miisc, mii_list)) 1519 mii_phy_reset(miisc); 1520 } 1521 mii_mediachg(mii); 1522 1523 BFE_UNLOCK(sc); 1524 return (0); 1525 } 1526 1527 /* 1528 * Report current media status. 1529 */ 1530 static void 1531 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1532 { 1533 struct bfe_softc *sc = ifp->if_softc; 1534 struct mii_data *mii; 1535 BFE_VAR(s); 1536 1537 BFE_LOCK(sc); 1538 1539 mii = device_get_softc(sc->bfe_miibus); 1540 mii_pollstat(mii); 1541 ifmr->ifm_active = mii->mii_media_active; 1542 ifmr->ifm_status = mii->mii_media_status; 1543 1544 BFE_UNLOCK(sc); 1545 } 1546 1547 static int 1548 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1549 { 1550 struct bfe_softc *sc = ifp->if_softc; 1551 struct ifreq *ifr = (struct ifreq *) data; 1552 struct mii_data *mii; 1553 int error = 0; 1554 BFE_VAR(s); 1555 1556 BFE_LOCK(sc); 1557 1558 switch(command) { 1559 case SIOCSIFFLAGS: 1560 if(ifp->if_flags & IFF_UP) 1561 if(ifp->if_flags & IFF_RUNNING) 1562 bfe_set_rx_mode(sc); 1563 else 1564 bfe_init(sc); 1565 else if(ifp->if_flags & IFF_RUNNING) 1566 bfe_stop(sc); 1567 break; 1568 case SIOCADDMULTI: 1569 case SIOCDELMULTI: 1570 if(ifp->if_flags & IFF_RUNNING) 1571 bfe_set_rx_mode(sc); 1572 break; 1573 case SIOCGIFMEDIA: 1574 case SIOCSIFMEDIA: 1575 mii = device_get_softc(sc->bfe_miibus); 1576 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1577 command); 1578 break; 1579 #if __FreeBSD_version > 500000 1580 default: 1581 error = ether_ioctl(ifp, command, data); 1582 break; 1583 #else 1584 case SIOCSIFADDR: 1585 case SIOCGIFADDR: 1586 case SIOCSIFMTU: 1587 error = ether_ioctl(ifp, command, data); 1588 break; 1589 1590 default: 1591 error = EINVAL; 1592 break; 1593 #endif 1594 } 1595 1596 BFE_UNLOCK(sc); 1597 return (error); 1598 } 1599 1600 static void 1601 bfe_watchdog(struct ifnet *ifp) 1602 { 1603 struct bfe_softc *sc; 1604 BFE_VAR(s); 1605 1606 sc = ifp->if_softc; 1607 1608 BFE_LOCK(sc); 1609 1610 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1611 1612 ifp->if_flags &= ~IFF_RUNNING; 1613 bfe_init(sc); 1614 1615 ifp->if_oerrors++; 1616 1617 BFE_UNLOCK(sc); 1618 } 1619 1620 static void 1621 bfe_tick(void *xsc) 1622 { 1623 struct bfe_softc *sc = xsc; 1624 struct mii_data *mii; 1625 BFE_VAR(s); 1626 1627 if (sc == NULL) 1628 return; 1629 1630 BFE_LOCK(sc); 1631 1632 mii = device_get_softc(sc->bfe_miibus); 1633 1634 bfe_stats_update(sc); 1635 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1636 1637 if(sc->bfe_link) { 1638 BFE_UNLOCK(sc); 1639 return; 1640 } 1641 1642 mii_tick(mii); 1643 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1644 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1645 sc->bfe_link++; 1646 #ifdef FALSE 1647 if (!sc->bfe_link) 1648 sc->bfe_link++; 1649 #endif 1650 1651 BFE_UNLOCK(sc); 1652 } 1653 1654 /* 1655 * Stop the adapter and free any mbufs allocated to the 1656 * RX and TX lists. 1657 */ 1658 static void 1659 bfe_stop(struct bfe_softc *sc) 1660 { 1661 struct ifnet *ifp; 1662 BFE_VAR(s); 1663 1664 BFE_LOCK(sc); 1665 1666 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1667 1668 ifp = &sc->arpcom.ac_if; 1669 1670 bfe_chip_halt(sc); 1671 bfe_tx_ring_free(sc); 1672 bfe_rx_ring_free(sc); 1673 1674 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1675 1676 BFE_UNLOCK(sc); 1677 }
Cache object: 69a5bdb541261b58d9043c288dc59802
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