FreeBSD/Linux Kernel Cross Reference
sys/dev/bfe/if_bfe.c
1 /*
2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
3 * and Duncan Barclay<dmlb@dmlb.org>
4 */
5
6 /*
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD: releng/5.2/sys/dev/bfe/if_bfe.c 122689 2003-11-14 19:00:32Z sam $");
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/sockio.h>
36 #include <sys/mbuf.h>
37 #include <sys/malloc.h>
38 #include <sys/kernel.h>
39 #include <sys/socket.h>
40 #include <sys/queue.h>
41
42 #include <net/if.h>
43 #include <net/if_arp.h>
44 #include <net/ethernet.h>
45 #include <net/if_dl.h>
46 #include <net/if_media.h>
47
48 #include <net/bpf.h>
49
50 #include <net/if_types.h>
51 #include <net/if_vlan_var.h>
52
53 #include <netinet/in_systm.h>
54 #include <netinet/in.h>
55 #include <netinet/ip.h>
56
57 #include <machine/clock.h> /* for DELAY */
58 #include <machine/bus_memio.h>
59 #include <machine/bus.h>
60 #include <machine/resource.h>
61 #include <sys/bus.h>
62 #include <sys/rman.h>
63
64 #include <dev/mii/mii.h>
65 #include <dev/mii/miivar.h>
66 #include "miidevs.h"
67
68 #include <dev/pci/pcireg.h>
69 #include <dev/pci/pcivar.h>
70
71 #include <dev/bfe/if_bfereg.h>
72
73 MODULE_DEPEND(bfe, pci, 1, 1, 1);
74 MODULE_DEPEND(bfe, ether, 1, 1, 1);
75 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
76
77 /* "controller miibus0" required. See GENERIC if you get errors here. */
78 #include "miibus_if.h"
79
80 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
81
82 static struct bfe_type bfe_devs[] = {
83 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401,
84 "Broadcom BCM4401 Fast Ethernet" },
85 { 0, 0, NULL }
86 };
87
88 static int bfe_probe (device_t);
89 static int bfe_attach (device_t);
90 static int bfe_detach (device_t);
91 static void bfe_release_resources (struct bfe_softc *);
92 static void bfe_intr (void *);
93 static void bfe_start (struct ifnet *);
94 static int bfe_ioctl (struct ifnet *, u_long, caddr_t);
95 static void bfe_init (void *);
96 static void bfe_stop (struct bfe_softc *);
97 static void bfe_watchdog (struct ifnet *);
98 static void bfe_shutdown (device_t);
99 static void bfe_tick (void *);
100 static void bfe_txeof (struct bfe_softc *);
101 static void bfe_rxeof (struct bfe_softc *);
102 static void bfe_set_rx_mode (struct bfe_softc *);
103 static int bfe_list_rx_init (struct bfe_softc *);
104 static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*);
105 static void bfe_rx_ring_free (struct bfe_softc *);
106
107 static void bfe_pci_setup (struct bfe_softc *, u_int32_t);
108 static int bfe_ifmedia_upd (struct ifnet *);
109 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *);
110 static int bfe_miibus_readreg (device_t, int, int);
111 static int bfe_miibus_writereg (device_t, int, int, int);
112 static void bfe_miibus_statchg (device_t);
113 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t,
114 u_long, const int);
115 static void bfe_get_config (struct bfe_softc *sc);
116 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *);
117 static void bfe_stats_update (struct bfe_softc *);
118 static void bfe_clear_stats (struct bfe_softc *);
119 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*);
120 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t);
121 static int bfe_resetphy (struct bfe_softc *);
122 static int bfe_setupphy (struct bfe_softc *);
123 static void bfe_chip_reset (struct bfe_softc *);
124 static void bfe_chip_halt (struct bfe_softc *);
125 static void bfe_core_reset (struct bfe_softc *);
126 static void bfe_core_disable (struct bfe_softc *);
127 static int bfe_dma_alloc (device_t);
128 static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int);
129 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int);
130 static void bfe_cam_write (struct bfe_softc *, u_char *, int);
131
132 static device_method_t bfe_methods[] = {
133 /* Device interface */
134 DEVMETHOD(device_probe, bfe_probe),
135 DEVMETHOD(device_attach, bfe_attach),
136 DEVMETHOD(device_detach, bfe_detach),
137 DEVMETHOD(device_shutdown, bfe_shutdown),
138
139 /* bus interface */
140 DEVMETHOD(bus_print_child, bus_generic_print_child),
141 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
142
143 /* MII interface */
144 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
145 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
146 DEVMETHOD(miibus_statchg, bfe_miibus_statchg),
147
148 { 0, 0 }
149 };
150
151 static driver_t bfe_driver = {
152 "bfe",
153 bfe_methods,
154 sizeof(struct bfe_softc)
155 };
156
157 static devclass_t bfe_devclass;
158
159 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
160 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
161
162 /*
163 * Probe for a Broadcom 4401 chip.
164 */
165 static int
166 bfe_probe(device_t dev)
167 {
168 struct bfe_type *t;
169 struct bfe_softc *sc;
170
171 t = bfe_devs;
172
173 sc = device_get_softc(dev);
174 bzero(sc, sizeof(struct bfe_softc));
175 sc->bfe_unit = device_get_unit(dev);
176 sc->bfe_dev = dev;
177
178 while(t->bfe_name != NULL) {
179 if ((pci_get_vendor(dev) == t->bfe_vid) &&
180 (pci_get_device(dev) == t->bfe_did)) {
181 device_set_desc_copy(dev, t->bfe_name);
182 return(0);
183 }
184 t++;
185 }
186
187 return(ENXIO);
188 }
189
190 static int
191 bfe_dma_alloc(device_t dev)
192 {
193 struct bfe_softc *sc;
194 int error, i;
195
196 sc = device_get_softc(dev);
197
198 /* parent tag */
199 error = bus_dma_tag_create(NULL, /* parent */
200 PAGE_SIZE, 0, /* alignment, boundary */
201 BUS_SPACE_MAXADDR, /* lowaddr */
202 BUS_SPACE_MAXADDR_32BIT, /* highaddr */
203 NULL, NULL, /* filter, filterarg */
204 MAXBSIZE, /* maxsize */
205 BUS_SPACE_UNRESTRICTED, /* num of segments */
206 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */
207 BUS_DMA_ALLOCNOW, /* flags */
208 NULL, NULL, /* lockfunc, lockarg */
209 &sc->bfe_parent_tag);
210
211 /* tag for TX ring */
212 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_TX_LIST_SIZE,
213 BFE_TX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
214 NULL, NULL, BFE_TX_LIST_SIZE, 1, BUS_SPACE_MAXSIZE_32BIT,
215 0, NULL, NULL, &sc->bfe_tx_tag);
216
217 if (error) {
218 device_printf(dev, "could not allocate dma tag\n");
219 return(ENOMEM);
220 }
221
222 /* tag for RX ring */
223 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_RX_LIST_SIZE,
224 BFE_RX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
225 NULL, NULL, BFE_RX_LIST_SIZE, 1, BUS_SPACE_MAXSIZE_32BIT,
226 0, NULL, NULL, &sc->bfe_rx_tag);
227
228 if (error) {
229 device_printf(dev, "could not allocate dma tag\n");
230 return(ENOMEM);
231 }
232
233 /* tag for mbufs */
234 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0,
235 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
236 1, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, &sc->bfe_tag);
237
238 if (error) {
239 device_printf(dev, "could not allocate dma tag\n");
240 return(ENOMEM);
241 }
242
243 /* pre allocate dmamaps for RX list */
244 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
245 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_rx_ring[i].bfe_map);
246 if (error) {
247 device_printf(dev, "cannot create DMA map for RX\n");
248 return(ENOMEM);
249 }
250 }
251
252 /* pre allocate dmamaps for TX list */
253 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
254 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_tx_ring[i].bfe_map);
255 if (error) {
256 device_printf(dev, "cannot create DMA map for TX\n");
257 return(ENOMEM);
258 }
259 }
260
261 /* Alloc dma for rx ring */
262 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
263 BUS_DMA_NOWAIT, &sc->bfe_rx_map);
264
265 if(error)
266 return(ENOMEM);
267
268 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
269 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
270 sc->bfe_rx_list, sizeof(struct bfe_desc),
271 bfe_dma_map, &sc->bfe_rx_dma, 0);
272
273 if(error)
274 return(ENOMEM);
275
276 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
277
278 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
279 BUS_DMA_NOWAIT, &sc->bfe_tx_map);
280 if (error)
281 return(ENOMEM);
282
283
284 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
285 sc->bfe_tx_list, sizeof(struct bfe_desc),
286 bfe_dma_map, &sc->bfe_tx_dma, 0);
287 if(error)
288 return(ENOMEM);
289
290 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
291 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
292
293 return(0);
294 }
295
296 static int
297 bfe_attach(device_t dev)
298 {
299 struct ifnet *ifp;
300 struct bfe_softc *sc;
301 int unit, error = 0, rid;
302
303 sc = device_get_softc(dev);
304 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
305 MTX_DEF | MTX_RECURSE);
306
307 unit = device_get_unit(dev);
308 sc->bfe_dev = dev;
309 sc->bfe_unit = unit;
310
311 /*
312 * Handle power management nonsense.
313 */
314 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
315 u_int32_t membase, irq;
316
317 /* Save important PCI config data. */
318 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4);
319 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4);
320
321 /* Reset the power state. */
322 printf("bfe%d: chip is is in D%d power mode -- setting to D0\n",
323 sc->bfe_unit, pci_get_powerstate(dev));
324
325 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
326
327 /* Restore PCI config data. */
328 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4);
329 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4);
330 }
331
332 /*
333 * Map control/status registers.
334 */
335 pci_enable_busmaster(dev);
336
337 rid = BFE_PCI_MEMLO;
338 sc->bfe_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1,
339 RF_ACTIVE);
340 if (sc->bfe_res == NULL) {
341 printf ("bfe%d: couldn't map memory\n", unit);
342 error = ENXIO;
343 goto fail;
344 }
345
346 sc->bfe_btag = rman_get_bustag(sc->bfe_res);
347 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res);
348 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res);
349
350 /* Allocate interrupt */
351 rid = 0;
352
353 sc->bfe_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
354 RF_SHAREABLE | RF_ACTIVE);
355 if (sc->bfe_irq == NULL) {
356 printf("bfe%d: couldn't map interrupt\n", unit);
357 error = ENXIO;
358 goto fail;
359 }
360
361 if (bfe_dma_alloc(dev)) {
362 printf("bfe%d: failed to allocate DMA resources\n", sc->bfe_unit);
363 bfe_release_resources(sc);
364 error = ENXIO;
365 goto fail;
366 }
367
368 /* Set up ifnet structure */
369 ifp = &sc->arpcom.ac_if;
370 ifp->if_softc = sc;
371 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
372 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
373 ifp->if_ioctl = bfe_ioctl;
374 ifp->if_output = ether_output;
375 ifp->if_start = bfe_start;
376 ifp->if_watchdog = bfe_watchdog;
377 ifp->if_init = bfe_init;
378 ifp->if_mtu = ETHERMTU;
379 ifp->if_baudrate = 10000000;
380 ifp->if_snd.ifq_maxlen = BFE_TX_QLEN;
381
382 bfe_get_config(sc);
383
384 printf("bfe%d: Ethernet address: %6D\n", unit, sc->arpcom.ac_enaddr, ":");
385
386 /* Reset the chip and turn on the PHY */
387 bfe_chip_reset(sc);
388
389 if (mii_phy_probe(dev, &sc->bfe_miibus,
390 bfe_ifmedia_upd, bfe_ifmedia_sts)) {
391 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit);
392 error = ENXIO;
393 goto fail;
394 }
395
396 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
397 callout_handle_init(&sc->bfe_stat_ch);
398
399 /*
400 * Hook interrupt last to avoid having to lock softc
401 */
402 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET,
403 bfe_intr, sc, &sc->bfe_intrhand);
404
405 if (error) {
406 bfe_release_resources(sc);
407 printf("bfe%d: couldn't set up irq\n", unit);
408 goto fail;
409 }
410 fail:
411 if(error)
412 bfe_release_resources(sc);
413 return(error);
414 }
415
416 static int
417 bfe_detach(device_t dev)
418 {
419 struct bfe_softc *sc;
420 struct ifnet *ifp;
421
422 sc = device_get_softc(dev);
423
424 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized"));
425 BFE_LOCK(scp);
426
427 ifp = &sc->arpcom.ac_if;
428
429 if (device_is_attached(dev)) {
430 bfe_stop(sc);
431 ether_ifdetach(ifp);
432 }
433
434 bfe_chip_reset(sc);
435
436 bus_generic_detach(dev);
437 if(sc->bfe_miibus != NULL)
438 device_delete_child(dev, sc->bfe_miibus);
439
440 bfe_release_resources(sc);
441 BFE_UNLOCK(sc);
442 mtx_destroy(&sc->bfe_mtx);
443
444 return(0);
445 }
446
447 /*
448 * Stop all chip I/O so that the kernel's probe routines don't
449 * get confused by errant DMAs when rebooting.
450 */
451 static void
452 bfe_shutdown(device_t dev)
453 {
454 struct bfe_softc *sc;
455
456 sc = device_get_softc(dev);
457 BFE_LOCK(sc);
458 bfe_stop(sc);
459
460 BFE_UNLOCK(sc);
461 return;
462 }
463
464 static int
465 bfe_miibus_readreg(device_t dev, int phy, int reg)
466 {
467 struct bfe_softc *sc;
468 u_int32_t ret;
469
470 sc = device_get_softc(dev);
471 if(phy != sc->bfe_phyaddr)
472 return(0);
473 bfe_readphy(sc, reg, &ret);
474
475 return(ret);
476 }
477
478 static int
479 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
480 {
481 struct bfe_softc *sc;
482
483 sc = device_get_softc(dev);
484 if(phy != sc->bfe_phyaddr)
485 return(0);
486 bfe_writephy(sc, reg, val);
487
488 return(0);
489 }
490
491 static void
492 bfe_miibus_statchg(device_t dev)
493 {
494 return;
495 }
496
497 static void
498 bfe_tx_ring_free(struct bfe_softc *sc)
499 {
500 int i;
501
502 for(i = 0; i < BFE_TX_LIST_CNT; i++) {
503 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
504 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
505 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
506 bus_dmamap_unload(sc->bfe_tag,
507 sc->bfe_tx_ring[i].bfe_map);
508 bus_dmamap_destroy(sc->bfe_tag,
509 sc->bfe_tx_ring[i].bfe_map);
510 }
511 }
512 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
513 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
514 }
515
516 static void
517 bfe_rx_ring_free(struct bfe_softc *sc)
518 {
519 int i;
520
521 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
522 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
523 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
524 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
525 bus_dmamap_unload(sc->bfe_tag,
526 sc->bfe_rx_ring[i].bfe_map);
527 bus_dmamap_destroy(sc->bfe_tag,
528 sc->bfe_rx_ring[i].bfe_map);
529 }
530 }
531 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
532 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
533 }
534
535
536 static int
537 bfe_list_rx_init(struct bfe_softc *sc)
538 {
539 int i;
540
541 for(i = 0; i < BFE_RX_LIST_CNT; i++) {
542 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS)
543 return ENOBUFS;
544 }
545
546 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
547 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
548
549 sc->bfe_rx_cons = 0;
550
551 return(0);
552 }
553
554 static int
555 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m)
556 {
557 struct bfe_rxheader *rx_header;
558 struct bfe_desc *d;
559 struct bfe_data *r;
560 u_int32_t ctrl;
561
562 if ((c < 0) || (c >= BFE_RX_LIST_CNT))
563 return(EINVAL);
564
565 if(m == NULL) {
566 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
567 if(m == NULL)
568 return(ENOBUFS);
569 m->m_len = m->m_pkthdr.len = MCLBYTES;
570 }
571 else
572 m->m_data = m->m_ext.ext_buf;
573
574 rx_header = mtod(m, struct bfe_rxheader *);
575 rx_header->len = 0;
576 rx_header->flags = 0;
577
578 /* Map the mbuf into DMA */
579 sc->bfe_rx_cnt = c;
580 d = &sc->bfe_rx_list[c];
581 r = &sc->bfe_rx_ring[c];
582 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *),
583 MCLBYTES, bfe_dma_map_desc, d, 0);
584 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE);
585
586 ctrl = ETHER_MAX_LEN + 32;
587
588 if(c == BFE_RX_LIST_CNT - 1)
589 ctrl |= BFE_DESC_EOT;
590
591 d->bfe_ctrl = ctrl;
592 r->bfe_mbuf = m;
593 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
594 return(0);
595 }
596
597 static void
598 bfe_get_config(struct bfe_softc *sc)
599 {
600 u_int8_t eeprom[128];
601
602 bfe_read_eeprom(sc, eeprom);
603
604 sc->arpcom.ac_enaddr[0] = eeprom[79];
605 sc->arpcom.ac_enaddr[1] = eeprom[78];
606 sc->arpcom.ac_enaddr[2] = eeprom[81];
607 sc->arpcom.ac_enaddr[3] = eeprom[80];
608 sc->arpcom.ac_enaddr[4] = eeprom[83];
609 sc->arpcom.ac_enaddr[5] = eeprom[82];
610
611 sc->bfe_phyaddr = eeprom[90] & 0x1f;
612 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
613
614 sc->bfe_core_unit = 0;
615 sc->bfe_dma_offset = BFE_PCI_DMA;
616 }
617
618 static void
619 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores)
620 {
621 u_int32_t bar_orig, pci_rev, val;
622
623 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
624 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
625 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
626
627 val = CSR_READ_4(sc, BFE_SBINTVEC);
628 val |= cores;
629 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
630
631 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
632 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
633 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
634
635 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
636 }
637
638 static void
639 bfe_clear_stats(struct bfe_softc *sc)
640 {
641 u_long reg;
642
643 BFE_LOCK(sc);
644
645 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
646 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
647 CSR_READ_4(sc, reg);
648 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
649 CSR_READ_4(sc, reg);
650
651 BFE_UNLOCK(sc);
652 }
653
654 static int
655 bfe_resetphy(struct bfe_softc *sc)
656 {
657 u_int32_t val;
658
659 BFE_LOCK(sc);
660 bfe_writephy(sc, 0, BMCR_RESET);
661 DELAY(100);
662 bfe_readphy(sc, 0, &val);
663 if (val & BMCR_RESET) {
664 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit);
665 BFE_UNLOCK(sc);
666 return ENXIO;
667 }
668 BFE_UNLOCK(sc);
669 return 0;
670 }
671
672 static void
673 bfe_chip_halt(struct bfe_softc *sc)
674 {
675 BFE_LOCK(sc);
676 /* disable interrupts - not that it actually does..*/
677 CSR_WRITE_4(sc, BFE_IMASK, 0);
678 CSR_READ_4(sc, BFE_IMASK);
679
680 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
681 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
682
683 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
684 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
685 DELAY(10);
686
687 BFE_UNLOCK(sc);
688 }
689
690 static void
691 bfe_chip_reset(struct bfe_softc *sc)
692 {
693 u_int32_t val;
694
695 BFE_LOCK(sc);
696
697 /* Set the interrupt vector for the enet core */
698 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
699
700 /* is core up? */
701 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK);
702 if (val == BFE_CLOCK) {
703 /* It is, so shut it down */
704 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
705 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
706 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
707 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
708 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
709 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
710 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0);
711 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
712 sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
713 }
714
715 bfe_core_reset(sc);
716 bfe_clear_stats(sc);
717
718 /*
719 * We want the phy registers to be accessible even when
720 * the driver is "downed" so initialize MDC preamble, frequency,
721 * and whether internal or external phy here.
722 */
723
724 /* 4402 has 62.5Mhz SB clock and internal phy */
725 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
726
727 /* Internal or external PHY? */
728 val = CSR_READ_4(sc, BFE_DEVCTRL);
729 if(!(val & BFE_IPP))
730 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
731 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
732 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
733 DELAY(100);
734 }
735
736 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB);
737 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
738 BFE_LAZY_FC_MASK));
739
740 /*
741 * We don't want lazy interrupts, so just send them at the end of a frame,
742 * please
743 */
744 BFE_OR(sc, BFE_RCV_LAZY, 0);
745
746 /* Set max lengths, accounting for VLAN tags */
747 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
748 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
749
750 /* Set watermark XXX - magic */
751 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
752
753 /*
754 * Initialise DMA channels - not forgetting dma addresses need to be added
755 * to BFE_PCI_DMA
756 */
757 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
758 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
759
760 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
761 BFE_RX_CTRL_ENABLE);
762 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
763
764 bfe_resetphy(sc);
765 bfe_setupphy(sc);
766
767 BFE_UNLOCK(sc);
768 }
769
770 static void
771 bfe_core_disable(struct bfe_softc *sc)
772 {
773 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
774 return;
775
776 /*
777 * Set reject, wait for it set, then wait for the core to stop being busy
778 * Then set reset and reject and enable the clocks
779 */
780 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
781 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
782 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
783 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
784 BFE_RESET));
785 CSR_READ_4(sc, BFE_SBTMSLOW);
786 DELAY(10);
787 /* Leave reset and reject set */
788 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
789 DELAY(10);
790 }
791
792 static void
793 bfe_core_reset(struct bfe_softc *sc)
794 {
795 u_int32_t val;
796
797 /* Disable the core */
798 bfe_core_disable(sc);
799
800 /* and bring it back up */
801 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
802 CSR_READ_4(sc, BFE_SBTMSLOW);
803 DELAY(10);
804
805 /* Chip bug, clear SERR, IB and TO if they are set. */
806 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
807 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
808 val = CSR_READ_4(sc, BFE_SBIMSTATE);
809 if (val & (BFE_IBE | BFE_TO))
810 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
811
812 /* Clear reset and allow it to move through the core */
813 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
814 CSR_READ_4(sc, BFE_SBTMSLOW);
815 DELAY(10);
816
817 /* Leave the clock set */
818 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
819 CSR_READ_4(sc, BFE_SBTMSLOW);
820 DELAY(10);
821 }
822
823 static void
824 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
825 {
826 u_int32_t val;
827
828 val = ((u_int32_t) data[2]) << 24;
829 val |= ((u_int32_t) data[3]) << 16;
830 val |= ((u_int32_t) data[4]) << 8;
831 val |= ((u_int32_t) data[5]);
832 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
833 val = (BFE_CAM_HI_VALID |
834 (((u_int32_t) data[0]) << 8) |
835 (((u_int32_t) data[1])));
836 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
837 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
838 (index << BFE_CAM_INDEX_SHIFT)));
839 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
840 }
841
842 static void
843 bfe_set_rx_mode(struct bfe_softc *sc)
844 {
845 struct ifnet *ifp = &sc->arpcom.ac_if;
846 struct ifmultiaddr *ifma;
847 u_int32_t val;
848 int i = 0;
849
850 val = CSR_READ_4(sc, BFE_RXCONF);
851
852 if (ifp->if_flags & IFF_PROMISC)
853 val |= BFE_RXCONF_PROMISC;
854 else
855 val &= ~BFE_RXCONF_PROMISC;
856
857 if (ifp->if_flags & IFF_BROADCAST)
858 val &= ~BFE_RXCONF_DBCAST;
859 else
860 val |= BFE_RXCONF_DBCAST;
861
862
863 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
864 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++);
865
866 if (ifp->if_flags & IFF_ALLMULTI)
867 val |= BFE_RXCONF_ALLMULTI;
868 else {
869 val &= ~BFE_RXCONF_ALLMULTI;
870 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
871 if (ifma->ifma_addr->sa_family != AF_LINK)
872 continue;
873 bfe_cam_write(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
874 i++);
875 }
876 }
877
878 CSR_WRITE_4(sc, BFE_RXCONF, val);
879 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
880 }
881
882 static void
883 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
884 {
885 u_int32_t *ptr;
886
887 ptr = arg;
888 *ptr = segs->ds_addr;
889 }
890
891 static void
892 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error)
893 {
894 struct bfe_desc *d;
895
896 d = arg;
897 /* The chip needs all addresses to be added to BFE_PCI_DMA */
898 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA;
899 }
900
901 static void
902 bfe_release_resources(struct bfe_softc *sc)
903 {
904 device_t dev;
905 int i;
906
907 dev = sc->bfe_dev;
908
909 if (sc->bfe_vpd_prodname != NULL)
910 free(sc->bfe_vpd_prodname, M_DEVBUF);
911
912 if (sc->bfe_vpd_readonly != NULL)
913 free(sc->bfe_vpd_readonly, M_DEVBUF);
914
915 if (sc->bfe_intrhand != NULL)
916 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand);
917
918 if (sc->bfe_irq != NULL)
919 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq);
920
921 if (sc->bfe_res != NULL)
922 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res);
923
924 if(sc->bfe_tx_tag != NULL) {
925 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
926 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, sc->bfe_tx_map);
927 bus_dma_tag_destroy(sc->bfe_tx_tag);
928 sc->bfe_tx_tag = NULL;
929 }
930
931 if(sc->bfe_rx_tag != NULL) {
932 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
933 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, sc->bfe_rx_map);
934 bus_dma_tag_destroy(sc->bfe_rx_tag);
935 sc->bfe_rx_tag = NULL;
936 }
937
938 if(sc->bfe_tag != NULL) {
939 for(i = 0; i < BFE_TX_LIST_CNT; i++) {
940 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_tx_ring[i].bfe_map);
941 }
942 bus_dma_tag_destroy(sc->bfe_tag);
943 sc->bfe_tag = NULL;
944 }
945
946 if(sc->bfe_parent_tag != NULL)
947 bus_dma_tag_destroy(sc->bfe_parent_tag);
948
949 return;
950 }
951
952 static void
953 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data)
954 {
955 long i;
956 u_int16_t *ptr = (u_int16_t *)data;
957
958 for(i = 0; i < 128; i += 2)
959 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
960 }
961
962 static int
963 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit,
964 u_long timeout, const int clear)
965 {
966 u_long i;
967
968 for (i = 0; i < timeout; i++) {
969 u_int32_t val = CSR_READ_4(sc, reg);
970
971 if (clear && !(val & bit))
972 break;
973 if (!clear && (val & bit))
974 break;
975 DELAY(10);
976 }
977 if (i == timeout) {
978 printf("bfe%d: BUG! Timeout waiting for bit %08x of register "
979 "%x to %s.\n", sc->bfe_unit, bit, reg,
980 (clear ? "clear" : "set"));
981 return -1;
982 }
983 return 0;
984 }
985
986 static int
987 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val)
988 {
989 int err;
990
991 BFE_LOCK(sc);
992 /* Clear MII ISR */
993 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
994 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
995 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
996 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
997 (reg << BFE_MDIO_RA_SHIFT) |
998 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
999 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1000 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
1001
1002 BFE_UNLOCK(sc);
1003 return err;
1004 }
1005
1006 static int
1007 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val)
1008 {
1009 int status;
1010
1011 BFE_LOCK(sc);
1012 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1013 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1014 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1015 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1016 (reg << BFE_MDIO_RA_SHIFT) |
1017 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1018 (val & BFE_MDIO_DATA_DATA)));
1019 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1020 BFE_UNLOCK(sc);
1021
1022 return status;
1023 }
1024
1025 /*
1026 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1027 * twice
1028 */
1029 static int
1030 bfe_setupphy(struct bfe_softc *sc)
1031 {
1032 u_int32_t val;
1033 BFE_LOCK(sc);
1034
1035 /* Enable activity LED */
1036 bfe_readphy(sc, 26, &val);
1037 bfe_writephy(sc, 26, val & 0x7fff);
1038 bfe_readphy(sc, 26, &val);
1039
1040 /* Enable traffic meter LED mode */
1041 bfe_readphy(sc, 27, &val);
1042 bfe_writephy(sc, 27, val | (1 << 6));
1043
1044 BFE_UNLOCK(sc);
1045 return 0;
1046 }
1047
1048 static void
1049 bfe_stats_update(struct bfe_softc *sc)
1050 {
1051 u_long reg;
1052 u_int32_t *val;
1053
1054 val = &sc->bfe_hwstats.tx_good_octets;
1055 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) {
1056 *val++ += CSR_READ_4(sc, reg);
1057 }
1058 val = &sc->bfe_hwstats.rx_good_octets;
1059 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) {
1060 *val++ += CSR_READ_4(sc, reg);
1061 }
1062 }
1063
1064 static void
1065 bfe_txeof(struct bfe_softc *sc)
1066 {
1067 struct ifnet *ifp;
1068 int i, chipidx;
1069
1070 BFE_LOCK(sc);
1071
1072 ifp = &sc->arpcom.ac_if;
1073
1074 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1075 chipidx /= sizeof(struct bfe_desc);
1076
1077 i = sc->bfe_tx_cons;
1078 /* Go through the mbufs and free those that have been transmitted */
1079 while(i != chipidx) {
1080 struct bfe_data *r = &sc->bfe_tx_ring[i];
1081 if(r->bfe_mbuf != NULL) {
1082 ifp->if_opackets++;
1083 m_freem(r->bfe_mbuf);
1084 r->bfe_mbuf = NULL;
1085 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1086 }
1087 sc->bfe_tx_cnt--;
1088 BFE_INC(i, BFE_TX_LIST_CNT);
1089 }
1090
1091 if(i != sc->bfe_tx_cons) {
1092 /* we freed up some mbufs */
1093 sc->bfe_tx_cons = i;
1094 ifp->if_flags &= ~IFF_OACTIVE;
1095 }
1096 if(sc->bfe_tx_cnt == 0)
1097 ifp->if_timer = 0;
1098 else
1099 ifp->if_timer = 5;
1100
1101 BFE_UNLOCK(sc);
1102 }
1103
1104 /* Pass a received packet up the stack */
1105 static void
1106 bfe_rxeof(struct bfe_softc *sc)
1107 {
1108 struct mbuf *m;
1109 struct ifnet *ifp;
1110 struct bfe_rxheader *rxheader;
1111 struct bfe_data *r;
1112 int cons;
1113 u_int32_t status, current, len, flags;
1114
1115 BFE_LOCK(sc);
1116 cons = sc->bfe_rx_cons;
1117 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1118 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1119
1120 ifp = &sc->arpcom.ac_if;
1121
1122 while(current != cons) {
1123 r = &sc->bfe_rx_ring[cons];
1124 m = r->bfe_mbuf;
1125 rxheader = mtod(m, struct bfe_rxheader*);
1126 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE);
1127 len = rxheader->len;
1128 r->bfe_mbuf = NULL;
1129
1130 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1131 flags = rxheader->flags;
1132
1133 len -= ETHER_CRC_LEN;
1134
1135 /* flag an error and try again */
1136 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
1137 ifp->if_ierrors++;
1138 if (flags & BFE_RX_FLAG_SERR)
1139 ifp->if_collisions++;
1140 bfe_list_newbuf(sc, cons, m);
1141 continue;
1142 }
1143
1144 /* Go past the rx header */
1145 if (bfe_list_newbuf(sc, cons, NULL) == 0) {
1146 m_adj(m, BFE_RX_OFFSET);
1147 m->m_len = m->m_pkthdr.len = len;
1148 } else {
1149 bfe_list_newbuf(sc, cons, m);
1150 ifp->if_ierrors++;
1151 continue;
1152 }
1153
1154 ifp->if_ipackets++;
1155 m->m_pkthdr.rcvif = ifp;
1156 BFE_UNLOCK(sc);
1157 (*ifp->if_input)(ifp, m);
1158 BFE_LOCK(sc);
1159
1160 BFE_INC(cons, BFE_RX_LIST_CNT);
1161 }
1162 sc->bfe_rx_cons = cons;
1163 BFE_UNLOCK(sc);
1164 }
1165
1166 static void
1167 bfe_intr(void *xsc)
1168 {
1169 struct bfe_softc *sc = xsc;
1170 struct ifnet *ifp;
1171 u_int32_t istat, imask, flag;
1172
1173 ifp = &sc->arpcom.ac_if;
1174
1175 BFE_LOCK(sc);
1176
1177 istat = CSR_READ_4(sc, BFE_ISTAT);
1178 imask = CSR_READ_4(sc, BFE_IMASK);
1179
1180 /*
1181 * Defer unsolicited interrupts - This is necessary because setting the
1182 * chips interrupt mask register to 0 doesn't actually stop the
1183 * interrupts
1184 */
1185 istat &= imask;
1186 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1187 CSR_READ_4(sc, BFE_ISTAT);
1188
1189 /* not expecting this interrupt, disregard it */
1190 if(istat == 0) {
1191 BFE_UNLOCK(sc);
1192 return;
1193 }
1194
1195 if(istat & BFE_ISTAT_ERRORS) {
1196 flag = CSR_READ_4(sc, BFE_DMATX_STAT);
1197 if(flag & BFE_STAT_EMASK)
1198 ifp->if_oerrors++;
1199
1200 flag = CSR_READ_4(sc, BFE_DMARX_STAT);
1201 if(flag & BFE_RX_FLAG_ERRORS)
1202 ifp->if_ierrors++;
1203
1204 ifp->if_flags &= ~IFF_RUNNING;
1205 bfe_init(sc);
1206 }
1207
1208 /* A packet was received */
1209 if(istat & BFE_ISTAT_RX)
1210 bfe_rxeof(sc);
1211
1212 /* A packet was sent */
1213 if(istat & BFE_ISTAT_TX)
1214 bfe_txeof(sc);
1215
1216 /* We have packets pending, fire them out */
1217 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
1218 bfe_start(ifp);
1219
1220 BFE_UNLOCK(sc);
1221 }
1222
1223 static int
1224 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
1225 {
1226 struct bfe_desc *d = NULL;
1227 struct bfe_data *r = NULL;
1228 struct mbuf *m;
1229 u_int32_t frag, cur, cnt = 0;
1230 int chainlen = 0;
1231
1232 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2)
1233 return(ENOBUFS);
1234
1235 /*
1236 * Count the number of frags in this chain to see if
1237 * we need to m_defrag. Since the descriptor list is shared
1238 * by all packets, we'll m_defrag long chains so that they
1239 * do not use up the entire list, even if they would fit.
1240 */
1241 for(m = m_head; m != NULL; m = m->m_next)
1242 chainlen++;
1243
1244
1245 if ((chainlen > BFE_TX_LIST_CNT / 4) ||
1246 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) {
1247 m = m_defrag(m_head, M_DONTWAIT);
1248 if (m == NULL)
1249 return(ENOBUFS);
1250 m_head = m;
1251 }
1252
1253 /*
1254 * Start packing the mbufs in this chain into
1255 * the fragment pointers. Stop when we run out
1256 * of fragments or hit the end of the mbuf chain.
1257 */
1258 m = m_head;
1259 cur = frag = *txidx;
1260 cnt = 0;
1261
1262 for(m = m_head; m != NULL; m = m->m_next) {
1263 if(m->m_len != 0) {
1264 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2)
1265 return(ENOBUFS);
1266
1267 d = &sc->bfe_tx_list[cur];
1268 r = &sc->bfe_tx_ring[cur];
1269 d->bfe_ctrl = BFE_DESC_LEN & m->m_len;
1270 /* always intterupt on completion */
1271 d->bfe_ctrl |= BFE_DESC_IOC;
1272 if(cnt == 0)
1273 /* Set start of frame */
1274 d->bfe_ctrl |= BFE_DESC_SOF;
1275 if(cur == BFE_TX_LIST_CNT - 1)
1276 /* Tell the chip to wrap to the start of the descriptor list */
1277 d->bfe_ctrl |= BFE_DESC_EOT;
1278
1279 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void*), m->m_len,
1280 bfe_dma_map_desc, d, 0);
1281 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREREAD);
1282
1283 frag = cur;
1284 BFE_INC(cur, BFE_TX_LIST_CNT);
1285 cnt++;
1286 }
1287 }
1288
1289 if (m != NULL)
1290 return(ENOBUFS);
1291
1292 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF;
1293 sc->bfe_tx_ring[frag].bfe_mbuf = m_head;
1294 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
1295
1296 *txidx = cur;
1297 sc->bfe_tx_cnt += cnt;
1298 return (0);
1299 }
1300
1301 /*
1302 * Set up to transmit a packet
1303 */
1304 static void
1305 bfe_start(struct ifnet *ifp)
1306 {
1307 struct bfe_softc *sc;
1308 struct mbuf *m_head = NULL;
1309 int idx;
1310
1311 sc = ifp->if_softc;
1312 idx = sc->bfe_tx_prod;
1313
1314 BFE_LOCK(sc);
1315
1316 /*
1317 * not much point trying to send if the link is down or we have nothing to
1318 * send
1319 */
1320 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) {
1321 BFE_UNLOCK(sc);
1322 return;
1323 }
1324
1325 if (ifp->if_flags & IFF_OACTIVE) {
1326 BFE_UNLOCK(sc);
1327 return;
1328 }
1329
1330 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) {
1331 IF_DEQUEUE(&ifp->if_snd, m_head);
1332 if(m_head == NULL)
1333 break;
1334
1335 /*
1336 * Pack the data into the tx ring. If we dont have enough room, let
1337 * the chip drain the ring
1338 */
1339 if(bfe_encap(sc, m_head, &idx)) {
1340 IF_PREPEND(&ifp->if_snd, m_head);
1341 ifp->if_flags |= IFF_OACTIVE;
1342 break;
1343 }
1344
1345 /*
1346 * If there's a BPF listener, bounce a copy of this frame
1347 * to him.
1348 */
1349 BPF_MTAP(ifp, m_head);
1350 }
1351
1352 sc->bfe_tx_prod = idx;
1353 /* Transmit - twice due to apparent hardware bug */
1354 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1355 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1356
1357 /*
1358 * Set a timeout in case the chip goes out to lunch.
1359 */
1360 ifp->if_timer = 5;
1361 BFE_UNLOCK(sc);
1362 }
1363
1364 static void
1365 bfe_init(void *xsc)
1366 {
1367 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1368 struct ifnet *ifp = &sc->arpcom.ac_if;
1369
1370 BFE_LOCK(sc);
1371
1372 if (ifp->if_flags & IFF_RUNNING) {
1373 BFE_UNLOCK(sc);
1374 return;
1375 }
1376
1377 bfe_stop(sc);
1378 bfe_chip_reset(sc);
1379
1380 if (bfe_list_rx_init(sc) == ENOBUFS) {
1381 printf("bfe%d: bfe_init failed. Not enough memory for list buffers\n",
1382 sc->bfe_unit);
1383 bfe_stop(sc);
1384 return;
1385 }
1386
1387 bfe_set_rx_mode(sc);
1388
1389 /* Enable the chip and core */
1390 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1391 /* Enable interrupts */
1392 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1393
1394 bfe_ifmedia_upd(ifp);
1395 ifp->if_flags |= IFF_RUNNING;
1396 ifp->if_flags &= ~IFF_OACTIVE;
1397
1398 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz);
1399 BFE_UNLOCK(sc);
1400 }
1401
1402 /*
1403 * Set media options.
1404 */
1405 static int
1406 bfe_ifmedia_upd(struct ifnet *ifp)
1407 {
1408 struct bfe_softc *sc;
1409 struct mii_data *mii;
1410
1411 sc = ifp->if_softc;
1412
1413 BFE_LOCK(sc);
1414
1415 mii = device_get_softc(sc->bfe_miibus);
1416 sc->bfe_link = 0;
1417 if (mii->mii_instance) {
1418 struct mii_softc *miisc;
1419 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1420 miisc = LIST_NEXT(miisc, mii_list))
1421 mii_phy_reset(miisc);
1422 }
1423 mii_mediachg(mii);
1424
1425 BFE_UNLOCK(sc);
1426 return(0);
1427 }
1428
1429 /*
1430 * Report current media status.
1431 */
1432 static void
1433 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1434 {
1435 struct bfe_softc *sc = ifp->if_softc;
1436 struct mii_data *mii;
1437
1438 BFE_LOCK(sc);
1439
1440 mii = device_get_softc(sc->bfe_miibus);
1441 mii_pollstat(mii);
1442 ifmr->ifm_active = mii->mii_media_active;
1443 ifmr->ifm_status = mii->mii_media_status;
1444
1445 BFE_UNLOCK(sc);
1446 }
1447
1448 static int
1449 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1450 {
1451 struct bfe_softc *sc = ifp->if_softc;
1452 struct ifreq *ifr = (struct ifreq *) data;
1453 struct mii_data *mii;
1454 int error = 0;
1455
1456 BFE_LOCK(sc);
1457
1458 switch(command) {
1459 case SIOCSIFFLAGS:
1460 if(ifp->if_flags & IFF_UP)
1461 if(ifp->if_flags & IFF_RUNNING)
1462 bfe_set_rx_mode(sc);
1463 else
1464 bfe_init(sc);
1465 else if(ifp->if_flags & IFF_RUNNING)
1466 bfe_stop(sc);
1467 break;
1468 case SIOCADDMULTI:
1469 case SIOCDELMULTI:
1470 if(ifp->if_flags & IFF_RUNNING)
1471 bfe_set_rx_mode(sc);
1472 break;
1473 case SIOCGIFMEDIA:
1474 case SIOCSIFMEDIA:
1475 mii = device_get_softc(sc->bfe_miibus);
1476 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1477 break;
1478 default:
1479 error = ether_ioctl(ifp, command, data);
1480 break;
1481 }
1482
1483 BFE_UNLOCK(sc);
1484 return error;
1485 }
1486
1487 static void
1488 bfe_watchdog(struct ifnet *ifp)
1489 {
1490 struct bfe_softc *sc;
1491
1492 sc = ifp->if_softc;
1493
1494 BFE_LOCK(sc);
1495
1496 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit);
1497
1498 ifp->if_flags &= ~IFF_RUNNING;
1499 bfe_init(sc);
1500
1501 ifp->if_oerrors++;
1502
1503 BFE_UNLOCK(sc);
1504 }
1505
1506 static void
1507 bfe_tick(void *xsc)
1508 {
1509 struct bfe_softc *sc = xsc;
1510 struct mii_data *mii;
1511
1512 if (sc == NULL)
1513 return;
1514
1515 BFE_LOCK(sc);
1516
1517 mii = device_get_softc(sc->bfe_miibus);
1518
1519 bfe_stats_update(sc);
1520 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz);
1521
1522 if(sc->bfe_link) {
1523 BFE_UNLOCK(sc);
1524 return;
1525 }
1526
1527 mii_tick(mii);
1528 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE &&
1529 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1530 sc->bfe_link++;
1531
1532 BFE_UNLOCK(sc);
1533 }
1534
1535 /*
1536 * Stop the adapter and free any mbufs allocated to the
1537 * RX and TX lists.
1538 */
1539 static void
1540 bfe_stop(struct bfe_softc *sc)
1541 {
1542 struct ifnet *ifp;
1543
1544 BFE_LOCK(sc);
1545
1546 untimeout(bfe_tick, sc, sc->bfe_stat_ch);
1547
1548 ifp = &sc->arpcom.ac_if;
1549
1550 bfe_chip_halt(sc);
1551 bfe_tx_ring_free(sc);
1552 bfe_rx_ring_free(sc);
1553
1554 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1555
1556 BFE_UNLOCK(sc);
1557 }
Cache object: 107449a590e7a2a1d9368fb26a93dc2e
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