Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/bfe/if_bfe.c
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1 /*- 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/malloc.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/socket.h> 39 #include <sys/queue.h> 40 41 #include <net/if.h> 42 #include <net/if_arp.h> 43 #include <net/ethernet.h> 44 #include <net/if_dl.h> 45 #include <net/if_media.h> 46 47 #include <net/bpf.h> 48 49 #include <net/if_types.h> 50 #include <net/if_vlan_var.h> 51 52 #include <netinet/in_systm.h> 53 #include <netinet/in.h> 54 #include <netinet/ip.h> 55 56 #include <machine/clock.h> /* for DELAY */ 57 #include <machine/bus_memio.h> 58 #include <machine/bus.h> 59 #include <machine/resource.h> 60 #include <sys/bus.h> 61 #include <sys/rman.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 #include "miidevs.h" 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 70 #include <dev/bfe/if_bfereg.h> 71 72 MODULE_DEPEND(bfe, pci, 1, 1, 1); 73 MODULE_DEPEND(bfe, ether, 1, 1, 1); 74 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 75 76 /* "controller miibus0" required. See GENERIC if you get errors here. */ 77 #include "miibus_if.h" 78 79 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 80 81 static struct bfe_type bfe_devs[] = { 82 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 83 "Broadcom BCM4401 Fast Ethernet" }, 84 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 85 "Broadcom BCM4401-B0 Fast Ethernet" }, 86 { 0, 0, NULL } 87 }; 88 89 static int bfe_probe (device_t); 90 static int bfe_attach (device_t); 91 static int bfe_detach (device_t); 92 static void bfe_release_resources (struct bfe_softc *); 93 static void bfe_intr (void *); 94 static void bfe_start (struct ifnet *); 95 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 96 static void bfe_init (void *); 97 static void bfe_stop (struct bfe_softc *); 98 static void bfe_watchdog (struct ifnet *); 99 static void bfe_shutdown (device_t); 100 static void bfe_tick (void *); 101 static void bfe_txeof (struct bfe_softc *); 102 static void bfe_rxeof (struct bfe_softc *); 103 static void bfe_set_rx_mode (struct bfe_softc *); 104 static int bfe_list_rx_init (struct bfe_softc *); 105 static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 106 static void bfe_rx_ring_free (struct bfe_softc *); 107 108 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 109 static int bfe_ifmedia_upd (struct ifnet *); 110 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 111 static int bfe_miibus_readreg (device_t, int, int); 112 static int bfe_miibus_writereg (device_t, int, int, int); 113 static void bfe_miibus_statchg (device_t); 114 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 115 u_long, const int); 116 static void bfe_get_config (struct bfe_softc *sc); 117 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 118 static void bfe_stats_update (struct bfe_softc *); 119 static void bfe_clear_stats (struct bfe_softc *); 120 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 121 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 122 static int bfe_resetphy (struct bfe_softc *); 123 static int bfe_setupphy (struct bfe_softc *); 124 static void bfe_chip_reset (struct bfe_softc *); 125 static void bfe_chip_halt (struct bfe_softc *); 126 static void bfe_core_reset (struct bfe_softc *); 127 static void bfe_core_disable (struct bfe_softc *); 128 static int bfe_dma_alloc (device_t); 129 static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 130 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 131 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 132 133 static device_method_t bfe_methods[] = { 134 /* Device interface */ 135 DEVMETHOD(device_probe, bfe_probe), 136 DEVMETHOD(device_attach, bfe_attach), 137 DEVMETHOD(device_detach, bfe_detach), 138 DEVMETHOD(device_shutdown, bfe_shutdown), 139 140 /* bus interface */ 141 DEVMETHOD(bus_print_child, bus_generic_print_child), 142 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 143 144 /* MII interface */ 145 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 146 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 147 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 148 149 { 0, 0 } 150 }; 151 152 static driver_t bfe_driver = { 153 "bfe", 154 bfe_methods, 155 sizeof(struct bfe_softc) 156 }; 157 158 static devclass_t bfe_devclass; 159 160 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 161 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 162 163 /* 164 * Probe for a Broadcom 4401 chip. 165 */ 166 static int 167 bfe_probe(device_t dev) 168 { 169 struct bfe_type *t; 170 struct bfe_softc *sc; 171 172 t = bfe_devs; 173 174 sc = device_get_softc(dev); 175 bzero(sc, sizeof(struct bfe_softc)); 176 sc->bfe_unit = device_get_unit(dev); 177 sc->bfe_dev = dev; 178 179 while(t->bfe_name != NULL) { 180 if ((pci_get_vendor(dev) == t->bfe_vid) && 181 (pci_get_device(dev) == t->bfe_did)) { 182 device_set_desc_copy(dev, t->bfe_name); 183 return (0); 184 } 185 t++; 186 } 187 188 return (ENXIO); 189 } 190 191 static int 192 bfe_dma_alloc(device_t dev) 193 { 194 struct bfe_softc *sc; 195 int error, i; 196 197 sc = device_get_softc(dev); 198 199 /* parent tag */ 200 error = bus_dma_tag_create(NULL, /* parent */ 201 PAGE_SIZE, 0, /* alignment, boundary */ 202 BUS_SPACE_MAXADDR, /* lowaddr */ 203 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 204 NULL, NULL, /* filter, filterarg */ 205 MAXBSIZE, /* maxsize */ 206 BUS_SPACE_UNRESTRICTED, /* num of segments */ 207 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 208 BUS_DMA_ALLOCNOW, /* flags */ 209 NULL, NULL, /* lockfunc, lockarg */ 210 &sc->bfe_parent_tag); 211 212 /* tag for TX ring */ 213 error = bus_dma_tag_create(sc->bfe_parent_tag, 214 BFE_TX_LIST_SIZE, BFE_TX_LIST_SIZE, 215 BUS_SPACE_MAXADDR, 216 BUS_SPACE_MAXADDR, 217 NULL, NULL, 218 BFE_TX_LIST_SIZE, 219 1, 220 BUS_SPACE_MAXSIZE_32BIT, 221 0, 222 NULL, NULL, 223 &sc->bfe_tx_tag); 224 225 if (error) { 226 device_printf(dev, "could not allocate dma tag\n"); 227 return (ENOMEM); 228 } 229 230 /* tag for RX ring */ 231 error = bus_dma_tag_create(sc->bfe_parent_tag, 232 BFE_RX_LIST_SIZE, BFE_RX_LIST_SIZE, 233 BUS_SPACE_MAXADDR, 234 BUS_SPACE_MAXADDR, 235 NULL, NULL, 236 BFE_RX_LIST_SIZE, 237 1, 238 BUS_SPACE_MAXSIZE_32BIT, 239 0, 240 NULL, NULL, 241 &sc->bfe_rx_tag); 242 243 if (error) { 244 device_printf(dev, "could not allocate dma tag\n"); 245 return (ENOMEM); 246 } 247 248 /* tag for mbufs */ 249 error = bus_dma_tag_create(sc->bfe_parent_tag, 250 ETHER_ALIGN, 0, 251 BUS_SPACE_MAXADDR, 252 BUS_SPACE_MAXADDR, 253 NULL, NULL, 254 MCLBYTES, 255 1, 256 BUS_SPACE_MAXSIZE_32BIT, 257 0, 258 NULL, NULL, 259 &sc->bfe_tag); 260 261 if (error) { 262 device_printf(dev, "could not allocate dma tag\n"); 263 return (ENOMEM); 264 } 265 266 /* pre allocate dmamaps for RX list */ 267 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 268 error = bus_dmamap_create(sc->bfe_tag, 0, 269 &sc->bfe_rx_ring[i].bfe_map); 270 if (error) { 271 device_printf(dev, "cannot create DMA map for RX\n"); 272 return (ENOMEM); 273 } 274 } 275 276 /* pre allocate dmamaps for TX list */ 277 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 278 error = bus_dmamap_create(sc->bfe_tag, 0, 279 &sc->bfe_tx_ring[i].bfe_map); 280 if (error) { 281 device_printf(dev, "cannot create DMA map for TX\n"); 282 return (ENOMEM); 283 } 284 } 285 286 /* Alloc dma for rx ring */ 287 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 288 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 289 290 if(error) 291 return (ENOMEM); 292 293 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 294 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 295 sc->bfe_rx_list, sizeof(struct bfe_desc), 296 bfe_dma_map, &sc->bfe_rx_dma, 0); 297 298 if(error) 299 return (ENOMEM); 300 301 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 302 303 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 304 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 305 if (error) 306 return (ENOMEM); 307 308 309 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 310 sc->bfe_tx_list, sizeof(struct bfe_desc), 311 bfe_dma_map, &sc->bfe_tx_dma, 0); 312 if(error) 313 return (ENOMEM); 314 315 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 316 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 317 318 return (0); 319 } 320 321 static int 322 bfe_attach(device_t dev) 323 { 324 struct ifnet *ifp; 325 struct bfe_softc *sc; 326 int unit, error = 0, rid; 327 328 sc = device_get_softc(dev); 329 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 330 MTX_DEF | MTX_RECURSE); 331 332 unit = device_get_unit(dev); 333 sc->bfe_dev = dev; 334 sc->bfe_unit = unit; 335 336 /* 337 * Handle power management nonsense. 338 */ 339 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 340 u_int32_t membase, irq; 341 342 /* Save important PCI config data. */ 343 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 344 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 345 346 /* Reset the power state. */ 347 printf("bfe%d: chip is is in D%d power mode -- setting to D0\n", 348 sc->bfe_unit, pci_get_powerstate(dev)); 349 350 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 351 352 /* Restore PCI config data. */ 353 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 354 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 355 } 356 357 /* 358 * Map control/status registers. 359 */ 360 pci_enable_busmaster(dev); 361 362 rid = BFE_PCI_MEMLO; 363 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 364 RF_ACTIVE); 365 if (sc->bfe_res == NULL) { 366 printf ("bfe%d: couldn't map memory\n", unit); 367 error = ENXIO; 368 goto fail; 369 } 370 371 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 372 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 373 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 374 375 /* Allocate interrupt */ 376 rid = 0; 377 378 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 379 RF_SHAREABLE | RF_ACTIVE); 380 if (sc->bfe_irq == NULL) { 381 printf("bfe%d: couldn't map interrupt\n", unit); 382 error = ENXIO; 383 goto fail; 384 } 385 386 if (bfe_dma_alloc(dev)) { 387 printf("bfe%d: failed to allocate DMA resources\n", 388 sc->bfe_unit); 389 bfe_release_resources(sc); 390 error = ENXIO; 391 goto fail; 392 } 393 394 /* Set up ifnet structure */ 395 ifp = &sc->arpcom.ac_if; 396 ifp->if_softc = sc; 397 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 398 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 399 ifp->if_ioctl = bfe_ioctl; 400 ifp->if_start = bfe_start; 401 ifp->if_watchdog = bfe_watchdog; 402 ifp->if_init = bfe_init; 403 ifp->if_mtu = ETHERMTU; 404 ifp->if_baudrate = 100000000; 405 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 406 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 407 IFQ_SET_READY(&ifp->if_snd); 408 409 bfe_get_config(sc); 410 411 /* Reset the chip and turn on the PHY */ 412 bfe_chip_reset(sc); 413 414 if (mii_phy_probe(dev, &sc->bfe_miibus, 415 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 416 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 417 error = ENXIO; 418 goto fail; 419 } 420 421 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 422 callout_handle_init(&sc->bfe_stat_ch); 423 424 /* 425 * Tell the upper layer(s) we support long frames. 426 */ 427 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 428 ifp->if_capabilities |= IFCAP_VLAN_MTU; 429 ifp->if_capenable |= IFCAP_VLAN_MTU; 430 431 /* 432 * Hook interrupt last to avoid having to lock softc 433 */ 434 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET, 435 bfe_intr, sc, &sc->bfe_intrhand); 436 437 if (error) { 438 bfe_release_resources(sc); 439 printf("bfe%d: couldn't set up irq\n", unit); 440 goto fail; 441 } 442 fail: 443 if(error) 444 bfe_release_resources(sc); 445 return (error); 446 } 447 448 static int 449 bfe_detach(device_t dev) 450 { 451 struct bfe_softc *sc; 452 struct ifnet *ifp; 453 454 sc = device_get_softc(dev); 455 456 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 457 BFE_LOCK(scp); 458 459 ifp = &sc->arpcom.ac_if; 460 461 if (device_is_attached(dev)) { 462 bfe_stop(sc); 463 ether_ifdetach(ifp); 464 } 465 466 bfe_chip_reset(sc); 467 468 bus_generic_detach(dev); 469 if(sc->bfe_miibus != NULL) 470 device_delete_child(dev, sc->bfe_miibus); 471 472 bfe_release_resources(sc); 473 BFE_UNLOCK(sc); 474 mtx_destroy(&sc->bfe_mtx); 475 476 return (0); 477 } 478 479 /* 480 * Stop all chip I/O so that the kernel's probe routines don't 481 * get confused by errant DMAs when rebooting. 482 */ 483 static void 484 bfe_shutdown(device_t dev) 485 { 486 struct bfe_softc *sc; 487 488 sc = device_get_softc(dev); 489 BFE_LOCK(sc); 490 bfe_stop(sc); 491 492 BFE_UNLOCK(sc); 493 return; 494 } 495 496 static int 497 bfe_miibus_readreg(device_t dev, int phy, int reg) 498 { 499 struct bfe_softc *sc; 500 u_int32_t ret; 501 502 sc = device_get_softc(dev); 503 if(phy != sc->bfe_phyaddr) 504 return (0); 505 bfe_readphy(sc, reg, &ret); 506 507 return (ret); 508 } 509 510 static int 511 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 512 { 513 struct bfe_softc *sc; 514 515 sc = device_get_softc(dev); 516 if(phy != sc->bfe_phyaddr) 517 return (0); 518 bfe_writephy(sc, reg, val); 519 520 return (0); 521 } 522 523 static void 524 bfe_miibus_statchg(device_t dev) 525 { 526 return; 527 } 528 529 static void 530 bfe_tx_ring_free(struct bfe_softc *sc) 531 { 532 int i; 533 534 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 535 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 536 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 537 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 538 bus_dmamap_unload(sc->bfe_tag, 539 sc->bfe_tx_ring[i].bfe_map); 540 } 541 } 542 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 543 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 544 } 545 546 static void 547 bfe_rx_ring_free(struct bfe_softc *sc) 548 { 549 int i; 550 551 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 552 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 553 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 554 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 555 bus_dmamap_unload(sc->bfe_tag, 556 sc->bfe_rx_ring[i].bfe_map); 557 } 558 } 559 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 560 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 561 } 562 563 static int 564 bfe_list_rx_init(struct bfe_softc *sc) 565 { 566 int i; 567 568 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 569 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 570 return (ENOBUFS); 571 } 572 573 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 574 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 575 576 sc->bfe_rx_cons = 0; 577 578 return (0); 579 } 580 581 static int 582 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 583 { 584 struct bfe_rxheader *rx_header; 585 struct bfe_desc *d; 586 struct bfe_data *r; 587 u_int32_t ctrl; 588 589 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 590 return (EINVAL); 591 592 if(m == NULL) { 593 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 594 if(m == NULL) 595 return (ENOBUFS); 596 m->m_len = m->m_pkthdr.len = MCLBYTES; 597 } 598 else 599 m->m_data = m->m_ext.ext_buf; 600 601 rx_header = mtod(m, struct bfe_rxheader *); 602 rx_header->len = 0; 603 rx_header->flags = 0; 604 605 /* Map the mbuf into DMA */ 606 sc->bfe_rx_cnt = c; 607 d = &sc->bfe_rx_list[c]; 608 r = &sc->bfe_rx_ring[c]; 609 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 610 MCLBYTES, bfe_dma_map_desc, d, 0); 611 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREREAD); 612 613 ctrl = ETHER_MAX_LEN + 32; 614 615 if(c == BFE_RX_LIST_CNT - 1) 616 ctrl |= BFE_DESC_EOT; 617 618 d->bfe_ctrl = ctrl; 619 r->bfe_mbuf = m; 620 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 621 return (0); 622 } 623 624 static void 625 bfe_get_config(struct bfe_softc *sc) 626 { 627 u_int8_t eeprom[128]; 628 629 bfe_read_eeprom(sc, eeprom); 630 631 sc->arpcom.ac_enaddr[0] = eeprom[79]; 632 sc->arpcom.ac_enaddr[1] = eeprom[78]; 633 sc->arpcom.ac_enaddr[2] = eeprom[81]; 634 sc->arpcom.ac_enaddr[3] = eeprom[80]; 635 sc->arpcom.ac_enaddr[4] = eeprom[83]; 636 sc->arpcom.ac_enaddr[5] = eeprom[82]; 637 638 sc->bfe_phyaddr = eeprom[90] & 0x1f; 639 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 640 641 sc->bfe_core_unit = 0; 642 sc->bfe_dma_offset = BFE_PCI_DMA; 643 } 644 645 static void 646 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 647 { 648 u_int32_t bar_orig, pci_rev, val; 649 650 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 651 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 652 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 653 654 val = CSR_READ_4(sc, BFE_SBINTVEC); 655 val |= cores; 656 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 657 658 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 659 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 660 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 661 662 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 663 } 664 665 static void 666 bfe_clear_stats(struct bfe_softc *sc) 667 { 668 u_long reg; 669 670 BFE_LOCK(sc); 671 672 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 673 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 674 CSR_READ_4(sc, reg); 675 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 676 CSR_READ_4(sc, reg); 677 678 BFE_UNLOCK(sc); 679 } 680 681 static int 682 bfe_resetphy(struct bfe_softc *sc) 683 { 684 u_int32_t val; 685 686 BFE_LOCK(sc); 687 bfe_writephy(sc, 0, BMCR_RESET); 688 DELAY(100); 689 bfe_readphy(sc, 0, &val); 690 if (val & BMCR_RESET) { 691 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 692 BFE_UNLOCK(sc); 693 return (ENXIO); 694 } 695 BFE_UNLOCK(sc); 696 return (0); 697 } 698 699 static void 700 bfe_chip_halt(struct bfe_softc *sc) 701 { 702 BFE_LOCK(sc); 703 /* disable interrupts - not that it actually does..*/ 704 CSR_WRITE_4(sc, BFE_IMASK, 0); 705 CSR_READ_4(sc, BFE_IMASK); 706 707 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 708 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 709 710 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 711 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 712 DELAY(10); 713 714 BFE_UNLOCK(sc); 715 } 716 717 static void 718 bfe_chip_reset(struct bfe_softc *sc) 719 { 720 u_int32_t val; 721 722 BFE_LOCK(sc); 723 724 /* Set the interrupt vector for the enet core */ 725 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 726 727 /* is core up? */ 728 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 729 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 730 if (val == BFE_CLOCK) { 731 /* It is, so shut it down */ 732 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 733 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 734 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 735 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 736 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 737 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 738 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 739 100, 0); 740 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 741 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 742 } 743 744 bfe_core_reset(sc); 745 bfe_clear_stats(sc); 746 747 /* 748 * We want the phy registers to be accessible even when 749 * the driver is "downed" so initialize MDC preamble, frequency, 750 * and whether internal or external phy here. 751 */ 752 753 /* 4402 has 62.5Mhz SB clock and internal phy */ 754 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 755 756 /* Internal or external PHY? */ 757 val = CSR_READ_4(sc, BFE_DEVCTRL); 758 if(!(val & BFE_IPP)) 759 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 760 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 761 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 762 DELAY(100); 763 } 764 765 /* Enable CRC32 generation and set proper LED modes */ 766 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 767 768 /* Reset or clear powerdown control bit */ 769 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 770 771 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 772 BFE_LAZY_FC_MASK)); 773 774 /* 775 * We don't want lazy interrupts, so just send them at 776 * the end of a frame, please 777 */ 778 BFE_OR(sc, BFE_RCV_LAZY, 0); 779 780 /* Set max lengths, accounting for VLAN tags */ 781 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 782 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 783 784 /* Set watermark XXX - magic */ 785 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 786 787 /* 788 * Initialise DMA channels 789 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 790 */ 791 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 792 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 793 794 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 795 BFE_RX_CTRL_ENABLE); 796 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 797 798 bfe_resetphy(sc); 799 bfe_setupphy(sc); 800 801 BFE_UNLOCK(sc); 802 } 803 804 static void 805 bfe_core_disable(struct bfe_softc *sc) 806 { 807 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 808 return; 809 810 /* 811 * Set reject, wait for it set, then wait for the core to stop 812 * being busy, then set reset and reject and enable the clocks. 813 */ 814 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 815 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 816 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 817 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 818 BFE_RESET)); 819 CSR_READ_4(sc, BFE_SBTMSLOW); 820 DELAY(10); 821 /* Leave reset and reject set */ 822 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 823 DELAY(10); 824 } 825 826 static void 827 bfe_core_reset(struct bfe_softc *sc) 828 { 829 u_int32_t val; 830 831 /* Disable the core */ 832 bfe_core_disable(sc); 833 834 /* and bring it back up */ 835 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 836 CSR_READ_4(sc, BFE_SBTMSLOW); 837 DELAY(10); 838 839 /* Chip bug, clear SERR, IB and TO if they are set. */ 840 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 841 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 842 val = CSR_READ_4(sc, BFE_SBIMSTATE); 843 if (val & (BFE_IBE | BFE_TO)) 844 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 845 846 /* Clear reset and allow it to move through the core */ 847 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 848 CSR_READ_4(sc, BFE_SBTMSLOW); 849 DELAY(10); 850 851 /* Leave the clock set */ 852 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 853 CSR_READ_4(sc, BFE_SBTMSLOW); 854 DELAY(10); 855 } 856 857 static void 858 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 859 { 860 u_int32_t val; 861 862 val = ((u_int32_t) data[2]) << 24; 863 val |= ((u_int32_t) data[3]) << 16; 864 val |= ((u_int32_t) data[4]) << 8; 865 val |= ((u_int32_t) data[5]); 866 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 867 val = (BFE_CAM_HI_VALID | 868 (((u_int32_t) data[0]) << 8) | 869 (((u_int32_t) data[1]))); 870 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 871 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 872 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 873 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 874 } 875 876 static void 877 bfe_set_rx_mode(struct bfe_softc *sc) 878 { 879 struct ifnet *ifp = &sc->arpcom.ac_if; 880 struct ifmultiaddr *ifma; 881 u_int32_t val; 882 int i = 0; 883 884 val = CSR_READ_4(sc, BFE_RXCONF); 885 886 if (ifp->if_flags & IFF_PROMISC) 887 val |= BFE_RXCONF_PROMISC; 888 else 889 val &= ~BFE_RXCONF_PROMISC; 890 891 if (ifp->if_flags & IFF_BROADCAST) 892 val &= ~BFE_RXCONF_DBCAST; 893 else 894 val |= BFE_RXCONF_DBCAST; 895 896 897 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 898 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 899 900 if (ifp->if_flags & IFF_ALLMULTI) 901 val |= BFE_RXCONF_ALLMULTI; 902 else { 903 val &= ~BFE_RXCONF_ALLMULTI; 904 IF_ADDR_LOCK(ifp); 905 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 906 if (ifma->ifma_addr->sa_family != AF_LINK) 907 continue; 908 bfe_cam_write(sc, 909 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 910 } 911 IF_ADDR_UNLOCK(ifp); 912 } 913 914 CSR_WRITE_4(sc, BFE_RXCONF, val); 915 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 916 } 917 918 static void 919 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 920 { 921 u_int32_t *ptr; 922 923 ptr = arg; 924 *ptr = segs->ds_addr; 925 } 926 927 static void 928 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 929 { 930 struct bfe_desc *d; 931 932 d = arg; 933 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 934 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 935 } 936 937 static void 938 bfe_release_resources(struct bfe_softc *sc) 939 { 940 device_t dev; 941 int i; 942 943 dev = sc->bfe_dev; 944 945 if (sc->bfe_vpd_prodname != NULL) 946 free(sc->bfe_vpd_prodname, M_DEVBUF); 947 948 if (sc->bfe_vpd_readonly != NULL) 949 free(sc->bfe_vpd_readonly, M_DEVBUF); 950 951 if (sc->bfe_intrhand != NULL) 952 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 953 954 if (sc->bfe_irq != NULL) 955 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 956 957 if (sc->bfe_res != NULL) 958 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 959 960 if(sc->bfe_tx_tag != NULL) { 961 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 962 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 963 sc->bfe_tx_map); 964 bus_dma_tag_destroy(sc->bfe_tx_tag); 965 sc->bfe_tx_tag = NULL; 966 } 967 968 if(sc->bfe_rx_tag != NULL) { 969 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 970 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 971 sc->bfe_rx_map); 972 bus_dma_tag_destroy(sc->bfe_rx_tag); 973 sc->bfe_rx_tag = NULL; 974 } 975 976 if(sc->bfe_tag != NULL) { 977 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 978 bus_dmamap_destroy(sc->bfe_tag, 979 sc->bfe_tx_ring[i].bfe_map); 980 } 981 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 982 bus_dmamap_destroy(sc->bfe_tag, 983 sc->bfe_rx_ring[i].bfe_map); 984 } 985 bus_dma_tag_destroy(sc->bfe_tag); 986 sc->bfe_tag = NULL; 987 } 988 989 if(sc->bfe_parent_tag != NULL) 990 bus_dma_tag_destroy(sc->bfe_parent_tag); 991 992 return; 993 } 994 995 static void 996 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 997 { 998 long i; 999 u_int16_t *ptr = (u_int16_t *)data; 1000 1001 for(i = 0; i < 128; i += 2) 1002 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 1003 } 1004 1005 static int 1006 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1007 u_long timeout, const int clear) 1008 { 1009 u_long i; 1010 1011 for (i = 0; i < timeout; i++) { 1012 u_int32_t val = CSR_READ_4(sc, reg); 1013 1014 if (clear && !(val & bit)) 1015 break; 1016 if (!clear && (val & bit)) 1017 break; 1018 DELAY(10); 1019 } 1020 if (i == timeout) { 1021 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1022 "%x to %s.\n", sc->bfe_unit, bit, reg, 1023 (clear ? "clear" : "set")); 1024 return (-1); 1025 } 1026 return (0); 1027 } 1028 1029 static int 1030 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1031 { 1032 int err; 1033 1034 BFE_LOCK(sc); 1035 /* Clear MII ISR */ 1036 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1037 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1038 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1039 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1040 (reg << BFE_MDIO_RA_SHIFT) | 1041 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1042 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1043 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1044 1045 BFE_UNLOCK(sc); 1046 return (err); 1047 } 1048 1049 static int 1050 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1051 { 1052 int status; 1053 1054 BFE_LOCK(sc); 1055 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1056 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1057 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1058 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1059 (reg << BFE_MDIO_RA_SHIFT) | 1060 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1061 (val & BFE_MDIO_DATA_DATA))); 1062 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1063 BFE_UNLOCK(sc); 1064 1065 return (status); 1066 } 1067 1068 /* 1069 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1070 * twice 1071 */ 1072 static int 1073 bfe_setupphy(struct bfe_softc *sc) 1074 { 1075 u_int32_t val; 1076 BFE_LOCK(sc); 1077 1078 /* Enable activity LED */ 1079 bfe_readphy(sc, 26, &val); 1080 bfe_writephy(sc, 26, val & 0x7fff); 1081 bfe_readphy(sc, 26, &val); 1082 1083 /* Enable traffic meter LED mode */ 1084 bfe_readphy(sc, 27, &val); 1085 bfe_writephy(sc, 27, val | (1 << 6)); 1086 1087 BFE_UNLOCK(sc); 1088 return (0); 1089 } 1090 1091 static void 1092 bfe_stats_update(struct bfe_softc *sc) 1093 { 1094 u_long reg; 1095 u_int32_t *val; 1096 1097 val = &sc->bfe_hwstats.tx_good_octets; 1098 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1099 *val++ += CSR_READ_4(sc, reg); 1100 } 1101 val = &sc->bfe_hwstats.rx_good_octets; 1102 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1103 *val++ += CSR_READ_4(sc, reg); 1104 } 1105 } 1106 1107 static void 1108 bfe_txeof(struct bfe_softc *sc) 1109 { 1110 struct ifnet *ifp; 1111 int i, chipidx; 1112 1113 BFE_LOCK(sc); 1114 1115 ifp = &sc->arpcom.ac_if; 1116 1117 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1118 chipidx /= sizeof(struct bfe_desc); 1119 1120 i = sc->bfe_tx_cons; 1121 /* Go through the mbufs and free those that have been transmitted */ 1122 while(i != chipidx) { 1123 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1124 if(r->bfe_mbuf != NULL) { 1125 ifp->if_opackets++; 1126 m_freem(r->bfe_mbuf); 1127 r->bfe_mbuf = NULL; 1128 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1129 } 1130 sc->bfe_tx_cnt--; 1131 BFE_INC(i, BFE_TX_LIST_CNT); 1132 } 1133 1134 if(i != sc->bfe_tx_cons) { 1135 /* we freed up some mbufs */ 1136 sc->bfe_tx_cons = i; 1137 ifp->if_flags &= ~IFF_OACTIVE; 1138 } 1139 if(sc->bfe_tx_cnt == 0) 1140 ifp->if_timer = 0; 1141 else 1142 ifp->if_timer = 5; 1143 1144 BFE_UNLOCK(sc); 1145 } 1146 1147 /* Pass a received packet up the stack */ 1148 static void 1149 bfe_rxeof(struct bfe_softc *sc) 1150 { 1151 struct mbuf *m; 1152 struct ifnet *ifp; 1153 struct bfe_rxheader *rxheader; 1154 struct bfe_data *r; 1155 int cons; 1156 u_int32_t status, current, len, flags; 1157 1158 BFE_LOCK(sc); 1159 cons = sc->bfe_rx_cons; 1160 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1161 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1162 1163 ifp = &sc->arpcom.ac_if; 1164 1165 while(current != cons) { 1166 r = &sc->bfe_rx_ring[cons]; 1167 m = r->bfe_mbuf; 1168 rxheader = mtod(m, struct bfe_rxheader*); 1169 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1170 len = rxheader->len; 1171 r->bfe_mbuf = NULL; 1172 1173 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1174 flags = rxheader->flags; 1175 1176 len -= ETHER_CRC_LEN; 1177 1178 /* flag an error and try again */ 1179 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1180 ifp->if_ierrors++; 1181 if (flags & BFE_RX_FLAG_SERR) 1182 ifp->if_collisions++; 1183 bfe_list_newbuf(sc, cons, m); 1184 BFE_INC(cons, BFE_RX_LIST_CNT); 1185 continue; 1186 } 1187 1188 /* Go past the rx header */ 1189 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1190 m_adj(m, BFE_RX_OFFSET); 1191 m->m_len = m->m_pkthdr.len = len; 1192 } else { 1193 bfe_list_newbuf(sc, cons, m); 1194 ifp->if_ierrors++; 1195 BFE_INC(cons, BFE_RX_LIST_CNT); 1196 continue; 1197 } 1198 1199 ifp->if_ipackets++; 1200 m->m_pkthdr.rcvif = ifp; 1201 BFE_UNLOCK(sc); 1202 (*ifp->if_input)(ifp, m); 1203 BFE_LOCK(sc); 1204 1205 BFE_INC(cons, BFE_RX_LIST_CNT); 1206 } 1207 sc->bfe_rx_cons = cons; 1208 BFE_UNLOCK(sc); 1209 } 1210 1211 static void 1212 bfe_intr(void *xsc) 1213 { 1214 struct bfe_softc *sc = xsc; 1215 struct ifnet *ifp; 1216 u_int32_t istat, imask, flag; 1217 1218 ifp = &sc->arpcom.ac_if; 1219 1220 BFE_LOCK(sc); 1221 1222 istat = CSR_READ_4(sc, BFE_ISTAT); 1223 imask = CSR_READ_4(sc, BFE_IMASK); 1224 1225 /* 1226 * Defer unsolicited interrupts - This is necessary because setting the 1227 * chips interrupt mask register to 0 doesn't actually stop the 1228 * interrupts 1229 */ 1230 istat &= imask; 1231 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1232 CSR_READ_4(sc, BFE_ISTAT); 1233 1234 /* not expecting this interrupt, disregard it */ 1235 if(istat == 0) { 1236 BFE_UNLOCK(sc); 1237 return; 1238 } 1239 1240 if(istat & BFE_ISTAT_ERRORS) { 1241 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1242 if(flag & BFE_STAT_EMASK) 1243 ifp->if_oerrors++; 1244 1245 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1246 if(flag & BFE_RX_FLAG_ERRORS) 1247 ifp->if_ierrors++; 1248 1249 ifp->if_flags &= ~IFF_RUNNING; 1250 bfe_init(sc); 1251 } 1252 1253 /* A packet was received */ 1254 if(istat & BFE_ISTAT_RX) 1255 bfe_rxeof(sc); 1256 1257 /* A packet was sent */ 1258 if(istat & BFE_ISTAT_TX) 1259 bfe_txeof(sc); 1260 1261 /* We have packets pending, fire them out */ 1262 if (ifp->if_flags & IFF_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1263 bfe_start(ifp); 1264 1265 BFE_UNLOCK(sc); 1266 } 1267 1268 static int 1269 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1270 { 1271 struct bfe_desc *d = NULL; 1272 struct bfe_data *r = NULL; 1273 struct mbuf *m; 1274 u_int32_t frag, cur, cnt = 0; 1275 int chainlen = 0; 1276 1277 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1278 return (ENOBUFS); 1279 1280 /* 1281 * Count the number of frags in this chain to see if 1282 * we need to m_defrag. Since the descriptor list is shared 1283 * by all packets, we'll m_defrag long chains so that they 1284 * do not use up the entire list, even if they would fit. 1285 */ 1286 for(m = m_head; m != NULL; m = m->m_next) 1287 chainlen++; 1288 1289 1290 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1291 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1292 m = m_defrag(m_head, M_DONTWAIT); 1293 if (m == NULL) 1294 return (ENOBUFS); 1295 m_head = m; 1296 } 1297 1298 /* 1299 * Start packing the mbufs in this chain into 1300 * the fragment pointers. Stop when we run out 1301 * of fragments or hit the end of the mbuf chain. 1302 */ 1303 m = m_head; 1304 cur = frag = *txidx; 1305 cnt = 0; 1306 1307 for(m = m_head; m != NULL; m = m->m_next) { 1308 if(m->m_len != 0) { 1309 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1310 return (ENOBUFS); 1311 1312 d = &sc->bfe_tx_list[cur]; 1313 r = &sc->bfe_tx_ring[cur]; 1314 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1315 /* always intterupt on completion */ 1316 d->bfe_ctrl |= BFE_DESC_IOC; 1317 if(cnt == 0) 1318 /* Set start of frame */ 1319 d->bfe_ctrl |= BFE_DESC_SOF; 1320 if(cur == BFE_TX_LIST_CNT - 1) 1321 /* 1322 * Tell the chip to wrap to the start of 1323 * the descriptor list 1324 */ 1325 d->bfe_ctrl |= BFE_DESC_EOT; 1326 1327 bus_dmamap_load(sc->bfe_tag, 1328 r->bfe_map, mtod(m, void*), m->m_len, 1329 bfe_dma_map_desc, d, 0); 1330 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1331 BUS_DMASYNC_PREREAD); 1332 1333 frag = cur; 1334 BFE_INC(cur, BFE_TX_LIST_CNT); 1335 cnt++; 1336 } 1337 } 1338 1339 if (m != NULL) 1340 return (ENOBUFS); 1341 1342 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1343 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1344 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1345 1346 *txidx = cur; 1347 sc->bfe_tx_cnt += cnt; 1348 return (0); 1349 } 1350 1351 /* 1352 * Set up to transmit a packet 1353 */ 1354 static void 1355 bfe_start(struct ifnet *ifp) 1356 { 1357 struct bfe_softc *sc; 1358 struct mbuf *m_head = NULL; 1359 int idx, queued = 0; 1360 1361 sc = ifp->if_softc; 1362 idx = sc->bfe_tx_prod; 1363 1364 BFE_LOCK(sc); 1365 1366 /* 1367 * Not much point trying to send if the link is down 1368 * or we have nothing to send. 1369 */ 1370 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) { 1371 BFE_UNLOCK(sc); 1372 return; 1373 } 1374 1375 if (ifp->if_flags & IFF_OACTIVE) { 1376 BFE_UNLOCK(sc); 1377 return; 1378 } 1379 1380 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1381 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1382 if(m_head == NULL) 1383 break; 1384 1385 /* 1386 * Pack the data into the tx ring. If we dont have 1387 * enough room, let the chip drain the ring. 1388 */ 1389 if(bfe_encap(sc, m_head, &idx)) { 1390 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1391 ifp->if_flags |= IFF_OACTIVE; 1392 break; 1393 } 1394 1395 queued++; 1396 1397 /* 1398 * If there's a BPF listener, bounce a copy of this frame 1399 * to him. 1400 */ 1401 BPF_MTAP(ifp, m_head); 1402 } 1403 1404 if (queued) { 1405 sc->bfe_tx_prod = idx; 1406 /* Transmit - twice due to apparent hardware bug */ 1407 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1408 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1409 1410 /* 1411 * Set a timeout in case the chip goes out to lunch. 1412 */ 1413 ifp->if_timer = 5; 1414 } 1415 1416 BFE_UNLOCK(sc); 1417 } 1418 1419 static void 1420 bfe_init(void *xsc) 1421 { 1422 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1423 struct ifnet *ifp = &sc->arpcom.ac_if; 1424 1425 BFE_LOCK(sc); 1426 1427 if (ifp->if_flags & IFF_RUNNING) { 1428 BFE_UNLOCK(sc); 1429 return; 1430 } 1431 1432 bfe_stop(sc); 1433 bfe_chip_reset(sc); 1434 1435 if (bfe_list_rx_init(sc) == ENOBUFS) { 1436 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1437 sc->bfe_unit); 1438 bfe_stop(sc); 1439 return; 1440 } 1441 1442 bfe_set_rx_mode(sc); 1443 1444 /* Enable the chip and core */ 1445 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1446 /* Enable interrupts */ 1447 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1448 1449 bfe_ifmedia_upd(ifp); 1450 ifp->if_flags |= IFF_RUNNING; 1451 ifp->if_flags &= ~IFF_OACTIVE; 1452 1453 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1454 BFE_UNLOCK(sc); 1455 } 1456 1457 /* 1458 * Set media options. 1459 */ 1460 static int 1461 bfe_ifmedia_upd(struct ifnet *ifp) 1462 { 1463 struct bfe_softc *sc; 1464 struct mii_data *mii; 1465 1466 sc = ifp->if_softc; 1467 1468 BFE_LOCK(sc); 1469 1470 mii = device_get_softc(sc->bfe_miibus); 1471 sc->bfe_link = 0; 1472 if (mii->mii_instance) { 1473 struct mii_softc *miisc; 1474 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1475 miisc = LIST_NEXT(miisc, mii_list)) 1476 mii_phy_reset(miisc); 1477 } 1478 mii_mediachg(mii); 1479 1480 BFE_UNLOCK(sc); 1481 return (0); 1482 } 1483 1484 /* 1485 * Report current media status. 1486 */ 1487 static void 1488 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1489 { 1490 struct bfe_softc *sc = ifp->if_softc; 1491 struct mii_data *mii; 1492 1493 BFE_LOCK(sc); 1494 1495 mii = device_get_softc(sc->bfe_miibus); 1496 mii_pollstat(mii); 1497 ifmr->ifm_active = mii->mii_media_active; 1498 ifmr->ifm_status = mii->mii_media_status; 1499 1500 BFE_UNLOCK(sc); 1501 } 1502 1503 static int 1504 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1505 { 1506 struct bfe_softc *sc = ifp->if_softc; 1507 struct ifreq *ifr = (struct ifreq *) data; 1508 struct mii_data *mii; 1509 int error = 0; 1510 1511 BFE_LOCK(sc); 1512 1513 switch(command) { 1514 case SIOCSIFFLAGS: 1515 if(ifp->if_flags & IFF_UP) 1516 if(ifp->if_flags & IFF_RUNNING) 1517 bfe_set_rx_mode(sc); 1518 else 1519 bfe_init(sc); 1520 else if(ifp->if_flags & IFF_RUNNING) 1521 bfe_stop(sc); 1522 break; 1523 case SIOCADDMULTI: 1524 case SIOCDELMULTI: 1525 if(ifp->if_flags & IFF_RUNNING) 1526 bfe_set_rx_mode(sc); 1527 break; 1528 case SIOCGIFMEDIA: 1529 case SIOCSIFMEDIA: 1530 mii = device_get_softc(sc->bfe_miibus); 1531 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1532 command); 1533 break; 1534 default: 1535 error = ether_ioctl(ifp, command, data); 1536 break; 1537 } 1538 1539 BFE_UNLOCK(sc); 1540 return (error); 1541 } 1542 1543 static void 1544 bfe_watchdog(struct ifnet *ifp) 1545 { 1546 struct bfe_softc *sc; 1547 1548 sc = ifp->if_softc; 1549 1550 BFE_LOCK(sc); 1551 1552 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1553 1554 ifp->if_flags &= ~IFF_RUNNING; 1555 bfe_init(sc); 1556 1557 ifp->if_oerrors++; 1558 1559 BFE_UNLOCK(sc); 1560 } 1561 1562 static void 1563 bfe_tick(void *xsc) 1564 { 1565 struct bfe_softc *sc = xsc; 1566 struct mii_data *mii; 1567 1568 if (sc == NULL) 1569 return; 1570 1571 BFE_LOCK(sc); 1572 1573 mii = device_get_softc(sc->bfe_miibus); 1574 1575 bfe_stats_update(sc); 1576 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1577 1578 if(sc->bfe_link) { 1579 BFE_UNLOCK(sc); 1580 return; 1581 } 1582 1583 mii_tick(mii); 1584 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1585 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1586 sc->bfe_link++; 1587 1588 BFE_UNLOCK(sc); 1589 } 1590 1591 /* 1592 * Stop the adapter and free any mbufs allocated to the 1593 * RX and TX lists. 1594 */ 1595 static void 1596 bfe_stop(struct bfe_softc *sc) 1597 { 1598 struct ifnet *ifp; 1599 1600 BFE_LOCK(sc); 1601 1602 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1603 1604 ifp = &sc->arpcom.ac_if; 1605 1606 bfe_chip_halt(sc); 1607 bfe_tx_ring_free(sc); 1608 bfe_rx_ring_free(sc); 1609 1610 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1611 1612 BFE_UNLOCK(sc); 1613 }
Cache object: b8f3262cc02ddc0726cc12e6cb8d009c
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