Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/bfe/if_bfe.c
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1 /*- 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD: releng/6.0/sys/dev/bfe/if_bfe.c 151141 2005-10-09 04:15:12Z delphij $"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/malloc.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/socket.h> 39 #include <sys/queue.h> 40 41 #include <net/if.h> 42 #include <net/if_arp.h> 43 #include <net/ethernet.h> 44 #include <net/if_dl.h> 45 #include <net/if_media.h> 46 47 #include <net/bpf.h> 48 49 #include <net/if_types.h> 50 #include <net/if_vlan_var.h> 51 52 #include <netinet/in_systm.h> 53 #include <netinet/in.h> 54 #include <netinet/ip.h> 55 56 #include <machine/clock.h> /* for DELAY */ 57 #include <machine/bus.h> 58 #include <machine/resource.h> 59 #include <sys/bus.h> 60 #include <sys/rman.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 #include "miidevs.h" 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 #include <dev/bfe/if_bfereg.h> 70 71 MODULE_DEPEND(bfe, pci, 1, 1, 1); 72 MODULE_DEPEND(bfe, ether, 1, 1, 1); 73 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 74 75 /* "controller miibus0" required. See GENERIC if you get errors here. */ 76 #include "miibus_if.h" 77 78 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 79 80 static struct bfe_type bfe_devs[] = { 81 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 82 "Broadcom BCM4401 Fast Ethernet" }, 83 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 84 "Broadcom BCM4401-B0 Fast Ethernet" }, 85 { 0, 0, NULL } 86 }; 87 88 static int bfe_probe (device_t); 89 static int bfe_attach (device_t); 90 static int bfe_detach (device_t); 91 static void bfe_release_resources (struct bfe_softc *); 92 static void bfe_intr (void *); 93 static void bfe_start (struct ifnet *); 94 static void bfe_start_locked (struct ifnet *); 95 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 96 static void bfe_init (void *); 97 static void bfe_init_locked (void *); 98 static void bfe_stop (struct bfe_softc *); 99 static void bfe_watchdog (struct ifnet *); 100 static void bfe_shutdown (device_t); 101 static void bfe_tick (void *); 102 static void bfe_txeof (struct bfe_softc *); 103 static void bfe_rxeof (struct bfe_softc *); 104 static void bfe_set_rx_mode (struct bfe_softc *); 105 static int bfe_list_rx_init (struct bfe_softc *); 106 static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 107 static void bfe_rx_ring_free (struct bfe_softc *); 108 109 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 110 static int bfe_ifmedia_upd (struct ifnet *); 111 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 112 static int bfe_miibus_readreg (device_t, int, int); 113 static int bfe_miibus_writereg (device_t, int, int, int); 114 static void bfe_miibus_statchg (device_t); 115 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 116 u_long, const int); 117 static void bfe_get_config (struct bfe_softc *sc); 118 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 119 static void bfe_stats_update (struct bfe_softc *); 120 static void bfe_clear_stats (struct bfe_softc *); 121 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 122 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 123 static int bfe_resetphy (struct bfe_softc *); 124 static int bfe_setupphy (struct bfe_softc *); 125 static void bfe_chip_reset (struct bfe_softc *); 126 static void bfe_chip_halt (struct bfe_softc *); 127 static void bfe_core_reset (struct bfe_softc *); 128 static void bfe_core_disable (struct bfe_softc *); 129 static int bfe_dma_alloc (device_t); 130 static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 131 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 132 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 133 134 static device_method_t bfe_methods[] = { 135 /* Device interface */ 136 DEVMETHOD(device_probe, bfe_probe), 137 DEVMETHOD(device_attach, bfe_attach), 138 DEVMETHOD(device_detach, bfe_detach), 139 DEVMETHOD(device_shutdown, bfe_shutdown), 140 141 /* bus interface */ 142 DEVMETHOD(bus_print_child, bus_generic_print_child), 143 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 144 145 /* MII interface */ 146 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 147 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 148 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 149 150 { 0, 0 } 151 }; 152 153 static driver_t bfe_driver = { 154 "bfe", 155 bfe_methods, 156 sizeof(struct bfe_softc) 157 }; 158 159 static devclass_t bfe_devclass; 160 161 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 162 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 163 164 /* 165 * Probe for a Broadcom 4401 chip. 166 */ 167 static int 168 bfe_probe(device_t dev) 169 { 170 struct bfe_type *t; 171 struct bfe_softc *sc; 172 173 t = bfe_devs; 174 175 sc = device_get_softc(dev); 176 bzero(sc, sizeof(struct bfe_softc)); 177 sc->bfe_unit = device_get_unit(dev); 178 sc->bfe_dev = dev; 179 180 while(t->bfe_name != NULL) { 181 if ((pci_get_vendor(dev) == t->bfe_vid) && 182 (pci_get_device(dev) == t->bfe_did)) { 183 device_set_desc_copy(dev, t->bfe_name); 184 return (BUS_PROBE_DEFAULT); 185 } 186 t++; 187 } 188 189 return (ENXIO); 190 } 191 192 static int 193 bfe_dma_alloc(device_t dev) 194 { 195 struct bfe_softc *sc; 196 int error, i; 197 198 sc = device_get_softc(dev); 199 200 /* parent tag */ 201 error = bus_dma_tag_create(NULL, /* parent */ 202 PAGE_SIZE, 0, /* alignment, boundary */ 203 BUS_SPACE_MAXADDR, /* lowaddr */ 204 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 205 NULL, NULL, /* filter, filterarg */ 206 MAXBSIZE, /* maxsize */ 207 BUS_SPACE_UNRESTRICTED, /* num of segments */ 208 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 209 BUS_DMA_ALLOCNOW, /* flags */ 210 NULL, NULL, /* lockfunc, lockarg */ 211 &sc->bfe_parent_tag); 212 213 /* tag for TX ring */ 214 error = bus_dma_tag_create(sc->bfe_parent_tag, 215 BFE_TX_LIST_SIZE, BFE_TX_LIST_SIZE, 216 BUS_SPACE_MAXADDR, 217 BUS_SPACE_MAXADDR, 218 NULL, NULL, 219 BFE_TX_LIST_SIZE, 220 1, 221 BUS_SPACE_MAXSIZE_32BIT, 222 0, 223 NULL, NULL, 224 &sc->bfe_tx_tag); 225 226 if (error) { 227 device_printf(dev, "could not allocate dma tag\n"); 228 return (ENOMEM); 229 } 230 231 /* tag for RX ring */ 232 error = bus_dma_tag_create(sc->bfe_parent_tag, 233 BFE_RX_LIST_SIZE, BFE_RX_LIST_SIZE, 234 BUS_SPACE_MAXADDR, 235 BUS_SPACE_MAXADDR, 236 NULL, NULL, 237 BFE_RX_LIST_SIZE, 238 1, 239 BUS_SPACE_MAXSIZE_32BIT, 240 0, 241 NULL, NULL, 242 &sc->bfe_rx_tag); 243 244 if (error) { 245 device_printf(dev, "could not allocate dma tag\n"); 246 return (ENOMEM); 247 } 248 249 /* tag for mbufs */ 250 error = bus_dma_tag_create(sc->bfe_parent_tag, 251 ETHER_ALIGN, 0, 252 BUS_SPACE_MAXADDR, 253 BUS_SPACE_MAXADDR, 254 NULL, NULL, 255 MCLBYTES, 256 1, 257 BUS_SPACE_MAXSIZE_32BIT, 258 0, 259 NULL, NULL, 260 &sc->bfe_tag); 261 262 if (error) { 263 device_printf(dev, "could not allocate dma tag\n"); 264 return (ENOMEM); 265 } 266 267 /* pre allocate dmamaps for RX list */ 268 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 269 error = bus_dmamap_create(sc->bfe_tag, 0, 270 &sc->bfe_rx_ring[i].bfe_map); 271 if (error) { 272 device_printf(dev, "cannot create DMA map for RX\n"); 273 return (ENOMEM); 274 } 275 } 276 277 /* pre allocate dmamaps for TX list */ 278 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 279 error = bus_dmamap_create(sc->bfe_tag, 0, 280 &sc->bfe_tx_ring[i].bfe_map); 281 if (error) { 282 device_printf(dev, "cannot create DMA map for TX\n"); 283 return (ENOMEM); 284 } 285 } 286 287 /* Alloc dma for rx ring */ 288 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 289 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 290 291 if(error) 292 return (ENOMEM); 293 294 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 295 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 296 sc->bfe_rx_list, sizeof(struct bfe_desc), 297 bfe_dma_map, &sc->bfe_rx_dma, 0); 298 299 if(error) 300 return (ENOMEM); 301 302 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 303 304 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 305 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 306 if (error) 307 return (ENOMEM); 308 309 310 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 311 sc->bfe_tx_list, sizeof(struct bfe_desc), 312 bfe_dma_map, &sc->bfe_tx_dma, 0); 313 if(error) 314 return (ENOMEM); 315 316 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 317 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 318 319 return (0); 320 } 321 322 static int 323 bfe_attach(device_t dev) 324 { 325 struct ifnet *ifp = NULL; 326 struct bfe_softc *sc; 327 int unit, error = 0, rid; 328 329 sc = device_get_softc(dev); 330 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 331 MTX_DEF); 332 333 unit = device_get_unit(dev); 334 sc->bfe_dev = dev; 335 sc->bfe_unit = unit; 336 337 /* 338 * Map control/status registers. 339 */ 340 pci_enable_busmaster(dev); 341 342 rid = BFE_PCI_MEMLO; 343 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 344 RF_ACTIVE); 345 if (sc->bfe_res == NULL) { 346 printf ("bfe%d: couldn't map memory\n", unit); 347 error = ENXIO; 348 goto fail; 349 } 350 351 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 352 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 353 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 354 355 /* Allocate interrupt */ 356 rid = 0; 357 358 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 359 RF_SHAREABLE | RF_ACTIVE); 360 if (sc->bfe_irq == NULL) { 361 printf("bfe%d: couldn't map interrupt\n", unit); 362 error = ENXIO; 363 goto fail; 364 } 365 366 if (bfe_dma_alloc(dev)) { 367 printf("bfe%d: failed to allocate DMA resources\n", 368 sc->bfe_unit); 369 bfe_release_resources(sc); 370 error = ENXIO; 371 goto fail; 372 } 373 374 /* Set up ifnet structure */ 375 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER); 376 if (ifp == NULL) { 377 printf("bfe%d: failed to if_alloc()\n", sc->bfe_unit); 378 error = ENOSPC; 379 goto fail; 380 } 381 ifp->if_softc = sc; 382 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 383 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 384 ifp->if_ioctl = bfe_ioctl; 385 ifp->if_start = bfe_start; 386 ifp->if_watchdog = bfe_watchdog; 387 ifp->if_init = bfe_init; 388 ifp->if_mtu = ETHERMTU; 389 ifp->if_baudrate = 100000000; 390 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 391 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 392 IFQ_SET_READY(&ifp->if_snd); 393 394 bfe_get_config(sc); 395 396 /* Reset the chip and turn on the PHY */ 397 BFE_LOCK(sc); 398 bfe_chip_reset(sc); 399 BFE_UNLOCK(sc); 400 401 if (mii_phy_probe(dev, &sc->bfe_miibus, 402 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 403 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 404 error = ENXIO; 405 goto fail; 406 } 407 408 ether_ifattach(ifp, sc->bfe_enaddr); 409 callout_handle_init(&sc->bfe_stat_ch); 410 411 /* 412 * Tell the upper layer(s) we support long frames. 413 */ 414 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 415 ifp->if_capabilities |= IFCAP_VLAN_MTU; 416 ifp->if_capenable |= IFCAP_VLAN_MTU; 417 418 /* 419 * Hook interrupt last to avoid having to lock softc 420 */ 421 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 422 bfe_intr, sc, &sc->bfe_intrhand); 423 424 if (error) { 425 bfe_release_resources(sc); 426 printf("bfe%d: couldn't set up irq\n", unit); 427 goto fail; 428 } 429 fail: 430 if (error) 431 bfe_release_resources(sc); 432 return (error); 433 } 434 435 static int 436 bfe_detach(device_t dev) 437 { 438 struct bfe_softc *sc; 439 struct ifnet *ifp; 440 441 sc = device_get_softc(dev); 442 443 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 444 BFE_LOCK(sc); 445 446 ifp = sc->bfe_ifp; 447 448 if (device_is_attached(dev)) { 449 bfe_stop(sc); 450 ether_ifdetach(ifp); 451 } 452 453 bfe_chip_reset(sc); 454 455 bus_generic_detach(dev); 456 if(sc->bfe_miibus != NULL) 457 device_delete_child(dev, sc->bfe_miibus); 458 459 bfe_release_resources(sc); 460 BFE_UNLOCK(sc); 461 mtx_destroy(&sc->bfe_mtx); 462 463 return (0); 464 } 465 466 /* 467 * Stop all chip I/O so that the kernel's probe routines don't 468 * get confused by errant DMAs when rebooting. 469 */ 470 static void 471 bfe_shutdown(device_t dev) 472 { 473 struct bfe_softc *sc; 474 475 sc = device_get_softc(dev); 476 BFE_LOCK(sc); 477 bfe_stop(sc); 478 479 BFE_UNLOCK(sc); 480 return; 481 } 482 483 static int 484 bfe_miibus_readreg(device_t dev, int phy, int reg) 485 { 486 struct bfe_softc *sc; 487 u_int32_t ret; 488 489 sc = device_get_softc(dev); 490 if(phy != sc->bfe_phyaddr) 491 return (0); 492 bfe_readphy(sc, reg, &ret); 493 494 return (ret); 495 } 496 497 static int 498 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 499 { 500 struct bfe_softc *sc; 501 502 sc = device_get_softc(dev); 503 if(phy != sc->bfe_phyaddr) 504 return (0); 505 bfe_writephy(sc, reg, val); 506 507 return (0); 508 } 509 510 static void 511 bfe_miibus_statchg(device_t dev) 512 { 513 return; 514 } 515 516 static void 517 bfe_tx_ring_free(struct bfe_softc *sc) 518 { 519 int i; 520 521 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 522 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 523 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 524 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 525 bus_dmamap_unload(sc->bfe_tag, 526 sc->bfe_tx_ring[i].bfe_map); 527 } 528 } 529 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 530 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 531 } 532 533 static void 534 bfe_rx_ring_free(struct bfe_softc *sc) 535 { 536 int i; 537 538 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 539 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 540 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 541 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 542 bus_dmamap_unload(sc->bfe_tag, 543 sc->bfe_rx_ring[i].bfe_map); 544 } 545 } 546 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 547 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 548 } 549 550 static int 551 bfe_list_rx_init(struct bfe_softc *sc) 552 { 553 int i; 554 555 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 556 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 557 return (ENOBUFS); 558 } 559 560 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 561 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 562 563 sc->bfe_rx_cons = 0; 564 565 return (0); 566 } 567 568 static int 569 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 570 { 571 struct bfe_rxheader *rx_header; 572 struct bfe_desc *d; 573 struct bfe_data *r; 574 u_int32_t ctrl; 575 576 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 577 return (EINVAL); 578 579 if(m == NULL) { 580 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 581 if(m == NULL) 582 return (ENOBUFS); 583 m->m_len = m->m_pkthdr.len = MCLBYTES; 584 } 585 else 586 m->m_data = m->m_ext.ext_buf; 587 588 rx_header = mtod(m, struct bfe_rxheader *); 589 rx_header->len = 0; 590 rx_header->flags = 0; 591 592 /* Map the mbuf into DMA */ 593 sc->bfe_rx_cnt = c; 594 d = &sc->bfe_rx_list[c]; 595 r = &sc->bfe_rx_ring[c]; 596 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 597 MCLBYTES, bfe_dma_map_desc, d, 0); 598 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREREAD); 599 600 ctrl = ETHER_MAX_LEN + 32; 601 602 if(c == BFE_RX_LIST_CNT - 1) 603 ctrl |= BFE_DESC_EOT; 604 605 d->bfe_ctrl = ctrl; 606 r->bfe_mbuf = m; 607 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 608 return (0); 609 } 610 611 static void 612 bfe_get_config(struct bfe_softc *sc) 613 { 614 u_int8_t eeprom[128]; 615 616 bfe_read_eeprom(sc, eeprom); 617 618 sc->bfe_enaddr[0] = eeprom[79]; 619 sc->bfe_enaddr[1] = eeprom[78]; 620 sc->bfe_enaddr[2] = eeprom[81]; 621 sc->bfe_enaddr[3] = eeprom[80]; 622 sc->bfe_enaddr[4] = eeprom[83]; 623 sc->bfe_enaddr[5] = eeprom[82]; 624 625 sc->bfe_phyaddr = eeprom[90] & 0x1f; 626 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 627 628 sc->bfe_core_unit = 0; 629 sc->bfe_dma_offset = BFE_PCI_DMA; 630 } 631 632 static void 633 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 634 { 635 u_int32_t bar_orig, pci_rev, val; 636 637 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 638 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 639 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 640 641 val = CSR_READ_4(sc, BFE_SBINTVEC); 642 val |= cores; 643 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 644 645 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 646 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 647 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 648 649 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 650 } 651 652 static void 653 bfe_clear_stats(struct bfe_softc *sc) 654 { 655 u_long reg; 656 657 BFE_LOCK_ASSERT(sc); 658 659 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 660 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 661 CSR_READ_4(sc, reg); 662 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 663 CSR_READ_4(sc, reg); 664 } 665 666 static int 667 bfe_resetphy(struct bfe_softc *sc) 668 { 669 u_int32_t val; 670 671 bfe_writephy(sc, 0, BMCR_RESET); 672 DELAY(100); 673 bfe_readphy(sc, 0, &val); 674 if (val & BMCR_RESET) { 675 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 676 return (ENXIO); 677 } 678 return (0); 679 } 680 681 static void 682 bfe_chip_halt(struct bfe_softc *sc) 683 { 684 BFE_LOCK_ASSERT(sc); 685 /* disable interrupts - not that it actually does..*/ 686 CSR_WRITE_4(sc, BFE_IMASK, 0); 687 CSR_READ_4(sc, BFE_IMASK); 688 689 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 690 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 691 692 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 693 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 694 DELAY(10); 695 } 696 697 static void 698 bfe_chip_reset(struct bfe_softc *sc) 699 { 700 u_int32_t val; 701 702 BFE_LOCK_ASSERT(sc); 703 704 /* Set the interrupt vector for the enet core */ 705 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 706 707 /* is core up? */ 708 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 709 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 710 if (val == BFE_CLOCK) { 711 /* It is, so shut it down */ 712 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 713 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 714 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 715 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 716 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 717 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 718 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 719 100, 0); 720 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 721 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 722 } 723 724 bfe_core_reset(sc); 725 bfe_clear_stats(sc); 726 727 /* 728 * We want the phy registers to be accessible even when 729 * the driver is "downed" so initialize MDC preamble, frequency, 730 * and whether internal or external phy here. 731 */ 732 733 /* 4402 has 62.5Mhz SB clock and internal phy */ 734 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 735 736 /* Internal or external PHY? */ 737 val = CSR_READ_4(sc, BFE_DEVCTRL); 738 if(!(val & BFE_IPP)) 739 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 740 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 741 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 742 DELAY(100); 743 } 744 745 /* Enable CRC32 generation and set proper LED modes */ 746 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 747 748 /* Reset or clear powerdown control bit */ 749 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 750 751 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 752 BFE_LAZY_FC_MASK)); 753 754 /* 755 * We don't want lazy interrupts, so just send them at 756 * the end of a frame, please 757 */ 758 BFE_OR(sc, BFE_RCV_LAZY, 0); 759 760 /* Set max lengths, accounting for VLAN tags */ 761 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 762 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 763 764 /* Set watermark XXX - magic */ 765 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 766 767 /* 768 * Initialise DMA channels 769 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 770 */ 771 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 772 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 773 774 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 775 BFE_RX_CTRL_ENABLE); 776 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 777 778 bfe_resetphy(sc); 779 bfe_setupphy(sc); 780 } 781 782 static void 783 bfe_core_disable(struct bfe_softc *sc) 784 { 785 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 786 return; 787 788 /* 789 * Set reject, wait for it set, then wait for the core to stop 790 * being busy, then set reset and reject and enable the clocks. 791 */ 792 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 793 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 794 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 795 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 796 BFE_RESET)); 797 CSR_READ_4(sc, BFE_SBTMSLOW); 798 DELAY(10); 799 /* Leave reset and reject set */ 800 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 801 DELAY(10); 802 } 803 804 static void 805 bfe_core_reset(struct bfe_softc *sc) 806 { 807 u_int32_t val; 808 809 /* Disable the core */ 810 bfe_core_disable(sc); 811 812 /* and bring it back up */ 813 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 814 CSR_READ_4(sc, BFE_SBTMSLOW); 815 DELAY(10); 816 817 /* Chip bug, clear SERR, IB and TO if they are set. */ 818 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 819 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 820 val = CSR_READ_4(sc, BFE_SBIMSTATE); 821 if (val & (BFE_IBE | BFE_TO)) 822 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 823 824 /* Clear reset and allow it to move through the core */ 825 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 826 CSR_READ_4(sc, BFE_SBTMSLOW); 827 DELAY(10); 828 829 /* Leave the clock set */ 830 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 831 CSR_READ_4(sc, BFE_SBTMSLOW); 832 DELAY(10); 833 } 834 835 static void 836 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 837 { 838 u_int32_t val; 839 840 val = ((u_int32_t) data[2]) << 24; 841 val |= ((u_int32_t) data[3]) << 16; 842 val |= ((u_int32_t) data[4]) << 8; 843 val |= ((u_int32_t) data[5]); 844 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 845 val = (BFE_CAM_HI_VALID | 846 (((u_int32_t) data[0]) << 8) | 847 (((u_int32_t) data[1]))); 848 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 849 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 850 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 851 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 852 } 853 854 static void 855 bfe_set_rx_mode(struct bfe_softc *sc) 856 { 857 struct ifnet *ifp = sc->bfe_ifp; 858 struct ifmultiaddr *ifma; 859 u_int32_t val; 860 int i = 0; 861 862 val = CSR_READ_4(sc, BFE_RXCONF); 863 864 if (ifp->if_flags & IFF_PROMISC) 865 val |= BFE_RXCONF_PROMISC; 866 else 867 val &= ~BFE_RXCONF_PROMISC; 868 869 if (ifp->if_flags & IFF_BROADCAST) 870 val &= ~BFE_RXCONF_DBCAST; 871 else 872 val |= BFE_RXCONF_DBCAST; 873 874 875 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 876 bfe_cam_write(sc, IFP2ENADDR(sc->bfe_ifp), i++); 877 878 if (ifp->if_flags & IFF_ALLMULTI) 879 val |= BFE_RXCONF_ALLMULTI; 880 else { 881 val &= ~BFE_RXCONF_ALLMULTI; 882 IF_ADDR_LOCK(ifp); 883 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 884 if (ifma->ifma_addr->sa_family != AF_LINK) 885 continue; 886 bfe_cam_write(sc, 887 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 888 } 889 IF_ADDR_UNLOCK(ifp); 890 } 891 892 CSR_WRITE_4(sc, BFE_RXCONF, val); 893 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 894 } 895 896 static void 897 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 898 { 899 u_int32_t *ptr; 900 901 ptr = arg; 902 *ptr = segs->ds_addr; 903 } 904 905 static void 906 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 907 { 908 struct bfe_desc *d; 909 910 d = arg; 911 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 912 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 913 } 914 915 static void 916 bfe_release_resources(struct bfe_softc *sc) 917 { 918 device_t dev; 919 int i; 920 921 dev = sc->bfe_dev; 922 923 if (sc->bfe_vpd_prodname != NULL) 924 free(sc->bfe_vpd_prodname, M_DEVBUF); 925 926 if (sc->bfe_vpd_readonly != NULL) 927 free(sc->bfe_vpd_readonly, M_DEVBUF); 928 929 if (sc->bfe_intrhand != NULL) 930 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 931 932 if (sc->bfe_irq != NULL) 933 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 934 935 if (sc->bfe_res != NULL) 936 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 937 938 if (sc->bfe_ifp != NULL) 939 if_free(sc->bfe_ifp); 940 941 if(sc->bfe_tx_tag != NULL) { 942 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 943 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 944 sc->bfe_tx_map); 945 bus_dma_tag_destroy(sc->bfe_tx_tag); 946 sc->bfe_tx_tag = NULL; 947 } 948 949 if(sc->bfe_rx_tag != NULL) { 950 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 951 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 952 sc->bfe_rx_map); 953 bus_dma_tag_destroy(sc->bfe_rx_tag); 954 sc->bfe_rx_tag = NULL; 955 } 956 957 if(sc->bfe_tag != NULL) { 958 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 959 bus_dmamap_destroy(sc->bfe_tag, 960 sc->bfe_tx_ring[i].bfe_map); 961 } 962 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 963 bus_dmamap_destroy(sc->bfe_tag, 964 sc->bfe_rx_ring[i].bfe_map); 965 } 966 bus_dma_tag_destroy(sc->bfe_tag); 967 sc->bfe_tag = NULL; 968 } 969 970 if(sc->bfe_parent_tag != NULL) 971 bus_dma_tag_destroy(sc->bfe_parent_tag); 972 973 return; 974 } 975 976 static void 977 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 978 { 979 long i; 980 u_int16_t *ptr = (u_int16_t *)data; 981 982 for(i = 0; i < 128; i += 2) 983 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 984 } 985 986 static int 987 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 988 u_long timeout, const int clear) 989 { 990 u_long i; 991 992 for (i = 0; i < timeout; i++) { 993 u_int32_t val = CSR_READ_4(sc, reg); 994 995 if (clear && !(val & bit)) 996 break; 997 if (!clear && (val & bit)) 998 break; 999 DELAY(10); 1000 } 1001 if (i == timeout) { 1002 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1003 "%x to %s.\n", sc->bfe_unit, bit, reg, 1004 (clear ? "clear" : "set")); 1005 return (-1); 1006 } 1007 return (0); 1008 } 1009 1010 static int 1011 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1012 { 1013 int err; 1014 1015 /* Clear MII ISR */ 1016 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1017 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1018 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1019 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1020 (reg << BFE_MDIO_RA_SHIFT) | 1021 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1022 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1023 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1024 1025 return (err); 1026 } 1027 1028 static int 1029 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1030 { 1031 int status; 1032 1033 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1034 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1035 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1036 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1037 (reg << BFE_MDIO_RA_SHIFT) | 1038 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1039 (val & BFE_MDIO_DATA_DATA))); 1040 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1041 1042 return (status); 1043 } 1044 1045 /* 1046 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1047 * twice 1048 */ 1049 static int 1050 bfe_setupphy(struct bfe_softc *sc) 1051 { 1052 u_int32_t val; 1053 1054 /* Enable activity LED */ 1055 bfe_readphy(sc, 26, &val); 1056 bfe_writephy(sc, 26, val & 0x7fff); 1057 bfe_readphy(sc, 26, &val); 1058 1059 /* Enable traffic meter LED mode */ 1060 bfe_readphy(sc, 27, &val); 1061 bfe_writephy(sc, 27, val | (1 << 6)); 1062 1063 return (0); 1064 } 1065 1066 static void 1067 bfe_stats_update(struct bfe_softc *sc) 1068 { 1069 u_long reg; 1070 u_int32_t *val; 1071 1072 val = &sc->bfe_hwstats.tx_good_octets; 1073 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1074 *val++ += CSR_READ_4(sc, reg); 1075 } 1076 val = &sc->bfe_hwstats.rx_good_octets; 1077 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1078 *val++ += CSR_READ_4(sc, reg); 1079 } 1080 } 1081 1082 static void 1083 bfe_txeof(struct bfe_softc *sc) 1084 { 1085 struct ifnet *ifp; 1086 int i, chipidx; 1087 1088 BFE_LOCK_ASSERT(sc); 1089 1090 ifp = sc->bfe_ifp; 1091 1092 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1093 chipidx /= sizeof(struct bfe_desc); 1094 1095 i = sc->bfe_tx_cons; 1096 /* Go through the mbufs and free those that have been transmitted */ 1097 while(i != chipidx) { 1098 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1099 if(r->bfe_mbuf != NULL) { 1100 ifp->if_opackets++; 1101 m_freem(r->bfe_mbuf); 1102 r->bfe_mbuf = NULL; 1103 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1104 } 1105 sc->bfe_tx_cnt--; 1106 BFE_INC(i, BFE_TX_LIST_CNT); 1107 } 1108 1109 if(i != sc->bfe_tx_cons) { 1110 /* we freed up some mbufs */ 1111 sc->bfe_tx_cons = i; 1112 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1113 } 1114 if(sc->bfe_tx_cnt == 0) 1115 ifp->if_timer = 0; 1116 else 1117 ifp->if_timer = 5; 1118 } 1119 1120 /* Pass a received packet up the stack */ 1121 static void 1122 bfe_rxeof(struct bfe_softc *sc) 1123 { 1124 struct mbuf *m; 1125 struct ifnet *ifp; 1126 struct bfe_rxheader *rxheader; 1127 struct bfe_data *r; 1128 int cons; 1129 u_int32_t status, current, len, flags; 1130 1131 BFE_LOCK_ASSERT(sc); 1132 cons = sc->bfe_rx_cons; 1133 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1134 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1135 1136 ifp = sc->bfe_ifp; 1137 1138 while(current != cons) { 1139 r = &sc->bfe_rx_ring[cons]; 1140 m = r->bfe_mbuf; 1141 rxheader = mtod(m, struct bfe_rxheader*); 1142 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1143 len = rxheader->len; 1144 r->bfe_mbuf = NULL; 1145 1146 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1147 flags = rxheader->flags; 1148 1149 len -= ETHER_CRC_LEN; 1150 1151 /* flag an error and try again */ 1152 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1153 ifp->if_ierrors++; 1154 if (flags & BFE_RX_FLAG_SERR) 1155 ifp->if_collisions++; 1156 bfe_list_newbuf(sc, cons, m); 1157 BFE_INC(cons, BFE_RX_LIST_CNT); 1158 continue; 1159 } 1160 1161 /* Go past the rx header */ 1162 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1163 m_adj(m, BFE_RX_OFFSET); 1164 m->m_len = m->m_pkthdr.len = len; 1165 } else { 1166 bfe_list_newbuf(sc, cons, m); 1167 ifp->if_ierrors++; 1168 BFE_INC(cons, BFE_RX_LIST_CNT); 1169 continue; 1170 } 1171 1172 ifp->if_ipackets++; 1173 m->m_pkthdr.rcvif = ifp; 1174 BFE_UNLOCK(sc); 1175 (*ifp->if_input)(ifp, m); 1176 BFE_LOCK(sc); 1177 1178 BFE_INC(cons, BFE_RX_LIST_CNT); 1179 } 1180 sc->bfe_rx_cons = cons; 1181 } 1182 1183 static void 1184 bfe_intr(void *xsc) 1185 { 1186 struct bfe_softc *sc = xsc; 1187 struct ifnet *ifp; 1188 u_int32_t istat, imask, flag; 1189 1190 ifp = sc->bfe_ifp; 1191 1192 BFE_LOCK(sc); 1193 1194 istat = CSR_READ_4(sc, BFE_ISTAT); 1195 imask = CSR_READ_4(sc, BFE_IMASK); 1196 1197 /* 1198 * Defer unsolicited interrupts - This is necessary because setting the 1199 * chips interrupt mask register to 0 doesn't actually stop the 1200 * interrupts 1201 */ 1202 istat &= imask; 1203 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1204 CSR_READ_4(sc, BFE_ISTAT); 1205 1206 /* not expecting this interrupt, disregard it */ 1207 if(istat == 0) { 1208 BFE_UNLOCK(sc); 1209 return; 1210 } 1211 1212 if(istat & BFE_ISTAT_ERRORS) { 1213 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1214 if(flag & BFE_STAT_EMASK) 1215 ifp->if_oerrors++; 1216 1217 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1218 if(flag & BFE_RX_FLAG_ERRORS) 1219 ifp->if_ierrors++; 1220 1221 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1222 bfe_init_locked(sc); 1223 } 1224 1225 /* A packet was received */ 1226 if(istat & BFE_ISTAT_RX) 1227 bfe_rxeof(sc); 1228 1229 /* A packet was sent */ 1230 if(istat & BFE_ISTAT_TX) 1231 bfe_txeof(sc); 1232 1233 /* We have packets pending, fire them out */ 1234 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1235 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1236 bfe_start_locked(ifp); 1237 1238 BFE_UNLOCK(sc); 1239 } 1240 1241 static int 1242 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1243 { 1244 struct bfe_desc *d = NULL; 1245 struct bfe_data *r = NULL; 1246 struct mbuf *m; 1247 u_int32_t frag, cur, cnt = 0; 1248 int chainlen = 0; 1249 1250 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1251 return (ENOBUFS); 1252 1253 /* 1254 * Count the number of frags in this chain to see if 1255 * we need to m_defrag. Since the descriptor list is shared 1256 * by all packets, we'll m_defrag long chains so that they 1257 * do not use up the entire list, even if they would fit. 1258 */ 1259 for(m = m_head; m != NULL; m = m->m_next) 1260 chainlen++; 1261 1262 1263 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1264 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1265 m = m_defrag(m_head, M_DONTWAIT); 1266 if (m == NULL) 1267 return (ENOBUFS); 1268 m_head = m; 1269 } 1270 1271 /* 1272 * Start packing the mbufs in this chain into 1273 * the fragment pointers. Stop when we run out 1274 * of fragments or hit the end of the mbuf chain. 1275 */ 1276 m = m_head; 1277 cur = frag = *txidx; 1278 cnt = 0; 1279 1280 for(m = m_head; m != NULL; m = m->m_next) { 1281 if(m->m_len != 0) { 1282 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1283 return (ENOBUFS); 1284 1285 d = &sc->bfe_tx_list[cur]; 1286 r = &sc->bfe_tx_ring[cur]; 1287 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1288 /* always intterupt on completion */ 1289 d->bfe_ctrl |= BFE_DESC_IOC; 1290 if(cnt == 0) 1291 /* Set start of frame */ 1292 d->bfe_ctrl |= BFE_DESC_SOF; 1293 if(cur == BFE_TX_LIST_CNT - 1) 1294 /* 1295 * Tell the chip to wrap to the start of 1296 * the descriptor list 1297 */ 1298 d->bfe_ctrl |= BFE_DESC_EOT; 1299 1300 bus_dmamap_load(sc->bfe_tag, 1301 r->bfe_map, mtod(m, void*), m->m_len, 1302 bfe_dma_map_desc, d, 0); 1303 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1304 BUS_DMASYNC_PREREAD); 1305 1306 frag = cur; 1307 BFE_INC(cur, BFE_TX_LIST_CNT); 1308 cnt++; 1309 } 1310 } 1311 1312 if (m != NULL) 1313 return (ENOBUFS); 1314 1315 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1316 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1317 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1318 1319 *txidx = cur; 1320 sc->bfe_tx_cnt += cnt; 1321 return (0); 1322 } 1323 1324 /* 1325 * Set up to transmit a packet. 1326 */ 1327 static void 1328 bfe_start(struct ifnet *ifp) 1329 { 1330 BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1331 bfe_start_locked(ifp); 1332 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1333 } 1334 1335 /* 1336 * Set up to transmit a packet. The softc is already locked. 1337 */ 1338 static void 1339 bfe_start_locked(struct ifnet *ifp) 1340 { 1341 struct bfe_softc *sc; 1342 struct mbuf *m_head = NULL; 1343 int idx, queued = 0; 1344 1345 sc = ifp->if_softc; 1346 idx = sc->bfe_tx_prod; 1347 1348 BFE_LOCK_ASSERT(sc); 1349 1350 /* 1351 * Not much point trying to send if the link is down 1352 * or we have nothing to send. 1353 */ 1354 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) 1355 return; 1356 1357 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1358 return; 1359 1360 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1361 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1362 if(m_head == NULL) 1363 break; 1364 1365 /* 1366 * Pack the data into the tx ring. If we dont have 1367 * enough room, let the chip drain the ring. 1368 */ 1369 if(bfe_encap(sc, m_head, &idx)) { 1370 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1371 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1372 break; 1373 } 1374 1375 queued++; 1376 1377 /* 1378 * If there's a BPF listener, bounce a copy of this frame 1379 * to him. 1380 */ 1381 BPF_MTAP(ifp, m_head); 1382 } 1383 1384 if (queued) { 1385 sc->bfe_tx_prod = idx; 1386 /* Transmit - twice due to apparent hardware bug */ 1387 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1388 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1389 1390 /* 1391 * Set a timeout in case the chip goes out to lunch. 1392 */ 1393 ifp->if_timer = 5; 1394 } 1395 } 1396 1397 static void 1398 bfe_init(void *xsc) 1399 { 1400 BFE_LOCK((struct bfe_softc *)xsc); 1401 bfe_init_locked(xsc); 1402 BFE_UNLOCK((struct bfe_softc *)xsc); 1403 } 1404 1405 static void 1406 bfe_init_locked(void *xsc) 1407 { 1408 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1409 struct ifnet *ifp = sc->bfe_ifp; 1410 1411 BFE_LOCK_ASSERT(sc); 1412 1413 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1414 return; 1415 1416 bfe_stop(sc); 1417 bfe_chip_reset(sc); 1418 1419 if (bfe_list_rx_init(sc) == ENOBUFS) { 1420 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1421 sc->bfe_unit); 1422 bfe_stop(sc); 1423 return; 1424 } 1425 1426 bfe_set_rx_mode(sc); 1427 1428 /* Enable the chip and core */ 1429 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1430 /* Enable interrupts */ 1431 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1432 1433 bfe_ifmedia_upd(ifp); 1434 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1435 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1436 1437 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1438 } 1439 1440 /* 1441 * Set media options. 1442 */ 1443 static int 1444 bfe_ifmedia_upd(struct ifnet *ifp) 1445 { 1446 struct bfe_softc *sc; 1447 struct mii_data *mii; 1448 1449 sc = ifp->if_softc; 1450 1451 mii = device_get_softc(sc->bfe_miibus); 1452 sc->bfe_link = 0; 1453 if (mii->mii_instance) { 1454 struct mii_softc *miisc; 1455 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1456 miisc = LIST_NEXT(miisc, mii_list)) 1457 mii_phy_reset(miisc); 1458 } 1459 mii_mediachg(mii); 1460 1461 return (0); 1462 } 1463 1464 /* 1465 * Report current media status. 1466 */ 1467 static void 1468 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1469 { 1470 struct bfe_softc *sc = ifp->if_softc; 1471 struct mii_data *mii; 1472 1473 mii = device_get_softc(sc->bfe_miibus); 1474 mii_pollstat(mii); 1475 ifmr->ifm_active = mii->mii_media_active; 1476 ifmr->ifm_status = mii->mii_media_status; 1477 } 1478 1479 static int 1480 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1481 { 1482 struct bfe_softc *sc = ifp->if_softc; 1483 struct ifreq *ifr = (struct ifreq *) data; 1484 struct mii_data *mii; 1485 int error = 0; 1486 1487 switch(command) { 1488 case SIOCSIFFLAGS: 1489 BFE_LOCK(sc); 1490 if(ifp->if_flags & IFF_UP) 1491 if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1492 bfe_set_rx_mode(sc); 1493 else 1494 bfe_init_locked(sc); 1495 else if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1496 bfe_stop(sc); 1497 BFE_UNLOCK(sc); 1498 break; 1499 case SIOCADDMULTI: 1500 case SIOCDELMULTI: 1501 BFE_LOCK(sc); 1502 if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1503 bfe_set_rx_mode(sc); 1504 BFE_UNLOCK(sc); 1505 break; 1506 case SIOCGIFMEDIA: 1507 case SIOCSIFMEDIA: 1508 mii = device_get_softc(sc->bfe_miibus); 1509 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1510 command); 1511 break; 1512 default: 1513 error = ether_ioctl(ifp, command, data); 1514 break; 1515 } 1516 1517 return (error); 1518 } 1519 1520 static void 1521 bfe_watchdog(struct ifnet *ifp) 1522 { 1523 struct bfe_softc *sc; 1524 1525 sc = ifp->if_softc; 1526 1527 BFE_LOCK(sc); 1528 1529 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1530 1531 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1532 bfe_init_locked(sc); 1533 1534 ifp->if_oerrors++; 1535 1536 BFE_UNLOCK(sc); 1537 } 1538 1539 static void 1540 bfe_tick(void *xsc) 1541 { 1542 struct bfe_softc *sc = xsc; 1543 struct mii_data *mii; 1544 1545 if (sc == NULL) 1546 return; 1547 1548 BFE_LOCK(sc); 1549 1550 mii = device_get_softc(sc->bfe_miibus); 1551 1552 bfe_stats_update(sc); 1553 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1554 1555 if(sc->bfe_link) { 1556 BFE_UNLOCK(sc); 1557 return; 1558 } 1559 1560 mii_tick(mii); 1561 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1562 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1563 sc->bfe_link++; 1564 1565 BFE_UNLOCK(sc); 1566 } 1567 1568 /* 1569 * Stop the adapter and free any mbufs allocated to the 1570 * RX and TX lists. 1571 */ 1572 static void 1573 bfe_stop(struct bfe_softc *sc) 1574 { 1575 struct ifnet *ifp; 1576 1577 BFE_LOCK_ASSERT(sc); 1578 1579 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1580 1581 ifp = sc->bfe_ifp; 1582 1583 bfe_chip_halt(sc); 1584 bfe_tx_ring_free(sc); 1585 bfe_rx_ring_free(sc); 1586 1587 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1588 }
Cache object: 27369a0cf245823ecf68cd419c2d8d80
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