FreeBSD/Linux Kernel Cross Reference
sys/dev/bfe/if_bfe.c
1 /*-
2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
3 * and Duncan Barclay<dmlb@dmlb.org>
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD: releng/6.1/sys/dev/bfe/if_bfe.c 158162 2006-04-30 04:55:34Z kensmith $");
30
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/sockio.h>
34 #include <sys/mbuf.h>
35 #include <sys/malloc.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
38 #include <sys/socket.h>
39 #include <sys/queue.h>
40
41 #include <net/if.h>
42 #include <net/if_arp.h>
43 #include <net/ethernet.h>
44 #include <net/if_dl.h>
45 #include <net/if_media.h>
46
47 #include <net/bpf.h>
48
49 #include <net/if_types.h>
50 #include <net/if_vlan_var.h>
51
52 #include <netinet/in_systm.h>
53 #include <netinet/in.h>
54 #include <netinet/ip.h>
55
56 #include <machine/clock.h> /* for DELAY */
57 #include <machine/bus.h>
58 #include <machine/resource.h>
59 #include <sys/bus.h>
60 #include <sys/rman.h>
61
62 #include <dev/mii/mii.h>
63 #include <dev/mii/miivar.h>
64 #include "miidevs.h"
65
66 #include <dev/pci/pcireg.h>
67 #include <dev/pci/pcivar.h>
68
69 #include <dev/bfe/if_bfereg.h>
70
71 MODULE_DEPEND(bfe, pci, 1, 1, 1);
72 MODULE_DEPEND(bfe, ether, 1, 1, 1);
73 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
74
75 /* "controller miibus0" required. See GENERIC if you get errors here. */
76 #include "miibus_if.h"
77
78 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
79
80 static struct bfe_type bfe_devs[] = {
81 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401,
82 "Broadcom BCM4401 Fast Ethernet" },
83 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0,
84 "Broadcom BCM4401-B0 Fast Ethernet" },
85 { 0, 0, NULL }
86 };
87
88 static int bfe_probe (device_t);
89 static int bfe_attach (device_t);
90 static int bfe_detach (device_t);
91 static void bfe_release_resources (struct bfe_softc *);
92 static void bfe_intr (void *);
93 static void bfe_start (struct ifnet *);
94 static void bfe_start_locked (struct ifnet *);
95 static int bfe_ioctl (struct ifnet *, u_long, caddr_t);
96 static void bfe_init (void *);
97 static void bfe_init_locked (void *);
98 static void bfe_stop (struct bfe_softc *);
99 static void bfe_watchdog (struct ifnet *);
100 static void bfe_shutdown (device_t);
101 static void bfe_tick (void *);
102 static void bfe_txeof (struct bfe_softc *);
103 static void bfe_rxeof (struct bfe_softc *);
104 static void bfe_set_rx_mode (struct bfe_softc *);
105 static int bfe_list_rx_init (struct bfe_softc *);
106 static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*);
107 static void bfe_rx_ring_free (struct bfe_softc *);
108
109 static void bfe_pci_setup (struct bfe_softc *, u_int32_t);
110 static int bfe_ifmedia_upd (struct ifnet *);
111 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *);
112 static int bfe_miibus_readreg (device_t, int, int);
113 static int bfe_miibus_writereg (device_t, int, int, int);
114 static void bfe_miibus_statchg (device_t);
115 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t,
116 u_long, const int);
117 static void bfe_get_config (struct bfe_softc *sc);
118 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *);
119 static void bfe_stats_update (struct bfe_softc *);
120 static void bfe_clear_stats (struct bfe_softc *);
121 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*);
122 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t);
123 static int bfe_resetphy (struct bfe_softc *);
124 static int bfe_setupphy (struct bfe_softc *);
125 static void bfe_chip_reset (struct bfe_softc *);
126 static void bfe_chip_halt (struct bfe_softc *);
127 static void bfe_core_reset (struct bfe_softc *);
128 static void bfe_core_disable (struct bfe_softc *);
129 static int bfe_dma_alloc (device_t);
130 static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int);
131 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int);
132 static void bfe_cam_write (struct bfe_softc *, u_char *, int);
133
134 static device_method_t bfe_methods[] = {
135 /* Device interface */
136 DEVMETHOD(device_probe, bfe_probe),
137 DEVMETHOD(device_attach, bfe_attach),
138 DEVMETHOD(device_detach, bfe_detach),
139 DEVMETHOD(device_shutdown, bfe_shutdown),
140
141 /* bus interface */
142 DEVMETHOD(bus_print_child, bus_generic_print_child),
143 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
144
145 /* MII interface */
146 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
147 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
148 DEVMETHOD(miibus_statchg, bfe_miibus_statchg),
149
150 { 0, 0 }
151 };
152
153 static driver_t bfe_driver = {
154 "bfe",
155 bfe_methods,
156 sizeof(struct bfe_softc)
157 };
158
159 static devclass_t bfe_devclass;
160
161 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
162 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
163
164 /*
165 * Probe for a Broadcom 4401 chip.
166 */
167 static int
168 bfe_probe(device_t dev)
169 {
170 struct bfe_type *t;
171 struct bfe_softc *sc;
172
173 t = bfe_devs;
174
175 sc = device_get_softc(dev);
176 bzero(sc, sizeof(struct bfe_softc));
177 sc->bfe_unit = device_get_unit(dev);
178 sc->bfe_dev = dev;
179
180 while(t->bfe_name != NULL) {
181 if ((pci_get_vendor(dev) == t->bfe_vid) &&
182 (pci_get_device(dev) == t->bfe_did)) {
183 device_set_desc_copy(dev, t->bfe_name);
184 return (BUS_PROBE_DEFAULT);
185 }
186 t++;
187 }
188
189 return (ENXIO);
190 }
191
192 static int
193 bfe_dma_alloc(device_t dev)
194 {
195 struct bfe_softc *sc;
196 int error, i;
197
198 sc = device_get_softc(dev);
199
200 /*
201 * parent tag. Apparently the chip cannot handle any DMA address
202 * greater than 1GB.
203 */
204 error = bus_dma_tag_create(NULL, /* parent */
205 PAGE_SIZE, 0, /* alignment, boundary */
206 0x3FFFFFFF, /* lowaddr */
207 BUS_SPACE_MAXADDR, /* highaddr */
208 NULL, NULL, /* filter, filterarg */
209 MAXBSIZE, /* maxsize */
210 BUS_SPACE_UNRESTRICTED, /* num of segments */
211 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */
212 0, /* flags */
213 NULL, NULL, /* lockfunc, lockarg */
214 &sc->bfe_parent_tag);
215
216 /* tag for TX ring */
217 error = bus_dma_tag_create(sc->bfe_parent_tag,
218 1, 0,
219 BUS_SPACE_MAXADDR,
220 BUS_SPACE_MAXADDR,
221 NULL, NULL,
222 BFE_TX_LIST_SIZE,
223 1,
224 BUS_SPACE_MAXSIZE_32BIT,
225 0,
226 NULL, NULL,
227 &sc->bfe_tx_tag);
228
229 if (error) {
230 device_printf(dev, "could not allocate dma tag\n");
231 return (ENOMEM);
232 }
233
234 /* tag for RX ring */
235 error = bus_dma_tag_create(sc->bfe_parent_tag,
236 1, 0,
237 BUS_SPACE_MAXADDR,
238 BUS_SPACE_MAXADDR,
239 NULL, NULL,
240 BFE_RX_LIST_SIZE,
241 1,
242 BUS_SPACE_MAXSIZE_32BIT,
243 0,
244 NULL, NULL,
245 &sc->bfe_rx_tag);
246
247 if (error) {
248 device_printf(dev, "could not allocate dma tag\n");
249 return (ENOMEM);
250 }
251
252 /* tag for mbufs */
253 error = bus_dma_tag_create(sc->bfe_parent_tag,
254 ETHER_ALIGN, 0,
255 BUS_SPACE_MAXADDR,
256 BUS_SPACE_MAXADDR,
257 NULL, NULL,
258 MCLBYTES,
259 1,
260 BUS_SPACE_MAXSIZE_32BIT,
261 BUS_DMA_ALLOCNOW,
262 NULL, NULL,
263 &sc->bfe_tag);
264
265 if (error) {
266 device_printf(dev, "could not allocate dma tag\n");
267 return (ENOMEM);
268 }
269
270 /* pre allocate dmamaps for RX list */
271 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
272 error = bus_dmamap_create(sc->bfe_tag, 0,
273 &sc->bfe_rx_ring[i].bfe_map);
274 if (error) {
275 device_printf(dev, "cannot create DMA map for RX\n");
276 return (ENOMEM);
277 }
278 }
279
280 /* pre allocate dmamaps for TX list */
281 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
282 error = bus_dmamap_create(sc->bfe_tag, 0,
283 &sc->bfe_tx_ring[i].bfe_map);
284 if (error) {
285 device_printf(dev, "cannot create DMA map for TX\n");
286 return (ENOMEM);
287 }
288 }
289
290 /* Alloc dma for rx ring */
291 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
292 BUS_DMA_NOWAIT, &sc->bfe_rx_map);
293
294 if(error)
295 return (ENOMEM);
296
297 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
298 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
299 sc->bfe_rx_list, sizeof(struct bfe_desc),
300 bfe_dma_map, &sc->bfe_rx_dma, 0);
301
302 if(error)
303 return (ENOMEM);
304
305 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
306
307 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
308 BUS_DMA_NOWAIT, &sc->bfe_tx_map);
309 if (error)
310 return (ENOMEM);
311
312
313 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
314 sc->bfe_tx_list, sizeof(struct bfe_desc),
315 bfe_dma_map, &sc->bfe_tx_dma, 0);
316 if(error)
317 return (ENOMEM);
318
319 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
320 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
321
322 return (0);
323 }
324
325 static int
326 bfe_attach(device_t dev)
327 {
328 struct ifnet *ifp = NULL;
329 struct bfe_softc *sc;
330 int unit, error = 0, rid;
331
332 sc = device_get_softc(dev);
333 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
334 MTX_DEF);
335
336 unit = device_get_unit(dev);
337 sc->bfe_dev = dev;
338 sc->bfe_unit = unit;
339
340 /*
341 * Map control/status registers.
342 */
343 pci_enable_busmaster(dev);
344
345 rid = BFE_PCI_MEMLO;
346 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
347 RF_ACTIVE);
348 if (sc->bfe_res == NULL) {
349 printf ("bfe%d: couldn't map memory\n", unit);
350 error = ENXIO;
351 goto fail;
352 }
353
354 sc->bfe_btag = rman_get_bustag(sc->bfe_res);
355 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res);
356 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res);
357
358 /* Allocate interrupt */
359 rid = 0;
360
361 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
362 RF_SHAREABLE | RF_ACTIVE);
363 if (sc->bfe_irq == NULL) {
364 printf("bfe%d: couldn't map interrupt\n", unit);
365 error = ENXIO;
366 goto fail;
367 }
368
369 if (bfe_dma_alloc(dev)) {
370 printf("bfe%d: failed to allocate DMA resources\n",
371 sc->bfe_unit);
372 bfe_release_resources(sc);
373 error = ENXIO;
374 goto fail;
375 }
376
377 /* Set up ifnet structure */
378 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER);
379 if (ifp == NULL) {
380 printf("bfe%d: failed to if_alloc()\n", sc->bfe_unit);
381 error = ENOSPC;
382 goto fail;
383 }
384 ifp->if_softc = sc;
385 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
386 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
387 ifp->if_ioctl = bfe_ioctl;
388 ifp->if_start = bfe_start;
389 ifp->if_watchdog = bfe_watchdog;
390 ifp->if_init = bfe_init;
391 ifp->if_mtu = ETHERMTU;
392 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN);
393 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN;
394 IFQ_SET_READY(&ifp->if_snd);
395
396 bfe_get_config(sc);
397
398 /* Reset the chip and turn on the PHY */
399 BFE_LOCK(sc);
400 bfe_chip_reset(sc);
401 BFE_UNLOCK(sc);
402
403 if (mii_phy_probe(dev, &sc->bfe_miibus,
404 bfe_ifmedia_upd, bfe_ifmedia_sts)) {
405 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit);
406 error = ENXIO;
407 goto fail;
408 }
409
410 ether_ifattach(ifp, sc->bfe_enaddr);
411 callout_handle_init(&sc->bfe_stat_ch);
412
413 /*
414 * Tell the upper layer(s) we support long frames.
415 */
416 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
417 ifp->if_capabilities |= IFCAP_VLAN_MTU;
418 ifp->if_capenable |= IFCAP_VLAN_MTU;
419
420 /*
421 * Hook interrupt last to avoid having to lock softc
422 */
423 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE,
424 bfe_intr, sc, &sc->bfe_intrhand);
425
426 if (error) {
427 bfe_release_resources(sc);
428 printf("bfe%d: couldn't set up irq\n", unit);
429 goto fail;
430 }
431 fail:
432 if (error)
433 bfe_release_resources(sc);
434 return (error);
435 }
436
437 static int
438 bfe_detach(device_t dev)
439 {
440 struct bfe_softc *sc;
441 struct ifnet *ifp;
442
443 sc = device_get_softc(dev);
444
445 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized"));
446 BFE_LOCK(sc);
447
448 ifp = sc->bfe_ifp;
449
450 if (device_is_attached(dev)) {
451 bfe_stop(sc);
452 ether_ifdetach(ifp);
453 }
454
455 bfe_chip_reset(sc);
456
457 bus_generic_detach(dev);
458 if(sc->bfe_miibus != NULL)
459 device_delete_child(dev, sc->bfe_miibus);
460
461 bfe_release_resources(sc);
462 BFE_UNLOCK(sc);
463 mtx_destroy(&sc->bfe_mtx);
464
465 return (0);
466 }
467
468 /*
469 * Stop all chip I/O so that the kernel's probe routines don't
470 * get confused by errant DMAs when rebooting.
471 */
472 static void
473 bfe_shutdown(device_t dev)
474 {
475 struct bfe_softc *sc;
476
477 sc = device_get_softc(dev);
478 BFE_LOCK(sc);
479 bfe_stop(sc);
480
481 BFE_UNLOCK(sc);
482 return;
483 }
484
485 static int
486 bfe_miibus_readreg(device_t dev, int phy, int reg)
487 {
488 struct bfe_softc *sc;
489 u_int32_t ret;
490
491 sc = device_get_softc(dev);
492 if(phy != sc->bfe_phyaddr)
493 return (0);
494 bfe_readphy(sc, reg, &ret);
495
496 return (ret);
497 }
498
499 static int
500 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
501 {
502 struct bfe_softc *sc;
503
504 sc = device_get_softc(dev);
505 if(phy != sc->bfe_phyaddr)
506 return (0);
507 bfe_writephy(sc, reg, val);
508
509 return (0);
510 }
511
512 static void
513 bfe_miibus_statchg(device_t dev)
514 {
515 return;
516 }
517
518 static void
519 bfe_tx_ring_free(struct bfe_softc *sc)
520 {
521 int i;
522
523 for(i = 0; i < BFE_TX_LIST_CNT; i++) {
524 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
525 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
526 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
527 bus_dmamap_unload(sc->bfe_tag,
528 sc->bfe_tx_ring[i].bfe_map);
529 }
530 }
531 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
532 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
533 }
534
535 static void
536 bfe_rx_ring_free(struct bfe_softc *sc)
537 {
538 int i;
539
540 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
541 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
542 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
543 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
544 bus_dmamap_unload(sc->bfe_tag,
545 sc->bfe_rx_ring[i].bfe_map);
546 }
547 }
548 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
549 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
550 }
551
552 static int
553 bfe_list_rx_init(struct bfe_softc *sc)
554 {
555 int i;
556
557 for(i = 0; i < BFE_RX_LIST_CNT; i++) {
558 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS)
559 return (ENOBUFS);
560 }
561
562 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
563 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
564
565 sc->bfe_rx_cons = 0;
566
567 return (0);
568 }
569
570 static int
571 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m)
572 {
573 struct bfe_rxheader *rx_header;
574 struct bfe_desc *d;
575 struct bfe_data *r;
576 u_int32_t ctrl;
577
578 if ((c < 0) || (c >= BFE_RX_LIST_CNT))
579 return (EINVAL);
580
581 if(m == NULL) {
582 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
583 if(m == NULL)
584 return (ENOBUFS);
585 m->m_len = m->m_pkthdr.len = MCLBYTES;
586 }
587 else
588 m->m_data = m->m_ext.ext_buf;
589
590 rx_header = mtod(m, struct bfe_rxheader *);
591 rx_header->len = 0;
592 rx_header->flags = 0;
593
594 /* Map the mbuf into DMA */
595 sc->bfe_rx_cnt = c;
596 d = &sc->bfe_rx_list[c];
597 r = &sc->bfe_rx_ring[c];
598 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *),
599 MCLBYTES, bfe_dma_map_desc, d, 0);
600 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE);
601
602 ctrl = ETHER_MAX_LEN + 32;
603
604 if(c == BFE_RX_LIST_CNT - 1)
605 ctrl |= BFE_DESC_EOT;
606
607 d->bfe_ctrl = ctrl;
608 r->bfe_mbuf = m;
609 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
610 return (0);
611 }
612
613 static void
614 bfe_get_config(struct bfe_softc *sc)
615 {
616 u_int8_t eeprom[128];
617
618 bfe_read_eeprom(sc, eeprom);
619
620 sc->bfe_enaddr[0] = eeprom[79];
621 sc->bfe_enaddr[1] = eeprom[78];
622 sc->bfe_enaddr[2] = eeprom[81];
623 sc->bfe_enaddr[3] = eeprom[80];
624 sc->bfe_enaddr[4] = eeprom[83];
625 sc->bfe_enaddr[5] = eeprom[82];
626
627 sc->bfe_phyaddr = eeprom[90] & 0x1f;
628 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
629
630 sc->bfe_core_unit = 0;
631 sc->bfe_dma_offset = BFE_PCI_DMA;
632 }
633
634 static void
635 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores)
636 {
637 u_int32_t bar_orig, pci_rev, val;
638
639 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
640 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
641 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
642
643 val = CSR_READ_4(sc, BFE_SBINTVEC);
644 val |= cores;
645 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
646
647 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
648 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
649 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
650
651 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
652 }
653
654 static void
655 bfe_clear_stats(struct bfe_softc *sc)
656 {
657 u_long reg;
658
659 BFE_LOCK_ASSERT(sc);
660
661 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
662 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
663 CSR_READ_4(sc, reg);
664 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
665 CSR_READ_4(sc, reg);
666 }
667
668 static int
669 bfe_resetphy(struct bfe_softc *sc)
670 {
671 u_int32_t val;
672
673 bfe_writephy(sc, 0, BMCR_RESET);
674 DELAY(100);
675 bfe_readphy(sc, 0, &val);
676 if (val & BMCR_RESET) {
677 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit);
678 return (ENXIO);
679 }
680 return (0);
681 }
682
683 static void
684 bfe_chip_halt(struct bfe_softc *sc)
685 {
686 BFE_LOCK_ASSERT(sc);
687 /* disable interrupts - not that it actually does..*/
688 CSR_WRITE_4(sc, BFE_IMASK, 0);
689 CSR_READ_4(sc, BFE_IMASK);
690
691 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
692 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
693
694 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
695 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
696 DELAY(10);
697 }
698
699 static void
700 bfe_chip_reset(struct bfe_softc *sc)
701 {
702 u_int32_t val;
703
704 BFE_LOCK_ASSERT(sc);
705
706 /* Set the interrupt vector for the enet core */
707 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
708
709 /* is core up? */
710 val = CSR_READ_4(sc, BFE_SBTMSLOW) &
711 (BFE_RESET | BFE_REJECT | BFE_CLOCK);
712 if (val == BFE_CLOCK) {
713 /* It is, so shut it down */
714 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
715 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
716 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
717 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
718 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
719 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
720 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE,
721 100, 0);
722 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
723 sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
724 }
725
726 bfe_core_reset(sc);
727 bfe_clear_stats(sc);
728
729 /*
730 * We want the phy registers to be accessible even when
731 * the driver is "downed" so initialize MDC preamble, frequency,
732 * and whether internal or external phy here.
733 */
734
735 /* 4402 has 62.5Mhz SB clock and internal phy */
736 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
737
738 /* Internal or external PHY? */
739 val = CSR_READ_4(sc, BFE_DEVCTRL);
740 if(!(val & BFE_IPP))
741 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
742 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
743 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
744 DELAY(100);
745 }
746
747 /* Enable CRC32 generation and set proper LED modes */
748 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
749
750 /* Reset or clear powerdown control bit */
751 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
752
753 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
754 BFE_LAZY_FC_MASK));
755
756 /*
757 * We don't want lazy interrupts, so just send them at
758 * the end of a frame, please
759 */
760 BFE_OR(sc, BFE_RCV_LAZY, 0);
761
762 /* Set max lengths, accounting for VLAN tags */
763 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
764 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
765
766 /* Set watermark XXX - magic */
767 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
768
769 /*
770 * Initialise DMA channels
771 * - not forgetting dma addresses need to be added to BFE_PCI_DMA
772 */
773 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
774 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
775
776 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
777 BFE_RX_CTRL_ENABLE);
778 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
779
780 bfe_resetphy(sc);
781 bfe_setupphy(sc);
782 }
783
784 static void
785 bfe_core_disable(struct bfe_softc *sc)
786 {
787 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
788 return;
789
790 /*
791 * Set reject, wait for it set, then wait for the core to stop
792 * being busy, then set reset and reject and enable the clocks.
793 */
794 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
795 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
796 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
797 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
798 BFE_RESET));
799 CSR_READ_4(sc, BFE_SBTMSLOW);
800 DELAY(10);
801 /* Leave reset and reject set */
802 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
803 DELAY(10);
804 }
805
806 static void
807 bfe_core_reset(struct bfe_softc *sc)
808 {
809 u_int32_t val;
810
811 /* Disable the core */
812 bfe_core_disable(sc);
813
814 /* and bring it back up */
815 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
816 CSR_READ_4(sc, BFE_SBTMSLOW);
817 DELAY(10);
818
819 /* Chip bug, clear SERR, IB and TO if they are set. */
820 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
821 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
822 val = CSR_READ_4(sc, BFE_SBIMSTATE);
823 if (val & (BFE_IBE | BFE_TO))
824 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
825
826 /* Clear reset and allow it to move through the core */
827 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
828 CSR_READ_4(sc, BFE_SBTMSLOW);
829 DELAY(10);
830
831 /* Leave the clock set */
832 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
833 CSR_READ_4(sc, BFE_SBTMSLOW);
834 DELAY(10);
835 }
836
837 static void
838 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
839 {
840 u_int32_t val;
841
842 val = ((u_int32_t) data[2]) << 24;
843 val |= ((u_int32_t) data[3]) << 16;
844 val |= ((u_int32_t) data[4]) << 8;
845 val |= ((u_int32_t) data[5]);
846 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
847 val = (BFE_CAM_HI_VALID |
848 (((u_int32_t) data[0]) << 8) |
849 (((u_int32_t) data[1])));
850 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
851 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
852 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT)));
853 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
854 }
855
856 static void
857 bfe_set_rx_mode(struct bfe_softc *sc)
858 {
859 struct ifnet *ifp = sc->bfe_ifp;
860 struct ifmultiaddr *ifma;
861 u_int32_t val;
862 int i = 0;
863
864 val = CSR_READ_4(sc, BFE_RXCONF);
865
866 if (ifp->if_flags & IFF_PROMISC)
867 val |= BFE_RXCONF_PROMISC;
868 else
869 val &= ~BFE_RXCONF_PROMISC;
870
871 if (ifp->if_flags & IFF_BROADCAST)
872 val &= ~BFE_RXCONF_DBCAST;
873 else
874 val |= BFE_RXCONF_DBCAST;
875
876
877 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
878 bfe_cam_write(sc, IFP2ENADDR(sc->bfe_ifp), i++);
879
880 if (ifp->if_flags & IFF_ALLMULTI)
881 val |= BFE_RXCONF_ALLMULTI;
882 else {
883 val &= ~BFE_RXCONF_ALLMULTI;
884 IF_ADDR_LOCK(ifp);
885 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
886 if (ifma->ifma_addr->sa_family != AF_LINK)
887 continue;
888 bfe_cam_write(sc,
889 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++);
890 }
891 IF_ADDR_UNLOCK(ifp);
892 }
893
894 CSR_WRITE_4(sc, BFE_RXCONF, val);
895 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
896 }
897
898 static void
899 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
900 {
901 u_int32_t *ptr;
902
903 ptr = arg;
904 *ptr = segs->ds_addr;
905 }
906
907 static void
908 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error)
909 {
910 struct bfe_desc *d;
911
912 d = arg;
913 /* The chip needs all addresses to be added to BFE_PCI_DMA */
914 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA;
915 }
916
917 static void
918 bfe_release_resources(struct bfe_softc *sc)
919 {
920 device_t dev;
921 int i;
922
923 dev = sc->bfe_dev;
924
925 if (sc->bfe_vpd_prodname != NULL)
926 free(sc->bfe_vpd_prodname, M_DEVBUF);
927
928 if (sc->bfe_vpd_readonly != NULL)
929 free(sc->bfe_vpd_readonly, M_DEVBUF);
930
931 if (sc->bfe_intrhand != NULL)
932 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand);
933
934 if (sc->bfe_irq != NULL)
935 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq);
936
937 if (sc->bfe_res != NULL)
938 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res);
939
940 if (sc->bfe_ifp != NULL)
941 if_free(sc->bfe_ifp);
942
943 if(sc->bfe_tx_tag != NULL) {
944 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
945 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
946 sc->bfe_tx_map);
947 bus_dma_tag_destroy(sc->bfe_tx_tag);
948 sc->bfe_tx_tag = NULL;
949 }
950
951 if(sc->bfe_rx_tag != NULL) {
952 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
953 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
954 sc->bfe_rx_map);
955 bus_dma_tag_destroy(sc->bfe_rx_tag);
956 sc->bfe_rx_tag = NULL;
957 }
958
959 if(sc->bfe_tag != NULL) {
960 for(i = 0; i < BFE_TX_LIST_CNT; i++) {
961 bus_dmamap_destroy(sc->bfe_tag,
962 sc->bfe_tx_ring[i].bfe_map);
963 }
964 for(i = 0; i < BFE_RX_LIST_CNT; i++) {
965 bus_dmamap_destroy(sc->bfe_tag,
966 sc->bfe_rx_ring[i].bfe_map);
967 }
968 bus_dma_tag_destroy(sc->bfe_tag);
969 sc->bfe_tag = NULL;
970 }
971
972 if(sc->bfe_parent_tag != NULL)
973 bus_dma_tag_destroy(sc->bfe_parent_tag);
974
975 return;
976 }
977
978 static void
979 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data)
980 {
981 long i;
982 u_int16_t *ptr = (u_int16_t *)data;
983
984 for(i = 0; i < 128; i += 2)
985 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
986 }
987
988 static int
989 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit,
990 u_long timeout, const int clear)
991 {
992 u_long i;
993
994 for (i = 0; i < timeout; i++) {
995 u_int32_t val = CSR_READ_4(sc, reg);
996
997 if (clear && !(val & bit))
998 break;
999 if (!clear && (val & bit))
1000 break;
1001 DELAY(10);
1002 }
1003 if (i == timeout) {
1004 printf("bfe%d: BUG! Timeout waiting for bit %08x of register "
1005 "%x to %s.\n", sc->bfe_unit, bit, reg,
1006 (clear ? "clear" : "set"));
1007 return (-1);
1008 }
1009 return (0);
1010 }
1011
1012 static int
1013 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val)
1014 {
1015 int err;
1016
1017 /* Clear MII ISR */
1018 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1019 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1020 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
1021 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1022 (reg << BFE_MDIO_RA_SHIFT) |
1023 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
1024 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1025 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
1026
1027 return (err);
1028 }
1029
1030 static int
1031 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val)
1032 {
1033 int status;
1034
1035 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1036 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1037 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1038 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1039 (reg << BFE_MDIO_RA_SHIFT) |
1040 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1041 (val & BFE_MDIO_DATA_DATA)));
1042 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1043
1044 return (status);
1045 }
1046
1047 /*
1048 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1049 * twice
1050 */
1051 static int
1052 bfe_setupphy(struct bfe_softc *sc)
1053 {
1054 u_int32_t val;
1055
1056 /* Enable activity LED */
1057 bfe_readphy(sc, 26, &val);
1058 bfe_writephy(sc, 26, val & 0x7fff);
1059 bfe_readphy(sc, 26, &val);
1060
1061 /* Enable traffic meter LED mode */
1062 bfe_readphy(sc, 27, &val);
1063 bfe_writephy(sc, 27, val | (1 << 6));
1064
1065 return (0);
1066 }
1067
1068 static void
1069 bfe_stats_update(struct bfe_softc *sc)
1070 {
1071 u_long reg;
1072 u_int32_t *val;
1073
1074 val = &sc->bfe_hwstats.tx_good_octets;
1075 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) {
1076 *val++ += CSR_READ_4(sc, reg);
1077 }
1078 val = &sc->bfe_hwstats.rx_good_octets;
1079 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) {
1080 *val++ += CSR_READ_4(sc, reg);
1081 }
1082 }
1083
1084 static void
1085 bfe_txeof(struct bfe_softc *sc)
1086 {
1087 struct ifnet *ifp;
1088 int i, chipidx;
1089
1090 BFE_LOCK_ASSERT(sc);
1091
1092 ifp = sc->bfe_ifp;
1093
1094 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1095 chipidx /= sizeof(struct bfe_desc);
1096
1097 i = sc->bfe_tx_cons;
1098 /* Go through the mbufs and free those that have been transmitted */
1099 while(i != chipidx) {
1100 struct bfe_data *r = &sc->bfe_tx_ring[i];
1101 if(r->bfe_mbuf != NULL) {
1102 ifp->if_opackets++;
1103 m_freem(r->bfe_mbuf);
1104 r->bfe_mbuf = NULL;
1105 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1106 }
1107 sc->bfe_tx_cnt--;
1108 BFE_INC(i, BFE_TX_LIST_CNT);
1109 }
1110
1111 if(i != sc->bfe_tx_cons) {
1112 /* we freed up some mbufs */
1113 sc->bfe_tx_cons = i;
1114 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1115 }
1116 if(sc->bfe_tx_cnt == 0)
1117 ifp->if_timer = 0;
1118 else
1119 ifp->if_timer = 5;
1120 }
1121
1122 /* Pass a received packet up the stack */
1123 static void
1124 bfe_rxeof(struct bfe_softc *sc)
1125 {
1126 struct mbuf *m;
1127 struct ifnet *ifp;
1128 struct bfe_rxheader *rxheader;
1129 struct bfe_data *r;
1130 int cons;
1131 u_int32_t status, current, len, flags;
1132
1133 BFE_LOCK_ASSERT(sc);
1134 cons = sc->bfe_rx_cons;
1135 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1136 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1137
1138 ifp = sc->bfe_ifp;
1139
1140 while(current != cons) {
1141 r = &sc->bfe_rx_ring[cons];
1142 m = r->bfe_mbuf;
1143 rxheader = mtod(m, struct bfe_rxheader*);
1144 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTREAD);
1145 len = rxheader->len;
1146 r->bfe_mbuf = NULL;
1147
1148 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1149 flags = rxheader->flags;
1150
1151 len -= ETHER_CRC_LEN;
1152
1153 /* flag an error and try again */
1154 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
1155 ifp->if_ierrors++;
1156 if (flags & BFE_RX_FLAG_SERR)
1157 ifp->if_collisions++;
1158 bfe_list_newbuf(sc, cons, m);
1159 BFE_INC(cons, BFE_RX_LIST_CNT);
1160 continue;
1161 }
1162
1163 /* Go past the rx header */
1164 if (bfe_list_newbuf(sc, cons, NULL) == 0) {
1165 m_adj(m, BFE_RX_OFFSET);
1166 m->m_len = m->m_pkthdr.len = len;
1167 } else {
1168 bfe_list_newbuf(sc, cons, m);
1169 ifp->if_ierrors++;
1170 BFE_INC(cons, BFE_RX_LIST_CNT);
1171 continue;
1172 }
1173
1174 ifp->if_ipackets++;
1175 m->m_pkthdr.rcvif = ifp;
1176 BFE_UNLOCK(sc);
1177 (*ifp->if_input)(ifp, m);
1178 BFE_LOCK(sc);
1179
1180 BFE_INC(cons, BFE_RX_LIST_CNT);
1181 }
1182 sc->bfe_rx_cons = cons;
1183 }
1184
1185 static void
1186 bfe_intr(void *xsc)
1187 {
1188 struct bfe_softc *sc = xsc;
1189 struct ifnet *ifp;
1190 u_int32_t istat, imask, flag;
1191
1192 ifp = sc->bfe_ifp;
1193
1194 BFE_LOCK(sc);
1195
1196 istat = CSR_READ_4(sc, BFE_ISTAT);
1197 imask = CSR_READ_4(sc, BFE_IMASK);
1198
1199 /*
1200 * Defer unsolicited interrupts - This is necessary because setting the
1201 * chips interrupt mask register to 0 doesn't actually stop the
1202 * interrupts
1203 */
1204 istat &= imask;
1205 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1206 CSR_READ_4(sc, BFE_ISTAT);
1207
1208 /* not expecting this interrupt, disregard it */
1209 if(istat == 0) {
1210 BFE_UNLOCK(sc);
1211 return;
1212 }
1213
1214 if(istat & BFE_ISTAT_ERRORS) {
1215 flag = CSR_READ_4(sc, BFE_DMATX_STAT);
1216 if(flag & BFE_STAT_EMASK)
1217 ifp->if_oerrors++;
1218
1219 flag = CSR_READ_4(sc, BFE_DMARX_STAT);
1220 if(flag & BFE_RX_FLAG_ERRORS)
1221 ifp->if_ierrors++;
1222
1223 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1224 bfe_init_locked(sc);
1225 }
1226
1227 /* A packet was received */
1228 if(istat & BFE_ISTAT_RX)
1229 bfe_rxeof(sc);
1230
1231 /* A packet was sent */
1232 if(istat & BFE_ISTAT_TX)
1233 bfe_txeof(sc);
1234
1235 /* We have packets pending, fire them out */
1236 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1237 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1238 bfe_start_locked(ifp);
1239
1240 BFE_UNLOCK(sc);
1241 }
1242
1243 static int
1244 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
1245 {
1246 struct bfe_desc *d = NULL;
1247 struct bfe_data *r = NULL;
1248 struct mbuf *m;
1249 u_int32_t frag, cur, cnt = 0;
1250 int chainlen = 0;
1251
1252 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2)
1253 return (ENOBUFS);
1254
1255 /*
1256 * Count the number of frags in this chain to see if
1257 * we need to m_defrag. Since the descriptor list is shared
1258 * by all packets, we'll m_defrag long chains so that they
1259 * do not use up the entire list, even if they would fit.
1260 */
1261 for(m = m_head; m != NULL; m = m->m_next)
1262 chainlen++;
1263
1264
1265 if ((chainlen > BFE_TX_LIST_CNT / 4) ||
1266 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) {
1267 m = m_defrag(m_head, M_DONTWAIT);
1268 if (m == NULL)
1269 return (ENOBUFS);
1270 m_head = m;
1271 }
1272
1273 /*
1274 * Start packing the mbufs in this chain into
1275 * the fragment pointers. Stop when we run out
1276 * of fragments or hit the end of the mbuf chain.
1277 */
1278 m = m_head;
1279 cur = frag = *txidx;
1280 cnt = 0;
1281
1282 for(m = m_head; m != NULL; m = m->m_next) {
1283 if(m->m_len != 0) {
1284 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2)
1285 return (ENOBUFS);
1286
1287 d = &sc->bfe_tx_list[cur];
1288 r = &sc->bfe_tx_ring[cur];
1289 d->bfe_ctrl = BFE_DESC_LEN & m->m_len;
1290 /* always intterupt on completion */
1291 d->bfe_ctrl |= BFE_DESC_IOC;
1292 if(cnt == 0)
1293 /* Set start of frame */
1294 d->bfe_ctrl |= BFE_DESC_SOF;
1295 if(cur == BFE_TX_LIST_CNT - 1)
1296 /*
1297 * Tell the chip to wrap to the start of
1298 * the descriptor list
1299 */
1300 d->bfe_ctrl |= BFE_DESC_EOT;
1301
1302 bus_dmamap_load(sc->bfe_tag,
1303 r->bfe_map, mtod(m, void*), m->m_len,
1304 bfe_dma_map_desc, d, 0);
1305 bus_dmamap_sync(sc->bfe_tag, r->bfe_map,
1306 BUS_DMASYNC_PREWRITE);
1307
1308 frag = cur;
1309 BFE_INC(cur, BFE_TX_LIST_CNT);
1310 cnt++;
1311 }
1312 }
1313
1314 if (m != NULL)
1315 return (ENOBUFS);
1316
1317 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF;
1318 sc->bfe_tx_ring[frag].bfe_mbuf = m_head;
1319 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
1320
1321 *txidx = cur;
1322 sc->bfe_tx_cnt += cnt;
1323 return (0);
1324 }
1325
1326 /*
1327 * Set up to transmit a packet.
1328 */
1329 static void
1330 bfe_start(struct ifnet *ifp)
1331 {
1332 BFE_LOCK((struct bfe_softc *)ifp->if_softc);
1333 bfe_start_locked(ifp);
1334 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc);
1335 }
1336
1337 /*
1338 * Set up to transmit a packet. The softc is already locked.
1339 */
1340 static void
1341 bfe_start_locked(struct ifnet *ifp)
1342 {
1343 struct bfe_softc *sc;
1344 struct mbuf *m_head = NULL;
1345 int idx, queued = 0;
1346
1347 sc = ifp->if_softc;
1348 idx = sc->bfe_tx_prod;
1349
1350 BFE_LOCK_ASSERT(sc);
1351
1352 /*
1353 * Not much point trying to send if the link is down
1354 * or we have nothing to send.
1355 */
1356 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10)
1357 return;
1358
1359 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1360 return;
1361
1362 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) {
1363 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1364 if(m_head == NULL)
1365 break;
1366
1367 /*
1368 * Pack the data into the tx ring. If we dont have
1369 * enough room, let the chip drain the ring.
1370 */
1371 if(bfe_encap(sc, m_head, &idx)) {
1372 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1373 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1374 break;
1375 }
1376
1377 queued++;
1378
1379 /*
1380 * If there's a BPF listener, bounce a copy of this frame
1381 * to him.
1382 */
1383 BPF_MTAP(ifp, m_head);
1384 }
1385
1386 if (queued) {
1387 sc->bfe_tx_prod = idx;
1388 /* Transmit - twice due to apparent hardware bug */
1389 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1390 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1391
1392 /*
1393 * Set a timeout in case the chip goes out to lunch.
1394 */
1395 ifp->if_timer = 5;
1396 }
1397 }
1398
1399 static void
1400 bfe_init(void *xsc)
1401 {
1402 BFE_LOCK((struct bfe_softc *)xsc);
1403 bfe_init_locked(xsc);
1404 BFE_UNLOCK((struct bfe_softc *)xsc);
1405 }
1406
1407 static void
1408 bfe_init_locked(void *xsc)
1409 {
1410 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1411 struct ifnet *ifp = sc->bfe_ifp;
1412
1413 BFE_LOCK_ASSERT(sc);
1414
1415 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1416 return;
1417
1418 bfe_stop(sc);
1419 bfe_chip_reset(sc);
1420
1421 if (bfe_list_rx_init(sc) == ENOBUFS) {
1422 printf("bfe%d: bfe_init: Not enough memory for list buffers\n",
1423 sc->bfe_unit);
1424 bfe_stop(sc);
1425 return;
1426 }
1427
1428 bfe_set_rx_mode(sc);
1429
1430 /* Enable the chip and core */
1431 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1432 /* Enable interrupts */
1433 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1434
1435 bfe_ifmedia_upd(ifp);
1436 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1437 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1438
1439 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz);
1440 }
1441
1442 /*
1443 * Set media options.
1444 */
1445 static int
1446 bfe_ifmedia_upd(struct ifnet *ifp)
1447 {
1448 struct bfe_softc *sc;
1449 struct mii_data *mii;
1450
1451 sc = ifp->if_softc;
1452
1453 mii = device_get_softc(sc->bfe_miibus);
1454 sc->bfe_link = 0;
1455 if (mii->mii_instance) {
1456 struct mii_softc *miisc;
1457 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1458 miisc = LIST_NEXT(miisc, mii_list))
1459 mii_phy_reset(miisc);
1460 }
1461 mii_mediachg(mii);
1462
1463 return (0);
1464 }
1465
1466 /*
1467 * Report current media status.
1468 */
1469 static void
1470 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1471 {
1472 struct bfe_softc *sc = ifp->if_softc;
1473 struct mii_data *mii;
1474
1475 mii = device_get_softc(sc->bfe_miibus);
1476 mii_pollstat(mii);
1477 ifmr->ifm_active = mii->mii_media_active;
1478 ifmr->ifm_status = mii->mii_media_status;
1479 }
1480
1481 static int
1482 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1483 {
1484 struct bfe_softc *sc = ifp->if_softc;
1485 struct ifreq *ifr = (struct ifreq *) data;
1486 struct mii_data *mii;
1487 int error = 0;
1488
1489 switch(command) {
1490 case SIOCSIFFLAGS:
1491 BFE_LOCK(sc);
1492 if(ifp->if_flags & IFF_UP)
1493 if(ifp->if_drv_flags & IFF_DRV_RUNNING)
1494 bfe_set_rx_mode(sc);
1495 else
1496 bfe_init_locked(sc);
1497 else if(ifp->if_drv_flags & IFF_DRV_RUNNING)
1498 bfe_stop(sc);
1499 BFE_UNLOCK(sc);
1500 break;
1501 case SIOCADDMULTI:
1502 case SIOCDELMULTI:
1503 BFE_LOCK(sc);
1504 if(ifp->if_drv_flags & IFF_DRV_RUNNING)
1505 bfe_set_rx_mode(sc);
1506 BFE_UNLOCK(sc);
1507 break;
1508 case SIOCGIFMEDIA:
1509 case SIOCSIFMEDIA:
1510 mii = device_get_softc(sc->bfe_miibus);
1511 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1512 command);
1513 break;
1514 default:
1515 error = ether_ioctl(ifp, command, data);
1516 break;
1517 }
1518
1519 return (error);
1520 }
1521
1522 static void
1523 bfe_watchdog(struct ifnet *ifp)
1524 {
1525 struct bfe_softc *sc;
1526
1527 sc = ifp->if_softc;
1528
1529 BFE_LOCK(sc);
1530
1531 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit);
1532
1533 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1534 bfe_init_locked(sc);
1535
1536 ifp->if_oerrors++;
1537
1538 BFE_UNLOCK(sc);
1539 }
1540
1541 static void
1542 bfe_tick(void *xsc)
1543 {
1544 struct bfe_softc *sc = xsc;
1545 struct mii_data *mii;
1546
1547 if (sc == NULL)
1548 return;
1549
1550 BFE_LOCK(sc);
1551
1552 mii = device_get_softc(sc->bfe_miibus);
1553
1554 bfe_stats_update(sc);
1555 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz);
1556
1557 if(sc->bfe_link) {
1558 BFE_UNLOCK(sc);
1559 return;
1560 }
1561
1562 mii_tick(mii);
1563 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE &&
1564 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1565 sc->bfe_link++;
1566
1567 BFE_UNLOCK(sc);
1568 }
1569
1570 /*
1571 * Stop the adapter and free any mbufs allocated to the
1572 * RX and TX lists.
1573 */
1574 static void
1575 bfe_stop(struct bfe_softc *sc)
1576 {
1577 struct ifnet *ifp;
1578
1579 BFE_LOCK_ASSERT(sc);
1580
1581 untimeout(bfe_tick, sc, sc->bfe_stat_ch);
1582
1583 ifp = sc->bfe_ifp;
1584
1585 bfe_chip_halt(sc);
1586 bfe_tx_ring_free(sc);
1587 bfe_rx_ring_free(sc);
1588
1589 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1590 }
Cache object: afe3b83ec7772136713e4399d0151ade
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