FreeBSD/Linux Kernel Cross Reference
sys/dev/bfe/if_bfe.c
1 /*-
2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
3 * and Duncan Barclay<dmlb@dmlb.org>
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD: releng/6.2/sys/dev/bfe/if_bfe.c 159717 2006-06-18 06:23:14Z silby $");
30
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/sockio.h>
34 #include <sys/mbuf.h>
35 #include <sys/malloc.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
38 #include <sys/socket.h>
39 #include <sys/queue.h>
40
41 #include <net/if.h>
42 #include <net/if_arp.h>
43 #include <net/ethernet.h>
44 #include <net/if_dl.h>
45 #include <net/if_media.h>
46
47 #include <net/bpf.h>
48
49 #include <net/if_types.h>
50 #include <net/if_vlan_var.h>
51
52 #include <netinet/in_systm.h>
53 #include <netinet/in.h>
54 #include <netinet/ip.h>
55
56 #include <machine/bus.h>
57 #include <machine/resource.h>
58 #include <sys/bus.h>
59 #include <sys/rman.h>
60
61 #include <dev/mii/mii.h>
62 #include <dev/mii/miivar.h>
63 #include "miidevs.h"
64
65 #include <dev/pci/pcireg.h>
66 #include <dev/pci/pcivar.h>
67
68 #include <dev/bfe/if_bfereg.h>
69
70 MODULE_DEPEND(bfe, pci, 1, 1, 1);
71 MODULE_DEPEND(bfe, ether, 1, 1, 1);
72 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
73
74 /* "controller miibus0" required. See GENERIC if you get errors here. */
75 #include "miibus_if.h"
76
77 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
78
79 static struct bfe_type bfe_devs[] = {
80 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401,
81 "Broadcom BCM4401 Fast Ethernet" },
82 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0,
83 "Broadcom BCM4401-B0 Fast Ethernet" },
84 { 0, 0, NULL }
85 };
86
87 static int bfe_probe (device_t);
88 static int bfe_attach (device_t);
89 static int bfe_detach (device_t);
90 static void bfe_release_resources (struct bfe_softc *);
91 static void bfe_intr (void *);
92 static void bfe_start (struct ifnet *);
93 static void bfe_start_locked (struct ifnet *);
94 static int bfe_ioctl (struct ifnet *, u_long, caddr_t);
95 static void bfe_init (void *);
96 static void bfe_init_locked (void *);
97 static void bfe_stop (struct bfe_softc *);
98 static void bfe_watchdog (struct ifnet *);
99 static void bfe_shutdown (device_t);
100 static void bfe_tick (void *);
101 static void bfe_txeof (struct bfe_softc *);
102 static void bfe_rxeof (struct bfe_softc *);
103 static void bfe_set_rx_mode (struct bfe_softc *);
104 static int bfe_list_rx_init (struct bfe_softc *);
105 static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*);
106 static void bfe_rx_ring_free (struct bfe_softc *);
107
108 static void bfe_pci_setup (struct bfe_softc *, u_int32_t);
109 static int bfe_ifmedia_upd (struct ifnet *);
110 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *);
111 static int bfe_miibus_readreg (device_t, int, int);
112 static int bfe_miibus_writereg (device_t, int, int, int);
113 static void bfe_miibus_statchg (device_t);
114 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t,
115 u_long, const int);
116 static void bfe_get_config (struct bfe_softc *sc);
117 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *);
118 static void bfe_stats_update (struct bfe_softc *);
119 static void bfe_clear_stats (struct bfe_softc *);
120 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*);
121 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t);
122 static int bfe_resetphy (struct bfe_softc *);
123 static int bfe_setupphy (struct bfe_softc *);
124 static void bfe_chip_reset (struct bfe_softc *);
125 static void bfe_chip_halt (struct bfe_softc *);
126 static void bfe_core_reset (struct bfe_softc *);
127 static void bfe_core_disable (struct bfe_softc *);
128 static int bfe_dma_alloc (device_t);
129 static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int);
130 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int);
131 static void bfe_cam_write (struct bfe_softc *, u_char *, int);
132
133 static device_method_t bfe_methods[] = {
134 /* Device interface */
135 DEVMETHOD(device_probe, bfe_probe),
136 DEVMETHOD(device_attach, bfe_attach),
137 DEVMETHOD(device_detach, bfe_detach),
138 DEVMETHOD(device_shutdown, bfe_shutdown),
139
140 /* bus interface */
141 DEVMETHOD(bus_print_child, bus_generic_print_child),
142 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
143
144 /* MII interface */
145 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
146 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
147 DEVMETHOD(miibus_statchg, bfe_miibus_statchg),
148
149 { 0, 0 }
150 };
151
152 static driver_t bfe_driver = {
153 "bfe",
154 bfe_methods,
155 sizeof(struct bfe_softc)
156 };
157
158 static devclass_t bfe_devclass;
159
160 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
161 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
162
163 /*
164 * Probe for a Broadcom 4401 chip.
165 */
166 static int
167 bfe_probe(device_t dev)
168 {
169 struct bfe_type *t;
170 struct bfe_softc *sc;
171
172 t = bfe_devs;
173
174 sc = device_get_softc(dev);
175 bzero(sc, sizeof(struct bfe_softc));
176 sc->bfe_unit = device_get_unit(dev);
177 sc->bfe_dev = dev;
178
179 while(t->bfe_name != NULL) {
180 if ((pci_get_vendor(dev) == t->bfe_vid) &&
181 (pci_get_device(dev) == t->bfe_did)) {
182 device_set_desc_copy(dev, t->bfe_name);
183 return (BUS_PROBE_DEFAULT);
184 }
185 t++;
186 }
187
188 return (ENXIO);
189 }
190
191 static int
192 bfe_dma_alloc(device_t dev)
193 {
194 struct bfe_softc *sc;
195 int error, i;
196
197 sc = device_get_softc(dev);
198
199 /*
200 * parent tag. Apparently the chip cannot handle any DMA address
201 * greater than 1GB.
202 */
203 error = bus_dma_tag_create(NULL, /* parent */
204 4096, 0, /* alignment, boundary */
205 0x3FFFFFFF, /* lowaddr */
206 BUS_SPACE_MAXADDR, /* highaddr */
207 NULL, NULL, /* filter, filterarg */
208 MAXBSIZE, /* maxsize */
209 BUS_SPACE_UNRESTRICTED, /* num of segments */
210 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */
211 0, /* flags */
212 NULL, NULL, /* lockfunc, lockarg */
213 &sc->bfe_parent_tag);
214
215 /* tag for TX ring */
216 error = bus_dma_tag_create(sc->bfe_parent_tag,
217 4096, 0,
218 BUS_SPACE_MAXADDR,
219 BUS_SPACE_MAXADDR,
220 NULL, NULL,
221 BFE_TX_LIST_SIZE,
222 1,
223 BUS_SPACE_MAXSIZE_32BIT,
224 0,
225 NULL, NULL,
226 &sc->bfe_tx_tag);
227
228 if (error) {
229 device_printf(dev, "could not allocate dma tag\n");
230 return (ENOMEM);
231 }
232
233 /* tag for RX ring */
234 error = bus_dma_tag_create(sc->bfe_parent_tag,
235 4096, 0,
236 BUS_SPACE_MAXADDR,
237 BUS_SPACE_MAXADDR,
238 NULL, NULL,
239 BFE_RX_LIST_SIZE,
240 1,
241 BUS_SPACE_MAXSIZE_32BIT,
242 0,
243 NULL, NULL,
244 &sc->bfe_rx_tag);
245
246 if (error) {
247 device_printf(dev, "could not allocate dma tag\n");
248 return (ENOMEM);
249 }
250
251 /* tag for mbufs */
252 error = bus_dma_tag_create(sc->bfe_parent_tag,
253 ETHER_ALIGN, 0,
254 BUS_SPACE_MAXADDR,
255 BUS_SPACE_MAXADDR,
256 NULL, NULL,
257 MCLBYTES,
258 1,
259 BUS_SPACE_MAXSIZE_32BIT,
260 BUS_DMA_ALLOCNOW,
261 NULL, NULL,
262 &sc->bfe_tag);
263
264 if (error) {
265 device_printf(dev, "could not allocate dma tag\n");
266 return (ENOMEM);
267 }
268
269 /* pre allocate dmamaps for RX list */
270 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
271 error = bus_dmamap_create(sc->bfe_tag, 0,
272 &sc->bfe_rx_ring[i].bfe_map);
273 if (error) {
274 device_printf(dev, "cannot create DMA map for RX\n");
275 return (ENOMEM);
276 }
277 }
278
279 /* pre allocate dmamaps for TX list */
280 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
281 error = bus_dmamap_create(sc->bfe_tag, 0,
282 &sc->bfe_tx_ring[i].bfe_map);
283 if (error) {
284 device_printf(dev, "cannot create DMA map for TX\n");
285 return (ENOMEM);
286 }
287 }
288
289 /* Alloc dma for rx ring */
290 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
291 BUS_DMA_NOWAIT, &sc->bfe_rx_map);
292
293 if(error)
294 return (ENOMEM);
295
296 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
297 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
298 sc->bfe_rx_list, sizeof(struct bfe_desc),
299 bfe_dma_map, &sc->bfe_rx_dma, BUS_DMA_NOWAIT);
300
301 if(error)
302 return (ENOMEM);
303
304 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
305
306 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
307 BUS_DMA_NOWAIT, &sc->bfe_tx_map);
308 if (error)
309 return (ENOMEM);
310
311
312 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
313 sc->bfe_tx_list, sizeof(struct bfe_desc),
314 bfe_dma_map, &sc->bfe_tx_dma, BUS_DMA_NOWAIT);
315 if(error)
316 return (ENOMEM);
317
318 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
319 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
320
321 return (0);
322 }
323
324 static int
325 bfe_attach(device_t dev)
326 {
327 struct ifnet *ifp = NULL;
328 struct bfe_softc *sc;
329 int unit, error = 0, rid;
330
331 sc = device_get_softc(dev);
332 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
333 MTX_DEF);
334
335 unit = device_get_unit(dev);
336 sc->bfe_dev = dev;
337 sc->bfe_unit = unit;
338
339 /*
340 * Map control/status registers.
341 */
342 pci_enable_busmaster(dev);
343
344 rid = BFE_PCI_MEMLO;
345 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
346 RF_ACTIVE);
347 if (sc->bfe_res == NULL) {
348 printf ("bfe%d: couldn't map memory\n", unit);
349 error = ENXIO;
350 goto fail;
351 }
352
353 sc->bfe_btag = rman_get_bustag(sc->bfe_res);
354 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res);
355 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res);
356
357 /* Allocate interrupt */
358 rid = 0;
359
360 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
361 RF_SHAREABLE | RF_ACTIVE);
362 if (sc->bfe_irq == NULL) {
363 printf("bfe%d: couldn't map interrupt\n", unit);
364 error = ENXIO;
365 goto fail;
366 }
367
368 if (bfe_dma_alloc(dev)) {
369 printf("bfe%d: failed to allocate DMA resources\n",
370 sc->bfe_unit);
371 bfe_release_resources(sc);
372 error = ENXIO;
373 goto fail;
374 }
375
376 /* Set up ifnet structure */
377 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER);
378 if (ifp == NULL) {
379 printf("bfe%d: failed to if_alloc()\n", sc->bfe_unit);
380 error = ENOSPC;
381 goto fail;
382 }
383 ifp->if_softc = sc;
384 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
385 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
386 ifp->if_ioctl = bfe_ioctl;
387 ifp->if_start = bfe_start;
388 ifp->if_watchdog = bfe_watchdog;
389 ifp->if_init = bfe_init;
390 ifp->if_mtu = ETHERMTU;
391 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN);
392 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN;
393 IFQ_SET_READY(&ifp->if_snd);
394
395 bfe_get_config(sc);
396
397 /* Reset the chip and turn on the PHY */
398 BFE_LOCK(sc);
399 bfe_chip_reset(sc);
400 BFE_UNLOCK(sc);
401
402 if (mii_phy_probe(dev, &sc->bfe_miibus,
403 bfe_ifmedia_upd, bfe_ifmedia_sts)) {
404 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit);
405 error = ENXIO;
406 goto fail;
407 }
408
409 ether_ifattach(ifp, sc->bfe_enaddr);
410 callout_handle_init(&sc->bfe_stat_ch);
411
412 /*
413 * Tell the upper layer(s) we support long frames.
414 */
415 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
416 ifp->if_capabilities |= IFCAP_VLAN_MTU;
417 ifp->if_capenable |= IFCAP_VLAN_MTU;
418
419 /*
420 * Hook interrupt last to avoid having to lock softc
421 */
422 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE,
423 bfe_intr, sc, &sc->bfe_intrhand);
424
425 if (error) {
426 bfe_release_resources(sc);
427 printf("bfe%d: couldn't set up irq\n", unit);
428 goto fail;
429 }
430 fail:
431 if (error)
432 bfe_release_resources(sc);
433 return (error);
434 }
435
436 static int
437 bfe_detach(device_t dev)
438 {
439 struct bfe_softc *sc;
440 struct ifnet *ifp;
441
442 sc = device_get_softc(dev);
443
444 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized"));
445 BFE_LOCK(sc);
446
447 ifp = sc->bfe_ifp;
448
449 if (device_is_attached(dev)) {
450 bfe_stop(sc);
451 ether_ifdetach(ifp);
452 }
453
454 bfe_chip_reset(sc);
455
456 bus_generic_detach(dev);
457 if(sc->bfe_miibus != NULL)
458 device_delete_child(dev, sc->bfe_miibus);
459
460 bfe_release_resources(sc);
461 BFE_UNLOCK(sc);
462 mtx_destroy(&sc->bfe_mtx);
463
464 return (0);
465 }
466
467 /*
468 * Stop all chip I/O so that the kernel's probe routines don't
469 * get confused by errant DMAs when rebooting.
470 */
471 static void
472 bfe_shutdown(device_t dev)
473 {
474 struct bfe_softc *sc;
475
476 sc = device_get_softc(dev);
477 BFE_LOCK(sc);
478 bfe_stop(sc);
479
480 BFE_UNLOCK(sc);
481 return;
482 }
483
484 static int
485 bfe_miibus_readreg(device_t dev, int phy, int reg)
486 {
487 struct bfe_softc *sc;
488 u_int32_t ret;
489
490 sc = device_get_softc(dev);
491 if(phy != sc->bfe_phyaddr)
492 return (0);
493 bfe_readphy(sc, reg, &ret);
494
495 return (ret);
496 }
497
498 static int
499 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
500 {
501 struct bfe_softc *sc;
502
503 sc = device_get_softc(dev);
504 if(phy != sc->bfe_phyaddr)
505 return (0);
506 bfe_writephy(sc, reg, val);
507
508 return (0);
509 }
510
511 static void
512 bfe_miibus_statchg(device_t dev)
513 {
514 return;
515 }
516
517 static void
518 bfe_tx_ring_free(struct bfe_softc *sc)
519 {
520 int i;
521
522 for(i = 0; i < BFE_TX_LIST_CNT; i++) {
523 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
524 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
525 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
526 bus_dmamap_unload(sc->bfe_tag,
527 sc->bfe_tx_ring[i].bfe_map);
528 }
529 }
530 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
531 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
532 }
533
534 static void
535 bfe_rx_ring_free(struct bfe_softc *sc)
536 {
537 int i;
538
539 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
540 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
541 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
542 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
543 bus_dmamap_unload(sc->bfe_tag,
544 sc->bfe_rx_ring[i].bfe_map);
545 }
546 }
547 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
548 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
549 }
550
551 static int
552 bfe_list_rx_init(struct bfe_softc *sc)
553 {
554 int i;
555
556 for(i = 0; i < BFE_RX_LIST_CNT; i++) {
557 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS)
558 return (ENOBUFS);
559 }
560
561 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
562 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
563
564 sc->bfe_rx_cons = 0;
565
566 return (0);
567 }
568
569 static int
570 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m)
571 {
572 struct bfe_rxheader *rx_header;
573 struct bfe_desc *d;
574 struct bfe_data *r;
575 u_int32_t ctrl;
576 int error;
577
578 if ((c < 0) || (c >= BFE_RX_LIST_CNT))
579 return (EINVAL);
580
581 if(m == NULL) {
582 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
583 if(m == NULL)
584 return (ENOBUFS);
585 m->m_len = m->m_pkthdr.len = MCLBYTES;
586 }
587 else
588 m->m_data = m->m_ext.ext_buf;
589
590 rx_header = mtod(m, struct bfe_rxheader *);
591 rx_header->len = 0;
592 rx_header->flags = 0;
593
594 /* Map the mbuf into DMA */
595 sc->bfe_rx_cnt = c;
596 d = &sc->bfe_rx_list[c];
597 r = &sc->bfe_rx_ring[c];
598 error = bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *),
599 MCLBYTES, bfe_dma_map_desc, d, BUS_DMA_NOWAIT);
600 if (error)
601 printf("Serious error: bfe failed to map RX buffer\n");
602 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE);
603
604 ctrl = ETHER_MAX_LEN + 32;
605
606 if(c == BFE_RX_LIST_CNT - 1)
607 ctrl |= BFE_DESC_EOT;
608
609 d->bfe_ctrl = ctrl;
610 r->bfe_mbuf = m;
611 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
612 return (0);
613 }
614
615 static void
616 bfe_get_config(struct bfe_softc *sc)
617 {
618 u_int8_t eeprom[128];
619
620 bfe_read_eeprom(sc, eeprom);
621
622 sc->bfe_enaddr[0] = eeprom[79];
623 sc->bfe_enaddr[1] = eeprom[78];
624 sc->bfe_enaddr[2] = eeprom[81];
625 sc->bfe_enaddr[3] = eeprom[80];
626 sc->bfe_enaddr[4] = eeprom[83];
627 sc->bfe_enaddr[5] = eeprom[82];
628
629 sc->bfe_phyaddr = eeprom[90] & 0x1f;
630 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
631
632 sc->bfe_core_unit = 0;
633 sc->bfe_dma_offset = BFE_PCI_DMA;
634 }
635
636 static void
637 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores)
638 {
639 u_int32_t bar_orig, pci_rev, val;
640
641 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
642 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
643 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
644
645 val = CSR_READ_4(sc, BFE_SBINTVEC);
646 val |= cores;
647 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
648
649 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
650 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
651 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
652
653 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
654 }
655
656 static void
657 bfe_clear_stats(struct bfe_softc *sc)
658 {
659 u_long reg;
660
661 BFE_LOCK_ASSERT(sc);
662
663 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
664 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
665 CSR_READ_4(sc, reg);
666 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
667 CSR_READ_4(sc, reg);
668 }
669
670 static int
671 bfe_resetphy(struct bfe_softc *sc)
672 {
673 u_int32_t val;
674
675 bfe_writephy(sc, 0, BMCR_RESET);
676 DELAY(100);
677 bfe_readphy(sc, 0, &val);
678 if (val & BMCR_RESET) {
679 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit);
680 return (ENXIO);
681 }
682 return (0);
683 }
684
685 static void
686 bfe_chip_halt(struct bfe_softc *sc)
687 {
688 BFE_LOCK_ASSERT(sc);
689 /* disable interrupts - not that it actually does..*/
690 CSR_WRITE_4(sc, BFE_IMASK, 0);
691 CSR_READ_4(sc, BFE_IMASK);
692
693 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
694 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
695
696 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
697 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
698 DELAY(10);
699 }
700
701 static void
702 bfe_chip_reset(struct bfe_softc *sc)
703 {
704 u_int32_t val;
705
706 BFE_LOCK_ASSERT(sc);
707
708 /* Set the interrupt vector for the enet core */
709 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
710
711 /* is core up? */
712 val = CSR_READ_4(sc, BFE_SBTMSLOW) &
713 (BFE_RESET | BFE_REJECT | BFE_CLOCK);
714 if (val == BFE_CLOCK) {
715 /* It is, so shut it down */
716 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
717 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
718 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
719 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
720 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
721 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
722 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE,
723 100, 0);
724 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
725 sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
726 }
727
728 bfe_core_reset(sc);
729 bfe_clear_stats(sc);
730
731 /*
732 * We want the phy registers to be accessible even when
733 * the driver is "downed" so initialize MDC preamble, frequency,
734 * and whether internal or external phy here.
735 */
736
737 /* 4402 has 62.5Mhz SB clock and internal phy */
738 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
739
740 /* Internal or external PHY? */
741 val = CSR_READ_4(sc, BFE_DEVCTRL);
742 if(!(val & BFE_IPP))
743 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
744 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
745 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
746 DELAY(100);
747 }
748
749 /* Enable CRC32 generation and set proper LED modes */
750 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
751
752 /* Reset or clear powerdown control bit */
753 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
754
755 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
756 BFE_LAZY_FC_MASK));
757
758 /*
759 * We don't want lazy interrupts, so just send them at
760 * the end of a frame, please
761 */
762 BFE_OR(sc, BFE_RCV_LAZY, 0);
763
764 /* Set max lengths, accounting for VLAN tags */
765 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
766 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
767
768 /* Set watermark XXX - magic */
769 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
770
771 /*
772 * Initialise DMA channels
773 * - not forgetting dma addresses need to be added to BFE_PCI_DMA
774 */
775 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
776 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
777
778 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
779 BFE_RX_CTRL_ENABLE);
780 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
781
782 bfe_resetphy(sc);
783 bfe_setupphy(sc);
784 }
785
786 static void
787 bfe_core_disable(struct bfe_softc *sc)
788 {
789 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
790 return;
791
792 /*
793 * Set reject, wait for it set, then wait for the core to stop
794 * being busy, then set reset and reject and enable the clocks.
795 */
796 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
797 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
798 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
799 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
800 BFE_RESET));
801 CSR_READ_4(sc, BFE_SBTMSLOW);
802 DELAY(10);
803 /* Leave reset and reject set */
804 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
805 DELAY(10);
806 }
807
808 static void
809 bfe_core_reset(struct bfe_softc *sc)
810 {
811 u_int32_t val;
812
813 /* Disable the core */
814 bfe_core_disable(sc);
815
816 /* and bring it back up */
817 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
818 CSR_READ_4(sc, BFE_SBTMSLOW);
819 DELAY(10);
820
821 /* Chip bug, clear SERR, IB and TO if they are set. */
822 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
823 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
824 val = CSR_READ_4(sc, BFE_SBIMSTATE);
825 if (val & (BFE_IBE | BFE_TO))
826 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
827
828 /* Clear reset and allow it to move through the core */
829 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
830 CSR_READ_4(sc, BFE_SBTMSLOW);
831 DELAY(10);
832
833 /* Leave the clock set */
834 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
835 CSR_READ_4(sc, BFE_SBTMSLOW);
836 DELAY(10);
837 }
838
839 static void
840 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
841 {
842 u_int32_t val;
843
844 val = ((u_int32_t) data[2]) << 24;
845 val |= ((u_int32_t) data[3]) << 16;
846 val |= ((u_int32_t) data[4]) << 8;
847 val |= ((u_int32_t) data[5]);
848 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
849 val = (BFE_CAM_HI_VALID |
850 (((u_int32_t) data[0]) << 8) |
851 (((u_int32_t) data[1])));
852 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
853 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
854 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT)));
855 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
856 }
857
858 static void
859 bfe_set_rx_mode(struct bfe_softc *sc)
860 {
861 struct ifnet *ifp = sc->bfe_ifp;
862 struct ifmultiaddr *ifma;
863 u_int32_t val;
864 int i = 0;
865
866 val = CSR_READ_4(sc, BFE_RXCONF);
867
868 if (ifp->if_flags & IFF_PROMISC)
869 val |= BFE_RXCONF_PROMISC;
870 else
871 val &= ~BFE_RXCONF_PROMISC;
872
873 if (ifp->if_flags & IFF_BROADCAST)
874 val &= ~BFE_RXCONF_DBCAST;
875 else
876 val |= BFE_RXCONF_DBCAST;
877
878
879 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
880 bfe_cam_write(sc, IFP2ENADDR(sc->bfe_ifp), i++);
881
882 if (ifp->if_flags & IFF_ALLMULTI)
883 val |= BFE_RXCONF_ALLMULTI;
884 else {
885 val &= ~BFE_RXCONF_ALLMULTI;
886 IF_ADDR_LOCK(ifp);
887 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
888 if (ifma->ifma_addr->sa_family != AF_LINK)
889 continue;
890 bfe_cam_write(sc,
891 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++);
892 }
893 IF_ADDR_UNLOCK(ifp);
894 }
895
896 CSR_WRITE_4(sc, BFE_RXCONF, val);
897 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
898 }
899
900 static void
901 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
902 {
903 u_int32_t *ptr;
904
905 ptr = arg;
906 *ptr = segs->ds_addr;
907 }
908
909 static void
910 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error)
911 {
912 struct bfe_desc *d;
913
914 d = arg;
915 /* The chip needs all addresses to be added to BFE_PCI_DMA */
916 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA;
917 }
918
919 static void
920 bfe_release_resources(struct bfe_softc *sc)
921 {
922 device_t dev;
923 int i;
924
925 dev = sc->bfe_dev;
926
927 if (sc->bfe_vpd_prodname != NULL)
928 free(sc->bfe_vpd_prodname, M_DEVBUF);
929
930 if (sc->bfe_vpd_readonly != NULL)
931 free(sc->bfe_vpd_readonly, M_DEVBUF);
932
933 if (sc->bfe_intrhand != NULL)
934 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand);
935
936 if (sc->bfe_irq != NULL)
937 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq);
938
939 if (sc->bfe_res != NULL)
940 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res);
941
942 if (sc->bfe_ifp != NULL)
943 if_free(sc->bfe_ifp);
944
945 if(sc->bfe_tx_tag != NULL) {
946 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
947 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
948 sc->bfe_tx_map);
949 bus_dma_tag_destroy(sc->bfe_tx_tag);
950 sc->bfe_tx_tag = NULL;
951 }
952
953 if(sc->bfe_rx_tag != NULL) {
954 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
955 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
956 sc->bfe_rx_map);
957 bus_dma_tag_destroy(sc->bfe_rx_tag);
958 sc->bfe_rx_tag = NULL;
959 }
960
961 if(sc->bfe_tag != NULL) {
962 for(i = 0; i < BFE_TX_LIST_CNT; i++) {
963 bus_dmamap_destroy(sc->bfe_tag,
964 sc->bfe_tx_ring[i].bfe_map);
965 }
966 for(i = 0; i < BFE_RX_LIST_CNT; i++) {
967 bus_dmamap_destroy(sc->bfe_tag,
968 sc->bfe_rx_ring[i].bfe_map);
969 }
970 bus_dma_tag_destroy(sc->bfe_tag);
971 sc->bfe_tag = NULL;
972 }
973
974 if(sc->bfe_parent_tag != NULL)
975 bus_dma_tag_destroy(sc->bfe_parent_tag);
976
977 return;
978 }
979
980 static void
981 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data)
982 {
983 long i;
984 u_int16_t *ptr = (u_int16_t *)data;
985
986 for(i = 0; i < 128; i += 2)
987 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
988 }
989
990 static int
991 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit,
992 u_long timeout, const int clear)
993 {
994 u_long i;
995
996 for (i = 0; i < timeout; i++) {
997 u_int32_t val = CSR_READ_4(sc, reg);
998
999 if (clear && !(val & bit))
1000 break;
1001 if (!clear && (val & bit))
1002 break;
1003 DELAY(10);
1004 }
1005 if (i == timeout) {
1006 printf("bfe%d: BUG! Timeout waiting for bit %08x of register "
1007 "%x to %s.\n", sc->bfe_unit, bit, reg,
1008 (clear ? "clear" : "set"));
1009 return (-1);
1010 }
1011 return (0);
1012 }
1013
1014 static int
1015 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val)
1016 {
1017 int err;
1018
1019 /* Clear MII ISR */
1020 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1021 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1022 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
1023 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1024 (reg << BFE_MDIO_RA_SHIFT) |
1025 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
1026 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1027 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
1028
1029 return (err);
1030 }
1031
1032 static int
1033 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val)
1034 {
1035 int status;
1036
1037 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1038 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1039 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1040 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1041 (reg << BFE_MDIO_RA_SHIFT) |
1042 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1043 (val & BFE_MDIO_DATA_DATA)));
1044 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1045
1046 return (status);
1047 }
1048
1049 /*
1050 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1051 * twice
1052 */
1053 static int
1054 bfe_setupphy(struct bfe_softc *sc)
1055 {
1056 u_int32_t val;
1057
1058 /* Enable activity LED */
1059 bfe_readphy(sc, 26, &val);
1060 bfe_writephy(sc, 26, val & 0x7fff);
1061 bfe_readphy(sc, 26, &val);
1062
1063 /* Enable traffic meter LED mode */
1064 bfe_readphy(sc, 27, &val);
1065 bfe_writephy(sc, 27, val | (1 << 6));
1066
1067 return (0);
1068 }
1069
1070 static void
1071 bfe_stats_update(struct bfe_softc *sc)
1072 {
1073 u_long reg;
1074 u_int32_t *val;
1075
1076 val = &sc->bfe_hwstats.tx_good_octets;
1077 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) {
1078 *val++ += CSR_READ_4(sc, reg);
1079 }
1080 val = &sc->bfe_hwstats.rx_good_octets;
1081 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) {
1082 *val++ += CSR_READ_4(sc, reg);
1083 }
1084 }
1085
1086 static void
1087 bfe_txeof(struct bfe_softc *sc)
1088 {
1089 struct ifnet *ifp;
1090 int i, chipidx;
1091
1092 BFE_LOCK_ASSERT(sc);
1093
1094 ifp = sc->bfe_ifp;
1095
1096 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1097 chipidx /= sizeof(struct bfe_desc);
1098
1099 i = sc->bfe_tx_cons;
1100 /* Go through the mbufs and free those that have been transmitted */
1101 while(i != chipidx) {
1102 struct bfe_data *r = &sc->bfe_tx_ring[i];
1103 if(r->bfe_mbuf != NULL) {
1104 ifp->if_opackets++;
1105 m_freem(r->bfe_mbuf);
1106 r->bfe_mbuf = NULL;
1107 }
1108 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1109 sc->bfe_tx_cnt--;
1110 BFE_INC(i, BFE_TX_LIST_CNT);
1111 }
1112
1113 if(i != sc->bfe_tx_cons) {
1114 /* we freed up some mbufs */
1115 sc->bfe_tx_cons = i;
1116 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1117 }
1118 if(sc->bfe_tx_cnt == 0)
1119 ifp->if_timer = 0;
1120 else
1121 ifp->if_timer = 5;
1122 }
1123
1124 /* Pass a received packet up the stack */
1125 static void
1126 bfe_rxeof(struct bfe_softc *sc)
1127 {
1128 struct mbuf *m;
1129 struct ifnet *ifp;
1130 struct bfe_rxheader *rxheader;
1131 struct bfe_data *r;
1132 int cons;
1133 u_int32_t status, current, len, flags;
1134
1135 BFE_LOCK_ASSERT(sc);
1136 cons = sc->bfe_rx_cons;
1137 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1138 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1139
1140 ifp = sc->bfe_ifp;
1141
1142 while(current != cons) {
1143 r = &sc->bfe_rx_ring[cons];
1144 m = r->bfe_mbuf;
1145 rxheader = mtod(m, struct bfe_rxheader*);
1146 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTREAD);
1147 len = rxheader->len;
1148 r->bfe_mbuf = NULL;
1149
1150 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1151 flags = rxheader->flags;
1152
1153 len -= ETHER_CRC_LEN;
1154
1155 /* flag an error and try again */
1156 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
1157 ifp->if_ierrors++;
1158 if (flags & BFE_RX_FLAG_SERR)
1159 ifp->if_collisions++;
1160 bfe_list_newbuf(sc, cons, m);
1161 BFE_INC(cons, BFE_RX_LIST_CNT);
1162 continue;
1163 }
1164
1165 /* Go past the rx header */
1166 if (bfe_list_newbuf(sc, cons, NULL) == 0) {
1167 m_adj(m, BFE_RX_OFFSET);
1168 m->m_len = m->m_pkthdr.len = len;
1169 } else {
1170 bfe_list_newbuf(sc, cons, m);
1171 ifp->if_ierrors++;
1172 BFE_INC(cons, BFE_RX_LIST_CNT);
1173 continue;
1174 }
1175
1176 ifp->if_ipackets++;
1177 m->m_pkthdr.rcvif = ifp;
1178 BFE_UNLOCK(sc);
1179 (*ifp->if_input)(ifp, m);
1180 BFE_LOCK(sc);
1181
1182 BFE_INC(cons, BFE_RX_LIST_CNT);
1183 }
1184 sc->bfe_rx_cons = cons;
1185 }
1186
1187 static void
1188 bfe_intr(void *xsc)
1189 {
1190 struct bfe_softc *sc = xsc;
1191 struct ifnet *ifp;
1192 u_int32_t istat, imask, flag;
1193
1194 ifp = sc->bfe_ifp;
1195
1196 BFE_LOCK(sc);
1197
1198 istat = CSR_READ_4(sc, BFE_ISTAT);
1199 imask = CSR_READ_4(sc, BFE_IMASK);
1200
1201 /*
1202 * Defer unsolicited interrupts - This is necessary because setting the
1203 * chips interrupt mask register to 0 doesn't actually stop the
1204 * interrupts
1205 */
1206 istat &= imask;
1207 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1208 CSR_READ_4(sc, BFE_ISTAT);
1209
1210 /* not expecting this interrupt, disregard it */
1211 if(istat == 0) {
1212 BFE_UNLOCK(sc);
1213 return;
1214 }
1215
1216 if(istat & BFE_ISTAT_ERRORS) {
1217
1218 if (istat & BFE_ISTAT_DSCE) {
1219 printf("if_bfe Descriptor Error\n");
1220 bfe_stop(sc);
1221 BFE_UNLOCK(sc);
1222 return;
1223 }
1224
1225 if (istat & BFE_ISTAT_DPE) {
1226 printf("if_bfe Descriptor Protocol Error\n");
1227 bfe_stop(sc);
1228 BFE_UNLOCK(sc);
1229 return;
1230 }
1231
1232 flag = CSR_READ_4(sc, BFE_DMATX_STAT);
1233 if(flag & BFE_STAT_EMASK)
1234 ifp->if_oerrors++;
1235
1236 flag = CSR_READ_4(sc, BFE_DMARX_STAT);
1237 if(flag & BFE_RX_FLAG_ERRORS)
1238 ifp->if_ierrors++;
1239
1240 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1241 bfe_init_locked(sc);
1242 }
1243
1244 /* A packet was received */
1245 if(istat & BFE_ISTAT_RX)
1246 bfe_rxeof(sc);
1247
1248 /* A packet was sent */
1249 if(istat & BFE_ISTAT_TX)
1250 bfe_txeof(sc);
1251
1252 /* We have packets pending, fire them out */
1253 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1254 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1255 bfe_start_locked(ifp);
1256
1257 BFE_UNLOCK(sc);
1258 }
1259
1260 static int
1261 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, u_int32_t *txidx)
1262 {
1263 struct bfe_desc *d = NULL;
1264 struct bfe_data *r = NULL;
1265 struct mbuf *m;
1266 u_int32_t frag, cur, cnt = 0;
1267 int chainlen = 0;
1268 int error;
1269
1270 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2)
1271 return (ENOBUFS);
1272
1273 /*
1274 * Count the number of frags in this chain to see if
1275 * we need to m_defrag. Since the descriptor list is shared
1276 * by all packets, we'll m_defrag long chains so that they
1277 * do not use up the entire list, even if they would fit.
1278 */
1279 for(m = *m_head; m != NULL; m = m->m_next)
1280 chainlen++;
1281
1282
1283 if ((chainlen > BFE_TX_LIST_CNT / 4) ||
1284 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) {
1285 m = m_defrag(*m_head, M_DONTWAIT);
1286 if (m == NULL)
1287 return (ENOBUFS);
1288 *m_head = m;
1289 }
1290
1291 /*
1292 * Start packing the mbufs in this chain into
1293 * the fragment pointers. Stop when we run out
1294 * of fragments or hit the end of the mbuf chain.
1295 */
1296 cur = frag = *txidx;
1297 cnt = 0;
1298
1299 for(m = *m_head; m != NULL; m = m->m_next) {
1300 if(m->m_len != 0) {
1301 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2)
1302 return (ENOBUFS);
1303
1304 d = &sc->bfe_tx_list[cur];
1305 r = &sc->bfe_tx_ring[cur];
1306 d->bfe_ctrl = BFE_DESC_LEN & m->m_len;
1307 /* always intterupt on completion */
1308 d->bfe_ctrl |= BFE_DESC_IOC;
1309 if(cnt == 0)
1310 /* Set start of frame */
1311 d->bfe_ctrl |= BFE_DESC_SOF;
1312 if(cur == BFE_TX_LIST_CNT - 1)
1313 /*
1314 * Tell the chip to wrap to the start of
1315 * the descriptor list
1316 */
1317 d->bfe_ctrl |= BFE_DESC_EOT;
1318
1319 error = bus_dmamap_load(sc->bfe_tag,
1320 r->bfe_map, mtod(m, void*), m->m_len,
1321 bfe_dma_map_desc, d, BUS_DMA_NOWAIT);
1322 if (error)
1323 return (ENOBUFS);
1324 bus_dmamap_sync(sc->bfe_tag, r->bfe_map,
1325 BUS_DMASYNC_PREWRITE);
1326
1327 frag = cur;
1328 BFE_INC(cur, BFE_TX_LIST_CNT);
1329 cnt++;
1330 }
1331 }
1332
1333 if (m != NULL)
1334 return (ENOBUFS);
1335
1336 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF;
1337 sc->bfe_tx_ring[frag].bfe_mbuf = *m_head;
1338 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
1339
1340 *txidx = cur;
1341 sc->bfe_tx_cnt += cnt;
1342 return (0);
1343 }
1344
1345 /*
1346 * Set up to transmit a packet.
1347 */
1348 static void
1349 bfe_start(struct ifnet *ifp)
1350 {
1351 BFE_LOCK((struct bfe_softc *)ifp->if_softc);
1352 bfe_start_locked(ifp);
1353 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc);
1354 }
1355
1356 /*
1357 * Set up to transmit a packet. The softc is already locked.
1358 */
1359 static void
1360 bfe_start_locked(struct ifnet *ifp)
1361 {
1362 struct bfe_softc *sc;
1363 struct mbuf *m_head = NULL;
1364 int idx, queued = 0;
1365
1366 sc = ifp->if_softc;
1367 idx = sc->bfe_tx_prod;
1368
1369 BFE_LOCK_ASSERT(sc);
1370
1371 /*
1372 * Not much point trying to send if the link is down
1373 * or we have nothing to send.
1374 */
1375 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10)
1376 return;
1377
1378 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1379 return;
1380
1381 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) {
1382 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1383 if(m_head == NULL)
1384 break;
1385
1386 /*
1387 * Pack the data into the tx ring. If we dont have
1388 * enough room, let the chip drain the ring.
1389 */
1390 if(bfe_encap(sc, &m_head, &idx)) {
1391 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1392 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1393 break;
1394 }
1395
1396 queued++;
1397
1398 /*
1399 * If there's a BPF listener, bounce a copy of this frame
1400 * to him.
1401 */
1402 BPF_MTAP(ifp, m_head);
1403 }
1404
1405 if (queued) {
1406 sc->bfe_tx_prod = idx;
1407 /* Transmit - twice due to apparent hardware bug */
1408 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1409 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1410
1411 /*
1412 * Set a timeout in case the chip goes out to lunch.
1413 */
1414 ifp->if_timer = 5;
1415 }
1416 }
1417
1418 static void
1419 bfe_init(void *xsc)
1420 {
1421 BFE_LOCK((struct bfe_softc *)xsc);
1422 bfe_init_locked(xsc);
1423 BFE_UNLOCK((struct bfe_softc *)xsc);
1424 }
1425
1426 static void
1427 bfe_init_locked(void *xsc)
1428 {
1429 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1430 struct ifnet *ifp = sc->bfe_ifp;
1431
1432 BFE_LOCK_ASSERT(sc);
1433
1434 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1435 return;
1436
1437 bfe_stop(sc);
1438 bfe_chip_reset(sc);
1439
1440 if (bfe_list_rx_init(sc) == ENOBUFS) {
1441 printf("bfe%d: bfe_init: Not enough memory for list buffers\n",
1442 sc->bfe_unit);
1443 bfe_stop(sc);
1444 return;
1445 }
1446
1447 bfe_set_rx_mode(sc);
1448
1449 /* Enable the chip and core */
1450 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1451 /* Enable interrupts */
1452 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1453
1454 bfe_ifmedia_upd(ifp);
1455 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1456 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1457
1458 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz);
1459 }
1460
1461 /*
1462 * Set media options.
1463 */
1464 static int
1465 bfe_ifmedia_upd(struct ifnet *ifp)
1466 {
1467 struct bfe_softc *sc;
1468 struct mii_data *mii;
1469
1470 sc = ifp->if_softc;
1471
1472 mii = device_get_softc(sc->bfe_miibus);
1473 sc->bfe_link = 0;
1474 if (mii->mii_instance) {
1475 struct mii_softc *miisc;
1476 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1477 miisc = LIST_NEXT(miisc, mii_list))
1478 mii_phy_reset(miisc);
1479 }
1480 mii_mediachg(mii);
1481
1482 return (0);
1483 }
1484
1485 /*
1486 * Report current media status.
1487 */
1488 static void
1489 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1490 {
1491 struct bfe_softc *sc = ifp->if_softc;
1492 struct mii_data *mii;
1493
1494 mii = device_get_softc(sc->bfe_miibus);
1495 mii_pollstat(mii);
1496 ifmr->ifm_active = mii->mii_media_active;
1497 ifmr->ifm_status = mii->mii_media_status;
1498 }
1499
1500 static int
1501 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1502 {
1503 struct bfe_softc *sc = ifp->if_softc;
1504 struct ifreq *ifr = (struct ifreq *) data;
1505 struct mii_data *mii;
1506 int error = 0;
1507
1508 switch(command) {
1509 case SIOCSIFFLAGS:
1510 BFE_LOCK(sc);
1511 if(ifp->if_flags & IFF_UP)
1512 if(ifp->if_drv_flags & IFF_DRV_RUNNING)
1513 bfe_set_rx_mode(sc);
1514 else
1515 bfe_init_locked(sc);
1516 else if(ifp->if_drv_flags & IFF_DRV_RUNNING)
1517 bfe_stop(sc);
1518 BFE_UNLOCK(sc);
1519 break;
1520 case SIOCADDMULTI:
1521 case SIOCDELMULTI:
1522 BFE_LOCK(sc);
1523 if(ifp->if_drv_flags & IFF_DRV_RUNNING)
1524 bfe_set_rx_mode(sc);
1525 BFE_UNLOCK(sc);
1526 break;
1527 case SIOCGIFMEDIA:
1528 case SIOCSIFMEDIA:
1529 mii = device_get_softc(sc->bfe_miibus);
1530 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1531 command);
1532 break;
1533 default:
1534 error = ether_ioctl(ifp, command, data);
1535 break;
1536 }
1537
1538 return (error);
1539 }
1540
1541 static void
1542 bfe_watchdog(struct ifnet *ifp)
1543 {
1544 struct bfe_softc *sc;
1545
1546 sc = ifp->if_softc;
1547
1548 BFE_LOCK(sc);
1549
1550 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit);
1551
1552 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1553 bfe_init_locked(sc);
1554
1555 ifp->if_oerrors++;
1556
1557 BFE_UNLOCK(sc);
1558 }
1559
1560 static void
1561 bfe_tick(void *xsc)
1562 {
1563 struct bfe_softc *sc = xsc;
1564 struct mii_data *mii;
1565
1566 if (sc == NULL)
1567 return;
1568
1569 BFE_LOCK(sc);
1570
1571 mii = device_get_softc(sc->bfe_miibus);
1572
1573 bfe_stats_update(sc);
1574 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz);
1575
1576 if(sc->bfe_link) {
1577 BFE_UNLOCK(sc);
1578 return;
1579 }
1580
1581 mii_tick(mii);
1582 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE &&
1583 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1584 sc->bfe_link++;
1585
1586 BFE_UNLOCK(sc);
1587 }
1588
1589 /*
1590 * Stop the adapter and free any mbufs allocated to the
1591 * RX and TX lists.
1592 */
1593 static void
1594 bfe_stop(struct bfe_softc *sc)
1595 {
1596 struct ifnet *ifp;
1597
1598 BFE_LOCK_ASSERT(sc);
1599
1600 untimeout(bfe_tick, sc, sc->bfe_stat_ch);
1601
1602 ifp = sc->bfe_ifp;
1603
1604 bfe_chip_halt(sc);
1605 bfe_tx_ring_free(sc);
1606 bfe_rx_ring_free(sc);
1607
1608 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1609 }
Cache object: 636c75b08962ef0cc4fe4a927cfc67ea
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