Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/bfe/if_bfe.c
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1 /*- 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/endian.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/mbuf.h> 38 #include <sys/module.h> 39 #include <sys/rman.h> 40 #include <sys/socket.h> 41 #include <sys/sockio.h> 42 43 #include <net/bpf.h> 44 #include <net/if.h> 45 #include <net/ethernet.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 #include <net/if_types.h> 49 #include <net/if_vlan_var.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcivar.h> 56 57 #include <machine/bus.h> 58 59 #include <dev/bfe/if_bfereg.h> 60 61 MODULE_DEPEND(bfe, pci, 1, 1, 1); 62 MODULE_DEPEND(bfe, ether, 1, 1, 1); 63 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 64 65 /* "controller miibus0" required. See GENERIC if you get errors here. */ 66 #include "miibus_if.h" 67 68 #if __FreeBSD_version < 700000 69 #define m_collapse(x, y, z) m_defrag(x, y) 70 #endif 71 72 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 73 74 static struct bfe_type bfe_devs[] = { 75 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 76 "Broadcom BCM4401 Fast Ethernet" }, 77 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 78 "Broadcom BCM4401-B0 Fast Ethernet" }, 79 { 0, 0, NULL } 80 }; 81 82 static int bfe_probe (device_t); 83 static int bfe_attach (device_t); 84 static int bfe_detach (device_t); 85 static int bfe_suspend (device_t); 86 static int bfe_resume (device_t); 87 static void bfe_release_resources (struct bfe_softc *); 88 static void bfe_intr (void *); 89 static int bfe_encap (struct bfe_softc *, struct mbuf **); 90 static void bfe_start (struct ifnet *); 91 static void bfe_start_locked (struct ifnet *); 92 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 93 static void bfe_init (void *); 94 static void bfe_init_locked (void *); 95 static void bfe_stop (struct bfe_softc *); 96 static void bfe_watchdog (struct bfe_softc *); 97 static void bfe_shutdown (device_t); 98 static void bfe_tick (void *); 99 static void bfe_txeof (struct bfe_softc *); 100 static void bfe_rxeof (struct bfe_softc *); 101 static void bfe_set_rx_mode (struct bfe_softc *); 102 static int bfe_list_rx_init (struct bfe_softc *); 103 static void bfe_list_tx_init (struct bfe_softc *); 104 static void bfe_discard_buf (struct bfe_softc *, int); 105 static int bfe_list_newbuf (struct bfe_softc *, int); 106 static void bfe_rx_ring_free (struct bfe_softc *); 107 108 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 109 static int bfe_ifmedia_upd (struct ifnet *); 110 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 111 static int bfe_miibus_readreg (device_t, int, int); 112 static int bfe_miibus_writereg (device_t, int, int, int); 113 static void bfe_miibus_statchg (device_t); 114 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 115 u_long, const int); 116 static void bfe_get_config (struct bfe_softc *sc); 117 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 118 static void bfe_stats_update (struct bfe_softc *); 119 static void bfe_clear_stats (struct bfe_softc *); 120 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 121 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 122 static int bfe_resetphy (struct bfe_softc *); 123 static int bfe_setupphy (struct bfe_softc *); 124 static void bfe_chip_reset (struct bfe_softc *); 125 static void bfe_chip_halt (struct bfe_softc *); 126 static void bfe_core_reset (struct bfe_softc *); 127 static void bfe_core_disable (struct bfe_softc *); 128 static int bfe_dma_alloc (struct bfe_softc *); 129 static void bfe_dma_free (struct bfe_softc *sc); 130 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 131 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 132 133 static device_method_t bfe_methods[] = { 134 /* Device interface */ 135 DEVMETHOD(device_probe, bfe_probe), 136 DEVMETHOD(device_attach, bfe_attach), 137 DEVMETHOD(device_detach, bfe_detach), 138 DEVMETHOD(device_shutdown, bfe_shutdown), 139 DEVMETHOD(device_suspend, bfe_suspend), 140 DEVMETHOD(device_resume, bfe_resume), 141 142 /* bus interface */ 143 DEVMETHOD(bus_print_child, bus_generic_print_child), 144 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 145 146 /* MII interface */ 147 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 148 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 149 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 150 151 { 0, 0 } 152 }; 153 154 static driver_t bfe_driver = { 155 "bfe", 156 bfe_methods, 157 sizeof(struct bfe_softc) 158 }; 159 160 static devclass_t bfe_devclass; 161 162 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 163 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 164 165 /* 166 * Probe for a Broadcom 4401 chip. 167 */ 168 static int 169 bfe_probe(device_t dev) 170 { 171 struct bfe_type *t; 172 173 t = bfe_devs; 174 175 while (t->bfe_name != NULL) { 176 if (pci_get_vendor(dev) == t->bfe_vid && 177 pci_get_device(dev) == t->bfe_did) { 178 device_set_desc(dev, t->bfe_name); 179 return (BUS_PROBE_DEFAULT); 180 } 181 t++; 182 } 183 184 return (ENXIO); 185 } 186 187 struct bfe_dmamap_arg { 188 bus_addr_t bfe_busaddr; 189 }; 190 191 static int 192 bfe_dma_alloc(struct bfe_softc *sc) 193 { 194 struct bfe_dmamap_arg ctx; 195 struct bfe_rx_data *rd; 196 struct bfe_tx_data *td; 197 int error, i; 198 199 /* 200 * parent tag. Apparently the chip cannot handle any DMA address 201 * greater than 1GB. 202 */ 203 error = bus_dma_tag_create(bus_get_dma_tag(sc->bfe_dev), /* parent */ 204 1, 0, /* alignment, boundary */ 205 BFE_DMA_MAXADDR, /* lowaddr */ 206 BUS_SPACE_MAXADDR, /* highaddr */ 207 NULL, NULL, /* filter, filterarg */ 208 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 209 0, /* nsegments */ 210 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 211 0, /* flags */ 212 NULL, NULL, /* lockfunc, lockarg */ 213 &sc->bfe_parent_tag); 214 if (error != 0) { 215 device_printf(sc->bfe_dev, "cannot create parent DMA tag.\n"); 216 goto fail; 217 } 218 219 /* Create tag for Tx ring. */ 220 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 221 BFE_TX_RING_ALIGN, 0, /* alignment, boundary */ 222 BUS_SPACE_MAXADDR, /* lowaddr */ 223 BUS_SPACE_MAXADDR, /* highaddr */ 224 NULL, NULL, /* filter, filterarg */ 225 BFE_TX_LIST_SIZE, /* maxsize */ 226 1, /* nsegments */ 227 BFE_TX_LIST_SIZE, /* maxsegsize */ 228 0, /* flags */ 229 NULL, NULL, /* lockfunc, lockarg */ 230 &sc->bfe_tx_tag); 231 if (error != 0) { 232 device_printf(sc->bfe_dev, "cannot create Tx ring DMA tag.\n"); 233 goto fail; 234 } 235 236 /* Create tag for Rx ring. */ 237 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 238 BFE_RX_RING_ALIGN, 0, /* alignment, boundary */ 239 BUS_SPACE_MAXADDR, /* lowaddr */ 240 BUS_SPACE_MAXADDR, /* highaddr */ 241 NULL, NULL, /* filter, filterarg */ 242 BFE_RX_LIST_SIZE, /* maxsize */ 243 1, /* nsegments */ 244 BFE_RX_LIST_SIZE, /* maxsegsize */ 245 0, /* flags */ 246 NULL, NULL, /* lockfunc, lockarg */ 247 &sc->bfe_rx_tag); 248 if (error != 0) { 249 device_printf(sc->bfe_dev, "cannot create Rx ring DMA tag.\n"); 250 goto fail; 251 } 252 253 /* Create tag for Tx buffers. */ 254 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 255 1, 0, /* alignment, boundary */ 256 BUS_SPACE_MAXADDR, /* lowaddr */ 257 BUS_SPACE_MAXADDR, /* highaddr */ 258 NULL, NULL, /* filter, filterarg */ 259 MCLBYTES * BFE_MAXTXSEGS, /* maxsize */ 260 BFE_MAXTXSEGS, /* nsegments */ 261 MCLBYTES, /* maxsegsize */ 262 0, /* flags */ 263 NULL, NULL, /* lockfunc, lockarg */ 264 &sc->bfe_txmbuf_tag); 265 if (error != 0) { 266 device_printf(sc->bfe_dev, 267 "cannot create Tx buffer DMA tag.\n"); 268 goto fail; 269 } 270 271 /* Create tag for Rx buffers. */ 272 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 273 1, 0, /* alignment, boundary */ 274 BUS_SPACE_MAXADDR, /* lowaddr */ 275 BUS_SPACE_MAXADDR, /* highaddr */ 276 NULL, NULL, /* filter, filterarg */ 277 MCLBYTES, /* maxsize */ 278 1, /* nsegments */ 279 MCLBYTES, /* maxsegsize */ 280 0, /* flags */ 281 NULL, NULL, /* lockfunc, lockarg */ 282 &sc->bfe_rxmbuf_tag); 283 if (error != 0) { 284 device_printf(sc->bfe_dev, 285 "cannot create Rx buffer DMA tag.\n"); 286 goto fail; 287 } 288 289 /* Allocate DMA'able memory and load DMA map. */ 290 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 291 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_tx_map); 292 if (error != 0) { 293 device_printf(sc->bfe_dev, 294 "cannot allocate DMA'able memory for Tx ring.\n"); 295 goto fail; 296 } 297 ctx.bfe_busaddr = 0; 298 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 299 sc->bfe_tx_list, BFE_TX_LIST_SIZE, bfe_dma_map, &ctx, 300 BUS_DMA_NOWAIT); 301 if (error != 0 || ctx.bfe_busaddr == 0) { 302 device_printf(sc->bfe_dev, 303 "cannot load DMA'able memory for Tx ring.\n"); 304 goto fail; 305 } 306 sc->bfe_tx_dma = BFE_ADDR_LO(ctx.bfe_busaddr); 307 308 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 309 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_rx_map); 310 if (error != 0) { 311 device_printf(sc->bfe_dev, 312 "cannot allocate DMA'able memory for Rx ring.\n"); 313 goto fail; 314 } 315 ctx.bfe_busaddr = 0; 316 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 317 sc->bfe_rx_list, BFE_RX_LIST_SIZE, bfe_dma_map, &ctx, 318 BUS_DMA_NOWAIT); 319 if (error != 0 || ctx.bfe_busaddr == 0) { 320 device_printf(sc->bfe_dev, 321 "cannot load DMA'able memory for Rx ring.\n"); 322 goto fail; 323 } 324 sc->bfe_rx_dma = BFE_ADDR_LO(ctx.bfe_busaddr); 325 326 /* Create DMA maps for Tx buffers. */ 327 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 328 td = &sc->bfe_tx_ring[i]; 329 td->bfe_mbuf = NULL; 330 td->bfe_map = NULL; 331 error = bus_dmamap_create(sc->bfe_txmbuf_tag, 0, &td->bfe_map); 332 if (error != 0) { 333 device_printf(sc->bfe_dev, 334 "cannot create DMA map for Tx.\n"); 335 goto fail; 336 } 337 } 338 339 /* Create spare DMA map for Rx buffers. */ 340 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &sc->bfe_rx_sparemap); 341 if (error != 0) { 342 device_printf(sc->bfe_dev, "cannot create spare DMA map for Rx.\n"); 343 goto fail; 344 } 345 /* Create DMA maps for Rx buffers. */ 346 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 347 rd = &sc->bfe_rx_ring[i]; 348 rd->bfe_mbuf = NULL; 349 rd->bfe_map = NULL; 350 rd->bfe_ctrl = 0; 351 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &rd->bfe_map); 352 if (error != 0) { 353 device_printf(sc->bfe_dev, 354 "cannot create DMA map for Rx.\n"); 355 goto fail; 356 } 357 } 358 359 fail: 360 return (error); 361 } 362 363 static void 364 bfe_dma_free(struct bfe_softc *sc) 365 { 366 struct bfe_tx_data *td; 367 struct bfe_rx_data *rd; 368 int i; 369 370 /* Tx ring. */ 371 if (sc->bfe_tx_tag != NULL) { 372 if (sc->bfe_tx_map != NULL) 373 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 374 if (sc->bfe_tx_map != NULL && sc->bfe_tx_list != NULL) 375 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 376 sc->bfe_tx_map); 377 sc->bfe_tx_map = NULL; 378 sc->bfe_tx_list = NULL; 379 bus_dma_tag_destroy(sc->bfe_tx_tag); 380 sc->bfe_tx_tag = NULL; 381 } 382 383 /* Rx ring. */ 384 if (sc->bfe_rx_tag != NULL) { 385 if (sc->bfe_rx_map != NULL) 386 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 387 if (sc->bfe_rx_map != NULL && sc->bfe_rx_list != NULL) 388 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 389 sc->bfe_rx_map); 390 sc->bfe_rx_map = NULL; 391 sc->bfe_rx_list = NULL; 392 bus_dma_tag_destroy(sc->bfe_rx_tag); 393 sc->bfe_rx_tag = NULL; 394 } 395 396 /* Tx buffers. */ 397 if (sc->bfe_txmbuf_tag != NULL) { 398 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 399 td = &sc->bfe_tx_ring[i]; 400 if (td->bfe_map != NULL) { 401 bus_dmamap_destroy(sc->bfe_txmbuf_tag, 402 td->bfe_map); 403 td->bfe_map = NULL; 404 } 405 } 406 bus_dma_tag_destroy(sc->bfe_txmbuf_tag); 407 sc->bfe_txmbuf_tag = NULL; 408 } 409 410 /* Rx buffers. */ 411 if (sc->bfe_rxmbuf_tag != NULL) { 412 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 413 rd = &sc->bfe_rx_ring[i]; 414 if (rd->bfe_map != NULL) { 415 bus_dmamap_destroy(sc->bfe_rxmbuf_tag, 416 rd->bfe_map); 417 rd->bfe_map = NULL; 418 } 419 } 420 if (sc->bfe_rx_sparemap != NULL) { 421 bus_dmamap_destroy(sc->bfe_rxmbuf_tag, 422 sc->bfe_rx_sparemap); 423 sc->bfe_rx_sparemap = NULL; 424 } 425 bus_dma_tag_destroy(sc->bfe_rxmbuf_tag); 426 sc->bfe_rxmbuf_tag = NULL; 427 } 428 429 if (sc->bfe_parent_tag != NULL) { 430 bus_dma_tag_destroy(sc->bfe_parent_tag); 431 sc->bfe_parent_tag = NULL; 432 } 433 } 434 435 static int 436 bfe_attach(device_t dev) 437 { 438 struct ifnet *ifp = NULL; 439 struct bfe_softc *sc; 440 int error = 0, rid; 441 442 sc = device_get_softc(dev); 443 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 444 MTX_DEF); 445 callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0); 446 447 sc->bfe_dev = dev; 448 449 /* 450 * Map control/status registers. 451 */ 452 pci_enable_busmaster(dev); 453 454 rid = PCIR_BAR(0); 455 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 456 RF_ACTIVE); 457 if (sc->bfe_res == NULL) { 458 device_printf(dev, "couldn't map memory\n"); 459 error = ENXIO; 460 goto fail; 461 } 462 463 /* Allocate interrupt */ 464 rid = 0; 465 466 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 467 RF_SHAREABLE | RF_ACTIVE); 468 if (sc->bfe_irq == NULL) { 469 device_printf(dev, "couldn't map interrupt\n"); 470 error = ENXIO; 471 goto fail; 472 } 473 474 if (bfe_dma_alloc(sc) != 0) { 475 device_printf(dev, "failed to allocate DMA resources\n"); 476 error = ENXIO; 477 goto fail; 478 } 479 480 /* Set up ifnet structure */ 481 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER); 482 if (ifp == NULL) { 483 device_printf(dev, "failed to if_alloc()\n"); 484 error = ENOSPC; 485 goto fail; 486 } 487 ifp->if_softc = sc; 488 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 489 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 490 ifp->if_ioctl = bfe_ioctl; 491 ifp->if_start = bfe_start; 492 ifp->if_init = bfe_init; 493 ifp->if_mtu = ETHERMTU; 494 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 495 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 496 IFQ_SET_READY(&ifp->if_snd); 497 498 bfe_get_config(sc); 499 500 /* Reset the chip and turn on the PHY */ 501 BFE_LOCK(sc); 502 bfe_chip_reset(sc); 503 BFE_UNLOCK(sc); 504 505 if (mii_phy_probe(dev, &sc->bfe_miibus, 506 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 507 device_printf(dev, "MII without any PHY!\n"); 508 error = ENXIO; 509 goto fail; 510 } 511 512 ether_ifattach(ifp, sc->bfe_enaddr); 513 514 /* 515 * Tell the upper layer(s) we support long frames. 516 */ 517 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 518 ifp->if_capabilities |= IFCAP_VLAN_MTU; 519 ifp->if_capenable |= IFCAP_VLAN_MTU; 520 521 /* 522 * Hook interrupt last to avoid having to lock softc 523 */ 524 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 525 bfe_intr, sc, &sc->bfe_intrhand); 526 527 if (error) { 528 device_printf(dev, "couldn't set up irq\n"); 529 goto fail; 530 } 531 fail: 532 if (error != 0) 533 bfe_detach(dev); 534 return (error); 535 } 536 537 static int 538 bfe_detach(device_t dev) 539 { 540 struct bfe_softc *sc; 541 struct ifnet *ifp; 542 543 sc = device_get_softc(dev); 544 545 ifp = sc->bfe_ifp; 546 547 if (device_is_attached(dev)) { 548 BFE_LOCK(sc); 549 sc->bfe_flags |= BFE_FLAG_DETACH; 550 bfe_stop(sc); 551 BFE_UNLOCK(sc); 552 callout_drain(&sc->bfe_stat_co); 553 if (ifp != NULL) 554 ether_ifdetach(ifp); 555 } 556 557 BFE_LOCK(sc); 558 bfe_chip_reset(sc); 559 BFE_UNLOCK(sc); 560 561 bus_generic_detach(dev); 562 if (sc->bfe_miibus != NULL) 563 device_delete_child(dev, sc->bfe_miibus); 564 565 bfe_release_resources(sc); 566 bfe_dma_free(sc); 567 mtx_destroy(&sc->bfe_mtx); 568 569 return (0); 570 } 571 572 /* 573 * Stop all chip I/O so that the kernel's probe routines don't 574 * get confused by errant DMAs when rebooting. 575 */ 576 static void 577 bfe_shutdown(device_t dev) 578 { 579 struct bfe_softc *sc; 580 581 sc = device_get_softc(dev); 582 BFE_LOCK(sc); 583 bfe_stop(sc); 584 585 BFE_UNLOCK(sc); 586 return; 587 } 588 589 static int 590 bfe_suspend(device_t dev) 591 { 592 struct bfe_softc *sc; 593 594 sc = device_get_softc(dev); 595 BFE_LOCK(sc); 596 bfe_stop(sc); 597 BFE_UNLOCK(sc); 598 599 return (0); 600 } 601 602 static int 603 bfe_resume(device_t dev) 604 { 605 struct bfe_softc *sc; 606 struct ifnet *ifp; 607 608 sc = device_get_softc(dev); 609 ifp = sc->bfe_ifp; 610 BFE_LOCK(sc); 611 bfe_chip_reset(sc); 612 if (ifp->if_flags & IFF_UP) { 613 bfe_init_locked(sc); 614 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 615 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 616 bfe_start_locked(ifp); 617 } 618 BFE_UNLOCK(sc); 619 620 return (0); 621 } 622 623 static int 624 bfe_miibus_readreg(device_t dev, int phy, int reg) 625 { 626 struct bfe_softc *sc; 627 u_int32_t ret; 628 629 sc = device_get_softc(dev); 630 if (phy != sc->bfe_phyaddr) 631 return (0); 632 bfe_readphy(sc, reg, &ret); 633 634 return (ret); 635 } 636 637 static int 638 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 639 { 640 struct bfe_softc *sc; 641 642 sc = device_get_softc(dev); 643 if (phy != sc->bfe_phyaddr) 644 return (0); 645 bfe_writephy(sc, reg, val); 646 647 return (0); 648 } 649 650 static void 651 bfe_miibus_statchg(device_t dev) 652 { 653 struct bfe_softc *sc; 654 struct mii_data *mii; 655 u_int32_t val, flow; 656 657 sc = device_get_softc(dev); 658 mii = device_get_softc(sc->bfe_miibus); 659 660 sc->bfe_flags &= ~BFE_FLAG_LINK; 661 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 662 (IFM_ACTIVE | IFM_AVALID)) { 663 switch (IFM_SUBTYPE(mii->mii_media_active)) { 664 case IFM_10_T: 665 case IFM_100_TX: 666 sc->bfe_flags |= BFE_FLAG_LINK; 667 break; 668 default: 669 break; 670 } 671 } 672 673 /* XXX Should stop Rx/Tx engine prior to touching MAC. */ 674 val = CSR_READ_4(sc, BFE_TX_CTRL); 675 val &= ~BFE_TX_DUPLEX; 676 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 677 val |= BFE_TX_DUPLEX; 678 flow = 0; 679 #ifdef notyet 680 flow = CSR_READ_4(sc, BFE_RXCONF); 681 flow &= ~BFE_RXCONF_FLOW; 682 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 683 IFM_ETH_RXPAUSE) != 0) 684 flow |= BFE_RXCONF_FLOW; 685 CSR_WRITE_4(sc, BFE_RXCONF, flow); 686 /* 687 * It seems that the hardware has Tx pause issues 688 * so enable only Rx pause. 689 */ 690 flow = CSR_READ_4(sc, BFE_MAC_FLOW); 691 flow &= ~BFE_FLOW_PAUSE_ENAB; 692 CSR_WRITE_4(sc, BFE_MAC_FLOW, flow); 693 #endif 694 } 695 CSR_WRITE_4(sc, BFE_TX_CTRL, val); 696 } 697 698 static void 699 bfe_tx_ring_free(struct bfe_softc *sc) 700 { 701 int i; 702 703 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 704 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 705 bus_dmamap_sync(sc->bfe_txmbuf_tag, 706 sc->bfe_tx_ring[i].bfe_map, BUS_DMASYNC_POSTWRITE); 707 bus_dmamap_unload(sc->bfe_txmbuf_tag, 708 sc->bfe_tx_ring[i].bfe_map); 709 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 710 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 711 } 712 } 713 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 714 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 715 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 716 } 717 718 static void 719 bfe_rx_ring_free(struct bfe_softc *sc) 720 { 721 int i; 722 723 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 724 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 725 bus_dmamap_sync(sc->bfe_rxmbuf_tag, 726 sc->bfe_rx_ring[i].bfe_map, BUS_DMASYNC_POSTREAD); 727 bus_dmamap_unload(sc->bfe_rxmbuf_tag, 728 sc->bfe_rx_ring[i].bfe_map); 729 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 730 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 731 } 732 } 733 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 734 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 735 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 736 } 737 738 static int 739 bfe_list_rx_init(struct bfe_softc *sc) 740 { 741 struct bfe_rx_data *rd; 742 int i; 743 744 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 745 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 746 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 747 rd = &sc->bfe_rx_ring[i]; 748 rd->bfe_mbuf = NULL; 749 rd->bfe_ctrl = 0; 750 if (bfe_list_newbuf(sc, i) != 0) 751 return (ENOBUFS); 752 } 753 754 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 755 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 756 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 757 758 return (0); 759 } 760 761 static void 762 bfe_list_tx_init(struct bfe_softc *sc) 763 { 764 int i; 765 766 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 767 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 768 for (i = 0; i < BFE_TX_LIST_CNT; i++) 769 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 770 771 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 772 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 773 } 774 775 static void 776 bfe_discard_buf(struct bfe_softc *sc, int c) 777 { 778 struct bfe_rx_data *r; 779 struct bfe_desc *d; 780 781 r = &sc->bfe_rx_ring[c]; 782 d = &sc->bfe_rx_list[c]; 783 d->bfe_ctrl = htole32(r->bfe_ctrl); 784 } 785 786 static int 787 bfe_list_newbuf(struct bfe_softc *sc, int c) 788 { 789 struct bfe_rxheader *rx_header; 790 struct bfe_desc *d; 791 struct bfe_rx_data *r; 792 struct mbuf *m; 793 bus_dma_segment_t segs[1]; 794 bus_dmamap_t map; 795 u_int32_t ctrl; 796 int nsegs; 797 798 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 799 m->m_len = m->m_pkthdr.len = MCLBYTES; 800 801 if (bus_dmamap_load_mbuf_sg(sc->bfe_rxmbuf_tag, sc->bfe_rx_sparemap, 802 m, segs, &nsegs, 0) != 0) { 803 m_freem(m); 804 return (ENOBUFS); 805 } 806 807 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 808 r = &sc->bfe_rx_ring[c]; 809 if (r->bfe_mbuf != NULL) { 810 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, 811 BUS_DMASYNC_POSTREAD); 812 bus_dmamap_unload(sc->bfe_rxmbuf_tag, r->bfe_map); 813 } 814 map = r->bfe_map; 815 r->bfe_map = sc->bfe_rx_sparemap; 816 sc->bfe_rx_sparemap = map; 817 r->bfe_mbuf = m; 818 819 rx_header = mtod(m, struct bfe_rxheader *); 820 rx_header->len = 0; 821 rx_header->flags = 0; 822 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, BUS_DMASYNC_PREREAD); 823 824 ctrl = segs[0].ds_len & BFE_DESC_LEN; 825 KASSERT(ctrl > ETHER_MAX_LEN + 32, ("%s: buffer size too small(%d)!", 826 __func__, ctrl)); 827 if (c == BFE_RX_LIST_CNT - 1) 828 ctrl |= BFE_DESC_EOT; 829 r->bfe_ctrl = ctrl; 830 831 d = &sc->bfe_rx_list[c]; 832 d->bfe_ctrl = htole32(ctrl); 833 /* The chip needs all addresses to be added to BFE_PCI_DMA. */ 834 d->bfe_addr = htole32(BFE_ADDR_LO(segs[0].ds_addr) + BFE_PCI_DMA); 835 836 return (0); 837 } 838 839 static void 840 bfe_get_config(struct bfe_softc *sc) 841 { 842 u_int8_t eeprom[128]; 843 844 bfe_read_eeprom(sc, eeprom); 845 846 sc->bfe_enaddr[0] = eeprom[79]; 847 sc->bfe_enaddr[1] = eeprom[78]; 848 sc->bfe_enaddr[2] = eeprom[81]; 849 sc->bfe_enaddr[3] = eeprom[80]; 850 sc->bfe_enaddr[4] = eeprom[83]; 851 sc->bfe_enaddr[5] = eeprom[82]; 852 853 sc->bfe_phyaddr = eeprom[90] & 0x1f; 854 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 855 856 sc->bfe_core_unit = 0; 857 sc->bfe_dma_offset = BFE_PCI_DMA; 858 } 859 860 static void 861 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 862 { 863 u_int32_t bar_orig, pci_rev, val; 864 865 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 866 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 867 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 868 869 val = CSR_READ_4(sc, BFE_SBINTVEC); 870 val |= cores; 871 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 872 873 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 874 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 875 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 876 877 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 878 } 879 880 static void 881 bfe_clear_stats(struct bfe_softc *sc) 882 { 883 u_long reg; 884 885 BFE_LOCK_ASSERT(sc); 886 887 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 888 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 889 CSR_READ_4(sc, reg); 890 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 891 CSR_READ_4(sc, reg); 892 } 893 894 static int 895 bfe_resetphy(struct bfe_softc *sc) 896 { 897 u_int32_t val; 898 899 bfe_writephy(sc, 0, BMCR_RESET); 900 DELAY(100); 901 bfe_readphy(sc, 0, &val); 902 if (val & BMCR_RESET) { 903 device_printf(sc->bfe_dev, "PHY Reset would not complete.\n"); 904 return (ENXIO); 905 } 906 return (0); 907 } 908 909 static void 910 bfe_chip_halt(struct bfe_softc *sc) 911 { 912 BFE_LOCK_ASSERT(sc); 913 /* disable interrupts - not that it actually does..*/ 914 CSR_WRITE_4(sc, BFE_IMASK, 0); 915 CSR_READ_4(sc, BFE_IMASK); 916 917 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 918 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 919 920 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 921 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 922 DELAY(10); 923 } 924 925 static void 926 bfe_chip_reset(struct bfe_softc *sc) 927 { 928 u_int32_t val; 929 930 BFE_LOCK_ASSERT(sc); 931 932 /* Set the interrupt vector for the enet core */ 933 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 934 935 /* is core up? */ 936 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 937 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 938 if (val == BFE_CLOCK) { 939 /* It is, so shut it down */ 940 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 941 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 942 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 943 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 944 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 945 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 946 100, 0); 947 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 948 } 949 950 bfe_core_reset(sc); 951 bfe_clear_stats(sc); 952 953 /* 954 * We want the phy registers to be accessible even when 955 * the driver is "downed" so initialize MDC preamble, frequency, 956 * and whether internal or external phy here. 957 */ 958 959 /* 4402 has 62.5Mhz SB clock and internal phy */ 960 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 961 962 /* Internal or external PHY? */ 963 val = CSR_READ_4(sc, BFE_DEVCTRL); 964 if (!(val & BFE_IPP)) 965 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 966 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 967 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 968 DELAY(100); 969 } 970 971 /* Enable CRC32 generation and set proper LED modes */ 972 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 973 974 /* Reset or clear powerdown control bit */ 975 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 976 977 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 978 BFE_LAZY_FC_MASK)); 979 980 /* 981 * We don't want lazy interrupts, so just send them at 982 * the end of a frame, please 983 */ 984 BFE_OR(sc, BFE_RCV_LAZY, 0); 985 986 /* Set max lengths, accounting for VLAN tags */ 987 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 988 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 989 990 /* Set watermark XXX - magic */ 991 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 992 993 /* 994 * Initialise DMA channels 995 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 996 */ 997 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 998 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 999 1000 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 1001 BFE_RX_CTRL_ENABLE); 1002 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 1003 1004 bfe_resetphy(sc); 1005 bfe_setupphy(sc); 1006 } 1007 1008 static void 1009 bfe_core_disable(struct bfe_softc *sc) 1010 { 1011 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 1012 return; 1013 1014 /* 1015 * Set reject, wait for it set, then wait for the core to stop 1016 * being busy, then set reset and reject and enable the clocks. 1017 */ 1018 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 1019 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 1020 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 1021 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 1022 BFE_RESET)); 1023 CSR_READ_4(sc, BFE_SBTMSLOW); 1024 DELAY(10); 1025 /* Leave reset and reject set */ 1026 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 1027 DELAY(10); 1028 } 1029 1030 static void 1031 bfe_core_reset(struct bfe_softc *sc) 1032 { 1033 u_int32_t val; 1034 1035 /* Disable the core */ 1036 bfe_core_disable(sc); 1037 1038 /* and bring it back up */ 1039 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 1040 CSR_READ_4(sc, BFE_SBTMSLOW); 1041 DELAY(10); 1042 1043 /* Chip bug, clear SERR, IB and TO if they are set. */ 1044 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 1045 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 1046 val = CSR_READ_4(sc, BFE_SBIMSTATE); 1047 if (val & (BFE_IBE | BFE_TO)) 1048 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 1049 1050 /* Clear reset and allow it to move through the core */ 1051 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 1052 CSR_READ_4(sc, BFE_SBTMSLOW); 1053 DELAY(10); 1054 1055 /* Leave the clock set */ 1056 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 1057 CSR_READ_4(sc, BFE_SBTMSLOW); 1058 DELAY(10); 1059 } 1060 1061 static void 1062 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 1063 { 1064 u_int32_t val; 1065 1066 val = ((u_int32_t) data[2]) << 24; 1067 val |= ((u_int32_t) data[3]) << 16; 1068 val |= ((u_int32_t) data[4]) << 8; 1069 val |= ((u_int32_t) data[5]); 1070 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 1071 val = (BFE_CAM_HI_VALID | 1072 (((u_int32_t) data[0]) << 8) | 1073 (((u_int32_t) data[1]))); 1074 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 1075 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 1076 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 1077 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 1078 } 1079 1080 static void 1081 bfe_set_rx_mode(struct bfe_softc *sc) 1082 { 1083 struct ifnet *ifp = sc->bfe_ifp; 1084 struct ifmultiaddr *ifma; 1085 u_int32_t val; 1086 int i = 0; 1087 1088 val = CSR_READ_4(sc, BFE_RXCONF); 1089 1090 if (ifp->if_flags & IFF_PROMISC) 1091 val |= BFE_RXCONF_PROMISC; 1092 else 1093 val &= ~BFE_RXCONF_PROMISC; 1094 1095 if (ifp->if_flags & IFF_BROADCAST) 1096 val &= ~BFE_RXCONF_DBCAST; 1097 else 1098 val |= BFE_RXCONF_DBCAST; 1099 1100 1101 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 1102 bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++); 1103 1104 if (ifp->if_flags & IFF_ALLMULTI) 1105 val |= BFE_RXCONF_ALLMULTI; 1106 else { 1107 val &= ~BFE_RXCONF_ALLMULTI; 1108 IF_ADDR_LOCK(ifp); 1109 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1110 if (ifma->ifma_addr->sa_family != AF_LINK) 1111 continue; 1112 bfe_cam_write(sc, 1113 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 1114 } 1115 IF_ADDR_UNLOCK(ifp); 1116 } 1117 1118 CSR_WRITE_4(sc, BFE_RXCONF, val); 1119 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 1120 } 1121 1122 static void 1123 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1124 { 1125 struct bfe_dmamap_arg *ctx; 1126 1127 if (error != 0) 1128 return; 1129 1130 KASSERT(nseg == 1, ("%s : %d segments returned!", __func__, nseg)); 1131 1132 ctx = (struct bfe_dmamap_arg *)arg; 1133 ctx->bfe_busaddr = segs[0].ds_addr; 1134 } 1135 1136 static void 1137 bfe_release_resources(struct bfe_softc *sc) 1138 { 1139 1140 if (sc->bfe_intrhand != NULL) 1141 bus_teardown_intr(sc->bfe_dev, sc->bfe_irq, sc->bfe_intrhand); 1142 1143 if (sc->bfe_irq != NULL) 1144 bus_release_resource(sc->bfe_dev, SYS_RES_IRQ, 0, sc->bfe_irq); 1145 1146 if (sc->bfe_res != NULL) 1147 bus_release_resource(sc->bfe_dev, SYS_RES_MEMORY, PCIR_BAR(0), 1148 sc->bfe_res); 1149 1150 if (sc->bfe_ifp != NULL) 1151 if_free(sc->bfe_ifp); 1152 } 1153 1154 static void 1155 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 1156 { 1157 long i; 1158 u_int16_t *ptr = (u_int16_t *)data; 1159 1160 for(i = 0; i < 128; i += 2) 1161 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 1162 } 1163 1164 static int 1165 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1166 u_long timeout, const int clear) 1167 { 1168 u_long i; 1169 1170 for (i = 0; i < timeout; i++) { 1171 u_int32_t val = CSR_READ_4(sc, reg); 1172 1173 if (clear && !(val & bit)) 1174 break; 1175 if (!clear && (val & bit)) 1176 break; 1177 DELAY(10); 1178 } 1179 if (i == timeout) { 1180 device_printf(sc->bfe_dev, 1181 "BUG! Timeout waiting for bit %08x of register " 1182 "%x to %s.\n", bit, reg, (clear ? "clear" : "set")); 1183 return (-1); 1184 } 1185 return (0); 1186 } 1187 1188 static int 1189 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1190 { 1191 int err; 1192 1193 /* Clear MII ISR */ 1194 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1195 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1196 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1197 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1198 (reg << BFE_MDIO_RA_SHIFT) | 1199 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1200 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1201 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1202 1203 return (err); 1204 } 1205 1206 static int 1207 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1208 { 1209 int status; 1210 1211 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1212 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1213 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1214 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1215 (reg << BFE_MDIO_RA_SHIFT) | 1216 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1217 (val & BFE_MDIO_DATA_DATA))); 1218 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1219 1220 return (status); 1221 } 1222 1223 /* 1224 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1225 * twice 1226 */ 1227 static int 1228 bfe_setupphy(struct bfe_softc *sc) 1229 { 1230 u_int32_t val; 1231 1232 /* Enable activity LED */ 1233 bfe_readphy(sc, 26, &val); 1234 bfe_writephy(sc, 26, val & 0x7fff); 1235 bfe_readphy(sc, 26, &val); 1236 1237 /* Enable traffic meter LED mode */ 1238 bfe_readphy(sc, 27, &val); 1239 bfe_writephy(sc, 27, val | (1 << 6)); 1240 1241 return (0); 1242 } 1243 1244 static void 1245 bfe_stats_update(struct bfe_softc *sc) 1246 { 1247 u_long reg; 1248 u_int32_t *val; 1249 1250 val = &sc->bfe_hwstats.tx_good_octets; 1251 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1252 *val++ += CSR_READ_4(sc, reg); 1253 } 1254 val = &sc->bfe_hwstats.rx_good_octets; 1255 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1256 *val++ += CSR_READ_4(sc, reg); 1257 } 1258 } 1259 1260 static void 1261 bfe_txeof(struct bfe_softc *sc) 1262 { 1263 struct bfe_tx_data *r; 1264 struct ifnet *ifp; 1265 int i, chipidx; 1266 1267 BFE_LOCK_ASSERT(sc); 1268 1269 ifp = sc->bfe_ifp; 1270 1271 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1272 chipidx /= sizeof(struct bfe_desc); 1273 1274 i = sc->bfe_tx_cons; 1275 if (i == chipidx) 1276 return; 1277 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 1278 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1279 /* Go through the mbufs and free those that have been transmitted */ 1280 for (; i != chipidx; BFE_INC(i, BFE_TX_LIST_CNT)) { 1281 r = &sc->bfe_tx_ring[i]; 1282 sc->bfe_tx_cnt--; 1283 if (r->bfe_mbuf == NULL) 1284 continue; 1285 bus_dmamap_sync(sc->bfe_txmbuf_tag, r->bfe_map, 1286 BUS_DMASYNC_POSTWRITE); 1287 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map); 1288 1289 ifp->if_opackets++; 1290 m_freem(r->bfe_mbuf); 1291 r->bfe_mbuf = NULL; 1292 } 1293 1294 if (i != sc->bfe_tx_cons) { 1295 /* we freed up some mbufs */ 1296 sc->bfe_tx_cons = i; 1297 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1298 } 1299 1300 if (sc->bfe_tx_cnt == 0) 1301 sc->bfe_watchdog_timer = 0; 1302 } 1303 1304 /* Pass a received packet up the stack */ 1305 static void 1306 bfe_rxeof(struct bfe_softc *sc) 1307 { 1308 struct mbuf *m; 1309 struct ifnet *ifp; 1310 struct bfe_rxheader *rxheader; 1311 struct bfe_rx_data *r; 1312 int cons, prog; 1313 u_int32_t status, current, len, flags; 1314 1315 BFE_LOCK_ASSERT(sc); 1316 cons = sc->bfe_rx_cons; 1317 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1318 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1319 1320 ifp = sc->bfe_ifp; 1321 1322 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 1323 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1324 1325 for (prog = 0; current != cons; prog++, 1326 BFE_INC(cons, BFE_RX_LIST_CNT)) { 1327 r = &sc->bfe_rx_ring[cons]; 1328 m = r->bfe_mbuf; 1329 /* 1330 * Rx status should be read from mbuf such that we can't 1331 * delay bus_dmamap_sync(9). This hardware limiation 1332 * results in inefficent mbuf usage as bfe(4) couldn't 1333 * reuse mapped buffer from errored frame. 1334 */ 1335 if (bfe_list_newbuf(sc, cons) != 0) { 1336 ifp->if_iqdrops++; 1337 bfe_discard_buf(sc, cons); 1338 continue; 1339 } 1340 rxheader = mtod(m, struct bfe_rxheader*); 1341 len = le16toh(rxheader->len); 1342 flags = le16toh(rxheader->flags); 1343 1344 /* Remove CRC bytes. */ 1345 len -= ETHER_CRC_LEN; 1346 1347 /* flag an error and try again */ 1348 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1349 ifp->if_ierrors++; 1350 if (flags & BFE_RX_FLAG_SERR) 1351 ifp->if_collisions++; 1352 m_freem(m); 1353 continue; 1354 } 1355 1356 /* Make sure to skip header bytes written by hardware. */ 1357 m_adj(m, BFE_RX_OFFSET); 1358 m->m_len = m->m_pkthdr.len = len; 1359 1360 ifp->if_ipackets++; 1361 m->m_pkthdr.rcvif = ifp; 1362 BFE_UNLOCK(sc); 1363 (*ifp->if_input)(ifp, m); 1364 BFE_LOCK(sc); 1365 } 1366 1367 if (prog > 0) { 1368 sc->bfe_rx_cons = cons; 1369 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 1370 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1371 } 1372 } 1373 1374 static void 1375 bfe_intr(void *xsc) 1376 { 1377 struct bfe_softc *sc = xsc; 1378 struct ifnet *ifp; 1379 u_int32_t istat, flag; 1380 1381 ifp = sc->bfe_ifp; 1382 1383 BFE_LOCK(sc); 1384 1385 istat = CSR_READ_4(sc, BFE_ISTAT); 1386 1387 /* 1388 * Defer unsolicited interrupts - This is necessary because setting the 1389 * chips interrupt mask register to 0 doesn't actually stop the 1390 * interrupts 1391 */ 1392 istat &= BFE_IMASK_DEF; 1393 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1394 CSR_READ_4(sc, BFE_ISTAT); 1395 1396 /* not expecting this interrupt, disregard it */ 1397 if (istat == 0 || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1398 BFE_UNLOCK(sc); 1399 return; 1400 } 1401 1402 if (istat & BFE_ISTAT_ERRORS) { 1403 1404 if (istat & BFE_ISTAT_DSCE) { 1405 device_printf(sc->bfe_dev, "Descriptor Error\n"); 1406 bfe_stop(sc); 1407 BFE_UNLOCK(sc); 1408 return; 1409 } 1410 1411 if (istat & BFE_ISTAT_DPE) { 1412 device_printf(sc->bfe_dev, 1413 "Descriptor Protocol Error\n"); 1414 bfe_stop(sc); 1415 BFE_UNLOCK(sc); 1416 return; 1417 } 1418 1419 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1420 if (flag & BFE_STAT_EMASK) 1421 ifp->if_oerrors++; 1422 1423 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1424 if (flag & BFE_RX_FLAG_ERRORS) 1425 ifp->if_ierrors++; 1426 1427 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1428 bfe_init_locked(sc); 1429 } 1430 1431 /* A packet was received */ 1432 if (istat & BFE_ISTAT_RX) 1433 bfe_rxeof(sc); 1434 1435 /* A packet was sent */ 1436 if (istat & BFE_ISTAT_TX) 1437 bfe_txeof(sc); 1438 1439 /* We have packets pending, fire them out */ 1440 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1441 bfe_start_locked(ifp); 1442 1443 BFE_UNLOCK(sc); 1444 } 1445 1446 static int 1447 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head) 1448 { 1449 struct bfe_desc *d; 1450 struct bfe_tx_data *r, *r1; 1451 struct mbuf *m; 1452 bus_dmamap_t map; 1453 bus_dma_segment_t txsegs[BFE_MAXTXSEGS]; 1454 uint32_t cur, si; 1455 int error, i, nsegs; 1456 1457 BFE_LOCK_ASSERT(sc); 1458 1459 M_ASSERTPKTHDR((*m_head)); 1460 1461 si = cur = sc->bfe_tx_prod; 1462 r = &sc->bfe_tx_ring[cur]; 1463 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, *m_head, 1464 txsegs, &nsegs, 0); 1465 if (error == EFBIG) { 1466 m = m_collapse(*m_head, M_DONTWAIT, BFE_MAXTXSEGS); 1467 if (m == NULL) { 1468 m_freem(*m_head); 1469 *m_head = NULL; 1470 return (ENOMEM); 1471 } 1472 *m_head = m; 1473 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, 1474 *m_head, txsegs, &nsegs, 0); 1475 if (error != 0) { 1476 m_freem(*m_head); 1477 *m_head = NULL; 1478 return (error); 1479 } 1480 } else if (error != 0) 1481 return (error); 1482 if (nsegs == 0) { 1483 m_freem(*m_head); 1484 *m_head = NULL; 1485 return (EIO); 1486 } 1487 1488 if (sc->bfe_tx_cnt + nsegs > BFE_TX_LIST_CNT - 1) { 1489 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map); 1490 return (ENOBUFS); 1491 } 1492 1493 for (i = 0; i < nsegs; i++) { 1494 d = &sc->bfe_tx_list[cur]; 1495 d->bfe_ctrl = htole32(txsegs[i].ds_len & BFE_DESC_LEN); 1496 d->bfe_ctrl |= htole32(BFE_DESC_IOC); 1497 if (cur == BFE_TX_LIST_CNT - 1) 1498 /* 1499 * Tell the chip to wrap to the start of 1500 * the descriptor list. 1501 */ 1502 d->bfe_ctrl |= htole32(BFE_DESC_EOT); 1503 /* The chip needs all addresses to be added to BFE_PCI_DMA. */ 1504 d->bfe_addr = htole32(BFE_ADDR_LO(txsegs[i].ds_addr) + 1505 BFE_PCI_DMA); 1506 BFE_INC(cur, BFE_TX_LIST_CNT); 1507 } 1508 1509 /* Update producer index. */ 1510 sc->bfe_tx_prod = cur; 1511 1512 /* Set EOF on the last descriptor. */ 1513 cur = (cur + BFE_TX_LIST_CNT - 1) % BFE_TX_LIST_CNT; 1514 d = &sc->bfe_tx_list[cur]; 1515 d->bfe_ctrl |= htole32(BFE_DESC_EOF); 1516 1517 /* Lastly set SOF on the first descriptor to avoid races. */ 1518 d = &sc->bfe_tx_list[si]; 1519 d->bfe_ctrl |= htole32(BFE_DESC_SOF); 1520 1521 r1 = &sc->bfe_tx_ring[cur]; 1522 map = r->bfe_map; 1523 r->bfe_map = r1->bfe_map; 1524 r1->bfe_map = map; 1525 r1->bfe_mbuf = *m_head; 1526 sc->bfe_tx_cnt += nsegs; 1527 1528 bus_dmamap_sync(sc->bfe_txmbuf_tag, map, BUS_DMASYNC_PREWRITE); 1529 1530 return (0); 1531 } 1532 1533 /* 1534 * Set up to transmit a packet. 1535 */ 1536 static void 1537 bfe_start(struct ifnet *ifp) 1538 { 1539 BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1540 bfe_start_locked(ifp); 1541 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1542 } 1543 1544 /* 1545 * Set up to transmit a packet. The softc is already locked. 1546 */ 1547 static void 1548 bfe_start_locked(struct ifnet *ifp) 1549 { 1550 struct bfe_softc *sc; 1551 struct mbuf *m_head; 1552 int queued; 1553 1554 sc = ifp->if_softc; 1555 1556 BFE_LOCK_ASSERT(sc); 1557 1558 /* 1559 * Not much point trying to send if the link is down 1560 * or we have nothing to send. 1561 */ 1562 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1563 IFF_DRV_RUNNING || (sc->bfe_flags & BFE_FLAG_LINK) == 0) 1564 return; 1565 1566 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1567 sc->bfe_tx_cnt < BFE_TX_LIST_CNT - 1;) { 1568 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1569 if (m_head == NULL) 1570 break; 1571 1572 /* 1573 * Pack the data into the tx ring. If we dont have 1574 * enough room, let the chip drain the ring. 1575 */ 1576 if (bfe_encap(sc, &m_head)) { 1577 if (m_head == NULL) 1578 break; 1579 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1580 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1581 break; 1582 } 1583 1584 queued++; 1585 1586 /* 1587 * If there's a BPF listener, bounce a copy of this frame 1588 * to him. 1589 */ 1590 BPF_MTAP(ifp, m_head); 1591 } 1592 1593 if (queued) { 1594 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 1595 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1596 /* Transmit - twice due to apparent hardware bug */ 1597 CSR_WRITE_4(sc, BFE_DMATX_PTR, 1598 sc->bfe_tx_prod * sizeof(struct bfe_desc)); 1599 /* 1600 * XXX It seems the following write is not necessary 1601 * to kick Tx command. What might be required would be 1602 * a way flushing PCI posted write. Reading the register 1603 * back ensures the flush operation. In addition, 1604 * hardware will execute PCI posted write in the long 1605 * run and watchdog timer for the kick command was set 1606 * to 5 seconds. Therefore I think the second write 1607 * access is not necessary or could be replaced with 1608 * read operation. 1609 */ 1610 CSR_WRITE_4(sc, BFE_DMATX_PTR, 1611 sc->bfe_tx_prod * sizeof(struct bfe_desc)); 1612 1613 /* 1614 * Set a timeout in case the chip goes out to lunch. 1615 */ 1616 sc->bfe_watchdog_timer = 5; 1617 } 1618 } 1619 1620 static void 1621 bfe_init(void *xsc) 1622 { 1623 BFE_LOCK((struct bfe_softc *)xsc); 1624 bfe_init_locked(xsc); 1625 BFE_UNLOCK((struct bfe_softc *)xsc); 1626 } 1627 1628 static void 1629 bfe_init_locked(void *xsc) 1630 { 1631 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1632 struct ifnet *ifp = sc->bfe_ifp; 1633 struct mii_data *mii; 1634 1635 BFE_LOCK_ASSERT(sc); 1636 1637 mii = device_get_softc(sc->bfe_miibus); 1638 1639 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1640 return; 1641 1642 bfe_stop(sc); 1643 bfe_chip_reset(sc); 1644 1645 if (bfe_list_rx_init(sc) == ENOBUFS) { 1646 device_printf(sc->bfe_dev, 1647 "%s: Not enough memory for list buffers\n", __func__); 1648 bfe_stop(sc); 1649 return; 1650 } 1651 bfe_list_tx_init(sc); 1652 1653 bfe_set_rx_mode(sc); 1654 1655 /* Enable the chip and core */ 1656 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1657 /* Enable interrupts */ 1658 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1659 1660 /* Clear link state and change media. */ 1661 sc->bfe_flags &= ~BFE_FLAG_LINK; 1662 mii_mediachg(mii); 1663 1664 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1665 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1666 1667 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1668 } 1669 1670 /* 1671 * Set media options. 1672 */ 1673 static int 1674 bfe_ifmedia_upd(struct ifnet *ifp) 1675 { 1676 struct bfe_softc *sc; 1677 struct mii_data *mii; 1678 int error; 1679 1680 sc = ifp->if_softc; 1681 BFE_LOCK(sc); 1682 1683 mii = device_get_softc(sc->bfe_miibus); 1684 if (mii->mii_instance) { 1685 struct mii_softc *miisc; 1686 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1687 miisc = LIST_NEXT(miisc, mii_list)) 1688 mii_phy_reset(miisc); 1689 } 1690 error = mii_mediachg(mii); 1691 BFE_UNLOCK(sc); 1692 1693 return (error); 1694 } 1695 1696 /* 1697 * Report current media status. 1698 */ 1699 static void 1700 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1701 { 1702 struct bfe_softc *sc = ifp->if_softc; 1703 struct mii_data *mii; 1704 1705 BFE_LOCK(sc); 1706 mii = device_get_softc(sc->bfe_miibus); 1707 mii_pollstat(mii); 1708 ifmr->ifm_active = mii->mii_media_active; 1709 ifmr->ifm_status = mii->mii_media_status; 1710 BFE_UNLOCK(sc); 1711 } 1712 1713 static int 1714 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1715 { 1716 struct bfe_softc *sc = ifp->if_softc; 1717 struct ifreq *ifr = (struct ifreq *) data; 1718 struct mii_data *mii; 1719 int error = 0; 1720 1721 switch (command) { 1722 case SIOCSIFFLAGS: 1723 BFE_LOCK(sc); 1724 if (ifp->if_flags & IFF_UP) { 1725 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1726 bfe_set_rx_mode(sc); 1727 else if ((sc->bfe_flags & BFE_FLAG_DETACH) == 0) 1728 bfe_init_locked(sc); 1729 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1730 bfe_stop(sc); 1731 BFE_UNLOCK(sc); 1732 break; 1733 case SIOCADDMULTI: 1734 case SIOCDELMULTI: 1735 BFE_LOCK(sc); 1736 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1737 bfe_set_rx_mode(sc); 1738 BFE_UNLOCK(sc); 1739 break; 1740 case SIOCGIFMEDIA: 1741 case SIOCSIFMEDIA: 1742 mii = device_get_softc(sc->bfe_miibus); 1743 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1744 break; 1745 default: 1746 error = ether_ioctl(ifp, command, data); 1747 break; 1748 } 1749 1750 return (error); 1751 } 1752 1753 static void 1754 bfe_watchdog(struct bfe_softc *sc) 1755 { 1756 struct ifnet *ifp; 1757 1758 BFE_LOCK_ASSERT(sc); 1759 1760 if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer) 1761 return; 1762 1763 ifp = sc->bfe_ifp; 1764 1765 device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n"); 1766 1767 ifp->if_oerrors++; 1768 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1769 bfe_init_locked(sc); 1770 1771 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1772 bfe_start_locked(ifp); 1773 } 1774 1775 static void 1776 bfe_tick(void *xsc) 1777 { 1778 struct bfe_softc *sc = xsc; 1779 struct mii_data *mii; 1780 1781 BFE_LOCK_ASSERT(sc); 1782 1783 mii = device_get_softc(sc->bfe_miibus); 1784 mii_tick(mii); 1785 bfe_stats_update(sc); 1786 bfe_watchdog(sc); 1787 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1788 } 1789 1790 /* 1791 * Stop the adapter and free any mbufs allocated to the 1792 * RX and TX lists. 1793 */ 1794 static void 1795 bfe_stop(struct bfe_softc *sc) 1796 { 1797 struct ifnet *ifp; 1798 1799 BFE_LOCK_ASSERT(sc); 1800 1801 ifp = sc->bfe_ifp; 1802 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1803 sc->bfe_flags &= ~BFE_FLAG_LINK; 1804 callout_stop(&sc->bfe_stat_co); 1805 sc->bfe_watchdog_timer = 0; 1806 1807 bfe_chip_halt(sc); 1808 bfe_tx_ring_free(sc); 1809 bfe_rx_ring_free(sc); 1810 }
Cache object: e398c0e95d2469d1d337c0df14918446
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