Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/bfe/if_bfe.c
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1 /*- 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/endian.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/mbuf.h> 38 #include <sys/module.h> 39 #include <sys/rman.h> 40 #include <sys/socket.h> 41 #include <sys/sockio.h> 42 43 #include <net/bpf.h> 44 #include <net/if.h> 45 #include <net/ethernet.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 #include <net/if_types.h> 49 #include <net/if_vlan_var.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcivar.h> 56 57 #include <machine/bus.h> 58 59 #include <dev/bfe/if_bfereg.h> 60 61 MODULE_DEPEND(bfe, pci, 1, 1, 1); 62 MODULE_DEPEND(bfe, ether, 1, 1, 1); 63 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 64 65 /* "device miibus" required. See GENERIC if you get errors here. */ 66 #include "miibus_if.h" 67 68 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 69 70 static struct bfe_type bfe_devs[] = { 71 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 72 "Broadcom BCM4401 Fast Ethernet" }, 73 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 74 "Broadcom BCM4401-B0 Fast Ethernet" }, 75 { 0, 0, NULL } 76 }; 77 78 static int bfe_probe (device_t); 79 static int bfe_attach (device_t); 80 static int bfe_detach (device_t); 81 static int bfe_suspend (device_t); 82 static int bfe_resume (device_t); 83 static void bfe_release_resources (struct bfe_softc *); 84 static void bfe_intr (void *); 85 static int bfe_encap (struct bfe_softc *, struct mbuf **); 86 static void bfe_start (struct ifnet *); 87 static void bfe_start_locked (struct ifnet *); 88 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 89 static void bfe_init (void *); 90 static void bfe_init_locked (void *); 91 static void bfe_stop (struct bfe_softc *); 92 static void bfe_watchdog (struct bfe_softc *); 93 static int bfe_shutdown (device_t); 94 static void bfe_tick (void *); 95 static void bfe_txeof (struct bfe_softc *); 96 static void bfe_rxeof (struct bfe_softc *); 97 static void bfe_set_rx_mode (struct bfe_softc *); 98 static int bfe_list_rx_init (struct bfe_softc *); 99 static void bfe_list_tx_init (struct bfe_softc *); 100 static void bfe_discard_buf (struct bfe_softc *, int); 101 static int bfe_list_newbuf (struct bfe_softc *, int); 102 static void bfe_rx_ring_free (struct bfe_softc *); 103 104 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 105 static int bfe_ifmedia_upd (struct ifnet *); 106 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 107 static int bfe_miibus_readreg (device_t, int, int); 108 static int bfe_miibus_writereg (device_t, int, int, int); 109 static void bfe_miibus_statchg (device_t); 110 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 111 u_long, const int); 112 static void bfe_get_config (struct bfe_softc *sc); 113 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 114 static void bfe_stats_update (struct bfe_softc *); 115 static void bfe_clear_stats (struct bfe_softc *); 116 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 117 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 118 static int bfe_resetphy (struct bfe_softc *); 119 static int bfe_setupphy (struct bfe_softc *); 120 static void bfe_chip_reset (struct bfe_softc *); 121 static void bfe_chip_halt (struct bfe_softc *); 122 static void bfe_core_reset (struct bfe_softc *); 123 static void bfe_core_disable (struct bfe_softc *); 124 static int bfe_dma_alloc (struct bfe_softc *); 125 static void bfe_dma_free (struct bfe_softc *sc); 126 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 127 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 128 129 static device_method_t bfe_methods[] = { 130 /* Device interface */ 131 DEVMETHOD(device_probe, bfe_probe), 132 DEVMETHOD(device_attach, bfe_attach), 133 DEVMETHOD(device_detach, bfe_detach), 134 DEVMETHOD(device_shutdown, bfe_shutdown), 135 DEVMETHOD(device_suspend, bfe_suspend), 136 DEVMETHOD(device_resume, bfe_resume), 137 138 /* bus interface */ 139 DEVMETHOD(bus_print_child, bus_generic_print_child), 140 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 141 142 /* MII interface */ 143 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 144 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 145 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 146 147 { 0, 0 } 148 }; 149 150 static driver_t bfe_driver = { 151 "bfe", 152 bfe_methods, 153 sizeof(struct bfe_softc) 154 }; 155 156 static devclass_t bfe_devclass; 157 158 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 159 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 160 161 /* 162 * Probe for a Broadcom 4401 chip. 163 */ 164 static int 165 bfe_probe(device_t dev) 166 { 167 struct bfe_type *t; 168 169 t = bfe_devs; 170 171 while (t->bfe_name != NULL) { 172 if (pci_get_vendor(dev) == t->bfe_vid && 173 pci_get_device(dev) == t->bfe_did) { 174 device_set_desc(dev, t->bfe_name); 175 return (BUS_PROBE_DEFAULT); 176 } 177 t++; 178 } 179 180 return (ENXIO); 181 } 182 183 struct bfe_dmamap_arg { 184 bus_addr_t bfe_busaddr; 185 }; 186 187 static int 188 bfe_dma_alloc(struct bfe_softc *sc) 189 { 190 struct bfe_dmamap_arg ctx; 191 struct bfe_rx_data *rd; 192 struct bfe_tx_data *td; 193 int error, i; 194 195 /* 196 * parent tag. Apparently the chip cannot handle any DMA address 197 * greater than 1GB. 198 */ 199 error = bus_dma_tag_create(bus_get_dma_tag(sc->bfe_dev), /* parent */ 200 1, 0, /* alignment, boundary */ 201 BFE_DMA_MAXADDR, /* lowaddr */ 202 BUS_SPACE_MAXADDR, /* highaddr */ 203 NULL, NULL, /* filter, filterarg */ 204 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 205 0, /* nsegments */ 206 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 207 0, /* flags */ 208 NULL, NULL, /* lockfunc, lockarg */ 209 &sc->bfe_parent_tag); 210 if (error != 0) { 211 device_printf(sc->bfe_dev, "cannot create parent DMA tag.\n"); 212 goto fail; 213 } 214 215 /* Create tag for Tx ring. */ 216 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 217 BFE_TX_RING_ALIGN, 0, /* alignment, boundary */ 218 BUS_SPACE_MAXADDR, /* lowaddr */ 219 BUS_SPACE_MAXADDR, /* highaddr */ 220 NULL, NULL, /* filter, filterarg */ 221 BFE_TX_LIST_SIZE, /* maxsize */ 222 1, /* nsegments */ 223 BFE_TX_LIST_SIZE, /* maxsegsize */ 224 0, /* flags */ 225 NULL, NULL, /* lockfunc, lockarg */ 226 &sc->bfe_tx_tag); 227 if (error != 0) { 228 device_printf(sc->bfe_dev, "cannot create Tx ring DMA tag.\n"); 229 goto fail; 230 } 231 232 /* Create tag for Rx ring. */ 233 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 234 BFE_RX_RING_ALIGN, 0, /* alignment, boundary */ 235 BUS_SPACE_MAXADDR, /* lowaddr */ 236 BUS_SPACE_MAXADDR, /* highaddr */ 237 NULL, NULL, /* filter, filterarg */ 238 BFE_RX_LIST_SIZE, /* maxsize */ 239 1, /* nsegments */ 240 BFE_RX_LIST_SIZE, /* maxsegsize */ 241 0, /* flags */ 242 NULL, NULL, /* lockfunc, lockarg */ 243 &sc->bfe_rx_tag); 244 if (error != 0) { 245 device_printf(sc->bfe_dev, "cannot create Rx ring DMA tag.\n"); 246 goto fail; 247 } 248 249 /* Create tag for Tx buffers. */ 250 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 251 1, 0, /* alignment, boundary */ 252 BUS_SPACE_MAXADDR, /* lowaddr */ 253 BUS_SPACE_MAXADDR, /* highaddr */ 254 NULL, NULL, /* filter, filterarg */ 255 MCLBYTES * BFE_MAXTXSEGS, /* maxsize */ 256 BFE_MAXTXSEGS, /* nsegments */ 257 MCLBYTES, /* maxsegsize */ 258 0, /* flags */ 259 NULL, NULL, /* lockfunc, lockarg */ 260 &sc->bfe_txmbuf_tag); 261 if (error != 0) { 262 device_printf(sc->bfe_dev, 263 "cannot create Tx buffer DMA tag.\n"); 264 goto fail; 265 } 266 267 /* Create tag for Rx buffers. */ 268 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 269 1, 0, /* alignment, boundary */ 270 BUS_SPACE_MAXADDR, /* lowaddr */ 271 BUS_SPACE_MAXADDR, /* highaddr */ 272 NULL, NULL, /* filter, filterarg */ 273 MCLBYTES, /* maxsize */ 274 1, /* nsegments */ 275 MCLBYTES, /* maxsegsize */ 276 0, /* flags */ 277 NULL, NULL, /* lockfunc, lockarg */ 278 &sc->bfe_rxmbuf_tag); 279 if (error != 0) { 280 device_printf(sc->bfe_dev, 281 "cannot create Rx buffer DMA tag.\n"); 282 goto fail; 283 } 284 285 /* Allocate DMA'able memory and load DMA map. */ 286 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 287 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_tx_map); 288 if (error != 0) { 289 device_printf(sc->bfe_dev, 290 "cannot allocate DMA'able memory for Tx ring.\n"); 291 goto fail; 292 } 293 ctx.bfe_busaddr = 0; 294 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 295 sc->bfe_tx_list, BFE_TX_LIST_SIZE, bfe_dma_map, &ctx, 296 BUS_DMA_NOWAIT); 297 if (error != 0 || ctx.bfe_busaddr == 0) { 298 device_printf(sc->bfe_dev, 299 "cannot load DMA'able memory for Tx ring.\n"); 300 goto fail; 301 } 302 sc->bfe_tx_dma = BFE_ADDR_LO(ctx.bfe_busaddr); 303 304 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 305 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_rx_map); 306 if (error != 0) { 307 device_printf(sc->bfe_dev, 308 "cannot allocate DMA'able memory for Rx ring.\n"); 309 goto fail; 310 } 311 ctx.bfe_busaddr = 0; 312 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 313 sc->bfe_rx_list, BFE_RX_LIST_SIZE, bfe_dma_map, &ctx, 314 BUS_DMA_NOWAIT); 315 if (error != 0 || ctx.bfe_busaddr == 0) { 316 device_printf(sc->bfe_dev, 317 "cannot load DMA'able memory for Rx ring.\n"); 318 goto fail; 319 } 320 sc->bfe_rx_dma = BFE_ADDR_LO(ctx.bfe_busaddr); 321 322 /* Create DMA maps for Tx buffers. */ 323 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 324 td = &sc->bfe_tx_ring[i]; 325 td->bfe_mbuf = NULL; 326 td->bfe_map = NULL; 327 error = bus_dmamap_create(sc->bfe_txmbuf_tag, 0, &td->bfe_map); 328 if (error != 0) { 329 device_printf(sc->bfe_dev, 330 "cannot create DMA map for Tx.\n"); 331 goto fail; 332 } 333 } 334 335 /* Create spare DMA map for Rx buffers. */ 336 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &sc->bfe_rx_sparemap); 337 if (error != 0) { 338 device_printf(sc->bfe_dev, "cannot create spare DMA map for Rx.\n"); 339 goto fail; 340 } 341 /* Create DMA maps for Rx buffers. */ 342 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 343 rd = &sc->bfe_rx_ring[i]; 344 rd->bfe_mbuf = NULL; 345 rd->bfe_map = NULL; 346 rd->bfe_ctrl = 0; 347 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &rd->bfe_map); 348 if (error != 0) { 349 device_printf(sc->bfe_dev, 350 "cannot create DMA map for Rx.\n"); 351 goto fail; 352 } 353 } 354 355 fail: 356 return (error); 357 } 358 359 static void 360 bfe_dma_free(struct bfe_softc *sc) 361 { 362 struct bfe_tx_data *td; 363 struct bfe_rx_data *rd; 364 int i; 365 366 /* Tx ring. */ 367 if (sc->bfe_tx_tag != NULL) { 368 if (sc->bfe_tx_map != NULL) 369 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 370 if (sc->bfe_tx_map != NULL && sc->bfe_tx_list != NULL) 371 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 372 sc->bfe_tx_map); 373 sc->bfe_tx_map = NULL; 374 sc->bfe_tx_list = NULL; 375 bus_dma_tag_destroy(sc->bfe_tx_tag); 376 sc->bfe_tx_tag = NULL; 377 } 378 379 /* Rx ring. */ 380 if (sc->bfe_rx_tag != NULL) { 381 if (sc->bfe_rx_map != NULL) 382 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 383 if (sc->bfe_rx_map != NULL && sc->bfe_rx_list != NULL) 384 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 385 sc->bfe_rx_map); 386 sc->bfe_rx_map = NULL; 387 sc->bfe_rx_list = NULL; 388 bus_dma_tag_destroy(sc->bfe_rx_tag); 389 sc->bfe_rx_tag = NULL; 390 } 391 392 /* Tx buffers. */ 393 if (sc->bfe_txmbuf_tag != NULL) { 394 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 395 td = &sc->bfe_tx_ring[i]; 396 if (td->bfe_map != NULL) { 397 bus_dmamap_destroy(sc->bfe_txmbuf_tag, 398 td->bfe_map); 399 td->bfe_map = NULL; 400 } 401 } 402 bus_dma_tag_destroy(sc->bfe_txmbuf_tag); 403 sc->bfe_txmbuf_tag = NULL; 404 } 405 406 /* Rx buffers. */ 407 if (sc->bfe_rxmbuf_tag != NULL) { 408 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 409 rd = &sc->bfe_rx_ring[i]; 410 if (rd->bfe_map != NULL) { 411 bus_dmamap_destroy(sc->bfe_rxmbuf_tag, 412 rd->bfe_map); 413 rd->bfe_map = NULL; 414 } 415 } 416 if (sc->bfe_rx_sparemap != NULL) { 417 bus_dmamap_destroy(sc->bfe_rxmbuf_tag, 418 sc->bfe_rx_sparemap); 419 sc->bfe_rx_sparemap = NULL; 420 } 421 bus_dma_tag_destroy(sc->bfe_rxmbuf_tag); 422 sc->bfe_rxmbuf_tag = NULL; 423 } 424 425 if (sc->bfe_parent_tag != NULL) { 426 bus_dma_tag_destroy(sc->bfe_parent_tag); 427 sc->bfe_parent_tag = NULL; 428 } 429 } 430 431 static int 432 bfe_attach(device_t dev) 433 { 434 struct ifnet *ifp = NULL; 435 struct bfe_softc *sc; 436 int error = 0, rid; 437 438 sc = device_get_softc(dev); 439 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 440 MTX_DEF); 441 callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0); 442 443 sc->bfe_dev = dev; 444 445 /* 446 * Map control/status registers. 447 */ 448 pci_enable_busmaster(dev); 449 450 rid = PCIR_BAR(0); 451 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 452 RF_ACTIVE); 453 if (sc->bfe_res == NULL) { 454 device_printf(dev, "couldn't map memory\n"); 455 error = ENXIO; 456 goto fail; 457 } 458 459 /* Allocate interrupt */ 460 rid = 0; 461 462 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 463 RF_SHAREABLE | RF_ACTIVE); 464 if (sc->bfe_irq == NULL) { 465 device_printf(dev, "couldn't map interrupt\n"); 466 error = ENXIO; 467 goto fail; 468 } 469 470 if (bfe_dma_alloc(sc) != 0) { 471 device_printf(dev, "failed to allocate DMA resources\n"); 472 error = ENXIO; 473 goto fail; 474 } 475 476 /* Set up ifnet structure */ 477 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER); 478 if (ifp == NULL) { 479 device_printf(dev, "failed to if_alloc()\n"); 480 error = ENOSPC; 481 goto fail; 482 } 483 ifp->if_softc = sc; 484 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 485 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 486 ifp->if_ioctl = bfe_ioctl; 487 ifp->if_start = bfe_start; 488 ifp->if_init = bfe_init; 489 ifp->if_mtu = ETHERMTU; 490 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 491 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 492 IFQ_SET_READY(&ifp->if_snd); 493 494 bfe_get_config(sc); 495 496 /* Reset the chip and turn on the PHY */ 497 BFE_LOCK(sc); 498 bfe_chip_reset(sc); 499 BFE_UNLOCK(sc); 500 501 if (mii_phy_probe(dev, &sc->bfe_miibus, 502 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 503 device_printf(dev, "MII without any PHY!\n"); 504 error = ENXIO; 505 goto fail; 506 } 507 508 ether_ifattach(ifp, sc->bfe_enaddr); 509 510 /* 511 * Tell the upper layer(s) we support long frames. 512 */ 513 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 514 ifp->if_capabilities |= IFCAP_VLAN_MTU; 515 ifp->if_capenable |= IFCAP_VLAN_MTU; 516 517 /* 518 * Hook interrupt last to avoid having to lock softc 519 */ 520 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 521 NULL, bfe_intr, sc, &sc->bfe_intrhand); 522 523 if (error) { 524 device_printf(dev, "couldn't set up irq\n"); 525 goto fail; 526 } 527 fail: 528 if (error != 0) 529 bfe_detach(dev); 530 return (error); 531 } 532 533 static int 534 bfe_detach(device_t dev) 535 { 536 struct bfe_softc *sc; 537 struct ifnet *ifp; 538 539 sc = device_get_softc(dev); 540 541 ifp = sc->bfe_ifp; 542 543 if (device_is_attached(dev)) { 544 BFE_LOCK(sc); 545 sc->bfe_flags |= BFE_FLAG_DETACH; 546 bfe_stop(sc); 547 BFE_UNLOCK(sc); 548 callout_drain(&sc->bfe_stat_co); 549 if (ifp != NULL) 550 ether_ifdetach(ifp); 551 } 552 553 BFE_LOCK(sc); 554 bfe_chip_reset(sc); 555 BFE_UNLOCK(sc); 556 557 bus_generic_detach(dev); 558 if (sc->bfe_miibus != NULL) 559 device_delete_child(dev, sc->bfe_miibus); 560 561 bfe_release_resources(sc); 562 bfe_dma_free(sc); 563 mtx_destroy(&sc->bfe_mtx); 564 565 return (0); 566 } 567 568 /* 569 * Stop all chip I/O so that the kernel's probe routines don't 570 * get confused by errant DMAs when rebooting. 571 */ 572 static int 573 bfe_shutdown(device_t dev) 574 { 575 struct bfe_softc *sc; 576 577 sc = device_get_softc(dev); 578 BFE_LOCK(sc); 579 bfe_stop(sc); 580 581 BFE_UNLOCK(sc); 582 583 return (0); 584 } 585 586 static int 587 bfe_suspend(device_t dev) 588 { 589 struct bfe_softc *sc; 590 591 sc = device_get_softc(dev); 592 BFE_LOCK(sc); 593 bfe_stop(sc); 594 BFE_UNLOCK(sc); 595 596 return (0); 597 } 598 599 static int 600 bfe_resume(device_t dev) 601 { 602 struct bfe_softc *sc; 603 struct ifnet *ifp; 604 605 sc = device_get_softc(dev); 606 ifp = sc->bfe_ifp; 607 BFE_LOCK(sc); 608 bfe_chip_reset(sc); 609 if (ifp->if_flags & IFF_UP) { 610 bfe_init_locked(sc); 611 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 612 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 613 bfe_start_locked(ifp); 614 } 615 BFE_UNLOCK(sc); 616 617 return (0); 618 } 619 620 static int 621 bfe_miibus_readreg(device_t dev, int phy, int reg) 622 { 623 struct bfe_softc *sc; 624 u_int32_t ret; 625 626 sc = device_get_softc(dev); 627 if (phy != sc->bfe_phyaddr) 628 return (0); 629 bfe_readphy(sc, reg, &ret); 630 631 return (ret); 632 } 633 634 static int 635 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 636 { 637 struct bfe_softc *sc; 638 639 sc = device_get_softc(dev); 640 if (phy != sc->bfe_phyaddr) 641 return (0); 642 bfe_writephy(sc, reg, val); 643 644 return (0); 645 } 646 647 static void 648 bfe_miibus_statchg(device_t dev) 649 { 650 struct bfe_softc *sc; 651 struct mii_data *mii; 652 u_int32_t val, flow; 653 654 sc = device_get_softc(dev); 655 mii = device_get_softc(sc->bfe_miibus); 656 657 sc->bfe_flags &= ~BFE_FLAG_LINK; 658 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 659 (IFM_ACTIVE | IFM_AVALID)) { 660 switch (IFM_SUBTYPE(mii->mii_media_active)) { 661 case IFM_10_T: 662 case IFM_100_TX: 663 sc->bfe_flags |= BFE_FLAG_LINK; 664 break; 665 default: 666 break; 667 } 668 } 669 670 /* XXX Should stop Rx/Tx engine prior to touching MAC. */ 671 val = CSR_READ_4(sc, BFE_TX_CTRL); 672 val &= ~BFE_TX_DUPLEX; 673 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 674 val |= BFE_TX_DUPLEX; 675 flow = 0; 676 #ifdef notyet 677 flow = CSR_READ_4(sc, BFE_RXCONF); 678 flow &= ~BFE_RXCONF_FLOW; 679 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 680 IFM_ETH_RXPAUSE) != 0) 681 flow |= BFE_RXCONF_FLOW; 682 CSR_WRITE_4(sc, BFE_RXCONF, flow); 683 /* 684 * It seems that the hardware has Tx pause issues 685 * so enable only Rx pause. 686 */ 687 flow = CSR_READ_4(sc, BFE_MAC_FLOW); 688 flow &= ~BFE_FLOW_PAUSE_ENAB; 689 CSR_WRITE_4(sc, BFE_MAC_FLOW, flow); 690 #endif 691 } 692 CSR_WRITE_4(sc, BFE_TX_CTRL, val); 693 } 694 695 static void 696 bfe_tx_ring_free(struct bfe_softc *sc) 697 { 698 int i; 699 700 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 701 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 702 bus_dmamap_sync(sc->bfe_txmbuf_tag, 703 sc->bfe_tx_ring[i].bfe_map, BUS_DMASYNC_POSTWRITE); 704 bus_dmamap_unload(sc->bfe_txmbuf_tag, 705 sc->bfe_tx_ring[i].bfe_map); 706 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 707 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 708 } 709 } 710 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 711 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 712 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 713 } 714 715 static void 716 bfe_rx_ring_free(struct bfe_softc *sc) 717 { 718 int i; 719 720 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 721 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 722 bus_dmamap_sync(sc->bfe_rxmbuf_tag, 723 sc->bfe_rx_ring[i].bfe_map, BUS_DMASYNC_POSTREAD); 724 bus_dmamap_unload(sc->bfe_rxmbuf_tag, 725 sc->bfe_rx_ring[i].bfe_map); 726 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 727 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 728 } 729 } 730 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 731 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 732 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 733 } 734 735 static int 736 bfe_list_rx_init(struct bfe_softc *sc) 737 { 738 struct bfe_rx_data *rd; 739 int i; 740 741 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 742 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 743 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 744 rd = &sc->bfe_rx_ring[i]; 745 rd->bfe_mbuf = NULL; 746 rd->bfe_ctrl = 0; 747 if (bfe_list_newbuf(sc, i) != 0) 748 return (ENOBUFS); 749 } 750 751 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 752 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 753 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 754 755 return (0); 756 } 757 758 static void 759 bfe_list_tx_init(struct bfe_softc *sc) 760 { 761 int i; 762 763 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 764 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 765 for (i = 0; i < BFE_TX_LIST_CNT; i++) 766 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 767 768 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 769 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 770 } 771 772 static void 773 bfe_discard_buf(struct bfe_softc *sc, int c) 774 { 775 struct bfe_rx_data *r; 776 struct bfe_desc *d; 777 778 r = &sc->bfe_rx_ring[c]; 779 d = &sc->bfe_rx_list[c]; 780 d->bfe_ctrl = htole32(r->bfe_ctrl); 781 } 782 783 static int 784 bfe_list_newbuf(struct bfe_softc *sc, int c) 785 { 786 struct bfe_rxheader *rx_header; 787 struct bfe_desc *d; 788 struct bfe_rx_data *r; 789 struct mbuf *m; 790 bus_dma_segment_t segs[1]; 791 bus_dmamap_t map; 792 u_int32_t ctrl; 793 int nsegs; 794 795 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 796 m->m_len = m->m_pkthdr.len = MCLBYTES; 797 798 if (bus_dmamap_load_mbuf_sg(sc->bfe_rxmbuf_tag, sc->bfe_rx_sparemap, 799 m, segs, &nsegs, 0) != 0) { 800 m_freem(m); 801 return (ENOBUFS); 802 } 803 804 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 805 r = &sc->bfe_rx_ring[c]; 806 if (r->bfe_mbuf != NULL) { 807 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, 808 BUS_DMASYNC_POSTREAD); 809 bus_dmamap_unload(sc->bfe_rxmbuf_tag, r->bfe_map); 810 } 811 map = r->bfe_map; 812 r->bfe_map = sc->bfe_rx_sparemap; 813 sc->bfe_rx_sparemap = map; 814 r->bfe_mbuf = m; 815 816 rx_header = mtod(m, struct bfe_rxheader *); 817 rx_header->len = 0; 818 rx_header->flags = 0; 819 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, BUS_DMASYNC_PREREAD); 820 821 ctrl = segs[0].ds_len & BFE_DESC_LEN; 822 KASSERT(ctrl > ETHER_MAX_LEN + 32, ("%s: buffer size too small(%d)!", 823 __func__, ctrl)); 824 if (c == BFE_RX_LIST_CNT - 1) 825 ctrl |= BFE_DESC_EOT; 826 r->bfe_ctrl = ctrl; 827 828 d = &sc->bfe_rx_list[c]; 829 d->bfe_ctrl = htole32(ctrl); 830 /* The chip needs all addresses to be added to BFE_PCI_DMA. */ 831 d->bfe_addr = htole32(BFE_ADDR_LO(segs[0].ds_addr) + BFE_PCI_DMA); 832 833 return (0); 834 } 835 836 static void 837 bfe_get_config(struct bfe_softc *sc) 838 { 839 u_int8_t eeprom[128]; 840 841 bfe_read_eeprom(sc, eeprom); 842 843 sc->bfe_enaddr[0] = eeprom[79]; 844 sc->bfe_enaddr[1] = eeprom[78]; 845 sc->bfe_enaddr[2] = eeprom[81]; 846 sc->bfe_enaddr[3] = eeprom[80]; 847 sc->bfe_enaddr[4] = eeprom[83]; 848 sc->bfe_enaddr[5] = eeprom[82]; 849 850 sc->bfe_phyaddr = eeprom[90] & 0x1f; 851 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 852 853 sc->bfe_core_unit = 0; 854 sc->bfe_dma_offset = BFE_PCI_DMA; 855 } 856 857 static void 858 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 859 { 860 u_int32_t bar_orig, pci_rev, val; 861 862 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 863 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 864 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 865 866 val = CSR_READ_4(sc, BFE_SBINTVEC); 867 val |= cores; 868 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 869 870 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 871 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 872 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 873 874 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 875 } 876 877 static void 878 bfe_clear_stats(struct bfe_softc *sc) 879 { 880 u_long reg; 881 882 BFE_LOCK_ASSERT(sc); 883 884 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 885 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 886 CSR_READ_4(sc, reg); 887 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 888 CSR_READ_4(sc, reg); 889 } 890 891 static int 892 bfe_resetphy(struct bfe_softc *sc) 893 { 894 u_int32_t val; 895 896 bfe_writephy(sc, 0, BMCR_RESET); 897 DELAY(100); 898 bfe_readphy(sc, 0, &val); 899 if (val & BMCR_RESET) { 900 device_printf(sc->bfe_dev, "PHY Reset would not complete.\n"); 901 return (ENXIO); 902 } 903 return (0); 904 } 905 906 static void 907 bfe_chip_halt(struct bfe_softc *sc) 908 { 909 BFE_LOCK_ASSERT(sc); 910 /* disable interrupts - not that it actually does..*/ 911 CSR_WRITE_4(sc, BFE_IMASK, 0); 912 CSR_READ_4(sc, BFE_IMASK); 913 914 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 915 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 916 917 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 918 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 919 DELAY(10); 920 } 921 922 static void 923 bfe_chip_reset(struct bfe_softc *sc) 924 { 925 u_int32_t val; 926 927 BFE_LOCK_ASSERT(sc); 928 929 /* Set the interrupt vector for the enet core */ 930 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 931 932 /* is core up? */ 933 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 934 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 935 if (val == BFE_CLOCK) { 936 /* It is, so shut it down */ 937 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 938 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 939 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 940 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 941 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 942 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 943 100, 0); 944 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 945 } 946 947 bfe_core_reset(sc); 948 bfe_clear_stats(sc); 949 950 /* 951 * We want the phy registers to be accessible even when 952 * the driver is "downed" so initialize MDC preamble, frequency, 953 * and whether internal or external phy here. 954 */ 955 956 /* 4402 has 62.5Mhz SB clock and internal phy */ 957 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 958 959 /* Internal or external PHY? */ 960 val = CSR_READ_4(sc, BFE_DEVCTRL); 961 if (!(val & BFE_IPP)) 962 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 963 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 964 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 965 DELAY(100); 966 } 967 968 /* Enable CRC32 generation and set proper LED modes */ 969 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 970 971 /* Reset or clear powerdown control bit */ 972 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 973 974 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 975 BFE_LAZY_FC_MASK)); 976 977 /* 978 * We don't want lazy interrupts, so just send them at 979 * the end of a frame, please 980 */ 981 BFE_OR(sc, BFE_RCV_LAZY, 0); 982 983 /* Set max lengths, accounting for VLAN tags */ 984 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 985 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 986 987 /* Set watermark XXX - magic */ 988 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 989 990 /* 991 * Initialise DMA channels 992 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 993 */ 994 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 995 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 996 997 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 998 BFE_RX_CTRL_ENABLE); 999 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 1000 1001 bfe_resetphy(sc); 1002 bfe_setupphy(sc); 1003 } 1004 1005 static void 1006 bfe_core_disable(struct bfe_softc *sc) 1007 { 1008 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 1009 return; 1010 1011 /* 1012 * Set reject, wait for it set, then wait for the core to stop 1013 * being busy, then set reset and reject and enable the clocks. 1014 */ 1015 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 1016 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 1017 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 1018 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 1019 BFE_RESET)); 1020 CSR_READ_4(sc, BFE_SBTMSLOW); 1021 DELAY(10); 1022 /* Leave reset and reject set */ 1023 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 1024 DELAY(10); 1025 } 1026 1027 static void 1028 bfe_core_reset(struct bfe_softc *sc) 1029 { 1030 u_int32_t val; 1031 1032 /* Disable the core */ 1033 bfe_core_disable(sc); 1034 1035 /* and bring it back up */ 1036 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 1037 CSR_READ_4(sc, BFE_SBTMSLOW); 1038 DELAY(10); 1039 1040 /* Chip bug, clear SERR, IB and TO if they are set. */ 1041 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 1042 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 1043 val = CSR_READ_4(sc, BFE_SBIMSTATE); 1044 if (val & (BFE_IBE | BFE_TO)) 1045 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 1046 1047 /* Clear reset and allow it to move through the core */ 1048 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 1049 CSR_READ_4(sc, BFE_SBTMSLOW); 1050 DELAY(10); 1051 1052 /* Leave the clock set */ 1053 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 1054 CSR_READ_4(sc, BFE_SBTMSLOW); 1055 DELAY(10); 1056 } 1057 1058 static void 1059 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 1060 { 1061 u_int32_t val; 1062 1063 val = ((u_int32_t) data[2]) << 24; 1064 val |= ((u_int32_t) data[3]) << 16; 1065 val |= ((u_int32_t) data[4]) << 8; 1066 val |= ((u_int32_t) data[5]); 1067 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 1068 val = (BFE_CAM_HI_VALID | 1069 (((u_int32_t) data[0]) << 8) | 1070 (((u_int32_t) data[1]))); 1071 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 1072 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 1073 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 1074 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 1075 } 1076 1077 static void 1078 bfe_set_rx_mode(struct bfe_softc *sc) 1079 { 1080 struct ifnet *ifp = sc->bfe_ifp; 1081 struct ifmultiaddr *ifma; 1082 u_int32_t val; 1083 int i = 0; 1084 1085 val = CSR_READ_4(sc, BFE_RXCONF); 1086 1087 if (ifp->if_flags & IFF_PROMISC) 1088 val |= BFE_RXCONF_PROMISC; 1089 else 1090 val &= ~BFE_RXCONF_PROMISC; 1091 1092 if (ifp->if_flags & IFF_BROADCAST) 1093 val &= ~BFE_RXCONF_DBCAST; 1094 else 1095 val |= BFE_RXCONF_DBCAST; 1096 1097 1098 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 1099 bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++); 1100 1101 if (ifp->if_flags & IFF_ALLMULTI) 1102 val |= BFE_RXCONF_ALLMULTI; 1103 else { 1104 val &= ~BFE_RXCONF_ALLMULTI; 1105 IF_ADDR_LOCK(ifp); 1106 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1107 if (ifma->ifma_addr->sa_family != AF_LINK) 1108 continue; 1109 bfe_cam_write(sc, 1110 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 1111 } 1112 IF_ADDR_UNLOCK(ifp); 1113 } 1114 1115 CSR_WRITE_4(sc, BFE_RXCONF, val); 1116 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 1117 } 1118 1119 static void 1120 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1121 { 1122 struct bfe_dmamap_arg *ctx; 1123 1124 if (error != 0) 1125 return; 1126 1127 KASSERT(nseg == 1, ("%s : %d segments returned!", __func__, nseg)); 1128 1129 ctx = (struct bfe_dmamap_arg *)arg; 1130 ctx->bfe_busaddr = segs[0].ds_addr; 1131 } 1132 1133 static void 1134 bfe_release_resources(struct bfe_softc *sc) 1135 { 1136 1137 if (sc->bfe_intrhand != NULL) 1138 bus_teardown_intr(sc->bfe_dev, sc->bfe_irq, sc->bfe_intrhand); 1139 1140 if (sc->bfe_irq != NULL) 1141 bus_release_resource(sc->bfe_dev, SYS_RES_IRQ, 0, sc->bfe_irq); 1142 1143 if (sc->bfe_res != NULL) 1144 bus_release_resource(sc->bfe_dev, SYS_RES_MEMORY, PCIR_BAR(0), 1145 sc->bfe_res); 1146 1147 if (sc->bfe_ifp != NULL) 1148 if_free(sc->bfe_ifp); 1149 } 1150 1151 static void 1152 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 1153 { 1154 long i; 1155 u_int16_t *ptr = (u_int16_t *)data; 1156 1157 for(i = 0; i < 128; i += 2) 1158 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 1159 } 1160 1161 static int 1162 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1163 u_long timeout, const int clear) 1164 { 1165 u_long i; 1166 1167 for (i = 0; i < timeout; i++) { 1168 u_int32_t val = CSR_READ_4(sc, reg); 1169 1170 if (clear && !(val & bit)) 1171 break; 1172 if (!clear && (val & bit)) 1173 break; 1174 DELAY(10); 1175 } 1176 if (i == timeout) { 1177 device_printf(sc->bfe_dev, 1178 "BUG! Timeout waiting for bit %08x of register " 1179 "%x to %s.\n", bit, reg, (clear ? "clear" : "set")); 1180 return (-1); 1181 } 1182 return (0); 1183 } 1184 1185 static int 1186 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1187 { 1188 int err; 1189 1190 /* Clear MII ISR */ 1191 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1192 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1193 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1194 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1195 (reg << BFE_MDIO_RA_SHIFT) | 1196 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1197 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1198 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1199 1200 return (err); 1201 } 1202 1203 static int 1204 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1205 { 1206 int status; 1207 1208 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1209 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1210 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1211 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1212 (reg << BFE_MDIO_RA_SHIFT) | 1213 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1214 (val & BFE_MDIO_DATA_DATA))); 1215 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1216 1217 return (status); 1218 } 1219 1220 /* 1221 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1222 * twice 1223 */ 1224 static int 1225 bfe_setupphy(struct bfe_softc *sc) 1226 { 1227 u_int32_t val; 1228 1229 /* Enable activity LED */ 1230 bfe_readphy(sc, 26, &val); 1231 bfe_writephy(sc, 26, val & 0x7fff); 1232 bfe_readphy(sc, 26, &val); 1233 1234 /* Enable traffic meter LED mode */ 1235 bfe_readphy(sc, 27, &val); 1236 bfe_writephy(sc, 27, val | (1 << 6)); 1237 1238 return (0); 1239 } 1240 1241 static void 1242 bfe_stats_update(struct bfe_softc *sc) 1243 { 1244 u_long reg; 1245 u_int32_t *val; 1246 1247 val = &sc->bfe_hwstats.tx_good_octets; 1248 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1249 *val++ += CSR_READ_4(sc, reg); 1250 } 1251 val = &sc->bfe_hwstats.rx_good_octets; 1252 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1253 *val++ += CSR_READ_4(sc, reg); 1254 } 1255 } 1256 1257 static void 1258 bfe_txeof(struct bfe_softc *sc) 1259 { 1260 struct bfe_tx_data *r; 1261 struct ifnet *ifp; 1262 int i, chipidx; 1263 1264 BFE_LOCK_ASSERT(sc); 1265 1266 ifp = sc->bfe_ifp; 1267 1268 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1269 chipidx /= sizeof(struct bfe_desc); 1270 1271 i = sc->bfe_tx_cons; 1272 if (i == chipidx) 1273 return; 1274 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 1275 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1276 /* Go through the mbufs and free those that have been transmitted */ 1277 for (; i != chipidx; BFE_INC(i, BFE_TX_LIST_CNT)) { 1278 r = &sc->bfe_tx_ring[i]; 1279 sc->bfe_tx_cnt--; 1280 if (r->bfe_mbuf == NULL) 1281 continue; 1282 bus_dmamap_sync(sc->bfe_txmbuf_tag, r->bfe_map, 1283 BUS_DMASYNC_POSTWRITE); 1284 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map); 1285 1286 ifp->if_opackets++; 1287 m_freem(r->bfe_mbuf); 1288 r->bfe_mbuf = NULL; 1289 } 1290 1291 if (i != sc->bfe_tx_cons) { 1292 /* we freed up some mbufs */ 1293 sc->bfe_tx_cons = i; 1294 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1295 } 1296 1297 if (sc->bfe_tx_cnt == 0) 1298 sc->bfe_watchdog_timer = 0; 1299 } 1300 1301 /* Pass a received packet up the stack */ 1302 static void 1303 bfe_rxeof(struct bfe_softc *sc) 1304 { 1305 struct mbuf *m; 1306 struct ifnet *ifp; 1307 struct bfe_rxheader *rxheader; 1308 struct bfe_rx_data *r; 1309 int cons, prog; 1310 u_int32_t status, current, len, flags; 1311 1312 BFE_LOCK_ASSERT(sc); 1313 cons = sc->bfe_rx_cons; 1314 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1315 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1316 1317 ifp = sc->bfe_ifp; 1318 1319 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 1320 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1321 1322 for (prog = 0; current != cons; prog++, 1323 BFE_INC(cons, BFE_RX_LIST_CNT)) { 1324 r = &sc->bfe_rx_ring[cons]; 1325 m = r->bfe_mbuf; 1326 /* 1327 * Rx status should be read from mbuf such that we can't 1328 * delay bus_dmamap_sync(9). This hardware limiation 1329 * results in inefficent mbuf usage as bfe(4) couldn't 1330 * reuse mapped buffer from errored frame. 1331 */ 1332 if (bfe_list_newbuf(sc, cons) != 0) { 1333 ifp->if_iqdrops++; 1334 bfe_discard_buf(sc, cons); 1335 continue; 1336 } 1337 rxheader = mtod(m, struct bfe_rxheader*); 1338 len = le16toh(rxheader->len); 1339 flags = le16toh(rxheader->flags); 1340 1341 /* Remove CRC bytes. */ 1342 len -= ETHER_CRC_LEN; 1343 1344 /* flag an error and try again */ 1345 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1346 ifp->if_ierrors++; 1347 if (flags & BFE_RX_FLAG_SERR) 1348 ifp->if_collisions++; 1349 m_freem(m); 1350 continue; 1351 } 1352 1353 /* Make sure to skip header bytes written by hardware. */ 1354 m_adj(m, BFE_RX_OFFSET); 1355 m->m_len = m->m_pkthdr.len = len; 1356 1357 ifp->if_ipackets++; 1358 m->m_pkthdr.rcvif = ifp; 1359 BFE_UNLOCK(sc); 1360 (*ifp->if_input)(ifp, m); 1361 BFE_LOCK(sc); 1362 } 1363 1364 if (prog > 0) { 1365 sc->bfe_rx_cons = cons; 1366 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 1367 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1368 } 1369 } 1370 1371 static void 1372 bfe_intr(void *xsc) 1373 { 1374 struct bfe_softc *sc = xsc; 1375 struct ifnet *ifp; 1376 u_int32_t istat, flag; 1377 1378 ifp = sc->bfe_ifp; 1379 1380 BFE_LOCK(sc); 1381 1382 istat = CSR_READ_4(sc, BFE_ISTAT); 1383 1384 /* 1385 * Defer unsolicited interrupts - This is necessary because setting the 1386 * chips interrupt mask register to 0 doesn't actually stop the 1387 * interrupts 1388 */ 1389 istat &= BFE_IMASK_DEF; 1390 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1391 CSR_READ_4(sc, BFE_ISTAT); 1392 1393 /* not expecting this interrupt, disregard it */ 1394 if (istat == 0 || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1395 BFE_UNLOCK(sc); 1396 return; 1397 } 1398 1399 if (istat & BFE_ISTAT_ERRORS) { 1400 1401 if (istat & BFE_ISTAT_DSCE) { 1402 device_printf(sc->bfe_dev, "Descriptor Error\n"); 1403 bfe_stop(sc); 1404 BFE_UNLOCK(sc); 1405 return; 1406 } 1407 1408 if (istat & BFE_ISTAT_DPE) { 1409 device_printf(sc->bfe_dev, 1410 "Descriptor Protocol Error\n"); 1411 bfe_stop(sc); 1412 BFE_UNLOCK(sc); 1413 return; 1414 } 1415 1416 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1417 if (flag & BFE_STAT_EMASK) 1418 ifp->if_oerrors++; 1419 1420 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1421 if (flag & BFE_RX_FLAG_ERRORS) 1422 ifp->if_ierrors++; 1423 1424 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1425 bfe_init_locked(sc); 1426 } 1427 1428 /* A packet was received */ 1429 if (istat & BFE_ISTAT_RX) 1430 bfe_rxeof(sc); 1431 1432 /* A packet was sent */ 1433 if (istat & BFE_ISTAT_TX) 1434 bfe_txeof(sc); 1435 1436 /* We have packets pending, fire them out */ 1437 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1438 bfe_start_locked(ifp); 1439 1440 BFE_UNLOCK(sc); 1441 } 1442 1443 static int 1444 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head) 1445 { 1446 struct bfe_desc *d; 1447 struct bfe_tx_data *r, *r1; 1448 struct mbuf *m; 1449 bus_dmamap_t map; 1450 bus_dma_segment_t txsegs[BFE_MAXTXSEGS]; 1451 uint32_t cur, si; 1452 int error, i, nsegs; 1453 1454 BFE_LOCK_ASSERT(sc); 1455 1456 M_ASSERTPKTHDR((*m_head)); 1457 1458 si = cur = sc->bfe_tx_prod; 1459 r = &sc->bfe_tx_ring[cur]; 1460 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, *m_head, 1461 txsegs, &nsegs, 0); 1462 if (error == EFBIG) { 1463 m = m_collapse(*m_head, M_DONTWAIT, BFE_MAXTXSEGS); 1464 if (m == NULL) { 1465 m_freem(*m_head); 1466 *m_head = NULL; 1467 return (ENOMEM); 1468 } 1469 *m_head = m; 1470 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, 1471 *m_head, txsegs, &nsegs, 0); 1472 if (error != 0) { 1473 m_freem(*m_head); 1474 *m_head = NULL; 1475 return (error); 1476 } 1477 } else if (error != 0) 1478 return (error); 1479 if (nsegs == 0) { 1480 m_freem(*m_head); 1481 *m_head = NULL; 1482 return (EIO); 1483 } 1484 1485 if (sc->bfe_tx_cnt + nsegs > BFE_TX_LIST_CNT - 1) { 1486 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map); 1487 return (ENOBUFS); 1488 } 1489 1490 for (i = 0; i < nsegs; i++) { 1491 d = &sc->bfe_tx_list[cur]; 1492 d->bfe_ctrl = htole32(txsegs[i].ds_len & BFE_DESC_LEN); 1493 d->bfe_ctrl |= htole32(BFE_DESC_IOC); 1494 if (cur == BFE_TX_LIST_CNT - 1) 1495 /* 1496 * Tell the chip to wrap to the start of 1497 * the descriptor list. 1498 */ 1499 d->bfe_ctrl |= htole32(BFE_DESC_EOT); 1500 /* The chip needs all addresses to be added to BFE_PCI_DMA. */ 1501 d->bfe_addr = htole32(BFE_ADDR_LO(txsegs[i].ds_addr) + 1502 BFE_PCI_DMA); 1503 BFE_INC(cur, BFE_TX_LIST_CNT); 1504 } 1505 1506 /* Update producer index. */ 1507 sc->bfe_tx_prod = cur; 1508 1509 /* Set EOF on the last descriptor. */ 1510 cur = (cur + BFE_TX_LIST_CNT - 1) % BFE_TX_LIST_CNT; 1511 d = &sc->bfe_tx_list[cur]; 1512 d->bfe_ctrl |= htole32(BFE_DESC_EOF); 1513 1514 /* Lastly set SOF on the first descriptor to avoid races. */ 1515 d = &sc->bfe_tx_list[si]; 1516 d->bfe_ctrl |= htole32(BFE_DESC_SOF); 1517 1518 r1 = &sc->bfe_tx_ring[cur]; 1519 map = r->bfe_map; 1520 r->bfe_map = r1->bfe_map; 1521 r1->bfe_map = map; 1522 r1->bfe_mbuf = *m_head; 1523 sc->bfe_tx_cnt += nsegs; 1524 1525 bus_dmamap_sync(sc->bfe_txmbuf_tag, map, BUS_DMASYNC_PREWRITE); 1526 1527 return (0); 1528 } 1529 1530 /* 1531 * Set up to transmit a packet. 1532 */ 1533 static void 1534 bfe_start(struct ifnet *ifp) 1535 { 1536 BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1537 bfe_start_locked(ifp); 1538 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1539 } 1540 1541 /* 1542 * Set up to transmit a packet. The softc is already locked. 1543 */ 1544 static void 1545 bfe_start_locked(struct ifnet *ifp) 1546 { 1547 struct bfe_softc *sc; 1548 struct mbuf *m_head; 1549 int queued; 1550 1551 sc = ifp->if_softc; 1552 1553 BFE_LOCK_ASSERT(sc); 1554 1555 /* 1556 * Not much point trying to send if the link is down 1557 * or we have nothing to send. 1558 */ 1559 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1560 IFF_DRV_RUNNING || (sc->bfe_flags & BFE_FLAG_LINK) == 0) 1561 return; 1562 1563 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1564 sc->bfe_tx_cnt < BFE_TX_LIST_CNT - 1;) { 1565 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1566 if (m_head == NULL) 1567 break; 1568 1569 /* 1570 * Pack the data into the tx ring. If we dont have 1571 * enough room, let the chip drain the ring. 1572 */ 1573 if (bfe_encap(sc, &m_head)) { 1574 if (m_head == NULL) 1575 break; 1576 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1577 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1578 break; 1579 } 1580 1581 queued++; 1582 1583 /* 1584 * If there's a BPF listener, bounce a copy of this frame 1585 * to him. 1586 */ 1587 BPF_MTAP(ifp, m_head); 1588 } 1589 1590 if (queued) { 1591 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 1592 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1593 /* Transmit - twice due to apparent hardware bug */ 1594 CSR_WRITE_4(sc, BFE_DMATX_PTR, 1595 sc->bfe_tx_prod * sizeof(struct bfe_desc)); 1596 /* 1597 * XXX It seems the following write is not necessary 1598 * to kick Tx command. What might be required would be 1599 * a way flushing PCI posted write. Reading the register 1600 * back ensures the flush operation. In addition, 1601 * hardware will execute PCI posted write in the long 1602 * run and watchdog timer for the kick command was set 1603 * to 5 seconds. Therefore I think the second write 1604 * access is not necessary or could be replaced with 1605 * read operation. 1606 */ 1607 CSR_WRITE_4(sc, BFE_DMATX_PTR, 1608 sc->bfe_tx_prod * sizeof(struct bfe_desc)); 1609 1610 /* 1611 * Set a timeout in case the chip goes out to lunch. 1612 */ 1613 sc->bfe_watchdog_timer = 5; 1614 } 1615 } 1616 1617 static void 1618 bfe_init(void *xsc) 1619 { 1620 BFE_LOCK((struct bfe_softc *)xsc); 1621 bfe_init_locked(xsc); 1622 BFE_UNLOCK((struct bfe_softc *)xsc); 1623 } 1624 1625 static void 1626 bfe_init_locked(void *xsc) 1627 { 1628 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1629 struct ifnet *ifp = sc->bfe_ifp; 1630 struct mii_data *mii; 1631 1632 BFE_LOCK_ASSERT(sc); 1633 1634 mii = device_get_softc(sc->bfe_miibus); 1635 1636 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1637 return; 1638 1639 bfe_stop(sc); 1640 bfe_chip_reset(sc); 1641 1642 if (bfe_list_rx_init(sc) == ENOBUFS) { 1643 device_printf(sc->bfe_dev, 1644 "%s: Not enough memory for list buffers\n", __func__); 1645 bfe_stop(sc); 1646 return; 1647 } 1648 bfe_list_tx_init(sc); 1649 1650 bfe_set_rx_mode(sc); 1651 1652 /* Enable the chip and core */ 1653 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1654 /* Enable interrupts */ 1655 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1656 1657 /* Clear link state and change media. */ 1658 sc->bfe_flags &= ~BFE_FLAG_LINK; 1659 mii_mediachg(mii); 1660 1661 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1662 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1663 1664 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1665 } 1666 1667 /* 1668 * Set media options. 1669 */ 1670 static int 1671 bfe_ifmedia_upd(struct ifnet *ifp) 1672 { 1673 struct bfe_softc *sc; 1674 struct mii_data *mii; 1675 int error; 1676 1677 sc = ifp->if_softc; 1678 BFE_LOCK(sc); 1679 1680 mii = device_get_softc(sc->bfe_miibus); 1681 if (mii->mii_instance) { 1682 struct mii_softc *miisc; 1683 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1684 miisc = LIST_NEXT(miisc, mii_list)) 1685 mii_phy_reset(miisc); 1686 } 1687 error = mii_mediachg(mii); 1688 BFE_UNLOCK(sc); 1689 1690 return (error); 1691 } 1692 1693 /* 1694 * Report current media status. 1695 */ 1696 static void 1697 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1698 { 1699 struct bfe_softc *sc = ifp->if_softc; 1700 struct mii_data *mii; 1701 1702 BFE_LOCK(sc); 1703 mii = device_get_softc(sc->bfe_miibus); 1704 mii_pollstat(mii); 1705 ifmr->ifm_active = mii->mii_media_active; 1706 ifmr->ifm_status = mii->mii_media_status; 1707 BFE_UNLOCK(sc); 1708 } 1709 1710 static int 1711 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1712 { 1713 struct bfe_softc *sc = ifp->if_softc; 1714 struct ifreq *ifr = (struct ifreq *) data; 1715 struct mii_data *mii; 1716 int error = 0; 1717 1718 switch (command) { 1719 case SIOCSIFFLAGS: 1720 BFE_LOCK(sc); 1721 if (ifp->if_flags & IFF_UP) { 1722 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1723 bfe_set_rx_mode(sc); 1724 else if ((sc->bfe_flags & BFE_FLAG_DETACH) == 0) 1725 bfe_init_locked(sc); 1726 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1727 bfe_stop(sc); 1728 BFE_UNLOCK(sc); 1729 break; 1730 case SIOCADDMULTI: 1731 case SIOCDELMULTI: 1732 BFE_LOCK(sc); 1733 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1734 bfe_set_rx_mode(sc); 1735 BFE_UNLOCK(sc); 1736 break; 1737 case SIOCGIFMEDIA: 1738 case SIOCSIFMEDIA: 1739 mii = device_get_softc(sc->bfe_miibus); 1740 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1741 break; 1742 default: 1743 error = ether_ioctl(ifp, command, data); 1744 break; 1745 } 1746 1747 return (error); 1748 } 1749 1750 static void 1751 bfe_watchdog(struct bfe_softc *sc) 1752 { 1753 struct ifnet *ifp; 1754 1755 BFE_LOCK_ASSERT(sc); 1756 1757 if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer) 1758 return; 1759 1760 ifp = sc->bfe_ifp; 1761 1762 device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n"); 1763 1764 ifp->if_oerrors++; 1765 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1766 bfe_init_locked(sc); 1767 1768 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1769 bfe_start_locked(ifp); 1770 } 1771 1772 static void 1773 bfe_tick(void *xsc) 1774 { 1775 struct bfe_softc *sc = xsc; 1776 struct mii_data *mii; 1777 1778 BFE_LOCK_ASSERT(sc); 1779 1780 mii = device_get_softc(sc->bfe_miibus); 1781 mii_tick(mii); 1782 bfe_stats_update(sc); 1783 bfe_watchdog(sc); 1784 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1785 } 1786 1787 /* 1788 * Stop the adapter and free any mbufs allocated to the 1789 * RX and TX lists. 1790 */ 1791 static void 1792 bfe_stop(struct bfe_softc *sc) 1793 { 1794 struct ifnet *ifp; 1795 1796 BFE_LOCK_ASSERT(sc); 1797 1798 ifp = sc->bfe_ifp; 1799 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1800 sc->bfe_flags &= ~BFE_FLAG_LINK; 1801 callout_stop(&sc->bfe_stat_co); 1802 sc->bfe_watchdog_timer = 0; 1803 1804 bfe_chip_halt(sc); 1805 bfe_tx_ring_free(sc); 1806 bfe_rx_ring_free(sc); 1807 }
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