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sys/dev/bfe/if_bfe.c
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1 /*- 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD: releng/7.4/sys/dev/bfe/if_bfe.c 214910 2010-11-07 11:12:30Z marius $"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/endian.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/mbuf.h> 38 #include <sys/module.h> 39 #include <sys/rman.h> 40 #include <sys/socket.h> 41 #include <sys/sockio.h> 42 43 #include <net/bpf.h> 44 #include <net/if.h> 45 #include <net/ethernet.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 #include <net/if_types.h> 49 #include <net/if_vlan_var.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcivar.h> 56 57 #include <machine/bus.h> 58 59 #include <dev/bfe/if_bfereg.h> 60 61 MODULE_DEPEND(bfe, pci, 1, 1, 1); 62 MODULE_DEPEND(bfe, ether, 1, 1, 1); 63 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 64 65 /* "device miibus" required. See GENERIC if you get errors here. */ 66 #include "miibus_if.h" 67 68 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 69 70 static struct bfe_type bfe_devs[] = { 71 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 72 "Broadcom BCM4401 Fast Ethernet" }, 73 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 74 "Broadcom BCM4401-B0 Fast Ethernet" }, 75 { 0, 0, NULL } 76 }; 77 78 static int bfe_probe (device_t); 79 static int bfe_attach (device_t); 80 static int bfe_detach (device_t); 81 static int bfe_suspend (device_t); 82 static int bfe_resume (device_t); 83 static void bfe_release_resources (struct bfe_softc *); 84 static void bfe_intr (void *); 85 static int bfe_encap (struct bfe_softc *, struct mbuf **); 86 static void bfe_start (struct ifnet *); 87 static void bfe_start_locked (struct ifnet *); 88 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 89 static void bfe_init (void *); 90 static void bfe_init_locked (void *); 91 static void bfe_stop (struct bfe_softc *); 92 static void bfe_watchdog (struct bfe_softc *); 93 static int bfe_shutdown (device_t); 94 static void bfe_tick (void *); 95 static void bfe_txeof (struct bfe_softc *); 96 static void bfe_rxeof (struct bfe_softc *); 97 static void bfe_set_rx_mode (struct bfe_softc *); 98 static int bfe_list_rx_init (struct bfe_softc *); 99 static void bfe_list_tx_init (struct bfe_softc *); 100 static void bfe_discard_buf (struct bfe_softc *, int); 101 static int bfe_list_newbuf (struct bfe_softc *, int); 102 static void bfe_rx_ring_free (struct bfe_softc *); 103 104 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 105 static int bfe_ifmedia_upd (struct ifnet *); 106 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 107 static int bfe_miibus_readreg (device_t, int, int); 108 static int bfe_miibus_writereg (device_t, int, int, int); 109 static void bfe_miibus_statchg (device_t); 110 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 111 u_long, const int); 112 static void bfe_get_config (struct bfe_softc *sc); 113 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 114 static void bfe_stats_update (struct bfe_softc *); 115 static void bfe_clear_stats (struct bfe_softc *); 116 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 117 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 118 static int bfe_resetphy (struct bfe_softc *); 119 static int bfe_setupphy (struct bfe_softc *); 120 static void bfe_chip_reset (struct bfe_softc *); 121 static void bfe_chip_halt (struct bfe_softc *); 122 static void bfe_core_reset (struct bfe_softc *); 123 static void bfe_core_disable (struct bfe_softc *); 124 static int bfe_dma_alloc (struct bfe_softc *); 125 static void bfe_dma_free (struct bfe_softc *sc); 126 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 127 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 128 129 static device_method_t bfe_methods[] = { 130 /* Device interface */ 131 DEVMETHOD(device_probe, bfe_probe), 132 DEVMETHOD(device_attach, bfe_attach), 133 DEVMETHOD(device_detach, bfe_detach), 134 DEVMETHOD(device_shutdown, bfe_shutdown), 135 DEVMETHOD(device_suspend, bfe_suspend), 136 DEVMETHOD(device_resume, bfe_resume), 137 138 /* bus interface */ 139 DEVMETHOD(bus_print_child, bus_generic_print_child), 140 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 141 142 /* MII interface */ 143 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 144 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 145 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 146 147 { 0, 0 } 148 }; 149 150 static driver_t bfe_driver = { 151 "bfe", 152 bfe_methods, 153 sizeof(struct bfe_softc) 154 }; 155 156 static devclass_t bfe_devclass; 157 158 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 159 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 160 161 /* 162 * Probe for a Broadcom 4401 chip. 163 */ 164 static int 165 bfe_probe(device_t dev) 166 { 167 struct bfe_type *t; 168 169 t = bfe_devs; 170 171 while (t->bfe_name != NULL) { 172 if (pci_get_vendor(dev) == t->bfe_vid && 173 pci_get_device(dev) == t->bfe_did) { 174 device_set_desc(dev, t->bfe_name); 175 return (BUS_PROBE_DEFAULT); 176 } 177 t++; 178 } 179 180 return (ENXIO); 181 } 182 183 struct bfe_dmamap_arg { 184 bus_addr_t bfe_busaddr; 185 }; 186 187 static int 188 bfe_dma_alloc(struct bfe_softc *sc) 189 { 190 struct bfe_dmamap_arg ctx; 191 struct bfe_rx_data *rd; 192 struct bfe_tx_data *td; 193 int error, i; 194 195 /* 196 * parent tag. Apparently the chip cannot handle any DMA address 197 * greater than 1GB. 198 */ 199 error = bus_dma_tag_create(bus_get_dma_tag(sc->bfe_dev), /* parent */ 200 1, 0, /* alignment, boundary */ 201 BFE_DMA_MAXADDR, /* lowaddr */ 202 BUS_SPACE_MAXADDR, /* highaddr */ 203 NULL, NULL, /* filter, filterarg */ 204 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 205 0, /* nsegments */ 206 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 207 0, /* flags */ 208 NULL, NULL, /* lockfunc, lockarg */ 209 &sc->bfe_parent_tag); 210 if (error != 0) { 211 device_printf(sc->bfe_dev, "cannot create parent DMA tag.\n"); 212 goto fail; 213 } 214 215 /* Create tag for Tx ring. */ 216 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 217 BFE_TX_RING_ALIGN, 0, /* alignment, boundary */ 218 BUS_SPACE_MAXADDR, /* lowaddr */ 219 BUS_SPACE_MAXADDR, /* highaddr */ 220 NULL, NULL, /* filter, filterarg */ 221 BFE_TX_LIST_SIZE, /* maxsize */ 222 1, /* nsegments */ 223 BFE_TX_LIST_SIZE, /* maxsegsize */ 224 0, /* flags */ 225 NULL, NULL, /* lockfunc, lockarg */ 226 &sc->bfe_tx_tag); 227 if (error != 0) { 228 device_printf(sc->bfe_dev, "cannot create Tx ring DMA tag.\n"); 229 goto fail; 230 } 231 232 /* Create tag for Rx ring. */ 233 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 234 BFE_RX_RING_ALIGN, 0, /* alignment, boundary */ 235 BUS_SPACE_MAXADDR, /* lowaddr */ 236 BUS_SPACE_MAXADDR, /* highaddr */ 237 NULL, NULL, /* filter, filterarg */ 238 BFE_RX_LIST_SIZE, /* maxsize */ 239 1, /* nsegments */ 240 BFE_RX_LIST_SIZE, /* maxsegsize */ 241 0, /* flags */ 242 NULL, NULL, /* lockfunc, lockarg */ 243 &sc->bfe_rx_tag); 244 if (error != 0) { 245 device_printf(sc->bfe_dev, "cannot create Rx ring DMA tag.\n"); 246 goto fail; 247 } 248 249 /* Create tag for Tx buffers. */ 250 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 251 1, 0, /* alignment, boundary */ 252 BUS_SPACE_MAXADDR, /* lowaddr */ 253 BUS_SPACE_MAXADDR, /* highaddr */ 254 NULL, NULL, /* filter, filterarg */ 255 MCLBYTES * BFE_MAXTXSEGS, /* maxsize */ 256 BFE_MAXTXSEGS, /* nsegments */ 257 MCLBYTES, /* maxsegsize */ 258 0, /* flags */ 259 NULL, NULL, /* lockfunc, lockarg */ 260 &sc->bfe_txmbuf_tag); 261 if (error != 0) { 262 device_printf(sc->bfe_dev, 263 "cannot create Tx buffer DMA tag.\n"); 264 goto fail; 265 } 266 267 /* Create tag for Rx buffers. */ 268 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 269 1, 0, /* alignment, boundary */ 270 BUS_SPACE_MAXADDR, /* lowaddr */ 271 BUS_SPACE_MAXADDR, /* highaddr */ 272 NULL, NULL, /* filter, filterarg */ 273 MCLBYTES, /* maxsize */ 274 1, /* nsegments */ 275 MCLBYTES, /* maxsegsize */ 276 0, /* flags */ 277 NULL, NULL, /* lockfunc, lockarg */ 278 &sc->bfe_rxmbuf_tag); 279 if (error != 0) { 280 device_printf(sc->bfe_dev, 281 "cannot create Rx buffer DMA tag.\n"); 282 goto fail; 283 } 284 285 /* Allocate DMA'able memory and load DMA map. */ 286 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 287 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_tx_map); 288 if (error != 0) { 289 device_printf(sc->bfe_dev, 290 "cannot allocate DMA'able memory for Tx ring.\n"); 291 goto fail; 292 } 293 ctx.bfe_busaddr = 0; 294 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 295 sc->bfe_tx_list, BFE_TX_LIST_SIZE, bfe_dma_map, &ctx, 296 BUS_DMA_NOWAIT); 297 if (error != 0 || ctx.bfe_busaddr == 0) { 298 device_printf(sc->bfe_dev, 299 "cannot load DMA'able memory for Tx ring.\n"); 300 goto fail; 301 } 302 sc->bfe_tx_dma = BFE_ADDR_LO(ctx.bfe_busaddr); 303 304 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 305 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_rx_map); 306 if (error != 0) { 307 device_printf(sc->bfe_dev, 308 "cannot allocate DMA'able memory for Rx ring.\n"); 309 goto fail; 310 } 311 ctx.bfe_busaddr = 0; 312 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 313 sc->bfe_rx_list, BFE_RX_LIST_SIZE, bfe_dma_map, &ctx, 314 BUS_DMA_NOWAIT); 315 if (error != 0 || ctx.bfe_busaddr == 0) { 316 device_printf(sc->bfe_dev, 317 "cannot load DMA'able memory for Rx ring.\n"); 318 goto fail; 319 } 320 sc->bfe_rx_dma = BFE_ADDR_LO(ctx.bfe_busaddr); 321 322 /* Create DMA maps for Tx buffers. */ 323 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 324 td = &sc->bfe_tx_ring[i]; 325 td->bfe_mbuf = NULL; 326 td->bfe_map = NULL; 327 error = bus_dmamap_create(sc->bfe_txmbuf_tag, 0, &td->bfe_map); 328 if (error != 0) { 329 device_printf(sc->bfe_dev, 330 "cannot create DMA map for Tx.\n"); 331 goto fail; 332 } 333 } 334 335 /* Create spare DMA map for Rx buffers. */ 336 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &sc->bfe_rx_sparemap); 337 if (error != 0) { 338 device_printf(sc->bfe_dev, "cannot create spare DMA map for Rx.\n"); 339 goto fail; 340 } 341 /* Create DMA maps for Rx buffers. */ 342 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 343 rd = &sc->bfe_rx_ring[i]; 344 rd->bfe_mbuf = NULL; 345 rd->bfe_map = NULL; 346 rd->bfe_ctrl = 0; 347 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &rd->bfe_map); 348 if (error != 0) { 349 device_printf(sc->bfe_dev, 350 "cannot create DMA map for Rx.\n"); 351 goto fail; 352 } 353 } 354 355 fail: 356 return (error); 357 } 358 359 static void 360 bfe_dma_free(struct bfe_softc *sc) 361 { 362 struct bfe_tx_data *td; 363 struct bfe_rx_data *rd; 364 int i; 365 366 /* Tx ring. */ 367 if (sc->bfe_tx_tag != NULL) { 368 if (sc->bfe_tx_map != NULL) 369 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 370 if (sc->bfe_tx_map != NULL && sc->bfe_tx_list != NULL) 371 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 372 sc->bfe_tx_map); 373 sc->bfe_tx_map = NULL; 374 sc->bfe_tx_list = NULL; 375 bus_dma_tag_destroy(sc->bfe_tx_tag); 376 sc->bfe_tx_tag = NULL; 377 } 378 379 /* Rx ring. */ 380 if (sc->bfe_rx_tag != NULL) { 381 if (sc->bfe_rx_map != NULL) 382 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 383 if (sc->bfe_rx_map != NULL && sc->bfe_rx_list != NULL) 384 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 385 sc->bfe_rx_map); 386 sc->bfe_rx_map = NULL; 387 sc->bfe_rx_list = NULL; 388 bus_dma_tag_destroy(sc->bfe_rx_tag); 389 sc->bfe_rx_tag = NULL; 390 } 391 392 /* Tx buffers. */ 393 if (sc->bfe_txmbuf_tag != NULL) { 394 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 395 td = &sc->bfe_tx_ring[i]; 396 if (td->bfe_map != NULL) { 397 bus_dmamap_destroy(sc->bfe_txmbuf_tag, 398 td->bfe_map); 399 td->bfe_map = NULL; 400 } 401 } 402 bus_dma_tag_destroy(sc->bfe_txmbuf_tag); 403 sc->bfe_txmbuf_tag = NULL; 404 } 405 406 /* Rx buffers. */ 407 if (sc->bfe_rxmbuf_tag != NULL) { 408 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 409 rd = &sc->bfe_rx_ring[i]; 410 if (rd->bfe_map != NULL) { 411 bus_dmamap_destroy(sc->bfe_rxmbuf_tag, 412 rd->bfe_map); 413 rd->bfe_map = NULL; 414 } 415 } 416 if (sc->bfe_rx_sparemap != NULL) { 417 bus_dmamap_destroy(sc->bfe_rxmbuf_tag, 418 sc->bfe_rx_sparemap); 419 sc->bfe_rx_sparemap = NULL; 420 } 421 bus_dma_tag_destroy(sc->bfe_rxmbuf_tag); 422 sc->bfe_rxmbuf_tag = NULL; 423 } 424 425 if (sc->bfe_parent_tag != NULL) { 426 bus_dma_tag_destroy(sc->bfe_parent_tag); 427 sc->bfe_parent_tag = NULL; 428 } 429 } 430 431 static int 432 bfe_attach(device_t dev) 433 { 434 struct ifnet *ifp = NULL; 435 struct bfe_softc *sc; 436 int error = 0, rid; 437 438 sc = device_get_softc(dev); 439 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 440 MTX_DEF); 441 callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0); 442 443 sc->bfe_dev = dev; 444 445 /* 446 * Map control/status registers. 447 */ 448 pci_enable_busmaster(dev); 449 450 rid = PCIR_BAR(0); 451 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 452 RF_ACTIVE); 453 if (sc->bfe_res == NULL) { 454 device_printf(dev, "couldn't map memory\n"); 455 error = ENXIO; 456 goto fail; 457 } 458 459 /* Allocate interrupt */ 460 rid = 0; 461 462 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 463 RF_SHAREABLE | RF_ACTIVE); 464 if (sc->bfe_irq == NULL) { 465 device_printf(dev, "couldn't map interrupt\n"); 466 error = ENXIO; 467 goto fail; 468 } 469 470 if (bfe_dma_alloc(sc) != 0) { 471 device_printf(dev, "failed to allocate DMA resources\n"); 472 error = ENXIO; 473 goto fail; 474 } 475 476 /* Set up ifnet structure */ 477 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER); 478 if (ifp == NULL) { 479 device_printf(dev, "failed to if_alloc()\n"); 480 error = ENOSPC; 481 goto fail; 482 } 483 ifp->if_softc = sc; 484 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 485 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 486 ifp->if_ioctl = bfe_ioctl; 487 ifp->if_start = bfe_start; 488 ifp->if_init = bfe_init; 489 ifp->if_mtu = ETHERMTU; 490 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 491 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 492 IFQ_SET_READY(&ifp->if_snd); 493 494 bfe_get_config(sc); 495 496 /* Reset the chip and turn on the PHY */ 497 BFE_LOCK(sc); 498 bfe_chip_reset(sc); 499 BFE_UNLOCK(sc); 500 501 error = mii_attach(dev, &sc->bfe_miibus, ifp, bfe_ifmedia_upd, 502 bfe_ifmedia_sts, BMSR_DEFCAPMASK, sc->bfe_phyaddr, MII_OFFSET_ANY, 503 0); 504 if (error != 0) { 505 device_printf(dev, "attaching PHYs failed\n"); 506 goto fail; 507 } 508 509 ether_ifattach(ifp, sc->bfe_enaddr); 510 511 /* 512 * Tell the upper layer(s) we support long frames. 513 */ 514 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 515 ifp->if_capabilities |= IFCAP_VLAN_MTU; 516 ifp->if_capenable |= IFCAP_VLAN_MTU; 517 518 /* 519 * Hook interrupt last to avoid having to lock softc 520 */ 521 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 522 NULL, bfe_intr, sc, &sc->bfe_intrhand); 523 524 if (error) { 525 device_printf(dev, "couldn't set up irq\n"); 526 goto fail; 527 } 528 fail: 529 if (error != 0) 530 bfe_detach(dev); 531 return (error); 532 } 533 534 static int 535 bfe_detach(device_t dev) 536 { 537 struct bfe_softc *sc; 538 struct ifnet *ifp; 539 540 sc = device_get_softc(dev); 541 542 ifp = sc->bfe_ifp; 543 544 if (device_is_attached(dev)) { 545 BFE_LOCK(sc); 546 sc->bfe_flags |= BFE_FLAG_DETACH; 547 bfe_stop(sc); 548 BFE_UNLOCK(sc); 549 callout_drain(&sc->bfe_stat_co); 550 if (ifp != NULL) 551 ether_ifdetach(ifp); 552 } 553 554 BFE_LOCK(sc); 555 bfe_chip_reset(sc); 556 BFE_UNLOCK(sc); 557 558 bus_generic_detach(dev); 559 if (sc->bfe_miibus != NULL) 560 device_delete_child(dev, sc->bfe_miibus); 561 562 bfe_release_resources(sc); 563 bfe_dma_free(sc); 564 mtx_destroy(&sc->bfe_mtx); 565 566 return (0); 567 } 568 569 /* 570 * Stop all chip I/O so that the kernel's probe routines don't 571 * get confused by errant DMAs when rebooting. 572 */ 573 static int 574 bfe_shutdown(device_t dev) 575 { 576 struct bfe_softc *sc; 577 578 sc = device_get_softc(dev); 579 BFE_LOCK(sc); 580 bfe_stop(sc); 581 582 BFE_UNLOCK(sc); 583 584 return (0); 585 } 586 587 static int 588 bfe_suspend(device_t dev) 589 { 590 struct bfe_softc *sc; 591 592 sc = device_get_softc(dev); 593 BFE_LOCK(sc); 594 bfe_stop(sc); 595 BFE_UNLOCK(sc); 596 597 return (0); 598 } 599 600 static int 601 bfe_resume(device_t dev) 602 { 603 struct bfe_softc *sc; 604 struct ifnet *ifp; 605 606 sc = device_get_softc(dev); 607 ifp = sc->bfe_ifp; 608 BFE_LOCK(sc); 609 bfe_chip_reset(sc); 610 if (ifp->if_flags & IFF_UP) { 611 bfe_init_locked(sc); 612 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 613 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 614 bfe_start_locked(ifp); 615 } 616 BFE_UNLOCK(sc); 617 618 return (0); 619 } 620 621 static int 622 bfe_miibus_readreg(device_t dev, int phy, int reg) 623 { 624 struct bfe_softc *sc; 625 u_int32_t ret; 626 627 sc = device_get_softc(dev); 628 bfe_readphy(sc, reg, &ret); 629 630 return (ret); 631 } 632 633 static int 634 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 635 { 636 struct bfe_softc *sc; 637 638 sc = device_get_softc(dev); 639 bfe_writephy(sc, reg, val); 640 641 return (0); 642 } 643 644 static void 645 bfe_miibus_statchg(device_t dev) 646 { 647 struct bfe_softc *sc; 648 struct mii_data *mii; 649 u_int32_t val, flow; 650 651 sc = device_get_softc(dev); 652 mii = device_get_softc(sc->bfe_miibus); 653 654 sc->bfe_flags &= ~BFE_FLAG_LINK; 655 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 656 (IFM_ACTIVE | IFM_AVALID)) { 657 switch (IFM_SUBTYPE(mii->mii_media_active)) { 658 case IFM_10_T: 659 case IFM_100_TX: 660 sc->bfe_flags |= BFE_FLAG_LINK; 661 break; 662 default: 663 break; 664 } 665 } 666 667 /* XXX Should stop Rx/Tx engine prior to touching MAC. */ 668 val = CSR_READ_4(sc, BFE_TX_CTRL); 669 val &= ~BFE_TX_DUPLEX; 670 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 671 val |= BFE_TX_DUPLEX; 672 flow = 0; 673 #ifdef notyet 674 flow = CSR_READ_4(sc, BFE_RXCONF); 675 flow &= ~BFE_RXCONF_FLOW; 676 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 677 IFM_ETH_RXPAUSE) != 0) 678 flow |= BFE_RXCONF_FLOW; 679 CSR_WRITE_4(sc, BFE_RXCONF, flow); 680 /* 681 * It seems that the hardware has Tx pause issues 682 * so enable only Rx pause. 683 */ 684 flow = CSR_READ_4(sc, BFE_MAC_FLOW); 685 flow &= ~BFE_FLOW_PAUSE_ENAB; 686 CSR_WRITE_4(sc, BFE_MAC_FLOW, flow); 687 #endif 688 } 689 CSR_WRITE_4(sc, BFE_TX_CTRL, val); 690 } 691 692 static void 693 bfe_tx_ring_free(struct bfe_softc *sc) 694 { 695 int i; 696 697 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 698 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 699 bus_dmamap_sync(sc->bfe_txmbuf_tag, 700 sc->bfe_tx_ring[i].bfe_map, BUS_DMASYNC_POSTWRITE); 701 bus_dmamap_unload(sc->bfe_txmbuf_tag, 702 sc->bfe_tx_ring[i].bfe_map); 703 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 704 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 705 } 706 } 707 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 708 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 709 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 710 } 711 712 static void 713 bfe_rx_ring_free(struct bfe_softc *sc) 714 { 715 int i; 716 717 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 718 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 719 bus_dmamap_sync(sc->bfe_rxmbuf_tag, 720 sc->bfe_rx_ring[i].bfe_map, BUS_DMASYNC_POSTREAD); 721 bus_dmamap_unload(sc->bfe_rxmbuf_tag, 722 sc->bfe_rx_ring[i].bfe_map); 723 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 724 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 725 } 726 } 727 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 728 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 729 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 730 } 731 732 static int 733 bfe_list_rx_init(struct bfe_softc *sc) 734 { 735 struct bfe_rx_data *rd; 736 int i; 737 738 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 739 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 740 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 741 rd = &sc->bfe_rx_ring[i]; 742 rd->bfe_mbuf = NULL; 743 rd->bfe_ctrl = 0; 744 if (bfe_list_newbuf(sc, i) != 0) 745 return (ENOBUFS); 746 } 747 748 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 749 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 750 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 751 752 return (0); 753 } 754 755 static void 756 bfe_list_tx_init(struct bfe_softc *sc) 757 { 758 int i; 759 760 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 761 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 762 for (i = 0; i < BFE_TX_LIST_CNT; i++) 763 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 764 765 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 766 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 767 } 768 769 static void 770 bfe_discard_buf(struct bfe_softc *sc, int c) 771 { 772 struct bfe_rx_data *r; 773 struct bfe_desc *d; 774 775 r = &sc->bfe_rx_ring[c]; 776 d = &sc->bfe_rx_list[c]; 777 d->bfe_ctrl = htole32(r->bfe_ctrl); 778 } 779 780 static int 781 bfe_list_newbuf(struct bfe_softc *sc, int c) 782 { 783 struct bfe_rxheader *rx_header; 784 struct bfe_desc *d; 785 struct bfe_rx_data *r; 786 struct mbuf *m; 787 bus_dma_segment_t segs[1]; 788 bus_dmamap_t map; 789 u_int32_t ctrl; 790 int nsegs; 791 792 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 793 m->m_len = m->m_pkthdr.len = MCLBYTES; 794 795 if (bus_dmamap_load_mbuf_sg(sc->bfe_rxmbuf_tag, sc->bfe_rx_sparemap, 796 m, segs, &nsegs, 0) != 0) { 797 m_freem(m); 798 return (ENOBUFS); 799 } 800 801 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 802 r = &sc->bfe_rx_ring[c]; 803 if (r->bfe_mbuf != NULL) { 804 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, 805 BUS_DMASYNC_POSTREAD); 806 bus_dmamap_unload(sc->bfe_rxmbuf_tag, r->bfe_map); 807 } 808 map = r->bfe_map; 809 r->bfe_map = sc->bfe_rx_sparemap; 810 sc->bfe_rx_sparemap = map; 811 r->bfe_mbuf = m; 812 813 rx_header = mtod(m, struct bfe_rxheader *); 814 rx_header->len = 0; 815 rx_header->flags = 0; 816 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, BUS_DMASYNC_PREREAD); 817 818 ctrl = segs[0].ds_len & BFE_DESC_LEN; 819 KASSERT(ctrl > ETHER_MAX_LEN + 32, ("%s: buffer size too small(%d)!", 820 __func__, ctrl)); 821 if (c == BFE_RX_LIST_CNT - 1) 822 ctrl |= BFE_DESC_EOT; 823 r->bfe_ctrl = ctrl; 824 825 d = &sc->bfe_rx_list[c]; 826 d->bfe_ctrl = htole32(ctrl); 827 /* The chip needs all addresses to be added to BFE_PCI_DMA. */ 828 d->bfe_addr = htole32(BFE_ADDR_LO(segs[0].ds_addr) + BFE_PCI_DMA); 829 830 return (0); 831 } 832 833 static void 834 bfe_get_config(struct bfe_softc *sc) 835 { 836 u_int8_t eeprom[128]; 837 838 bfe_read_eeprom(sc, eeprom); 839 840 sc->bfe_enaddr[0] = eeprom[79]; 841 sc->bfe_enaddr[1] = eeprom[78]; 842 sc->bfe_enaddr[2] = eeprom[81]; 843 sc->bfe_enaddr[3] = eeprom[80]; 844 sc->bfe_enaddr[4] = eeprom[83]; 845 sc->bfe_enaddr[5] = eeprom[82]; 846 847 sc->bfe_phyaddr = eeprom[90] & 0x1f; 848 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 849 850 sc->bfe_core_unit = 0; 851 sc->bfe_dma_offset = BFE_PCI_DMA; 852 } 853 854 static void 855 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 856 { 857 u_int32_t bar_orig, pci_rev, val; 858 859 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 860 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 861 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 862 863 val = CSR_READ_4(sc, BFE_SBINTVEC); 864 val |= cores; 865 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 866 867 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 868 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 869 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 870 871 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 872 } 873 874 static void 875 bfe_clear_stats(struct bfe_softc *sc) 876 { 877 u_long reg; 878 879 BFE_LOCK_ASSERT(sc); 880 881 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 882 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 883 CSR_READ_4(sc, reg); 884 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 885 CSR_READ_4(sc, reg); 886 } 887 888 static int 889 bfe_resetphy(struct bfe_softc *sc) 890 { 891 u_int32_t val; 892 893 bfe_writephy(sc, 0, BMCR_RESET); 894 DELAY(100); 895 bfe_readphy(sc, 0, &val); 896 if (val & BMCR_RESET) { 897 device_printf(sc->bfe_dev, "PHY Reset would not complete.\n"); 898 return (ENXIO); 899 } 900 return (0); 901 } 902 903 static void 904 bfe_chip_halt(struct bfe_softc *sc) 905 { 906 BFE_LOCK_ASSERT(sc); 907 /* disable interrupts - not that it actually does..*/ 908 CSR_WRITE_4(sc, BFE_IMASK, 0); 909 CSR_READ_4(sc, BFE_IMASK); 910 911 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 912 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 913 914 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 915 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 916 DELAY(10); 917 } 918 919 static void 920 bfe_chip_reset(struct bfe_softc *sc) 921 { 922 u_int32_t val; 923 924 BFE_LOCK_ASSERT(sc); 925 926 /* Set the interrupt vector for the enet core */ 927 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 928 929 /* is core up? */ 930 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 931 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 932 if (val == BFE_CLOCK) { 933 /* It is, so shut it down */ 934 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 935 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 936 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 937 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 938 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 939 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 940 100, 0); 941 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 942 } 943 944 bfe_core_reset(sc); 945 bfe_clear_stats(sc); 946 947 /* 948 * We want the phy registers to be accessible even when 949 * the driver is "downed" so initialize MDC preamble, frequency, 950 * and whether internal or external phy here. 951 */ 952 953 /* 4402 has 62.5Mhz SB clock and internal phy */ 954 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 955 956 /* Internal or external PHY? */ 957 val = CSR_READ_4(sc, BFE_DEVCTRL); 958 if (!(val & BFE_IPP)) 959 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 960 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 961 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 962 DELAY(100); 963 } 964 965 /* Enable CRC32 generation and set proper LED modes */ 966 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 967 968 /* Reset or clear powerdown control bit */ 969 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 970 971 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 972 BFE_LAZY_FC_MASK)); 973 974 /* 975 * We don't want lazy interrupts, so just send them at 976 * the end of a frame, please 977 */ 978 BFE_OR(sc, BFE_RCV_LAZY, 0); 979 980 /* Set max lengths, accounting for VLAN tags */ 981 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 982 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 983 984 /* Set watermark XXX - magic */ 985 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 986 987 /* 988 * Initialise DMA channels 989 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 990 */ 991 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 992 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 993 994 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 995 BFE_RX_CTRL_ENABLE); 996 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 997 998 bfe_resetphy(sc); 999 bfe_setupphy(sc); 1000 } 1001 1002 static void 1003 bfe_core_disable(struct bfe_softc *sc) 1004 { 1005 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 1006 return; 1007 1008 /* 1009 * Set reject, wait for it set, then wait for the core to stop 1010 * being busy, then set reset and reject and enable the clocks. 1011 */ 1012 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 1013 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 1014 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 1015 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 1016 BFE_RESET)); 1017 CSR_READ_4(sc, BFE_SBTMSLOW); 1018 DELAY(10); 1019 /* Leave reset and reject set */ 1020 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 1021 DELAY(10); 1022 } 1023 1024 static void 1025 bfe_core_reset(struct bfe_softc *sc) 1026 { 1027 u_int32_t val; 1028 1029 /* Disable the core */ 1030 bfe_core_disable(sc); 1031 1032 /* and bring it back up */ 1033 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 1034 CSR_READ_4(sc, BFE_SBTMSLOW); 1035 DELAY(10); 1036 1037 /* Chip bug, clear SERR, IB and TO if they are set. */ 1038 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 1039 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 1040 val = CSR_READ_4(sc, BFE_SBIMSTATE); 1041 if (val & (BFE_IBE | BFE_TO)) 1042 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 1043 1044 /* Clear reset and allow it to move through the core */ 1045 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 1046 CSR_READ_4(sc, BFE_SBTMSLOW); 1047 DELAY(10); 1048 1049 /* Leave the clock set */ 1050 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 1051 CSR_READ_4(sc, BFE_SBTMSLOW); 1052 DELAY(10); 1053 } 1054 1055 static void 1056 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 1057 { 1058 u_int32_t val; 1059 1060 val = ((u_int32_t) data[2]) << 24; 1061 val |= ((u_int32_t) data[3]) << 16; 1062 val |= ((u_int32_t) data[4]) << 8; 1063 val |= ((u_int32_t) data[5]); 1064 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 1065 val = (BFE_CAM_HI_VALID | 1066 (((u_int32_t) data[0]) << 8) | 1067 (((u_int32_t) data[1]))); 1068 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 1069 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 1070 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 1071 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 1072 } 1073 1074 static void 1075 bfe_set_rx_mode(struct bfe_softc *sc) 1076 { 1077 struct ifnet *ifp = sc->bfe_ifp; 1078 struct ifmultiaddr *ifma; 1079 u_int32_t val; 1080 int i = 0; 1081 1082 val = CSR_READ_4(sc, BFE_RXCONF); 1083 1084 if (ifp->if_flags & IFF_PROMISC) 1085 val |= BFE_RXCONF_PROMISC; 1086 else 1087 val &= ~BFE_RXCONF_PROMISC; 1088 1089 if (ifp->if_flags & IFF_BROADCAST) 1090 val &= ~BFE_RXCONF_DBCAST; 1091 else 1092 val |= BFE_RXCONF_DBCAST; 1093 1094 1095 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 1096 bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++); 1097 1098 if (ifp->if_flags & IFF_ALLMULTI) 1099 val |= BFE_RXCONF_ALLMULTI; 1100 else { 1101 val &= ~BFE_RXCONF_ALLMULTI; 1102 IF_ADDR_LOCK(ifp); 1103 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1104 if (ifma->ifma_addr->sa_family != AF_LINK) 1105 continue; 1106 bfe_cam_write(sc, 1107 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 1108 } 1109 IF_ADDR_UNLOCK(ifp); 1110 } 1111 1112 CSR_WRITE_4(sc, BFE_RXCONF, val); 1113 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 1114 } 1115 1116 static void 1117 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1118 { 1119 struct bfe_dmamap_arg *ctx; 1120 1121 if (error != 0) 1122 return; 1123 1124 KASSERT(nseg == 1, ("%s : %d segments returned!", __func__, nseg)); 1125 1126 ctx = (struct bfe_dmamap_arg *)arg; 1127 ctx->bfe_busaddr = segs[0].ds_addr; 1128 } 1129 1130 static void 1131 bfe_release_resources(struct bfe_softc *sc) 1132 { 1133 1134 if (sc->bfe_intrhand != NULL) 1135 bus_teardown_intr(sc->bfe_dev, sc->bfe_irq, sc->bfe_intrhand); 1136 1137 if (sc->bfe_irq != NULL) 1138 bus_release_resource(sc->bfe_dev, SYS_RES_IRQ, 0, sc->bfe_irq); 1139 1140 if (sc->bfe_res != NULL) 1141 bus_release_resource(sc->bfe_dev, SYS_RES_MEMORY, PCIR_BAR(0), 1142 sc->bfe_res); 1143 1144 if (sc->bfe_ifp != NULL) 1145 if_free(sc->bfe_ifp); 1146 } 1147 1148 static void 1149 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 1150 { 1151 long i; 1152 u_int16_t *ptr = (u_int16_t *)data; 1153 1154 for(i = 0; i < 128; i += 2) 1155 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 1156 } 1157 1158 static int 1159 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1160 u_long timeout, const int clear) 1161 { 1162 u_long i; 1163 1164 for (i = 0; i < timeout; i++) { 1165 u_int32_t val = CSR_READ_4(sc, reg); 1166 1167 if (clear && !(val & bit)) 1168 break; 1169 if (!clear && (val & bit)) 1170 break; 1171 DELAY(10); 1172 } 1173 if (i == timeout) { 1174 device_printf(sc->bfe_dev, 1175 "BUG! Timeout waiting for bit %08x of register " 1176 "%x to %s.\n", bit, reg, (clear ? "clear" : "set")); 1177 return (-1); 1178 } 1179 return (0); 1180 } 1181 1182 static int 1183 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1184 { 1185 int err; 1186 1187 /* Clear MII ISR */ 1188 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1189 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1190 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1191 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1192 (reg << BFE_MDIO_RA_SHIFT) | 1193 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1194 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1195 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1196 1197 return (err); 1198 } 1199 1200 static int 1201 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1202 { 1203 int status; 1204 1205 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1206 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1207 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1208 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1209 (reg << BFE_MDIO_RA_SHIFT) | 1210 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1211 (val & BFE_MDIO_DATA_DATA))); 1212 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1213 1214 return (status); 1215 } 1216 1217 /* 1218 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1219 * twice 1220 */ 1221 static int 1222 bfe_setupphy(struct bfe_softc *sc) 1223 { 1224 u_int32_t val; 1225 1226 /* Enable activity LED */ 1227 bfe_readphy(sc, 26, &val); 1228 bfe_writephy(sc, 26, val & 0x7fff); 1229 bfe_readphy(sc, 26, &val); 1230 1231 /* Enable traffic meter LED mode */ 1232 bfe_readphy(sc, 27, &val); 1233 bfe_writephy(sc, 27, val | (1 << 6)); 1234 1235 return (0); 1236 } 1237 1238 static void 1239 bfe_stats_update(struct bfe_softc *sc) 1240 { 1241 u_long reg; 1242 u_int32_t *val; 1243 1244 val = &sc->bfe_hwstats.tx_good_octets; 1245 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1246 *val++ += CSR_READ_4(sc, reg); 1247 } 1248 val = &sc->bfe_hwstats.rx_good_octets; 1249 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1250 *val++ += CSR_READ_4(sc, reg); 1251 } 1252 } 1253 1254 static void 1255 bfe_txeof(struct bfe_softc *sc) 1256 { 1257 struct bfe_tx_data *r; 1258 struct ifnet *ifp; 1259 int i, chipidx; 1260 1261 BFE_LOCK_ASSERT(sc); 1262 1263 ifp = sc->bfe_ifp; 1264 1265 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1266 chipidx /= sizeof(struct bfe_desc); 1267 1268 i = sc->bfe_tx_cons; 1269 if (i == chipidx) 1270 return; 1271 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 1272 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1273 /* Go through the mbufs and free those that have been transmitted */ 1274 for (; i != chipidx; BFE_INC(i, BFE_TX_LIST_CNT)) { 1275 r = &sc->bfe_tx_ring[i]; 1276 sc->bfe_tx_cnt--; 1277 if (r->bfe_mbuf == NULL) 1278 continue; 1279 bus_dmamap_sync(sc->bfe_txmbuf_tag, r->bfe_map, 1280 BUS_DMASYNC_POSTWRITE); 1281 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map); 1282 1283 ifp->if_opackets++; 1284 m_freem(r->bfe_mbuf); 1285 r->bfe_mbuf = NULL; 1286 } 1287 1288 if (i != sc->bfe_tx_cons) { 1289 /* we freed up some mbufs */ 1290 sc->bfe_tx_cons = i; 1291 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1292 } 1293 1294 if (sc->bfe_tx_cnt == 0) 1295 sc->bfe_watchdog_timer = 0; 1296 } 1297 1298 /* Pass a received packet up the stack */ 1299 static void 1300 bfe_rxeof(struct bfe_softc *sc) 1301 { 1302 struct mbuf *m; 1303 struct ifnet *ifp; 1304 struct bfe_rxheader *rxheader; 1305 struct bfe_rx_data *r; 1306 int cons, prog; 1307 u_int32_t status, current, len, flags; 1308 1309 BFE_LOCK_ASSERT(sc); 1310 cons = sc->bfe_rx_cons; 1311 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1312 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1313 1314 ifp = sc->bfe_ifp; 1315 1316 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 1317 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1318 1319 for (prog = 0; current != cons; prog++, 1320 BFE_INC(cons, BFE_RX_LIST_CNT)) { 1321 r = &sc->bfe_rx_ring[cons]; 1322 m = r->bfe_mbuf; 1323 /* 1324 * Rx status should be read from mbuf such that we can't 1325 * delay bus_dmamap_sync(9). This hardware limiation 1326 * results in inefficent mbuf usage as bfe(4) couldn't 1327 * reuse mapped buffer from errored frame. 1328 */ 1329 if (bfe_list_newbuf(sc, cons) != 0) { 1330 ifp->if_iqdrops++; 1331 bfe_discard_buf(sc, cons); 1332 continue; 1333 } 1334 rxheader = mtod(m, struct bfe_rxheader*); 1335 len = le16toh(rxheader->len); 1336 flags = le16toh(rxheader->flags); 1337 1338 /* Remove CRC bytes. */ 1339 len -= ETHER_CRC_LEN; 1340 1341 /* flag an error and try again */ 1342 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1343 ifp->if_ierrors++; 1344 if (flags & BFE_RX_FLAG_SERR) 1345 ifp->if_collisions++; 1346 m_freem(m); 1347 continue; 1348 } 1349 1350 /* Make sure to skip header bytes written by hardware. */ 1351 m_adj(m, BFE_RX_OFFSET); 1352 m->m_len = m->m_pkthdr.len = len; 1353 1354 ifp->if_ipackets++; 1355 m->m_pkthdr.rcvif = ifp; 1356 BFE_UNLOCK(sc); 1357 (*ifp->if_input)(ifp, m); 1358 BFE_LOCK(sc); 1359 } 1360 1361 if (prog > 0) { 1362 sc->bfe_rx_cons = cons; 1363 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 1364 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1365 } 1366 } 1367 1368 static void 1369 bfe_intr(void *xsc) 1370 { 1371 struct bfe_softc *sc = xsc; 1372 struct ifnet *ifp; 1373 u_int32_t istat, flag; 1374 1375 ifp = sc->bfe_ifp; 1376 1377 BFE_LOCK(sc); 1378 1379 istat = CSR_READ_4(sc, BFE_ISTAT); 1380 1381 /* 1382 * Defer unsolicited interrupts - This is necessary because setting the 1383 * chips interrupt mask register to 0 doesn't actually stop the 1384 * interrupts 1385 */ 1386 istat &= BFE_IMASK_DEF; 1387 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1388 CSR_READ_4(sc, BFE_ISTAT); 1389 1390 /* not expecting this interrupt, disregard it */ 1391 if (istat == 0 || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1392 BFE_UNLOCK(sc); 1393 return; 1394 } 1395 1396 if (istat & BFE_ISTAT_ERRORS) { 1397 1398 if (istat & BFE_ISTAT_DSCE) { 1399 device_printf(sc->bfe_dev, "Descriptor Error\n"); 1400 bfe_stop(sc); 1401 BFE_UNLOCK(sc); 1402 return; 1403 } 1404 1405 if (istat & BFE_ISTAT_DPE) { 1406 device_printf(sc->bfe_dev, 1407 "Descriptor Protocol Error\n"); 1408 bfe_stop(sc); 1409 BFE_UNLOCK(sc); 1410 return; 1411 } 1412 1413 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1414 if (flag & BFE_STAT_EMASK) 1415 ifp->if_oerrors++; 1416 1417 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1418 if (flag & BFE_RX_FLAG_ERRORS) 1419 ifp->if_ierrors++; 1420 1421 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1422 bfe_init_locked(sc); 1423 } 1424 1425 /* A packet was received */ 1426 if (istat & BFE_ISTAT_RX) 1427 bfe_rxeof(sc); 1428 1429 /* A packet was sent */ 1430 if (istat & BFE_ISTAT_TX) 1431 bfe_txeof(sc); 1432 1433 /* We have packets pending, fire them out */ 1434 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1435 bfe_start_locked(ifp); 1436 1437 BFE_UNLOCK(sc); 1438 } 1439 1440 static int 1441 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head) 1442 { 1443 struct bfe_desc *d; 1444 struct bfe_tx_data *r, *r1; 1445 struct mbuf *m; 1446 bus_dmamap_t map; 1447 bus_dma_segment_t txsegs[BFE_MAXTXSEGS]; 1448 uint32_t cur, si; 1449 int error, i, nsegs; 1450 1451 BFE_LOCK_ASSERT(sc); 1452 1453 M_ASSERTPKTHDR((*m_head)); 1454 1455 si = cur = sc->bfe_tx_prod; 1456 r = &sc->bfe_tx_ring[cur]; 1457 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, *m_head, 1458 txsegs, &nsegs, 0); 1459 if (error == EFBIG) { 1460 m = m_collapse(*m_head, M_DONTWAIT, BFE_MAXTXSEGS); 1461 if (m == NULL) { 1462 m_freem(*m_head); 1463 *m_head = NULL; 1464 return (ENOMEM); 1465 } 1466 *m_head = m; 1467 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, 1468 *m_head, txsegs, &nsegs, 0); 1469 if (error != 0) { 1470 m_freem(*m_head); 1471 *m_head = NULL; 1472 return (error); 1473 } 1474 } else if (error != 0) 1475 return (error); 1476 if (nsegs == 0) { 1477 m_freem(*m_head); 1478 *m_head = NULL; 1479 return (EIO); 1480 } 1481 1482 if (sc->bfe_tx_cnt + nsegs > BFE_TX_LIST_CNT - 1) { 1483 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map); 1484 return (ENOBUFS); 1485 } 1486 1487 for (i = 0; i < nsegs; i++) { 1488 d = &sc->bfe_tx_list[cur]; 1489 d->bfe_ctrl = htole32(txsegs[i].ds_len & BFE_DESC_LEN); 1490 d->bfe_ctrl |= htole32(BFE_DESC_IOC); 1491 if (cur == BFE_TX_LIST_CNT - 1) 1492 /* 1493 * Tell the chip to wrap to the start of 1494 * the descriptor list. 1495 */ 1496 d->bfe_ctrl |= htole32(BFE_DESC_EOT); 1497 /* The chip needs all addresses to be added to BFE_PCI_DMA. */ 1498 d->bfe_addr = htole32(BFE_ADDR_LO(txsegs[i].ds_addr) + 1499 BFE_PCI_DMA); 1500 BFE_INC(cur, BFE_TX_LIST_CNT); 1501 } 1502 1503 /* Update producer index. */ 1504 sc->bfe_tx_prod = cur; 1505 1506 /* Set EOF on the last descriptor. */ 1507 cur = (cur + BFE_TX_LIST_CNT - 1) % BFE_TX_LIST_CNT; 1508 d = &sc->bfe_tx_list[cur]; 1509 d->bfe_ctrl |= htole32(BFE_DESC_EOF); 1510 1511 /* Lastly set SOF on the first descriptor to avoid races. */ 1512 d = &sc->bfe_tx_list[si]; 1513 d->bfe_ctrl |= htole32(BFE_DESC_SOF); 1514 1515 r1 = &sc->bfe_tx_ring[cur]; 1516 map = r->bfe_map; 1517 r->bfe_map = r1->bfe_map; 1518 r1->bfe_map = map; 1519 r1->bfe_mbuf = *m_head; 1520 sc->bfe_tx_cnt += nsegs; 1521 1522 bus_dmamap_sync(sc->bfe_txmbuf_tag, map, BUS_DMASYNC_PREWRITE); 1523 1524 return (0); 1525 } 1526 1527 /* 1528 * Set up to transmit a packet. 1529 */ 1530 static void 1531 bfe_start(struct ifnet *ifp) 1532 { 1533 BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1534 bfe_start_locked(ifp); 1535 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1536 } 1537 1538 /* 1539 * Set up to transmit a packet. The softc is already locked. 1540 */ 1541 static void 1542 bfe_start_locked(struct ifnet *ifp) 1543 { 1544 struct bfe_softc *sc; 1545 struct mbuf *m_head; 1546 int queued; 1547 1548 sc = ifp->if_softc; 1549 1550 BFE_LOCK_ASSERT(sc); 1551 1552 /* 1553 * Not much point trying to send if the link is down 1554 * or we have nothing to send. 1555 */ 1556 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1557 IFF_DRV_RUNNING || (sc->bfe_flags & BFE_FLAG_LINK) == 0) 1558 return; 1559 1560 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1561 sc->bfe_tx_cnt < BFE_TX_LIST_CNT - 1;) { 1562 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1563 if (m_head == NULL) 1564 break; 1565 1566 /* 1567 * Pack the data into the tx ring. If we dont have 1568 * enough room, let the chip drain the ring. 1569 */ 1570 if (bfe_encap(sc, &m_head)) { 1571 if (m_head == NULL) 1572 break; 1573 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1574 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1575 break; 1576 } 1577 1578 queued++; 1579 1580 /* 1581 * If there's a BPF listener, bounce a copy of this frame 1582 * to him. 1583 */ 1584 BPF_MTAP(ifp, m_head); 1585 } 1586 1587 if (queued) { 1588 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 1589 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1590 /* Transmit - twice due to apparent hardware bug */ 1591 CSR_WRITE_4(sc, BFE_DMATX_PTR, 1592 sc->bfe_tx_prod * sizeof(struct bfe_desc)); 1593 /* 1594 * XXX It seems the following write is not necessary 1595 * to kick Tx command. What might be required would be 1596 * a way flushing PCI posted write. Reading the register 1597 * back ensures the flush operation. In addition, 1598 * hardware will execute PCI posted write in the long 1599 * run and watchdog timer for the kick command was set 1600 * to 5 seconds. Therefore I think the second write 1601 * access is not necessary or could be replaced with 1602 * read operation. 1603 */ 1604 CSR_WRITE_4(sc, BFE_DMATX_PTR, 1605 sc->bfe_tx_prod * sizeof(struct bfe_desc)); 1606 1607 /* 1608 * Set a timeout in case the chip goes out to lunch. 1609 */ 1610 sc->bfe_watchdog_timer = 5; 1611 } 1612 } 1613 1614 static void 1615 bfe_init(void *xsc) 1616 { 1617 BFE_LOCK((struct bfe_softc *)xsc); 1618 bfe_init_locked(xsc); 1619 BFE_UNLOCK((struct bfe_softc *)xsc); 1620 } 1621 1622 static void 1623 bfe_init_locked(void *xsc) 1624 { 1625 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1626 struct ifnet *ifp = sc->bfe_ifp; 1627 struct mii_data *mii; 1628 1629 BFE_LOCK_ASSERT(sc); 1630 1631 mii = device_get_softc(sc->bfe_miibus); 1632 1633 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1634 return; 1635 1636 bfe_stop(sc); 1637 bfe_chip_reset(sc); 1638 1639 if (bfe_list_rx_init(sc) == ENOBUFS) { 1640 device_printf(sc->bfe_dev, 1641 "%s: Not enough memory for list buffers\n", __func__); 1642 bfe_stop(sc); 1643 return; 1644 } 1645 bfe_list_tx_init(sc); 1646 1647 bfe_set_rx_mode(sc); 1648 1649 /* Enable the chip and core */ 1650 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1651 /* Enable interrupts */ 1652 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1653 1654 /* Clear link state and change media. */ 1655 sc->bfe_flags &= ~BFE_FLAG_LINK; 1656 mii_mediachg(mii); 1657 1658 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1659 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1660 1661 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1662 } 1663 1664 /* 1665 * Set media options. 1666 */ 1667 static int 1668 bfe_ifmedia_upd(struct ifnet *ifp) 1669 { 1670 struct bfe_softc *sc; 1671 struct mii_data *mii; 1672 int error; 1673 1674 sc = ifp->if_softc; 1675 BFE_LOCK(sc); 1676 1677 mii = device_get_softc(sc->bfe_miibus); 1678 if (mii->mii_instance) { 1679 struct mii_softc *miisc; 1680 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1681 miisc = LIST_NEXT(miisc, mii_list)) 1682 mii_phy_reset(miisc); 1683 } 1684 error = mii_mediachg(mii); 1685 BFE_UNLOCK(sc); 1686 1687 return (error); 1688 } 1689 1690 /* 1691 * Report current media status. 1692 */ 1693 static void 1694 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1695 { 1696 struct bfe_softc *sc = ifp->if_softc; 1697 struct mii_data *mii; 1698 1699 BFE_LOCK(sc); 1700 mii = device_get_softc(sc->bfe_miibus); 1701 mii_pollstat(mii); 1702 ifmr->ifm_active = mii->mii_media_active; 1703 ifmr->ifm_status = mii->mii_media_status; 1704 BFE_UNLOCK(sc); 1705 } 1706 1707 static int 1708 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1709 { 1710 struct bfe_softc *sc = ifp->if_softc; 1711 struct ifreq *ifr = (struct ifreq *) data; 1712 struct mii_data *mii; 1713 int error = 0; 1714 1715 switch (command) { 1716 case SIOCSIFFLAGS: 1717 BFE_LOCK(sc); 1718 if (ifp->if_flags & IFF_UP) { 1719 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1720 bfe_set_rx_mode(sc); 1721 else if ((sc->bfe_flags & BFE_FLAG_DETACH) == 0) 1722 bfe_init_locked(sc); 1723 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1724 bfe_stop(sc); 1725 BFE_UNLOCK(sc); 1726 break; 1727 case SIOCADDMULTI: 1728 case SIOCDELMULTI: 1729 BFE_LOCK(sc); 1730 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1731 bfe_set_rx_mode(sc); 1732 BFE_UNLOCK(sc); 1733 break; 1734 case SIOCGIFMEDIA: 1735 case SIOCSIFMEDIA: 1736 mii = device_get_softc(sc->bfe_miibus); 1737 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1738 break; 1739 default: 1740 error = ether_ioctl(ifp, command, data); 1741 break; 1742 } 1743 1744 return (error); 1745 } 1746 1747 static void 1748 bfe_watchdog(struct bfe_softc *sc) 1749 { 1750 struct ifnet *ifp; 1751 1752 BFE_LOCK_ASSERT(sc); 1753 1754 if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer) 1755 return; 1756 1757 ifp = sc->bfe_ifp; 1758 1759 device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n"); 1760 1761 ifp->if_oerrors++; 1762 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1763 bfe_init_locked(sc); 1764 1765 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1766 bfe_start_locked(ifp); 1767 } 1768 1769 static void 1770 bfe_tick(void *xsc) 1771 { 1772 struct bfe_softc *sc = xsc; 1773 struct mii_data *mii; 1774 1775 BFE_LOCK_ASSERT(sc); 1776 1777 mii = device_get_softc(sc->bfe_miibus); 1778 mii_tick(mii); 1779 bfe_stats_update(sc); 1780 bfe_watchdog(sc); 1781 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1782 } 1783 1784 /* 1785 * Stop the adapter and free any mbufs allocated to the 1786 * RX and TX lists. 1787 */ 1788 static void 1789 bfe_stop(struct bfe_softc *sc) 1790 { 1791 struct ifnet *ifp; 1792 1793 BFE_LOCK_ASSERT(sc); 1794 1795 ifp = sc->bfe_ifp; 1796 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1797 sc->bfe_flags &= ~BFE_FLAG_LINK; 1798 callout_stop(&sc->bfe_stat_co); 1799 sc->bfe_watchdog_timer = 0; 1800 1801 bfe_chip_halt(sc); 1802 bfe_tx_ring_free(sc); 1803 bfe_rx_ring_free(sc); 1804 }
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