The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/bfe/if_bfe.c

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    1 /*-
    2  * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
    3  * and Duncan Barclay<dmlb@dmlb.org>
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 
   28 #include <sys/cdefs.h>
   29 __FBSDID("$FreeBSD: releng/8.0/sys/dev/bfe/if_bfe.c 195049 2009-06-26 11:45:06Z rwatson $");
   30 
   31 #include <sys/param.h>
   32 #include <sys/systm.h>
   33 #include <sys/bus.h>
   34 #include <sys/endian.h>
   35 #include <sys/kernel.h>
   36 #include <sys/malloc.h>
   37 #include <sys/mbuf.h>
   38 #include <sys/module.h>
   39 #include <sys/rman.h>
   40 #include <sys/socket.h>
   41 #include <sys/sockio.h>
   42 #include <sys/sysctl.h>
   43 
   44 #include <net/bpf.h>
   45 #include <net/if.h>
   46 #include <net/ethernet.h>
   47 #include <net/if_dl.h>
   48 #include <net/if_media.h>
   49 #include <net/if_types.h>
   50 #include <net/if_vlan_var.h>
   51 
   52 #include <dev/mii/mii.h>
   53 #include <dev/mii/miivar.h>
   54 
   55 #include <dev/pci/pcireg.h>
   56 #include <dev/pci/pcivar.h>
   57 
   58 #include <machine/bus.h>
   59 
   60 #include <dev/bfe/if_bfereg.h>
   61 
   62 MODULE_DEPEND(bfe, pci, 1, 1, 1);
   63 MODULE_DEPEND(bfe, ether, 1, 1, 1);
   64 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
   65 
   66 /* "device miibus" required.  See GENERIC if you get errors here. */
   67 #include "miibus_if.h"
   68 
   69 #define BFE_DEVDESC_MAX         64      /* Maximum device description length */
   70 
   71 static struct bfe_type bfe_devs[] = {
   72         { BCOM_VENDORID, BCOM_DEVICEID_BCM4401,
   73                 "Broadcom BCM4401 Fast Ethernet" },
   74         { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0,
   75                 "Broadcom BCM4401-B0 Fast Ethernet" },
   76                 { 0, 0, NULL }
   77 };
   78 
   79 static int  bfe_probe                           (device_t);
   80 static int  bfe_attach                          (device_t);
   81 static int  bfe_detach                          (device_t);
   82 static int  bfe_suspend                         (device_t);
   83 static int  bfe_resume                          (device_t);
   84 static void bfe_release_resources       (struct bfe_softc *);
   85 static void bfe_intr                            (void *);
   86 static int  bfe_encap                           (struct bfe_softc *, struct mbuf **);
   87 static void bfe_start                           (struct ifnet *);
   88 static void bfe_start_locked                    (struct ifnet *);
   89 static int  bfe_ioctl                           (struct ifnet *, u_long, caddr_t);
   90 static void bfe_init                            (void *);
   91 static void bfe_init_locked                     (void *);
   92 static void bfe_stop                            (struct bfe_softc *);
   93 static void bfe_watchdog                        (struct bfe_softc *);
   94 static int  bfe_shutdown                        (device_t);
   95 static void bfe_tick                            (void *);
   96 static void bfe_txeof                           (struct bfe_softc *);
   97 static void bfe_rxeof                           (struct bfe_softc *);
   98 static void bfe_set_rx_mode                     (struct bfe_softc *);
   99 static int  bfe_list_rx_init            (struct bfe_softc *);
  100 static void bfe_list_tx_init            (struct bfe_softc *);
  101 static void bfe_discard_buf             (struct bfe_softc *, int);
  102 static int  bfe_list_newbuf                     (struct bfe_softc *, int);
  103 static void bfe_rx_ring_free            (struct bfe_softc *);
  104 
  105 static void bfe_pci_setup                       (struct bfe_softc *, u_int32_t);
  106 static int  bfe_ifmedia_upd                     (struct ifnet *);
  107 static void bfe_ifmedia_sts                     (struct ifnet *, struct ifmediareq *);
  108 static int  bfe_miibus_readreg          (device_t, int, int);
  109 static int  bfe_miibus_writereg         (device_t, int, int, int);
  110 static void bfe_miibus_statchg          (device_t);
  111 static int  bfe_wait_bit                        (struct bfe_softc *, u_int32_t, u_int32_t,
  112                 u_long, const int);
  113 static void bfe_get_config                      (struct bfe_softc *sc);
  114 static void bfe_read_eeprom                     (struct bfe_softc *, u_int8_t *);
  115 static void bfe_stats_update            (struct bfe_softc *);
  116 static void bfe_clear_stats                     (struct bfe_softc *);
  117 static int  bfe_readphy                         (struct bfe_softc *, u_int32_t, u_int32_t*);
  118 static int  bfe_writephy                        (struct bfe_softc *, u_int32_t, u_int32_t);
  119 static int  bfe_resetphy                        (struct bfe_softc *);
  120 static int  bfe_setupphy                        (struct bfe_softc *);
  121 static void bfe_chip_reset                      (struct bfe_softc *);
  122 static void bfe_chip_halt                       (struct bfe_softc *);
  123 static void bfe_core_reset                      (struct bfe_softc *);
  124 static void bfe_core_disable            (struct bfe_softc *);
  125 static int  bfe_dma_alloc                       (struct bfe_softc *);
  126 static void bfe_dma_free                (struct bfe_softc *sc);
  127 static void bfe_dma_map                         (void *, bus_dma_segment_t *, int, int);
  128 static void bfe_cam_write                       (struct bfe_softc *, u_char *, int);
  129 static int  sysctl_bfe_stats            (SYSCTL_HANDLER_ARGS);
  130 
  131 static device_method_t bfe_methods[] = {
  132         /* Device interface */
  133         DEVMETHOD(device_probe,         bfe_probe),
  134         DEVMETHOD(device_attach,        bfe_attach),
  135         DEVMETHOD(device_detach,        bfe_detach),
  136         DEVMETHOD(device_shutdown,      bfe_shutdown),
  137         DEVMETHOD(device_suspend,       bfe_suspend),
  138         DEVMETHOD(device_resume,        bfe_resume),
  139 
  140         /* bus interface */
  141         DEVMETHOD(bus_print_child,      bus_generic_print_child),
  142         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
  143 
  144         /* MII interface */
  145         DEVMETHOD(miibus_readreg,       bfe_miibus_readreg),
  146         DEVMETHOD(miibus_writereg,      bfe_miibus_writereg),
  147         DEVMETHOD(miibus_statchg,       bfe_miibus_statchg),
  148 
  149         { 0, 0 }
  150 };
  151 
  152 static driver_t bfe_driver = {
  153         "bfe",
  154         bfe_methods,
  155         sizeof(struct bfe_softc)
  156 };
  157 
  158 static devclass_t bfe_devclass;
  159 
  160 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
  161 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
  162 
  163 /*
  164  * Probe for a Broadcom 4401 chip.
  165  */
  166 static int
  167 bfe_probe(device_t dev)
  168 {
  169         struct bfe_type *t;
  170 
  171         t = bfe_devs;
  172 
  173         while (t->bfe_name != NULL) {
  174                 if (pci_get_vendor(dev) == t->bfe_vid &&
  175                     pci_get_device(dev) == t->bfe_did) {
  176                         device_set_desc(dev, t->bfe_name);
  177                         return (BUS_PROBE_DEFAULT);
  178                 }
  179                 t++;
  180         }
  181 
  182         return (ENXIO);
  183 }
  184 
  185 struct bfe_dmamap_arg {
  186         bus_addr_t      bfe_busaddr;
  187 };
  188 
  189 static int
  190 bfe_dma_alloc(struct bfe_softc *sc)
  191 {
  192         struct bfe_dmamap_arg ctx;
  193         struct bfe_rx_data *rd;
  194         struct bfe_tx_data *td;
  195         int error, i;
  196 
  197         /*
  198          * parent tag.  Apparently the chip cannot handle any DMA address
  199          * greater than 1GB.
  200          */
  201         error = bus_dma_tag_create(bus_get_dma_tag(sc->bfe_dev), /* parent */
  202             1, 0,                       /* alignment, boundary */
  203             BFE_DMA_MAXADDR,            /* lowaddr */
  204             BUS_SPACE_MAXADDR,          /* highaddr */
  205             NULL, NULL,                 /* filter, filterarg */
  206             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
  207             0,                          /* nsegments */
  208             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
  209             0,                          /* flags */
  210             NULL, NULL,                 /* lockfunc, lockarg */
  211             &sc->bfe_parent_tag);
  212         if (error != 0) {
  213                 device_printf(sc->bfe_dev, "cannot create parent DMA tag.\n");
  214                 goto fail;
  215         }
  216 
  217         /* Create tag for Tx ring. */
  218         error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
  219             BFE_TX_RING_ALIGN, 0,       /* alignment, boundary */
  220             BUS_SPACE_MAXADDR,          /* lowaddr */
  221             BUS_SPACE_MAXADDR,          /* highaddr */
  222             NULL, NULL,                 /* filter, filterarg */
  223             BFE_TX_LIST_SIZE,           /* maxsize */
  224             1,                          /* nsegments */
  225             BFE_TX_LIST_SIZE,           /* maxsegsize */
  226             0,                          /* flags */
  227             NULL, NULL,                 /* lockfunc, lockarg */
  228             &sc->bfe_tx_tag);
  229         if (error != 0) {
  230                 device_printf(sc->bfe_dev, "cannot create Tx ring DMA tag.\n");
  231                 goto fail;
  232         }
  233 
  234         /* Create tag for Rx ring. */
  235         error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
  236             BFE_RX_RING_ALIGN, 0,       /* alignment, boundary */
  237             BUS_SPACE_MAXADDR,          /* lowaddr */
  238             BUS_SPACE_MAXADDR,          /* highaddr */
  239             NULL, NULL,                 /* filter, filterarg */
  240             BFE_RX_LIST_SIZE,           /* maxsize */
  241             1,                          /* nsegments */
  242             BFE_RX_LIST_SIZE,           /* maxsegsize */
  243             0,                          /* flags */
  244             NULL, NULL,                 /* lockfunc, lockarg */
  245             &sc->bfe_rx_tag);
  246         if (error != 0) {
  247                 device_printf(sc->bfe_dev, "cannot create Rx ring DMA tag.\n");
  248                 goto fail;
  249         }
  250 
  251         /* Create tag for Tx buffers. */
  252         error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
  253             1, 0,                       /* alignment, boundary */
  254             BUS_SPACE_MAXADDR,          /* lowaddr */
  255             BUS_SPACE_MAXADDR,          /* highaddr */
  256             NULL, NULL,                 /* filter, filterarg */
  257             MCLBYTES * BFE_MAXTXSEGS,   /* maxsize */
  258             BFE_MAXTXSEGS,              /* nsegments */
  259             MCLBYTES,                   /* maxsegsize */
  260             0,                          /* flags */
  261             NULL, NULL,                 /* lockfunc, lockarg */
  262             &sc->bfe_txmbuf_tag);
  263         if (error != 0) {
  264                 device_printf(sc->bfe_dev,
  265                     "cannot create Tx buffer DMA tag.\n");
  266                 goto fail;
  267         }
  268 
  269         /* Create tag for Rx buffers. */
  270         error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
  271             1, 0,                       /* alignment, boundary */
  272             BUS_SPACE_MAXADDR,          /* lowaddr */
  273             BUS_SPACE_MAXADDR,          /* highaddr */
  274             NULL, NULL,                 /* filter, filterarg */
  275             MCLBYTES,                   /* maxsize */
  276             1,                          /* nsegments */
  277             MCLBYTES,                   /* maxsegsize */
  278             0,                          /* flags */
  279             NULL, NULL,                 /* lockfunc, lockarg */
  280             &sc->bfe_rxmbuf_tag);
  281         if (error != 0) {
  282                 device_printf(sc->bfe_dev,
  283                     "cannot create Rx buffer DMA tag.\n");
  284                 goto fail;
  285         }
  286 
  287         /* Allocate DMA'able memory and load DMA map. */
  288         error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
  289           BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_tx_map);
  290         if (error != 0) {
  291                 device_printf(sc->bfe_dev,
  292                     "cannot allocate DMA'able memory for Tx ring.\n");
  293                 goto fail;
  294         }
  295         ctx.bfe_busaddr = 0;
  296         error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
  297             sc->bfe_tx_list, BFE_TX_LIST_SIZE, bfe_dma_map, &ctx,
  298             BUS_DMA_NOWAIT);
  299         if (error != 0 || ctx.bfe_busaddr == 0) {
  300                 device_printf(sc->bfe_dev,
  301                     "cannot load DMA'able memory for Tx ring.\n");
  302                 goto fail;
  303         }
  304         sc->bfe_tx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
  305 
  306         error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
  307           BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_rx_map);
  308         if (error != 0) {
  309                 device_printf(sc->bfe_dev,
  310                     "cannot allocate DMA'able memory for Rx ring.\n");
  311                 goto fail;
  312         }
  313         ctx.bfe_busaddr = 0;
  314         error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
  315             sc->bfe_rx_list, BFE_RX_LIST_SIZE, bfe_dma_map, &ctx,
  316             BUS_DMA_NOWAIT);
  317         if (error != 0 || ctx.bfe_busaddr == 0) {
  318                 device_printf(sc->bfe_dev,
  319                     "cannot load DMA'able memory for Rx ring.\n");
  320                 goto fail;
  321         }
  322         sc->bfe_rx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
  323 
  324         /* Create DMA maps for Tx buffers. */
  325         for (i = 0; i < BFE_TX_LIST_CNT; i++) {
  326                 td = &sc->bfe_tx_ring[i];
  327                 td->bfe_mbuf = NULL;
  328                 td->bfe_map = NULL;
  329                 error = bus_dmamap_create(sc->bfe_txmbuf_tag, 0, &td->bfe_map);
  330                 if (error != 0) {
  331                         device_printf(sc->bfe_dev,
  332                             "cannot create DMA map for Tx.\n");
  333                         goto fail;
  334                 }
  335         }
  336 
  337         /* Create spare DMA map for Rx buffers. */
  338         error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &sc->bfe_rx_sparemap);
  339         if (error != 0) {
  340                 device_printf(sc->bfe_dev, "cannot create spare DMA map for Rx.\n");
  341                 goto fail;
  342         }
  343         /* Create DMA maps for Rx buffers. */
  344         for (i = 0; i < BFE_RX_LIST_CNT; i++) {
  345                 rd = &sc->bfe_rx_ring[i];
  346                 rd->bfe_mbuf = NULL;
  347                 rd->bfe_map = NULL;
  348                 rd->bfe_ctrl = 0;
  349                 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &rd->bfe_map);
  350                 if (error != 0) {
  351                         device_printf(sc->bfe_dev,
  352                             "cannot create DMA map for Rx.\n");
  353                         goto fail;
  354                 }
  355         }
  356 
  357 fail:
  358         return (error);
  359 }
  360 
  361 static void
  362 bfe_dma_free(struct bfe_softc *sc)
  363 {
  364         struct bfe_tx_data *td;
  365         struct bfe_rx_data *rd;
  366         int i;
  367 
  368         /* Tx ring. */
  369         if (sc->bfe_tx_tag != NULL) {
  370                 if (sc->bfe_tx_map != NULL)
  371                         bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
  372                 if (sc->bfe_tx_map != NULL && sc->bfe_tx_list != NULL)
  373                         bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
  374                             sc->bfe_tx_map);
  375                 sc->bfe_tx_map = NULL;
  376                 sc->bfe_tx_list = NULL;
  377                 bus_dma_tag_destroy(sc->bfe_tx_tag);
  378                 sc->bfe_tx_tag = NULL;
  379         }
  380 
  381         /* Rx ring. */
  382         if (sc->bfe_rx_tag != NULL) {
  383                 if (sc->bfe_rx_map != NULL)
  384                         bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
  385                 if (sc->bfe_rx_map != NULL && sc->bfe_rx_list != NULL)
  386                         bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
  387                             sc->bfe_rx_map);
  388                 sc->bfe_rx_map = NULL;
  389                 sc->bfe_rx_list = NULL;
  390                 bus_dma_tag_destroy(sc->bfe_rx_tag);
  391                 sc->bfe_rx_tag = NULL;
  392         }
  393 
  394         /* Tx buffers. */
  395         if (sc->bfe_txmbuf_tag != NULL) {
  396                 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
  397                         td = &sc->bfe_tx_ring[i];
  398                         if (td->bfe_map != NULL) {
  399                                 bus_dmamap_destroy(sc->bfe_txmbuf_tag,
  400                                     td->bfe_map);
  401                                 td->bfe_map = NULL;
  402                         }
  403                 }
  404                 bus_dma_tag_destroy(sc->bfe_txmbuf_tag);
  405                 sc->bfe_txmbuf_tag = NULL;
  406         }
  407 
  408         /* Rx buffers. */
  409         if (sc->bfe_rxmbuf_tag != NULL) {
  410                 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
  411                         rd = &sc->bfe_rx_ring[i];
  412                         if (rd->bfe_map != NULL) {
  413                                 bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
  414                                     rd->bfe_map);
  415                                 rd->bfe_map = NULL;
  416                         }
  417                 }
  418                 if (sc->bfe_rx_sparemap != NULL) {
  419                         bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
  420                             sc->bfe_rx_sparemap);
  421                         sc->bfe_rx_sparemap = NULL;
  422                 }
  423                 bus_dma_tag_destroy(sc->bfe_rxmbuf_tag);
  424                 sc->bfe_rxmbuf_tag = NULL;
  425         }
  426 
  427         if (sc->bfe_parent_tag != NULL) {
  428                 bus_dma_tag_destroy(sc->bfe_parent_tag);
  429                 sc->bfe_parent_tag = NULL;
  430         }
  431 }
  432 
  433 static int
  434 bfe_attach(device_t dev)
  435 {
  436         struct ifnet *ifp = NULL;
  437         struct bfe_softc *sc;
  438         int error = 0, rid;
  439 
  440         sc = device_get_softc(dev);
  441         mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
  442                         MTX_DEF);
  443         callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0);
  444 
  445         sc->bfe_dev = dev;
  446 
  447         /*
  448          * Map control/status registers.
  449          */
  450         pci_enable_busmaster(dev);
  451 
  452         rid = PCIR_BAR(0);
  453         sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
  454                         RF_ACTIVE);
  455         if (sc->bfe_res == NULL) {
  456                 device_printf(dev, "couldn't map memory\n");
  457                 error = ENXIO;
  458                 goto fail;
  459         }
  460 
  461         /* Allocate interrupt */
  462         rid = 0;
  463 
  464         sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
  465                         RF_SHAREABLE | RF_ACTIVE);
  466         if (sc->bfe_irq == NULL) {
  467                 device_printf(dev, "couldn't map interrupt\n");
  468                 error = ENXIO;
  469                 goto fail;
  470         }
  471 
  472         if (bfe_dma_alloc(sc) != 0) {
  473                 device_printf(dev, "failed to allocate DMA resources\n");
  474                 error = ENXIO;
  475                 goto fail;
  476         }
  477 
  478         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
  479             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
  480             "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_bfe_stats,
  481             "I", "Statistics");
  482 
  483         /* Set up ifnet structure */
  484         ifp = sc->bfe_ifp = if_alloc(IFT_ETHER);
  485         if (ifp == NULL) {
  486                 device_printf(dev, "failed to if_alloc()\n");
  487                 error = ENOSPC;
  488                 goto fail;
  489         }
  490         ifp->if_softc = sc;
  491         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
  492         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
  493         ifp->if_ioctl = bfe_ioctl;
  494         ifp->if_start = bfe_start;
  495         ifp->if_init = bfe_init;
  496         ifp->if_mtu = ETHERMTU;
  497         IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN);
  498         ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN;
  499         IFQ_SET_READY(&ifp->if_snd);
  500 
  501         bfe_get_config(sc);
  502 
  503         /* Reset the chip and turn on the PHY */
  504         BFE_LOCK(sc);
  505         bfe_chip_reset(sc);
  506         BFE_UNLOCK(sc);
  507 
  508         if (mii_phy_probe(dev, &sc->bfe_miibus,
  509                                 bfe_ifmedia_upd, bfe_ifmedia_sts)) {
  510                 device_printf(dev, "MII without any PHY!\n");
  511                 error = ENXIO;
  512                 goto fail;
  513         }
  514 
  515         ether_ifattach(ifp, sc->bfe_enaddr);
  516 
  517         /*
  518          * Tell the upper layer(s) we support long frames.
  519          */
  520         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
  521         ifp->if_capabilities |= IFCAP_VLAN_MTU;
  522         ifp->if_capenable |= IFCAP_VLAN_MTU;
  523 
  524         /*
  525          * Hook interrupt last to avoid having to lock softc
  526          */
  527         error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE,
  528                         NULL, bfe_intr, sc, &sc->bfe_intrhand);
  529 
  530         if (error) {
  531                 device_printf(dev, "couldn't set up irq\n");
  532                 goto fail;
  533         }
  534 fail:
  535         if (error != 0)
  536                 bfe_detach(dev);
  537         return (error);
  538 }
  539 
  540 static int
  541 bfe_detach(device_t dev)
  542 {
  543         struct bfe_softc *sc;
  544         struct ifnet *ifp;
  545 
  546         sc = device_get_softc(dev);
  547 
  548         ifp = sc->bfe_ifp;
  549 
  550         if (device_is_attached(dev)) {
  551                 BFE_LOCK(sc);
  552                 sc->bfe_flags |= BFE_FLAG_DETACH;
  553                 bfe_stop(sc);
  554                 BFE_UNLOCK(sc);
  555                 callout_drain(&sc->bfe_stat_co);
  556                 if (ifp != NULL)
  557                         ether_ifdetach(ifp);
  558         }
  559 
  560         BFE_LOCK(sc);
  561         bfe_chip_reset(sc);
  562         BFE_UNLOCK(sc);
  563 
  564         bus_generic_detach(dev);
  565         if (sc->bfe_miibus != NULL)
  566                 device_delete_child(dev, sc->bfe_miibus);
  567 
  568         bfe_release_resources(sc);
  569         bfe_dma_free(sc);
  570         mtx_destroy(&sc->bfe_mtx);
  571 
  572         return (0);
  573 }
  574 
  575 /*
  576  * Stop all chip I/O so that the kernel's probe routines don't
  577  * get confused by errant DMAs when rebooting.
  578  */
  579 static int
  580 bfe_shutdown(device_t dev)
  581 {
  582         struct bfe_softc *sc;
  583 
  584         sc = device_get_softc(dev);
  585         BFE_LOCK(sc);
  586         bfe_stop(sc);
  587 
  588         BFE_UNLOCK(sc);
  589 
  590         return (0);
  591 }
  592 
  593 static int
  594 bfe_suspend(device_t dev)
  595 {
  596         struct bfe_softc *sc;
  597 
  598         sc = device_get_softc(dev);
  599         BFE_LOCK(sc);
  600         bfe_stop(sc);
  601         BFE_UNLOCK(sc);
  602 
  603         return (0);
  604 }
  605 
  606 static int
  607 bfe_resume(device_t dev)
  608 {
  609         struct bfe_softc *sc;
  610         struct ifnet *ifp;
  611 
  612         sc = device_get_softc(dev);
  613         ifp = sc->bfe_ifp;
  614         BFE_LOCK(sc);
  615         bfe_chip_reset(sc);
  616         if (ifp->if_flags & IFF_UP) {
  617                 bfe_init_locked(sc);
  618                 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
  619                     !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
  620                         bfe_start_locked(ifp);
  621         }
  622         BFE_UNLOCK(sc);
  623 
  624         return (0);
  625 }
  626 
  627 static int
  628 bfe_miibus_readreg(device_t dev, int phy, int reg)
  629 {
  630         struct bfe_softc *sc;
  631         u_int32_t ret;
  632 
  633         sc = device_get_softc(dev);
  634         if (phy != sc->bfe_phyaddr)
  635                 return (0);
  636         bfe_readphy(sc, reg, &ret);
  637 
  638         return (ret);
  639 }
  640 
  641 static int
  642 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
  643 {
  644         struct bfe_softc *sc;
  645 
  646         sc = device_get_softc(dev);
  647         if (phy != sc->bfe_phyaddr)
  648                 return (0);
  649         bfe_writephy(sc, reg, val);
  650 
  651         return (0);
  652 }
  653 
  654 static void
  655 bfe_miibus_statchg(device_t dev)
  656 {
  657         struct bfe_softc *sc;
  658         struct mii_data *mii;
  659         u_int32_t val, flow;
  660 
  661         sc = device_get_softc(dev);
  662         mii = device_get_softc(sc->bfe_miibus);
  663 
  664         sc->bfe_flags &= ~BFE_FLAG_LINK;
  665         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
  666             (IFM_ACTIVE | IFM_AVALID)) {
  667                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
  668                 case IFM_10_T:
  669                 case IFM_100_TX:
  670                         sc->bfe_flags |= BFE_FLAG_LINK;
  671                         break;
  672                 default:
  673                         break;
  674                 }
  675         }
  676 
  677         /* XXX Should stop Rx/Tx engine prior to touching MAC. */
  678         val = CSR_READ_4(sc, BFE_TX_CTRL);
  679         val &= ~BFE_TX_DUPLEX;
  680         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
  681                 val |= BFE_TX_DUPLEX;
  682                 flow = 0;
  683 #ifdef notyet
  684                 flow = CSR_READ_4(sc, BFE_RXCONF);
  685                 flow &= ~BFE_RXCONF_FLOW;
  686                 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
  687                     IFM_ETH_RXPAUSE) != 0)
  688                         flow |= BFE_RXCONF_FLOW;
  689                 CSR_WRITE_4(sc, BFE_RXCONF, flow);
  690                 /*
  691                  * It seems that the hardware has Tx pause issues
  692                  * so enable only Rx pause.
  693                  */
  694                 flow = CSR_READ_4(sc, BFE_MAC_FLOW);
  695                 flow &= ~BFE_FLOW_PAUSE_ENAB;
  696                 CSR_WRITE_4(sc, BFE_MAC_FLOW, flow);
  697 #endif
  698         }
  699         CSR_WRITE_4(sc, BFE_TX_CTRL, val);
  700 }
  701 
  702 static void
  703 bfe_tx_ring_free(struct bfe_softc *sc)
  704 {
  705         int i;
  706 
  707         for(i = 0; i < BFE_TX_LIST_CNT; i++) {
  708                 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
  709                         bus_dmamap_sync(sc->bfe_txmbuf_tag,
  710                             sc->bfe_tx_ring[i].bfe_map, BUS_DMASYNC_POSTWRITE);
  711                         bus_dmamap_unload(sc->bfe_txmbuf_tag,
  712                             sc->bfe_tx_ring[i].bfe_map);
  713                         m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
  714                         sc->bfe_tx_ring[i].bfe_mbuf = NULL;
  715                 }
  716         }
  717         bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
  718         bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
  719             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
  720 }
  721 
  722 static void
  723 bfe_rx_ring_free(struct bfe_softc *sc)
  724 {
  725         int i;
  726 
  727         for (i = 0; i < BFE_RX_LIST_CNT; i++) {
  728                 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
  729                         bus_dmamap_sync(sc->bfe_rxmbuf_tag,
  730                             sc->bfe_rx_ring[i].bfe_map, BUS_DMASYNC_POSTREAD);
  731                         bus_dmamap_unload(sc->bfe_rxmbuf_tag,
  732                             sc->bfe_rx_ring[i].bfe_map);
  733                         m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
  734                         sc->bfe_rx_ring[i].bfe_mbuf = NULL;
  735                 }
  736         }
  737         bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
  738         bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
  739             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
  740 }
  741 
  742 static int
  743 bfe_list_rx_init(struct bfe_softc *sc)
  744 {
  745         struct bfe_rx_data *rd;
  746         int i;
  747 
  748         sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
  749         bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
  750         for (i = 0; i < BFE_RX_LIST_CNT; i++) {
  751                 rd = &sc->bfe_rx_ring[i];
  752                 rd->bfe_mbuf = NULL;
  753                 rd->bfe_ctrl = 0;
  754                 if (bfe_list_newbuf(sc, i) != 0)
  755                         return (ENOBUFS);
  756         }
  757 
  758         bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
  759             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
  760         CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
  761 
  762         return (0);
  763 }
  764 
  765 static void
  766 bfe_list_tx_init(struct bfe_softc *sc)
  767 {
  768         int i;
  769 
  770         sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
  771         bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
  772         for (i = 0; i < BFE_TX_LIST_CNT; i++)
  773                 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
  774 
  775         bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
  776             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
  777 }
  778 
  779 static void
  780 bfe_discard_buf(struct bfe_softc *sc, int c)
  781 {
  782         struct bfe_rx_data *r;
  783         struct bfe_desc *d;
  784 
  785         r = &sc->bfe_rx_ring[c];
  786         d = &sc->bfe_rx_list[c];
  787         d->bfe_ctrl = htole32(r->bfe_ctrl);
  788 }
  789 
  790 static int
  791 bfe_list_newbuf(struct bfe_softc *sc, int c)
  792 {
  793         struct bfe_rxheader *rx_header;
  794         struct bfe_desc *d;
  795         struct bfe_rx_data *r;
  796         struct mbuf *m;
  797         bus_dma_segment_t segs[1];
  798         bus_dmamap_t map;
  799         u_int32_t ctrl;
  800         int nsegs;
  801 
  802         m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
  803         m->m_len = m->m_pkthdr.len = MCLBYTES;
  804 
  805         if (bus_dmamap_load_mbuf_sg(sc->bfe_rxmbuf_tag, sc->bfe_rx_sparemap,
  806             m, segs, &nsegs, 0) != 0) {
  807                 m_freem(m);
  808                 return (ENOBUFS);
  809         }
  810 
  811         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
  812         r = &sc->bfe_rx_ring[c];
  813         if (r->bfe_mbuf != NULL) {
  814                 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map,
  815                     BUS_DMASYNC_POSTREAD);
  816                 bus_dmamap_unload(sc->bfe_rxmbuf_tag, r->bfe_map);
  817         }
  818         map = r->bfe_map;
  819         r->bfe_map = sc->bfe_rx_sparemap;
  820         sc->bfe_rx_sparemap = map;
  821         r->bfe_mbuf = m;
  822 
  823         rx_header = mtod(m, struct bfe_rxheader *);
  824         rx_header->len = 0;
  825         rx_header->flags = 0;
  826         bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, BUS_DMASYNC_PREREAD);
  827         
  828         ctrl = segs[0].ds_len & BFE_DESC_LEN;
  829         KASSERT(ctrl > ETHER_MAX_LEN + 32, ("%s: buffer size too small(%d)!",
  830             __func__, ctrl));
  831         if (c == BFE_RX_LIST_CNT - 1)
  832                 ctrl |= BFE_DESC_EOT;
  833         r->bfe_ctrl = ctrl;
  834 
  835         d = &sc->bfe_rx_list[c];
  836         d->bfe_ctrl = htole32(ctrl);
  837         /* The chip needs all addresses to be added to BFE_PCI_DMA. */
  838         d->bfe_addr = htole32(BFE_ADDR_LO(segs[0].ds_addr) + BFE_PCI_DMA);
  839 
  840         return (0);
  841 }
  842 
  843 static void
  844 bfe_get_config(struct bfe_softc *sc)
  845 {
  846         u_int8_t eeprom[128];
  847 
  848         bfe_read_eeprom(sc, eeprom);
  849 
  850         sc->bfe_enaddr[0] = eeprom[79];
  851         sc->bfe_enaddr[1] = eeprom[78];
  852         sc->bfe_enaddr[2] = eeprom[81];
  853         sc->bfe_enaddr[3] = eeprom[80];
  854         sc->bfe_enaddr[4] = eeprom[83];
  855         sc->bfe_enaddr[5] = eeprom[82];
  856 
  857         sc->bfe_phyaddr = eeprom[90] & 0x1f;
  858         sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
  859 
  860         sc->bfe_core_unit = 0;
  861         sc->bfe_dma_offset = BFE_PCI_DMA;
  862 }
  863 
  864 static void
  865 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores)
  866 {
  867         u_int32_t bar_orig, pci_rev, val;
  868 
  869         bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
  870         pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
  871         pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
  872 
  873         val = CSR_READ_4(sc, BFE_SBINTVEC);
  874         val |= cores;
  875         CSR_WRITE_4(sc, BFE_SBINTVEC, val);
  876 
  877         val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
  878         val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
  879         CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
  880 
  881         pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
  882 }
  883 
  884 static void
  885 bfe_clear_stats(struct bfe_softc *sc)
  886 {
  887         uint32_t reg;
  888 
  889         BFE_LOCK_ASSERT(sc);
  890 
  891         CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
  892         for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
  893                 CSR_READ_4(sc, reg);
  894         for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
  895                 CSR_READ_4(sc, reg);
  896 }
  897 
  898 static int
  899 bfe_resetphy(struct bfe_softc *sc)
  900 {
  901         u_int32_t val;
  902 
  903         bfe_writephy(sc, 0, BMCR_RESET);
  904         DELAY(100);
  905         bfe_readphy(sc, 0, &val);
  906         if (val & BMCR_RESET) {
  907                 device_printf(sc->bfe_dev, "PHY Reset would not complete.\n");
  908                 return (ENXIO);
  909         }
  910         return (0);
  911 }
  912 
  913 static void
  914 bfe_chip_halt(struct bfe_softc *sc)
  915 {
  916         BFE_LOCK_ASSERT(sc);
  917         /* disable interrupts - not that it actually does..*/
  918         CSR_WRITE_4(sc, BFE_IMASK, 0);
  919         CSR_READ_4(sc, BFE_IMASK);
  920 
  921         CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
  922         bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
  923 
  924         CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
  925         CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
  926         DELAY(10);
  927 }
  928 
  929 static void
  930 bfe_chip_reset(struct bfe_softc *sc)
  931 {
  932         u_int32_t val;
  933 
  934         BFE_LOCK_ASSERT(sc);
  935 
  936         /* Set the interrupt vector for the enet core */
  937         bfe_pci_setup(sc, BFE_INTVEC_ENET0);
  938 
  939         /* is core up? */
  940         val = CSR_READ_4(sc, BFE_SBTMSLOW) &
  941             (BFE_RESET | BFE_REJECT | BFE_CLOCK);
  942         if (val == BFE_CLOCK) {
  943                 /* It is, so shut it down */
  944                 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
  945                 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
  946                 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
  947                 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
  948                 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
  949                         bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE,
  950                             100, 0);
  951                 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
  952         }
  953 
  954         bfe_core_reset(sc);
  955         bfe_clear_stats(sc);
  956 
  957         /*
  958          * We want the phy registers to be accessible even when
  959          * the driver is "downed" so initialize MDC preamble, frequency,
  960          * and whether internal or external phy here.
  961          */
  962 
  963         /* 4402 has 62.5Mhz SB clock and internal phy */
  964         CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
  965 
  966         /* Internal or external PHY? */
  967         val = CSR_READ_4(sc, BFE_DEVCTRL);
  968         if (!(val & BFE_IPP))
  969                 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
  970         else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
  971                 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
  972                 DELAY(100);
  973         }
  974 
  975         /* Enable CRC32 generation and set proper LED modes */
  976         BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
  977 
  978         /* Reset or clear powerdown control bit  */
  979         BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
  980 
  981         CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
  982                                 BFE_LAZY_FC_MASK));
  983 
  984         /*
  985          * We don't want lazy interrupts, so just send them at
  986          * the end of a frame, please
  987          */
  988         BFE_OR(sc, BFE_RCV_LAZY, 0);
  989 
  990         /* Set max lengths, accounting for VLAN tags */
  991         CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
  992         CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
  993 
  994         /* Set watermark XXX - magic */
  995         CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
  996 
  997         /*
  998          * Initialise DMA channels
  999          * - not forgetting dma addresses need to be added to BFE_PCI_DMA
 1000          */
 1001         CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
 1002         CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
 1003 
 1004         CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
 1005                         BFE_RX_CTRL_ENABLE);
 1006         CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
 1007 
 1008         bfe_resetphy(sc);
 1009         bfe_setupphy(sc);
 1010 }
 1011 
 1012 static void
 1013 bfe_core_disable(struct bfe_softc *sc)
 1014 {
 1015         if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
 1016                 return;
 1017 
 1018         /*
 1019          * Set reject, wait for it set, then wait for the core to stop
 1020          * being busy, then set reset and reject and enable the clocks.
 1021          */
 1022         CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
 1023         bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
 1024         bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
 1025         CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
 1026                                 BFE_RESET));
 1027         CSR_READ_4(sc, BFE_SBTMSLOW);
 1028         DELAY(10);
 1029         /* Leave reset and reject set */
 1030         CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
 1031         DELAY(10);
 1032 }
 1033 
 1034 static void
 1035 bfe_core_reset(struct bfe_softc *sc)
 1036 {
 1037         u_int32_t val;
 1038 
 1039         /* Disable the core */
 1040         bfe_core_disable(sc);
 1041 
 1042         /* and bring it back up */
 1043         CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
 1044         CSR_READ_4(sc, BFE_SBTMSLOW);
 1045         DELAY(10);
 1046 
 1047         /* Chip bug, clear SERR, IB and TO if they are set. */
 1048         if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
 1049                 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
 1050         val = CSR_READ_4(sc, BFE_SBIMSTATE);
 1051         if (val & (BFE_IBE | BFE_TO))
 1052                 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
 1053 
 1054         /* Clear reset and allow it to move through the core */
 1055         CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
 1056         CSR_READ_4(sc, BFE_SBTMSLOW);
 1057         DELAY(10);
 1058 
 1059         /* Leave the clock set */
 1060         CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
 1061         CSR_READ_4(sc, BFE_SBTMSLOW);
 1062         DELAY(10);
 1063 }
 1064 
 1065 static void
 1066 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
 1067 {
 1068         u_int32_t val;
 1069 
 1070         val  = ((u_int32_t) data[2]) << 24;
 1071         val |= ((u_int32_t) data[3]) << 16;
 1072         val |= ((u_int32_t) data[4]) <<  8;
 1073         val |= ((u_int32_t) data[5]);
 1074         CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
 1075         val = (BFE_CAM_HI_VALID |
 1076                         (((u_int32_t) data[0]) << 8) |
 1077                         (((u_int32_t) data[1])));
 1078         CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
 1079         CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
 1080                                 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT)));
 1081         bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
 1082 }
 1083 
 1084 static void
 1085 bfe_set_rx_mode(struct bfe_softc *sc)
 1086 {
 1087         struct ifnet *ifp = sc->bfe_ifp;
 1088         struct ifmultiaddr  *ifma;
 1089         u_int32_t val;
 1090         int i = 0;
 1091 
 1092         BFE_LOCK_ASSERT(sc);
 1093 
 1094         val = CSR_READ_4(sc, BFE_RXCONF);
 1095 
 1096         if (ifp->if_flags & IFF_PROMISC)
 1097                 val |= BFE_RXCONF_PROMISC;
 1098         else
 1099                 val &= ~BFE_RXCONF_PROMISC;
 1100 
 1101         if (ifp->if_flags & IFF_BROADCAST)
 1102                 val &= ~BFE_RXCONF_DBCAST;
 1103         else
 1104                 val |= BFE_RXCONF_DBCAST;
 1105 
 1106 
 1107         CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
 1108         bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++);
 1109 
 1110         if (ifp->if_flags & IFF_ALLMULTI)
 1111                 val |= BFE_RXCONF_ALLMULTI;
 1112         else {
 1113                 val &= ~BFE_RXCONF_ALLMULTI;
 1114                 if_maddr_rlock(ifp);
 1115                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 1116                         if (ifma->ifma_addr->sa_family != AF_LINK)
 1117                                 continue;
 1118                         bfe_cam_write(sc,
 1119                             LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++);
 1120                 }
 1121                 if_maddr_runlock(ifp);
 1122         }
 1123 
 1124         CSR_WRITE_4(sc, BFE_RXCONF, val);
 1125         BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
 1126 }
 1127 
 1128 static void
 1129 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 1130 {
 1131         struct bfe_dmamap_arg *ctx;
 1132 
 1133         if (error != 0)
 1134                 return;
 1135 
 1136         KASSERT(nseg == 1, ("%s : %d segments returned!", __func__, nseg));
 1137 
 1138         ctx = (struct bfe_dmamap_arg *)arg;
 1139         ctx->bfe_busaddr = segs[0].ds_addr;
 1140 }
 1141 
 1142 static void
 1143 bfe_release_resources(struct bfe_softc *sc)
 1144 {
 1145 
 1146         if (sc->bfe_intrhand != NULL)
 1147                 bus_teardown_intr(sc->bfe_dev, sc->bfe_irq, sc->bfe_intrhand);
 1148 
 1149         if (sc->bfe_irq != NULL)
 1150                 bus_release_resource(sc->bfe_dev, SYS_RES_IRQ, 0, sc->bfe_irq);
 1151 
 1152         if (sc->bfe_res != NULL)
 1153                 bus_release_resource(sc->bfe_dev, SYS_RES_MEMORY, PCIR_BAR(0),
 1154                     sc->bfe_res);
 1155 
 1156         if (sc->bfe_ifp != NULL)
 1157                 if_free(sc->bfe_ifp);
 1158 }
 1159 
 1160 static void
 1161 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data)
 1162 {
 1163         long i;
 1164         u_int16_t *ptr = (u_int16_t *)data;
 1165 
 1166         for(i = 0; i < 128; i += 2)
 1167                 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
 1168 }
 1169 
 1170 static int
 1171 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit,
 1172                 u_long timeout, const int clear)
 1173 {
 1174         u_long i;
 1175 
 1176         for (i = 0; i < timeout; i++) {
 1177                 u_int32_t val = CSR_READ_4(sc, reg);
 1178 
 1179                 if (clear && !(val & bit))
 1180                         break;
 1181                 if (!clear && (val & bit))
 1182                         break;
 1183                 DELAY(10);
 1184         }
 1185         if (i == timeout) {
 1186                 device_printf(sc->bfe_dev,
 1187                     "BUG!  Timeout waiting for bit %08x of register "
 1188                     "%x to %s.\n", bit, reg, (clear ? "clear" : "set"));
 1189                 return (-1);
 1190         }
 1191         return (0);
 1192 }
 1193 
 1194 static int
 1195 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val)
 1196 {
 1197         int err;
 1198 
 1199         /* Clear MII ISR */
 1200         CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
 1201         CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
 1202                                 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
 1203                                 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
 1204                                 (reg << BFE_MDIO_RA_SHIFT) |
 1205                                 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
 1206         err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
 1207         *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
 1208 
 1209         return (err);
 1210 }
 1211 
 1212 static int
 1213 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val)
 1214 {
 1215         int status;
 1216 
 1217         CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
 1218         CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
 1219                                 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
 1220                                 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
 1221                                 (reg << BFE_MDIO_RA_SHIFT) |
 1222                                 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
 1223                                 (val & BFE_MDIO_DATA_DATA)));
 1224         status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
 1225 
 1226         return (status);
 1227 }
 1228 
 1229 /*
 1230  * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
 1231  * twice
 1232  */
 1233 static int
 1234 bfe_setupphy(struct bfe_softc *sc)
 1235 {
 1236         u_int32_t val;
 1237 
 1238         /* Enable activity LED */
 1239         bfe_readphy(sc, 26, &val);
 1240         bfe_writephy(sc, 26, val & 0x7fff);
 1241         bfe_readphy(sc, 26, &val);
 1242 
 1243         /* Enable traffic meter LED mode */
 1244         bfe_readphy(sc, 27, &val);
 1245         bfe_writephy(sc, 27, val | (1 << 6));
 1246 
 1247         return (0);
 1248 }
 1249 
 1250 static void
 1251 bfe_stats_update(struct bfe_softc *sc)
 1252 {
 1253         struct bfe_hw_stats *stats;
 1254         struct ifnet *ifp;
 1255         uint32_t mib[BFE_MIB_CNT];
 1256         uint32_t reg, *val;
 1257 
 1258         BFE_LOCK_ASSERT(sc);
 1259 
 1260         val = mib;
 1261         CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
 1262         for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
 1263                 *val++ = CSR_READ_4(sc, reg);
 1264         for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
 1265                 *val++ = CSR_READ_4(sc, reg);
 1266 
 1267         ifp = sc->bfe_ifp;
 1268         stats = &sc->bfe_stats;
 1269         /* Tx stat. */
 1270         stats->tx_good_octets += mib[MIB_TX_GOOD_O];
 1271         stats->tx_good_frames += mib[MIB_TX_GOOD_P];
 1272         stats->tx_octets += mib[MIB_TX_O];
 1273         stats->tx_frames += mib[MIB_TX_P];
 1274         stats->tx_bcast_frames += mib[MIB_TX_BCAST];
 1275         stats->tx_mcast_frames += mib[MIB_TX_MCAST];
 1276         stats->tx_pkts_64 += mib[MIB_TX_64];
 1277         stats->tx_pkts_65_127 += mib[MIB_TX_65_127];
 1278         stats->tx_pkts_128_255 += mib[MIB_TX_128_255];
 1279         stats->tx_pkts_256_511 += mib[MIB_TX_256_511];
 1280         stats->tx_pkts_512_1023 += mib[MIB_TX_512_1023];
 1281         stats->tx_pkts_1024_max += mib[MIB_TX_1024_MAX];
 1282         stats->tx_jabbers += mib[MIB_TX_JABBER];
 1283         stats->tx_oversize_frames += mib[MIB_TX_OSIZE];
 1284         stats->tx_frag_frames += mib[MIB_TX_FRAG];
 1285         stats->tx_underruns += mib[MIB_TX_URUNS];
 1286         stats->tx_colls += mib[MIB_TX_TCOLS];
 1287         stats->tx_single_colls += mib[MIB_TX_SCOLS];
 1288         stats->tx_multi_colls += mib[MIB_TX_MCOLS];
 1289         stats->tx_excess_colls += mib[MIB_TX_ECOLS];
 1290         stats->tx_late_colls += mib[MIB_TX_LCOLS];
 1291         stats->tx_deferrals += mib[MIB_TX_DEFERED];
 1292         stats->tx_carrier_losts += mib[MIB_TX_CLOST];
 1293         stats->tx_pause_frames += mib[MIB_TX_PAUSE];
 1294         /* Rx stat. */
 1295         stats->rx_good_octets += mib[MIB_RX_GOOD_O];
 1296         stats->rx_good_frames += mib[MIB_RX_GOOD_P];
 1297         stats->rx_octets += mib[MIB_RX_O];
 1298         stats->rx_frames += mib[MIB_RX_P];
 1299         stats->rx_bcast_frames += mib[MIB_RX_BCAST];
 1300         stats->rx_mcast_frames += mib[MIB_RX_MCAST];
 1301         stats->rx_pkts_64 += mib[MIB_RX_64];
 1302         stats->rx_pkts_65_127 += mib[MIB_RX_65_127];
 1303         stats->rx_pkts_128_255 += mib[MIB_RX_128_255];
 1304         stats->rx_pkts_256_511 += mib[MIB_RX_256_511];
 1305         stats->rx_pkts_512_1023 += mib[MIB_RX_512_1023];
 1306         stats->rx_pkts_1024_max += mib[MIB_RX_1024_MAX];
 1307         stats->rx_jabbers += mib[MIB_RX_JABBER];
 1308         stats->rx_oversize_frames += mib[MIB_RX_OSIZE];
 1309         stats->rx_frag_frames += mib[MIB_RX_FRAG];
 1310         stats->rx_missed_frames += mib[MIB_RX_MISS];
 1311         stats->rx_crc_align_errs += mib[MIB_RX_CRCA];
 1312         stats->rx_runts += mib[MIB_RX_USIZE];
 1313         stats->rx_crc_errs += mib[MIB_RX_CRC];
 1314         stats->rx_align_errs += mib[MIB_RX_ALIGN];
 1315         stats->rx_symbol_errs += mib[MIB_RX_SYM];
 1316         stats->rx_pause_frames += mib[MIB_RX_PAUSE];
 1317         stats->rx_control_frames += mib[MIB_RX_NPAUSE];
 1318 
 1319         /* Update counters in ifnet. */
 1320         ifp->if_opackets += (u_long)mib[MIB_TX_GOOD_P];
 1321         ifp->if_collisions += (u_long)mib[MIB_TX_TCOLS];
 1322         ifp->if_oerrors += (u_long)mib[MIB_TX_URUNS] +
 1323             (u_long)mib[MIB_TX_ECOLS] +
 1324             (u_long)mib[MIB_TX_DEFERED] +
 1325             (u_long)mib[MIB_TX_CLOST];
 1326 
 1327         ifp->if_ipackets += (u_long)mib[MIB_RX_GOOD_P];
 1328 
 1329         ifp->if_ierrors += mib[MIB_RX_JABBER] +
 1330             mib[MIB_RX_MISS] +
 1331             mib[MIB_RX_CRCA] +
 1332             mib[MIB_RX_USIZE] +
 1333             mib[MIB_RX_CRC] +
 1334             mib[MIB_RX_ALIGN] +
 1335             mib[MIB_RX_SYM];
 1336 }
 1337 
 1338 static void
 1339 bfe_txeof(struct bfe_softc *sc)
 1340 {
 1341         struct bfe_tx_data *r;
 1342         struct ifnet *ifp;
 1343         int i, chipidx;
 1344 
 1345         BFE_LOCK_ASSERT(sc);
 1346 
 1347         ifp = sc->bfe_ifp;
 1348 
 1349         chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
 1350         chipidx /= sizeof(struct bfe_desc);
 1351 
 1352         i = sc->bfe_tx_cons;
 1353         if (i == chipidx)
 1354                 return;
 1355         bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
 1356             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 1357         /* Go through the mbufs and free those that have been transmitted */
 1358         for (; i != chipidx; BFE_INC(i, BFE_TX_LIST_CNT)) {
 1359                 r = &sc->bfe_tx_ring[i];
 1360                 sc->bfe_tx_cnt--;
 1361                 if (r->bfe_mbuf == NULL)
 1362                         continue;
 1363                 bus_dmamap_sync(sc->bfe_txmbuf_tag, r->bfe_map,
 1364                     BUS_DMASYNC_POSTWRITE);
 1365                 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
 1366 
 1367                 m_freem(r->bfe_mbuf);
 1368                 r->bfe_mbuf = NULL;
 1369         }
 1370 
 1371         if (i != sc->bfe_tx_cons) {
 1372                 /* we freed up some mbufs */
 1373                 sc->bfe_tx_cons = i;
 1374                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 1375         }
 1376 
 1377         if (sc->bfe_tx_cnt == 0)
 1378                 sc->bfe_watchdog_timer = 0;
 1379 }
 1380 
 1381 /* Pass a received packet up the stack */
 1382 static void
 1383 bfe_rxeof(struct bfe_softc *sc)
 1384 {
 1385         struct mbuf *m;
 1386         struct ifnet *ifp;
 1387         struct bfe_rxheader *rxheader;
 1388         struct bfe_rx_data *r;
 1389         int cons, prog;
 1390         u_int32_t status, current, len, flags;
 1391 
 1392         BFE_LOCK_ASSERT(sc);
 1393         cons = sc->bfe_rx_cons;
 1394         status = CSR_READ_4(sc, BFE_DMARX_STAT);
 1395         current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
 1396 
 1397         ifp = sc->bfe_ifp;
 1398 
 1399         bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
 1400             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 1401 
 1402         for (prog = 0; current != cons; prog++,
 1403             BFE_INC(cons, BFE_RX_LIST_CNT)) {
 1404                 r = &sc->bfe_rx_ring[cons];
 1405                 m = r->bfe_mbuf;
 1406                 /*
 1407                  * Rx status should be read from mbuf such that we can't
 1408                  * delay bus_dmamap_sync(9). This hardware limiation
 1409                  * results in inefficent mbuf usage as bfe(4) couldn't
 1410                  * reuse mapped buffer from errored frame. 
 1411                  */
 1412                 if (bfe_list_newbuf(sc, cons) != 0) {
 1413                         ifp->if_iqdrops++;
 1414                         bfe_discard_buf(sc, cons);
 1415                         continue;
 1416                 }
 1417                 rxheader = mtod(m, struct bfe_rxheader*);
 1418                 len = le16toh(rxheader->len);
 1419                 flags = le16toh(rxheader->flags);
 1420 
 1421                 /* Remove CRC bytes. */
 1422                 len -= ETHER_CRC_LEN;
 1423 
 1424                 /* flag an error and try again */
 1425                 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
 1426                         m_freem(m);
 1427                         continue;
 1428                 }
 1429 
 1430                 /* Make sure to skip header bytes written by hardware. */
 1431                 m_adj(m, BFE_RX_OFFSET);
 1432                 m->m_len = m->m_pkthdr.len = len;
 1433 
 1434                 m->m_pkthdr.rcvif = ifp;
 1435                 BFE_UNLOCK(sc);
 1436                 (*ifp->if_input)(ifp, m);
 1437                 BFE_LOCK(sc);
 1438         }
 1439 
 1440         if (prog > 0) {
 1441                 sc->bfe_rx_cons = cons;
 1442                 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
 1443                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 1444         }
 1445 }
 1446 
 1447 static void
 1448 bfe_intr(void *xsc)
 1449 {
 1450         struct bfe_softc *sc = xsc;
 1451         struct ifnet *ifp;
 1452         u_int32_t istat;
 1453 
 1454         ifp = sc->bfe_ifp;
 1455 
 1456         BFE_LOCK(sc);
 1457 
 1458         istat = CSR_READ_4(sc, BFE_ISTAT);
 1459 
 1460         /*
 1461          * Defer unsolicited interrupts - This is necessary because setting the
 1462          * chips interrupt mask register to 0 doesn't actually stop the
 1463          * interrupts
 1464          */
 1465         istat &= BFE_IMASK_DEF;
 1466         CSR_WRITE_4(sc, BFE_ISTAT, istat);
 1467         CSR_READ_4(sc, BFE_ISTAT);
 1468 
 1469         /* not expecting this interrupt, disregard it */
 1470         if (istat == 0 || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
 1471                 BFE_UNLOCK(sc);
 1472                 return;
 1473         }
 1474 
 1475         /* A packet was received */
 1476         if (istat & BFE_ISTAT_RX)
 1477                 bfe_rxeof(sc);
 1478 
 1479         /* A packet was sent */
 1480         if (istat & BFE_ISTAT_TX)
 1481                 bfe_txeof(sc);
 1482 
 1483         if (istat & BFE_ISTAT_ERRORS) {
 1484 
 1485                 if (istat & BFE_ISTAT_DSCE) {
 1486                         device_printf(sc->bfe_dev, "Descriptor Error\n");
 1487                         bfe_stop(sc);
 1488                         BFE_UNLOCK(sc);
 1489                         return;
 1490                 }
 1491 
 1492                 if (istat & BFE_ISTAT_DPE) {
 1493                         device_printf(sc->bfe_dev,
 1494                             "Descriptor Protocol Error\n");
 1495                         bfe_stop(sc);
 1496                         BFE_UNLOCK(sc);
 1497                         return;
 1498                 }
 1499                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 1500                 bfe_init_locked(sc);
 1501         }
 1502 
 1503         /* We have packets pending, fire them out */
 1504         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
 1505                 bfe_start_locked(ifp);
 1506 
 1507         BFE_UNLOCK(sc);
 1508 }
 1509 
 1510 static int
 1511 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head)
 1512 {
 1513         struct bfe_desc *d;
 1514         struct bfe_tx_data *r, *r1;
 1515         struct mbuf *m;
 1516         bus_dmamap_t map;
 1517         bus_dma_segment_t txsegs[BFE_MAXTXSEGS];
 1518         uint32_t cur, si;
 1519         int error, i, nsegs;
 1520 
 1521         BFE_LOCK_ASSERT(sc);
 1522 
 1523         M_ASSERTPKTHDR((*m_head));
 1524 
 1525         si = cur = sc->bfe_tx_prod;
 1526         r = &sc->bfe_tx_ring[cur];
 1527         error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, *m_head,
 1528             txsegs, &nsegs, 0);
 1529         if (error == EFBIG) {
 1530                 m = m_collapse(*m_head, M_DONTWAIT, BFE_MAXTXSEGS);
 1531                 if (m == NULL) {
 1532                         m_freem(*m_head);
 1533                         *m_head = NULL;
 1534                         return (ENOMEM);
 1535                 }
 1536                 *m_head = m;
 1537                 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map,
 1538                     *m_head, txsegs, &nsegs, 0);
 1539                 if (error != 0) {
 1540                         m_freem(*m_head);
 1541                         *m_head = NULL;
 1542                         return (error);
 1543                 }
 1544         } else if (error != 0)
 1545                 return (error);
 1546         if (nsegs == 0) {
 1547                 m_freem(*m_head);
 1548                 *m_head = NULL;
 1549                 return (EIO);
 1550         }
 1551 
 1552         if (sc->bfe_tx_cnt + nsegs > BFE_TX_LIST_CNT - 1) {
 1553                 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
 1554                 return (ENOBUFS);
 1555         }
 1556 
 1557         for (i = 0; i < nsegs; i++) {
 1558                 d = &sc->bfe_tx_list[cur];
 1559                 d->bfe_ctrl = htole32(txsegs[i].ds_len & BFE_DESC_LEN);
 1560                 d->bfe_ctrl |= htole32(BFE_DESC_IOC);
 1561                 if (cur == BFE_TX_LIST_CNT - 1)
 1562                         /*
 1563                          * Tell the chip to wrap to the start of
 1564                          * the descriptor list.
 1565                          */
 1566                         d->bfe_ctrl |= htole32(BFE_DESC_EOT);
 1567                 /* The chip needs all addresses to be added to BFE_PCI_DMA. */
 1568                 d->bfe_addr = htole32(BFE_ADDR_LO(txsegs[i].ds_addr) +
 1569                     BFE_PCI_DMA);
 1570                 BFE_INC(cur, BFE_TX_LIST_CNT);
 1571         }
 1572 
 1573         /* Update producer index. */
 1574         sc->bfe_tx_prod = cur;
 1575 
 1576         /* Set EOF on the last descriptor. */
 1577         cur = (cur + BFE_TX_LIST_CNT - 1) % BFE_TX_LIST_CNT;
 1578         d = &sc->bfe_tx_list[cur];
 1579         d->bfe_ctrl |= htole32(BFE_DESC_EOF);
 1580 
 1581         /* Lastly set SOF on the first descriptor to avoid races. */
 1582         d = &sc->bfe_tx_list[si];
 1583         d->bfe_ctrl |= htole32(BFE_DESC_SOF);
 1584 
 1585         r1 = &sc->bfe_tx_ring[cur];
 1586         map = r->bfe_map;
 1587         r->bfe_map = r1->bfe_map;
 1588         r1->bfe_map = map;
 1589         r1->bfe_mbuf = *m_head;
 1590         sc->bfe_tx_cnt += nsegs;
 1591 
 1592         bus_dmamap_sync(sc->bfe_txmbuf_tag, map, BUS_DMASYNC_PREWRITE);
 1593 
 1594         return (0);
 1595 }
 1596 
 1597 /*
 1598  * Set up to transmit a packet.
 1599  */
 1600 static void
 1601 bfe_start(struct ifnet *ifp)
 1602 {
 1603         BFE_LOCK((struct bfe_softc *)ifp->if_softc);
 1604         bfe_start_locked(ifp);
 1605         BFE_UNLOCK((struct bfe_softc *)ifp->if_softc);
 1606 }
 1607 
 1608 /*
 1609  * Set up to transmit a packet. The softc is already locked.
 1610  */
 1611 static void
 1612 bfe_start_locked(struct ifnet *ifp)
 1613 {
 1614         struct bfe_softc *sc;
 1615         struct mbuf *m_head;
 1616         int queued;
 1617 
 1618         sc = ifp->if_softc;
 1619 
 1620         BFE_LOCK_ASSERT(sc);
 1621 
 1622         /*
 1623          * Not much point trying to send if the link is down
 1624          * or we have nothing to send.
 1625          */
 1626         if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
 1627             IFF_DRV_RUNNING || (sc->bfe_flags & BFE_FLAG_LINK) == 0)
 1628                 return;
 1629 
 1630         for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
 1631             sc->bfe_tx_cnt < BFE_TX_LIST_CNT - 1;) {
 1632                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
 1633                 if (m_head == NULL)
 1634                         break;
 1635 
 1636                 /*
 1637                  * Pack the data into the tx ring.  If we dont have
 1638                  * enough room, let the chip drain the ring.
 1639                  */
 1640                 if (bfe_encap(sc, &m_head)) {
 1641                         if (m_head == NULL)
 1642                                 break;
 1643                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
 1644                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 1645                         break;
 1646                 }
 1647 
 1648                 queued++;
 1649 
 1650                 /*
 1651                  * If there's a BPF listener, bounce a copy of this frame
 1652                  * to him.
 1653                  */
 1654                 BPF_MTAP(ifp, m_head);
 1655         }
 1656 
 1657         if (queued) {
 1658                 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
 1659                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 1660                 /* Transmit - twice due to apparent hardware bug */
 1661                 CSR_WRITE_4(sc, BFE_DMATX_PTR,
 1662                     sc->bfe_tx_prod * sizeof(struct bfe_desc));
 1663                 /*
 1664                  * XXX It seems the following write is not necessary
 1665                  * to kick Tx command. What might be required would be
 1666                  * a way flushing PCI posted write. Reading the register
 1667                  * back ensures the flush operation. In addition,
 1668                  * hardware will execute PCI posted write in the long
 1669                  * run and watchdog timer for the kick command was set
 1670                  * to 5 seconds. Therefore I think the second write
 1671                  * access is not necessary or could be replaced with
 1672                  * read operation.
 1673                  */
 1674                 CSR_WRITE_4(sc, BFE_DMATX_PTR,
 1675                     sc->bfe_tx_prod * sizeof(struct bfe_desc));
 1676 
 1677                 /*
 1678                  * Set a timeout in case the chip goes out to lunch.
 1679                  */
 1680                 sc->bfe_watchdog_timer = 5;
 1681         }
 1682 }
 1683 
 1684 static void
 1685 bfe_init(void *xsc)
 1686 {
 1687         BFE_LOCK((struct bfe_softc *)xsc);
 1688         bfe_init_locked(xsc);
 1689         BFE_UNLOCK((struct bfe_softc *)xsc);
 1690 }
 1691 
 1692 static void
 1693 bfe_init_locked(void *xsc)
 1694 {
 1695         struct bfe_softc *sc = (struct bfe_softc*)xsc;
 1696         struct ifnet *ifp = sc->bfe_ifp;
 1697         struct mii_data *mii;
 1698 
 1699         BFE_LOCK_ASSERT(sc);
 1700 
 1701         mii = device_get_softc(sc->bfe_miibus);
 1702 
 1703         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
 1704                 return;
 1705 
 1706         bfe_stop(sc);
 1707         bfe_chip_reset(sc);
 1708 
 1709         if (bfe_list_rx_init(sc) == ENOBUFS) {
 1710                 device_printf(sc->bfe_dev,
 1711                     "%s: Not enough memory for list buffers\n", __func__);
 1712                 bfe_stop(sc);
 1713                 return;
 1714         }
 1715         bfe_list_tx_init(sc);
 1716 
 1717         bfe_set_rx_mode(sc);
 1718 
 1719         /* Enable the chip and core */
 1720         BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
 1721         /* Enable interrupts */
 1722         CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
 1723 
 1724         /* Clear link state and change media. */
 1725         sc->bfe_flags &= ~BFE_FLAG_LINK;
 1726         mii_mediachg(mii);
 1727 
 1728         ifp->if_drv_flags |= IFF_DRV_RUNNING;
 1729         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 1730 
 1731         callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
 1732 }
 1733 
 1734 /*
 1735  * Set media options.
 1736  */
 1737 static int
 1738 bfe_ifmedia_upd(struct ifnet *ifp)
 1739 {
 1740         struct bfe_softc *sc;
 1741         struct mii_data *mii;
 1742         int error;
 1743 
 1744         sc = ifp->if_softc;
 1745         BFE_LOCK(sc);
 1746 
 1747         mii = device_get_softc(sc->bfe_miibus);
 1748         if (mii->mii_instance) {
 1749                 struct mii_softc *miisc;
 1750                 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
 1751                                 miisc = LIST_NEXT(miisc, mii_list))
 1752                         mii_phy_reset(miisc);
 1753         }
 1754         error = mii_mediachg(mii);
 1755         BFE_UNLOCK(sc);
 1756 
 1757         return (error);
 1758 }
 1759 
 1760 /*
 1761  * Report current media status.
 1762  */
 1763 static void
 1764 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 1765 {
 1766         struct bfe_softc *sc = ifp->if_softc;
 1767         struct mii_data *mii;
 1768 
 1769         BFE_LOCK(sc);
 1770         mii = device_get_softc(sc->bfe_miibus);
 1771         mii_pollstat(mii);
 1772         ifmr->ifm_active = mii->mii_media_active;
 1773         ifmr->ifm_status = mii->mii_media_status;
 1774         BFE_UNLOCK(sc);
 1775 }
 1776 
 1777 static int
 1778 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 1779 {
 1780         struct bfe_softc *sc = ifp->if_softc;
 1781         struct ifreq *ifr = (struct ifreq *) data;
 1782         struct mii_data *mii;
 1783         int error = 0;
 1784 
 1785         switch (command) {
 1786         case SIOCSIFFLAGS:
 1787                 BFE_LOCK(sc);
 1788                 if (ifp->if_flags & IFF_UP) {
 1789                         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
 1790                                 bfe_set_rx_mode(sc);
 1791                         else if ((sc->bfe_flags & BFE_FLAG_DETACH) == 0)
 1792                                 bfe_init_locked(sc);
 1793                 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
 1794                         bfe_stop(sc);
 1795                 BFE_UNLOCK(sc);
 1796                 break;
 1797         case SIOCADDMULTI:
 1798         case SIOCDELMULTI:
 1799                 BFE_LOCK(sc);
 1800                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
 1801                         bfe_set_rx_mode(sc);
 1802                 BFE_UNLOCK(sc);
 1803                 break;
 1804         case SIOCGIFMEDIA:
 1805         case SIOCSIFMEDIA:
 1806                 mii = device_get_softc(sc->bfe_miibus);
 1807                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
 1808                 break;
 1809         default:
 1810                 error = ether_ioctl(ifp, command, data);
 1811                 break;
 1812         }
 1813 
 1814         return (error);
 1815 }
 1816 
 1817 static void
 1818 bfe_watchdog(struct bfe_softc *sc)
 1819 {
 1820         struct ifnet *ifp;
 1821 
 1822         BFE_LOCK_ASSERT(sc);
 1823 
 1824         if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer)
 1825                 return;
 1826 
 1827         ifp = sc->bfe_ifp;
 1828 
 1829         device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n");
 1830 
 1831         ifp->if_oerrors++;
 1832         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 1833         bfe_init_locked(sc);
 1834 
 1835         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
 1836                 bfe_start_locked(ifp);
 1837 }
 1838 
 1839 static void
 1840 bfe_tick(void *xsc)
 1841 {
 1842         struct bfe_softc *sc = xsc;
 1843         struct mii_data *mii;
 1844 
 1845         BFE_LOCK_ASSERT(sc);
 1846 
 1847         mii = device_get_softc(sc->bfe_miibus);
 1848         mii_tick(mii);
 1849         bfe_stats_update(sc);
 1850         bfe_watchdog(sc);
 1851         callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
 1852 }
 1853 
 1854 /*
 1855  * Stop the adapter and free any mbufs allocated to the
 1856  * RX and TX lists.
 1857  */
 1858 static void
 1859 bfe_stop(struct bfe_softc *sc)
 1860 {
 1861         struct ifnet *ifp;
 1862 
 1863         BFE_LOCK_ASSERT(sc);
 1864 
 1865         ifp = sc->bfe_ifp;
 1866         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
 1867         sc->bfe_flags &= ~BFE_FLAG_LINK;
 1868         callout_stop(&sc->bfe_stat_co);
 1869         sc->bfe_watchdog_timer = 0;
 1870 
 1871         bfe_chip_halt(sc);
 1872         bfe_tx_ring_free(sc);
 1873         bfe_rx_ring_free(sc);
 1874 }
 1875 
 1876 static int
 1877 sysctl_bfe_stats(SYSCTL_HANDLER_ARGS)
 1878 {
 1879         struct bfe_softc *sc;
 1880         struct bfe_hw_stats *stats;
 1881         int error, result;
 1882 
 1883         result = -1;
 1884         error = sysctl_handle_int(oidp, &result, 0, req);
 1885 
 1886         if (error != 0 || req->newptr == NULL)
 1887                 return (error);
 1888 
 1889         if (result != 1)
 1890                 return (error);
 1891 
 1892         sc = (struct bfe_softc *)arg1;
 1893         stats = &sc->bfe_stats;
 1894 
 1895         printf("%s statistics:\n", device_get_nameunit(sc->bfe_dev));
 1896         printf("Transmit good octets : %ju\n",
 1897             (uintmax_t)stats->tx_good_octets);
 1898         printf("Transmit good frames : %ju\n",
 1899             (uintmax_t)stats->tx_good_frames);
 1900         printf("Transmit octets : %ju\n",
 1901             (uintmax_t)stats->tx_octets);
 1902         printf("Transmit frames : %ju\n",
 1903             (uintmax_t)stats->tx_frames);
 1904         printf("Transmit broadcast frames : %ju\n",
 1905             (uintmax_t)stats->tx_bcast_frames);
 1906         printf("Transmit multicast frames : %ju\n",
 1907             (uintmax_t)stats->tx_mcast_frames);
 1908         printf("Transmit frames 64 bytes : %ju\n",
 1909             (uint64_t)stats->tx_pkts_64);
 1910         printf("Transmit frames 65 to 127 bytes : %ju\n",
 1911             (uint64_t)stats->tx_pkts_65_127);
 1912         printf("Transmit frames 128 to 255 bytes : %ju\n",
 1913             (uint64_t)stats->tx_pkts_128_255);
 1914         printf("Transmit frames 256 to 511 bytes : %ju\n",
 1915             (uint64_t)stats->tx_pkts_256_511);
 1916         printf("Transmit frames 512 to 1023 bytes : %ju\n",
 1917             (uint64_t)stats->tx_pkts_512_1023);
 1918         printf("Transmit frames 1024 to max bytes : %ju\n",
 1919             (uint64_t)stats->tx_pkts_1024_max);
 1920         printf("Transmit jabber errors : %u\n", stats->tx_jabbers);
 1921         printf("Transmit oversized frames : %ju\n",
 1922             (uint64_t)stats->tx_oversize_frames);
 1923         printf("Transmit fragmented frames : %ju\n",
 1924             (uint64_t)stats->tx_frag_frames);
 1925         printf("Transmit underruns : %u\n", stats->tx_colls);
 1926         printf("Transmit total collisions : %u\n", stats->tx_single_colls);
 1927         printf("Transmit single collisions : %u\n", stats->tx_single_colls);
 1928         printf("Transmit multiple collisions : %u\n", stats->tx_multi_colls);
 1929         printf("Transmit excess collisions : %u\n", stats->tx_excess_colls);
 1930         printf("Transmit late collisions : %u\n", stats->tx_late_colls);
 1931         printf("Transmit deferrals : %u\n", stats->tx_deferrals);
 1932         printf("Transmit carrier losts : %u\n", stats->tx_carrier_losts);
 1933         printf("Transmit pause frames : %u\n", stats->tx_pause_frames);
 1934 
 1935         printf("Receive good octets : %ju\n",
 1936             (uintmax_t)stats->rx_good_octets);
 1937         printf("Receive good frames : %ju\n",
 1938             (uintmax_t)stats->rx_good_frames);
 1939         printf("Receive octets : %ju\n",
 1940             (uintmax_t)stats->rx_octets);
 1941         printf("Receive frames : %ju\n",
 1942             (uintmax_t)stats->rx_frames);
 1943         printf("Receive broadcast frames : %ju\n",
 1944             (uintmax_t)stats->rx_bcast_frames);
 1945         printf("Receive multicast frames : %ju\n",
 1946             (uintmax_t)stats->rx_mcast_frames);
 1947         printf("Receive frames 64 bytes : %ju\n",
 1948             (uint64_t)stats->rx_pkts_64);
 1949         printf("Receive frames 65 to 127 bytes : %ju\n",
 1950             (uint64_t)stats->rx_pkts_65_127);
 1951         printf("Receive frames 128 to 255 bytes : %ju\n",
 1952             (uint64_t)stats->rx_pkts_128_255);
 1953         printf("Receive frames 256 to 511 bytes : %ju\n",
 1954             (uint64_t)stats->rx_pkts_256_511);
 1955         printf("Receive frames 512 to 1023 bytes : %ju\n",
 1956             (uint64_t)stats->rx_pkts_512_1023);
 1957         printf("Receive frames 1024 to max bytes : %ju\n",
 1958             (uint64_t)stats->rx_pkts_1024_max);
 1959         printf("Receive jabber errors : %u\n", stats->rx_jabbers);
 1960         printf("Receive oversized frames : %ju\n",
 1961             (uint64_t)stats->rx_oversize_frames);
 1962         printf("Receive fragmented frames : %ju\n",
 1963             (uint64_t)stats->rx_frag_frames);
 1964         printf("Receive missed frames : %u\n", stats->rx_missed_frames);
 1965         printf("Receive CRC align errors : %u\n", stats->rx_crc_align_errs);
 1966         printf("Receive undersized frames : %u\n", stats->rx_runts);
 1967         printf("Receive CRC errors : %u\n", stats->rx_crc_errs);
 1968         printf("Receive align errors : %u\n", stats->rx_align_errs);
 1969         printf("Receive symbol errors : %u\n", stats->rx_symbol_errs);
 1970         printf("Receive pause frames : %u\n", stats->rx_pause_frames);
 1971         printf("Receive control frames : %u\n", stats->rx_control_frames);
 1972 
 1973         return (error);
 1974 }

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