Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/bfe/if_bfe.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 5 * and Duncan Barclay<dmlb@dmlb.org> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/kernel.h> 37 #include <sys/malloc.h> 38 #include <sys/mbuf.h> 39 #include <sys/module.h> 40 #include <sys/rman.h> 41 #include <sys/socket.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 45 #include <net/bpf.h> 46 #include <net/if.h> 47 #include <net/if_var.h> 48 #include <net/ethernet.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 #include <net/if_types.h> 52 #include <net/if_vlan_var.h> 53 54 #include <dev/mii/mii.h> 55 #include <dev/mii/miivar.h> 56 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcivar.h> 59 60 #include <machine/bus.h> 61 62 #include <dev/bfe/if_bfereg.h> 63 64 MODULE_DEPEND(bfe, pci, 1, 1, 1); 65 MODULE_DEPEND(bfe, ether, 1, 1, 1); 66 MODULE_DEPEND(bfe, miibus, 1, 1, 1); 67 68 /* "device miibus" required. See GENERIC if you get errors here. */ 69 #include "miibus_if.h" 70 71 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 72 73 static struct bfe_type bfe_devs[] = { 74 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 75 "Broadcom BCM4401 Fast Ethernet" }, 76 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 77 "Broadcom BCM4401-B0 Fast Ethernet" }, 78 { 0, 0, NULL } 79 }; 80 81 static int bfe_probe (device_t); 82 static int bfe_attach (device_t); 83 static int bfe_detach (device_t); 84 static int bfe_suspend (device_t); 85 static int bfe_resume (device_t); 86 static void bfe_release_resources (struct bfe_softc *); 87 static void bfe_intr (void *); 88 static int bfe_encap (struct bfe_softc *, struct mbuf **); 89 static void bfe_start (struct ifnet *); 90 static void bfe_start_locked (struct ifnet *); 91 static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 92 static void bfe_init (void *); 93 static void bfe_init_locked (void *); 94 static void bfe_stop (struct bfe_softc *); 95 static void bfe_watchdog (struct bfe_softc *); 96 static int bfe_shutdown (device_t); 97 static void bfe_tick (void *); 98 static void bfe_txeof (struct bfe_softc *); 99 static void bfe_rxeof (struct bfe_softc *); 100 static void bfe_set_rx_mode (struct bfe_softc *); 101 static int bfe_list_rx_init (struct bfe_softc *); 102 static void bfe_list_tx_init (struct bfe_softc *); 103 static void bfe_discard_buf (struct bfe_softc *, int); 104 static int bfe_list_newbuf (struct bfe_softc *, int); 105 static void bfe_rx_ring_free (struct bfe_softc *); 106 107 static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 108 static int bfe_ifmedia_upd (struct ifnet *); 109 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 110 static int bfe_miibus_readreg (device_t, int, int); 111 static int bfe_miibus_writereg (device_t, int, int, int); 112 static void bfe_miibus_statchg (device_t); 113 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 114 u_long, const int); 115 static void bfe_get_config (struct bfe_softc *sc); 116 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 117 static void bfe_stats_update (struct bfe_softc *); 118 static void bfe_clear_stats (struct bfe_softc *); 119 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 120 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 121 static int bfe_resetphy (struct bfe_softc *); 122 static int bfe_setupphy (struct bfe_softc *); 123 static void bfe_chip_reset (struct bfe_softc *); 124 static void bfe_chip_halt (struct bfe_softc *); 125 static void bfe_core_reset (struct bfe_softc *); 126 static void bfe_core_disable (struct bfe_softc *); 127 static int bfe_dma_alloc (struct bfe_softc *); 128 static void bfe_dma_free (struct bfe_softc *sc); 129 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 130 static void bfe_cam_write (struct bfe_softc *, u_char *, int); 131 static int sysctl_bfe_stats (SYSCTL_HANDLER_ARGS); 132 133 static device_method_t bfe_methods[] = { 134 /* Device interface */ 135 DEVMETHOD(device_probe, bfe_probe), 136 DEVMETHOD(device_attach, bfe_attach), 137 DEVMETHOD(device_detach, bfe_detach), 138 DEVMETHOD(device_shutdown, bfe_shutdown), 139 DEVMETHOD(device_suspend, bfe_suspend), 140 DEVMETHOD(device_resume, bfe_resume), 141 142 /* MII interface */ 143 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 144 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 145 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 146 147 DEVMETHOD_END 148 }; 149 150 static driver_t bfe_driver = { 151 "bfe", 152 bfe_methods, 153 sizeof(struct bfe_softc) 154 }; 155 156 static devclass_t bfe_devclass; 157 158 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 159 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, bfe, bfe_devs, 160 nitems(bfe_devs) - 1); 161 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 162 163 /* 164 * Probe for a Broadcom 4401 chip. 165 */ 166 static int 167 bfe_probe(device_t dev) 168 { 169 struct bfe_type *t; 170 171 t = bfe_devs; 172 173 while (t->bfe_name != NULL) { 174 if (pci_get_vendor(dev) == t->bfe_vid && 175 pci_get_device(dev) == t->bfe_did) { 176 device_set_desc(dev, t->bfe_name); 177 return (BUS_PROBE_DEFAULT); 178 } 179 t++; 180 } 181 182 return (ENXIO); 183 } 184 185 struct bfe_dmamap_arg { 186 bus_addr_t bfe_busaddr; 187 }; 188 189 static int 190 bfe_dma_alloc(struct bfe_softc *sc) 191 { 192 struct bfe_dmamap_arg ctx; 193 struct bfe_rx_data *rd; 194 struct bfe_tx_data *td; 195 int error, i; 196 197 /* 198 * parent tag. Apparently the chip cannot handle any DMA address 199 * greater than 1GB. 200 */ 201 error = bus_dma_tag_create(bus_get_dma_tag(sc->bfe_dev), /* parent */ 202 1, 0, /* alignment, boundary */ 203 BFE_DMA_MAXADDR, /* lowaddr */ 204 BUS_SPACE_MAXADDR, /* highaddr */ 205 NULL, NULL, /* filter, filterarg */ 206 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 207 0, /* nsegments */ 208 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 209 0, /* flags */ 210 NULL, NULL, /* lockfunc, lockarg */ 211 &sc->bfe_parent_tag); 212 if (error != 0) { 213 device_printf(sc->bfe_dev, "cannot create parent DMA tag.\n"); 214 goto fail; 215 } 216 217 /* Create tag for Tx ring. */ 218 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 219 BFE_TX_RING_ALIGN, 0, /* alignment, boundary */ 220 BUS_SPACE_MAXADDR, /* lowaddr */ 221 BUS_SPACE_MAXADDR, /* highaddr */ 222 NULL, NULL, /* filter, filterarg */ 223 BFE_TX_LIST_SIZE, /* maxsize */ 224 1, /* nsegments */ 225 BFE_TX_LIST_SIZE, /* maxsegsize */ 226 0, /* flags */ 227 NULL, NULL, /* lockfunc, lockarg */ 228 &sc->bfe_tx_tag); 229 if (error != 0) { 230 device_printf(sc->bfe_dev, "cannot create Tx ring DMA tag.\n"); 231 goto fail; 232 } 233 234 /* Create tag for Rx ring. */ 235 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 236 BFE_RX_RING_ALIGN, 0, /* alignment, boundary */ 237 BUS_SPACE_MAXADDR, /* lowaddr */ 238 BUS_SPACE_MAXADDR, /* highaddr */ 239 NULL, NULL, /* filter, filterarg */ 240 BFE_RX_LIST_SIZE, /* maxsize */ 241 1, /* nsegments */ 242 BFE_RX_LIST_SIZE, /* maxsegsize */ 243 0, /* flags */ 244 NULL, NULL, /* lockfunc, lockarg */ 245 &sc->bfe_rx_tag); 246 if (error != 0) { 247 device_printf(sc->bfe_dev, "cannot create Rx ring DMA tag.\n"); 248 goto fail; 249 } 250 251 /* Create tag for Tx buffers. */ 252 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 253 1, 0, /* alignment, boundary */ 254 BUS_SPACE_MAXADDR, /* lowaddr */ 255 BUS_SPACE_MAXADDR, /* highaddr */ 256 NULL, NULL, /* filter, filterarg */ 257 MCLBYTES * BFE_MAXTXSEGS, /* maxsize */ 258 BFE_MAXTXSEGS, /* nsegments */ 259 MCLBYTES, /* maxsegsize */ 260 0, /* flags */ 261 NULL, NULL, /* lockfunc, lockarg */ 262 &sc->bfe_txmbuf_tag); 263 if (error != 0) { 264 device_printf(sc->bfe_dev, 265 "cannot create Tx buffer DMA tag.\n"); 266 goto fail; 267 } 268 269 /* Create tag for Rx buffers. */ 270 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 271 1, 0, /* alignment, boundary */ 272 BUS_SPACE_MAXADDR, /* lowaddr */ 273 BUS_SPACE_MAXADDR, /* highaddr */ 274 NULL, NULL, /* filter, filterarg */ 275 MCLBYTES, /* maxsize */ 276 1, /* nsegments */ 277 MCLBYTES, /* maxsegsize */ 278 0, /* flags */ 279 NULL, NULL, /* lockfunc, lockarg */ 280 &sc->bfe_rxmbuf_tag); 281 if (error != 0) { 282 device_printf(sc->bfe_dev, 283 "cannot create Rx buffer DMA tag.\n"); 284 goto fail; 285 } 286 287 /* Allocate DMA'able memory and load DMA map. */ 288 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 289 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_tx_map); 290 if (error != 0) { 291 device_printf(sc->bfe_dev, 292 "cannot allocate DMA'able memory for Tx ring.\n"); 293 goto fail; 294 } 295 ctx.bfe_busaddr = 0; 296 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 297 sc->bfe_tx_list, BFE_TX_LIST_SIZE, bfe_dma_map, &ctx, 298 BUS_DMA_NOWAIT); 299 if (error != 0 || ctx.bfe_busaddr == 0) { 300 device_printf(sc->bfe_dev, 301 "cannot load DMA'able memory for Tx ring.\n"); 302 goto fail; 303 } 304 sc->bfe_tx_dma = BFE_ADDR_LO(ctx.bfe_busaddr); 305 306 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 307 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_rx_map); 308 if (error != 0) { 309 device_printf(sc->bfe_dev, 310 "cannot allocate DMA'able memory for Rx ring.\n"); 311 goto fail; 312 } 313 ctx.bfe_busaddr = 0; 314 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 315 sc->bfe_rx_list, BFE_RX_LIST_SIZE, bfe_dma_map, &ctx, 316 BUS_DMA_NOWAIT); 317 if (error != 0 || ctx.bfe_busaddr == 0) { 318 device_printf(sc->bfe_dev, 319 "cannot load DMA'able memory for Rx ring.\n"); 320 goto fail; 321 } 322 sc->bfe_rx_dma = BFE_ADDR_LO(ctx.bfe_busaddr); 323 324 /* Create DMA maps for Tx buffers. */ 325 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 326 td = &sc->bfe_tx_ring[i]; 327 td->bfe_mbuf = NULL; 328 td->bfe_map = NULL; 329 error = bus_dmamap_create(sc->bfe_txmbuf_tag, 0, &td->bfe_map); 330 if (error != 0) { 331 device_printf(sc->bfe_dev, 332 "cannot create DMA map for Tx.\n"); 333 goto fail; 334 } 335 } 336 337 /* Create spare DMA map for Rx buffers. */ 338 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &sc->bfe_rx_sparemap); 339 if (error != 0) { 340 device_printf(sc->bfe_dev, "cannot create spare DMA map for Rx.\n"); 341 goto fail; 342 } 343 /* Create DMA maps for Rx buffers. */ 344 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 345 rd = &sc->bfe_rx_ring[i]; 346 rd->bfe_mbuf = NULL; 347 rd->bfe_map = NULL; 348 rd->bfe_ctrl = 0; 349 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &rd->bfe_map); 350 if (error != 0) { 351 device_printf(sc->bfe_dev, 352 "cannot create DMA map for Rx.\n"); 353 goto fail; 354 } 355 } 356 357 fail: 358 return (error); 359 } 360 361 static void 362 bfe_dma_free(struct bfe_softc *sc) 363 { 364 struct bfe_tx_data *td; 365 struct bfe_rx_data *rd; 366 int i; 367 368 /* Tx ring. */ 369 if (sc->bfe_tx_tag != NULL) { 370 if (sc->bfe_tx_dma != 0) 371 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 372 if (sc->bfe_tx_list != NULL) 373 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 374 sc->bfe_tx_map); 375 sc->bfe_tx_dma = 0; 376 sc->bfe_tx_list = NULL; 377 bus_dma_tag_destroy(sc->bfe_tx_tag); 378 sc->bfe_tx_tag = NULL; 379 } 380 381 /* Rx ring. */ 382 if (sc->bfe_rx_tag != NULL) { 383 if (sc->bfe_rx_dma != 0) 384 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 385 if (sc->bfe_rx_list != NULL) 386 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 387 sc->bfe_rx_map); 388 sc->bfe_rx_dma = 0; 389 sc->bfe_rx_list = NULL; 390 bus_dma_tag_destroy(sc->bfe_rx_tag); 391 sc->bfe_rx_tag = NULL; 392 } 393 394 /* Tx buffers. */ 395 if (sc->bfe_txmbuf_tag != NULL) { 396 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 397 td = &sc->bfe_tx_ring[i]; 398 if (td->bfe_map != NULL) { 399 bus_dmamap_destroy(sc->bfe_txmbuf_tag, 400 td->bfe_map); 401 td->bfe_map = NULL; 402 } 403 } 404 bus_dma_tag_destroy(sc->bfe_txmbuf_tag); 405 sc->bfe_txmbuf_tag = NULL; 406 } 407 408 /* Rx buffers. */ 409 if (sc->bfe_rxmbuf_tag != NULL) { 410 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 411 rd = &sc->bfe_rx_ring[i]; 412 if (rd->bfe_map != NULL) { 413 bus_dmamap_destroy(sc->bfe_rxmbuf_tag, 414 rd->bfe_map); 415 rd->bfe_map = NULL; 416 } 417 } 418 if (sc->bfe_rx_sparemap != NULL) { 419 bus_dmamap_destroy(sc->bfe_rxmbuf_tag, 420 sc->bfe_rx_sparemap); 421 sc->bfe_rx_sparemap = NULL; 422 } 423 bus_dma_tag_destroy(sc->bfe_rxmbuf_tag); 424 sc->bfe_rxmbuf_tag = NULL; 425 } 426 427 if (sc->bfe_parent_tag != NULL) { 428 bus_dma_tag_destroy(sc->bfe_parent_tag); 429 sc->bfe_parent_tag = NULL; 430 } 431 } 432 433 static int 434 bfe_attach(device_t dev) 435 { 436 struct ifnet *ifp = NULL; 437 struct bfe_softc *sc; 438 int error = 0, rid; 439 440 sc = device_get_softc(dev); 441 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 442 MTX_DEF); 443 callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0); 444 445 sc->bfe_dev = dev; 446 447 /* 448 * Map control/status registers. 449 */ 450 pci_enable_busmaster(dev); 451 452 rid = PCIR_BAR(0); 453 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 454 RF_ACTIVE); 455 if (sc->bfe_res == NULL) { 456 device_printf(dev, "couldn't map memory\n"); 457 error = ENXIO; 458 goto fail; 459 } 460 461 /* Allocate interrupt */ 462 rid = 0; 463 464 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 465 RF_SHAREABLE | RF_ACTIVE); 466 if (sc->bfe_irq == NULL) { 467 device_printf(dev, "couldn't map interrupt\n"); 468 error = ENXIO; 469 goto fail; 470 } 471 472 if (bfe_dma_alloc(sc) != 0) { 473 device_printf(dev, "failed to allocate DMA resources\n"); 474 error = ENXIO; 475 goto fail; 476 } 477 478 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 479 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 480 "stats", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 481 sysctl_bfe_stats, "I", "Statistics"); 482 483 /* Set up ifnet structure */ 484 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER); 485 if (ifp == NULL) { 486 device_printf(dev, "failed to if_alloc()\n"); 487 error = ENOSPC; 488 goto fail; 489 } 490 ifp->if_softc = sc; 491 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 492 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 493 ifp->if_ioctl = bfe_ioctl; 494 ifp->if_start = bfe_start; 495 ifp->if_init = bfe_init; 496 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 497 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 498 IFQ_SET_READY(&ifp->if_snd); 499 500 bfe_get_config(sc); 501 502 /* Reset the chip and turn on the PHY */ 503 BFE_LOCK(sc); 504 bfe_chip_reset(sc); 505 BFE_UNLOCK(sc); 506 507 error = mii_attach(dev, &sc->bfe_miibus, ifp, bfe_ifmedia_upd, 508 bfe_ifmedia_sts, BMSR_DEFCAPMASK, sc->bfe_phyaddr, MII_OFFSET_ANY, 509 0); 510 if (error != 0) { 511 device_printf(dev, "attaching PHYs failed\n"); 512 goto fail; 513 } 514 515 ether_ifattach(ifp, sc->bfe_enaddr); 516 517 /* 518 * Tell the upper layer(s) we support long frames. 519 */ 520 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 521 ifp->if_capabilities |= IFCAP_VLAN_MTU; 522 ifp->if_capenable |= IFCAP_VLAN_MTU; 523 524 /* 525 * Hook interrupt last to avoid having to lock softc 526 */ 527 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 528 NULL, bfe_intr, sc, &sc->bfe_intrhand); 529 530 if (error) { 531 device_printf(dev, "couldn't set up irq\n"); 532 goto fail; 533 } 534 fail: 535 if (error != 0) 536 bfe_detach(dev); 537 return (error); 538 } 539 540 static int 541 bfe_detach(device_t dev) 542 { 543 struct bfe_softc *sc; 544 struct ifnet *ifp; 545 546 sc = device_get_softc(dev); 547 548 ifp = sc->bfe_ifp; 549 550 if (device_is_attached(dev)) { 551 BFE_LOCK(sc); 552 sc->bfe_flags |= BFE_FLAG_DETACH; 553 bfe_stop(sc); 554 BFE_UNLOCK(sc); 555 callout_drain(&sc->bfe_stat_co); 556 if (ifp != NULL) 557 ether_ifdetach(ifp); 558 } 559 560 BFE_LOCK(sc); 561 bfe_chip_reset(sc); 562 BFE_UNLOCK(sc); 563 564 bus_generic_detach(dev); 565 if (sc->bfe_miibus != NULL) 566 device_delete_child(dev, sc->bfe_miibus); 567 568 bfe_release_resources(sc); 569 bfe_dma_free(sc); 570 mtx_destroy(&sc->bfe_mtx); 571 572 return (0); 573 } 574 575 /* 576 * Stop all chip I/O so that the kernel's probe routines don't 577 * get confused by errant DMAs when rebooting. 578 */ 579 static int 580 bfe_shutdown(device_t dev) 581 { 582 struct bfe_softc *sc; 583 584 sc = device_get_softc(dev); 585 BFE_LOCK(sc); 586 bfe_stop(sc); 587 588 BFE_UNLOCK(sc); 589 590 return (0); 591 } 592 593 static int 594 bfe_suspend(device_t dev) 595 { 596 struct bfe_softc *sc; 597 598 sc = device_get_softc(dev); 599 BFE_LOCK(sc); 600 bfe_stop(sc); 601 BFE_UNLOCK(sc); 602 603 return (0); 604 } 605 606 static int 607 bfe_resume(device_t dev) 608 { 609 struct bfe_softc *sc; 610 struct ifnet *ifp; 611 612 sc = device_get_softc(dev); 613 ifp = sc->bfe_ifp; 614 BFE_LOCK(sc); 615 bfe_chip_reset(sc); 616 if (ifp->if_flags & IFF_UP) { 617 bfe_init_locked(sc); 618 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 619 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 620 bfe_start_locked(ifp); 621 } 622 BFE_UNLOCK(sc); 623 624 return (0); 625 } 626 627 static int 628 bfe_miibus_readreg(device_t dev, int phy, int reg) 629 { 630 struct bfe_softc *sc; 631 u_int32_t ret; 632 633 sc = device_get_softc(dev); 634 bfe_readphy(sc, reg, &ret); 635 636 return (ret); 637 } 638 639 static int 640 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 641 { 642 struct bfe_softc *sc; 643 644 sc = device_get_softc(dev); 645 bfe_writephy(sc, reg, val); 646 647 return (0); 648 } 649 650 static void 651 bfe_miibus_statchg(device_t dev) 652 { 653 struct bfe_softc *sc; 654 struct mii_data *mii; 655 u_int32_t val, flow; 656 657 sc = device_get_softc(dev); 658 mii = device_get_softc(sc->bfe_miibus); 659 660 sc->bfe_flags &= ~BFE_FLAG_LINK; 661 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 662 (IFM_ACTIVE | IFM_AVALID)) { 663 switch (IFM_SUBTYPE(mii->mii_media_active)) { 664 case IFM_10_T: 665 case IFM_100_TX: 666 sc->bfe_flags |= BFE_FLAG_LINK; 667 break; 668 default: 669 break; 670 } 671 } 672 673 /* XXX Should stop Rx/Tx engine prior to touching MAC. */ 674 val = CSR_READ_4(sc, BFE_TX_CTRL); 675 val &= ~BFE_TX_DUPLEX; 676 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 677 val |= BFE_TX_DUPLEX; 678 flow = 0; 679 #ifdef notyet 680 flow = CSR_READ_4(sc, BFE_RXCONF); 681 flow &= ~BFE_RXCONF_FLOW; 682 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 683 IFM_ETH_RXPAUSE) != 0) 684 flow |= BFE_RXCONF_FLOW; 685 CSR_WRITE_4(sc, BFE_RXCONF, flow); 686 /* 687 * It seems that the hardware has Tx pause issues 688 * so enable only Rx pause. 689 */ 690 flow = CSR_READ_4(sc, BFE_MAC_FLOW); 691 flow &= ~BFE_FLOW_PAUSE_ENAB; 692 CSR_WRITE_4(sc, BFE_MAC_FLOW, flow); 693 #endif 694 } 695 CSR_WRITE_4(sc, BFE_TX_CTRL, val); 696 } 697 698 static void 699 bfe_tx_ring_free(struct bfe_softc *sc) 700 { 701 int i; 702 703 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 704 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 705 bus_dmamap_sync(sc->bfe_txmbuf_tag, 706 sc->bfe_tx_ring[i].bfe_map, BUS_DMASYNC_POSTWRITE); 707 bus_dmamap_unload(sc->bfe_txmbuf_tag, 708 sc->bfe_tx_ring[i].bfe_map); 709 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 710 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 711 } 712 } 713 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 714 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 715 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 716 } 717 718 static void 719 bfe_rx_ring_free(struct bfe_softc *sc) 720 { 721 int i; 722 723 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 724 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 725 bus_dmamap_sync(sc->bfe_rxmbuf_tag, 726 sc->bfe_rx_ring[i].bfe_map, BUS_DMASYNC_POSTREAD); 727 bus_dmamap_unload(sc->bfe_rxmbuf_tag, 728 sc->bfe_rx_ring[i].bfe_map); 729 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 730 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 731 } 732 } 733 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 734 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 735 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 736 } 737 738 static int 739 bfe_list_rx_init(struct bfe_softc *sc) 740 { 741 struct bfe_rx_data *rd; 742 int i; 743 744 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 745 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 746 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 747 rd = &sc->bfe_rx_ring[i]; 748 rd->bfe_mbuf = NULL; 749 rd->bfe_ctrl = 0; 750 if (bfe_list_newbuf(sc, i) != 0) 751 return (ENOBUFS); 752 } 753 754 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 755 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 756 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 757 758 return (0); 759 } 760 761 static void 762 bfe_list_tx_init(struct bfe_softc *sc) 763 { 764 int i; 765 766 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 767 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 768 for (i = 0; i < BFE_TX_LIST_CNT; i++) 769 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 770 771 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 772 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 773 } 774 775 static void 776 bfe_discard_buf(struct bfe_softc *sc, int c) 777 { 778 struct bfe_rx_data *r; 779 struct bfe_desc *d; 780 781 r = &sc->bfe_rx_ring[c]; 782 d = &sc->bfe_rx_list[c]; 783 d->bfe_ctrl = htole32(r->bfe_ctrl); 784 } 785 786 static int 787 bfe_list_newbuf(struct bfe_softc *sc, int c) 788 { 789 struct bfe_rxheader *rx_header; 790 struct bfe_desc *d; 791 struct bfe_rx_data *r; 792 struct mbuf *m; 793 bus_dma_segment_t segs[1]; 794 bus_dmamap_t map; 795 u_int32_t ctrl; 796 int nsegs; 797 798 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 799 if (m == NULL) 800 return (ENOBUFS); 801 m->m_len = m->m_pkthdr.len = MCLBYTES; 802 803 if (bus_dmamap_load_mbuf_sg(sc->bfe_rxmbuf_tag, sc->bfe_rx_sparemap, 804 m, segs, &nsegs, 0) != 0) { 805 m_freem(m); 806 return (ENOBUFS); 807 } 808 809 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 810 r = &sc->bfe_rx_ring[c]; 811 if (r->bfe_mbuf != NULL) { 812 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, 813 BUS_DMASYNC_POSTREAD); 814 bus_dmamap_unload(sc->bfe_rxmbuf_tag, r->bfe_map); 815 } 816 map = r->bfe_map; 817 r->bfe_map = sc->bfe_rx_sparemap; 818 sc->bfe_rx_sparemap = map; 819 r->bfe_mbuf = m; 820 821 rx_header = mtod(m, struct bfe_rxheader *); 822 rx_header->len = 0; 823 rx_header->flags = 0; 824 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, BUS_DMASYNC_PREREAD); 825 826 ctrl = segs[0].ds_len & BFE_DESC_LEN; 827 KASSERT(ctrl > ETHER_MAX_LEN + 32, ("%s: buffer size too small(%d)!", 828 __func__, ctrl)); 829 if (c == BFE_RX_LIST_CNT - 1) 830 ctrl |= BFE_DESC_EOT; 831 r->bfe_ctrl = ctrl; 832 833 d = &sc->bfe_rx_list[c]; 834 d->bfe_ctrl = htole32(ctrl); 835 /* The chip needs all addresses to be added to BFE_PCI_DMA. */ 836 d->bfe_addr = htole32(BFE_ADDR_LO(segs[0].ds_addr) + BFE_PCI_DMA); 837 838 return (0); 839 } 840 841 static void 842 bfe_get_config(struct bfe_softc *sc) 843 { 844 u_int8_t eeprom[128]; 845 846 bfe_read_eeprom(sc, eeprom); 847 848 sc->bfe_enaddr[0] = eeprom[79]; 849 sc->bfe_enaddr[1] = eeprom[78]; 850 sc->bfe_enaddr[2] = eeprom[81]; 851 sc->bfe_enaddr[3] = eeprom[80]; 852 sc->bfe_enaddr[4] = eeprom[83]; 853 sc->bfe_enaddr[5] = eeprom[82]; 854 855 sc->bfe_phyaddr = eeprom[90] & 0x1f; 856 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 857 858 sc->bfe_core_unit = 0; 859 sc->bfe_dma_offset = BFE_PCI_DMA; 860 } 861 862 static void 863 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 864 { 865 u_int32_t bar_orig, pci_rev, val; 866 867 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 868 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 869 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 870 871 val = CSR_READ_4(sc, BFE_SBINTVEC); 872 val |= cores; 873 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 874 875 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 876 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 877 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 878 879 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 880 } 881 882 static void 883 bfe_clear_stats(struct bfe_softc *sc) 884 { 885 uint32_t reg; 886 887 BFE_LOCK_ASSERT(sc); 888 889 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 890 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 891 CSR_READ_4(sc, reg); 892 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 893 CSR_READ_4(sc, reg); 894 } 895 896 static int 897 bfe_resetphy(struct bfe_softc *sc) 898 { 899 u_int32_t val; 900 901 bfe_writephy(sc, 0, BMCR_RESET); 902 DELAY(100); 903 bfe_readphy(sc, 0, &val); 904 if (val & BMCR_RESET) { 905 device_printf(sc->bfe_dev, "PHY Reset would not complete.\n"); 906 return (ENXIO); 907 } 908 return (0); 909 } 910 911 static void 912 bfe_chip_halt(struct bfe_softc *sc) 913 { 914 BFE_LOCK_ASSERT(sc); 915 /* disable interrupts - not that it actually does..*/ 916 CSR_WRITE_4(sc, BFE_IMASK, 0); 917 CSR_READ_4(sc, BFE_IMASK); 918 919 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 920 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 921 922 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 923 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 924 DELAY(10); 925 } 926 927 static void 928 bfe_chip_reset(struct bfe_softc *sc) 929 { 930 u_int32_t val; 931 932 BFE_LOCK_ASSERT(sc); 933 934 /* Set the interrupt vector for the enet core */ 935 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 936 937 /* is core up? */ 938 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 939 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 940 if (val == BFE_CLOCK) { 941 /* It is, so shut it down */ 942 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 943 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 944 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 945 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 946 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 947 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 948 100, 0); 949 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 950 } 951 952 bfe_core_reset(sc); 953 bfe_clear_stats(sc); 954 955 /* 956 * We want the phy registers to be accessible even when 957 * the driver is "downed" so initialize MDC preamble, frequency, 958 * and whether internal or external phy here. 959 */ 960 961 /* 4402 has 62.5Mhz SB clock and internal phy */ 962 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 963 964 /* Internal or external PHY? */ 965 val = CSR_READ_4(sc, BFE_DEVCTRL); 966 if (!(val & BFE_IPP)) 967 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 968 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 969 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 970 DELAY(100); 971 } 972 973 /* Enable CRC32 generation and set proper LED modes */ 974 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 975 976 /* Reset or clear powerdown control bit */ 977 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 978 979 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 980 BFE_LAZY_FC_MASK)); 981 982 /* 983 * We don't want lazy interrupts, so just send them at 984 * the end of a frame, please 985 */ 986 BFE_OR(sc, BFE_RCV_LAZY, 0); 987 988 /* Set max lengths, accounting for VLAN tags */ 989 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 990 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 991 992 /* Set watermark XXX - magic */ 993 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 994 995 /* 996 * Initialise DMA channels 997 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 998 */ 999 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 1000 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 1001 1002 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 1003 BFE_RX_CTRL_ENABLE); 1004 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 1005 1006 bfe_resetphy(sc); 1007 bfe_setupphy(sc); 1008 } 1009 1010 static void 1011 bfe_core_disable(struct bfe_softc *sc) 1012 { 1013 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 1014 return; 1015 1016 /* 1017 * Set reject, wait for it set, then wait for the core to stop 1018 * being busy, then set reset and reject and enable the clocks. 1019 */ 1020 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 1021 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 1022 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 1023 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 1024 BFE_RESET)); 1025 CSR_READ_4(sc, BFE_SBTMSLOW); 1026 DELAY(10); 1027 /* Leave reset and reject set */ 1028 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 1029 DELAY(10); 1030 } 1031 1032 static void 1033 bfe_core_reset(struct bfe_softc *sc) 1034 { 1035 u_int32_t val; 1036 1037 /* Disable the core */ 1038 bfe_core_disable(sc); 1039 1040 /* and bring it back up */ 1041 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 1042 CSR_READ_4(sc, BFE_SBTMSLOW); 1043 DELAY(10); 1044 1045 /* Chip bug, clear SERR, IB and TO if they are set. */ 1046 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 1047 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 1048 val = CSR_READ_4(sc, BFE_SBIMSTATE); 1049 if (val & (BFE_IBE | BFE_TO)) 1050 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 1051 1052 /* Clear reset and allow it to move through the core */ 1053 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 1054 CSR_READ_4(sc, BFE_SBTMSLOW); 1055 DELAY(10); 1056 1057 /* Leave the clock set */ 1058 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 1059 CSR_READ_4(sc, BFE_SBTMSLOW); 1060 DELAY(10); 1061 } 1062 1063 static void 1064 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 1065 { 1066 u_int32_t val; 1067 1068 val = ((u_int32_t) data[2]) << 24; 1069 val |= ((u_int32_t) data[3]) << 16; 1070 val |= ((u_int32_t) data[4]) << 8; 1071 val |= ((u_int32_t) data[5]); 1072 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 1073 val = (BFE_CAM_HI_VALID | 1074 (((u_int32_t) data[0]) << 8) | 1075 (((u_int32_t) data[1]))); 1076 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 1077 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 1078 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 1079 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 1080 } 1081 1082 static u_int 1083 bfe_write_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1084 { 1085 struct bfe_softc *sc = arg; 1086 1087 bfe_cam_write(sc, LLADDR(sdl), cnt + 1); 1088 1089 return (1); 1090 } 1091 1092 static void 1093 bfe_set_rx_mode(struct bfe_softc *sc) 1094 { 1095 struct ifnet *ifp = sc->bfe_ifp; 1096 u_int32_t val; 1097 1098 BFE_LOCK_ASSERT(sc); 1099 1100 val = CSR_READ_4(sc, BFE_RXCONF); 1101 1102 if (ifp->if_flags & IFF_PROMISC) 1103 val |= BFE_RXCONF_PROMISC; 1104 else 1105 val &= ~BFE_RXCONF_PROMISC; 1106 1107 if (ifp->if_flags & IFF_BROADCAST) 1108 val &= ~BFE_RXCONF_DBCAST; 1109 else 1110 val |= BFE_RXCONF_DBCAST; 1111 1112 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 1113 bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), 0); 1114 1115 if (ifp->if_flags & IFF_ALLMULTI) 1116 val |= BFE_RXCONF_ALLMULTI; 1117 else { 1118 val &= ~BFE_RXCONF_ALLMULTI; 1119 if_foreach_llmaddr(ifp, bfe_write_maddr, sc); 1120 } 1121 1122 CSR_WRITE_4(sc, BFE_RXCONF, val); 1123 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 1124 } 1125 1126 static void 1127 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1128 { 1129 struct bfe_dmamap_arg *ctx; 1130 1131 if (error != 0) 1132 return; 1133 1134 KASSERT(nseg == 1, ("%s : %d segments returned!", __func__, nseg)); 1135 1136 ctx = (struct bfe_dmamap_arg *)arg; 1137 ctx->bfe_busaddr = segs[0].ds_addr; 1138 } 1139 1140 static void 1141 bfe_release_resources(struct bfe_softc *sc) 1142 { 1143 1144 if (sc->bfe_intrhand != NULL) 1145 bus_teardown_intr(sc->bfe_dev, sc->bfe_irq, sc->bfe_intrhand); 1146 1147 if (sc->bfe_irq != NULL) 1148 bus_release_resource(sc->bfe_dev, SYS_RES_IRQ, 0, sc->bfe_irq); 1149 1150 if (sc->bfe_res != NULL) 1151 bus_release_resource(sc->bfe_dev, SYS_RES_MEMORY, PCIR_BAR(0), 1152 sc->bfe_res); 1153 1154 if (sc->bfe_ifp != NULL) 1155 if_free(sc->bfe_ifp); 1156 } 1157 1158 static void 1159 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 1160 { 1161 long i; 1162 u_int16_t *ptr = (u_int16_t *)data; 1163 1164 for(i = 0; i < 128; i += 2) 1165 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 1166 } 1167 1168 static int 1169 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1170 u_long timeout, const int clear) 1171 { 1172 u_long i; 1173 1174 for (i = 0; i < timeout; i++) { 1175 u_int32_t val = CSR_READ_4(sc, reg); 1176 1177 if (clear && !(val & bit)) 1178 break; 1179 if (!clear && (val & bit)) 1180 break; 1181 DELAY(10); 1182 } 1183 if (i == timeout) { 1184 device_printf(sc->bfe_dev, 1185 "BUG! Timeout waiting for bit %08x of register " 1186 "%x to %s.\n", bit, reg, (clear ? "clear" : "set")); 1187 return (-1); 1188 } 1189 return (0); 1190 } 1191 1192 static int 1193 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1194 { 1195 int err; 1196 1197 /* Clear MII ISR */ 1198 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1199 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1200 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1201 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1202 (reg << BFE_MDIO_RA_SHIFT) | 1203 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1204 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1205 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1206 1207 return (err); 1208 } 1209 1210 static int 1211 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1212 { 1213 int status; 1214 1215 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1216 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1217 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1218 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1219 (reg << BFE_MDIO_RA_SHIFT) | 1220 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1221 (val & BFE_MDIO_DATA_DATA))); 1222 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1223 1224 return (status); 1225 } 1226 1227 /* 1228 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1229 * twice 1230 */ 1231 static int 1232 bfe_setupphy(struct bfe_softc *sc) 1233 { 1234 u_int32_t val; 1235 1236 /* Enable activity LED */ 1237 bfe_readphy(sc, 26, &val); 1238 bfe_writephy(sc, 26, val & 0x7fff); 1239 bfe_readphy(sc, 26, &val); 1240 1241 /* Enable traffic meter LED mode */ 1242 bfe_readphy(sc, 27, &val); 1243 bfe_writephy(sc, 27, val | (1 << 6)); 1244 1245 return (0); 1246 } 1247 1248 static void 1249 bfe_stats_update(struct bfe_softc *sc) 1250 { 1251 struct bfe_hw_stats *stats; 1252 struct ifnet *ifp; 1253 uint32_t mib[BFE_MIB_CNT]; 1254 uint32_t reg, *val; 1255 1256 BFE_LOCK_ASSERT(sc); 1257 1258 val = mib; 1259 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 1260 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 1261 *val++ = CSR_READ_4(sc, reg); 1262 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 1263 *val++ = CSR_READ_4(sc, reg); 1264 1265 ifp = sc->bfe_ifp; 1266 stats = &sc->bfe_stats; 1267 /* Tx stat. */ 1268 stats->tx_good_octets += mib[MIB_TX_GOOD_O]; 1269 stats->tx_good_frames += mib[MIB_TX_GOOD_P]; 1270 stats->tx_octets += mib[MIB_TX_O]; 1271 stats->tx_frames += mib[MIB_TX_P]; 1272 stats->tx_bcast_frames += mib[MIB_TX_BCAST]; 1273 stats->tx_mcast_frames += mib[MIB_TX_MCAST]; 1274 stats->tx_pkts_64 += mib[MIB_TX_64]; 1275 stats->tx_pkts_65_127 += mib[MIB_TX_65_127]; 1276 stats->tx_pkts_128_255 += mib[MIB_TX_128_255]; 1277 stats->tx_pkts_256_511 += mib[MIB_TX_256_511]; 1278 stats->tx_pkts_512_1023 += mib[MIB_TX_512_1023]; 1279 stats->tx_pkts_1024_max += mib[MIB_TX_1024_MAX]; 1280 stats->tx_jabbers += mib[MIB_TX_JABBER]; 1281 stats->tx_oversize_frames += mib[MIB_TX_OSIZE]; 1282 stats->tx_frag_frames += mib[MIB_TX_FRAG]; 1283 stats->tx_underruns += mib[MIB_TX_URUNS]; 1284 stats->tx_colls += mib[MIB_TX_TCOLS]; 1285 stats->tx_single_colls += mib[MIB_TX_SCOLS]; 1286 stats->tx_multi_colls += mib[MIB_TX_MCOLS]; 1287 stats->tx_excess_colls += mib[MIB_TX_ECOLS]; 1288 stats->tx_late_colls += mib[MIB_TX_LCOLS]; 1289 stats->tx_deferrals += mib[MIB_TX_DEFERED]; 1290 stats->tx_carrier_losts += mib[MIB_TX_CLOST]; 1291 stats->tx_pause_frames += mib[MIB_TX_PAUSE]; 1292 /* Rx stat. */ 1293 stats->rx_good_octets += mib[MIB_RX_GOOD_O]; 1294 stats->rx_good_frames += mib[MIB_RX_GOOD_P]; 1295 stats->rx_octets += mib[MIB_RX_O]; 1296 stats->rx_frames += mib[MIB_RX_P]; 1297 stats->rx_bcast_frames += mib[MIB_RX_BCAST]; 1298 stats->rx_mcast_frames += mib[MIB_RX_MCAST]; 1299 stats->rx_pkts_64 += mib[MIB_RX_64]; 1300 stats->rx_pkts_65_127 += mib[MIB_RX_65_127]; 1301 stats->rx_pkts_128_255 += mib[MIB_RX_128_255]; 1302 stats->rx_pkts_256_511 += mib[MIB_RX_256_511]; 1303 stats->rx_pkts_512_1023 += mib[MIB_RX_512_1023]; 1304 stats->rx_pkts_1024_max += mib[MIB_RX_1024_MAX]; 1305 stats->rx_jabbers += mib[MIB_RX_JABBER]; 1306 stats->rx_oversize_frames += mib[MIB_RX_OSIZE]; 1307 stats->rx_frag_frames += mib[MIB_RX_FRAG]; 1308 stats->rx_missed_frames += mib[MIB_RX_MISS]; 1309 stats->rx_crc_align_errs += mib[MIB_RX_CRCA]; 1310 stats->rx_runts += mib[MIB_RX_USIZE]; 1311 stats->rx_crc_errs += mib[MIB_RX_CRC]; 1312 stats->rx_align_errs += mib[MIB_RX_ALIGN]; 1313 stats->rx_symbol_errs += mib[MIB_RX_SYM]; 1314 stats->rx_pause_frames += mib[MIB_RX_PAUSE]; 1315 stats->rx_control_frames += mib[MIB_RX_NPAUSE]; 1316 1317 /* Update counters in ifnet. */ 1318 if_inc_counter(ifp, IFCOUNTER_OPACKETS, (u_long)mib[MIB_TX_GOOD_P]); 1319 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (u_long)mib[MIB_TX_TCOLS]); 1320 if_inc_counter(ifp, IFCOUNTER_OERRORS, (u_long)mib[MIB_TX_URUNS] + 1321 (u_long)mib[MIB_TX_ECOLS] + 1322 (u_long)mib[MIB_TX_DEFERED] + 1323 (u_long)mib[MIB_TX_CLOST]); 1324 1325 if_inc_counter(ifp, IFCOUNTER_IPACKETS, (u_long)mib[MIB_RX_GOOD_P]); 1326 1327 if_inc_counter(ifp, IFCOUNTER_IERRORS, mib[MIB_RX_JABBER] + 1328 mib[MIB_RX_MISS] + 1329 mib[MIB_RX_CRCA] + 1330 mib[MIB_RX_USIZE] + 1331 mib[MIB_RX_CRC] + 1332 mib[MIB_RX_ALIGN] + 1333 mib[MIB_RX_SYM]); 1334 } 1335 1336 static void 1337 bfe_txeof(struct bfe_softc *sc) 1338 { 1339 struct bfe_tx_data *r; 1340 struct ifnet *ifp; 1341 int i, chipidx; 1342 1343 BFE_LOCK_ASSERT(sc); 1344 1345 ifp = sc->bfe_ifp; 1346 1347 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1348 chipidx /= sizeof(struct bfe_desc); 1349 1350 i = sc->bfe_tx_cons; 1351 if (i == chipidx) 1352 return; 1353 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 1354 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1355 /* Go through the mbufs and free those that have been transmitted */ 1356 for (; i != chipidx; BFE_INC(i, BFE_TX_LIST_CNT)) { 1357 r = &sc->bfe_tx_ring[i]; 1358 sc->bfe_tx_cnt--; 1359 if (r->bfe_mbuf == NULL) 1360 continue; 1361 bus_dmamap_sync(sc->bfe_txmbuf_tag, r->bfe_map, 1362 BUS_DMASYNC_POSTWRITE); 1363 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map); 1364 1365 m_freem(r->bfe_mbuf); 1366 r->bfe_mbuf = NULL; 1367 } 1368 1369 if (i != sc->bfe_tx_cons) { 1370 /* we freed up some mbufs */ 1371 sc->bfe_tx_cons = i; 1372 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1373 } 1374 1375 if (sc->bfe_tx_cnt == 0) 1376 sc->bfe_watchdog_timer = 0; 1377 } 1378 1379 /* Pass a received packet up the stack */ 1380 static void 1381 bfe_rxeof(struct bfe_softc *sc) 1382 { 1383 struct mbuf *m; 1384 struct ifnet *ifp; 1385 struct bfe_rxheader *rxheader; 1386 struct bfe_rx_data *r; 1387 int cons, prog; 1388 u_int32_t status, current, len, flags; 1389 1390 BFE_LOCK_ASSERT(sc); 1391 cons = sc->bfe_rx_cons; 1392 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1393 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1394 1395 ifp = sc->bfe_ifp; 1396 1397 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 1398 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1399 1400 for (prog = 0; current != cons; prog++, 1401 BFE_INC(cons, BFE_RX_LIST_CNT)) { 1402 r = &sc->bfe_rx_ring[cons]; 1403 m = r->bfe_mbuf; 1404 /* 1405 * Rx status should be read from mbuf such that we can't 1406 * delay bus_dmamap_sync(9). This hardware limiation 1407 * results in inefficent mbuf usage as bfe(4) couldn't 1408 * reuse mapped buffer from errored frame. 1409 */ 1410 if (bfe_list_newbuf(sc, cons) != 0) { 1411 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1412 bfe_discard_buf(sc, cons); 1413 continue; 1414 } 1415 rxheader = mtod(m, struct bfe_rxheader*); 1416 len = le16toh(rxheader->len); 1417 flags = le16toh(rxheader->flags); 1418 1419 /* Remove CRC bytes. */ 1420 len -= ETHER_CRC_LEN; 1421 1422 /* flag an error and try again */ 1423 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1424 m_freem(m); 1425 continue; 1426 } 1427 1428 /* Make sure to skip header bytes written by hardware. */ 1429 m_adj(m, BFE_RX_OFFSET); 1430 m->m_len = m->m_pkthdr.len = len; 1431 1432 m->m_pkthdr.rcvif = ifp; 1433 BFE_UNLOCK(sc); 1434 (*ifp->if_input)(ifp, m); 1435 BFE_LOCK(sc); 1436 } 1437 1438 if (prog > 0) { 1439 sc->bfe_rx_cons = cons; 1440 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 1441 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1442 } 1443 } 1444 1445 static void 1446 bfe_intr(void *xsc) 1447 { 1448 struct bfe_softc *sc = xsc; 1449 struct ifnet *ifp; 1450 u_int32_t istat; 1451 1452 ifp = sc->bfe_ifp; 1453 1454 BFE_LOCK(sc); 1455 1456 istat = CSR_READ_4(sc, BFE_ISTAT); 1457 1458 /* 1459 * Defer unsolicited interrupts - This is necessary because setting the 1460 * chips interrupt mask register to 0 doesn't actually stop the 1461 * interrupts 1462 */ 1463 istat &= BFE_IMASK_DEF; 1464 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1465 CSR_READ_4(sc, BFE_ISTAT); 1466 1467 /* not expecting this interrupt, disregard it */ 1468 if (istat == 0 || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1469 BFE_UNLOCK(sc); 1470 return; 1471 } 1472 1473 /* A packet was received */ 1474 if (istat & BFE_ISTAT_RX) 1475 bfe_rxeof(sc); 1476 1477 /* A packet was sent */ 1478 if (istat & BFE_ISTAT_TX) 1479 bfe_txeof(sc); 1480 1481 if (istat & BFE_ISTAT_ERRORS) { 1482 if (istat & BFE_ISTAT_DSCE) { 1483 device_printf(sc->bfe_dev, "Descriptor Error\n"); 1484 bfe_stop(sc); 1485 BFE_UNLOCK(sc); 1486 return; 1487 } 1488 1489 if (istat & BFE_ISTAT_DPE) { 1490 device_printf(sc->bfe_dev, 1491 "Descriptor Protocol Error\n"); 1492 bfe_stop(sc); 1493 BFE_UNLOCK(sc); 1494 return; 1495 } 1496 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1497 bfe_init_locked(sc); 1498 } 1499 1500 /* We have packets pending, fire them out */ 1501 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1502 bfe_start_locked(ifp); 1503 1504 BFE_UNLOCK(sc); 1505 } 1506 1507 static int 1508 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head) 1509 { 1510 struct bfe_desc *d; 1511 struct bfe_tx_data *r, *r1; 1512 struct mbuf *m; 1513 bus_dmamap_t map; 1514 bus_dma_segment_t txsegs[BFE_MAXTXSEGS]; 1515 uint32_t cur, si; 1516 int error, i, nsegs; 1517 1518 BFE_LOCK_ASSERT(sc); 1519 1520 M_ASSERTPKTHDR((*m_head)); 1521 1522 si = cur = sc->bfe_tx_prod; 1523 r = &sc->bfe_tx_ring[cur]; 1524 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, *m_head, 1525 txsegs, &nsegs, 0); 1526 if (error == EFBIG) { 1527 m = m_collapse(*m_head, M_NOWAIT, BFE_MAXTXSEGS); 1528 if (m == NULL) { 1529 m_freem(*m_head); 1530 *m_head = NULL; 1531 return (ENOMEM); 1532 } 1533 *m_head = m; 1534 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, 1535 *m_head, txsegs, &nsegs, 0); 1536 if (error != 0) { 1537 m_freem(*m_head); 1538 *m_head = NULL; 1539 return (error); 1540 } 1541 } else if (error != 0) 1542 return (error); 1543 if (nsegs == 0) { 1544 m_freem(*m_head); 1545 *m_head = NULL; 1546 return (EIO); 1547 } 1548 1549 if (sc->bfe_tx_cnt + nsegs > BFE_TX_LIST_CNT - 1) { 1550 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map); 1551 return (ENOBUFS); 1552 } 1553 1554 for (i = 0; i < nsegs; i++) { 1555 d = &sc->bfe_tx_list[cur]; 1556 d->bfe_ctrl = htole32(txsegs[i].ds_len & BFE_DESC_LEN); 1557 d->bfe_ctrl |= htole32(BFE_DESC_IOC); 1558 if (cur == BFE_TX_LIST_CNT - 1) 1559 /* 1560 * Tell the chip to wrap to the start of 1561 * the descriptor list. 1562 */ 1563 d->bfe_ctrl |= htole32(BFE_DESC_EOT); 1564 /* The chip needs all addresses to be added to BFE_PCI_DMA. */ 1565 d->bfe_addr = htole32(BFE_ADDR_LO(txsegs[i].ds_addr) + 1566 BFE_PCI_DMA); 1567 BFE_INC(cur, BFE_TX_LIST_CNT); 1568 } 1569 1570 /* Update producer index. */ 1571 sc->bfe_tx_prod = cur; 1572 1573 /* Set EOF on the last descriptor. */ 1574 cur = (cur + BFE_TX_LIST_CNT - 1) % BFE_TX_LIST_CNT; 1575 d = &sc->bfe_tx_list[cur]; 1576 d->bfe_ctrl |= htole32(BFE_DESC_EOF); 1577 1578 /* Lastly set SOF on the first descriptor to avoid races. */ 1579 d = &sc->bfe_tx_list[si]; 1580 d->bfe_ctrl |= htole32(BFE_DESC_SOF); 1581 1582 r1 = &sc->bfe_tx_ring[cur]; 1583 map = r->bfe_map; 1584 r->bfe_map = r1->bfe_map; 1585 r1->bfe_map = map; 1586 r1->bfe_mbuf = *m_head; 1587 sc->bfe_tx_cnt += nsegs; 1588 1589 bus_dmamap_sync(sc->bfe_txmbuf_tag, map, BUS_DMASYNC_PREWRITE); 1590 1591 return (0); 1592 } 1593 1594 /* 1595 * Set up to transmit a packet. 1596 */ 1597 static void 1598 bfe_start(struct ifnet *ifp) 1599 { 1600 BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1601 bfe_start_locked(ifp); 1602 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1603 } 1604 1605 /* 1606 * Set up to transmit a packet. The softc is already locked. 1607 */ 1608 static void 1609 bfe_start_locked(struct ifnet *ifp) 1610 { 1611 struct bfe_softc *sc; 1612 struct mbuf *m_head; 1613 int queued; 1614 1615 sc = ifp->if_softc; 1616 1617 BFE_LOCK_ASSERT(sc); 1618 1619 /* 1620 * Not much point trying to send if the link is down 1621 * or we have nothing to send. 1622 */ 1623 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1624 IFF_DRV_RUNNING || (sc->bfe_flags & BFE_FLAG_LINK) == 0) 1625 return; 1626 1627 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1628 sc->bfe_tx_cnt < BFE_TX_LIST_CNT - 1;) { 1629 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1630 if (m_head == NULL) 1631 break; 1632 1633 /* 1634 * Pack the data into the tx ring. If we dont have 1635 * enough room, let the chip drain the ring. 1636 */ 1637 if (bfe_encap(sc, &m_head)) { 1638 if (m_head == NULL) 1639 break; 1640 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1641 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1642 break; 1643 } 1644 1645 queued++; 1646 1647 /* 1648 * If there's a BPF listener, bounce a copy of this frame 1649 * to him. 1650 */ 1651 BPF_MTAP(ifp, m_head); 1652 } 1653 1654 if (queued) { 1655 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 1656 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1657 /* Transmit - twice due to apparent hardware bug */ 1658 CSR_WRITE_4(sc, BFE_DMATX_PTR, 1659 sc->bfe_tx_prod * sizeof(struct bfe_desc)); 1660 /* 1661 * XXX It seems the following write is not necessary 1662 * to kick Tx command. What might be required would be 1663 * a way flushing PCI posted write. Reading the register 1664 * back ensures the flush operation. In addition, 1665 * hardware will execute PCI posted write in the long 1666 * run and watchdog timer for the kick command was set 1667 * to 5 seconds. Therefore I think the second write 1668 * access is not necessary or could be replaced with 1669 * read operation. 1670 */ 1671 CSR_WRITE_4(sc, BFE_DMATX_PTR, 1672 sc->bfe_tx_prod * sizeof(struct bfe_desc)); 1673 1674 /* 1675 * Set a timeout in case the chip goes out to lunch. 1676 */ 1677 sc->bfe_watchdog_timer = 5; 1678 } 1679 } 1680 1681 static void 1682 bfe_init(void *xsc) 1683 { 1684 BFE_LOCK((struct bfe_softc *)xsc); 1685 bfe_init_locked(xsc); 1686 BFE_UNLOCK((struct bfe_softc *)xsc); 1687 } 1688 1689 static void 1690 bfe_init_locked(void *xsc) 1691 { 1692 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1693 struct ifnet *ifp = sc->bfe_ifp; 1694 struct mii_data *mii; 1695 1696 BFE_LOCK_ASSERT(sc); 1697 1698 mii = device_get_softc(sc->bfe_miibus); 1699 1700 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1701 return; 1702 1703 bfe_stop(sc); 1704 bfe_chip_reset(sc); 1705 1706 if (bfe_list_rx_init(sc) == ENOBUFS) { 1707 device_printf(sc->bfe_dev, 1708 "%s: Not enough memory for list buffers\n", __func__); 1709 bfe_stop(sc); 1710 return; 1711 } 1712 bfe_list_tx_init(sc); 1713 1714 bfe_set_rx_mode(sc); 1715 1716 /* Enable the chip and core */ 1717 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1718 /* Enable interrupts */ 1719 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1720 1721 /* Clear link state and change media. */ 1722 sc->bfe_flags &= ~BFE_FLAG_LINK; 1723 mii_mediachg(mii); 1724 1725 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1726 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1727 1728 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1729 } 1730 1731 /* 1732 * Set media options. 1733 */ 1734 static int 1735 bfe_ifmedia_upd(struct ifnet *ifp) 1736 { 1737 struct bfe_softc *sc; 1738 struct mii_data *mii; 1739 struct mii_softc *miisc; 1740 int error; 1741 1742 sc = ifp->if_softc; 1743 BFE_LOCK(sc); 1744 1745 mii = device_get_softc(sc->bfe_miibus); 1746 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1747 PHY_RESET(miisc); 1748 error = mii_mediachg(mii); 1749 BFE_UNLOCK(sc); 1750 1751 return (error); 1752 } 1753 1754 /* 1755 * Report current media status. 1756 */ 1757 static void 1758 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1759 { 1760 struct bfe_softc *sc = ifp->if_softc; 1761 struct mii_data *mii; 1762 1763 BFE_LOCK(sc); 1764 mii = device_get_softc(sc->bfe_miibus); 1765 mii_pollstat(mii); 1766 ifmr->ifm_active = mii->mii_media_active; 1767 ifmr->ifm_status = mii->mii_media_status; 1768 BFE_UNLOCK(sc); 1769 } 1770 1771 static int 1772 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1773 { 1774 struct bfe_softc *sc = ifp->if_softc; 1775 struct ifreq *ifr = (struct ifreq *) data; 1776 struct mii_data *mii; 1777 int error = 0; 1778 1779 switch (command) { 1780 case SIOCSIFFLAGS: 1781 BFE_LOCK(sc); 1782 if (ifp->if_flags & IFF_UP) { 1783 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1784 bfe_set_rx_mode(sc); 1785 else if ((sc->bfe_flags & BFE_FLAG_DETACH) == 0) 1786 bfe_init_locked(sc); 1787 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1788 bfe_stop(sc); 1789 BFE_UNLOCK(sc); 1790 break; 1791 case SIOCADDMULTI: 1792 case SIOCDELMULTI: 1793 BFE_LOCK(sc); 1794 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1795 bfe_set_rx_mode(sc); 1796 BFE_UNLOCK(sc); 1797 break; 1798 case SIOCGIFMEDIA: 1799 case SIOCSIFMEDIA: 1800 mii = device_get_softc(sc->bfe_miibus); 1801 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1802 break; 1803 default: 1804 error = ether_ioctl(ifp, command, data); 1805 break; 1806 } 1807 1808 return (error); 1809 } 1810 1811 static void 1812 bfe_watchdog(struct bfe_softc *sc) 1813 { 1814 struct ifnet *ifp; 1815 1816 BFE_LOCK_ASSERT(sc); 1817 1818 if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer) 1819 return; 1820 1821 ifp = sc->bfe_ifp; 1822 1823 device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n"); 1824 1825 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1826 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1827 bfe_init_locked(sc); 1828 1829 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1830 bfe_start_locked(ifp); 1831 } 1832 1833 static void 1834 bfe_tick(void *xsc) 1835 { 1836 struct bfe_softc *sc = xsc; 1837 struct mii_data *mii; 1838 1839 BFE_LOCK_ASSERT(sc); 1840 1841 mii = device_get_softc(sc->bfe_miibus); 1842 mii_tick(mii); 1843 bfe_stats_update(sc); 1844 bfe_watchdog(sc); 1845 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1846 } 1847 1848 /* 1849 * Stop the adapter and free any mbufs allocated to the 1850 * RX and TX lists. 1851 */ 1852 static void 1853 bfe_stop(struct bfe_softc *sc) 1854 { 1855 struct ifnet *ifp; 1856 1857 BFE_LOCK_ASSERT(sc); 1858 1859 ifp = sc->bfe_ifp; 1860 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1861 sc->bfe_flags &= ~BFE_FLAG_LINK; 1862 callout_stop(&sc->bfe_stat_co); 1863 sc->bfe_watchdog_timer = 0; 1864 1865 bfe_chip_halt(sc); 1866 bfe_tx_ring_free(sc); 1867 bfe_rx_ring_free(sc); 1868 } 1869 1870 static int 1871 sysctl_bfe_stats(SYSCTL_HANDLER_ARGS) 1872 { 1873 struct bfe_softc *sc; 1874 struct bfe_hw_stats *stats; 1875 int error, result; 1876 1877 result = -1; 1878 error = sysctl_handle_int(oidp, &result, 0, req); 1879 1880 if (error != 0 || req->newptr == NULL) 1881 return (error); 1882 1883 if (result != 1) 1884 return (error); 1885 1886 sc = (struct bfe_softc *)arg1; 1887 stats = &sc->bfe_stats; 1888 1889 printf("%s statistics:\n", device_get_nameunit(sc->bfe_dev)); 1890 printf("Transmit good octets : %ju\n", 1891 (uintmax_t)stats->tx_good_octets); 1892 printf("Transmit good frames : %ju\n", 1893 (uintmax_t)stats->tx_good_frames); 1894 printf("Transmit octets : %ju\n", 1895 (uintmax_t)stats->tx_octets); 1896 printf("Transmit frames : %ju\n", 1897 (uintmax_t)stats->tx_frames); 1898 printf("Transmit broadcast frames : %ju\n", 1899 (uintmax_t)stats->tx_bcast_frames); 1900 printf("Transmit multicast frames : %ju\n", 1901 (uintmax_t)stats->tx_mcast_frames); 1902 printf("Transmit frames 64 bytes : %ju\n", 1903 (uint64_t)stats->tx_pkts_64); 1904 printf("Transmit frames 65 to 127 bytes : %ju\n", 1905 (uint64_t)stats->tx_pkts_65_127); 1906 printf("Transmit frames 128 to 255 bytes : %ju\n", 1907 (uint64_t)stats->tx_pkts_128_255); 1908 printf("Transmit frames 256 to 511 bytes : %ju\n", 1909 (uint64_t)stats->tx_pkts_256_511); 1910 printf("Transmit frames 512 to 1023 bytes : %ju\n", 1911 (uint64_t)stats->tx_pkts_512_1023); 1912 printf("Transmit frames 1024 to max bytes : %ju\n", 1913 (uint64_t)stats->tx_pkts_1024_max); 1914 printf("Transmit jabber errors : %u\n", stats->tx_jabbers); 1915 printf("Transmit oversized frames : %ju\n", 1916 (uint64_t)stats->tx_oversize_frames); 1917 printf("Transmit fragmented frames : %ju\n", 1918 (uint64_t)stats->tx_frag_frames); 1919 printf("Transmit underruns : %u\n", stats->tx_colls); 1920 printf("Transmit total collisions : %u\n", stats->tx_single_colls); 1921 printf("Transmit single collisions : %u\n", stats->tx_single_colls); 1922 printf("Transmit multiple collisions : %u\n", stats->tx_multi_colls); 1923 printf("Transmit excess collisions : %u\n", stats->tx_excess_colls); 1924 printf("Transmit late collisions : %u\n", stats->tx_late_colls); 1925 printf("Transmit deferrals : %u\n", stats->tx_deferrals); 1926 printf("Transmit carrier losts : %u\n", stats->tx_carrier_losts); 1927 printf("Transmit pause frames : %u\n", stats->tx_pause_frames); 1928 1929 printf("Receive good octets : %ju\n", 1930 (uintmax_t)stats->rx_good_octets); 1931 printf("Receive good frames : %ju\n", 1932 (uintmax_t)stats->rx_good_frames); 1933 printf("Receive octets : %ju\n", 1934 (uintmax_t)stats->rx_octets); 1935 printf("Receive frames : %ju\n", 1936 (uintmax_t)stats->rx_frames); 1937 printf("Receive broadcast frames : %ju\n", 1938 (uintmax_t)stats->rx_bcast_frames); 1939 printf("Receive multicast frames : %ju\n", 1940 (uintmax_t)stats->rx_mcast_frames); 1941 printf("Receive frames 64 bytes : %ju\n", 1942 (uint64_t)stats->rx_pkts_64); 1943 printf("Receive frames 65 to 127 bytes : %ju\n", 1944 (uint64_t)stats->rx_pkts_65_127); 1945 printf("Receive frames 128 to 255 bytes : %ju\n", 1946 (uint64_t)stats->rx_pkts_128_255); 1947 printf("Receive frames 256 to 511 bytes : %ju\n", 1948 (uint64_t)stats->rx_pkts_256_511); 1949 printf("Receive frames 512 to 1023 bytes : %ju\n", 1950 (uint64_t)stats->rx_pkts_512_1023); 1951 printf("Receive frames 1024 to max bytes : %ju\n", 1952 (uint64_t)stats->rx_pkts_1024_max); 1953 printf("Receive jabber errors : %u\n", stats->rx_jabbers); 1954 printf("Receive oversized frames : %ju\n", 1955 (uint64_t)stats->rx_oversize_frames); 1956 printf("Receive fragmented frames : %ju\n", 1957 (uint64_t)stats->rx_frag_frames); 1958 printf("Receive missed frames : %u\n", stats->rx_missed_frames); 1959 printf("Receive CRC align errors : %u\n", stats->rx_crc_align_errs); 1960 printf("Receive undersized frames : %u\n", stats->rx_runts); 1961 printf("Receive CRC errors : %u\n", stats->rx_crc_errs); 1962 printf("Receive align errors : %u\n", stats->rx_align_errs); 1963 printf("Receive symbol errors : %u\n", stats->rx_symbol_errs); 1964 printf("Receive pause frames : %u\n", stats->rx_pause_frames); 1965 printf("Receive control frames : %u\n", stats->rx_control_frames); 1966 1967 return (error); 1968 }
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