The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/bge/if_bge.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-4-Clause
    3  *
    4  * Copyright (c) 2001 Wind River Systems
    5  * Copyright (c) 1997, 1998, 1999, 2001
    6  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. All advertising materials mentioning features or use of this software
   17  *    must display the following acknowledgement:
   18  *      This product includes software developed by Bill Paul.
   19  * 4. Neither the name of the author nor the names of any co-contributors
   20  *    may be used to endorse or promote products derived from this software
   21  *    without specific prior written permission.
   22  *
   23  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   26  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   27  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   31  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   33  * THE POSSIBILITY OF SUCH DAMAGE.
   34  */
   35 
   36 #include <sys/cdefs.h>
   37 __FBSDID("$FreeBSD: head/sys/dev/bge/if_bge.c 338948 2018-09-26 17:12:14Z imp $");
   38 
   39 /*
   40  * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver
   41  *
   42  * The Broadcom BCM5700 is based on technology originally developed by
   43  * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet
   44  * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
   45  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
   46  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
   47  * frames, highly configurable RX filtering, and 16 RX and TX queues
   48  * (which, along with RX filter rules, can be used for QOS applications).
   49  * Other features, such as TCP segmentation, may be available as part
   50  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
   51  * firmware images can be stored in hardware and need not be compiled
   52  * into the driver.
   53  *
   54  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
   55  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
   56  *
   57  * The BCM5701 is a single-chip solution incorporating both the BCM5700
   58  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
   59  * does not support external SSRAM.
   60  *
   61  * Broadcom also produces a variation of the BCM5700 under the "Altima"
   62  * brand name, which is functionally similar but lacks PCI-X support.
   63  *
   64  * Without external SSRAM, you can only have at most 4 TX rings,
   65  * and the use of the mini RX ring is disabled. This seems to imply
   66  * that these features are simply not available on the BCM5701. As a
   67  * result, this driver does not implement any support for the mini RX
   68  * ring.
   69  */
   70 
   71 #ifdef HAVE_KERNEL_OPTION_HEADERS
   72 #include "opt_device_polling.h"
   73 #endif
   74 
   75 #include <sys/param.h>
   76 #include <sys/endian.h>
   77 #include <sys/systm.h>
   78 #include <sys/sockio.h>
   79 #include <sys/mbuf.h>
   80 #include <sys/malloc.h>
   81 #include <sys/kernel.h>
   82 #include <sys/module.h>
   83 #include <sys/socket.h>
   84 #include <sys/sysctl.h>
   85 #include <sys/taskqueue.h>
   86 
   87 #include <net/if.h>
   88 #include <net/if_var.h>
   89 #include <net/if_arp.h>
   90 #include <net/ethernet.h>
   91 #include <net/if_dl.h>
   92 #include <net/if_media.h>
   93 
   94 #include <net/bpf.h>
   95 
   96 #include <net/if_types.h>
   97 #include <net/if_vlan_var.h>
   98 
   99 #include <netinet/in_systm.h>
  100 #include <netinet/in.h>
  101 #include <netinet/ip.h>
  102 #include <netinet/tcp.h>
  103 #include <netinet/netdump/netdump.h>
  104 
  105 #include <machine/bus.h>
  106 #include <machine/resource.h>
  107 #include <sys/bus.h>
  108 #include <sys/rman.h>
  109 
  110 #include <dev/mii/mii.h>
  111 #include <dev/mii/miivar.h>
  112 #include "miidevs.h"
  113 #include <dev/mii/brgphyreg.h>
  114 
  115 #ifdef __sparc64__
  116 #include <dev/ofw/ofw_bus.h>
  117 #include <dev/ofw/openfirm.h>
  118 #include <machine/ofw_machdep.h>
  119 #include <machine/ver.h>
  120 #endif
  121 
  122 #include <dev/pci/pcireg.h>
  123 #include <dev/pci/pcivar.h>
  124 
  125 #include <dev/bge/if_bgereg.h>
  126 
  127 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP)
  128 #define ETHER_MIN_NOPAD         (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
  129 
  130 MODULE_DEPEND(bge, pci, 1, 1, 1);
  131 MODULE_DEPEND(bge, ether, 1, 1, 1);
  132 MODULE_DEPEND(bge, miibus, 1, 1, 1);
  133 
  134 /* "device miibus" required.  See GENERIC if you get errors here. */
  135 #include "miibus_if.h"
  136 
  137 /*
  138  * Various supported device vendors/types and their names. Note: the
  139  * spec seems to indicate that the hardware still has Alteon's vendor
  140  * ID burned into it, though it will always be overriden by the vendor
  141  * ID in the EEPROM. Just to be safe, we cover all possibilities.
  142  */
  143 static const struct bge_type {
  144         uint16_t        bge_vid;
  145         uint16_t        bge_did;
  146 } bge_devs[] = {
  147         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5700 },
  148         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5701 },
  149 
  150         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1000 },
  151         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1002 },
  152         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC9100 },
  153 
  154         { APPLE_VENDORID,       APPLE_DEVICE_BCM5701 },
  155 
  156         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5700 },
  157         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5701 },
  158         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702 },
  159         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702_ALT },
  160         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702X },
  161         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703 },
  162         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703_ALT },
  163         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703X },
  164         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704C },
  165         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S },
  166         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S_ALT },
  167         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705 },
  168         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705F },
  169         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705K },
  170         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M },
  171         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M_ALT },
  172         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714C },
  173         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714S },
  174         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715 },
  175         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715S },
  176         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5717 },
  177         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5717C },
  178         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5718 },
  179         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5719 },
  180         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5720 },
  181         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5721 },
  182         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5722 },
  183         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5723 },
  184         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5725 },
  185         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5727 },
  186         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750 },
  187         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750M },
  188         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751 },
  189         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751F },
  190         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751M },
  191         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752 },
  192         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752M },
  193         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753 },
  194         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753F },
  195         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753M },
  196         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754 },
  197         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754M },
  198         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755 },
  199         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755M },
  200         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5756 },
  201         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761 },
  202         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761E },
  203         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761S },
  204         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761SE },
  205         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5762 },
  206         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5764 },
  207         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780 },
  208         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780S },
  209         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5781 },
  210         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5782 },
  211         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5784 },
  212         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785F },
  213         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785G },
  214         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5786 },
  215         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787 },
  216         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787F },
  217         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787M },
  218         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5788 },
  219         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5789 },
  220         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901 },
  221         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901A2 },
  222         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5903M },
  223         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906 },
  224         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906M },
  225         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57760 },
  226         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57761 },
  227         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57762 },
  228         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57764 },
  229         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57765 },
  230         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57766 },
  231         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57767 },
  232         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57780 },
  233         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57781 },
  234         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57782 },
  235         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57785 },
  236         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57786 },
  237         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57787 },
  238         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57788 },
  239         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57790 },
  240         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57791 },
  241         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57795 },
  242 
  243         { SK_VENDORID,          SK_DEVICEID_ALTIMA },
  244 
  245         { TC_VENDORID,          TC_DEVICEID_3C996 },
  246 
  247         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE4 },
  248         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE5 },
  249         { FJTSU_VENDORID,       FJTSU_DEVICEID_PP250450 },
  250 
  251         { 0, 0 }
  252 };
  253 
  254 static const struct bge_vendor {
  255         uint16_t        v_id;
  256         const char      *v_name;
  257 } bge_vendors[] = {
  258         { ALTEON_VENDORID,      "Alteon" },
  259         { ALTIMA_VENDORID,      "Altima" },
  260         { APPLE_VENDORID,       "Apple" },
  261         { BCOM_VENDORID,        "Broadcom" },
  262         { SK_VENDORID,          "SysKonnect" },
  263         { TC_VENDORID,          "3Com" },
  264         { FJTSU_VENDORID,       "Fujitsu" },
  265 
  266         { 0, NULL }
  267 };
  268 
  269 static const struct bge_revision {
  270         uint32_t        br_chipid;
  271         const char      *br_name;
  272 } bge_revisions[] = {
  273         { BGE_CHIPID_BCM5700_A0,        "BCM5700 A0" },
  274         { BGE_CHIPID_BCM5700_A1,        "BCM5700 A1" },
  275         { BGE_CHIPID_BCM5700_B0,        "BCM5700 B0" },
  276         { BGE_CHIPID_BCM5700_B1,        "BCM5700 B1" },
  277         { BGE_CHIPID_BCM5700_B2,        "BCM5700 B2" },
  278         { BGE_CHIPID_BCM5700_B3,        "BCM5700 B3" },
  279         { BGE_CHIPID_BCM5700_ALTIMA,    "BCM5700 Altima" },
  280         { BGE_CHIPID_BCM5700_C0,        "BCM5700 C0" },
  281         { BGE_CHIPID_BCM5701_A0,        "BCM5701 A0" },
  282         { BGE_CHIPID_BCM5701_B0,        "BCM5701 B0" },
  283         { BGE_CHIPID_BCM5701_B2,        "BCM5701 B2" },
  284         { BGE_CHIPID_BCM5701_B5,        "BCM5701 B5" },
  285         { BGE_CHIPID_BCM5703_A0,        "BCM5703 A0" },
  286         { BGE_CHIPID_BCM5703_A1,        "BCM5703 A1" },
  287         { BGE_CHIPID_BCM5703_A2,        "BCM5703 A2" },
  288         { BGE_CHIPID_BCM5703_A3,        "BCM5703 A3" },
  289         { BGE_CHIPID_BCM5703_B0,        "BCM5703 B0" },
  290         { BGE_CHIPID_BCM5704_A0,        "BCM5704 A0" },
  291         { BGE_CHIPID_BCM5704_A1,        "BCM5704 A1" },
  292         { BGE_CHIPID_BCM5704_A2,        "BCM5704 A2" },
  293         { BGE_CHIPID_BCM5704_A3,        "BCM5704 A3" },
  294         { BGE_CHIPID_BCM5704_B0,        "BCM5704 B0" },
  295         { BGE_CHIPID_BCM5705_A0,        "BCM5705 A0" },
  296         { BGE_CHIPID_BCM5705_A1,        "BCM5705 A1" },
  297         { BGE_CHIPID_BCM5705_A2,        "BCM5705 A2" },
  298         { BGE_CHIPID_BCM5705_A3,        "BCM5705 A3" },
  299         { BGE_CHIPID_BCM5750_A0,        "BCM5750 A0" },
  300         { BGE_CHIPID_BCM5750_A1,        "BCM5750 A1" },
  301         { BGE_CHIPID_BCM5750_A3,        "BCM5750 A3" },
  302         { BGE_CHIPID_BCM5750_B0,        "BCM5750 B0" },
  303         { BGE_CHIPID_BCM5750_B1,        "BCM5750 B1" },
  304         { BGE_CHIPID_BCM5750_C0,        "BCM5750 C0" },
  305         { BGE_CHIPID_BCM5750_C1,        "BCM5750 C1" },
  306         { BGE_CHIPID_BCM5750_C2,        "BCM5750 C2" },
  307         { BGE_CHIPID_BCM5714_A0,        "BCM5714 A0" },
  308         { BGE_CHIPID_BCM5752_A0,        "BCM5752 A0" },
  309         { BGE_CHIPID_BCM5752_A1,        "BCM5752 A1" },
  310         { BGE_CHIPID_BCM5752_A2,        "BCM5752 A2" },
  311         { BGE_CHIPID_BCM5714_B0,        "BCM5714 B0" },
  312         { BGE_CHIPID_BCM5714_B3,        "BCM5714 B3" },
  313         { BGE_CHIPID_BCM5715_A0,        "BCM5715 A0" },
  314         { BGE_CHIPID_BCM5715_A1,        "BCM5715 A1" },
  315         { BGE_CHIPID_BCM5715_A3,        "BCM5715 A3" },
  316         { BGE_CHIPID_BCM5717_A0,        "BCM5717 A0" },
  317         { BGE_CHIPID_BCM5717_B0,        "BCM5717 B0" },
  318         { BGE_CHIPID_BCM5717_C0,        "BCM5717 C0" },
  319         { BGE_CHIPID_BCM5719_A0,        "BCM5719 A0" },
  320         { BGE_CHIPID_BCM5720_A0,        "BCM5720 A0" },
  321         { BGE_CHIPID_BCM5755_A0,        "BCM5755 A0" },
  322         { BGE_CHIPID_BCM5755_A1,        "BCM5755 A1" },
  323         { BGE_CHIPID_BCM5755_A2,        "BCM5755 A2" },
  324         { BGE_CHIPID_BCM5722_A0,        "BCM5722 A0" },
  325         { BGE_CHIPID_BCM5761_A0,        "BCM5761 A0" },
  326         { BGE_CHIPID_BCM5761_A1,        "BCM5761 A1" },
  327         { BGE_CHIPID_BCM5762_A0,        "BCM5762 A0" },
  328         { BGE_CHIPID_BCM5784_A0,        "BCM5784 A0" },
  329         { BGE_CHIPID_BCM5784_A1,        "BCM5784 A1" },
  330         /* 5754 and 5787 share the same ASIC ID */
  331         { BGE_CHIPID_BCM5787_A0,        "BCM5754/5787 A0" },
  332         { BGE_CHIPID_BCM5787_A1,        "BCM5754/5787 A1" },
  333         { BGE_CHIPID_BCM5787_A2,        "BCM5754/5787 A2" },
  334         { BGE_CHIPID_BCM5906_A1,        "BCM5906 A1" },
  335         { BGE_CHIPID_BCM5906_A2,        "BCM5906 A2" },
  336         { BGE_CHIPID_BCM57765_A0,       "BCM57765 A0" },
  337         { BGE_CHIPID_BCM57765_B0,       "BCM57765 B0" },
  338         { BGE_CHIPID_BCM57780_A0,       "BCM57780 A0" },
  339         { BGE_CHIPID_BCM57780_A1,       "BCM57780 A1" },
  340 
  341         { 0, NULL }
  342 };
  343 
  344 /*
  345  * Some defaults for major revisions, so that newer steppings
  346  * that we don't know about have a shot at working.
  347  */
  348 static const struct bge_revision bge_majorrevs[] = {
  349         { BGE_ASICREV_BCM5700,          "unknown BCM5700" },
  350         { BGE_ASICREV_BCM5701,          "unknown BCM5701" },
  351         { BGE_ASICREV_BCM5703,          "unknown BCM5703" },
  352         { BGE_ASICREV_BCM5704,          "unknown BCM5704" },
  353         { BGE_ASICREV_BCM5705,          "unknown BCM5705" },
  354         { BGE_ASICREV_BCM5750,          "unknown BCM5750" },
  355         { BGE_ASICREV_BCM5714_A0,       "unknown BCM5714" },
  356         { BGE_ASICREV_BCM5752,          "unknown BCM5752" },
  357         { BGE_ASICREV_BCM5780,          "unknown BCM5780" },
  358         { BGE_ASICREV_BCM5714,          "unknown BCM5714" },
  359         { BGE_ASICREV_BCM5755,          "unknown BCM5755" },
  360         { BGE_ASICREV_BCM5761,          "unknown BCM5761" },
  361         { BGE_ASICREV_BCM5784,          "unknown BCM5784" },
  362         { BGE_ASICREV_BCM5785,          "unknown BCM5785" },
  363         /* 5754 and 5787 share the same ASIC ID */
  364         { BGE_ASICREV_BCM5787,          "unknown BCM5754/5787" },
  365         { BGE_ASICREV_BCM5906,          "unknown BCM5906" },
  366         { BGE_ASICREV_BCM57765,         "unknown BCM57765" },
  367         { BGE_ASICREV_BCM57766,         "unknown BCM57766" },
  368         { BGE_ASICREV_BCM57780,         "unknown BCM57780" },
  369         { BGE_ASICREV_BCM5717,          "unknown BCM5717" },
  370         { BGE_ASICREV_BCM5719,          "unknown BCM5719" },
  371         { BGE_ASICREV_BCM5720,          "unknown BCM5720" },
  372         { BGE_ASICREV_BCM5762,          "unknown BCM5762" },
  373 
  374         { 0, NULL }
  375 };
  376 
  377 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
  378 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
  379 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
  380 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
  381 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
  382 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
  383 #define BGE_IS_5717_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5717_PLUS)
  384 #define BGE_IS_57765_PLUS(sc)           ((sc)->bge_flags & BGE_FLAG_57765_PLUS)
  385 
  386 static uint32_t bge_chipid(device_t);
  387 static const struct bge_vendor * bge_lookup_vendor(uint16_t);
  388 static const struct bge_revision * bge_lookup_rev(uint32_t);
  389 
  390 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
  391 
  392 static int bge_probe(device_t);
  393 static int bge_attach(device_t);
  394 static int bge_detach(device_t);
  395 static int bge_suspend(device_t);
  396 static int bge_resume(device_t);
  397 static void bge_release_resources(struct bge_softc *);
  398 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
  399 static int bge_dma_alloc(struct bge_softc *);
  400 static void bge_dma_free(struct bge_softc *);
  401 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t,
  402     bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
  403 
  404 static void bge_devinfo(struct bge_softc *);
  405 static int bge_mbox_reorder(struct bge_softc *);
  406 
  407 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
  408 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
  409 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
  410 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
  411 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
  412 
  413 static void bge_txeof(struct bge_softc *, uint16_t);
  414 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
  415 static int bge_rxeof(struct bge_softc *, uint16_t, int);
  416 
  417 static void bge_asf_driver_up (struct bge_softc *);
  418 static void bge_tick(void *);
  419 static void bge_stats_clear_regs(struct bge_softc *);
  420 static void bge_stats_update(struct bge_softc *);
  421 static void bge_stats_update_regs(struct bge_softc *);
  422 static struct mbuf *bge_check_short_dma(struct mbuf *);
  423 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
  424     uint16_t *, uint16_t *);
  425 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
  426 
  427 static void bge_intr(void *);
  428 static int bge_msi_intr(void *);
  429 static void bge_intr_task(void *, int);
  430 static void bge_start(if_t);
  431 static void bge_start_locked(if_t);
  432 static void bge_start_tx(struct bge_softc *, uint32_t);
  433 static int bge_ioctl(if_t, u_long, caddr_t);
  434 static void bge_init_locked(struct bge_softc *);
  435 static void bge_init(void *);
  436 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
  437 static void bge_stop(struct bge_softc *);
  438 static void bge_watchdog(struct bge_softc *);
  439 static int bge_shutdown(device_t);
  440 static int bge_ifmedia_upd_locked(if_t);
  441 static int bge_ifmedia_upd(if_t);
  442 static void bge_ifmedia_sts(if_t, struct ifmediareq *);
  443 static uint64_t bge_get_counter(if_t, ift_counter);
  444 
  445 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
  446 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
  447 
  448 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
  449 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
  450 
  451 static void bge_setpromisc(struct bge_softc *);
  452 static void bge_setmulti(struct bge_softc *);
  453 static void bge_setvlan(struct bge_softc *);
  454 
  455 static __inline void bge_rxreuse_std(struct bge_softc *, int);
  456 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int);
  457 static int bge_newbuf_std(struct bge_softc *, int);
  458 static int bge_newbuf_jumbo(struct bge_softc *, int);
  459 static int bge_init_rx_ring_std(struct bge_softc *);
  460 static void bge_free_rx_ring_std(struct bge_softc *);
  461 static int bge_init_rx_ring_jumbo(struct bge_softc *);
  462 static void bge_free_rx_ring_jumbo(struct bge_softc *);
  463 static void bge_free_tx_ring(struct bge_softc *);
  464 static int bge_init_tx_ring(struct bge_softc *);
  465 
  466 static int bge_chipinit(struct bge_softc *);
  467 static int bge_blockinit(struct bge_softc *);
  468 static uint32_t bge_dma_swap_options(struct bge_softc *);
  469 
  470 static int bge_has_eaddr(struct bge_softc *);
  471 static uint32_t bge_readmem_ind(struct bge_softc *, int);
  472 static void bge_writemem_ind(struct bge_softc *, int, int);
  473 static void bge_writembx(struct bge_softc *, int, int);
  474 #ifdef notdef
  475 static uint32_t bge_readreg_ind(struct bge_softc *, int);
  476 #endif
  477 static void bge_writemem_direct(struct bge_softc *, int, int);
  478 static void bge_writereg_ind(struct bge_softc *, int, int);
  479 
  480 static int bge_miibus_readreg(device_t, int, int);
  481 static int bge_miibus_writereg(device_t, int, int, int);
  482 static void bge_miibus_statchg(device_t);
  483 #ifdef DEVICE_POLLING
  484 static int bge_poll(if_t ifp, enum poll_cmd cmd, int count);
  485 #endif
  486 
  487 #define BGE_RESET_SHUTDOWN      0
  488 #define BGE_RESET_START         1
  489 #define BGE_RESET_SUSPEND       2
  490 static void bge_sig_post_reset(struct bge_softc *, int);
  491 static void bge_sig_legacy(struct bge_softc *, int);
  492 static void bge_sig_pre_reset(struct bge_softc *, int);
  493 static void bge_stop_fw(struct bge_softc *);
  494 static int bge_reset(struct bge_softc *);
  495 static void bge_link_upd(struct bge_softc *);
  496 
  497 static void bge_ape_lock_init(struct bge_softc *);
  498 static void bge_ape_read_fw_ver(struct bge_softc *);
  499 static int bge_ape_lock(struct bge_softc *, int);
  500 static void bge_ape_unlock(struct bge_softc *, int);
  501 static void bge_ape_send_event(struct bge_softc *, uint32_t);
  502 static void bge_ape_driver_state_change(struct bge_softc *, int);
  503 
  504 /*
  505  * The BGE_REGISTER_DEBUG option is only for low-level debugging.  It may
  506  * leak information to untrusted users.  It is also known to cause alignment
  507  * traps on certain architectures.
  508  */
  509 #ifdef BGE_REGISTER_DEBUG
  510 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
  511 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
  512 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS);
  513 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
  514 #endif
  515 static void bge_add_sysctls(struct bge_softc *);
  516 static void bge_add_sysctl_stats_regs(struct bge_softc *,
  517     struct sysctl_ctx_list *, struct sysctl_oid_list *);
  518 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *,
  519     struct sysctl_oid_list *);
  520 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
  521 
  522 NETDUMP_DEFINE(bge);
  523 
  524 static device_method_t bge_methods[] = {
  525         /* Device interface */
  526         DEVMETHOD(device_probe,         bge_probe),
  527         DEVMETHOD(device_attach,        bge_attach),
  528         DEVMETHOD(device_detach,        bge_detach),
  529         DEVMETHOD(device_shutdown,      bge_shutdown),
  530         DEVMETHOD(device_suspend,       bge_suspend),
  531         DEVMETHOD(device_resume,        bge_resume),
  532 
  533         /* MII interface */
  534         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
  535         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
  536         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
  537 
  538         DEVMETHOD_END
  539 };
  540 
  541 static driver_t bge_driver = {
  542         "bge",
  543         bge_methods,
  544         sizeof(struct bge_softc)
  545 };
  546 
  547 static devclass_t bge_devclass;
  548 
  549 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
  550 MODULE_PNP_INFO("U16:vendor;U16:device", pci, bge, bge_devs,
  551     nitems(bge_devs) - 1);
  552 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
  553 
  554 static int bge_allow_asf = 1;
  555 
  556 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
  557 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RDTUN, &bge_allow_asf, 0,
  558         "Allow ASF mode if available");
  559 
  560 #define SPARC64_BLADE_1500_MODEL        "SUNW,Sun-Blade-1500"
  561 #define SPARC64_BLADE_1500_PATH_BGE     "/pci@1f,700000/network@2"
  562 #define SPARC64_BLADE_2500_MODEL        "SUNW,Sun-Blade-2500"
  563 #define SPARC64_BLADE_2500_PATH_BGE     "/pci@1c,600000/network@3"
  564 #define SPARC64_OFW_SUBVENDOR           "subsystem-vendor-id"
  565 
  566 static int
  567 bge_has_eaddr(struct bge_softc *sc)
  568 {
  569 #ifdef __sparc64__
  570         char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
  571         device_t dev;
  572         uint32_t subvendor;
  573 
  574         dev = sc->bge_dev;
  575 
  576         /*
  577          * The on-board BGEs found in sun4u machines aren't fitted with
  578          * an EEPROM which means that we have to obtain the MAC address
  579          * via OFW and that some tests will always fail.  We distinguish
  580          * such BGEs by the subvendor ID, which also has to be obtained
  581          * from OFW instead of the PCI configuration space as the latter
  582          * indicates Broadcom as the subvendor of the netboot interface.
  583          * For early Blade 1500 and 2500 we even have to check the OFW
  584          * device path as the subvendor ID always defaults to Broadcom
  585          * there.
  586          */
  587         if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
  588             &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
  589             (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID))
  590                 return (0);
  591         memset(buf, 0, sizeof(buf));
  592         if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
  593                 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
  594                     strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
  595                         return (0);
  596                 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
  597                     strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
  598                         return (0);
  599         }
  600 #endif
  601         return (1);
  602 }
  603 
  604 static uint32_t
  605 bge_readmem_ind(struct bge_softc *sc, int off)
  606 {
  607         device_t dev;
  608         uint32_t val;
  609 
  610         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
  611             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
  612                 return (0);
  613 
  614         dev = sc->bge_dev;
  615 
  616         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
  617         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
  618         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
  619         return (val);
  620 }
  621 
  622 static void
  623 bge_writemem_ind(struct bge_softc *sc, int off, int val)
  624 {
  625         device_t dev;
  626 
  627         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
  628             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
  629                 return;
  630 
  631         dev = sc->bge_dev;
  632 
  633         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
  634         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
  635         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
  636 }
  637 
  638 #ifdef notdef
  639 static uint32_t
  640 bge_readreg_ind(struct bge_softc *sc, int off)
  641 {
  642         device_t dev;
  643 
  644         dev = sc->bge_dev;
  645 
  646         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
  647         return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
  648 }
  649 #endif
  650 
  651 static void
  652 bge_writereg_ind(struct bge_softc *sc, int off, int val)
  653 {
  654         device_t dev;
  655 
  656         dev = sc->bge_dev;
  657 
  658         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
  659         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
  660 }
  661 
  662 static void
  663 bge_writemem_direct(struct bge_softc *sc, int off, int val)
  664 {
  665         CSR_WRITE_4(sc, off, val);
  666 }
  667 
  668 static void
  669 bge_writembx(struct bge_softc *sc, int off, int val)
  670 {
  671         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
  672                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
  673 
  674         CSR_WRITE_4(sc, off, val);
  675         if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0)
  676                 CSR_READ_4(sc, off);
  677 }
  678 
  679 /*
  680  * Clear all stale locks and select the lock for this driver instance.
  681  */
  682 static void
  683 bge_ape_lock_init(struct bge_softc *sc)
  684 {
  685         uint32_t bit, regbase;
  686         int i;
  687 
  688         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
  689                 regbase = BGE_APE_LOCK_GRANT;
  690         else
  691                 regbase = BGE_APE_PER_LOCK_GRANT;
  692 
  693         /* Clear any stale locks. */
  694         for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) {
  695                 switch (i) {
  696                 case BGE_APE_LOCK_PHY0:
  697                 case BGE_APE_LOCK_PHY1:
  698                 case BGE_APE_LOCK_PHY2:
  699                 case BGE_APE_LOCK_PHY3:
  700                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
  701                         break;
  702                 default:
  703                         if (sc->bge_func_addr == 0)
  704                                 bit = BGE_APE_LOCK_GRANT_DRIVER0;
  705                         else
  706                                 bit = (1 << sc->bge_func_addr);
  707                 }
  708                 APE_WRITE_4(sc, regbase + 4 * i, bit);
  709         }
  710 
  711         /* Select the PHY lock based on the device's function number. */
  712         switch (sc->bge_func_addr) {
  713         case 0:
  714                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0;
  715                 break;
  716         case 1:
  717                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1;
  718                 break;
  719         case 2:
  720                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2;
  721                 break;
  722         case 3:
  723                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3;
  724                 break;
  725         default:
  726                 device_printf(sc->bge_dev,
  727                     "PHY lock not supported on this function\n");
  728         }
  729 }
  730 
  731 /*
  732  * Check for APE firmware, set flags, and print version info.
  733  */
  734 static void
  735 bge_ape_read_fw_ver(struct bge_softc *sc)
  736 {
  737         const char *fwtype;
  738         uint32_t apedata, features;
  739 
  740         /* Check for a valid APE signature in shared memory. */
  741         apedata = APE_READ_4(sc, BGE_APE_SEG_SIG);
  742         if (apedata != BGE_APE_SEG_SIG_MAGIC) {
  743                 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE;
  744                 return;
  745         }
  746 
  747         /* Check if APE firmware is running. */
  748         apedata = APE_READ_4(sc, BGE_APE_FW_STATUS);
  749         if ((apedata & BGE_APE_FW_STATUS_READY) == 0) {
  750                 device_printf(sc->bge_dev, "APE signature found "
  751                     "but FW status not ready! 0x%08x\n", apedata);
  752                 return;
  753         }
  754 
  755         sc->bge_mfw_flags |= BGE_MFW_ON_APE;
  756 
  757         /* Fetch the APE firwmare type and version. */
  758         apedata = APE_READ_4(sc, BGE_APE_FW_VERSION);
  759         features = APE_READ_4(sc, BGE_APE_FW_FEATURES);
  760         if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) {
  761                 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI;
  762                 fwtype = "NCSI";
  763         } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) {
  764                 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH;
  765                 fwtype = "DASH";
  766         } else
  767                 fwtype = "UNKN";
  768 
  769         /* Print the APE firmware version. */
  770         device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n",
  771             fwtype,
  772             (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT,
  773             (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT,
  774             (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT,
  775             (apedata & BGE_APE_FW_VERSION_BLDMSK));
  776 }
  777 
  778 static int
  779 bge_ape_lock(struct bge_softc *sc, int locknum)
  780 {
  781         uint32_t bit, gnt, req, status;
  782         int i, off;
  783 
  784         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
  785                 return (0);
  786 
  787         /* Lock request/grant registers have different bases. */
  788         if (sc->bge_asicrev == BGE_ASICREV_BCM5761) {
  789                 req = BGE_APE_LOCK_REQ;
  790                 gnt = BGE_APE_LOCK_GRANT;
  791         } else {
  792                 req = BGE_APE_PER_LOCK_REQ;
  793                 gnt = BGE_APE_PER_LOCK_GRANT;
  794         }
  795 
  796         off = 4 * locknum;
  797 
  798         switch (locknum) {
  799         case BGE_APE_LOCK_GPIO:
  800                 /* Lock required when using GPIO. */
  801                 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
  802                         return (0);
  803                 if (sc->bge_func_addr == 0)
  804                         bit = BGE_APE_LOCK_REQ_DRIVER0;
  805                 else
  806                         bit = (1 << sc->bge_func_addr);
  807                 break;
  808         case BGE_APE_LOCK_GRC:
  809                 /* Lock required to reset the device. */
  810                 if (sc->bge_func_addr == 0)
  811                         bit = BGE_APE_LOCK_REQ_DRIVER0;
  812                 else
  813                         bit = (1 << sc->bge_func_addr);
  814                 break;
  815         case BGE_APE_LOCK_MEM:
  816                 /* Lock required when accessing certain APE memory. */
  817                 if (sc->bge_func_addr == 0)
  818                         bit = BGE_APE_LOCK_REQ_DRIVER0;
  819                 else
  820                         bit = (1 << sc->bge_func_addr);
  821                 break;
  822         case BGE_APE_LOCK_PHY0:
  823         case BGE_APE_LOCK_PHY1:
  824         case BGE_APE_LOCK_PHY2:
  825         case BGE_APE_LOCK_PHY3:
  826                 /* Lock required when accessing PHYs. */
  827                 bit = BGE_APE_LOCK_REQ_DRIVER0;
  828                 break;
  829         default:
  830                 return (EINVAL);
  831         }
  832 
  833         /* Request a lock. */
  834         APE_WRITE_4(sc, req + off, bit);
  835 
  836         /* Wait up to 1 second to acquire lock. */
  837         for (i = 0; i < 20000; i++) {
  838                 status = APE_READ_4(sc, gnt + off);
  839                 if (status == bit)
  840                         break;
  841                 DELAY(50);
  842         }
  843 
  844         /* Handle any errors. */
  845         if (status != bit) {
  846                 device_printf(sc->bge_dev, "APE lock %d request failed! "
  847                     "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n",
  848                     locknum, req + off, bit & 0xFFFF, gnt + off,
  849                     status & 0xFFFF);
  850                 /* Revoke the lock request. */
  851                 APE_WRITE_4(sc, gnt + off, bit);
  852                 return (EBUSY);
  853         }
  854 
  855         return (0);
  856 }
  857 
  858 static void
  859 bge_ape_unlock(struct bge_softc *sc, int locknum)
  860 {
  861         uint32_t bit, gnt;
  862         int off;
  863 
  864         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
  865                 return;
  866 
  867         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
  868                 gnt = BGE_APE_LOCK_GRANT;
  869         else
  870                 gnt = BGE_APE_PER_LOCK_GRANT;
  871 
  872         off = 4 * locknum;
  873 
  874         switch (locknum) {
  875         case BGE_APE_LOCK_GPIO:
  876                 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
  877                         return;
  878                 if (sc->bge_func_addr == 0)
  879                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
  880                 else
  881                         bit = (1 << sc->bge_func_addr);
  882                 break;
  883         case BGE_APE_LOCK_GRC:
  884                 if (sc->bge_func_addr == 0)
  885                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
  886                 else
  887                         bit = (1 << sc->bge_func_addr);
  888                 break;
  889         case BGE_APE_LOCK_MEM:
  890                 if (sc->bge_func_addr == 0)
  891                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
  892                 else
  893                         bit = (1 << sc->bge_func_addr);
  894                 break;
  895         case BGE_APE_LOCK_PHY0:
  896         case BGE_APE_LOCK_PHY1:
  897         case BGE_APE_LOCK_PHY2:
  898         case BGE_APE_LOCK_PHY3:
  899                 bit = BGE_APE_LOCK_GRANT_DRIVER0;
  900                 break;
  901         default:
  902                 return;
  903         }
  904 
  905         APE_WRITE_4(sc, gnt + off, bit);
  906 }
  907 
  908 /*
  909  * Send an event to the APE firmware.
  910  */
  911 static void
  912 bge_ape_send_event(struct bge_softc *sc, uint32_t event)
  913 {
  914         uint32_t apedata;
  915         int i;
  916 
  917         /* NCSI does not support APE events. */
  918         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
  919                 return;
  920 
  921         /* Wait up to 1ms for APE to service previous event. */
  922         for (i = 10; i > 0; i--) {
  923                 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0)
  924                         break;
  925                 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS);
  926                 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) {
  927                         APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |
  928                             BGE_APE_EVENT_STATUS_EVENT_PENDING);
  929                         bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
  930                         APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1);
  931                         break;
  932                 }
  933                 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
  934                 DELAY(100);
  935         }
  936         if (i == 0)
  937                 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n",
  938                     event);
  939 }
  940 
  941 static void
  942 bge_ape_driver_state_change(struct bge_softc *sc, int kind)
  943 {
  944         uint32_t apedata, event;
  945 
  946         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
  947                 return;
  948 
  949         switch (kind) {
  950         case BGE_RESET_START:
  951                 /* If this is the first load, clear the load counter. */
  952                 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG);
  953                 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC)
  954                         APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0);
  955                 else {
  956                         apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT);
  957                         APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata);
  958                 }
  959                 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,
  960                     BGE_APE_HOST_SEG_SIG_MAGIC);
  961                 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,
  962                     BGE_APE_HOST_SEG_LEN_MAGIC);
  963 
  964                 /* Add some version info if bge(4) supports it. */
  965                 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,
  966                     BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0));
  967                 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,
  968                     BGE_APE_HOST_BEHAV_NO_PHYLOCK);
  969                 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,
  970                     BGE_APE_HOST_HEARTBEAT_INT_DISABLE);
  971                 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
  972                     BGE_APE_HOST_DRVR_STATE_START);
  973                 event = BGE_APE_EVENT_STATUS_STATE_START;
  974                 break;
  975         case BGE_RESET_SHUTDOWN:
  976                 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
  977                     BGE_APE_HOST_DRVR_STATE_UNLOAD);
  978                 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
  979                 break;
  980         case BGE_RESET_SUSPEND:
  981                 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
  982                 break;
  983         default:
  984                 return;
  985         }
  986 
  987         bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT |
  988             BGE_APE_EVENT_STATUS_STATE_CHNGE);
  989 }
  990 
  991 /*
  992  * Map a single buffer address.
  993  */
  994 
  995 static void
  996 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
  997 {
  998         struct bge_dmamap_arg *ctx;
  999 
 1000         if (error)
 1001                 return;
 1002 
 1003         KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
 1004 
 1005         ctx = arg;
 1006         ctx->bge_busaddr = segs->ds_addr;
 1007 }
 1008 
 1009 static uint8_t
 1010 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 1011 {
 1012         uint32_t access, byte = 0;
 1013         int i;
 1014 
 1015         /* Lock. */
 1016         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 1017         for (i = 0; i < 8000; i++) {
 1018                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 1019                         break;
 1020                 DELAY(20);
 1021         }
 1022         if (i == 8000)
 1023                 return (1);
 1024 
 1025         /* Enable access. */
 1026         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 1027         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 1028 
 1029         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 1030         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 1031         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 1032                 DELAY(10);
 1033                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 1034                         DELAY(10);
 1035                         break;
 1036                 }
 1037         }
 1038 
 1039         if (i == BGE_TIMEOUT * 10) {
 1040                 if_printf(sc->bge_ifp, "nvram read timed out\n");
 1041                 return (1);
 1042         }
 1043 
 1044         /* Get result. */
 1045         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 1046 
 1047         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 1048 
 1049         /* Disable access. */
 1050         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 1051 
 1052         /* Unlock. */
 1053         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 1054         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 1055 
 1056         return (0);
 1057 }
 1058 
 1059 /*
 1060  * Read a sequence of bytes from NVRAM.
 1061  */
 1062 static int
 1063 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 1064 {
 1065         int err = 0, i;
 1066         uint8_t byte = 0;
 1067 
 1068         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 1069                 return (1);
 1070 
 1071         for (i = 0; i < cnt; i++) {
 1072                 err = bge_nvram_getbyte(sc, off + i, &byte);
 1073                 if (err)
 1074                         break;
 1075                 *(dest + i) = byte;
 1076         }
 1077 
 1078         return (err ? 1 : 0);
 1079 }
 1080 
 1081 /*
 1082  * Read a byte of data stored in the EEPROM at address 'addr.' The
 1083  * BCM570x supports both the traditional bitbang interface and an
 1084  * auto access interface for reading the EEPROM. We use the auto
 1085  * access method.
 1086  */
 1087 static uint8_t
 1088 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 1089 {
 1090         int i;
 1091         uint32_t byte = 0;
 1092 
 1093         /*
 1094          * Enable use of auto EEPROM access so we can avoid
 1095          * having to use the bitbang method.
 1096          */
 1097         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 1098 
 1099         /* Reset the EEPROM, load the clock period. */
 1100         CSR_WRITE_4(sc, BGE_EE_ADDR,
 1101             BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 1102         DELAY(20);
 1103 
 1104         /* Issue the read EEPROM command. */
 1105         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 1106 
 1107         /* Wait for completion */
 1108         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 1109                 DELAY(10);
 1110                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 1111                         break;
 1112         }
 1113 
 1114         if (i == BGE_TIMEOUT * 10) {
 1115                 device_printf(sc->bge_dev, "EEPROM read timed out\n");
 1116                 return (1);
 1117         }
 1118 
 1119         /* Get result. */
 1120         byte = CSR_READ_4(sc, BGE_EE_DATA);
 1121 
 1122         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 1123 
 1124         return (0);
 1125 }
 1126 
 1127 /*
 1128  * Read a sequence of bytes from the EEPROM.
 1129  */
 1130 static int
 1131 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 1132 {
 1133         int i, error = 0;
 1134         uint8_t byte = 0;
 1135 
 1136         for (i = 0; i < cnt; i++) {
 1137                 error = bge_eeprom_getbyte(sc, off + i, &byte);
 1138                 if (error)
 1139                         break;
 1140                 *(dest + i) = byte;
 1141         }
 1142 
 1143         return (error ? 1 : 0);
 1144 }
 1145 
 1146 static int
 1147 bge_miibus_readreg(device_t dev, int phy, int reg)
 1148 {
 1149         struct bge_softc *sc;
 1150         uint32_t val;
 1151         int i;
 1152 
 1153         sc = device_get_softc(dev);
 1154 
 1155         if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
 1156                 return (0);
 1157 
 1158         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 1159         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
 1160                 CSR_WRITE_4(sc, BGE_MI_MODE,
 1161                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 1162                 DELAY(80);
 1163         }
 1164 
 1165         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 1166             BGE_MIPHY(phy) | BGE_MIREG(reg));
 1167 
 1168         /* Poll for the PHY register access to complete. */
 1169         for (i = 0; i < BGE_TIMEOUT; i++) {
 1170                 DELAY(10);
 1171                 val = CSR_READ_4(sc, BGE_MI_COMM);
 1172                 if ((val & BGE_MICOMM_BUSY) == 0) {
 1173                         DELAY(5);
 1174                         val = CSR_READ_4(sc, BGE_MI_COMM);
 1175                         break;
 1176                 }
 1177         }
 1178 
 1179         if (i == BGE_TIMEOUT) {
 1180                 device_printf(sc->bge_dev,
 1181                     "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
 1182                     phy, reg, val);
 1183                 val = 0;
 1184         }
 1185 
 1186         /* Restore the autopoll bit if necessary. */
 1187         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
 1188                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
 1189                 DELAY(80);
 1190         }
 1191 
 1192         bge_ape_unlock(sc, sc->bge_phy_ape_lock);
 1193 
 1194         if (val & BGE_MICOMM_READFAIL)
 1195                 return (0);
 1196 
 1197         return (val & 0xFFFF);
 1198 }
 1199 
 1200 static int
 1201 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 1202 {
 1203         struct bge_softc *sc;
 1204         int i;
 1205 
 1206         sc = device_get_softc(dev);
 1207 
 1208         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 1209             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 1210                 return (0);
 1211 
 1212         if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
 1213                 return (0);
 1214 
 1215         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 1216         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
 1217                 CSR_WRITE_4(sc, BGE_MI_MODE,
 1218                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 1219                 DELAY(80);
 1220         }
 1221 
 1222         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 1223             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 1224 
 1225         for (i = 0; i < BGE_TIMEOUT; i++) {
 1226                 DELAY(10);
 1227                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 1228                         DELAY(5);
 1229                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 1230                         break;
 1231                 }
 1232         }
 1233 
 1234         /* Restore the autopoll bit if necessary. */
 1235         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
 1236                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
 1237                 DELAY(80);
 1238         }
 1239 
 1240         bge_ape_unlock(sc, sc->bge_phy_ape_lock);
 1241 
 1242         if (i == BGE_TIMEOUT)
 1243                 device_printf(sc->bge_dev,
 1244                     "PHY write timed out (phy %d, reg %d, val 0x%04x)\n",
 1245                     phy, reg, val);
 1246 
 1247         return (0);
 1248 }
 1249 
 1250 static void
 1251 bge_miibus_statchg(device_t dev)
 1252 {
 1253         struct bge_softc *sc;
 1254         struct mii_data *mii;
 1255         uint32_t mac_mode, rx_mode, tx_mode;
 1256 
 1257         sc = device_get_softc(dev);
 1258         if ((if_getdrvflags(sc->bge_ifp) & IFF_DRV_RUNNING) == 0)
 1259                 return;
 1260         mii = device_get_softc(sc->bge_miibus);
 1261 
 1262         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 1263             (IFM_ACTIVE | IFM_AVALID)) {
 1264                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 1265                 case IFM_10_T:
 1266                 case IFM_100_TX:
 1267                         sc->bge_link = 1;
 1268                         break;
 1269                 case IFM_1000_T:
 1270                 case IFM_1000_SX:
 1271                 case IFM_2500_SX:
 1272                         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 1273                                 sc->bge_link = 1;
 1274                         else
 1275                                 sc->bge_link = 0;
 1276                         break;
 1277                 default:
 1278                         sc->bge_link = 0;
 1279                         break;
 1280                 }
 1281         } else
 1282                 sc->bge_link = 0;
 1283         if (sc->bge_link == 0)
 1284                 return;
 1285 
 1286         /*
 1287          * APE firmware touches these registers to keep the MAC
 1288          * connected to the outside world.  Try to keep the
 1289          * accesses atomic.
 1290          */
 1291 
 1292         /* Set the port mode (MII/GMII) to match the link speed. */
 1293         mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
 1294             ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
 1295         tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
 1296         rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
 1297 
 1298         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 1299             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
 1300                 mac_mode |= BGE_PORTMODE_GMII;
 1301         else
 1302                 mac_mode |= BGE_PORTMODE_MII;
 1303 
 1304         /* Set MAC flow control behavior to match link flow control settings. */
 1305         tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE;
 1306         rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE;
 1307         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
 1308                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
 1309                         tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE;
 1310                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
 1311                         rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE;
 1312         } else
 1313                 mac_mode |= BGE_MACMODE_HALF_DUPLEX;
 1314 
 1315         CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode);
 1316         DELAY(40);
 1317         CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
 1318         CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
 1319 }
 1320 
 1321 /*
 1322  * Intialize a standard receive ring descriptor.
 1323  */
 1324 static int
 1325 bge_newbuf_std(struct bge_softc *sc, int i)
 1326 {
 1327         struct mbuf *m;
 1328         struct bge_rx_bd *r;
 1329         bus_dma_segment_t segs[1];
 1330         bus_dmamap_t map;
 1331         int error, nsegs;
 1332 
 1333         if (sc->bge_flags & BGE_FLAG_JUMBO_STD &&
 1334             (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
 1335             ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) {
 1336                 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
 1337                 if (m == NULL)
 1338                         return (ENOBUFS);
 1339                 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
 1340         } else {
 1341                 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
 1342                 if (m == NULL)
 1343                         return (ENOBUFS);
 1344                 m->m_len = m->m_pkthdr.len = MCLBYTES;
 1345         }
 1346         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 1347                 m_adj(m, ETHER_ALIGN);
 1348 
 1349         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
 1350             sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
 1351         if (error != 0) {
 1352                 m_freem(m);
 1353                 return (error);
 1354         }
 1355         if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 1356                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 1357                     sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
 1358                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
 1359                     sc->bge_cdata.bge_rx_std_dmamap[i]);
 1360         }
 1361         map = sc->bge_cdata.bge_rx_std_dmamap[i];
 1362         sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
 1363         sc->bge_cdata.bge_rx_std_sparemap = map;
 1364         sc->bge_cdata.bge_rx_std_chain[i] = m;
 1365         sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
 1366         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
 1367         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
 1368         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
 1369         r->bge_flags = BGE_RXBDFLAG_END;
 1370         r->bge_len = segs[0].ds_len;
 1371         r->bge_idx = i;
 1372 
 1373         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 1374             sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
 1375 
 1376         return (0);
 1377 }
 1378 
 1379 /*
 1380  * Initialize a jumbo receive ring descriptor. This allocates
 1381  * a jumbo buffer from the pool managed internally by the driver.
 1382  */
 1383 static int
 1384 bge_newbuf_jumbo(struct bge_softc *sc, int i)
 1385 {
 1386         bus_dma_segment_t segs[BGE_NSEG_JUMBO];
 1387         bus_dmamap_t map;
 1388         struct bge_extrx_bd *r;
 1389         struct mbuf *m;
 1390         int error, nsegs;
 1391 
 1392         MGETHDR(m, M_NOWAIT, MT_DATA);
 1393         if (m == NULL)
 1394                 return (ENOBUFS);
 1395 
 1396         if (m_cljget(m, M_NOWAIT, MJUM9BYTES) == NULL) {
 1397                 m_freem(m);
 1398                 return (ENOBUFS);
 1399         }
 1400         m->m_len = m->m_pkthdr.len = MJUM9BYTES;
 1401         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 1402                 m_adj(m, ETHER_ALIGN);
 1403 
 1404         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
 1405             sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
 1406         if (error != 0) {
 1407                 m_freem(m);
 1408                 return (error);
 1409         }
 1410 
 1411         if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
 1412                 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
 1413                     sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
 1414                 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
 1415                     sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
 1416         }
 1417         map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
 1418         sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
 1419             sc->bge_cdata.bge_rx_jumbo_sparemap;
 1420         sc->bge_cdata.bge_rx_jumbo_sparemap = map;
 1421         sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
 1422         sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
 1423         sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
 1424         sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
 1425         sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
 1426 
 1427         /*
 1428          * Fill in the extended RX buffer descriptor.
 1429          */
 1430         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
 1431         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
 1432         r->bge_idx = i;
 1433         r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
 1434         switch (nsegs) {
 1435         case 4:
 1436                 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
 1437                 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
 1438                 r->bge_len3 = segs[3].ds_len;
 1439                 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
 1440         case 3:
 1441                 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
 1442                 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
 1443                 r->bge_len2 = segs[2].ds_len;
 1444                 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
 1445         case 2:
 1446                 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
 1447                 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
 1448                 r->bge_len1 = segs[1].ds_len;
 1449                 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
 1450         case 1:
 1451                 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
 1452                 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
 1453                 r->bge_len0 = segs[0].ds_len;
 1454                 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
 1455                 break;
 1456         default:
 1457                 panic("%s: %d segments\n", __func__, nsegs);
 1458         }
 1459 
 1460         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
 1461             sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
 1462 
 1463         return (0);
 1464 }
 1465 
 1466 static int
 1467 bge_init_rx_ring_std(struct bge_softc *sc)
 1468 {
 1469         int error, i;
 1470 
 1471         bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
 1472         sc->bge_std = 0;
 1473         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 1474                 if ((error = bge_newbuf_std(sc, i)) != 0)
 1475                         return (error);
 1476                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
 1477         }
 1478 
 1479         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
 1480             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
 1481 
 1482         sc->bge_std = 0;
 1483         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
 1484 
 1485         return (0);
 1486 }
 1487 
 1488 static void
 1489 bge_free_rx_ring_std(struct bge_softc *sc)
 1490 {
 1491         int i;
 1492 
 1493         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 1494                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 1495                         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 1496                             sc->bge_cdata.bge_rx_std_dmamap[i],
 1497                             BUS_DMASYNC_POSTREAD);
 1498                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
 1499                             sc->bge_cdata.bge_rx_std_dmamap[i]);
 1500                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
 1501                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
 1502                 }
 1503                 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
 1504                     sizeof(struct bge_rx_bd));
 1505         }
 1506 }
 1507 
 1508 static int
 1509 bge_init_rx_ring_jumbo(struct bge_softc *sc)
 1510 {
 1511         struct bge_rcb *rcb;
 1512         int error, i;
 1513 
 1514         bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
 1515         sc->bge_jumbo = 0;
 1516         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 1517                 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
 1518                         return (error);
 1519                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
 1520         }
 1521 
 1522         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 1523             sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
 1524 
 1525         sc->bge_jumbo = 0;
 1526 
 1527         /* Enable the jumbo receive producer ring. */
 1528         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
 1529         rcb->bge_maxlen_flags =
 1530             BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD);
 1531         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 1532 
 1533         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
 1534 
 1535         return (0);
 1536 }
 1537 
 1538 static void
 1539 bge_free_rx_ring_jumbo(struct bge_softc *sc)
 1540 {
 1541         int i;
 1542 
 1543         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 1544                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
 1545                         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
 1546                             sc->bge_cdata.bge_rx_jumbo_dmamap[i],
 1547                             BUS_DMASYNC_POSTREAD);
 1548                         bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
 1549                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
 1550                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
 1551                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
 1552                 }
 1553                 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
 1554                     sizeof(struct bge_extrx_bd));
 1555         }
 1556 }
 1557 
 1558 static void
 1559 bge_free_tx_ring(struct bge_softc *sc)
 1560 {
 1561         int i;
 1562 
 1563         if (sc->bge_ldata.bge_tx_ring == NULL)
 1564                 return;
 1565 
 1566         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 1567                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
 1568                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
 1569                             sc->bge_cdata.bge_tx_dmamap[i],
 1570                             BUS_DMASYNC_POSTWRITE);
 1571                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
 1572                             sc->bge_cdata.bge_tx_dmamap[i]);
 1573                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
 1574                         sc->bge_cdata.bge_tx_chain[i] = NULL;
 1575                 }
 1576                 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
 1577                     sizeof(struct bge_tx_bd));
 1578         }
 1579 }
 1580 
 1581 static int
 1582 bge_init_tx_ring(struct bge_softc *sc)
 1583 {
 1584         sc->bge_txcnt = 0;
 1585         sc->bge_tx_saved_considx = 0;
 1586 
 1587         bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
 1588         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
 1589             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
 1590 
 1591         /* Initialize transmit producer index for host-memory send ring. */
 1592         sc->bge_tx_prodidx = 0;
 1593         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
 1594 
 1595         /* 5700 b2 errata */
 1596         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
 1597                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
 1598 
 1599         /* NIC-memory send ring not used; initialize to zero. */
 1600         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
 1601         /* 5700 b2 errata */
 1602         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
 1603                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
 1604 
 1605         return (0);
 1606 }
 1607 
 1608 static void
 1609 bge_setpromisc(struct bge_softc *sc)
 1610 {
 1611         if_t ifp;
 1612 
 1613         BGE_LOCK_ASSERT(sc);
 1614 
 1615         ifp = sc->bge_ifp;
 1616 
 1617         /* Enable or disable promiscuous mode as needed. */
 1618         if (if_getflags(ifp) & IFF_PROMISC)
 1619                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
 1620         else
 1621                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
 1622 }
 1623 
 1624 static void
 1625 bge_setmulti(struct bge_softc *sc)
 1626 {
 1627         if_t ifp;
 1628         int mc_count = 0;
 1629         uint32_t hashes[4] = { 0, 0, 0, 0 };
 1630         int h, i, mcnt;
 1631         unsigned char *mta;
 1632 
 1633         BGE_LOCK_ASSERT(sc);
 1634 
 1635         ifp = sc->bge_ifp;
 1636 
 1637         mc_count = if_multiaddr_count(ifp, -1);
 1638         mta = malloc(sizeof(unsigned char) *  ETHER_ADDR_LEN *
 1639             mc_count, M_DEVBUF, M_NOWAIT);
 1640 
 1641         if(mta == NULL) {
 1642                 device_printf(sc->bge_dev, 
 1643                     "Failed to allocated temp mcast list\n");
 1644                 return;
 1645         }
 1646 
 1647         if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) {
 1648                 for (i = 0; i < 4; i++)
 1649                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
 1650                 free(mta, M_DEVBUF);
 1651                 return;
 1652         }
 1653 
 1654         /* First, zot all the existing filters. */
 1655         for (i = 0; i < 4; i++)
 1656                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
 1657 
 1658         if_multiaddr_array(ifp, mta, &mcnt, mc_count);
 1659         for(i = 0; i < mcnt; i++) {
 1660                 h = ether_crc32_le(mta + (i * ETHER_ADDR_LEN),
 1661                     ETHER_ADDR_LEN) & 0x7F;
 1662                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
 1663         }
 1664 
 1665         for (i = 0; i < 4; i++)
 1666                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
 1667 
 1668         free(mta, M_DEVBUF);
 1669 }
 1670 
 1671 static void
 1672 bge_setvlan(struct bge_softc *sc)
 1673 {
 1674         if_t ifp;
 1675 
 1676         BGE_LOCK_ASSERT(sc);
 1677 
 1678         ifp = sc->bge_ifp;
 1679 
 1680         /* Enable or disable VLAN tag stripping as needed. */
 1681         if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING)
 1682                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
 1683         else
 1684                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
 1685 }
 1686 
 1687 static void
 1688 bge_sig_pre_reset(struct bge_softc *sc, int type)
 1689 {
 1690 
 1691         /*
 1692          * Some chips don't like this so only do this if ASF is enabled
 1693          */
 1694         if (sc->bge_asf_mode)
 1695                 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
 1696 
 1697         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
 1698                 switch (type) {
 1699                 case BGE_RESET_START:
 1700                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
 1701                             BGE_FW_DRV_STATE_START);
 1702                         break;
 1703                 case BGE_RESET_SHUTDOWN:
 1704                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
 1705                             BGE_FW_DRV_STATE_UNLOAD);
 1706                         break;
 1707                 case BGE_RESET_SUSPEND:
 1708                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
 1709                             BGE_FW_DRV_STATE_SUSPEND);
 1710                         break;
 1711                 }
 1712         }
 1713 
 1714         if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
 1715                 bge_ape_driver_state_change(sc, type);
 1716 }
 1717 
 1718 static void
 1719 bge_sig_post_reset(struct bge_softc *sc, int type)
 1720 {
 1721 
 1722         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
 1723                 switch (type) {
 1724                 case BGE_RESET_START:
 1725                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
 1726                             BGE_FW_DRV_STATE_START_DONE);
 1727                         /* START DONE */
 1728                         break;
 1729                 case BGE_RESET_SHUTDOWN:
 1730                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
 1731                             BGE_FW_DRV_STATE_UNLOAD_DONE);
 1732                         break;
 1733                 }
 1734         }
 1735         if (type == BGE_RESET_SHUTDOWN)
 1736                 bge_ape_driver_state_change(sc, type);
 1737 }
 1738 
 1739 static void
 1740 bge_sig_legacy(struct bge_softc *sc, int type)
 1741 {
 1742 
 1743         if (sc->bge_asf_mode) {
 1744                 switch (type) {
 1745                 case BGE_RESET_START:
 1746                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
 1747                             BGE_FW_DRV_STATE_START);
 1748                         break;
 1749                 case BGE_RESET_SHUTDOWN:
 1750                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
 1751                             BGE_FW_DRV_STATE_UNLOAD);
 1752                         break;
 1753                 }
 1754         }
 1755 }
 1756 
 1757 static void
 1758 bge_stop_fw(struct bge_softc *sc)
 1759 {
 1760         int i;
 1761 
 1762         if (sc->bge_asf_mode) {
 1763                 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
 1764                 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
 1765                     CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
 1766 
 1767                 for (i = 0; i < 100; i++ ) {
 1768                         if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
 1769                             BGE_RX_CPU_DRV_EVENT))
 1770                                 break;
 1771                         DELAY(10);
 1772                 }
 1773         }
 1774 }
 1775 
 1776 static uint32_t
 1777 bge_dma_swap_options(struct bge_softc *sc)
 1778 {
 1779         uint32_t dma_options;
 1780 
 1781         dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
 1782             BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
 1783 #if BYTE_ORDER == BIG_ENDIAN
 1784         dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
 1785 #endif
 1786         return (dma_options);
 1787 }
 1788 
 1789 /*
 1790  * Do endian, PCI and DMA initialization.
 1791  */
 1792 static int
 1793 bge_chipinit(struct bge_softc *sc)
 1794 {
 1795         uint32_t dma_rw_ctl, misc_ctl, mode_ctl;
 1796         uint16_t val;
 1797         int i;
 1798 
 1799         /* Set endianness before we access any non-PCI registers. */
 1800         misc_ctl = BGE_INIT;
 1801         if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
 1802                 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
 1803         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
 1804 
 1805         /*
 1806          * Clear the MAC statistics block in the NIC's
 1807          * internal memory.
 1808          */
 1809         for (i = BGE_STATS_BLOCK;
 1810             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
 1811                 BGE_MEMWIN_WRITE(sc, i, 0);
 1812 
 1813         for (i = BGE_STATUS_BLOCK;
 1814             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
 1815                 BGE_MEMWIN_WRITE(sc, i, 0);
 1816 
 1817         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
 1818                 /*
 1819                  *  Fix data corruption caused by non-qword write with WB.
 1820                  *  Fix master abort in PCI mode.
 1821                  *  Fix PCI latency timer.
 1822                  */
 1823                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
 1824                 val |= (1 << 10) | (1 << 12) | (1 << 13);
 1825                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
 1826         }
 1827 
 1828         if (sc->bge_asicrev == BGE_ASICREV_BCM57765 ||
 1829             sc->bge_asicrev == BGE_ASICREV_BCM57766) {
 1830                 /*
 1831                  * For the 57766 and non Ax versions of 57765, bootcode
 1832                  * needs to setup the PCIE Fast Training Sequence (FTS)
 1833                  * value to prevent transmit hangs.
 1834                  */
 1835                 if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) {
 1836                         CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL,
 1837                             CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) |
 1838                             BGE_CPMU_PADRNG_CTL_RDIV2);
 1839                 }
 1840         }
 1841 
 1842         /*
 1843          * Set up the PCI DMA control register.
 1844          */
 1845         dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
 1846             BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
 1847         if (sc->bge_flags & BGE_FLAG_PCIE) {
 1848                 if (sc->bge_mps >= 256)
 1849                         dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
 1850                 else
 1851                         dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
 1852         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
 1853                 if (BGE_IS_5714_FAMILY(sc)) {
 1854                         /* 256 bytes for read and write. */
 1855                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
 1856                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
 1857                         dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
 1858                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
 1859                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
 1860                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
 1861                         /*
 1862                          * In the BCM5703, the DMA read watermark should
 1863                          * be set to less than or equal to the maximum
 1864                          * memory read byte count of the PCI-X command
 1865                          * register.
 1866                          */
 1867                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
 1868                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
 1869                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
 1870                         /* 1536 bytes for read, 384 bytes for write. */
 1871                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
 1872                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
 1873                 } else {
 1874                         /* 384 bytes for read and write. */
 1875                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
 1876                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
 1877                             0x0F;
 1878                 }
 1879                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
 1880                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
 1881                         uint32_t tmp;
 1882 
 1883                         /* Set ONE_DMA_AT_ONCE for hardware workaround. */
 1884                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
 1885                         if (tmp == 6 || tmp == 7)
 1886                                 dma_rw_ctl |=
 1887                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
 1888 
 1889                         /* Set PCI-X DMA write workaround. */
 1890                         dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
 1891                 }
 1892         } else {
 1893                 /* Conventional PCI bus: 256 bytes for read and write. */
 1894                 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
 1895                     BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
 1896 
 1897                 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
 1898                     sc->bge_asicrev != BGE_ASICREV_BCM5750)
 1899                         dma_rw_ctl |= 0x0F;
 1900         }
 1901         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
 1902             sc->bge_asicrev == BGE_ASICREV_BCM5701)
 1903                 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
 1904                     BGE_PCIDMARWCTL_ASRT_ALL_BE;
 1905         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
 1906             sc->bge_asicrev == BGE_ASICREV_BCM5704)
 1907                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
 1908         if (BGE_IS_5717_PLUS(sc)) {
 1909                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
 1910                 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
 1911                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
 1912                 /*
 1913                  * Enable HW workaround for controllers that misinterpret
 1914                  * a status tag update and leave interrupts permanently
 1915                  * disabled.
 1916                  */
 1917                 if (!BGE_IS_57765_PLUS(sc) &&
 1918                     sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
 1919                     sc->bge_asicrev != BGE_ASICREV_BCM5762)
 1920                         dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
 1921         }
 1922         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
 1923 
 1924         /*
 1925          * Set up general mode register.
 1926          */
 1927         mode_ctl = bge_dma_swap_options(sc);
 1928         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
 1929             sc->bge_asicrev == BGE_ASICREV_BCM5762) {
 1930                 /* Retain Host-2-BMC settings written by APE firmware. */
 1931                 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
 1932                     (BGE_MODECTL_BYTESWAP_B2HRX_DATA |
 1933                     BGE_MODECTL_WORDSWAP_B2HRX_DATA |
 1934                     BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE);
 1935         }
 1936         mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
 1937             BGE_MODECTL_TX_NO_PHDR_CSUM;
 1938 
 1939         /*
 1940          * BCM5701 B5 have a bug causing data corruption when using
 1941          * 64-bit DMA reads, which can be terminated early and then
 1942          * completed later as 32-bit accesses, in combination with
 1943          * certain bridges.
 1944          */
 1945         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
 1946             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
 1947                 mode_ctl |= BGE_MODECTL_FORCE_PCI32;
 1948 
 1949         /*
 1950          * Tell the firmware the driver is running
 1951          */
 1952         if (sc->bge_asf_mode & ASF_STACKUP)
 1953                 mode_ctl |= BGE_MODECTL_STACKUP;
 1954 
 1955         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
 1956 
 1957         /*
 1958          * Disable memory write invalidate.  Apparently it is not supported
 1959          * properly by these devices.
 1960          */
 1961         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
 1962 
 1963         /* Set the timer prescaler (always 66 MHz). */
 1964         CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
 1965 
 1966         /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
 1967         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
 1968                 DELAY(40);      /* XXX */
 1969 
 1970                 /* Put PHY into ready state */
 1971                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
 1972                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
 1973                 DELAY(40);
 1974         }
 1975 
 1976         return (0);
 1977 }
 1978 
 1979 static int
 1980 bge_blockinit(struct bge_softc *sc)
 1981 {
 1982         struct bge_rcb *rcb;
 1983         bus_size_t vrcb;
 1984         bge_hostaddr taddr;
 1985         uint32_t dmactl, rdmareg, val;
 1986         int i, limit;
 1987 
 1988         /*
 1989          * Initialize the memory window pointer register so that
 1990          * we can access the first 32K of internal NIC RAM. This will
 1991          * allow us to set up the TX send ring RCBs and the RX return
 1992          * ring RCBs, plus other things which live in NIC memory.
 1993          */
 1994         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
 1995 
 1996         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
 1997 
 1998         if (!(BGE_IS_5705_PLUS(sc))) {
 1999                 /* Configure mbuf memory pool */
 2000                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
 2001                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
 2002                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
 2003                 else
 2004                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
 2005 
 2006                 /* Configure DMA resource pool */
 2007                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
 2008                     BGE_DMA_DESCRIPTORS);
 2009                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
 2010         }
 2011 
 2012         /* Configure mbuf pool watermarks */
 2013         if (BGE_IS_5717_PLUS(sc)) {
 2014                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
 2015                 if (if_getmtu(sc->bge_ifp) > ETHERMTU) {
 2016                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
 2017                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
 2018                 } else {
 2019                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
 2020                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
 2021                 }
 2022         } else if (!BGE_IS_5705_PLUS(sc)) {
 2023                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
 2024                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
 2025                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
 2026         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
 2027                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
 2028                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
 2029                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
 2030         } else {
 2031                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
 2032                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
 2033                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
 2034         }
 2035 
 2036         /* Configure DMA resource watermarks */
 2037         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
 2038         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
 2039 
 2040         /* Enable buffer manager */
 2041         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
 2042         /*
 2043          * Change the arbitration algorithm of TXMBUF read request to
 2044          * round-robin instead of priority based for BCM5719.  When
 2045          * TXFIFO is almost empty, RDMA will hold its request until
 2046          * TXFIFO is not almost empty.
 2047          */
 2048         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
 2049                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
 2050         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
 2051 
 2052         /* Poll for buffer manager start indication */
 2053         for (i = 0; i < BGE_TIMEOUT; i++) {
 2054                 DELAY(10);
 2055                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
 2056                         break;
 2057         }
 2058 
 2059         if (i == BGE_TIMEOUT) {
 2060                 device_printf(sc->bge_dev, "buffer manager failed to start\n");
 2061                 return (ENXIO);
 2062         }
 2063 
 2064         /* Enable flow-through queues */
 2065         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
 2066         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
 2067 
 2068         /* Wait until queue initialization is complete */
 2069         for (i = 0; i < BGE_TIMEOUT; i++) {
 2070                 DELAY(10);
 2071                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
 2072                         break;
 2073         }
 2074 
 2075         if (i == BGE_TIMEOUT) {
 2076                 device_printf(sc->bge_dev, "flow-through queue init failed\n");
 2077                 return (ENXIO);
 2078         }
 2079 
 2080         /*
 2081          * Summary of rings supported by the controller:
 2082          *
 2083          * Standard Receive Producer Ring
 2084          * - This ring is used to feed receive buffers for "standard"
 2085          *   sized frames (typically 1536 bytes) to the controller.
 2086          *
 2087          * Jumbo Receive Producer Ring
 2088          * - This ring is used to feed receive buffers for jumbo sized
 2089          *   frames (i.e. anything bigger than the "standard" frames)
 2090          *   to the controller.
 2091          *
 2092          * Mini Receive Producer Ring
 2093          * - This ring is used to feed receive buffers for "mini"
 2094          *   sized frames to the controller.
 2095          * - This feature required external memory for the controller
 2096          *   but was never used in a production system.  Should always
 2097          *   be disabled.
 2098          *
 2099          * Receive Return Ring
 2100          * - After the controller has placed an incoming frame into a
 2101          *   receive buffer that buffer is moved into a receive return
 2102          *   ring.  The driver is then responsible to passing the
 2103          *   buffer up to the stack.  Many versions of the controller
 2104          *   support multiple RR rings.
 2105          *
 2106          * Send Ring
 2107          * - This ring is used for outgoing frames.  Many versions of
 2108          *   the controller support multiple send rings.
 2109          */
 2110 
 2111         /* Initialize the standard receive producer ring control block. */
 2112         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
 2113         rcb->bge_hostaddr.bge_addr_lo =
 2114             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
 2115         rcb->bge_hostaddr.bge_addr_hi =
 2116             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
 2117         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
 2118             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
 2119         if (BGE_IS_5717_PLUS(sc)) {
 2120                 /*
 2121                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
 2122                  * Bits 15-2 : Maximum RX frame size
 2123                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
 2124                  * Bit 0     : Reserved
 2125                  */
 2126                 rcb->bge_maxlen_flags =
 2127                     BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
 2128         } else if (BGE_IS_5705_PLUS(sc)) {
 2129                 /*
 2130                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
 2131                  * Bits 15-2 : Reserved (should be 0)
 2132                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
 2133                  * Bit 0     : Reserved
 2134                  */
 2135                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
 2136         } else {
 2137                 /*
 2138                  * Ring size is always XXX entries
 2139                  * Bits 31-16: Maximum RX frame size
 2140                  * Bits 15-2 : Reserved (should be 0)
 2141                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
 2142                  * Bit 0     : Reserved
 2143                  */
 2144                 rcb->bge_maxlen_flags =
 2145                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
 2146         }
 2147         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
 2148             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
 2149             sc->bge_asicrev == BGE_ASICREV_BCM5720)
 2150                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
 2151         else
 2152                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
 2153         /* Write the standard receive producer ring control block. */
 2154         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
 2155         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
 2156         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 2157         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
 2158 
 2159         /* Reset the standard receive producer ring producer index. */
 2160         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
 2161 
 2162         /*
 2163          * Initialize the jumbo RX producer ring control
 2164          * block.  We set the 'ring disabled' bit in the
 2165          * flags field until we're actually ready to start
 2166          * using this ring (i.e. once we set the MTU
 2167          * high enough to require it).
 2168          */
 2169         if (BGE_IS_JUMBO_CAPABLE(sc)) {
 2170                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
 2171                 /* Get the jumbo receive producer ring RCB parameters. */
 2172                 rcb->bge_hostaddr.bge_addr_lo =
 2173                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
 2174                 rcb->bge_hostaddr.bge_addr_hi =
 2175                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
 2176                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 2177                     sc->bge_cdata.bge_rx_jumbo_ring_map,
 2178                     BUS_DMASYNC_PREREAD);
 2179                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
 2180                     BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
 2181                 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
 2182                     sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
 2183                     sc->bge_asicrev == BGE_ASICREV_BCM5720)
 2184                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
 2185                 else
 2186                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
 2187                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
 2188                     rcb->bge_hostaddr.bge_addr_hi);
 2189                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
 2190                     rcb->bge_hostaddr.bge_addr_lo);
 2191                 /* Program the jumbo receive producer ring RCB parameters. */
 2192                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
 2193                     rcb->bge_maxlen_flags);
 2194                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
 2195                 /* Reset the jumbo receive producer ring producer index. */
 2196                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
 2197         }
 2198 
 2199         /* Disable the mini receive producer ring RCB. */
 2200         if (BGE_IS_5700_FAMILY(sc)) {
 2201                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
 2202                 rcb->bge_maxlen_flags =
 2203                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
 2204                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
 2205                     rcb->bge_maxlen_flags);
 2206                 /* Reset the mini receive producer ring producer index. */
 2207                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
 2208         }
 2209 
 2210         /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
 2211         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
 2212                 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
 2213                     sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
 2214                     sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
 2215                         CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
 2216                             (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
 2217         }
 2218         /*
 2219          * The BD ring replenish thresholds control how often the
 2220          * hardware fetches new BD's from the producer rings in host
 2221          * memory.  Setting the value too low on a busy system can
 2222          * starve the hardware and recue the throughpout.
 2223          *
 2224          * Set the BD ring replentish thresholds. The recommended
 2225          * values are 1/8th the number of descriptors allocated to
 2226          * each ring.
 2227          * XXX The 5754 requires a lower threshold, so it might be a
 2228          * requirement of all 575x family chips.  The Linux driver sets
 2229          * the lower threshold for all 5705 family chips as well, but there
 2230          * are reports that it might not need to be so strict.
 2231          *
 2232          * XXX Linux does some extra fiddling here for the 5906 parts as
 2233          * well.
 2234          */
 2235         if (BGE_IS_5705_PLUS(sc))
 2236                 val = 8;
 2237         else
 2238                 val = BGE_STD_RX_RING_CNT / 8;
 2239         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
 2240         if (BGE_IS_JUMBO_CAPABLE(sc))
 2241                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
 2242                     BGE_JUMBO_RX_RING_CNT/8);
 2243         if (BGE_IS_5717_PLUS(sc)) {
 2244                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
 2245                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
 2246         }
 2247 
 2248         /*
 2249          * Disable all send rings by setting the 'ring disabled' bit
 2250          * in the flags field of all the TX send ring control blocks,
 2251          * located in NIC memory.
 2252          */
 2253         if (!BGE_IS_5705_PLUS(sc))
 2254                 /* 5700 to 5704 had 16 send rings. */
 2255                 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
 2256         else if (BGE_IS_57765_PLUS(sc) ||
 2257             sc->bge_asicrev == BGE_ASICREV_BCM5762)
 2258                 limit = 2;
 2259         else if (BGE_IS_5717_PLUS(sc))
 2260                 limit = 4;
 2261         else
 2262                 limit = 1;
 2263         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
 2264         for (i = 0; i < limit; i++) {
 2265                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
 2266                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
 2267                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
 2268                 vrcb += sizeof(struct bge_rcb);
 2269         }
 2270 
 2271         /* Configure send ring RCB 0 (we use only the first ring) */
 2272         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
 2273         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
 2274         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
 2275         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
 2276         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
 2277             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
 2278             sc->bge_asicrev == BGE_ASICREV_BCM5720)
 2279                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
 2280         else
 2281                 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
 2282                     BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
 2283         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
 2284             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
 2285 
 2286         /*
 2287          * Disable all receive return rings by setting the
 2288          * 'ring diabled' bit in the flags field of all the receive
 2289          * return ring control blocks, located in NIC memory.
 2290          */
 2291         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
 2292             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
 2293             sc->bge_asicrev == BGE_ASICREV_BCM5720) {
 2294                 /* Should be 17, use 16 until we get an SRAM map. */
 2295                 limit = 16;
 2296         } else if (!BGE_IS_5705_PLUS(sc))
 2297                 limit = BGE_RX_RINGS_MAX;
 2298         else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
 2299             sc->bge_asicrev == BGE_ASICREV_BCM5762 ||
 2300             BGE_IS_57765_PLUS(sc))
 2301                 limit = 4;
 2302         else
 2303                 limit = 1;
 2304         /* Disable all receive return rings. */
 2305         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
 2306         for (i = 0; i < limit; i++) {
 2307                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
 2308                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
 2309                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
 2310                     BGE_RCB_FLAG_RING_DISABLED);
 2311                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
 2312                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
 2313                     (i * (sizeof(uint64_t))), 0);
 2314                 vrcb += sizeof(struct bge_rcb);
 2315         }
 2316 
 2317         /*
 2318          * Set up receive return ring 0.  Note that the NIC address
 2319          * for RX return rings is 0x0.  The return rings live entirely
 2320          * within the host, so the nicaddr field in the RCB isn't used.
 2321          */
 2322         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
 2323         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
 2324         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
 2325         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
 2326         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
 2327         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
 2328             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
 2329 
 2330         /* Set random backoff seed for TX */
 2331         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
 2332             (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
 2333             IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
 2334             IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) &
 2335             BGE_TX_BACKOFF_SEED_MASK);
 2336 
 2337         /* Set inter-packet gap */
 2338         val = 0x2620;
 2339         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
 2340             sc->bge_asicrev == BGE_ASICREV_BCM5762)
 2341                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
 2342                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
 2343         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
 2344 
 2345         /*
 2346          * Specify which ring to use for packets that don't match
 2347          * any RX rules.
 2348          */
 2349         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
 2350 
 2351         /*
 2352          * Configure number of RX lists. One interrupt distribution
 2353          * list, sixteen active lists, one bad frames class.
 2354          */
 2355         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
 2356 
 2357         /* Inialize RX list placement stats mask. */
 2358         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
 2359         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
 2360 
 2361         /* Disable host coalescing until we get it set up */
 2362         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
 2363 
 2364         /* Poll to make sure it's shut down. */
 2365         for (i = 0; i < BGE_TIMEOUT; i++) {
 2366                 DELAY(10);
 2367                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
 2368                         break;
 2369         }
 2370 
 2371         if (i == BGE_TIMEOUT) {
 2372                 device_printf(sc->bge_dev,
 2373                     "host coalescing engine failed to idle\n");
 2374                 return (ENXIO);
 2375         }
 2376 
 2377         /* Set up host coalescing defaults */
 2378         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
 2379         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
 2380         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
 2381         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
 2382         if (!(BGE_IS_5705_PLUS(sc))) {
 2383                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
 2384                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
 2385         }
 2386         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
 2387         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
 2388 
 2389         /* Set up address of statistics block */
 2390         if (!(BGE_IS_5705_PLUS(sc))) {
 2391                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
 2392                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
 2393                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
 2394                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
 2395                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
 2396                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
 2397                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
 2398         }
 2399 
 2400         /* Set up address of status block */
 2401         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
 2402             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
 2403         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
 2404             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
 2405 
 2406         /* Set up status block size. */
 2407         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
 2408             sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
 2409                 val = BGE_STATBLKSZ_FULL;
 2410                 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
 2411         } else {
 2412                 val = BGE_STATBLKSZ_32BYTE;
 2413                 bzero(sc->bge_ldata.bge_status_block, 32);
 2414         }
 2415         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
 2416             sc->bge_cdata.bge_status_map,
 2417             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 2418 
 2419         /* Turn on host coalescing state machine */
 2420         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
 2421 
 2422         /* Turn on RX BD completion state machine and enable attentions */
 2423         CSR_WRITE_4(sc, BGE_RBDC_MODE,
 2424             BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
 2425 
 2426         /* Turn on RX list placement state machine */
 2427         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
 2428 
 2429         /* Turn on RX list selector state machine. */
 2430         if (!(BGE_IS_5705_PLUS(sc)))
 2431                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
 2432 
 2433         /* Turn on DMA, clear stats. */
 2434         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
 2435             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
 2436             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
 2437             BGE_MACMODE_FRMHDR_DMA_ENB;
 2438 
 2439         if (sc->bge_flags & BGE_FLAG_TBI)
 2440                 val |= BGE_PORTMODE_TBI;
 2441         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
 2442                 val |= BGE_PORTMODE_GMII;
 2443         else
 2444                 val |= BGE_PORTMODE_MII;
 2445 
 2446         /* Allow APE to send/receive frames. */
 2447         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
 2448                 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
 2449 
 2450         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
 2451         DELAY(40);
 2452 
 2453         /* Set misc. local control, enable interrupts on attentions */
 2454         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
 2455 
 2456 #ifdef notdef
 2457         /* Assert GPIO pins for PHY reset */
 2458         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
 2459             BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
 2460         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
 2461             BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
 2462 #endif
 2463 
 2464         /* Turn on DMA completion state machine */
 2465         if (!(BGE_IS_5705_PLUS(sc)))
 2466                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
 2467 
 2468         val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
 2469 
 2470         /* Enable host coalescing bug fix. */
 2471         if (BGE_IS_5755_PLUS(sc))
 2472                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
 2473 
 2474         /* Request larger DMA burst size to get better performance. */
 2475         if (sc->bge_asicrev == BGE_ASICREV_BCM5785)
 2476                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
 2477 
 2478         /* Turn on write DMA state machine */
 2479         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
 2480         DELAY(40);
 2481 
 2482         /* Turn on read DMA state machine */
 2483         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
 2484 
 2485         if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
 2486                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
 2487 
 2488         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
 2489             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
 2490             sc->bge_asicrev == BGE_ASICREV_BCM57780)
 2491                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
 2492                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
 2493                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
 2494         if (sc->bge_flags & BGE_FLAG_PCIE)
 2495                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
 2496         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
 2497                 val |= BGE_RDMAMODE_TSO4_ENABLE;
 2498                 if (sc->bge_flags & BGE_FLAG_TSO3 ||
 2499                     sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
 2500                     sc->bge_asicrev == BGE_ASICREV_BCM57780)
 2501                         val |= BGE_RDMAMODE_TSO6_ENABLE;
 2502         }
 2503 
 2504         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
 2505             sc->bge_asicrev == BGE_ASICREV_BCM5762) {
 2506                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
 2507                         BGE_RDMAMODE_H2BNC_VLAN_DET;
 2508                 /*
 2509                  * Allow multiple outstanding read requests from
 2510                  * non-LSO read DMA engine.
 2511                  */
 2512                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
 2513         }
 2514 
 2515         if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
 2516             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
 2517             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
 2518             sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
 2519             BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) {
 2520                 if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
 2521                         rdmareg = BGE_RDMA_RSRVCTRL_REG2;
 2522                 else
 2523                         rdmareg = BGE_RDMA_RSRVCTRL;
 2524                 dmactl = CSR_READ_4(sc, rdmareg);
 2525                 /*
 2526                  * Adjust tx margin to prevent TX data corruption and
 2527                  * fix internal FIFO overflow.
 2528                  */
 2529                 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 ||
 2530                     sc->bge_asicrev == BGE_ASICREV_BCM5762) {
 2531                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
 2532                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
 2533                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
 2534                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
 2535                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
 2536                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
 2537                 }
 2538                 /*
 2539                  * Enable fix for read DMA FIFO overruns.
 2540                  * The fix is to limit the number of RX BDs
 2541                  * the hardware would fetch at a fime.
 2542                  */
 2543                 CSR_WRITE_4(sc, rdmareg, dmactl |
 2544                     BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
 2545         }
 2546 
 2547         if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
 2548                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
 2549                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
 2550                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
 2551                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
 2552         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
 2553                 /*
 2554                  * Allow 4KB burst length reads for non-LSO frames.
 2555                  * Enable 512B burst length reads for buffer descriptors.
 2556                  */
 2557                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
 2558                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
 2559                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
 2560                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
 2561         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) {
 2562                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2,
 2563                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |
 2564                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
 2565                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
 2566         }
 2567 
 2568         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
 2569         DELAY(40);
 2570 
 2571         if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
 2572                 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) {
 2573                         val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);
 2574                         if ((val & 0xFFFF) > BGE_FRAMELEN)
 2575                                 break;
 2576                         if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN)
 2577                                 break;
 2578                 }
 2579                 if (i != BGE_NUM_RDMA_CHANNELS / 2) {
 2580                         val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
 2581                         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
 2582                                 val |= BGE_RDMA_TX_LENGTH_WA_5719;
 2583                         else
 2584                                 val |= BGE_RDMA_TX_LENGTH_WA_5720;
 2585                         CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
 2586                 }
 2587         }
 2588 
 2589         /* Turn on RX data completion state machine */
 2590         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
 2591 
 2592         /* Turn on RX BD initiator state machine */
 2593         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
 2594 
 2595         /* Turn on RX data and RX BD initiator state machine */
 2596         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
 2597 
 2598         /* Turn on Mbuf cluster free state machine */
 2599         if (!(BGE_IS_5705_PLUS(sc)))
 2600                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
 2601 
 2602         /* Turn on send BD completion state machine */
 2603         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
 2604 
 2605         /* Turn on send data completion state machine */
 2606         val = BGE_SDCMODE_ENABLE;
 2607         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
 2608                 val |= BGE_SDCMODE_CDELAY;
 2609         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
 2610 
 2611         /* Turn on send data initiator state machine */
 2612         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
 2613                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
 2614                     BGE_SDIMODE_HW_LSO_PRE_DMA);
 2615         else
 2616                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
 2617 
 2618         /* Turn on send BD initiator state machine */
 2619         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
 2620 
 2621         /* Turn on send BD selector state machine */
 2622         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
 2623 
 2624         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
 2625         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
 2626             BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
 2627 
 2628         /* ack/clear link change events */
 2629         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
 2630             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
 2631             BGE_MACSTAT_LINK_CHANGED);
 2632         CSR_WRITE_4(sc, BGE_MI_STS, 0);
 2633 
 2634         /*
 2635          * Enable attention when the link has changed state for
 2636          * devices that use auto polling.
 2637          */
 2638         if (sc->bge_flags & BGE_FLAG_TBI) {
 2639                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
 2640         } else {
 2641                 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
 2642                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
 2643                         DELAY(80);
 2644                 }
 2645                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
 2646                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
 2647                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
 2648                             BGE_EVTENB_MI_INTERRUPT);
 2649         }
 2650 
 2651         /*
 2652          * Clear any pending link state attention.
 2653          * Otherwise some link state change events may be lost until attention
 2654          * is cleared by bge_intr() -> bge_link_upd() sequence.
 2655          * It's not necessary on newer BCM chips - perhaps enabling link
 2656          * state change attentions implies clearing pending attention.
 2657          */
 2658         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
 2659             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
 2660             BGE_MACSTAT_LINK_CHANGED);
 2661 
 2662         /* Enable link state change attentions. */
 2663         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
 2664 
 2665         return (0);
 2666 }
 2667 
 2668 static const struct bge_revision *
 2669 bge_lookup_rev(uint32_t chipid)
 2670 {
 2671         const struct bge_revision *br;
 2672 
 2673         for (br = bge_revisions; br->br_name != NULL; br++) {
 2674                 if (br->br_chipid == chipid)
 2675                         return (br);
 2676         }
 2677 
 2678         for (br = bge_majorrevs; br->br_name != NULL; br++) {
 2679                 if (br->br_chipid == BGE_ASICREV(chipid))
 2680                         return (br);
 2681         }
 2682 
 2683         return (NULL);
 2684 }
 2685 
 2686 static const struct bge_vendor *
 2687 bge_lookup_vendor(uint16_t vid)
 2688 {
 2689         const struct bge_vendor *v;
 2690 
 2691         for (v = bge_vendors; v->v_name != NULL; v++)
 2692                 if (v->v_id == vid)
 2693                         return (v);
 2694 
 2695         return (NULL);
 2696 }
 2697 
 2698 static uint32_t
 2699 bge_chipid(device_t dev)
 2700 {
 2701         uint32_t id;
 2702 
 2703         id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
 2704             BGE_PCIMISCCTL_ASICREV_SHIFT;
 2705         if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
 2706                 /*
 2707                  * Find the ASCI revision.  Different chips use different
 2708                  * registers.
 2709                  */
 2710                 switch (pci_get_device(dev)) {
 2711                 case BCOM_DEVICEID_BCM5717C:
 2712                         /* 5717 C0 seems to belong to 5720 line. */
 2713                         id = BGE_CHIPID_BCM5720_A0;
 2714                         break;
 2715                 case BCOM_DEVICEID_BCM5717:
 2716                 case BCOM_DEVICEID_BCM5718:
 2717                 case BCOM_DEVICEID_BCM5719:
 2718                 case BCOM_DEVICEID_BCM5720:
 2719                 case BCOM_DEVICEID_BCM5725:
 2720                 case BCOM_DEVICEID_BCM5727:
 2721                 case BCOM_DEVICEID_BCM5762:
 2722                 case BCOM_DEVICEID_BCM57764:
 2723                 case BCOM_DEVICEID_BCM57767:
 2724                 case BCOM_DEVICEID_BCM57787:
 2725                         id = pci_read_config(dev,
 2726                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
 2727                         break;
 2728                 case BCOM_DEVICEID_BCM57761:
 2729                 case BCOM_DEVICEID_BCM57762:
 2730                 case BCOM_DEVICEID_BCM57765:
 2731                 case BCOM_DEVICEID_BCM57766:
 2732                 case BCOM_DEVICEID_BCM57781:
 2733                 case BCOM_DEVICEID_BCM57782:
 2734                 case BCOM_DEVICEID_BCM57785:
 2735                 case BCOM_DEVICEID_BCM57786:
 2736                 case BCOM_DEVICEID_BCM57791:
 2737                 case BCOM_DEVICEID_BCM57795:
 2738                         id = pci_read_config(dev,
 2739                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
 2740                         break;
 2741                 default:
 2742                         id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
 2743                 }
 2744         }
 2745         return (id);
 2746 }
 2747 
 2748 /*
 2749  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
 2750  * against our list and return its name if we find a match.
 2751  *
 2752  * Note that since the Broadcom controller contains VPD support, we
 2753  * try to get the device name string from the controller itself instead
 2754  * of the compiled-in string. It guarantees we'll always announce the
 2755  * right product name. We fall back to the compiled-in string when
 2756  * VPD is unavailable or corrupt.
 2757  */
 2758 static int
 2759 bge_probe(device_t dev)
 2760 {
 2761         char buf[96];
 2762         char model[64];
 2763         const struct bge_revision *br;
 2764         const char *pname;
 2765         struct bge_softc *sc;
 2766         const struct bge_type *t = bge_devs;
 2767         const struct bge_vendor *v;
 2768         uint32_t id;
 2769         uint16_t did, vid;
 2770 
 2771         sc = device_get_softc(dev);
 2772         sc->bge_dev = dev;
 2773         vid = pci_get_vendor(dev);
 2774         did = pci_get_device(dev);
 2775         while(t->bge_vid != 0) {
 2776                 if ((vid == t->bge_vid) && (did == t->bge_did)) {
 2777                         id = bge_chipid(dev);
 2778                         br = bge_lookup_rev(id);
 2779                         if (bge_has_eaddr(sc) &&
 2780                             pci_get_vpd_ident(dev, &pname) == 0)
 2781                                 snprintf(model, sizeof(model), "%s", pname);
 2782                         else {
 2783                                 v = bge_lookup_vendor(vid);
 2784                                 snprintf(model, sizeof(model), "%s %s",
 2785                                     v != NULL ? v->v_name : "Unknown",
 2786                                     br != NULL ? br->br_name :
 2787                                     "NetXtreme/NetLink Ethernet Controller");
 2788                         }
 2789                         snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x",
 2790                             model, br != NULL ? "" : "unknown ", id);
 2791                         device_set_desc_copy(dev, buf);
 2792                         return (BUS_PROBE_DEFAULT);
 2793                 }
 2794                 t++;
 2795         }
 2796 
 2797         return (ENXIO);
 2798 }
 2799 
 2800 static void
 2801 bge_dma_free(struct bge_softc *sc)
 2802 {
 2803         int i;
 2804 
 2805         /* Destroy DMA maps for RX buffers. */
 2806         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 2807                 if (sc->bge_cdata.bge_rx_std_dmamap[i])
 2808                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
 2809                             sc->bge_cdata.bge_rx_std_dmamap[i]);
 2810         }
 2811         if (sc->bge_cdata.bge_rx_std_sparemap)
 2812                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
 2813                     sc->bge_cdata.bge_rx_std_sparemap);
 2814 
 2815         /* Destroy DMA maps for jumbo RX buffers. */
 2816         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 2817                 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
 2818                         bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
 2819                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
 2820         }
 2821         if (sc->bge_cdata.bge_rx_jumbo_sparemap)
 2822                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
 2823                     sc->bge_cdata.bge_rx_jumbo_sparemap);
 2824 
 2825         /* Destroy DMA maps for TX buffers. */
 2826         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 2827                 if (sc->bge_cdata.bge_tx_dmamap[i])
 2828                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
 2829                             sc->bge_cdata.bge_tx_dmamap[i]);
 2830         }
 2831 
 2832         if (sc->bge_cdata.bge_rx_mtag)
 2833                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
 2834         if (sc->bge_cdata.bge_mtag_jumbo)
 2835                 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo);
 2836         if (sc->bge_cdata.bge_tx_mtag)
 2837                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
 2838 
 2839         /* Destroy standard RX ring. */
 2840         if (sc->bge_ldata.bge_rx_std_ring_paddr)
 2841                 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
 2842                     sc->bge_cdata.bge_rx_std_ring_map);
 2843         if (sc->bge_ldata.bge_rx_std_ring)
 2844                 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
 2845                     sc->bge_ldata.bge_rx_std_ring,
 2846                     sc->bge_cdata.bge_rx_std_ring_map);
 2847 
 2848         if (sc->bge_cdata.bge_rx_std_ring_tag)
 2849                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
 2850 
 2851         /* Destroy jumbo RX ring. */
 2852         if (sc->bge_ldata.bge_rx_jumbo_ring_paddr)
 2853                 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 2854                     sc->bge_cdata.bge_rx_jumbo_ring_map);
 2855 
 2856         if (sc->bge_ldata.bge_rx_jumbo_ring)
 2857                 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 2858                     sc->bge_ldata.bge_rx_jumbo_ring,
 2859                     sc->bge_cdata.bge_rx_jumbo_ring_map);
 2860 
 2861         if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
 2862                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
 2863 
 2864         /* Destroy RX return ring. */
 2865         if (sc->bge_ldata.bge_rx_return_ring_paddr)
 2866                 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
 2867                     sc->bge_cdata.bge_rx_return_ring_map);
 2868 
 2869         if (sc->bge_ldata.bge_rx_return_ring)
 2870                 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
 2871                     sc->bge_ldata.bge_rx_return_ring,
 2872                     sc->bge_cdata.bge_rx_return_ring_map);
 2873 
 2874         if (sc->bge_cdata.bge_rx_return_ring_tag)
 2875                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
 2876 
 2877         /* Destroy TX ring. */
 2878         if (sc->bge_ldata.bge_tx_ring_paddr)
 2879                 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
 2880                     sc->bge_cdata.bge_tx_ring_map);
 2881 
 2882         if (sc->bge_ldata.bge_tx_ring)
 2883                 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
 2884                     sc->bge_ldata.bge_tx_ring,
 2885                     sc->bge_cdata.bge_tx_ring_map);
 2886 
 2887         if (sc->bge_cdata.bge_tx_ring_tag)
 2888                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
 2889 
 2890         /* Destroy status block. */
 2891         if (sc->bge_ldata.bge_status_block_paddr)
 2892                 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
 2893                     sc->bge_cdata.bge_status_map);
 2894 
 2895         if (sc->bge_ldata.bge_status_block)
 2896                 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
 2897                     sc->bge_ldata.bge_status_block,
 2898                     sc->bge_cdata.bge_status_map);
 2899 
 2900         if (sc->bge_cdata.bge_status_tag)
 2901                 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
 2902 
 2903         /* Destroy statistics block. */
 2904         if (sc->bge_ldata.bge_stats_paddr)
 2905                 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
 2906                     sc->bge_cdata.bge_stats_map);
 2907 
 2908         if (sc->bge_ldata.bge_stats)
 2909                 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
 2910                     sc->bge_ldata.bge_stats,
 2911                     sc->bge_cdata.bge_stats_map);
 2912 
 2913         if (sc->bge_cdata.bge_stats_tag)
 2914                 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
 2915 
 2916         if (sc->bge_cdata.bge_buffer_tag)
 2917                 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag);
 2918 
 2919         /* Destroy the parent tag. */
 2920         if (sc->bge_cdata.bge_parent_tag)
 2921                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
 2922 }
 2923 
 2924 static int
 2925 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment,
 2926     bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
 2927     bus_addr_t *paddr, const char *msg)
 2928 {
 2929         struct bge_dmamap_arg ctx;
 2930         int error;
 2931 
 2932         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
 2933             alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
 2934             NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
 2935         if (error != 0) {
 2936                 device_printf(sc->bge_dev,
 2937                     "could not create %s dma tag\n", msg);
 2938                 return (ENOMEM);
 2939         }
 2940         /* Allocate DMA'able memory for ring. */
 2941         error = bus_dmamem_alloc(*tag, (void **)ring,
 2942             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
 2943         if (error != 0) {
 2944                 device_printf(sc->bge_dev,
 2945                     "could not allocate DMA'able memory for %s\n", msg);
 2946                 return (ENOMEM);
 2947         }
 2948         /* Load the address of the ring. */
 2949         ctx.bge_busaddr = 0;
 2950         error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr,
 2951             &ctx, BUS_DMA_NOWAIT);
 2952         if (error != 0) {
 2953                 device_printf(sc->bge_dev,
 2954                     "could not load DMA'able memory for %s\n", msg);
 2955                 return (ENOMEM);
 2956         }
 2957         *paddr = ctx.bge_busaddr;
 2958         return (0);
 2959 }
 2960 
 2961 static int
 2962 bge_dma_alloc(struct bge_softc *sc)
 2963 {
 2964         bus_addr_t lowaddr;
 2965         bus_size_t rxmaxsegsz, sbsz, txsegsz, txmaxsegsz;
 2966         int i, error;
 2967 
 2968         lowaddr = BUS_SPACE_MAXADDR;
 2969         if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
 2970                 lowaddr = BGE_DMA_MAXADDR;
 2971         /*
 2972          * Allocate the parent bus DMA tag appropriate for PCI.
 2973          */
 2974         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
 2975             1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
 2976             NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
 2977             0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
 2978         if (error != 0) {
 2979                 device_printf(sc->bge_dev,
 2980                     "could not allocate parent dma tag\n");
 2981                 return (ENOMEM);
 2982         }
 2983 
 2984         /* Create tag for standard RX ring. */
 2985         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ,
 2986             &sc->bge_cdata.bge_rx_std_ring_tag,
 2987             (uint8_t **)&sc->bge_ldata.bge_rx_std_ring,
 2988             &sc->bge_cdata.bge_rx_std_ring_map,
 2989             &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring");
 2990         if (error)
 2991                 return (error);
 2992 
 2993         /* Create tag for RX return ring. */
 2994         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc),
 2995             &sc->bge_cdata.bge_rx_return_ring_tag,
 2996             (uint8_t **)&sc->bge_ldata.bge_rx_return_ring,
 2997             &sc->bge_cdata.bge_rx_return_ring_map,
 2998             &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring");
 2999         if (error)
 3000                 return (error);
 3001 
 3002         /* Create tag for TX ring. */
 3003         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ,
 3004             &sc->bge_cdata.bge_tx_ring_tag,
 3005             (uint8_t **)&sc->bge_ldata.bge_tx_ring,
 3006             &sc->bge_cdata.bge_tx_ring_map,
 3007             &sc->bge_ldata.bge_tx_ring_paddr, "TX ring");
 3008         if (error)
 3009                 return (error);
 3010 
 3011         /*
 3012          * Create tag for status block.
 3013          * Because we only use single Tx/Rx/Rx return ring, use
 3014          * minimum status block size except BCM5700 AX/BX which
 3015          * seems to want to see full status block size regardless
 3016          * of configured number of ring.
 3017          */
 3018         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
 3019             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
 3020                 sbsz = BGE_STATUS_BLK_SZ;
 3021         else
 3022                 sbsz = 32;
 3023         error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz,
 3024             &sc->bge_cdata.bge_status_tag,
 3025             (uint8_t **)&sc->bge_ldata.bge_status_block,
 3026             &sc->bge_cdata.bge_status_map,
 3027             &sc->bge_ldata.bge_status_block_paddr, "status block");
 3028         if (error)
 3029                 return (error);
 3030 
 3031         /* Create tag for statistics block. */
 3032         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ,
 3033             &sc->bge_cdata.bge_stats_tag,
 3034             (uint8_t **)&sc->bge_ldata.bge_stats,
 3035             &sc->bge_cdata.bge_stats_map,
 3036             &sc->bge_ldata.bge_stats_paddr, "statistics block");
 3037         if (error)
 3038                 return (error);
 3039 
 3040         /* Create tag for jumbo RX ring. */
 3041         if (BGE_IS_JUMBO_CAPABLE(sc)) {
 3042                 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ,
 3043                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
 3044                     (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring,
 3045                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
 3046                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring");
 3047                 if (error)
 3048                         return (error);
 3049         }
 3050 
 3051         /* Create parent tag for buffers. */
 3052         if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) {
 3053                 /*
 3054                  * XXX
 3055                  * watchdog timeout issue was observed on BCM5704 which
 3056                  * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge).
 3057                  * Both limiting DMA address space to 32bits and flushing
 3058                  * mailbox write seem to address the issue.
 3059                  */
 3060                 if (sc->bge_pcixcap != 0)
 3061                         lowaddr = BUS_SPACE_MAXADDR_32BIT;
 3062         }
 3063         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 1, 0, lowaddr,
 3064             BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0,
 3065             BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
 3066             &sc->bge_cdata.bge_buffer_tag);
 3067         if (error != 0) {
 3068                 device_printf(sc->bge_dev,
 3069                     "could not allocate buffer dma tag\n");
 3070                 return (ENOMEM);
 3071         }
 3072         /* Create tag for Tx mbufs. */
 3073         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
 3074                 txsegsz = BGE_TSOSEG_SZ;
 3075                 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
 3076         } else {
 3077                 txsegsz = MCLBYTES;
 3078                 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
 3079         }
 3080         error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
 3081             0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
 3082             txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
 3083             &sc->bge_cdata.bge_tx_mtag);
 3084 
 3085         if (error) {
 3086                 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
 3087                 return (ENOMEM);
 3088         }
 3089 
 3090         /* Create tag for Rx mbufs. */
 3091         if (sc->bge_flags & BGE_FLAG_JUMBO_STD)
 3092                 rxmaxsegsz = MJUM9BYTES;
 3093         else
 3094                 rxmaxsegsz = MCLBYTES;
 3095         error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0,
 3096             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1,
 3097             rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
 3098 
 3099         if (error) {
 3100                 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
 3101                 return (ENOMEM);
 3102         }
 3103 
 3104         /* Create DMA maps for RX buffers. */
 3105         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
 3106             &sc->bge_cdata.bge_rx_std_sparemap);
 3107         if (error) {
 3108                 device_printf(sc->bge_dev,
 3109                     "can't create spare DMA map for RX\n");
 3110                 return (ENOMEM);
 3111         }
 3112         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 3113                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
 3114                             &sc->bge_cdata.bge_rx_std_dmamap[i]);
 3115                 if (error) {
 3116                         device_printf(sc->bge_dev,
 3117                             "can't create DMA map for RX\n");
 3118                         return (ENOMEM);
 3119                 }
 3120         }
 3121 
 3122         /* Create DMA maps for TX buffers. */
 3123         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 3124                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
 3125                             &sc->bge_cdata.bge_tx_dmamap[i]);
 3126                 if (error) {
 3127                         device_printf(sc->bge_dev,
 3128                             "can't create DMA map for TX\n");
 3129                         return (ENOMEM);
 3130                 }
 3131         }
 3132 
 3133         /* Create tags for jumbo RX buffers. */
 3134         if (BGE_IS_JUMBO_CAPABLE(sc)) {
 3135                 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag,
 3136                     1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
 3137                     NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
 3138                     0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
 3139                 if (error) {
 3140                         device_printf(sc->bge_dev,
 3141                             "could not allocate jumbo dma tag\n");
 3142                         return (ENOMEM);
 3143                 }
 3144                 /* Create DMA maps for jumbo RX buffers. */
 3145                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
 3146                     0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
 3147                 if (error) {
 3148                         device_printf(sc->bge_dev,
 3149                             "can't create spare DMA map for jumbo RX\n");
 3150                         return (ENOMEM);
 3151                 }
 3152                 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 3153                         error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
 3154                                     0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
 3155                         if (error) {
 3156                                 device_printf(sc->bge_dev,
 3157                                     "can't create DMA map for jumbo RX\n");
 3158                                 return (ENOMEM);
 3159                         }
 3160                 }
 3161         }
 3162 
 3163         return (0);
 3164 }
 3165 
 3166 /*
 3167  * Return true if this device has more than one port.
 3168  */
 3169 static int
 3170 bge_has_multiple_ports(struct bge_softc *sc)
 3171 {
 3172         device_t dev = sc->bge_dev;
 3173         u_int b, d, f, fscan, s;
 3174 
 3175         d = pci_get_domain(dev);
 3176         b = pci_get_bus(dev);
 3177         s = pci_get_slot(dev);
 3178         f = pci_get_function(dev);
 3179         for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
 3180                 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
 3181                         return (1);
 3182         return (0);
 3183 }
 3184 
 3185 /*
 3186  * Return true if MSI can be used with this device.
 3187  */
 3188 static int
 3189 bge_can_use_msi(struct bge_softc *sc)
 3190 {
 3191         int can_use_msi = 0;
 3192 
 3193         if (sc->bge_msi == 0)
 3194                 return (0);
 3195 
 3196         /* Disable MSI for polling(4). */
 3197 #ifdef DEVICE_POLLING
 3198         return (0);
 3199 #endif
 3200         switch (sc->bge_asicrev) {
 3201         case BGE_ASICREV_BCM5714_A0:
 3202         case BGE_ASICREV_BCM5714:
 3203                 /*
 3204                  * Apparently, MSI doesn't work when these chips are
 3205                  * configured in single-port mode.
 3206                  */
 3207                 if (bge_has_multiple_ports(sc))
 3208                         can_use_msi = 1;
 3209                 break;
 3210         case BGE_ASICREV_BCM5750:
 3211                 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
 3212                     sc->bge_chiprev != BGE_CHIPREV_5750_BX)
 3213                         can_use_msi = 1;
 3214                 break;
 3215         case BGE_ASICREV_BCM5784:
 3216                 /*
 3217                  * Prevent infinite "watchdog timeout" errors
 3218                  * in some MacBook Pro and make it work out-of-the-box.
 3219                  */
 3220                 if (sc->bge_chiprev == BGE_CHIPREV_5784_AX)
 3221                         break;
 3222                 /* FALLTHROUGH */
 3223         default:
 3224                 if (BGE_IS_575X_PLUS(sc))
 3225                         can_use_msi = 1;
 3226         }
 3227         return (can_use_msi);
 3228 }
 3229 
 3230 static int
 3231 bge_mbox_reorder(struct bge_softc *sc)
 3232 {
 3233         /* Lists of PCI bridges that are known to reorder mailbox writes. */
 3234         static const struct mbox_reorder {
 3235                 const uint16_t vendor;
 3236                 const uint16_t device;
 3237                 const char *desc;
 3238         } mbox_reorder_lists[] = {
 3239                 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" },
 3240         };
 3241         devclass_t pci, pcib;
 3242         device_t bus, dev;
 3243         int i;
 3244 
 3245         pci = devclass_find("pci");
 3246         pcib = devclass_find("pcib");
 3247         dev = sc->bge_dev;
 3248         bus = device_get_parent(dev);
 3249         for (;;) {
 3250                 dev = device_get_parent(bus);
 3251                 bus = device_get_parent(dev);
 3252                 if (device_get_devclass(dev) != pcib)
 3253                         break;
 3254                 for (i = 0; i < nitems(mbox_reorder_lists); i++) {
 3255                         if (pci_get_vendor(dev) ==
 3256                             mbox_reorder_lists[i].vendor &&
 3257                             pci_get_device(dev) ==
 3258                             mbox_reorder_lists[i].device) {
 3259                                 device_printf(sc->bge_dev,
 3260                                     "enabling MBOX workaround for %s\n",
 3261                                     mbox_reorder_lists[i].desc);
 3262                                 return (1);
 3263                         }
 3264                 }
 3265                 if (device_get_devclass(bus) != pci)
 3266                         break;
 3267         }
 3268         return (0);
 3269 }
 3270 
 3271 static void
 3272 bge_devinfo(struct bge_softc *sc)
 3273 {
 3274         uint32_t cfg, clk;
 3275 
 3276         device_printf(sc->bge_dev,
 3277             "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ",
 3278             sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev);
 3279         if (sc->bge_flags & BGE_FLAG_PCIE)
 3280                 printf("PCI-E\n");
 3281         else if (sc->bge_flags & BGE_FLAG_PCIX) {
 3282                 printf("PCI-X ");
 3283                 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
 3284                 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE)
 3285                         clk = 133;
 3286                 else {
 3287                         clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
 3288                         switch (clk) {
 3289                         case 0:
 3290                                 clk = 33;
 3291                                 break;
 3292                         case 2:
 3293                                 clk = 50;
 3294                                 break;
 3295                         case 4:
 3296                                 clk = 66;
 3297                                 break;
 3298                         case 6:
 3299                                 clk = 100;
 3300                                 break;
 3301                         case 7:
 3302                                 clk = 133;
 3303                                 break;
 3304                         }
 3305                 }
 3306                 printf("%u MHz\n", clk);
 3307         } else {
 3308                 if (sc->bge_pcixcap != 0)
 3309                         printf("PCI on PCI-X ");
 3310                 else
 3311                         printf("PCI ");
 3312                 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
 3313                 if (cfg & BGE_PCISTATE_PCI_BUSSPEED)
 3314                         clk = 66;
 3315                 else
 3316                         clk = 33;
 3317                 if (cfg & BGE_PCISTATE_32BIT_BUS)
 3318                         printf("%u MHz; 32bit\n", clk);
 3319                 else
 3320                         printf("%u MHz; 64bit\n", clk);
 3321         }
 3322 }
 3323 
 3324 static int
 3325 bge_attach(device_t dev)
 3326 {
 3327         if_t ifp;
 3328         struct bge_softc *sc;
 3329         uint32_t hwcfg = 0, misccfg, pcistate;
 3330         u_char eaddr[ETHER_ADDR_LEN];
 3331         int capmask, error, reg, rid, trys;
 3332 
 3333         sc = device_get_softc(dev);
 3334         sc->bge_dev = dev;
 3335 
 3336         BGE_LOCK_INIT(sc, device_get_nameunit(dev));
 3337         TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
 3338         callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
 3339 
 3340         pci_enable_busmaster(dev);
 3341 
 3342         /*
 3343          * Allocate control/status registers.
 3344          */
 3345         rid = PCIR_BAR(0);
 3346         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 3347             RF_ACTIVE);
 3348 
 3349         if (sc->bge_res == NULL) {
 3350                 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n");
 3351                 error = ENXIO;
 3352                 goto fail;
 3353         }
 3354 
 3355         /* Save various chip information. */
 3356         sc->bge_func_addr = pci_get_function(dev);
 3357         sc->bge_chipid = bge_chipid(dev);
 3358         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
 3359         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
 3360 
 3361         /* Set default PHY address. */
 3362         sc->bge_phy_addr = 1;
 3363          /*
 3364           * PHY address mapping for various devices.
 3365           *
 3366           *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
 3367           * ---------+-------+-------+-------+-------+
 3368           * BCM57XX  |   1   |   X   |   X   |   X   |
 3369           * BCM5704  |   1   |   X   |   1   |   X   |
 3370           * BCM5717  |   1   |   8   |   2   |   9   |
 3371           * BCM5719  |   1   |   8   |   2   |   9   |
 3372           * BCM5720  |   1   |   8   |   2   |   9   |
 3373           *
 3374           *          | F2 Cu | F2 Sr | F3 Cu | F3 Sr |
 3375           * ---------+-------+-------+-------+-------+
 3376           * BCM57XX  |   X   |   X   |   X   |   X   |
 3377           * BCM5704  |   X   |   X   |   X   |   X   |
 3378           * BCM5717  |   X   |   X   |   X   |   X   |
 3379           * BCM5719  |   3   |   10  |   4   |   11  |
 3380           * BCM5720  |   X   |   X   |   X   |   X   |
 3381           *
 3382           * Other addresses may respond but they are not
 3383           * IEEE compliant PHYs and should be ignored.
 3384           */
 3385         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
 3386             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
 3387             sc->bge_asicrev == BGE_ASICREV_BCM5720) {
 3388                 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) {
 3389                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
 3390                             BGE_SGDIGSTS_IS_SERDES)
 3391                                 sc->bge_phy_addr = sc->bge_func_addr + 8;
 3392                         else
 3393                                 sc->bge_phy_addr = sc->bge_func_addr + 1;
 3394                 } else {
 3395                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
 3396                             BGE_CPMU_PHY_STRAP_IS_SERDES)
 3397                                 sc->bge_phy_addr = sc->bge_func_addr + 8;
 3398                         else
 3399                                 sc->bge_phy_addr = sc->bge_func_addr + 1;
 3400                 }
 3401         }
 3402 
 3403         if (bge_has_eaddr(sc))
 3404                 sc->bge_flags |= BGE_FLAG_EADDR;
 3405 
 3406         /* Save chipset family. */
 3407         switch (sc->bge_asicrev) {
 3408         case BGE_ASICREV_BCM5762:
 3409         case BGE_ASICREV_BCM57765:
 3410         case BGE_ASICREV_BCM57766:
 3411                 sc->bge_flags |= BGE_FLAG_57765_PLUS;
 3412                 /* FALLTHROUGH */
 3413         case BGE_ASICREV_BCM5717:
 3414         case BGE_ASICREV_BCM5719:
 3415         case BGE_ASICREV_BCM5720:
 3416                 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
 3417                     BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
 3418                     BGE_FLAG_JUMBO_FRAME;
 3419                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
 3420                     sc->bge_asicrev == BGE_ASICREV_BCM5720) {
 3421                         /*
 3422                          * Enable work around for DMA engine miscalculation
 3423                          * of TXMBUF available space.
 3424                          */
 3425                         sc->bge_flags |= BGE_FLAG_RDMA_BUG;
 3426                         if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
 3427                             sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
 3428                                 /* Jumbo frame on BCM5719 A0 does not work. */
 3429                                 sc->bge_flags &= ~BGE_FLAG_JUMBO;
 3430                         }
 3431                 }
 3432                 break;
 3433         case BGE_ASICREV_BCM5755:
 3434         case BGE_ASICREV_BCM5761:
 3435         case BGE_ASICREV_BCM5784:
 3436         case BGE_ASICREV_BCM5785:
 3437         case BGE_ASICREV_BCM5787:
 3438         case BGE_ASICREV_BCM57780:
 3439                 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
 3440                     BGE_FLAG_5705_PLUS;
 3441                 break;
 3442         case BGE_ASICREV_BCM5700:
 3443         case BGE_ASICREV_BCM5701:
 3444         case BGE_ASICREV_BCM5703:
 3445         case BGE_ASICREV_BCM5704:
 3446                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
 3447                 break;
 3448         case BGE_ASICREV_BCM5714_A0:
 3449         case BGE_ASICREV_BCM5780:
 3450         case BGE_ASICREV_BCM5714:
 3451                 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD;
 3452                 /* FALLTHROUGH */
 3453         case BGE_ASICREV_BCM5750:
 3454         case BGE_ASICREV_BCM5752:
 3455         case BGE_ASICREV_BCM5906:
 3456                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
 3457                 /* FALLTHROUGH */
 3458         case BGE_ASICREV_BCM5705:
 3459                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
 3460                 break;
 3461         }
 3462 
 3463         /* Identify chips with APE processor. */
 3464         switch (sc->bge_asicrev) {
 3465         case BGE_ASICREV_BCM5717:
 3466         case BGE_ASICREV_BCM5719:
 3467         case BGE_ASICREV_BCM5720:
 3468         case BGE_ASICREV_BCM5761:
 3469         case BGE_ASICREV_BCM5762:
 3470                 sc->bge_flags |= BGE_FLAG_APE;
 3471                 break;
 3472         }
 3473 
 3474         /* Chips with APE need BAR2 access for APE registers/memory. */
 3475         if ((sc->bge_flags & BGE_FLAG_APE) != 0) {
 3476                 rid = PCIR_BAR(2);
 3477                 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 3478                     RF_ACTIVE);
 3479                 if (sc->bge_res2 == NULL) {
 3480                         device_printf (sc->bge_dev,
 3481                             "couldn't map BAR2 memory\n");
 3482                         error = ENXIO;
 3483                         goto fail;
 3484                 }
 3485 
 3486                 /* Enable APE register/memory access by host driver. */
 3487                 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
 3488                 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
 3489                     BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
 3490                     BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
 3491                 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4);
 3492 
 3493                 bge_ape_lock_init(sc);
 3494                 bge_ape_read_fw_ver(sc);
 3495         }
 3496 
 3497         /* Add SYSCTLs, requires the chipset family to be set. */
 3498         bge_add_sysctls(sc);
 3499 
 3500         /* Identify the chips that use an CPMU. */
 3501         if (BGE_IS_5717_PLUS(sc) ||
 3502             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
 3503             sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
 3504             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
 3505             sc->bge_asicrev == BGE_ASICREV_BCM57780)
 3506                 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
 3507         if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
 3508                 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
 3509         else
 3510                 sc->bge_mi_mode = BGE_MIMODE_BASE;
 3511         /* Enable auto polling for BCM570[0-5]. */
 3512         if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
 3513                 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
 3514 
 3515         /*
 3516          * All Broadcom controllers have 4GB boundary DMA bug.
 3517          * Whenever an address crosses a multiple of the 4GB boundary
 3518          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
 3519          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
 3520          * state machine will lockup and cause the device to hang.
 3521          */
 3522         sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
 3523 
 3524         /* BCM5755 or higher and BCM5906 have short DMA bug. */
 3525         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
 3526                 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
 3527 
 3528         /*
 3529          * BCM5719 cannot handle DMA requests for DMA segments that
 3530          * have larger than 4KB in size.  However the maximum DMA
 3531          * segment size created in DMA tag is 4KB for TSO, so we
 3532          * wouldn't encounter the issue here.
 3533          */
 3534         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
 3535                 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG;
 3536 
 3537         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
 3538         if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
 3539                 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
 3540                     misccfg == BGE_MISCCFG_BOARD_ID_5788M)
 3541                         sc->bge_flags |= BGE_FLAG_5788;
 3542         }
 3543 
 3544         capmask = BMSR_DEFCAPMASK;
 3545         if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
 3546             (misccfg == 0x4000 || misccfg == 0x8000)) ||
 3547             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
 3548             pci_get_vendor(dev) == BCOM_VENDORID &&
 3549             (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 ||
 3550             pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 ||
 3551             pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) ||
 3552             (pci_get_vendor(dev) == BCOM_VENDORID &&
 3553             (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F ||
 3554             pci_get_device(dev) == BCOM_DEVICEID_BCM5753F ||
 3555             pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) ||
 3556             pci_get_device(dev) == BCOM_DEVICEID_BCM57790 ||
 3557             pci_get_device(dev) == BCOM_DEVICEID_BCM57791 ||
 3558             pci_get_device(dev) == BCOM_DEVICEID_BCM57795 ||
 3559             sc->bge_asicrev == BGE_ASICREV_BCM5906) {
 3560                 /* These chips are 10/100 only. */
 3561                 capmask &= ~BMSR_EXTSTAT;
 3562                 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
 3563         }
 3564 
 3565         /*
 3566          * Some controllers seem to require a special firmware to use
 3567          * TSO. But the firmware is not available to FreeBSD and Linux
 3568          * claims that the TSO performed by the firmware is slower than
 3569          * hardware based TSO. Moreover the firmware based TSO has one
 3570          * known bug which can't handle TSO if Ethernet header + IP/TCP
 3571          * header is greater than 80 bytes. A workaround for the TSO
 3572          * bug exist but it seems it's too expensive than not using
 3573          * TSO at all. Some hardwares also have the TSO bug so limit
 3574          * the TSO to the controllers that are not affected TSO issues
 3575          * (e.g. 5755 or higher).
 3576          */
 3577         if (BGE_IS_5717_PLUS(sc)) {
 3578                 /* BCM5717 requires different TSO configuration. */
 3579                 sc->bge_flags |= BGE_FLAG_TSO3;
 3580                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
 3581                     sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
 3582                         /* TSO on BCM5719 A0 does not work. */
 3583                         sc->bge_flags &= ~BGE_FLAG_TSO3;
 3584                 }
 3585         } else if (BGE_IS_5755_PLUS(sc)) {
 3586                 /*
 3587                  * BCM5754 and BCM5787 shares the same ASIC id so
 3588                  * explicit device id check is required.
 3589                  * Due to unknown reason TSO does not work on BCM5755M.
 3590                  */
 3591                 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
 3592                     pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
 3593                     pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
 3594                         sc->bge_flags |= BGE_FLAG_TSO;
 3595         }
 3596 
 3597         /*
 3598          * Check if this is a PCI-X or PCI Express device.
 3599          */
 3600         if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
 3601                 /*
 3602                  * Found a PCI Express capabilities register, this
 3603                  * must be a PCI Express device.
 3604                  */
 3605                 sc->bge_flags |= BGE_FLAG_PCIE;
 3606                 sc->bge_expcap = reg;
 3607                 /* Extract supported maximum payload size. */
 3608                 sc->bge_mps = pci_read_config(dev, sc->bge_expcap +
 3609                     PCIER_DEVICE_CAP, 2);
 3610                 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD);
 3611                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
 3612                     sc->bge_asicrev == BGE_ASICREV_BCM5720)
 3613                         sc->bge_expmrq = 2048;
 3614                 else
 3615                         sc->bge_expmrq = 4096;
 3616                 pci_set_max_read_req(dev, sc->bge_expmrq);
 3617         } else {
 3618                 /*
 3619                  * Check if the device is in PCI-X Mode.
 3620                  * (This bit is not valid on PCI Express controllers.)
 3621                  */
 3622                 if (pci_find_cap(dev, PCIY_PCIX, &reg) == 0)
 3623                         sc->bge_pcixcap = reg;
 3624                 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
 3625                     BGE_PCISTATE_PCI_BUSMODE) == 0)
 3626                         sc->bge_flags |= BGE_FLAG_PCIX;
 3627         }
 3628 
 3629         /*
 3630          * The 40bit DMA bug applies to the 5714/5715 controllers and is
 3631          * not actually a MAC controller bug but an issue with the embedded
 3632          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
 3633          */
 3634         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
 3635                 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
 3636         /*
 3637          * Some PCI-X bridges are known to trigger write reordering to
 3638          * the mailbox registers. Typical phenomena is watchdog timeouts
 3639          * caused by out-of-order TX completions.  Enable workaround for
 3640          * PCI-X devices that live behind these bridges.
 3641          * Note, PCI-X controllers can run in PCI mode so we can't use
 3642          * BGE_FLAG_PCIX flag to detect PCI-X controllers.
 3643          */
 3644         if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0)
 3645                 sc->bge_flags |= BGE_FLAG_MBOX_REORDER;
 3646         /*
 3647          * Allocate the interrupt, using MSI if possible.  These devices
 3648          * support 8 MSI messages, but only the first one is used in
 3649          * normal operation.
 3650          */
 3651         rid = 0;
 3652         if (pci_find_cap(sc->bge_dev, PCIY_MSI, &reg) == 0) {
 3653                 sc->bge_msicap = reg;
 3654                 reg = 1;
 3655                 if (bge_can_use_msi(sc) && pci_alloc_msi(dev, &reg) == 0) {
 3656                         rid = 1;
 3657                         sc->bge_flags |= BGE_FLAG_MSI;
 3658                 }
 3659         }
 3660 
 3661         /*
 3662          * All controllers except BCM5700 supports tagged status but
 3663          * we use tagged status only for MSI case on BCM5717. Otherwise
 3664          * MSI on BCM5717 does not work.
 3665          */
 3666 #ifndef DEVICE_POLLING
 3667         if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
 3668                 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
 3669 #endif
 3670 
 3671         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 3672             RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
 3673 
 3674         if (sc->bge_irq == NULL) {
 3675                 device_printf(sc->bge_dev, "couldn't map interrupt\n");
 3676                 error = ENXIO;
 3677                 goto fail;
 3678         }
 3679 
 3680         bge_devinfo(sc);
 3681 
 3682         sc->bge_asf_mode = 0;
 3683         /* No ASF if APE present. */
 3684         if ((sc->bge_flags & BGE_FLAG_APE) == 0) {
 3685                 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
 3686                     BGE_SRAM_DATA_SIG_MAGIC)) {
 3687                         if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
 3688                             BGE_HWCFG_ASF) {
 3689                                 sc->bge_asf_mode |= ASF_ENABLE;
 3690                                 sc->bge_asf_mode |= ASF_STACKUP;
 3691                                 if (BGE_IS_575X_PLUS(sc))
 3692                                         sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
 3693                         }
 3694                 }
 3695         }
 3696 
 3697         bge_stop_fw(sc);
 3698         bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
 3699         if (bge_reset(sc)) {
 3700                 device_printf(sc->bge_dev, "chip reset failed\n");
 3701                 error = ENXIO;
 3702                 goto fail;
 3703         }
 3704 
 3705         bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
 3706         bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
 3707 
 3708         if (bge_chipinit(sc)) {
 3709                 device_printf(sc->bge_dev, "chip initialization failed\n");
 3710                 error = ENXIO;
 3711                 goto fail;
 3712         }
 3713 
 3714         error = bge_get_eaddr(sc, eaddr);
 3715         if (error) {
 3716                 device_printf(sc->bge_dev,
 3717                     "failed to read station address\n");
 3718                 error = ENXIO;
 3719                 goto fail;
 3720         }
 3721 
 3722         /* 5705 limits RX return ring to 512 entries. */
 3723         if (BGE_IS_5717_PLUS(sc))
 3724                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
 3725         else if (BGE_IS_5705_PLUS(sc))
 3726                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
 3727         else
 3728                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
 3729 
 3730         if (bge_dma_alloc(sc)) {
 3731                 device_printf(sc->bge_dev,
 3732                     "failed to allocate DMA resources\n");
 3733                 error = ENXIO;
 3734                 goto fail;
 3735         }
 3736 
 3737         /* Set default tuneable values. */
 3738         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
 3739         sc->bge_rx_coal_ticks = 150;
 3740         sc->bge_tx_coal_ticks = 150;
 3741         sc->bge_rx_max_coal_bds = 10;
 3742         sc->bge_tx_max_coal_bds = 10;
 3743 
 3744         /* Initialize checksum features to use. */
 3745         sc->bge_csum_features = BGE_CSUM_FEATURES;
 3746         if (sc->bge_forced_udpcsum != 0)
 3747                 sc->bge_csum_features |= CSUM_UDP;
 3748 
 3749         /* Set up ifnet structure */
 3750         ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
 3751         if (ifp == NULL) {
 3752                 device_printf(sc->bge_dev, "failed to if_alloc()\n");
 3753                 error = ENXIO;
 3754                 goto fail;
 3755         }
 3756         if_setsoftc(ifp, sc);
 3757         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 3758         if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
 3759         if_setioctlfn(ifp, bge_ioctl);
 3760         if_setstartfn(ifp, bge_start);
 3761         if_setinitfn(ifp, bge_init);
 3762         if_setgetcounterfn(ifp, bge_get_counter);
 3763         if_setsendqlen(ifp, BGE_TX_RING_CNT - 1);
 3764         if_setsendqready(ifp);
 3765         if_sethwassist(ifp, sc->bge_csum_features);
 3766         if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
 3767             IFCAP_VLAN_MTU);
 3768         if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
 3769                 if_sethwassistbits(ifp, CSUM_TSO, 0);
 3770                 if_setcapabilitiesbit(ifp, IFCAP_TSO4 | IFCAP_VLAN_HWTSO, 0);
 3771         }
 3772 #ifdef IFCAP_VLAN_HWCSUM
 3773         if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0);
 3774 #endif
 3775         if_setcapenable(ifp, if_getcapabilities(ifp));
 3776 #ifdef DEVICE_POLLING
 3777         if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
 3778 #endif
 3779 
 3780         /*
 3781          * 5700 B0 chips do not support checksumming correctly due
 3782          * to hardware bugs.
 3783          */
 3784         if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
 3785                 if_setcapabilitiesbit(ifp, 0, IFCAP_HWCSUM);
 3786                 if_setcapenablebit(ifp, 0, IFCAP_HWCSUM);
 3787                 if_sethwassist(ifp, 0);
 3788         }
 3789 
 3790         /*
 3791          * Figure out what sort of media we have by checking the
 3792          * hardware config word in the first 32k of NIC internal memory,
 3793          * or fall back to examining the EEPROM if necessary.
 3794          * Note: on some BCM5700 cards, this value appears to be unset.
 3795          * If that's the case, we have to rely on identifying the NIC
 3796          * by its PCI subsystem ID, as we do below for the SysKonnect
 3797          * SK-9D41.
 3798          */
 3799         if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC)
 3800                 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
 3801         else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
 3802             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
 3803                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
 3804                     sizeof(hwcfg))) {
 3805                         device_printf(sc->bge_dev, "failed to read EEPROM\n");
 3806                         error = ENXIO;
 3807                         goto fail;
 3808                 }
 3809                 hwcfg = ntohl(hwcfg);
 3810         }
 3811 
 3812         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
 3813         if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
 3814             SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
 3815                 if (BGE_IS_5705_PLUS(sc)) {
 3816                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
 3817                         sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
 3818                 } else
 3819                         sc->bge_flags |= BGE_FLAG_TBI;
 3820         }
 3821 
 3822         /* Set various PHY bug flags. */
 3823         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
 3824             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
 3825                 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
 3826         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
 3827             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
 3828                 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
 3829         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
 3830                 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
 3831         if (pci_get_subvendor(dev) == DELL_VENDORID)
 3832                 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
 3833         if ((BGE_IS_5705_PLUS(sc)) &&
 3834             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
 3835             sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
 3836             sc->bge_asicrev != BGE_ASICREV_BCM57780 &&
 3837             !BGE_IS_5717_PLUS(sc)) {
 3838                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
 3839                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
 3840                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
 3841                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
 3842                         if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
 3843                             pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
 3844                                 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
 3845                         if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
 3846                                 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
 3847                 } else
 3848                         sc->bge_phy_flags |= BGE_PHY_BER_BUG;
 3849         }
 3850 
 3851         /*
 3852          * Don't enable Ethernet@WireSpeed for the 5700 or the
 3853          * 5705 A0 and A1 chips.
 3854          */
 3855         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
 3856             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
 3857             (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
 3858             sc->bge_chipid != BGE_CHIPID_BCM5705_A1)))
 3859                 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
 3860 
 3861         if (sc->bge_flags & BGE_FLAG_TBI) {
 3862                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
 3863                     bge_ifmedia_sts);
 3864                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
 3865                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
 3866                     0, NULL);
 3867                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
 3868                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
 3869                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
 3870         } else {
 3871                 /*
 3872                  * Do transceiver setup and tell the firmware the
 3873                  * driver is down so we can try to get access the
 3874                  * probe if ASF is running.  Retry a couple of times
 3875                  * if we get a conflict with the ASF firmware accessing
 3876                  * the PHY.
 3877                  */
 3878                 trys = 0;
 3879                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
 3880 again:
 3881                 bge_asf_driver_up(sc);
 3882 
 3883                 error = mii_attach(dev, &sc->bge_miibus, ifp, 
 3884                     (ifm_change_cb_t)bge_ifmedia_upd,
 3885                     (ifm_stat_cb_t)bge_ifmedia_sts, capmask, sc->bge_phy_addr, 
 3886                     MII_OFFSET_ANY, MIIF_DOPAUSE);
 3887                 if (error != 0) {
 3888                         if (trys++ < 4) {
 3889                                 device_printf(sc->bge_dev, "Try again\n");
 3890                                 bge_miibus_writereg(sc->bge_dev,
 3891                                     sc->bge_phy_addr, MII_BMCR, BMCR_RESET);
 3892                                 goto again;
 3893                         }
 3894                         device_printf(sc->bge_dev, "attaching PHYs failed\n");
 3895                         goto fail;
 3896                 }
 3897 
 3898                 /*
 3899                  * Now tell the firmware we are going up after probing the PHY
 3900                  */
 3901                 if (sc->bge_asf_mode & ASF_STACKUP)
 3902                         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
 3903         }
 3904 
 3905         /*
 3906          * When using the BCM5701 in PCI-X mode, data corruption has
 3907          * been observed in the first few bytes of some received packets.
 3908          * Aligning the packet buffer in memory eliminates the corruption.
 3909          * Unfortunately, this misaligns the packet payloads.  On platforms
 3910          * which do not support unaligned accesses, we will realign the
 3911          * payloads by copying the received packets.
 3912          */
 3913         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
 3914             sc->bge_flags & BGE_FLAG_PCIX)
 3915                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
 3916 
 3917         /*
 3918          * Call MI attach routine.
 3919          */
 3920         ether_ifattach(ifp, eaddr);
 3921 
 3922         /* Tell upper layer we support long frames. */
 3923         if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
 3924 
 3925         /*
 3926          * Hookup IRQ last.
 3927          */
 3928         if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
 3929                 /* Take advantage of single-shot MSI. */
 3930                 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
 3931                     ~BGE_MSIMODE_ONE_SHOT_DISABLE);
 3932                 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
 3933                     taskqueue_thread_enqueue, &sc->bge_tq);
 3934                 if (sc->bge_tq == NULL) {
 3935                         device_printf(dev, "could not create taskqueue.\n");
 3936                         ether_ifdetach(ifp);
 3937                         error = ENOMEM;
 3938                         goto fail;
 3939                 }
 3940                 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET,
 3941                     "%s taskq", device_get_nameunit(sc->bge_dev));
 3942                 if (error != 0) {
 3943                         device_printf(dev, "could not start threads.\n");
 3944                         ether_ifdetach(ifp);
 3945                         goto fail;
 3946                 }
 3947                 error = bus_setup_intr(dev, sc->bge_irq,
 3948                     INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
 3949                     &sc->bge_intrhand);
 3950         } else
 3951                 error = bus_setup_intr(dev, sc->bge_irq,
 3952                     INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
 3953                     &sc->bge_intrhand);
 3954 
 3955         if (error) {
 3956                 ether_ifdetach(ifp);
 3957                 device_printf(sc->bge_dev, "couldn't set up irq\n");
 3958                 goto fail;
 3959         }
 3960 
 3961         /* Attach driver netdump methods. */
 3962         NETDUMP_SET(ifp, bge);
 3963 
 3964 fail:
 3965         if (error)
 3966                 bge_detach(dev);
 3967         return (error);
 3968 }
 3969 
 3970 static int
 3971 bge_detach(device_t dev)
 3972 {
 3973         struct bge_softc *sc;
 3974         if_t ifp;
 3975 
 3976         sc = device_get_softc(dev);
 3977         ifp = sc->bge_ifp;
 3978 
 3979 #ifdef DEVICE_POLLING
 3980         if (if_getcapenable(ifp) & IFCAP_POLLING)
 3981                 ether_poll_deregister(ifp);
 3982 #endif
 3983 
 3984         if (device_is_attached(dev)) {
 3985                 ether_ifdetach(ifp);
 3986                 BGE_LOCK(sc);
 3987                 bge_stop(sc);
 3988                 BGE_UNLOCK(sc);
 3989                 callout_drain(&sc->bge_stat_ch);
 3990         }
 3991 
 3992         if (sc->bge_tq)
 3993                 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
 3994 
 3995         if (sc->bge_flags & BGE_FLAG_TBI)
 3996                 ifmedia_removeall(&sc->bge_ifmedia);
 3997         else if (sc->bge_miibus != NULL) {
 3998                 bus_generic_detach(dev);
 3999                 device_delete_child(dev, sc->bge_miibus);
 4000         }
 4001 
 4002         bge_release_resources(sc);
 4003 
 4004         return (0);
 4005 }
 4006 
 4007 static void
 4008 bge_release_resources(struct bge_softc *sc)
 4009 {
 4010         device_t dev;
 4011 
 4012         dev = sc->bge_dev;
 4013 
 4014         if (sc->bge_tq != NULL)
 4015                 taskqueue_free(sc->bge_tq);
 4016 
 4017         if (sc->bge_intrhand != NULL)
 4018                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
 4019 
 4020         if (sc->bge_irq != NULL) {
 4021                 bus_release_resource(dev, SYS_RES_IRQ,
 4022                     rman_get_rid(sc->bge_irq), sc->bge_irq);
 4023                 pci_release_msi(dev);
 4024         }
 4025 
 4026         if (sc->bge_res != NULL)
 4027                 bus_release_resource(dev, SYS_RES_MEMORY,
 4028                     rman_get_rid(sc->bge_res), sc->bge_res);
 4029 
 4030         if (sc->bge_res2 != NULL)
 4031                 bus_release_resource(dev, SYS_RES_MEMORY,
 4032                     rman_get_rid(sc->bge_res2), sc->bge_res2);
 4033 
 4034         if (sc->bge_ifp != NULL)
 4035                 if_free(sc->bge_ifp);
 4036 
 4037         bge_dma_free(sc);
 4038 
 4039         if (mtx_initialized(&sc->bge_mtx))      /* XXX */
 4040                 BGE_LOCK_DESTROY(sc);
 4041 }
 4042 
 4043 static int
 4044 bge_reset(struct bge_softc *sc)
 4045 {
 4046         device_t dev;
 4047         uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val;
 4048         void (*write_op)(struct bge_softc *, int, int);
 4049         uint16_t devctl;
 4050         int i;
 4051 
 4052         dev = sc->bge_dev;
 4053 
 4054         mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
 4055         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
 4056                 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
 4057         mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
 4058 
 4059         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
 4060             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
 4061                 if (sc->bge_flags & BGE_FLAG_PCIE)
 4062                         write_op = bge_writemem_direct;
 4063                 else
 4064                         write_op = bge_writemem_ind;
 4065         } else
 4066                 write_op = bge_writereg_ind;
 4067 
 4068         if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
 4069             sc->bge_asicrev != BGE_ASICREV_BCM5701) {
 4070                 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 4071                 for (i = 0; i < 8000; i++) {
 4072                         if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &
 4073                             BGE_NVRAMSWARB_GNT1)
 4074                                 break;
 4075                         DELAY(20);
 4076                 }
 4077                 if (i == 8000) {
 4078                         if (bootverbose)
 4079                                 device_printf(dev, "NVRAM lock timedout!\n");
 4080                 }
 4081         }
 4082         /* Take APE lock when performing reset. */
 4083         bge_ape_lock(sc, BGE_APE_LOCK_GRC);
 4084 
 4085         /* Save some important PCI state. */
 4086         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
 4087         command = pci_read_config(dev, BGE_PCI_CMD, 4);
 4088 
 4089         pci_write_config(dev, BGE_PCI_MISC_CTL,
 4090             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
 4091             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
 4092 
 4093         /* Disable fastboot on controllers that support it. */
 4094         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
 4095             BGE_IS_5755_PLUS(sc)) {
 4096                 if (bootverbose)
 4097                         device_printf(dev, "Disabling fastboot\n");
 4098                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
 4099         }
 4100 
 4101         /*
 4102          * Write the magic number to SRAM at offset 0xB50.
 4103          * When firmware finishes its initialization it will
 4104          * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
 4105          */
 4106         bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
 4107 
 4108         reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
 4109 
 4110         /* XXX: Broadcom Linux driver. */
 4111         if (sc->bge_flags & BGE_FLAG_PCIE) {
 4112                 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
 4113                     (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) {
 4114                         if (CSR_READ_4(sc, 0x7E2C) == 0x60)     /* PCIE 1.0 */
 4115                                 CSR_WRITE_4(sc, 0x7E2C, 0x20);
 4116                 }
 4117                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
 4118                         /* Prevent PCIE link training during global reset */
 4119                         CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
 4120                         reset |= 1 << 29;
 4121                 }
 4122         }
 4123 
 4124         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
 4125                 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
 4126                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
 4127                     val | BGE_VCPU_STATUS_DRV_RESET);
 4128                 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
 4129                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
 4130                     val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
 4131         }
 4132 
 4133         /*
 4134          * Set GPHY Power Down Override to leave GPHY
 4135          * powered up in D0 uninitialized.
 4136          */
 4137         if (BGE_IS_5705_PLUS(sc) &&
 4138             (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0)
 4139                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
 4140 
 4141         /* Issue global reset */
 4142         write_op(sc, BGE_MISC_CFG, reset);
 4143 
 4144         if (sc->bge_flags & BGE_FLAG_PCIE)
 4145                 DELAY(100 * 1000);
 4146         else
 4147                 DELAY(1000);
 4148 
 4149         /* XXX: Broadcom Linux driver. */
 4150         if (sc->bge_flags & BGE_FLAG_PCIE) {
 4151                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
 4152                         DELAY(500000); /* wait for link training to complete */
 4153                         val = pci_read_config(dev, 0xC4, 4);
 4154                         pci_write_config(dev, 0xC4, val | (1 << 15), 4);
 4155                 }
 4156                 devctl = pci_read_config(dev,
 4157                     sc->bge_expcap + PCIER_DEVICE_CTL, 2);
 4158                 /* Clear enable no snoop and disable relaxed ordering. */
 4159                 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE |
 4160                     PCIEM_CTL_NOSNOOP_ENABLE);
 4161                 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL,
 4162                     devctl, 2);
 4163                 pci_set_max_read_req(dev, sc->bge_expmrq);
 4164                 /* Clear error status. */
 4165                 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA,
 4166                     PCIEM_STA_CORRECTABLE_ERROR |
 4167                     PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
 4168                     PCIEM_STA_UNSUPPORTED_REQ, 2);
 4169         }
 4170 
 4171         /* Reset some of the PCI state that got zapped by reset. */
 4172         pci_write_config(dev, BGE_PCI_MISC_CTL,
 4173             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
 4174             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
 4175         val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
 4176         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
 4177             (sc->bge_flags & BGE_FLAG_PCIX) != 0)
 4178                 val |= BGE_PCISTATE_RETRY_SAME_DMA;
 4179         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
 4180                 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
 4181                     BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
 4182                     BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
 4183         pci_write_config(dev, BGE_PCI_PCISTATE, val, 4);
 4184         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
 4185         pci_write_config(dev, BGE_PCI_CMD, command, 4);
 4186         /*
 4187          * Disable PCI-X relaxed ordering to ensure status block update
 4188          * comes first then packet buffer DMA. Otherwise driver may
 4189          * read stale status block.
 4190          */
 4191         if (sc->bge_flags & BGE_FLAG_PCIX) {
 4192                 devctl = pci_read_config(dev,
 4193                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
 4194                 devctl &= ~PCIXM_COMMAND_ERO;
 4195                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
 4196                         devctl &= ~PCIXM_COMMAND_MAX_READ;
 4197                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
 4198                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
 4199                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
 4200                             PCIXM_COMMAND_MAX_READ);
 4201                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
 4202                 }
 4203                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
 4204                     devctl, 2);
 4205         }
 4206         /* Re-enable MSI, if necessary, and enable the memory arbiter. */
 4207         if (BGE_IS_5714_FAMILY(sc)) {
 4208                 /* This chip disables MSI on reset. */
 4209                 if (sc->bge_flags & BGE_FLAG_MSI) {
 4210                         val = pci_read_config(dev,
 4211                             sc->bge_msicap + PCIR_MSI_CTRL, 2);
 4212                         pci_write_config(dev,
 4213                             sc->bge_msicap + PCIR_MSI_CTRL,
 4214                             val | PCIM_MSICTRL_MSI_ENABLE, 2);
 4215                         val = CSR_READ_4(sc, BGE_MSI_MODE);
 4216                         CSR_WRITE_4(sc, BGE_MSI_MODE,
 4217                             val | BGE_MSIMODE_ENABLE);
 4218                 }
 4219                 val = CSR_READ_4(sc, BGE_MARB_MODE);
 4220                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
 4221         } else
 4222                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
 4223 
 4224         /* Fix up byte swapping. */
 4225         CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
 4226 
 4227         val = CSR_READ_4(sc, BGE_MAC_MODE);
 4228         val = (val & ~mac_mode_mask) | mac_mode;
 4229         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
 4230         DELAY(40);
 4231 
 4232         bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
 4233 
 4234         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
 4235                 for (i = 0; i < BGE_TIMEOUT; i++) {
 4236                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
 4237                         if (val & BGE_VCPU_STATUS_INIT_DONE)
 4238                                 break;
 4239                         DELAY(100);
 4240                 }
 4241                 if (i == BGE_TIMEOUT) {
 4242                         device_printf(dev, "reset timed out\n");
 4243                         return (1);
 4244                 }
 4245         } else {
 4246                 /*
 4247                  * Poll until we see the 1's complement of the magic number.
 4248                  * This indicates that the firmware initialization is complete.
 4249                  * We expect this to fail if no chip containing the Ethernet
 4250                  * address is fitted though.
 4251                  */
 4252                 for (i = 0; i < BGE_TIMEOUT; i++) {
 4253                         DELAY(10);
 4254                         val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
 4255                         if (val == ~BGE_SRAM_FW_MB_MAGIC)
 4256                                 break;
 4257                 }
 4258 
 4259                 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
 4260                         device_printf(dev,
 4261                             "firmware handshake timed out, found 0x%08x\n",
 4262                             val);
 4263                 /* BCM57765 A0 needs additional time before accessing. */
 4264                 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
 4265                         DELAY(10 * 1000);       /* XXX */
 4266         }
 4267 
 4268         /*
 4269          * The 5704 in TBI mode apparently needs some special
 4270          * adjustment to insure the SERDES drive level is set
 4271          * to 1.2V.
 4272          */
 4273         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
 4274             sc->bge_flags & BGE_FLAG_TBI) {
 4275                 val = CSR_READ_4(sc, BGE_SERDES_CFG);
 4276                 val = (val & ~0xFFF) | 0x880;
 4277                 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
 4278         }
 4279 
 4280         /* XXX: Broadcom Linux driver. */
 4281         if (sc->bge_flags & BGE_FLAG_PCIE &&
 4282             !BGE_IS_5717_PLUS(sc) &&
 4283             sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
 4284             sc->bge_asicrev != BGE_ASICREV_BCM5785) {
 4285                 /* Enable Data FIFO protection. */
 4286                 val = CSR_READ_4(sc, 0x7C00);
 4287                 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
 4288         }
 4289 
 4290         if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
 4291                 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
 4292                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
 4293 
 4294         return (0);
 4295 }
 4296 
 4297 static __inline void
 4298 bge_rxreuse_std(struct bge_softc *sc, int i)
 4299 {
 4300         struct bge_rx_bd *r;
 4301 
 4302         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
 4303         r->bge_flags = BGE_RXBDFLAG_END;
 4304         r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
 4305         r->bge_idx = i;
 4306         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
 4307 }
 4308 
 4309 static __inline void
 4310 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
 4311 {
 4312         struct bge_extrx_bd *r;
 4313 
 4314         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
 4315         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
 4316         r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
 4317         r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
 4318         r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
 4319         r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
 4320         r->bge_idx = i;
 4321         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
 4322 }
 4323 
 4324 /*
 4325  * Frame reception handling. This is called if there's a frame
 4326  * on the receive return list.
 4327  *
 4328  * Note: we have to be able to handle two possibilities here:
 4329  * 1) the frame is from the jumbo receive ring
 4330  * 2) the frame is from the standard receive ring
 4331  */
 4332 
 4333 static int
 4334 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
 4335 {
 4336         if_t ifp;
 4337         int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
 4338         uint16_t rx_cons;
 4339 
 4340         rx_cons = sc->bge_rx_saved_considx;
 4341 
 4342         /* Nothing to do. */
 4343         if (rx_cons == rx_prod)
 4344                 return (rx_npkts);
 4345 
 4346         ifp = sc->bge_ifp;
 4347 
 4348         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
 4349             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
 4350         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
 4351             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
 4352         if (BGE_IS_JUMBO_CAPABLE(sc) &&
 4353             if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN + 
 4354             ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))
 4355                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 4356                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
 4357 
 4358         while (rx_cons != rx_prod) {
 4359                 struct bge_rx_bd        *cur_rx;
 4360                 uint32_t                rxidx;
 4361                 struct mbuf             *m = NULL;
 4362                 uint16_t                vlan_tag = 0;
 4363                 int                     have_tag = 0;
 4364 
 4365 #ifdef DEVICE_POLLING
 4366                 if (if_getcapenable(ifp) & IFCAP_POLLING) {
 4367                         if (sc->rxcycles <= 0)
 4368                                 break;
 4369                         sc->rxcycles--;
 4370                 }
 4371 #endif
 4372 
 4373                 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
 4374 
 4375                 rxidx = cur_rx->bge_idx;
 4376                 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
 4377 
 4378                 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING &&
 4379                     cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
 4380                         have_tag = 1;
 4381                         vlan_tag = cur_rx->bge_vlan_tag;
 4382                 }
 4383 
 4384                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
 4385                         jumbocnt++;
 4386                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
 4387                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
 4388                                 bge_rxreuse_jumbo(sc, rxidx);
 4389                                 continue;
 4390                         }
 4391                         if (bge_newbuf_jumbo(sc, rxidx) != 0) {
 4392                                 bge_rxreuse_jumbo(sc, rxidx);
 4393                                 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
 4394                                 continue;
 4395                         }
 4396                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
 4397                 } else {
 4398                         stdcnt++;
 4399                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
 4400                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
 4401                                 bge_rxreuse_std(sc, rxidx);
 4402                                 continue;
 4403                         }
 4404                         if (bge_newbuf_std(sc, rxidx) != 0) {
 4405                                 bge_rxreuse_std(sc, rxidx);
 4406                                 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
 4407                                 continue;
 4408                         }
 4409                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
 4410                 }
 4411 
 4412                 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
 4413 #ifndef __NO_STRICT_ALIGNMENT
 4414                 /*
 4415                  * For architectures with strict alignment we must make sure
 4416                  * the payload is aligned.
 4417                  */
 4418                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
 4419                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
 4420                             cur_rx->bge_len);
 4421                         m->m_data += ETHER_ALIGN;
 4422                 }
 4423 #endif
 4424                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
 4425                 m->m_pkthdr.rcvif = ifp;
 4426 
 4427                 if (if_getcapenable(ifp) & IFCAP_RXCSUM)
 4428                         bge_rxcsum(sc, cur_rx, m);
 4429 
 4430                 /*
 4431                  * If we received a packet with a vlan tag,
 4432                  * attach that information to the packet.
 4433                  */
 4434                 if (have_tag) {
 4435                         m->m_pkthdr.ether_vtag = vlan_tag;
 4436                         m->m_flags |= M_VLANTAG;
 4437                 }
 4438 
 4439                 if (holdlck != 0) {
 4440                         BGE_UNLOCK(sc);
 4441                         if_input(ifp, m);
 4442                         BGE_LOCK(sc);
 4443                 } else
 4444                         if_input(ifp, m);
 4445                 rx_npkts++;
 4446 
 4447                 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
 4448                         return (rx_npkts);
 4449         }
 4450 
 4451         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
 4452             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
 4453         if (stdcnt > 0)
 4454                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
 4455                     sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
 4456 
 4457         if (jumbocnt > 0)
 4458                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 4459                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
 4460 
 4461         sc->bge_rx_saved_considx = rx_cons;
 4462         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
 4463         if (stdcnt)
 4464                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std +
 4465                     BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT);
 4466         if (jumbocnt)
 4467                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo +
 4468                     BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT);
 4469 #ifdef notyet
 4470         /*
 4471          * This register wraps very quickly under heavy packet drops.
 4472          * If you need correct statistics, you can enable this check.
 4473          */
 4474         if (BGE_IS_5705_PLUS(sc))
 4475                 if_incierrors(ifp, CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS));
 4476 #endif
 4477         return (rx_npkts);
 4478 }
 4479 
 4480 static void
 4481 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
 4482 {
 4483 
 4484         if (BGE_IS_5717_PLUS(sc)) {
 4485                 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
 4486                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
 4487                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
 4488                                 if ((cur_rx->bge_error_flag &
 4489                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
 4490                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
 4491                         }
 4492                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
 4493                                 m->m_pkthdr.csum_data =
 4494                                     cur_rx->bge_tcp_udp_csum;
 4495                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
 4496                                     CSUM_PSEUDO_HDR;
 4497                         }
 4498                 }
 4499         } else {
 4500                 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
 4501                         m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
 4502                         if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
 4503                                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
 4504                 }
 4505                 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
 4506                     m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
 4507                         m->m_pkthdr.csum_data =
 4508                             cur_rx->bge_tcp_udp_csum;
 4509                         m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
 4510                             CSUM_PSEUDO_HDR;
 4511                 }
 4512         }
 4513 }
 4514 
 4515 static void
 4516 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
 4517 {
 4518         struct bge_tx_bd *cur_tx;
 4519         if_t ifp;
 4520 
 4521         BGE_LOCK_ASSERT(sc);
 4522 
 4523         /* Nothing to do. */
 4524         if (sc->bge_tx_saved_considx == tx_cons)
 4525                 return;
 4526 
 4527         ifp = sc->bge_ifp;
 4528 
 4529         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
 4530             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
 4531         /*
 4532          * Go through our tx ring and free mbufs for those
 4533          * frames that have been sent.
 4534          */
 4535         while (sc->bge_tx_saved_considx != tx_cons) {
 4536                 uint32_t                idx;
 4537 
 4538                 idx = sc->bge_tx_saved_considx;
 4539                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
 4540                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
 4541                         if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
 4542                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
 4543                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
 4544                             sc->bge_cdata.bge_tx_dmamap[idx],
 4545                             BUS_DMASYNC_POSTWRITE);
 4546                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
 4547                             sc->bge_cdata.bge_tx_dmamap[idx]);
 4548                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
 4549                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
 4550                 }
 4551                 sc->bge_txcnt--;
 4552                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
 4553         }
 4554 
 4555         if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
 4556         if (sc->bge_txcnt == 0)
 4557                 sc->bge_timer = 0;
 4558 }
 4559 
 4560 #ifdef DEVICE_POLLING
 4561 static int
 4562 bge_poll(if_t ifp, enum poll_cmd cmd, int count)
 4563 {
 4564         struct bge_softc *sc = if_getsoftc(ifp);
 4565         uint16_t rx_prod, tx_cons;
 4566         uint32_t statusword;
 4567         int rx_npkts = 0;
 4568 
 4569         BGE_LOCK(sc);
 4570         if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
 4571                 BGE_UNLOCK(sc);
 4572                 return (rx_npkts);
 4573         }
 4574 
 4575         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
 4576             sc->bge_cdata.bge_status_map,
 4577             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 4578         /* Fetch updates from the status block. */
 4579         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
 4580         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
 4581 
 4582         statusword = sc->bge_ldata.bge_status_block->bge_status;
 4583         /* Clear the status so the next pass only sees the changes. */
 4584         sc->bge_ldata.bge_status_block->bge_status = 0;
 4585 
 4586         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
 4587             sc->bge_cdata.bge_status_map,
 4588             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 4589 
 4590         /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
 4591         if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
 4592                 sc->bge_link_evt++;
 4593 
 4594         if (cmd == POLL_AND_CHECK_STATUS)
 4595                 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
 4596                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
 4597                     sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
 4598                         bge_link_upd(sc);
 4599 
 4600         sc->rxcycles = count;
 4601         rx_npkts = bge_rxeof(sc, rx_prod, 1);
 4602         if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
 4603                 BGE_UNLOCK(sc);
 4604                 return (rx_npkts);
 4605         }
 4606         bge_txeof(sc, tx_cons);
 4607         if (!if_sendq_empty(ifp))
 4608                 bge_start_locked(ifp);
 4609 
 4610         BGE_UNLOCK(sc);
 4611         return (rx_npkts);
 4612 }
 4613 #endif /* DEVICE_POLLING */
 4614 
 4615 static int
 4616 bge_msi_intr(void *arg)
 4617 {
 4618         struct bge_softc *sc;
 4619 
 4620         sc = (struct bge_softc *)arg;
 4621         /*
 4622          * This interrupt is not shared and controller already
 4623          * disabled further interrupt.
 4624          */
 4625         taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
 4626         return (FILTER_HANDLED);
 4627 }
 4628 
 4629 static void
 4630 bge_intr_task(void *arg, int pending)
 4631 {
 4632         struct bge_softc *sc;
 4633         if_t ifp;
 4634         uint32_t status, status_tag;
 4635         uint16_t rx_prod, tx_cons;
 4636 
 4637         sc = (struct bge_softc *)arg;
 4638         ifp = sc->bge_ifp;
 4639 
 4640         BGE_LOCK(sc);
 4641         if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
 4642                 BGE_UNLOCK(sc);
 4643                 return;
 4644         }
 4645 
 4646         /* Get updated status block. */
 4647         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
 4648             sc->bge_cdata.bge_status_map,
 4649             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 4650 
 4651         /* Save producer/consumer indices. */
 4652         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
 4653         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
 4654         status = sc->bge_ldata.bge_status_block->bge_status;
 4655         status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
 4656         /* Dirty the status flag. */
 4657         sc->bge_ldata.bge_status_block->bge_status = 0;
 4658         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
 4659             sc->bge_cdata.bge_status_map,
 4660             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 4661         if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
 4662                 status_tag = 0;
 4663 
 4664         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0)
 4665                 bge_link_upd(sc);
 4666 
 4667         /* Let controller work. */
 4668         bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
 4669 
 4670         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
 4671             sc->bge_rx_saved_considx != rx_prod) {
 4672                 /* Check RX return ring producer/consumer. */
 4673                 BGE_UNLOCK(sc);
 4674                 bge_rxeof(sc, rx_prod, 0);
 4675                 BGE_LOCK(sc);
 4676         }
 4677         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
 4678                 /* Check TX ring producer/consumer. */
 4679                 bge_txeof(sc, tx_cons);
 4680                 if (!if_sendq_empty(ifp))
 4681                         bge_start_locked(ifp);
 4682         }
 4683         BGE_UNLOCK(sc);
 4684 }
 4685 
 4686 static void
 4687 bge_intr(void *xsc)
 4688 {
 4689         struct bge_softc *sc;
 4690         if_t ifp;
 4691         uint32_t statusword;
 4692         uint16_t rx_prod, tx_cons;
 4693 
 4694         sc = xsc;
 4695 
 4696         BGE_LOCK(sc);
 4697 
 4698         ifp = sc->bge_ifp;
 4699 
 4700 #ifdef DEVICE_POLLING
 4701         if (if_getcapenable(ifp) & IFCAP_POLLING) {
 4702                 BGE_UNLOCK(sc);
 4703                 return;
 4704         }
 4705 #endif
 4706 
 4707         /*
 4708          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
 4709          * disable interrupts by writing nonzero like we used to, since with
 4710          * our current organization this just gives complications and
 4711          * pessimizations for re-enabling interrupts.  We used to have races
 4712          * instead of the necessary complications.  Disabling interrupts
 4713          * would just reduce the chance of a status update while we are
 4714          * running (by switching to the interrupt-mode coalescence
 4715          * parameters), but this chance is already very low so it is more
 4716          * efficient to get another interrupt than prevent it.
 4717          *
 4718          * We do the ack first to ensure another interrupt if there is a
 4719          * status update after the ack.  We don't check for the status
 4720          * changing later because it is more efficient to get another
 4721          * interrupt than prevent it, not quite as above (not checking is
 4722          * a smaller optimization than not toggling the interrupt enable,
 4723          * since checking doesn't involve PCI accesses and toggling require
 4724          * the status check).  So toggling would probably be a pessimization
 4725          * even with MSI.  It would only be needed for using a task queue.
 4726          */
 4727         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
 4728 
 4729         /*
 4730          * Do the mandatory PCI flush as well as get the link status.
 4731          */
 4732         statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
 4733 
 4734         /* Make sure the descriptor ring indexes are coherent. */
 4735         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
 4736             sc->bge_cdata.bge_status_map,
 4737             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 4738         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
 4739         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
 4740         sc->bge_ldata.bge_status_block->bge_status = 0;
 4741         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
 4742             sc->bge_cdata.bge_status_map,
 4743             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 4744 
 4745         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
 4746             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
 4747             statusword || sc->bge_link_evt)
 4748                 bge_link_upd(sc);
 4749 
 4750         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
 4751                 /* Check RX return ring producer/consumer. */
 4752                 bge_rxeof(sc, rx_prod, 1);
 4753         }
 4754 
 4755         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
 4756                 /* Check TX ring producer/consumer. */
 4757                 bge_txeof(sc, tx_cons);
 4758         }
 4759 
 4760         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
 4761             !if_sendq_empty(ifp))
 4762                 bge_start_locked(ifp);
 4763 
 4764         BGE_UNLOCK(sc);
 4765 }
 4766 
 4767 static void
 4768 bge_asf_driver_up(struct bge_softc *sc)
 4769 {
 4770         if (sc->bge_asf_mode & ASF_STACKUP) {
 4771                 /* Send ASF heartbeat aprox. every 2s */
 4772                 if (sc->bge_asf_count)
 4773                         sc->bge_asf_count --;
 4774                 else {
 4775                         sc->bge_asf_count = 2;
 4776                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
 4777                             BGE_FW_CMD_DRV_ALIVE);
 4778                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
 4779                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
 4780                             BGE_FW_HB_TIMEOUT_SEC);
 4781                         CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
 4782                             CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
 4783                             BGE_RX_CPU_DRV_EVENT);
 4784                 }
 4785         }
 4786 }
 4787 
 4788 static void
 4789 bge_tick(void *xsc)
 4790 {
 4791         struct bge_softc *sc = xsc;
 4792         struct mii_data *mii = NULL;
 4793 
 4794         BGE_LOCK_ASSERT(sc);
 4795 
 4796         /* Synchronize with possible callout reset/stop. */
 4797         if (callout_pending(&sc->bge_stat_ch) ||
 4798             !callout_active(&sc->bge_stat_ch))
 4799                 return;
 4800 
 4801         if (BGE_IS_5705_PLUS(sc))
 4802                 bge_stats_update_regs(sc);
 4803         else
 4804                 bge_stats_update(sc);
 4805 
 4806         /* XXX Add APE heartbeat check here? */
 4807 
 4808         if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
 4809                 mii = device_get_softc(sc->bge_miibus);
 4810                 /*
 4811                  * Do not touch PHY if we have link up. This could break
 4812                  * IPMI/ASF mode or produce extra input errors
 4813                  * (extra errors was reported for bcm5701 & bcm5704).
 4814                  */
 4815                 if (!sc->bge_link)
 4816                         mii_tick(mii);
 4817         } else {
 4818                 /*
 4819                  * Since in TBI mode auto-polling can't be used we should poll
 4820                  * link status manually. Here we register pending link event
 4821                  * and trigger interrupt.
 4822                  */
 4823 #ifdef DEVICE_POLLING
 4824                 /* In polling mode we poll link state in bge_poll(). */
 4825                 if (!(if_getcapenable(sc->bge_ifp) & IFCAP_POLLING))
 4826 #endif
 4827                 {
 4828                 sc->bge_link_evt++;
 4829                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
 4830                     sc->bge_flags & BGE_FLAG_5788)
 4831                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
 4832                 else
 4833                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
 4834                 }
 4835         }
 4836 
 4837         bge_asf_driver_up(sc);
 4838         bge_watchdog(sc);
 4839 
 4840         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
 4841 }
 4842 
 4843 static void
 4844 bge_stats_update_regs(struct bge_softc *sc)
 4845 {
 4846         if_t ifp;
 4847         struct bge_mac_stats *stats;
 4848         uint32_t val;
 4849 
 4850         ifp = sc->bge_ifp;
 4851         stats = &sc->bge_mac_stats;
 4852 
 4853         stats->ifHCOutOctets +=
 4854             CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
 4855         stats->etherStatsCollisions +=
 4856             CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
 4857         stats->outXonSent +=
 4858             CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
 4859         stats->outXoffSent +=
 4860             CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
 4861         stats->dot3StatsInternalMacTransmitErrors +=
 4862             CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
 4863         stats->dot3StatsSingleCollisionFrames +=
 4864             CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
 4865         stats->dot3StatsMultipleCollisionFrames +=
 4866             CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
 4867         stats->dot3StatsDeferredTransmissions +=
 4868             CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
 4869         stats->dot3StatsExcessiveCollisions +=
 4870             CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
 4871         stats->dot3StatsLateCollisions +=
 4872             CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
 4873         stats->ifHCOutUcastPkts +=
 4874             CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
 4875         stats->ifHCOutMulticastPkts +=
 4876             CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
 4877         stats->ifHCOutBroadcastPkts +=
 4878             CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
 4879 
 4880         stats->ifHCInOctets +=
 4881             CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
 4882         stats->etherStatsFragments +=
 4883             CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
 4884         stats->ifHCInUcastPkts +=
 4885             CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
 4886         stats->ifHCInMulticastPkts +=
 4887             CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
 4888         stats->ifHCInBroadcastPkts +=
 4889             CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
 4890         stats->dot3StatsFCSErrors +=
 4891             CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
 4892         stats->dot3StatsAlignmentErrors +=
 4893             CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
 4894         stats->xonPauseFramesReceived +=
 4895             CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
 4896         stats->xoffPauseFramesReceived +=
 4897             CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
 4898         stats->macControlFramesReceived +=
 4899             CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
 4900         stats->xoffStateEntered +=
 4901             CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
 4902         stats->dot3StatsFramesTooLong +=
 4903             CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
 4904         stats->etherStatsJabbers +=
 4905             CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
 4906         stats->etherStatsUndersizePkts +=
 4907             CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
 4908 
 4909         stats->FramesDroppedDueToFilters +=
 4910             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
 4911         stats->DmaWriteQueueFull +=
 4912             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
 4913         stats->DmaWriteHighPriQueueFull +=
 4914             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
 4915         stats->NoMoreRxBDs +=
 4916             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
 4917         /*
 4918          * XXX
 4919          * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS
 4920          * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0
 4921          * includes number of unwanted multicast frames.  This comes
 4922          * from silicon bug and known workaround to get rough(not
 4923          * exact) counter is to enable interrupt on MBUF low water
 4924          * attention.  This can be accomplished by setting
 4925          * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE,
 4926          * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and
 4927          * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL.
 4928          * However that change would generate more interrupts and
 4929          * there are still possibilities of losing multiple frames
 4930          * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling.
 4931          * Given that the workaround still would not get correct
 4932          * counter I don't think it's worth to implement it.  So
 4933          * ignore reading the counter on controllers that have the
 4934          * silicon bug.
 4935          */
 4936         if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
 4937             sc->bge_chipid != BGE_CHIPID_BCM5719_A0 &&
 4938             sc->bge_chipid != BGE_CHIPID_BCM5720_A0)
 4939                 stats->InputDiscards +=
 4940                     CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
 4941         stats->InputErrors +=
 4942             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
 4943         stats->RecvThresholdHit +=
 4944             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
 4945 
 4946         if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
 4947                 /*
 4948                  * If controller transmitted more than BGE_NUM_RDMA_CHANNELS
 4949                  * frames, it's safe to disable workaround for DMA engine's
 4950                  * miscalculation of TXMBUF space.
 4951                  */
 4952                 if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts +
 4953                     stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) {
 4954                         val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
 4955                         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
 4956                                 val &= ~BGE_RDMA_TX_LENGTH_WA_5719;
 4957                         else
 4958                                 val &= ~BGE_RDMA_TX_LENGTH_WA_5720;
 4959                         CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
 4960                         sc->bge_flags &= ~BGE_FLAG_RDMA_BUG;
 4961                 }
 4962         }
 4963 }
 4964 
 4965 static void
 4966 bge_stats_clear_regs(struct bge_softc *sc)
 4967 {
 4968 
 4969         CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
 4970         CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
 4971         CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
 4972         CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
 4973         CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
 4974         CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
 4975         CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
 4976         CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
 4977         CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
 4978         CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
 4979         CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
 4980         CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
 4981         CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
 4982 
 4983         CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
 4984         CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
 4985         CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
 4986         CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
 4987         CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
 4988         CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
 4989         CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
 4990         CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
 4991         CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
 4992         CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
 4993         CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
 4994         CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
 4995         CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
 4996         CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
 4997 
 4998         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
 4999         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
 5000         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
 5001         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
 5002         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
 5003         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
 5004         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
 5005 }
 5006 
 5007 static void
 5008 bge_stats_update(struct bge_softc *sc)
 5009 {
 5010         if_t ifp;
 5011         bus_size_t stats;
 5012         uint32_t cnt;   /* current register value */
 5013 
 5014         ifp = sc->bge_ifp;
 5015 
 5016         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
 5017 
 5018 #define READ_STAT(sc, stats, stat) \
 5019         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
 5020 
 5021         cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
 5022         if_inc_counter(ifp, IFCOUNTER_COLLISIONS, cnt - sc->bge_tx_collisions);
 5023         sc->bge_tx_collisions = cnt;
 5024 
 5025         cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo);
 5026         if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_nobds);
 5027         sc->bge_rx_nobds = cnt;
 5028         cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo);
 5029         if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_inerrs);
 5030         sc->bge_rx_inerrs = cnt;
 5031         cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
 5032         if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_discards);
 5033         sc->bge_rx_discards = cnt;
 5034 
 5035         cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
 5036         if_inc_counter(ifp, IFCOUNTER_OERRORS, cnt - sc->bge_tx_discards);
 5037         sc->bge_tx_discards = cnt;
 5038 
 5039 #undef  READ_STAT
 5040 }
 5041 
 5042 /*
 5043  * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
 5044  * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
 5045  * but when such padded frames employ the bge IP/TCP checksum offload,
 5046  * the hardware checksum assist gives incorrect results (possibly
 5047  * from incorporating its own padding into the UDP/TCP checksum; who knows).
 5048  * If we pad such runts with zeros, the onboard checksum comes out correct.
 5049  */
 5050 static __inline int
 5051 bge_cksum_pad(struct mbuf *m)
 5052 {
 5053         int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
 5054         struct mbuf *last;
 5055 
 5056         /* If there's only the packet-header and we can pad there, use it. */
 5057         if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
 5058             M_TRAILINGSPACE(m) >= padlen) {
 5059                 last = m;
 5060         } else {
 5061                 /*
 5062                  * Walk packet chain to find last mbuf. We will either
 5063                  * pad there, or append a new mbuf and pad it.
 5064                  */
 5065                 for (last = m; last->m_next != NULL; last = last->m_next);
 5066                 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
 5067                         /* Allocate new empty mbuf, pad it. Compact later. */
 5068                         struct mbuf *n;
 5069 
 5070                         MGET(n, M_NOWAIT, MT_DATA);
 5071                         if (n == NULL)
 5072                                 return (ENOBUFS);
 5073                         n->m_len = 0;
 5074                         last->m_next = n;
 5075                         last = n;
 5076                 }
 5077         }
 5078 
 5079         /* Now zero the pad area, to avoid the bge cksum-assist bug. */
 5080         memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
 5081         last->m_len += padlen;
 5082         m->m_pkthdr.len += padlen;
 5083 
 5084         return (0);
 5085 }
 5086 
 5087 static struct mbuf *
 5088 bge_check_short_dma(struct mbuf *m)
 5089 {
 5090         struct mbuf *n;
 5091         int found;
 5092 
 5093         /*
 5094          * If device receive two back-to-back send BDs with less than
 5095          * or equal to 8 total bytes then the device may hang.  The two
 5096          * back-to-back send BDs must in the same frame for this failure
 5097          * to occur.  Scan mbuf chains and see whether two back-to-back
 5098          * send BDs are there. If this is the case, allocate new mbuf
 5099          * and copy the frame to workaround the silicon bug.
 5100          */
 5101         for (n = m, found = 0; n != NULL; n = n->m_next) {
 5102                 if (n->m_len < 8) {
 5103                         found++;
 5104                         if (found > 1)
 5105                                 break;
 5106                         continue;
 5107                 }
 5108                 found = 0;
 5109         }
 5110 
 5111         if (found > 1) {
 5112                 n = m_defrag(m, M_NOWAIT);
 5113                 if (n == NULL)
 5114                         m_freem(m);
 5115         } else
 5116                 n = m;
 5117         return (n);
 5118 }
 5119 
 5120 static struct mbuf *
 5121 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
 5122     uint16_t *flags)
 5123 {
 5124         struct ip *ip;
 5125         struct tcphdr *tcp;
 5126         struct mbuf *n;
 5127         uint16_t hlen;
 5128         uint32_t poff;
 5129 
 5130         if (M_WRITABLE(m) == 0) {
 5131                 /* Get a writable copy. */
 5132                 n = m_dup(m, M_NOWAIT);
 5133                 m_freem(m);
 5134                 if (n == NULL)
 5135                         return (NULL);
 5136                 m = n;
 5137         }
 5138         m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
 5139         if (m == NULL)
 5140                 return (NULL);
 5141         ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
 5142         poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
 5143         m = m_pullup(m, poff + sizeof(struct tcphdr));
 5144         if (m == NULL)
 5145                 return (NULL);
 5146         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
 5147         m = m_pullup(m, poff + (tcp->th_off << 2));
 5148         if (m == NULL)
 5149                 return (NULL);
 5150         /*
 5151          * It seems controller doesn't modify IP length and TCP pseudo
 5152          * checksum. These checksum computed by upper stack should be 0.
 5153          */
 5154         *mss = m->m_pkthdr.tso_segsz;
 5155         ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
 5156         ip->ip_sum = 0;
 5157         ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
 5158         /* Clear pseudo checksum computed by TCP stack. */
 5159         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
 5160         tcp->th_sum = 0;
 5161         /*
 5162          * Broadcom controllers uses different descriptor format for
 5163          * TSO depending on ASIC revision. Due to TSO-capable firmware
 5164          * license issue and lower performance of firmware based TSO
 5165          * we only support hardware based TSO.
 5166          */
 5167         /* Calculate header length, incl. TCP/IP options, in 32 bit units. */
 5168         hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
 5169         if (sc->bge_flags & BGE_FLAG_TSO3) {
 5170                 /*
 5171                  * For BCM5717 and newer controllers, hardware based TSO
 5172                  * uses the 14 lower bits of the bge_mss field to store the
 5173                  * MSS and the upper 2 bits to store the lowest 2 bits of
 5174                  * the IP/TCP header length.  The upper 6 bits of the header
 5175                  * length are stored in the bge_flags[14:10,4] field.  Jumbo
 5176                  * frames are supported.
 5177                  */
 5178                 *mss |= ((hlen & 0x3) << 14);
 5179                 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2);
 5180         } else {
 5181                 /*
 5182                  * For BCM5755 and newer controllers, hardware based TSO uses
 5183                  * the lower 11 bits to store the MSS and the upper 5 bits to
 5184                  * store the IP/TCP header length. Jumbo frames are not
 5185                  * supported.
 5186                  */
 5187                 *mss |= (hlen << 11);
 5188         }
 5189         return (m);
 5190 }
 5191 
 5192 /*
 5193  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
 5194  * pointers to descriptors.
 5195  */
 5196 static int
 5197 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
 5198 {
 5199         bus_dma_segment_t       segs[BGE_NSEG_NEW];
 5200         bus_dmamap_t            map;
 5201         struct bge_tx_bd        *d;
 5202         struct mbuf             *m = *m_head;
 5203         uint32_t                idx = *txidx;
 5204         uint16_t                csum_flags, mss, vlan_tag;
 5205         int                     nsegs, i, error;
 5206 
 5207         csum_flags = 0;
 5208         mss = 0;
 5209         vlan_tag = 0;
 5210         if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
 5211             m->m_next != NULL) {
 5212                 *m_head = bge_check_short_dma(m);
 5213                 if (*m_head == NULL)
 5214                         return (ENOBUFS);
 5215                 m = *m_head;
 5216         }
 5217         if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
 5218                 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
 5219                 if (*m_head == NULL)
 5220                         return (ENOBUFS);
 5221                 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
 5222                     BGE_TXBDFLAG_CPU_POST_DMA;
 5223         } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
 5224                 if (m->m_pkthdr.csum_flags & CSUM_IP)
 5225                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
 5226                 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
 5227                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
 5228                         if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
 5229                             (error = bge_cksum_pad(m)) != 0) {
 5230                                 m_freem(m);
 5231                                 *m_head = NULL;
 5232                                 return (error);
 5233                         }
 5234                 }
 5235         }
 5236 
 5237         if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) {
 5238                 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
 5239                     m->m_pkthdr.len > ETHER_MAX_LEN)
 5240                         csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME;
 5241                 if (sc->bge_forced_collapse > 0 &&
 5242                     (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
 5243                         /*
 5244                          * Forcedly collapse mbuf chains to overcome hardware
 5245                          * limitation which only support a single outstanding
 5246                          * DMA read operation.
 5247                          */
 5248                         if (sc->bge_forced_collapse == 1)
 5249                                 m = m_defrag(m, M_NOWAIT);
 5250                         else
 5251                                 m = m_collapse(m, M_NOWAIT,
 5252                                     sc->bge_forced_collapse);
 5253                         if (m == NULL)
 5254                                 m = *m_head;
 5255                         *m_head = m;
 5256                 }
 5257         }
 5258 
 5259         map = sc->bge_cdata.bge_tx_dmamap[idx];
 5260         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
 5261             &nsegs, BUS_DMA_NOWAIT);
 5262         if (error == EFBIG) {
 5263                 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW);
 5264                 if (m == NULL) {
 5265                         m_freem(*m_head);
 5266                         *m_head = NULL;
 5267                         return (ENOBUFS);
 5268                 }
 5269                 *m_head = m;
 5270                 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
 5271                     m, segs, &nsegs, BUS_DMA_NOWAIT);
 5272                 if (error) {
 5273                         m_freem(m);
 5274                         *m_head = NULL;
 5275                         return (error);
 5276                 }
 5277         } else if (error != 0)
 5278                 return (error);
 5279 
 5280         /* Check if we have enough free send BDs. */
 5281         if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
 5282                 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
 5283                 return (ENOBUFS);
 5284         }
 5285 
 5286         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
 5287 
 5288         if (m->m_flags & M_VLANTAG) {
 5289                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
 5290                 vlan_tag = m->m_pkthdr.ether_vtag;
 5291         }
 5292 
 5293         if (sc->bge_asicrev == BGE_ASICREV_BCM5762 &&
 5294             (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
 5295                 /*
 5296                  * 5725 family of devices corrupts TSO packets when TSO DMA
 5297                  * buffers cross into regions which are within MSS bytes of
 5298                  * a 4GB boundary.  If we encounter the condition, drop the
 5299                  * packet.
 5300                  */
 5301                 for (i = 0; ; i++) {
 5302                         d = &sc->bge_ldata.bge_tx_ring[idx];
 5303                         d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
 5304                         d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
 5305                         d->bge_len = segs[i].ds_len;
 5306                         if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss <
 5307                             d->bge_addr.bge_addr_lo)
 5308                                 break;
 5309                         d->bge_flags = csum_flags;
 5310                         d->bge_vlan_tag = vlan_tag;
 5311                         d->bge_mss = mss;
 5312                         if (i == nsegs - 1)
 5313                                 break;
 5314                         BGE_INC(idx, BGE_TX_RING_CNT);
 5315                 }
 5316                 if (i != nsegs - 1) {
 5317                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map,
 5318                             BUS_DMASYNC_POSTWRITE);
 5319                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
 5320                         m_freem(*m_head);
 5321                         *m_head = NULL;
 5322                         return (EIO);
 5323                 }
 5324         } else {
 5325                 for (i = 0; ; i++) {
 5326                         d = &sc->bge_ldata.bge_tx_ring[idx];
 5327                         d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
 5328                         d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
 5329                         d->bge_len = segs[i].ds_len;
 5330                         d->bge_flags = csum_flags;
 5331                         d->bge_vlan_tag = vlan_tag;
 5332                         d->bge_mss = mss;
 5333                         if (i == nsegs - 1)
 5334                                 break;
 5335                         BGE_INC(idx, BGE_TX_RING_CNT);
 5336                 }
 5337         }
 5338 
 5339         /* Mark the last segment as end of packet... */
 5340         d->bge_flags |= BGE_TXBDFLAG_END;
 5341 
 5342         /*
 5343          * Insure that the map for this transmission
 5344          * is placed at the array index of the last descriptor
 5345          * in this chain.
 5346          */
 5347         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
 5348         sc->bge_cdata.bge_tx_dmamap[idx] = map;
 5349         sc->bge_cdata.bge_tx_chain[idx] = m;
 5350         sc->bge_txcnt += nsegs;
 5351 
 5352         BGE_INC(idx, BGE_TX_RING_CNT);
 5353         *txidx = idx;
 5354 
 5355         return (0);
 5356 }
 5357 
 5358 /*
 5359  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
 5360  * to the mbuf data regions directly in the transmit descriptors.
 5361  */
 5362 static void
 5363 bge_start_locked(if_t ifp)
 5364 {
 5365         struct bge_softc *sc;
 5366         struct mbuf *m_head;
 5367         uint32_t prodidx;
 5368         int count;
 5369 
 5370         sc = if_getsoftc(ifp);
 5371         BGE_LOCK_ASSERT(sc);
 5372 
 5373         if (!sc->bge_link ||
 5374             (if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
 5375             IFF_DRV_RUNNING)
 5376                 return;
 5377 
 5378         prodidx = sc->bge_tx_prodidx;
 5379 
 5380         for (count = 0; !if_sendq_empty(ifp);) {
 5381                 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
 5382                         if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
 5383                         break;
 5384                 }
 5385                 m_head = if_dequeue(ifp);
 5386                 if (m_head == NULL)
 5387                         break;
 5388 
 5389                 /*
 5390                  * Pack the data into the transmit ring. If we
 5391                  * don't have room, set the OACTIVE flag and wait
 5392                  * for the NIC to drain the ring.
 5393                  */
 5394                 if (bge_encap(sc, &m_head, &prodidx)) {
 5395                         if (m_head == NULL)
 5396                                 break;
 5397                         if_sendq_prepend(ifp, m_head);
 5398                         if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
 5399                         break;
 5400                 }
 5401                 ++count;
 5402 
 5403                 /*
 5404                  * If there's a BPF listener, bounce a copy of this frame
 5405                  * to him.
 5406                  */
 5407                 if_bpfmtap(ifp, m_head);
 5408         }
 5409 
 5410         if (count > 0)
 5411                 bge_start_tx(sc, prodidx);
 5412 }
 5413 
 5414 static void
 5415 bge_start_tx(struct bge_softc *sc, uint32_t prodidx)
 5416 {
 5417 
 5418         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
 5419             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
 5420         /* Transmit. */
 5421         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
 5422         /* 5700 b2 errata */
 5423         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
 5424                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
 5425 
 5426         sc->bge_tx_prodidx = prodidx;
 5427 
 5428         /* Set a timeout in case the chip goes out to lunch. */
 5429         sc->bge_timer = BGE_TX_TIMEOUT;
 5430 }
 5431 
 5432 /*
 5433  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
 5434  * to the mbuf data regions directly in the transmit descriptors.
 5435  */
 5436 static void
 5437 bge_start(if_t ifp)
 5438 {
 5439         struct bge_softc *sc;
 5440 
 5441         sc = if_getsoftc(ifp);
 5442         BGE_LOCK(sc);
 5443         bge_start_locked(ifp);
 5444         BGE_UNLOCK(sc);
 5445 }
 5446 
 5447 static void
 5448 bge_init_locked(struct bge_softc *sc)
 5449 {
 5450         if_t ifp;
 5451         uint16_t *m;
 5452         uint32_t mode;
 5453 
 5454         BGE_LOCK_ASSERT(sc);
 5455 
 5456         ifp = sc->bge_ifp;
 5457 
 5458         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
 5459                 return;
 5460 
 5461         /* Cancel pending I/O and flush buffers. */
 5462         bge_stop(sc);
 5463 
 5464         bge_stop_fw(sc);
 5465         bge_sig_pre_reset(sc, BGE_RESET_START);
 5466         bge_reset(sc);
 5467         bge_sig_legacy(sc, BGE_RESET_START);
 5468         bge_sig_post_reset(sc, BGE_RESET_START);
 5469 
 5470         bge_chipinit(sc);
 5471 
 5472         /*
 5473          * Init the various state machines, ring
 5474          * control blocks and firmware.
 5475          */
 5476         if (bge_blockinit(sc)) {
 5477                 device_printf(sc->bge_dev, "initialization failure\n");
 5478                 return;
 5479         }
 5480 
 5481         ifp = sc->bge_ifp;
 5482 
 5483         /* Specify MTU. */
 5484         CSR_WRITE_4(sc, BGE_RX_MTU, if_getmtu(ifp) +
 5485             ETHER_HDR_LEN + ETHER_CRC_LEN +
 5486             (if_getcapenable(ifp) & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
 5487 
 5488         /* Load our MAC address. */
 5489         m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
 5490         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
 5491         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
 5492 
 5493         /* Program promiscuous mode. */
 5494         bge_setpromisc(sc);
 5495 
 5496         /* Program multicast filter. */
 5497         bge_setmulti(sc);
 5498 
 5499         /* Program VLAN tag stripping. */
 5500         bge_setvlan(sc);
 5501 
 5502         /* Override UDP checksum offloading. */
 5503         if (sc->bge_forced_udpcsum == 0)
 5504                 sc->bge_csum_features &= ~CSUM_UDP;
 5505         else
 5506                 sc->bge_csum_features |= CSUM_UDP;
 5507         if (if_getcapabilities(ifp) & IFCAP_TXCSUM &&
 5508             if_getcapenable(ifp) & IFCAP_TXCSUM) {
 5509                 if_sethwassistbits(ifp, 0, (BGE_CSUM_FEATURES | CSUM_UDP));
 5510                 if_sethwassistbits(ifp, sc->bge_csum_features, 0);
 5511         }
 5512 
 5513         /* Init RX ring. */
 5514         if (bge_init_rx_ring_std(sc) != 0) {
 5515                 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
 5516                 bge_stop(sc);
 5517                 return;
 5518         }
 5519 
 5520         /*
 5521          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
 5522          * memory to insure that the chip has in fact read the first
 5523          * entry of the ring.
 5524          */
 5525         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
 5526                 uint32_t                v, i;
 5527                 for (i = 0; i < 10; i++) {
 5528                         DELAY(20);
 5529                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
 5530                         if (v == (MCLBYTES - ETHER_ALIGN))
 5531                                 break;
 5532                 }
 5533                 if (i == 10)
 5534                         device_printf (sc->bge_dev,
 5535                             "5705 A0 chip failed to load RX ring\n");
 5536         }
 5537 
 5538         /* Init jumbo RX ring. */
 5539         if (BGE_IS_JUMBO_CAPABLE(sc) &&
 5540             if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN + 
 5541             ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)) {
 5542                 if (bge_init_rx_ring_jumbo(sc) != 0) {
 5543                         device_printf(sc->bge_dev,
 5544                             "no memory for jumbo Rx buffers.\n");
 5545                         bge_stop(sc);
 5546                         return;
 5547                 }
 5548         }
 5549 
 5550         /* Init our RX return ring index. */
 5551         sc->bge_rx_saved_considx = 0;
 5552 
 5553         /* Init our RX/TX stat counters. */
 5554         sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
 5555 
 5556         /* Init TX ring. */
 5557         bge_init_tx_ring(sc);
 5558 
 5559         /* Enable TX MAC state machine lockup fix. */
 5560         mode = CSR_READ_4(sc, BGE_TX_MODE);
 5561         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
 5562                 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
 5563         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
 5564             sc->bge_asicrev == BGE_ASICREV_BCM5762) {
 5565                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
 5566                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
 5567                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
 5568         }
 5569         /* Turn on transmitter. */
 5570         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
 5571         DELAY(100);
 5572 
 5573         /* Turn on receiver. */
 5574         mode = CSR_READ_4(sc, BGE_RX_MODE);
 5575         if (BGE_IS_5755_PLUS(sc))
 5576                 mode |= BGE_RXMODE_IPV6_ENABLE;
 5577         if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
 5578                 mode |= BGE_RXMODE_IPV4_FRAG_FIX;
 5579         CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE);
 5580         DELAY(10);
 5581 
 5582         /*
 5583          * Set the number of good frames to receive after RX MBUF
 5584          * Low Watermark has been reached. After the RX MAC receives
 5585          * this number of frames, it will drop subsequent incoming
 5586          * frames until the MBUF High Watermark is reached.
 5587          */
 5588         if (BGE_IS_57765_PLUS(sc))
 5589                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
 5590         else
 5591                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
 5592 
 5593         /* Clear MAC statistics. */
 5594         if (BGE_IS_5705_PLUS(sc))
 5595                 bge_stats_clear_regs(sc);
 5596 
 5597         /* Tell firmware we're alive. */
 5598         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
 5599 
 5600 #ifdef DEVICE_POLLING
 5601         /* Disable interrupts if we are polling. */
 5602         if (if_getcapenable(ifp) & IFCAP_POLLING) {
 5603                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
 5604                     BGE_PCIMISCCTL_MASK_PCI_INTR);
 5605                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
 5606         } else
 5607 #endif
 5608 
 5609         /* Enable host interrupts. */
 5610         {
 5611         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
 5612         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
 5613         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
 5614         }
 5615 
 5616         if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
 5617         if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
 5618 
 5619         bge_ifmedia_upd_locked(ifp);
 5620 
 5621         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
 5622 }
 5623 
 5624 static void
 5625 bge_init(void *xsc)
 5626 {
 5627         struct bge_softc *sc = xsc;
 5628 
 5629         BGE_LOCK(sc);
 5630         bge_init_locked(sc);
 5631         BGE_UNLOCK(sc);
 5632 }
 5633 
 5634 /*
 5635  * Set media options.
 5636  */
 5637 static int
 5638 bge_ifmedia_upd(if_t ifp)
 5639 {
 5640         struct bge_softc *sc = if_getsoftc(ifp);
 5641         int res;
 5642 
 5643         BGE_LOCK(sc);
 5644         res = bge_ifmedia_upd_locked(ifp);
 5645         BGE_UNLOCK(sc);
 5646 
 5647         return (res);
 5648 }
 5649 
 5650 static int
 5651 bge_ifmedia_upd_locked(if_t ifp)
 5652 {
 5653         struct bge_softc *sc = if_getsoftc(ifp);
 5654         struct mii_data *mii;
 5655         struct mii_softc *miisc;
 5656         struct ifmedia *ifm;
 5657 
 5658         BGE_LOCK_ASSERT(sc);
 5659 
 5660         ifm = &sc->bge_ifmedia;
 5661 
 5662         /* If this is a 1000baseX NIC, enable the TBI port. */
 5663         if (sc->bge_flags & BGE_FLAG_TBI) {
 5664                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
 5665                         return (EINVAL);
 5666                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
 5667                 case IFM_AUTO:
 5668                         /*
 5669                          * The BCM5704 ASIC appears to have a special
 5670                          * mechanism for programming the autoneg
 5671                          * advertisement registers in TBI mode.
 5672                          */
 5673                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
 5674                                 uint32_t sgdig;
 5675                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
 5676                                 if (sgdig & BGE_SGDIGSTS_DONE) {
 5677                                         CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
 5678                                         sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
 5679                                         sgdig |= BGE_SGDIGCFG_AUTO |
 5680                                             BGE_SGDIGCFG_PAUSE_CAP |
 5681                                             BGE_SGDIGCFG_ASYM_PAUSE;
 5682                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG,
 5683                                             sgdig | BGE_SGDIGCFG_SEND);
 5684                                         DELAY(5);
 5685                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
 5686                                 }
 5687                         }
 5688                         break;
 5689                 case IFM_1000_SX:
 5690                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
 5691                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
 5692                                     BGE_MACMODE_HALF_DUPLEX);
 5693                         } else {
 5694                                 BGE_SETBIT(sc, BGE_MAC_MODE,
 5695                                     BGE_MACMODE_HALF_DUPLEX);
 5696                         }
 5697                         DELAY(40);
 5698                         break;
 5699                 default:
 5700                         return (EINVAL);
 5701                 }
 5702                 return (0);
 5703         }
 5704 
 5705         sc->bge_link_evt++;
 5706         mii = device_get_softc(sc->bge_miibus);
 5707         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 5708                 PHY_RESET(miisc);
 5709         mii_mediachg(mii);
 5710 
 5711         /*
 5712          * Force an interrupt so that we will call bge_link_upd
 5713          * if needed and clear any pending link state attention.
 5714          * Without this we are not getting any further interrupts
 5715          * for link state changes and thus will not UP the link and
 5716          * not be able to send in bge_start_locked. The only
 5717          * way to get things working was to receive a packet and
 5718          * get an RX intr.
 5719          * bge_tick should help for fiber cards and we might not
 5720          * need to do this here if BGE_FLAG_TBI is set but as
 5721          * we poll for fiber anyway it should not harm.
 5722          */
 5723         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
 5724             sc->bge_flags & BGE_FLAG_5788)
 5725                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
 5726         else
 5727                 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
 5728 
 5729         return (0);
 5730 }
 5731 
 5732 /*
 5733  * Report current media status.
 5734  */
 5735 static void
 5736 bge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
 5737 {
 5738         struct bge_softc *sc = if_getsoftc(ifp);
 5739         struct mii_data *mii;
 5740 
 5741         BGE_LOCK(sc);
 5742 
 5743         if ((if_getflags(ifp) & IFF_UP) == 0) {
 5744                 BGE_UNLOCK(sc);
 5745                 return;
 5746         }
 5747         if (sc->bge_flags & BGE_FLAG_TBI) {
 5748                 ifmr->ifm_status = IFM_AVALID;
 5749                 ifmr->ifm_active = IFM_ETHER;
 5750                 if (CSR_READ_4(sc, BGE_MAC_STS) &
 5751                     BGE_MACSTAT_TBI_PCS_SYNCHED)
 5752                         ifmr->ifm_status |= IFM_ACTIVE;
 5753                 else {
 5754                         ifmr->ifm_active |= IFM_NONE;
 5755                         BGE_UNLOCK(sc);
 5756                         return;
 5757                 }
 5758                 ifmr->ifm_active |= IFM_1000_SX;
 5759                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
 5760                         ifmr->ifm_active |= IFM_HDX;
 5761                 else
 5762                         ifmr->ifm_active |= IFM_FDX;
 5763                 BGE_UNLOCK(sc);
 5764                 return;
 5765         }
 5766 
 5767         mii = device_get_softc(sc->bge_miibus);
 5768         mii_pollstat(mii);
 5769         ifmr->ifm_active = mii->mii_media_active;
 5770         ifmr->ifm_status = mii->mii_media_status;
 5771 
 5772         BGE_UNLOCK(sc);
 5773 }
 5774 
 5775 static int
 5776 bge_ioctl(if_t ifp, u_long command, caddr_t data)
 5777 {
 5778         struct bge_softc *sc = if_getsoftc(ifp);
 5779         struct ifreq *ifr = (struct ifreq *) data;
 5780         struct mii_data *mii;
 5781         int flags, mask, error = 0;
 5782 
 5783         switch (command) {
 5784         case SIOCSIFMTU:
 5785                 if (BGE_IS_JUMBO_CAPABLE(sc) ||
 5786                     (sc->bge_flags & BGE_FLAG_JUMBO_STD)) {
 5787                         if (ifr->ifr_mtu < ETHERMIN ||
 5788                             ifr->ifr_mtu > BGE_JUMBO_MTU) {
 5789                                 error = EINVAL;
 5790                                 break;
 5791                         }
 5792                 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) {
 5793                         error = EINVAL;
 5794                         break;
 5795                 }
 5796                 BGE_LOCK(sc);
 5797                 if (if_getmtu(ifp) != ifr->ifr_mtu) {
 5798                         if_setmtu(ifp, ifr->ifr_mtu);
 5799                         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
 5800                                 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
 5801                                 bge_init_locked(sc);
 5802                         }
 5803                 }
 5804                 BGE_UNLOCK(sc);
 5805                 break;
 5806         case SIOCSIFFLAGS:
 5807                 BGE_LOCK(sc);
 5808                 if (if_getflags(ifp) & IFF_UP) {
 5809                         /*
 5810                          * If only the state of the PROMISC flag changed,
 5811                          * then just use the 'set promisc mode' command
 5812                          * instead of reinitializing the entire NIC. Doing
 5813                          * a full re-init means reloading the firmware and
 5814                          * waiting for it to start up, which may take a
 5815                          * second or two.  Similarly for ALLMULTI.
 5816                          */
 5817                         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
 5818                                 flags = if_getflags(ifp) ^ sc->bge_if_flags;
 5819                                 if (flags & IFF_PROMISC)
 5820                                         bge_setpromisc(sc);
 5821                                 if (flags & IFF_ALLMULTI)
 5822                                         bge_setmulti(sc);
 5823                         } else
 5824                                 bge_init_locked(sc);
 5825                 } else {
 5826                         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
 5827                                 bge_stop(sc);
 5828                         }
 5829                 }
 5830                 sc->bge_if_flags = if_getflags(ifp);
 5831                 BGE_UNLOCK(sc);
 5832                 error = 0;
 5833                 break;
 5834         case SIOCADDMULTI:
 5835         case SIOCDELMULTI:
 5836                 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
 5837                         BGE_LOCK(sc);
 5838                         bge_setmulti(sc);
 5839                         BGE_UNLOCK(sc);
 5840                         error = 0;
 5841                 }
 5842                 break;
 5843         case SIOCSIFMEDIA:
 5844         case SIOCGIFMEDIA:
 5845                 if (sc->bge_flags & BGE_FLAG_TBI) {
 5846                         error = ifmedia_ioctl(ifp, ifr,
 5847                             &sc->bge_ifmedia, command);
 5848                 } else {
 5849                         mii = device_get_softc(sc->bge_miibus);
 5850                         error = ifmedia_ioctl(ifp, ifr,
 5851                             &mii->mii_media, command);
 5852                 }
 5853                 break;
 5854         case SIOCSIFCAP:
 5855                 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
 5856 #ifdef DEVICE_POLLING
 5857                 if (mask & IFCAP_POLLING) {
 5858                         if (ifr->ifr_reqcap & IFCAP_POLLING) {
 5859                                 error = ether_poll_register(bge_poll, ifp);
 5860                                 if (error)
 5861                                         return (error);
 5862                                 BGE_LOCK(sc);
 5863                                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
 5864                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
 5865                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
 5866                                 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
 5867                                 BGE_UNLOCK(sc);
 5868                         } else {
 5869                                 error = ether_poll_deregister(ifp);
 5870                                 /* Enable interrupt even in error case */
 5871                                 BGE_LOCK(sc);
 5872                                 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
 5873                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
 5874                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
 5875                                 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
 5876                                 BGE_UNLOCK(sc);
 5877                         }
 5878                 }
 5879 #endif
 5880                 if ((mask & IFCAP_TXCSUM) != 0 &&
 5881                     (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
 5882                         if_togglecapenable(ifp, IFCAP_TXCSUM);
 5883                         if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
 5884                                 if_sethwassistbits(ifp,
 5885                                     sc->bge_csum_features, 0);
 5886                         else
 5887                                 if_sethwassistbits(ifp, 0,
 5888                                     sc->bge_csum_features);
 5889                 }
 5890 
 5891                 if ((mask & IFCAP_RXCSUM) != 0 &&
 5892                     (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0)
 5893                         if_togglecapenable(ifp, IFCAP_RXCSUM);
 5894 
 5895                 if ((mask & IFCAP_TSO4) != 0 &&
 5896                     (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
 5897                         if_togglecapenable(ifp, IFCAP_TSO4);
 5898                         if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
 5899                                 if_sethwassistbits(ifp, CSUM_TSO, 0);
 5900                         else
 5901                                 if_sethwassistbits(ifp, 0, CSUM_TSO);
 5902                 }
 5903 
 5904                 if (mask & IFCAP_VLAN_MTU) {
 5905                         if_togglecapenable(ifp, IFCAP_VLAN_MTU);
 5906                         if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
 5907                         bge_init(sc);
 5908                 }
 5909 
 5910                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
 5911                     (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
 5912                         if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
 5913                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
 5914                     (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
 5915                         if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
 5916                         if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
 5917                                 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO);
 5918                         BGE_LOCK(sc);
 5919                         bge_setvlan(sc);
 5920                         BGE_UNLOCK(sc);
 5921                 }
 5922 #ifdef VLAN_CAPABILITIES
 5923                 if_vlancap(ifp);
 5924 #endif
 5925                 break;
 5926         default:
 5927                 error = ether_ioctl(ifp, command, data);
 5928                 break;
 5929         }
 5930 
 5931         return (error);
 5932 }
 5933 
 5934 static void
 5935 bge_watchdog(struct bge_softc *sc)
 5936 {
 5937         if_t ifp;
 5938         uint32_t status;
 5939 
 5940         BGE_LOCK_ASSERT(sc);
 5941 
 5942         if (sc->bge_timer == 0 || --sc->bge_timer)
 5943                 return;
 5944 
 5945         /* If pause frames are active then don't reset the hardware. */
 5946         if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) {
 5947                 status = CSR_READ_4(sc, BGE_RX_STS);
 5948                 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) {
 5949                         /*
 5950                          * If link partner has us in XOFF state then wait for
 5951                          * the condition to clear.
 5952                          */
 5953                         CSR_WRITE_4(sc, BGE_RX_STS, status);
 5954                         sc->bge_timer = BGE_TX_TIMEOUT;
 5955                         return;
 5956                 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 &&
 5957                     (status & BGE_RXSTAT_RCVD_XON) != 0) {
 5958                         /*
 5959                          * If link partner has us in XOFF state then wait for
 5960                          * the condition to clear.
 5961                          */
 5962                         CSR_WRITE_4(sc, BGE_RX_STS, status);
 5963                         sc->bge_timer = BGE_TX_TIMEOUT;
 5964                         return;
 5965                 }
 5966                 /*
 5967                  * Any other condition is unexpected and the controller
 5968                  * should be reset.
 5969                  */
 5970         }
 5971 
 5972         ifp = sc->bge_ifp;
 5973 
 5974         if_printf(ifp, "watchdog timeout -- resetting\n");
 5975 
 5976         if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
 5977         bge_init_locked(sc);
 5978 
 5979         if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
 5980 }
 5981 
 5982 static void
 5983 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
 5984 {
 5985         int i;
 5986 
 5987         BGE_CLRBIT(sc, reg, bit);
 5988 
 5989         for (i = 0; i < BGE_TIMEOUT; i++) {
 5990                 if ((CSR_READ_4(sc, reg) & bit) == 0)
 5991                         return;
 5992                 DELAY(100);
 5993         }
 5994 }
 5995 
 5996 /*
 5997  * Stop the adapter and free any mbufs allocated to the
 5998  * RX and TX lists.
 5999  */
 6000 static void
 6001 bge_stop(struct bge_softc *sc)
 6002 {
 6003         if_t ifp;
 6004 
 6005         BGE_LOCK_ASSERT(sc);
 6006 
 6007         ifp = sc->bge_ifp;
 6008 
 6009         callout_stop(&sc->bge_stat_ch);
 6010 
 6011         /* Disable host interrupts. */
 6012         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
 6013         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
 6014 
 6015         /*
 6016          * Tell firmware we're shutting down.
 6017          */
 6018         bge_stop_fw(sc);
 6019         bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
 6020 
 6021         /*
 6022          * Disable all of the receiver blocks.
 6023          */
 6024         bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
 6025         bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
 6026         bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
 6027         if (BGE_IS_5700_FAMILY(sc))
 6028                 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
 6029         bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
 6030         bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
 6031         bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
 6032 
 6033         /*
 6034          * Disable all of the transmit blocks.
 6035          */
 6036         bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
 6037         bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
 6038         bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
 6039         bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
 6040         bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
 6041         if (BGE_IS_5700_FAMILY(sc))
 6042                 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
 6043         bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
 6044 
 6045         /*
 6046          * Shut down all of the memory managers and related
 6047          * state machines.
 6048          */
 6049         bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
 6050         bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
 6051         if (BGE_IS_5700_FAMILY(sc))
 6052                 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
 6053 
 6054         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
 6055         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
 6056         if (!(BGE_IS_5705_PLUS(sc))) {
 6057                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
 6058                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
 6059         }
 6060         /* Update MAC statistics. */
 6061         if (BGE_IS_5705_PLUS(sc))
 6062                 bge_stats_update_regs(sc);
 6063 
 6064         bge_reset(sc);
 6065         bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
 6066         bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
 6067 
 6068         /*
 6069          * Keep the ASF firmware running if up.
 6070          */
 6071         if (sc->bge_asf_mode & ASF_STACKUP)
 6072                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
 6073         else
 6074                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
 6075 
 6076         /* Free the RX lists. */
 6077         bge_free_rx_ring_std(sc);
 6078 
 6079         /* Free jumbo RX list. */
 6080         if (BGE_IS_JUMBO_CAPABLE(sc))
 6081                 bge_free_rx_ring_jumbo(sc);
 6082 
 6083         /* Free TX buffers. */
 6084         bge_free_tx_ring(sc);
 6085 
 6086         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
 6087 
 6088         /* Clear MAC's link state (PHY may still have link UP). */
 6089         if (bootverbose && sc->bge_link)
 6090                 if_printf(sc->bge_ifp, "link DOWN\n");
 6091         sc->bge_link = 0;
 6092 
 6093         if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
 6094 }
 6095 
 6096 /*
 6097  * Stop all chip I/O so that the kernel's probe routines don't
 6098  * get confused by errant DMAs when rebooting.
 6099  */
 6100 static int
 6101 bge_shutdown(device_t dev)
 6102 {
 6103         struct bge_softc *sc;
 6104 
 6105         sc = device_get_softc(dev);
 6106         BGE_LOCK(sc);
 6107         bge_stop(sc);
 6108         BGE_UNLOCK(sc);
 6109 
 6110         return (0);
 6111 }
 6112 
 6113 static int
 6114 bge_suspend(device_t dev)
 6115 {
 6116         struct bge_softc *sc;
 6117 
 6118         sc = device_get_softc(dev);
 6119         BGE_LOCK(sc);
 6120         bge_stop(sc);
 6121         BGE_UNLOCK(sc);
 6122 
 6123         return (0);
 6124 }
 6125 
 6126 static int
 6127 bge_resume(device_t dev)
 6128 {
 6129         struct bge_softc *sc;
 6130         if_t ifp;
 6131 
 6132         sc = device_get_softc(dev);
 6133         BGE_LOCK(sc);
 6134         ifp = sc->bge_ifp;
 6135         if (if_getflags(ifp) & IFF_UP) {
 6136                 bge_init_locked(sc);
 6137                 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
 6138                         bge_start_locked(ifp);
 6139         }
 6140         BGE_UNLOCK(sc);
 6141 
 6142         return (0);
 6143 }
 6144 
 6145 static void
 6146 bge_link_upd(struct bge_softc *sc)
 6147 {
 6148         struct mii_data *mii;
 6149         uint32_t link, status;
 6150 
 6151         BGE_LOCK_ASSERT(sc);
 6152 
 6153         /* Clear 'pending link event' flag. */
 6154         sc->bge_link_evt = 0;
 6155 
 6156         /*
 6157          * Process link state changes.
 6158          * Grrr. The link status word in the status block does
 6159          * not work correctly on the BCM5700 rev AX and BX chips,
 6160          * according to all available information. Hence, we have
 6161          * to enable MII interrupts in order to properly obtain
 6162          * async link changes. Unfortunately, this also means that
 6163          * we have to read the MAC status register to detect link
 6164          * changes, thereby adding an additional register access to
 6165          * the interrupt handler.
 6166          *
 6167          * XXX: perhaps link state detection procedure used for
 6168          * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
 6169          */
 6170 
 6171         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
 6172             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
 6173                 status = CSR_READ_4(sc, BGE_MAC_STS);
 6174                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
 6175                         mii = device_get_softc(sc->bge_miibus);
 6176                         mii_pollstat(mii);
 6177                         if (!sc->bge_link &&
 6178                             mii->mii_media_status & IFM_ACTIVE &&
 6179                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
 6180                                 sc->bge_link++;
 6181                                 if (bootverbose)
 6182                                         if_printf(sc->bge_ifp, "link UP\n");
 6183                         } else if (sc->bge_link &&
 6184                             (!(mii->mii_media_status & IFM_ACTIVE) ||
 6185                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
 6186                                 sc->bge_link = 0;
 6187                                 if (bootverbose)
 6188                                         if_printf(sc->bge_ifp, "link DOWN\n");
 6189                         }
 6190 
 6191                         /* Clear the interrupt. */
 6192                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
 6193                             BGE_EVTENB_MI_INTERRUPT);
 6194                         bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr,
 6195                             BRGPHY_MII_ISR);
 6196                         bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr,
 6197                             BRGPHY_MII_IMR, BRGPHY_INTRS);
 6198                 }
 6199                 return;
 6200         }
 6201 
 6202         if (sc->bge_flags & BGE_FLAG_TBI) {
 6203                 status = CSR_READ_4(sc, BGE_MAC_STS);
 6204                 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
 6205                         if (!sc->bge_link) {
 6206                                 sc->bge_link++;
 6207                                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
 6208                                         BGE_CLRBIT(sc, BGE_MAC_MODE,
 6209                                             BGE_MACMODE_TBI_SEND_CFGS);
 6210                                         DELAY(40);
 6211                                 }
 6212                                 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
 6213                                 if (bootverbose)
 6214                                         if_printf(sc->bge_ifp, "link UP\n");
 6215                                 if_link_state_change(sc->bge_ifp,
 6216                                     LINK_STATE_UP);
 6217                         }
 6218                 } else if (sc->bge_link) {
 6219                         sc->bge_link = 0;
 6220                         if (bootverbose)
 6221                                 if_printf(sc->bge_ifp, "link DOWN\n");
 6222                         if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
 6223                 }
 6224         } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
 6225                 /*
 6226                  * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
 6227                  * in status word always set. Workaround this bug by reading
 6228                  * PHY link status directly.
 6229                  */
 6230                 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
 6231 
 6232                 if (link != sc->bge_link ||
 6233                     sc->bge_asicrev == BGE_ASICREV_BCM5700) {
 6234                         mii = device_get_softc(sc->bge_miibus);
 6235                         mii_pollstat(mii);
 6236                         if (!sc->bge_link &&
 6237                             mii->mii_media_status & IFM_ACTIVE &&
 6238                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
 6239                                 sc->bge_link++;
 6240                                 if (bootverbose)
 6241                                         if_printf(sc->bge_ifp, "link UP\n");
 6242                         } else if (sc->bge_link &&
 6243                             (!(mii->mii_media_status & IFM_ACTIVE) ||
 6244                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
 6245                                 sc->bge_link = 0;
 6246                                 if (bootverbose)
 6247                                         if_printf(sc->bge_ifp, "link DOWN\n");
 6248                         }
 6249                 }
 6250         } else {
 6251                 /*
 6252                  * For controllers that call mii_tick, we have to poll
 6253                  * link status.
 6254                  */
 6255                 mii = device_get_softc(sc->bge_miibus);
 6256                 mii_pollstat(mii);
 6257                 bge_miibus_statchg(sc->bge_dev);
 6258         }
 6259 
 6260         /* Disable MAC attention when link is up. */
 6261         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
 6262             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
 6263             BGE_MACSTAT_LINK_CHANGED);
 6264 }
 6265 
 6266 static void
 6267 bge_add_sysctls(struct bge_softc *sc)
 6268 {
 6269         struct sysctl_ctx_list *ctx;
 6270         struct sysctl_oid_list *children;
 6271         int unit;
 6272 
 6273         ctx = device_get_sysctl_ctx(sc->bge_dev);
 6274         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
 6275 
 6276 #ifdef BGE_REGISTER_DEBUG
 6277         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
 6278             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
 6279             "Debug Information");
 6280 
 6281         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
 6282             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
 6283             "MAC Register Read");
 6284 
 6285         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read",
 6286             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I",
 6287             "APE Register Read");
 6288 
 6289         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
 6290             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
 6291             "Memory Read");
 6292 
 6293 #endif
 6294 
 6295         unit = device_get_unit(sc->bge_dev);
 6296         /*
 6297          * A common design characteristic for many Broadcom client controllers
 6298          * is that they only support a single outstanding DMA read operation
 6299          * on the PCIe bus. This means that it will take twice as long to fetch
 6300          * a TX frame that is split into header and payload buffers as it does
 6301          * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
 6302          * these controllers, coalescing buffers to reduce the number of memory
 6303          * reads is effective way to get maximum performance(about 940Mbps).
 6304          * Without collapsing TX buffers the maximum TCP bulk transfer
 6305          * performance is about 850Mbps. However forcing coalescing mbufs
 6306          * consumes a lot of CPU cycles, so leave it off by default.
 6307          */
 6308         sc->bge_forced_collapse = 0;
 6309         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
 6310             CTLFLAG_RWTUN, &sc->bge_forced_collapse, 0,
 6311             "Number of fragmented TX buffers of a frame allowed before "
 6312             "forced collapsing");
 6313 
 6314         sc->bge_msi = 1;
 6315         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi",
 6316             CTLFLAG_RDTUN, &sc->bge_msi, 0, "Enable MSI");
 6317 
 6318         /*
 6319          * It seems all Broadcom controllers have a bug that can generate UDP
 6320          * datagrams with checksum value 0 when TX UDP checksum offloading is
 6321          * enabled.  Generating UDP checksum value 0 is RFC 768 violation.
 6322          * Even though the probability of generating such UDP datagrams is
 6323          * low, I don't want to see FreeBSD boxes to inject such datagrams
 6324          * into network so disable UDP checksum offloading by default.  Users
 6325          * still override this behavior by setting a sysctl variable,
 6326          * dev.bge.0.forced_udpcsum.
 6327          */
 6328         sc->bge_forced_udpcsum = 0;
 6329         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum",
 6330             CTLFLAG_RWTUN, &sc->bge_forced_udpcsum, 0,
 6331             "Enable UDP checksum offloading even if controller can "
 6332             "generate UDP checksum value 0");
 6333 
 6334         if (BGE_IS_5705_PLUS(sc))
 6335                 bge_add_sysctl_stats_regs(sc, ctx, children);
 6336         else
 6337                 bge_add_sysctl_stats(sc, ctx, children);
 6338 }
 6339 
 6340 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
 6341         SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
 6342             sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
 6343             desc)
 6344 
 6345 static void
 6346 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
 6347     struct sysctl_oid_list *parent)
 6348 {
 6349         struct sysctl_oid *tree;
 6350         struct sysctl_oid_list *children, *schildren;
 6351 
 6352         tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
 6353             NULL, "BGE Statistics");
 6354         schildren = children = SYSCTL_CHILDREN(tree);
 6355         BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
 6356             children, COSFramesDroppedDueToFilters,
 6357             "FramesDroppedDueToFilters");
 6358         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
 6359             children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
 6360         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
 6361             children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
 6362         BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
 6363             children, nicNoMoreRxBDs, "NoMoreRxBDs");
 6364         BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
 6365             children, ifInDiscards, "InputDiscards");
 6366         BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
 6367             children, ifInErrors, "InputErrors");
 6368         BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
 6369             children, nicRecvThresholdHit, "RecvThresholdHit");
 6370         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
 6371             children, nicDmaReadQueueFull, "DmaReadQueueFull");
 6372         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
 6373             children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
 6374         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
 6375             children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
 6376         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
 6377             children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
 6378         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
 6379             children, nicRingStatusUpdate, "RingStatusUpdate");
 6380         BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
 6381             children, nicInterrupts, "Interrupts");
 6382         BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
 6383             children, nicAvoidedInterrupts, "AvoidedInterrupts");
 6384         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
 6385             children, nicSendThresholdHit, "SendThresholdHit");
 6386 
 6387         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
 6388             NULL, "BGE RX Statistics");
 6389         children = SYSCTL_CHILDREN(tree);
 6390         BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
 6391             children, rxstats.ifHCInOctets, "ifHCInOctets");
 6392         BGE_SYSCTL_STAT(sc, ctx, "Fragments",
 6393             children, rxstats.etherStatsFragments, "Fragments");
 6394         BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
 6395             children, rxstats.ifHCInUcastPkts, "UnicastPkts");
 6396         BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
 6397             children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
 6398         BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
 6399             children, rxstats.dot3StatsFCSErrors, "FCSErrors");
 6400         BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
 6401             children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
 6402         BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
 6403             children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
 6404         BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
 6405             children, rxstats.xoffPauseFramesReceived,
 6406             "xoffPauseFramesReceived");
 6407         BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
 6408             children, rxstats.macControlFramesReceived,
 6409             "ControlFramesReceived");
 6410         BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
 6411             children, rxstats.xoffStateEntered, "xoffStateEntered");
 6412         BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
 6413             children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
 6414         BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
 6415             children, rxstats.etherStatsJabbers, "Jabbers");
 6416         BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
 6417             children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
 6418         BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
 6419             children, rxstats.inRangeLengthError, "inRangeLengthError");
 6420         BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
 6421             children, rxstats.outRangeLengthError, "outRangeLengthError");
 6422 
 6423         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
 6424             NULL, "BGE TX Statistics");
 6425         children = SYSCTL_CHILDREN(tree);
 6426         BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
 6427             children, txstats.ifHCOutOctets, "ifHCOutOctets");
 6428         BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
 6429             children, txstats.etherStatsCollisions, "Collisions");
 6430         BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
 6431             children, txstats.outXonSent, "XonSent");
 6432         BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
 6433             children, txstats.outXoffSent, "XoffSent");
 6434         BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
 6435             children, txstats.flowControlDone, "flowControlDone");
 6436         BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
 6437             children, txstats.dot3StatsInternalMacTransmitErrors,
 6438             "InternalMacTransmitErrors");
 6439         BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
 6440             children, txstats.dot3StatsSingleCollisionFrames,
 6441             "SingleCollisionFrames");
 6442         BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
 6443             children, txstats.dot3StatsMultipleCollisionFrames,
 6444             "MultipleCollisionFrames");
 6445         BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
 6446             children, txstats.dot3StatsDeferredTransmissions,
 6447             "DeferredTransmissions");
 6448         BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
 6449             children, txstats.dot3StatsExcessiveCollisions,
 6450             "ExcessiveCollisions");
 6451         BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
 6452             children, txstats.dot3StatsLateCollisions,
 6453             "LateCollisions");
 6454         BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
 6455             children, txstats.ifHCOutUcastPkts, "UnicastPkts");
 6456         BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
 6457             children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
 6458         BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
 6459             children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
 6460         BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
 6461             children, txstats.dot3StatsCarrierSenseErrors,
 6462             "CarrierSenseErrors");
 6463         BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
 6464             children, txstats.ifOutDiscards, "Discards");
 6465         BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
 6466             children, txstats.ifOutErrors, "Errors");
 6467 }
 6468 
 6469 #undef BGE_SYSCTL_STAT
 6470 
 6471 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d)    \
 6472             SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
 6473 
 6474 static void
 6475 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
 6476     struct sysctl_oid_list *parent)
 6477 {
 6478         struct sysctl_oid *tree;
 6479         struct sysctl_oid_list *child, *schild;
 6480         struct bge_mac_stats *stats;
 6481 
 6482         stats = &sc->bge_mac_stats;
 6483         tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
 6484             NULL, "BGE Statistics");
 6485         schild = child = SYSCTL_CHILDREN(tree);
 6486         BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters",
 6487             &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters");
 6488         BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull",
 6489             &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full");
 6490         BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull",
 6491             &stats->DmaWriteHighPriQueueFull,
 6492             "NIC DMA Write High Priority Queue Full");
 6493         BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs",
 6494             &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors");
 6495         BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards",
 6496             &stats->InputDiscards, "Discarded Input Frames");
 6497         BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors",
 6498             &stats->InputErrors, "Input Errors");
 6499         BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit",
 6500             &stats->RecvThresholdHit, "NIC Recv Threshold Hit");
 6501 
 6502         tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD,
 6503             NULL, "BGE RX Statistics");
 6504         child = SYSCTL_CHILDREN(tree);
 6505         BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets",
 6506             &stats->ifHCInOctets, "Inbound Octets");
 6507         BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments",
 6508             &stats->etherStatsFragments, "Fragments");
 6509         BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
 6510             &stats->ifHCInUcastPkts, "Inbound Unicast Packets");
 6511         BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
 6512             &stats->ifHCInMulticastPkts, "Inbound Multicast Packets");
 6513         BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
 6514             &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets");
 6515         BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors",
 6516             &stats->dot3StatsFCSErrors, "FCS Errors");
 6517         BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors",
 6518             &stats->dot3StatsAlignmentErrors, "Alignment Errors");
 6519         BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived",
 6520             &stats->xonPauseFramesReceived, "XON Pause Frames Received");
 6521         BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived",
 6522             &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received");
 6523         BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived",
 6524             &stats->macControlFramesReceived, "MAC Control Frames Received");
 6525         BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered",
 6526             &stats->xoffStateEntered, "XOFF State Entered");
 6527         BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong",
 6528             &stats->dot3StatsFramesTooLong, "Frames Too Long");
 6529         BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers",
 6530             &stats->etherStatsJabbers, "Jabbers");
 6531         BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts",
 6532             &stats->etherStatsUndersizePkts, "Undersized Packets");
 6533 
 6534         tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD,
 6535             NULL, "BGE TX Statistics");
 6536         child = SYSCTL_CHILDREN(tree);
 6537         BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets",
 6538             &stats->ifHCOutOctets, "Outbound Octets");
 6539         BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions",
 6540             &stats->etherStatsCollisions, "TX Collisions");
 6541         BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent",
 6542             &stats->outXonSent, "XON Sent");
 6543         BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent",
 6544             &stats->outXoffSent, "XOFF Sent");
 6545         BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors",
 6546             &stats->dot3StatsInternalMacTransmitErrors,
 6547             "Internal MAC TX Errors");
 6548         BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames",
 6549             &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames");
 6550         BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames",
 6551             &stats->dot3StatsMultipleCollisionFrames,
 6552             "Multiple Collision Frames");
 6553         BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions",
 6554             &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions");
 6555         BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions",
 6556             &stats->dot3StatsExcessiveCollisions, "Excessive Collisions");
 6557         BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions",
 6558             &stats->dot3StatsLateCollisions, "Late Collisions");
 6559         BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
 6560             &stats->ifHCOutUcastPkts, "Outbound Unicast Packets");
 6561         BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
 6562             &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets");
 6563         BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
 6564             &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets");
 6565 }
 6566 
 6567 #undef  BGE_SYSCTL_STAT_ADD64
 6568 
 6569 static int
 6570 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
 6571 {
 6572         struct bge_softc *sc;
 6573         uint32_t result;
 6574         int offset;
 6575 
 6576         sc = (struct bge_softc *)arg1;
 6577         offset = arg2;
 6578         result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
 6579             offsetof(bge_hostaddr, bge_addr_lo));
 6580         return (sysctl_handle_int(oidp, &result, 0, req));
 6581 }
 6582 
 6583 #ifdef BGE_REGISTER_DEBUG
 6584 static int
 6585 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
 6586 {
 6587         struct bge_softc *sc;
 6588         uint16_t *sbdata;
 6589         int error, result, sbsz;
 6590         int i, j;
 6591 
 6592         result = -1;
 6593         error = sysctl_handle_int(oidp, &result, 0, req);
 6594         if (error || (req->newptr == NULL))
 6595                 return (error);
 6596 
 6597         if (result == 1) {
 6598                 sc = (struct bge_softc *)arg1;
 6599 
 6600                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
 6601                     sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
 6602                         sbsz = BGE_STATUS_BLK_SZ;
 6603                 else
 6604                         sbsz = 32;
 6605                 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
 6606                 printf("Status Block:\n");
 6607                 BGE_LOCK(sc);
 6608                 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
 6609                     sc->bge_cdata.bge_status_map,
 6610                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 6611                 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) {
 6612                         printf("%06x:", i);
 6613                         for (j = 0; j < 8; j++)
 6614                                 printf(" %04x", sbdata[i++]);
 6615                         printf("\n");
 6616                 }
 6617 
 6618                 printf("Registers:\n");
 6619                 for (i = 0x800; i < 0xA00; ) {
 6620                         printf("%06x:", i);
 6621                         for (j = 0; j < 8; j++) {
 6622                                 printf(" %08x", CSR_READ_4(sc, i));
 6623                                 i += 4;
 6624                         }
 6625                         printf("\n");
 6626                 }
 6627                 BGE_UNLOCK(sc);
 6628 
 6629                 printf("Hardware Flags:\n");
 6630                 if (BGE_IS_5717_PLUS(sc))
 6631                         printf(" - 5717 Plus\n");
 6632                 if (BGE_IS_5755_PLUS(sc))
 6633                         printf(" - 5755 Plus\n");
 6634                 if (BGE_IS_575X_PLUS(sc))
 6635                         printf(" - 575X Plus\n");
 6636                 if (BGE_IS_5705_PLUS(sc))
 6637                         printf(" - 5705 Plus\n");
 6638                 if (BGE_IS_5714_FAMILY(sc))
 6639                         printf(" - 5714 Family\n");
 6640                 if (BGE_IS_5700_FAMILY(sc))
 6641                         printf(" - 5700 Family\n");
 6642                 if (sc->bge_flags & BGE_FLAG_JUMBO)
 6643                         printf(" - Supports Jumbo Frames\n");
 6644                 if (sc->bge_flags & BGE_FLAG_PCIX)
 6645                         printf(" - PCI-X Bus\n");
 6646                 if (sc->bge_flags & BGE_FLAG_PCIE)
 6647                         printf(" - PCI Express Bus\n");
 6648                 if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
 6649                         printf(" - No 3 LEDs\n");
 6650                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
 6651                         printf(" - RX Alignment Bug\n");
 6652         }
 6653 
 6654         return (error);
 6655 }
 6656 
 6657 static int
 6658 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
 6659 {
 6660         struct bge_softc *sc;
 6661         int error;
 6662         uint16_t result;
 6663         uint32_t val;
 6664 
 6665         result = -1;
 6666         error = sysctl_handle_int(oidp, &result, 0, req);
 6667         if (error || (req->newptr == NULL))
 6668                 return (error);
 6669 
 6670         if (result < 0x8000) {
 6671                 sc = (struct bge_softc *)arg1;
 6672                 val = CSR_READ_4(sc, result);
 6673                 printf("reg 0x%06X = 0x%08X\n", result, val);
 6674         }
 6675 
 6676         return (error);
 6677 }
 6678 
 6679 static int
 6680 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS)
 6681 {
 6682         struct bge_softc *sc;
 6683         int error;
 6684         uint16_t result;
 6685         uint32_t val;
 6686 
 6687         result = -1;
 6688         error = sysctl_handle_int(oidp, &result, 0, req);
 6689         if (error || (req->newptr == NULL))
 6690                 return (error);
 6691 
 6692         if (result < 0x8000) {
 6693                 sc = (struct bge_softc *)arg1;
 6694                 val = APE_READ_4(sc, result);
 6695                 printf("reg 0x%06X = 0x%08X\n", result, val);
 6696         }
 6697 
 6698         return (error);
 6699 }
 6700 
 6701 static int
 6702 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
 6703 {
 6704         struct bge_softc *sc;
 6705         int error;
 6706         uint16_t result;
 6707         uint32_t val;
 6708 
 6709         result = -1;
 6710         error = sysctl_handle_int(oidp, &result, 0, req);
 6711         if (error || (req->newptr == NULL))
 6712                 return (error);
 6713 
 6714         if (result < 0x8000) {
 6715                 sc = (struct bge_softc *)arg1;
 6716                 val = bge_readmem_ind(sc, result);
 6717                 printf("mem 0x%06X = 0x%08X\n", result, val);
 6718         }
 6719 
 6720         return (error);
 6721 }
 6722 #endif
 6723 
 6724 static int
 6725 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
 6726 {
 6727 #ifdef __sparc64__
 6728         if (sc->bge_flags & BGE_FLAG_EADDR)
 6729                 return (1);
 6730 
 6731         OF_getetheraddr(sc->bge_dev, ether_addr);
 6732         return (0);
 6733 #else
 6734         return (1);
 6735 #endif
 6736 }
 6737 
 6738 static int
 6739 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
 6740 {
 6741         uint32_t mac_addr;
 6742 
 6743         mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
 6744         if ((mac_addr >> 16) == 0x484b) {
 6745                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
 6746                 ether_addr[1] = (uint8_t)mac_addr;
 6747                 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
 6748                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
 6749                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
 6750                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
 6751                 ether_addr[5] = (uint8_t)mac_addr;
 6752                 return (0);
 6753         }
 6754         return (1);
 6755 }
 6756 
 6757 static int
 6758 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
 6759 {
 6760         int mac_offset = BGE_EE_MAC_OFFSET;
 6761 
 6762         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 6763                 mac_offset = BGE_EE_MAC_OFFSET_5906;
 6764 
 6765         return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
 6766             ETHER_ADDR_LEN));
 6767 }
 6768 
 6769 static int
 6770 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
 6771 {
 6772 
 6773         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 6774                 return (1);
 6775 
 6776         return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
 6777            ETHER_ADDR_LEN));
 6778 }
 6779 
 6780 static int
 6781 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
 6782 {
 6783         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
 6784                 /* NOTE: Order is critical */
 6785                 bge_get_eaddr_fw,
 6786                 bge_get_eaddr_mem,
 6787                 bge_get_eaddr_nvram,
 6788                 bge_get_eaddr_eeprom,
 6789                 NULL
 6790         };
 6791         const bge_eaddr_fcn_t *func;
 6792 
 6793         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
 6794                 if ((*func)(sc, eaddr) == 0)
 6795                         break;
 6796         }
 6797         return (*func == NULL ? ENXIO : 0);
 6798 }
 6799 
 6800 static uint64_t
 6801 bge_get_counter(if_t ifp, ift_counter cnt)
 6802 {
 6803         struct bge_softc *sc;
 6804         struct bge_mac_stats *stats;
 6805 
 6806         sc = if_getsoftc(ifp);
 6807         if (!BGE_IS_5705_PLUS(sc))
 6808                 return (if_get_counter_default(ifp, cnt));
 6809         stats = &sc->bge_mac_stats;
 6810 
 6811         switch (cnt) {
 6812         case IFCOUNTER_IERRORS:
 6813                 return (stats->NoMoreRxBDs + stats->InputDiscards +
 6814                     stats->InputErrors);
 6815         case IFCOUNTER_COLLISIONS:
 6816                 return (stats->etherStatsCollisions);
 6817         default:
 6818                 return (if_get_counter_default(ifp, cnt));
 6819         }
 6820 }
 6821 
 6822 #ifdef NETDUMP
 6823 static void
 6824 bge_netdump_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
 6825 {
 6826         struct bge_softc *sc;
 6827 
 6828         sc = if_getsoftc(ifp);
 6829         BGE_LOCK(sc);
 6830         *nrxr = sc->bge_return_ring_cnt;
 6831         *ncl = NETDUMP_MAX_IN_FLIGHT;
 6832         if ((sc->bge_flags & BGE_FLAG_JUMBO_STD) != 0 &&
 6833             (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
 6834             ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)))
 6835                 *clsize = MJUM9BYTES;
 6836         else
 6837                 *clsize = MCLBYTES;
 6838         BGE_UNLOCK(sc);
 6839 }
 6840 
 6841 static void
 6842 bge_netdump_event(if_t ifp __unused, enum netdump_ev event __unused)
 6843 {
 6844 }
 6845 
 6846 static int
 6847 bge_netdump_transmit(if_t ifp, struct mbuf *m)
 6848 {
 6849         struct bge_softc *sc;
 6850         uint32_t prodidx;
 6851         int error;
 6852 
 6853         sc = if_getsoftc(ifp);
 6854         if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
 6855             IFF_DRV_RUNNING)
 6856                 return (1);
 6857 
 6858         prodidx = sc->bge_tx_prodidx;
 6859         error = bge_encap(sc, &m, &prodidx);
 6860         if (error == 0)
 6861                 bge_start_tx(sc, prodidx);
 6862         return (error);
 6863 }
 6864 
 6865 static int
 6866 bge_netdump_poll(if_t ifp, int count)
 6867 {
 6868         struct bge_softc *sc;
 6869         uint32_t rx_prod, tx_cons;
 6870 
 6871         sc = if_getsoftc(ifp);
 6872         if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
 6873             IFF_DRV_RUNNING)
 6874                 return (1);
 6875 
 6876         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
 6877             sc->bge_cdata.bge_status_map,
 6878             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 6879 
 6880         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
 6881         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
 6882 
 6883         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
 6884             sc->bge_cdata.bge_status_map,
 6885             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 6886 
 6887         (void)bge_rxeof(sc, rx_prod, 0);
 6888         bge_txeof(sc, tx_cons);
 6889         return (0);
 6890 }
 6891 #endif /* NETDUMP */

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