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sys/dev/bge/if_bge.c
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1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 /* 40 * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver 41 * 42 * The Broadcom BCM5700 is based on technology originally developed by 43 * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet 44 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 45 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 46 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 47 * frames, highly configurable RX filtering, and 16 RX and TX queues 48 * (which, along with RX filter rules, can be used for QOS applications). 49 * Other features, such as TCP segmentation, may be available as part 50 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 51 * firmware images can be stored in hardware and need not be compiled 52 * into the driver. 53 * 54 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 55 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 56 * 57 * The BCM5701 is a single-chip solution incorporating both the BCM5700 58 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 59 * does not support external SSRAM. 60 * 61 * Broadcom also produces a variation of the BCM5700 under the "Altima" 62 * brand name, which is functionally similar but lacks PCI-X support. 63 * 64 * Without external SSRAM, you can only have at most 4 TX rings, 65 * and the use of the mini RX ring is disabled. This seems to imply 66 * that these features are simply not available on the BCM5701. As a 67 * result, this driver does not implement any support for the mini RX 68 * ring. 69 */ 70 71 #ifdef HAVE_KERNEL_OPTION_HEADERS 72 #include "opt_device_polling.h" 73 #endif 74 75 #include <sys/param.h> 76 #include <sys/endian.h> 77 #include <sys/systm.h> 78 #include <sys/sockio.h> 79 #include <sys/mbuf.h> 80 #include <sys/malloc.h> 81 #include <sys/kernel.h> 82 #include <sys/module.h> 83 #include <sys/socket.h> 84 #include <sys/sysctl.h> 85 #include <sys/taskqueue.h> 86 87 #include <net/debugnet.h> 88 #include <net/if.h> 89 #include <net/if_var.h> 90 #include <net/if_arp.h> 91 #include <net/ethernet.h> 92 #include <net/if_dl.h> 93 #include <net/if_media.h> 94 95 #include <net/bpf.h> 96 97 #include <net/if_types.h> 98 #include <net/if_vlan_var.h> 99 100 #include <netinet/in_systm.h> 101 #include <netinet/in.h> 102 #include <netinet/ip.h> 103 #include <netinet/tcp.h> 104 105 #include <machine/bus.h> 106 #include <machine/resource.h> 107 #include <sys/bus.h> 108 #include <sys/rman.h> 109 110 #include <dev/mii/mii.h> 111 #include <dev/mii/miivar.h> 112 #include "miidevs.h" 113 #include <dev/mii/brgphyreg.h> 114 115 #include <dev/pci/pcireg.h> 116 #include <dev/pci/pcivar.h> 117 118 #include <dev/bge/if_bgereg.h> 119 120 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP) 121 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 122 123 MODULE_DEPEND(bge, pci, 1, 1, 1); 124 MODULE_DEPEND(bge, ether, 1, 1, 1); 125 MODULE_DEPEND(bge, miibus, 1, 1, 1); 126 127 /* "device miibus" required. See GENERIC if you get errors here. */ 128 #include "miibus_if.h" 129 130 /* 131 * Various supported device vendors/types and their names. Note: the 132 * spec seems to indicate that the hardware still has Alteon's vendor 133 * ID burned into it, though it will always be overridden by the vendor 134 * ID in the EEPROM. Just to be safe, we cover all possibilities. 135 */ 136 static const struct bge_type { 137 uint16_t bge_vid; 138 uint16_t bge_did; 139 } bge_devs[] = { 140 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 141 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 142 143 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 144 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 145 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 146 147 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 148 149 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 151 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717C }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5725 }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5727 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5762 }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 }, 205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F }, 206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G }, 207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F }, 210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 216 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 217 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 218 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, 219 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 }, 220 { BCOM_VENDORID, BCOM_DEVICEID_BCM57762 }, 221 { BCOM_VENDORID, BCOM_DEVICEID_BCM57764 }, 222 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 }, 223 { BCOM_VENDORID, BCOM_DEVICEID_BCM57766 }, 224 { BCOM_VENDORID, BCOM_DEVICEID_BCM57767 }, 225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, 226 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 }, 227 { BCOM_VENDORID, BCOM_DEVICEID_BCM57782 }, 228 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 }, 229 { BCOM_VENDORID, BCOM_DEVICEID_BCM57786 }, 230 { BCOM_VENDORID, BCOM_DEVICEID_BCM57787 }, 231 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 }, 232 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 }, 233 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 }, 234 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 }, 235 236 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 237 238 { TC_VENDORID, TC_DEVICEID_3C996 }, 239 240 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 }, 241 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 }, 242 { 0, 0 } 243 }; 244 245 static const struct bge_vendor { 246 uint16_t v_id; 247 const char *v_name; 248 } bge_vendors[] = { 249 { ALTEON_VENDORID, "Alteon" }, 250 { ALTIMA_VENDORID, "Altima" }, 251 { APPLE_VENDORID, "Apple" }, 252 { BCOM_VENDORID, "Broadcom" }, 253 { SK_VENDORID, "SysKonnect" }, 254 { TC_VENDORID, "3Com" }, 255 { FJTSU_VENDORID, "Fujitsu" }, 256 { 0, NULL } 257 }; 258 259 static const struct bge_revision { 260 uint32_t br_chipid; 261 const char *br_name; 262 } bge_revisions[] = { 263 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 264 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 265 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 266 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 267 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 268 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 269 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 270 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 271 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 272 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 273 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 274 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 275 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 276 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 277 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 278 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 279 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 280 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 281 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 282 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 283 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 284 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 285 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 286 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 287 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 288 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 289 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 290 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 291 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 292 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 293 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 294 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 295 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 296 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 297 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 298 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 299 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 300 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 301 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 302 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 303 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 304 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 305 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 306 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 307 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 308 { BGE_CHIPID_BCM5717_C0, "BCM5717 C0" }, 309 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 310 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 311 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 312 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 313 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 314 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 315 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 316 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 317 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" }, 318 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 319 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 320 /* 5754 and 5787 share the same ASIC ID */ 321 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 322 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 323 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 324 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 325 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 326 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 327 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 328 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 329 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 330 { 0, NULL } 331 }; 332 333 /* 334 * Some defaults for major revisions, so that newer steppings 335 * that we don't know about have a shot at working. 336 */ 337 static const struct bge_revision bge_majorrevs[] = { 338 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 339 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 340 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 341 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 342 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 343 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 344 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 345 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 346 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 347 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 348 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 349 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 350 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 351 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 352 /* 5754 and 5787 share the same ASIC ID */ 353 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 354 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 355 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 356 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 357 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 358 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 359 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 360 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 361 { BGE_ASICREV_BCM5762, "unknown BCM5762" }, 362 { 0, NULL } 363 }; 364 365 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 366 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 367 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 368 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 369 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 370 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 371 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS) 372 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_57765_PLUS) 373 374 static uint32_t bge_chipid(device_t); 375 static const struct bge_vendor * bge_lookup_vendor(uint16_t); 376 static const struct bge_revision * bge_lookup_rev(uint32_t); 377 378 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 379 380 static int bge_probe(device_t); 381 static int bge_attach(device_t); 382 static int bge_detach(device_t); 383 static int bge_suspend(device_t); 384 static int bge_resume(device_t); 385 static void bge_release_resources(struct bge_softc *); 386 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 387 static int bge_dma_alloc(struct bge_softc *); 388 static void bge_dma_free(struct bge_softc *); 389 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t, 390 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 391 392 static void bge_devinfo(struct bge_softc *); 393 static int bge_mbox_reorder(struct bge_softc *); 394 395 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 396 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 397 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 398 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 399 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 400 401 static void bge_txeof(struct bge_softc *, uint16_t); 402 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 403 static int bge_rxeof(struct bge_softc *, uint16_t, int); 404 405 static void bge_asf_driver_up (struct bge_softc *); 406 static void bge_tick(void *); 407 static void bge_stats_clear_regs(struct bge_softc *); 408 static void bge_stats_update(struct bge_softc *); 409 static void bge_stats_update_regs(struct bge_softc *); 410 static struct mbuf *bge_check_short_dma(struct mbuf *); 411 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *, 412 uint16_t *, uint16_t *); 413 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 414 415 static void bge_intr(void *); 416 static int bge_msi_intr(void *); 417 static void bge_intr_task(void *, int); 418 static void bge_start(if_t); 419 static void bge_start_locked(if_t); 420 static void bge_start_tx(struct bge_softc *, uint32_t); 421 static int bge_ioctl(if_t, u_long, caddr_t); 422 static void bge_init_locked(struct bge_softc *); 423 static void bge_init(void *); 424 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t); 425 static void bge_stop(struct bge_softc *); 426 static void bge_watchdog(struct bge_softc *); 427 static int bge_shutdown(device_t); 428 static int bge_ifmedia_upd_locked(if_t); 429 static int bge_ifmedia_upd(if_t); 430 static void bge_ifmedia_sts(if_t, struct ifmediareq *); 431 static uint64_t bge_get_counter(if_t, ift_counter); 432 433 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 434 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 435 436 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 437 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 438 439 static void bge_setpromisc(struct bge_softc *); 440 static void bge_setmulti(struct bge_softc *); 441 static void bge_setvlan(struct bge_softc *); 442 443 static __inline void bge_rxreuse_std(struct bge_softc *, int); 444 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int); 445 static int bge_newbuf_std(struct bge_softc *, int); 446 static int bge_newbuf_jumbo(struct bge_softc *, int); 447 static int bge_init_rx_ring_std(struct bge_softc *); 448 static void bge_free_rx_ring_std(struct bge_softc *); 449 static int bge_init_rx_ring_jumbo(struct bge_softc *); 450 static void bge_free_rx_ring_jumbo(struct bge_softc *); 451 static void bge_free_tx_ring(struct bge_softc *); 452 static int bge_init_tx_ring(struct bge_softc *); 453 454 static int bge_chipinit(struct bge_softc *); 455 static int bge_blockinit(struct bge_softc *); 456 static uint32_t bge_dma_swap_options(struct bge_softc *); 457 458 static int bge_has_eaddr(struct bge_softc *); 459 static uint32_t bge_readmem_ind(struct bge_softc *, int); 460 static void bge_writemem_ind(struct bge_softc *, int, int); 461 static void bge_writembx(struct bge_softc *, int, int); 462 #ifdef notdef 463 static uint32_t bge_readreg_ind(struct bge_softc *, int); 464 #endif 465 static void bge_writemem_direct(struct bge_softc *, int, int); 466 static void bge_writereg_ind(struct bge_softc *, int, int); 467 468 static int bge_miibus_readreg(device_t, int, int); 469 static int bge_miibus_writereg(device_t, int, int, int); 470 static void bge_miibus_statchg(device_t); 471 #ifdef DEVICE_POLLING 472 static int bge_poll(if_t ifp, enum poll_cmd cmd, int count); 473 #endif 474 475 #define BGE_RESET_SHUTDOWN 0 476 #define BGE_RESET_START 1 477 #define BGE_RESET_SUSPEND 2 478 static void bge_sig_post_reset(struct bge_softc *, int); 479 static void bge_sig_legacy(struct bge_softc *, int); 480 static void bge_sig_pre_reset(struct bge_softc *, int); 481 static void bge_stop_fw(struct bge_softc *); 482 static int bge_reset(struct bge_softc *); 483 static void bge_link_upd(struct bge_softc *); 484 485 static void bge_ape_lock_init(struct bge_softc *); 486 static void bge_ape_read_fw_ver(struct bge_softc *); 487 static int bge_ape_lock(struct bge_softc *, int); 488 static void bge_ape_unlock(struct bge_softc *, int); 489 static void bge_ape_send_event(struct bge_softc *, uint32_t); 490 static void bge_ape_driver_state_change(struct bge_softc *, int); 491 492 /* 493 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 494 * leak information to untrusted users. It is also known to cause alignment 495 * traps on certain architectures. 496 */ 497 #ifdef BGE_REGISTER_DEBUG 498 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 499 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 500 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS); 501 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 502 #endif 503 static void bge_add_sysctls(struct bge_softc *); 504 static void bge_add_sysctl_stats_regs(struct bge_softc *, 505 struct sysctl_ctx_list *, struct sysctl_oid_list *); 506 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *, 507 struct sysctl_oid_list *); 508 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 509 510 DEBUGNET_DEFINE(bge); 511 512 static device_method_t bge_methods[] = { 513 /* Device interface */ 514 DEVMETHOD(device_probe, bge_probe), 515 DEVMETHOD(device_attach, bge_attach), 516 DEVMETHOD(device_detach, bge_detach), 517 DEVMETHOD(device_shutdown, bge_shutdown), 518 DEVMETHOD(device_suspend, bge_suspend), 519 DEVMETHOD(device_resume, bge_resume), 520 521 /* MII interface */ 522 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 523 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 524 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 525 526 DEVMETHOD_END 527 }; 528 529 static driver_t bge_driver = { 530 "bge", 531 bge_methods, 532 sizeof(struct bge_softc) 533 }; 534 535 DRIVER_MODULE(bge, pci, bge_driver, 0, 0); 536 MODULE_PNP_INFO("U16:vendor;U16:device", pci, bge, bge_devs, 537 nitems(bge_devs) - 1); 538 DRIVER_MODULE(miibus, bge, miibus_driver, 0, 0); 539 540 static int bge_allow_asf = 1; 541 542 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 543 "BGE driver parameters"); 544 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RDTUN, &bge_allow_asf, 0, 545 "Allow ASF mode if available"); 546 547 static int 548 bge_has_eaddr(struct bge_softc *sc) 549 { 550 return (1); 551 } 552 553 static uint32_t 554 bge_readmem_ind(struct bge_softc *sc, int off) 555 { 556 device_t dev; 557 uint32_t val; 558 559 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 560 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 561 return (0); 562 563 dev = sc->bge_dev; 564 565 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 566 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 567 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 568 return (val); 569 } 570 571 static void 572 bge_writemem_ind(struct bge_softc *sc, int off, int val) 573 { 574 device_t dev; 575 576 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 577 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 578 return; 579 580 dev = sc->bge_dev; 581 582 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 583 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 584 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 585 } 586 587 #ifdef notdef 588 static uint32_t 589 bge_readreg_ind(struct bge_softc *sc, int off) 590 { 591 device_t dev; 592 593 dev = sc->bge_dev; 594 595 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 596 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 597 } 598 #endif 599 600 static void 601 bge_writereg_ind(struct bge_softc *sc, int off, int val) 602 { 603 device_t dev; 604 605 dev = sc->bge_dev; 606 607 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 608 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 609 } 610 611 static void 612 bge_writemem_direct(struct bge_softc *sc, int off, int val) 613 { 614 CSR_WRITE_4(sc, off, val); 615 } 616 617 static void 618 bge_writembx(struct bge_softc *sc, int off, int val) 619 { 620 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 621 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 622 623 CSR_WRITE_4(sc, off, val); 624 if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0) 625 CSR_READ_4(sc, off); 626 } 627 628 /* 629 * Clear all stale locks and select the lock for this driver instance. 630 */ 631 static void 632 bge_ape_lock_init(struct bge_softc *sc) 633 { 634 uint32_t bit, regbase; 635 int i; 636 637 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 638 regbase = BGE_APE_LOCK_GRANT; 639 else 640 regbase = BGE_APE_PER_LOCK_GRANT; 641 642 /* Clear any stale locks. */ 643 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 644 switch (i) { 645 case BGE_APE_LOCK_PHY0: 646 case BGE_APE_LOCK_PHY1: 647 case BGE_APE_LOCK_PHY2: 648 case BGE_APE_LOCK_PHY3: 649 bit = BGE_APE_LOCK_GRANT_DRIVER0; 650 break; 651 default: 652 if (sc->bge_func_addr == 0) 653 bit = BGE_APE_LOCK_GRANT_DRIVER0; 654 else 655 bit = (1 << sc->bge_func_addr); 656 } 657 APE_WRITE_4(sc, regbase + 4 * i, bit); 658 } 659 660 /* Select the PHY lock based on the device's function number. */ 661 switch (sc->bge_func_addr) { 662 case 0: 663 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 664 break; 665 case 1: 666 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 667 break; 668 case 2: 669 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 670 break; 671 case 3: 672 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 673 break; 674 default: 675 device_printf(sc->bge_dev, 676 "PHY lock not supported on this function\n"); 677 } 678 } 679 680 /* 681 * Check for APE firmware, set flags, and print version info. 682 */ 683 static void 684 bge_ape_read_fw_ver(struct bge_softc *sc) 685 { 686 const char *fwtype; 687 uint32_t apedata, features; 688 689 /* Check for a valid APE signature in shared memory. */ 690 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 691 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 692 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 693 return; 694 } 695 696 /* Check if APE firmware is running. */ 697 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 698 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 699 device_printf(sc->bge_dev, "APE signature found " 700 "but FW status not ready! 0x%08x\n", apedata); 701 return; 702 } 703 704 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 705 706 /* Fetch the APE firwmare type and version. */ 707 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 708 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 709 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 710 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 711 fwtype = "NCSI"; 712 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 713 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 714 fwtype = "DASH"; 715 } else 716 fwtype = "UNKN"; 717 718 /* Print the APE firmware version. */ 719 device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n", 720 fwtype, 721 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 722 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 723 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 724 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 725 } 726 727 static int 728 bge_ape_lock(struct bge_softc *sc, int locknum) 729 { 730 uint32_t bit, gnt, req, status; 731 int i, off; 732 733 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 734 return (0); 735 736 /* Lock request/grant registers have different bases. */ 737 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) { 738 req = BGE_APE_LOCK_REQ; 739 gnt = BGE_APE_LOCK_GRANT; 740 } else { 741 req = BGE_APE_PER_LOCK_REQ; 742 gnt = BGE_APE_PER_LOCK_GRANT; 743 } 744 745 off = 4 * locknum; 746 747 switch (locknum) { 748 case BGE_APE_LOCK_GPIO: 749 /* Lock required when using GPIO. */ 750 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 751 return (0); 752 if (sc->bge_func_addr == 0) 753 bit = BGE_APE_LOCK_REQ_DRIVER0; 754 else 755 bit = (1 << sc->bge_func_addr); 756 break; 757 case BGE_APE_LOCK_GRC: 758 /* Lock required to reset the device. */ 759 if (sc->bge_func_addr == 0) 760 bit = BGE_APE_LOCK_REQ_DRIVER0; 761 else 762 bit = (1 << sc->bge_func_addr); 763 break; 764 case BGE_APE_LOCK_MEM: 765 /* Lock required when accessing certain APE memory. */ 766 if (sc->bge_func_addr == 0) 767 bit = BGE_APE_LOCK_REQ_DRIVER0; 768 else 769 bit = (1 << sc->bge_func_addr); 770 break; 771 case BGE_APE_LOCK_PHY0: 772 case BGE_APE_LOCK_PHY1: 773 case BGE_APE_LOCK_PHY2: 774 case BGE_APE_LOCK_PHY3: 775 /* Lock required when accessing PHYs. */ 776 bit = BGE_APE_LOCK_REQ_DRIVER0; 777 break; 778 default: 779 return (EINVAL); 780 } 781 782 /* Request a lock. */ 783 APE_WRITE_4(sc, req + off, bit); 784 785 /* Wait up to 1 second to acquire lock. */ 786 for (i = 0; i < 20000; i++) { 787 status = APE_READ_4(sc, gnt + off); 788 if (status == bit) 789 break; 790 DELAY(50); 791 } 792 793 /* Handle any errors. */ 794 if (status != bit) { 795 device_printf(sc->bge_dev, "APE lock %d request failed! " 796 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 797 locknum, req + off, bit & 0xFFFF, gnt + off, 798 status & 0xFFFF); 799 /* Revoke the lock request. */ 800 APE_WRITE_4(sc, gnt + off, bit); 801 return (EBUSY); 802 } 803 804 return (0); 805 } 806 807 static void 808 bge_ape_unlock(struct bge_softc *sc, int locknum) 809 { 810 uint32_t bit, gnt; 811 int off; 812 813 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 814 return; 815 816 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 817 gnt = BGE_APE_LOCK_GRANT; 818 else 819 gnt = BGE_APE_PER_LOCK_GRANT; 820 821 off = 4 * locknum; 822 823 switch (locknum) { 824 case BGE_APE_LOCK_GPIO: 825 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 826 return; 827 if (sc->bge_func_addr == 0) 828 bit = BGE_APE_LOCK_GRANT_DRIVER0; 829 else 830 bit = (1 << sc->bge_func_addr); 831 break; 832 case BGE_APE_LOCK_GRC: 833 if (sc->bge_func_addr == 0) 834 bit = BGE_APE_LOCK_GRANT_DRIVER0; 835 else 836 bit = (1 << sc->bge_func_addr); 837 break; 838 case BGE_APE_LOCK_MEM: 839 if (sc->bge_func_addr == 0) 840 bit = BGE_APE_LOCK_GRANT_DRIVER0; 841 else 842 bit = (1 << sc->bge_func_addr); 843 break; 844 case BGE_APE_LOCK_PHY0: 845 case BGE_APE_LOCK_PHY1: 846 case BGE_APE_LOCK_PHY2: 847 case BGE_APE_LOCK_PHY3: 848 bit = BGE_APE_LOCK_GRANT_DRIVER0; 849 break; 850 default: 851 return; 852 } 853 854 APE_WRITE_4(sc, gnt + off, bit); 855 } 856 857 /* 858 * Send an event to the APE firmware. 859 */ 860 static void 861 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 862 { 863 uint32_t apedata; 864 int i; 865 866 /* NCSI does not support APE events. */ 867 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 868 return; 869 870 /* Wait up to 1ms for APE to service previous event. */ 871 for (i = 10; i > 0; i--) { 872 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 873 break; 874 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 875 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 876 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 877 BGE_APE_EVENT_STATUS_EVENT_PENDING); 878 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 879 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 880 break; 881 } 882 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 883 DELAY(100); 884 } 885 if (i == 0) 886 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n", 887 event); 888 } 889 890 static void 891 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 892 { 893 uint32_t apedata, event; 894 895 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 896 return; 897 898 switch (kind) { 899 case BGE_RESET_START: 900 /* If this is the first load, clear the load counter. */ 901 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 902 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 903 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 904 else { 905 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 906 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 907 } 908 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 909 BGE_APE_HOST_SEG_SIG_MAGIC); 910 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 911 BGE_APE_HOST_SEG_LEN_MAGIC); 912 913 /* Add some version info if bge(4) supports it. */ 914 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 915 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 916 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 917 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 918 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 919 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 920 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 921 BGE_APE_HOST_DRVR_STATE_START); 922 event = BGE_APE_EVENT_STATUS_STATE_START; 923 break; 924 case BGE_RESET_SHUTDOWN: 925 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 926 BGE_APE_HOST_DRVR_STATE_UNLOAD); 927 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 928 break; 929 case BGE_RESET_SUSPEND: 930 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 931 break; 932 default: 933 return; 934 } 935 936 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 937 BGE_APE_EVENT_STATUS_STATE_CHNGE); 938 } 939 940 /* 941 * Map a single buffer address. 942 */ 943 944 static void 945 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 946 { 947 struct bge_dmamap_arg *ctx; 948 949 if (error) 950 return; 951 952 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 953 954 ctx = arg; 955 ctx->bge_busaddr = segs->ds_addr; 956 } 957 958 static uint8_t 959 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 960 { 961 uint32_t access, byte = 0; 962 int i; 963 964 /* Lock. */ 965 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 966 for (i = 0; i < 8000; i++) { 967 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 968 break; 969 DELAY(20); 970 } 971 if (i == 8000) 972 return (1); 973 974 /* Enable access. */ 975 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 976 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 977 978 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 979 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 980 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 981 DELAY(10); 982 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 983 DELAY(10); 984 break; 985 } 986 } 987 988 if (i == BGE_TIMEOUT * 10) { 989 if_printf(sc->bge_ifp, "nvram read timed out\n"); 990 return (1); 991 } 992 993 /* Get result. */ 994 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 995 996 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 997 998 /* Disable access. */ 999 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1000 1001 /* Unlock. */ 1002 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1003 CSR_READ_4(sc, BGE_NVRAM_SWARB); 1004 1005 return (0); 1006 } 1007 1008 /* 1009 * Read a sequence of bytes from NVRAM. 1010 */ 1011 static int 1012 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 1013 { 1014 int err = 0, i; 1015 uint8_t byte = 0; 1016 1017 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 1018 return (1); 1019 1020 for (i = 0; i < cnt; i++) { 1021 err = bge_nvram_getbyte(sc, off + i, &byte); 1022 if (err) 1023 break; 1024 *(dest + i) = byte; 1025 } 1026 1027 return (err ? 1 : 0); 1028 } 1029 1030 /* 1031 * Read a byte of data stored in the EEPROM at address 'addr.' The 1032 * BCM570x supports both the traditional bitbang interface and an 1033 * auto access interface for reading the EEPROM. We use the auto 1034 * access method. 1035 */ 1036 static uint8_t 1037 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1038 { 1039 int i; 1040 uint32_t byte = 0; 1041 1042 /* 1043 * Enable use of auto EEPROM access so we can avoid 1044 * having to use the bitbang method. 1045 */ 1046 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1047 1048 /* Reset the EEPROM, load the clock period. */ 1049 CSR_WRITE_4(sc, BGE_EE_ADDR, 1050 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1051 DELAY(20); 1052 1053 /* Issue the read EEPROM command. */ 1054 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1055 1056 /* Wait for completion */ 1057 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 1058 DELAY(10); 1059 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1060 break; 1061 } 1062 1063 if (i == BGE_TIMEOUT * 10) { 1064 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 1065 return (1); 1066 } 1067 1068 /* Get result. */ 1069 byte = CSR_READ_4(sc, BGE_EE_DATA); 1070 1071 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1072 1073 return (0); 1074 } 1075 1076 /* 1077 * Read a sequence of bytes from the EEPROM. 1078 */ 1079 static int 1080 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 1081 { 1082 int i, error = 0; 1083 uint8_t byte = 0; 1084 1085 for (i = 0; i < cnt; i++) { 1086 error = bge_eeprom_getbyte(sc, off + i, &byte); 1087 if (error) 1088 break; 1089 *(dest + i) = byte; 1090 } 1091 1092 return (error ? 1 : 0); 1093 } 1094 1095 static int 1096 bge_miibus_readreg(device_t dev, int phy, int reg) 1097 { 1098 struct bge_softc *sc; 1099 uint32_t val; 1100 int i; 1101 1102 sc = device_get_softc(dev); 1103 1104 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1105 return (0); 1106 1107 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1108 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1109 CSR_WRITE_4(sc, BGE_MI_MODE, 1110 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1111 DELAY(80); 1112 } 1113 1114 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1115 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1116 1117 /* Poll for the PHY register access to complete. */ 1118 for (i = 0; i < BGE_TIMEOUT; i++) { 1119 DELAY(10); 1120 val = CSR_READ_4(sc, BGE_MI_COMM); 1121 if ((val & BGE_MICOMM_BUSY) == 0) { 1122 DELAY(5); 1123 val = CSR_READ_4(sc, BGE_MI_COMM); 1124 break; 1125 } 1126 } 1127 1128 if (i == BGE_TIMEOUT) { 1129 device_printf(sc->bge_dev, 1130 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 1131 phy, reg, val); 1132 val = 0; 1133 } 1134 1135 /* Restore the autopoll bit if necessary. */ 1136 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1137 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1138 DELAY(80); 1139 } 1140 1141 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1142 1143 if (val & BGE_MICOMM_READFAIL) 1144 return (0); 1145 1146 return (val & 0xFFFF); 1147 } 1148 1149 static int 1150 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1151 { 1152 struct bge_softc *sc; 1153 int i; 1154 1155 sc = device_get_softc(dev); 1156 1157 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 1158 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1159 return (0); 1160 1161 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1162 return (0); 1163 1164 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1165 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1166 CSR_WRITE_4(sc, BGE_MI_MODE, 1167 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1168 DELAY(80); 1169 } 1170 1171 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1172 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1173 1174 for (i = 0; i < BGE_TIMEOUT; i++) { 1175 DELAY(10); 1176 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1177 DELAY(5); 1178 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 1179 break; 1180 } 1181 } 1182 1183 /* Restore the autopoll bit if necessary. */ 1184 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1185 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1186 DELAY(80); 1187 } 1188 1189 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1190 1191 if (i == BGE_TIMEOUT) 1192 device_printf(sc->bge_dev, 1193 "PHY write timed out (phy %d, reg %d, val 0x%04x)\n", 1194 phy, reg, val); 1195 1196 return (0); 1197 } 1198 1199 static void 1200 bge_miibus_statchg(device_t dev) 1201 { 1202 struct bge_softc *sc; 1203 struct mii_data *mii; 1204 uint32_t mac_mode, rx_mode, tx_mode; 1205 1206 sc = device_get_softc(dev); 1207 if ((if_getdrvflags(sc->bge_ifp) & IFF_DRV_RUNNING) == 0) 1208 return; 1209 mii = device_get_softc(sc->bge_miibus); 1210 1211 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1212 (IFM_ACTIVE | IFM_AVALID)) { 1213 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1214 case IFM_10_T: 1215 case IFM_100_TX: 1216 sc->bge_link = 1; 1217 break; 1218 case IFM_1000_T: 1219 case IFM_1000_SX: 1220 case IFM_2500_SX: 1221 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 1222 sc->bge_link = 1; 1223 else 1224 sc->bge_link = 0; 1225 break; 1226 default: 1227 sc->bge_link = 0; 1228 break; 1229 } 1230 } else 1231 sc->bge_link = 0; 1232 if (sc->bge_link == 0) 1233 return; 1234 1235 /* 1236 * APE firmware touches these registers to keep the MAC 1237 * connected to the outside world. Try to keep the 1238 * accesses atomic. 1239 */ 1240 1241 /* Set the port mode (MII/GMII) to match the link speed. */ 1242 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1243 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1244 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1245 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1246 1247 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1248 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1249 mac_mode |= BGE_PORTMODE_GMII; 1250 else 1251 mac_mode |= BGE_PORTMODE_MII; 1252 1253 /* Set MAC flow control behavior to match link flow control settings. */ 1254 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1255 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1256 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1257 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1258 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1259 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1260 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1261 } else 1262 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1263 1264 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode); 1265 DELAY(40); 1266 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1267 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1268 } 1269 1270 /* 1271 * Intialize a standard receive ring descriptor. 1272 */ 1273 static int 1274 bge_newbuf_std(struct bge_softc *sc, int i) 1275 { 1276 struct mbuf *m; 1277 struct bge_rx_bd *r; 1278 bus_dma_segment_t segs[1]; 1279 bus_dmamap_t map; 1280 int error, nsegs; 1281 1282 if (sc->bge_flags & BGE_FLAG_JUMBO_STD && 1283 (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN + 1284 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) { 1285 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1286 if (m == NULL) 1287 return (ENOBUFS); 1288 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1289 } else { 1290 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1291 if (m == NULL) 1292 return (ENOBUFS); 1293 m->m_len = m->m_pkthdr.len = MCLBYTES; 1294 } 1295 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1296 m_adj(m, ETHER_ALIGN); 1297 1298 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag, 1299 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0); 1300 if (error != 0) { 1301 m_freem(m); 1302 return (error); 1303 } 1304 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1305 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1306 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD); 1307 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1308 sc->bge_cdata.bge_rx_std_dmamap[i]); 1309 } 1310 map = sc->bge_cdata.bge_rx_std_dmamap[i]; 1311 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap; 1312 sc->bge_cdata.bge_rx_std_sparemap = map; 1313 sc->bge_cdata.bge_rx_std_chain[i] = m; 1314 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len; 1315 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 1316 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1317 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1318 r->bge_flags = BGE_RXBDFLAG_END; 1319 r->bge_len = segs[0].ds_len; 1320 r->bge_idx = i; 1321 1322 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1323 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD); 1324 1325 return (0); 1326 } 1327 1328 /* 1329 * Initialize a jumbo receive ring descriptor. This allocates 1330 * a jumbo buffer from the pool managed internally by the driver. 1331 */ 1332 static int 1333 bge_newbuf_jumbo(struct bge_softc *sc, int i) 1334 { 1335 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 1336 bus_dmamap_t map; 1337 struct bge_extrx_bd *r; 1338 struct mbuf *m; 1339 int error, nsegs; 1340 1341 MGETHDR(m, M_NOWAIT, MT_DATA); 1342 if (m == NULL) 1343 return (ENOBUFS); 1344 1345 if (m_cljget(m, M_NOWAIT, MJUM9BYTES) == NULL) { 1346 m_freem(m); 1347 return (ENOBUFS); 1348 } 1349 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1350 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1351 m_adj(m, ETHER_ALIGN); 1352 1353 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 1354 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1355 if (error != 0) { 1356 m_freem(m); 1357 return (error); 1358 } 1359 1360 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1361 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1362 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD); 1363 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1364 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1365 } 1366 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i]; 1367 sc->bge_cdata.bge_rx_jumbo_dmamap[i] = 1368 sc->bge_cdata.bge_rx_jumbo_sparemap; 1369 sc->bge_cdata.bge_rx_jumbo_sparemap = map; 1370 sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 1371 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0; 1372 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0; 1373 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0; 1374 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0; 1375 1376 /* 1377 * Fill in the extended RX buffer descriptor. 1378 */ 1379 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 1380 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 1381 r->bge_idx = i; 1382 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 1383 switch (nsegs) { 1384 case 4: 1385 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 1386 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 1387 r->bge_len3 = segs[3].ds_len; 1388 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len; 1389 case 3: 1390 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 1391 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 1392 r->bge_len2 = segs[2].ds_len; 1393 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len; 1394 case 2: 1395 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 1396 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 1397 r->bge_len1 = segs[1].ds_len; 1398 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len; 1399 case 1: 1400 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1401 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1402 r->bge_len0 = segs[0].ds_len; 1403 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len; 1404 break; 1405 default: 1406 panic("%s: %d segments\n", __func__, nsegs); 1407 } 1408 1409 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1410 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD); 1411 1412 return (0); 1413 } 1414 1415 static int 1416 bge_init_rx_ring_std(struct bge_softc *sc) 1417 { 1418 int error, i; 1419 1420 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1421 sc->bge_std = 0; 1422 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1423 if ((error = bge_newbuf_std(sc, i)) != 0) 1424 return (error); 1425 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1426 } 1427 1428 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1429 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1430 1431 sc->bge_std = 0; 1432 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1); 1433 1434 return (0); 1435 } 1436 1437 static void 1438 bge_free_rx_ring_std(struct bge_softc *sc) 1439 { 1440 int i; 1441 1442 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1443 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1444 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1445 sc->bge_cdata.bge_rx_std_dmamap[i], 1446 BUS_DMASYNC_POSTREAD); 1447 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1448 sc->bge_cdata.bge_rx_std_dmamap[i]); 1449 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1450 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1451 } 1452 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1453 sizeof(struct bge_rx_bd)); 1454 } 1455 } 1456 1457 static int 1458 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1459 { 1460 struct bge_rcb *rcb; 1461 int error, i; 1462 1463 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ); 1464 sc->bge_jumbo = 0; 1465 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1466 if ((error = bge_newbuf_jumbo(sc, i)) != 0) 1467 return (error); 1468 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1469 } 1470 1471 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1472 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1473 1474 sc->bge_jumbo = 0; 1475 1476 /* Enable the jumbo receive producer ring. */ 1477 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1478 rcb->bge_maxlen_flags = 1479 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD); 1480 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1481 1482 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1); 1483 1484 return (0); 1485 } 1486 1487 static void 1488 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1489 { 1490 int i; 1491 1492 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1493 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1494 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1495 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1496 BUS_DMASYNC_POSTREAD); 1497 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1498 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1499 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1500 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1501 } 1502 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1503 sizeof(struct bge_extrx_bd)); 1504 } 1505 } 1506 1507 static void 1508 bge_free_tx_ring(struct bge_softc *sc) 1509 { 1510 int i; 1511 1512 if (sc->bge_ldata.bge_tx_ring == NULL) 1513 return; 1514 1515 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1516 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1517 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 1518 sc->bge_cdata.bge_tx_dmamap[i], 1519 BUS_DMASYNC_POSTWRITE); 1520 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1521 sc->bge_cdata.bge_tx_dmamap[i]); 1522 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1523 sc->bge_cdata.bge_tx_chain[i] = NULL; 1524 } 1525 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1526 sizeof(struct bge_tx_bd)); 1527 } 1528 } 1529 1530 static int 1531 bge_init_tx_ring(struct bge_softc *sc) 1532 { 1533 sc->bge_txcnt = 0; 1534 sc->bge_tx_saved_considx = 0; 1535 1536 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 1537 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 1538 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1539 1540 /* Initialize transmit producer index for host-memory send ring. */ 1541 sc->bge_tx_prodidx = 0; 1542 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1543 1544 /* 5700 b2 errata */ 1545 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1546 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1547 1548 /* NIC-memory send ring not used; initialize to zero. */ 1549 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1550 /* 5700 b2 errata */ 1551 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1552 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1553 1554 return (0); 1555 } 1556 1557 static void 1558 bge_setpromisc(struct bge_softc *sc) 1559 { 1560 if_t ifp; 1561 1562 BGE_LOCK_ASSERT(sc); 1563 1564 ifp = sc->bge_ifp; 1565 1566 /* Enable or disable promiscuous mode as needed. */ 1567 if (if_getflags(ifp) & IFF_PROMISC) 1568 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1569 else 1570 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1571 } 1572 1573 static u_int 1574 bge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1575 { 1576 uint32_t *hashes = arg; 1577 int h; 1578 1579 h = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0x7F; 1580 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1581 1582 return (1); 1583 } 1584 1585 static void 1586 bge_setmulti(struct bge_softc *sc) 1587 { 1588 if_t ifp; 1589 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1590 int i; 1591 1592 BGE_LOCK_ASSERT(sc); 1593 1594 ifp = sc->bge_ifp; 1595 1596 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) { 1597 for (i = 0; i < 4; i++) 1598 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1599 return; 1600 } 1601 1602 /* First, zot all the existing filters. */ 1603 for (i = 0; i < 4; i++) 1604 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1605 1606 if_foreach_llmaddr(ifp, bge_hash_maddr, hashes); 1607 1608 for (i = 0; i < 4; i++) 1609 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1610 } 1611 1612 static void 1613 bge_setvlan(struct bge_softc *sc) 1614 { 1615 if_t ifp; 1616 1617 BGE_LOCK_ASSERT(sc); 1618 1619 ifp = sc->bge_ifp; 1620 1621 /* Enable or disable VLAN tag stripping as needed. */ 1622 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) 1623 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1624 else 1625 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1626 } 1627 1628 static void 1629 bge_sig_pre_reset(struct bge_softc *sc, int type) 1630 { 1631 1632 /* 1633 * Some chips don't like this so only do this if ASF is enabled 1634 */ 1635 if (sc->bge_asf_mode) 1636 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1637 1638 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1639 switch (type) { 1640 case BGE_RESET_START: 1641 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1642 BGE_FW_DRV_STATE_START); 1643 break; 1644 case BGE_RESET_SHUTDOWN: 1645 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1646 BGE_FW_DRV_STATE_UNLOAD); 1647 break; 1648 case BGE_RESET_SUSPEND: 1649 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1650 BGE_FW_DRV_STATE_SUSPEND); 1651 break; 1652 } 1653 } 1654 1655 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1656 bge_ape_driver_state_change(sc, type); 1657 } 1658 1659 static void 1660 bge_sig_post_reset(struct bge_softc *sc, int type) 1661 { 1662 1663 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1664 switch (type) { 1665 case BGE_RESET_START: 1666 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1667 BGE_FW_DRV_STATE_START_DONE); 1668 /* START DONE */ 1669 break; 1670 case BGE_RESET_SHUTDOWN: 1671 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1672 BGE_FW_DRV_STATE_UNLOAD_DONE); 1673 break; 1674 } 1675 } 1676 if (type == BGE_RESET_SHUTDOWN) 1677 bge_ape_driver_state_change(sc, type); 1678 } 1679 1680 static void 1681 bge_sig_legacy(struct bge_softc *sc, int type) 1682 { 1683 1684 if (sc->bge_asf_mode) { 1685 switch (type) { 1686 case BGE_RESET_START: 1687 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1688 BGE_FW_DRV_STATE_START); 1689 break; 1690 case BGE_RESET_SHUTDOWN: 1691 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1692 BGE_FW_DRV_STATE_UNLOAD); 1693 break; 1694 } 1695 } 1696 } 1697 1698 static void 1699 bge_stop_fw(struct bge_softc *sc) 1700 { 1701 int i; 1702 1703 if (sc->bge_asf_mode) { 1704 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1705 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 1706 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1707 1708 for (i = 0; i < 100; i++ ) { 1709 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1710 BGE_RX_CPU_DRV_EVENT)) 1711 break; 1712 DELAY(10); 1713 } 1714 } 1715 } 1716 1717 static uint32_t 1718 bge_dma_swap_options(struct bge_softc *sc) 1719 { 1720 uint32_t dma_options; 1721 1722 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME | 1723 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA; 1724 #if BYTE_ORDER == BIG_ENDIAN 1725 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME; 1726 #endif 1727 return (dma_options); 1728 } 1729 1730 /* 1731 * Do endian, PCI and DMA initialization. 1732 */ 1733 static int 1734 bge_chipinit(struct bge_softc *sc) 1735 { 1736 uint32_t dma_rw_ctl, misc_ctl, mode_ctl; 1737 uint16_t val; 1738 int i; 1739 1740 /* Set endianness before we access any non-PCI registers. */ 1741 misc_ctl = BGE_INIT; 1742 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS) 1743 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 1744 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4); 1745 1746 /* 1747 * Clear the MAC statistics block in the NIC's 1748 * internal memory. 1749 */ 1750 for (i = BGE_STATS_BLOCK; 1751 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1752 BGE_MEMWIN_WRITE(sc, i, 0); 1753 1754 for (i = BGE_STATUS_BLOCK; 1755 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1756 BGE_MEMWIN_WRITE(sc, i, 0); 1757 1758 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1759 /* 1760 * Fix data corruption caused by non-qword write with WB. 1761 * Fix master abort in PCI mode. 1762 * Fix PCI latency timer. 1763 */ 1764 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1765 val |= (1 << 10) | (1 << 12) | (1 << 13); 1766 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1767 } 1768 1769 if (sc->bge_asicrev == BGE_ASICREV_BCM57765 || 1770 sc->bge_asicrev == BGE_ASICREV_BCM57766) { 1771 /* 1772 * For the 57766 and non Ax versions of 57765, bootcode 1773 * needs to setup the PCIE Fast Training Sequence (FTS) 1774 * value to prevent transmit hangs. 1775 */ 1776 if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) { 1777 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 1778 CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) | 1779 BGE_CPMU_PADRNG_CTL_RDIV2); 1780 } 1781 } 1782 1783 /* 1784 * Set up the PCI DMA control register. 1785 */ 1786 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1787 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1788 if (sc->bge_flags & BGE_FLAG_PCIE) { 1789 if (sc->bge_mps >= 256) 1790 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1791 else 1792 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1793 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1794 if (BGE_IS_5714_FAMILY(sc)) { 1795 /* 256 bytes for read and write. */ 1796 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1797 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1798 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1799 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1800 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1801 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 1802 /* 1803 * In the BCM5703, the DMA read watermark should 1804 * be set to less than or equal to the maximum 1805 * memory read byte count of the PCI-X command 1806 * register. 1807 */ 1808 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 1809 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1810 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1811 /* 1536 bytes for read, 384 bytes for write. */ 1812 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1813 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1814 } else { 1815 /* 384 bytes for read and write. */ 1816 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1817 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1818 0x0F; 1819 } 1820 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1821 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1822 uint32_t tmp; 1823 1824 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1825 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1826 if (tmp == 6 || tmp == 7) 1827 dma_rw_ctl |= 1828 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1829 1830 /* Set PCI-X DMA write workaround. */ 1831 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1832 } 1833 } else { 1834 /* Conventional PCI bus: 256 bytes for read and write. */ 1835 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1836 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1837 1838 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1839 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1840 dma_rw_ctl |= 0x0F; 1841 } 1842 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1843 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1844 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1845 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1846 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1847 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1848 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1849 if (BGE_IS_5717_PLUS(sc)) { 1850 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 1851 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 1852 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 1853 /* 1854 * Enable HW workaround for controllers that misinterpret 1855 * a status tag update and leave interrupts permanently 1856 * disabled. 1857 */ 1858 if (!BGE_IS_57765_PLUS(sc) && 1859 sc->bge_asicrev != BGE_ASICREV_BCM5717 && 1860 sc->bge_asicrev != BGE_ASICREV_BCM5762) 1861 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 1862 } 1863 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1864 1865 /* 1866 * Set up general mode register. 1867 */ 1868 mode_ctl = bge_dma_swap_options(sc); 1869 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 1870 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 1871 /* Retain Host-2-BMC settings written by APE firmware. */ 1872 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 1873 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 1874 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 1875 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 1876 } 1877 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1878 BGE_MODECTL_TX_NO_PHDR_CSUM; 1879 1880 /* 1881 * BCM5701 B5 have a bug causing data corruption when using 1882 * 64-bit DMA reads, which can be terminated early and then 1883 * completed later as 32-bit accesses, in combination with 1884 * certain bridges. 1885 */ 1886 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1887 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1888 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 1889 1890 /* 1891 * Tell the firmware the driver is running 1892 */ 1893 if (sc->bge_asf_mode & ASF_STACKUP) 1894 mode_ctl |= BGE_MODECTL_STACKUP; 1895 1896 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1897 1898 /* 1899 * Disable memory write invalidate. Apparently it is not supported 1900 * properly by these devices. 1901 */ 1902 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1903 1904 /* Set the timer prescaler (always 66 MHz). */ 1905 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1906 1907 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1908 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1909 DELAY(40); /* XXX */ 1910 1911 /* Put PHY into ready state */ 1912 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1913 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1914 DELAY(40); 1915 } 1916 1917 return (0); 1918 } 1919 1920 static int 1921 bge_blockinit(struct bge_softc *sc) 1922 { 1923 struct bge_rcb *rcb; 1924 bus_size_t vrcb; 1925 bge_hostaddr taddr; 1926 uint32_t dmactl, rdmareg, val; 1927 int i, limit; 1928 1929 /* 1930 * Initialize the memory window pointer register so that 1931 * we can access the first 32K of internal NIC RAM. This will 1932 * allow us to set up the TX send ring RCBs and the RX return 1933 * ring RCBs, plus other things which live in NIC memory. 1934 */ 1935 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1936 1937 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1938 1939 if (!(BGE_IS_5705_PLUS(sc))) { 1940 /* Configure mbuf memory pool */ 1941 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1942 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1943 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1944 else 1945 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1946 1947 /* Configure DMA resource pool */ 1948 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1949 BGE_DMA_DESCRIPTORS); 1950 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1951 } 1952 1953 /* Configure mbuf pool watermarks */ 1954 if (BGE_IS_5717_PLUS(sc)) { 1955 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1956 if (if_getmtu(sc->bge_ifp) > ETHERMTU) { 1957 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 1958 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 1959 } else { 1960 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 1961 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 1962 } 1963 } else if (!BGE_IS_5705_PLUS(sc)) { 1964 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1965 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1966 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1967 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1968 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1969 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1970 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1971 } else { 1972 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1973 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1974 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1975 } 1976 1977 /* Configure DMA resource watermarks */ 1978 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1979 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1980 1981 /* Enable buffer manager */ 1982 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN; 1983 /* 1984 * Change the arbitration algorithm of TXMBUF read request to 1985 * round-robin instead of priority based for BCM5719. When 1986 * TXFIFO is almost empty, RDMA will hold its request until 1987 * TXFIFO is not almost empty. 1988 */ 1989 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 1990 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 1991 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 1992 1993 /* Poll for buffer manager start indication */ 1994 for (i = 0; i < BGE_TIMEOUT; i++) { 1995 DELAY(10); 1996 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1997 break; 1998 } 1999 2000 if (i == BGE_TIMEOUT) { 2001 device_printf(sc->bge_dev, "buffer manager failed to start\n"); 2002 return (ENXIO); 2003 } 2004 2005 /* Enable flow-through queues */ 2006 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2007 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2008 2009 /* Wait until queue initialization is complete */ 2010 for (i = 0; i < BGE_TIMEOUT; i++) { 2011 DELAY(10); 2012 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2013 break; 2014 } 2015 2016 if (i == BGE_TIMEOUT) { 2017 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 2018 return (ENXIO); 2019 } 2020 2021 /* 2022 * Summary of rings supported by the controller: 2023 * 2024 * Standard Receive Producer Ring 2025 * - This ring is used to feed receive buffers for "standard" 2026 * sized frames (typically 1536 bytes) to the controller. 2027 * 2028 * Jumbo Receive Producer Ring 2029 * - This ring is used to feed receive buffers for jumbo sized 2030 * frames (i.e. anything bigger than the "standard" frames) 2031 * to the controller. 2032 * 2033 * Mini Receive Producer Ring 2034 * - This ring is used to feed receive buffers for "mini" 2035 * sized frames to the controller. 2036 * - This feature required external memory for the controller 2037 * but was never used in a production system. Should always 2038 * be disabled. 2039 * 2040 * Receive Return Ring 2041 * - After the controller has placed an incoming frame into a 2042 * receive buffer that buffer is moved into a receive return 2043 * ring. The driver is then responsible to passing the 2044 * buffer up to the stack. Many versions of the controller 2045 * support multiple RR rings. 2046 * 2047 * Send Ring 2048 * - This ring is used for outgoing frames. Many versions of 2049 * the controller support multiple send rings. 2050 */ 2051 2052 /* Initialize the standard receive producer ring control block. */ 2053 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 2054 rcb->bge_hostaddr.bge_addr_lo = 2055 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 2056 rcb->bge_hostaddr.bge_addr_hi = 2057 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 2058 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2059 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 2060 if (BGE_IS_5717_PLUS(sc)) { 2061 /* 2062 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2063 * Bits 15-2 : Maximum RX frame size 2064 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2065 * Bit 0 : Reserved 2066 */ 2067 rcb->bge_maxlen_flags = 2068 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2069 } else if (BGE_IS_5705_PLUS(sc)) { 2070 /* 2071 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2072 * Bits 15-2 : Reserved (should be 0) 2073 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2074 * Bit 0 : Reserved 2075 */ 2076 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2077 } else { 2078 /* 2079 * Ring size is always XXX entries 2080 * Bits 31-16: Maximum RX frame size 2081 * Bits 15-2 : Reserved (should be 0) 2082 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2083 * Bit 0 : Reserved 2084 */ 2085 rcb->bge_maxlen_flags = 2086 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2087 } 2088 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2089 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2090 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2091 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2092 else 2093 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2094 /* Write the standard receive producer ring control block. */ 2095 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2096 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2097 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2098 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2099 2100 /* Reset the standard receive producer ring producer index. */ 2101 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2102 2103 /* 2104 * Initialize the jumbo RX producer ring control 2105 * block. We set the 'ring disabled' bit in the 2106 * flags field until we're actually ready to start 2107 * using this ring (i.e. once we set the MTU 2108 * high enough to require it). 2109 */ 2110 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2111 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 2112 /* Get the jumbo receive producer ring RCB parameters. */ 2113 rcb->bge_hostaddr.bge_addr_lo = 2114 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2115 rcb->bge_hostaddr.bge_addr_hi = 2116 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2117 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2118 sc->bge_cdata.bge_rx_jumbo_ring_map, 2119 BUS_DMASYNC_PREREAD); 2120 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2121 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2122 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2123 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2124 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2125 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2126 else 2127 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2128 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2129 rcb->bge_hostaddr.bge_addr_hi); 2130 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2131 rcb->bge_hostaddr.bge_addr_lo); 2132 /* Program the jumbo receive producer ring RCB parameters. */ 2133 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2134 rcb->bge_maxlen_flags); 2135 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2136 /* Reset the jumbo receive producer ring producer index. */ 2137 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2138 } 2139 2140 /* Disable the mini receive producer ring RCB. */ 2141 if (BGE_IS_5700_FAMILY(sc)) { 2142 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 2143 rcb->bge_maxlen_flags = 2144 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2145 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2146 rcb->bge_maxlen_flags); 2147 /* Reset the mini receive producer ring producer index. */ 2148 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2149 } 2150 2151 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2152 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2153 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2154 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2155 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2156 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2157 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2158 } 2159 /* 2160 * The BD ring replenish thresholds control how often the 2161 * hardware fetches new BD's from the producer rings in host 2162 * memory. Setting the value too low on a busy system can 2163 * starve the hardware and recue the throughpout. 2164 * 2165 * Set the BD ring replentish thresholds. The recommended 2166 * values are 1/8th the number of descriptors allocated to 2167 * each ring. 2168 * XXX The 5754 requires a lower threshold, so it might be a 2169 * requirement of all 575x family chips. The Linux driver sets 2170 * the lower threshold for all 5705 family chips as well, but there 2171 * are reports that it might not need to be so strict. 2172 * 2173 * XXX Linux does some extra fiddling here for the 5906 parts as 2174 * well. 2175 */ 2176 if (BGE_IS_5705_PLUS(sc)) 2177 val = 8; 2178 else 2179 val = BGE_STD_RX_RING_CNT / 8; 2180 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 2181 if (BGE_IS_JUMBO_CAPABLE(sc)) 2182 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 2183 BGE_JUMBO_RX_RING_CNT/8); 2184 if (BGE_IS_5717_PLUS(sc)) { 2185 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32); 2186 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16); 2187 } 2188 2189 /* 2190 * Disable all send rings by setting the 'ring disabled' bit 2191 * in the flags field of all the TX send ring control blocks, 2192 * located in NIC memory. 2193 */ 2194 if (!BGE_IS_5705_PLUS(sc)) 2195 /* 5700 to 5704 had 16 send rings. */ 2196 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2197 else if (BGE_IS_57765_PLUS(sc) || 2198 sc->bge_asicrev == BGE_ASICREV_BCM5762) 2199 limit = 2; 2200 else if (BGE_IS_5717_PLUS(sc)) 2201 limit = 4; 2202 else 2203 limit = 1; 2204 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2205 for (i = 0; i < limit; i++) { 2206 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2207 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2208 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2209 vrcb += sizeof(struct bge_rcb); 2210 } 2211 2212 /* Configure send ring RCB 0 (we use only the first ring) */ 2213 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2214 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 2215 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2216 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2217 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2218 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2219 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2220 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717); 2221 else 2222 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 2223 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2224 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2225 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2226 2227 /* 2228 * Disable all receive return rings by setting the 2229 * 'ring diabled' bit in the flags field of all the receive 2230 * return ring control blocks, located in NIC memory. 2231 */ 2232 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2233 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2234 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2235 /* Should be 17, use 16 until we get an SRAM map. */ 2236 limit = 16; 2237 } else if (!BGE_IS_5705_PLUS(sc)) 2238 limit = BGE_RX_RINGS_MAX; 2239 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2240 sc->bge_asicrev == BGE_ASICREV_BCM5762 || 2241 BGE_IS_57765_PLUS(sc)) 2242 limit = 4; 2243 else 2244 limit = 1; 2245 /* Disable all receive return rings. */ 2246 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2247 for (i = 0; i < limit; i++) { 2248 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 2249 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 2250 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2251 BGE_RCB_FLAG_RING_DISABLED); 2252 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2253 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2254 (i * (sizeof(uint64_t))), 0); 2255 vrcb += sizeof(struct bge_rcb); 2256 } 2257 2258 /* 2259 * Set up receive return ring 0. Note that the NIC address 2260 * for RX return rings is 0x0. The return rings live entirely 2261 * within the host, so the nicaddr field in the RCB isn't used. 2262 */ 2263 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2264 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 2265 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2266 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2267 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2268 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2269 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2270 2271 /* Set random backoff seed for TX */ 2272 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2273 (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 2274 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 2275 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) & 2276 BGE_TX_BACKOFF_SEED_MASK); 2277 2278 /* Set inter-packet gap */ 2279 val = 0x2620; 2280 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 2281 sc->bge_asicrev == BGE_ASICREV_BCM5762) 2282 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2283 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2284 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2285 2286 /* 2287 * Specify which ring to use for packets that don't match 2288 * any RX rules. 2289 */ 2290 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2291 2292 /* 2293 * Configure number of RX lists. One interrupt distribution 2294 * list, sixteen active lists, one bad frames class. 2295 */ 2296 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2297 2298 /* Inialize RX list placement stats mask. */ 2299 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2300 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2301 2302 /* Disable host coalescing until we get it set up */ 2303 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2304 2305 /* Poll to make sure it's shut down. */ 2306 for (i = 0; i < BGE_TIMEOUT; i++) { 2307 DELAY(10); 2308 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2309 break; 2310 } 2311 2312 if (i == BGE_TIMEOUT) { 2313 device_printf(sc->bge_dev, 2314 "host coalescing engine failed to idle\n"); 2315 return (ENXIO); 2316 } 2317 2318 /* Set up host coalescing defaults */ 2319 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2320 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2321 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2322 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2323 if (!(BGE_IS_5705_PLUS(sc))) { 2324 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2325 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2326 } 2327 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 2328 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 2329 2330 /* Set up address of statistics block */ 2331 if (!(BGE_IS_5705_PLUS(sc))) { 2332 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 2333 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 2334 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 2335 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 2336 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2337 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2338 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2339 } 2340 2341 /* Set up address of status block */ 2342 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 2343 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 2344 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 2345 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 2346 2347 /* Set up status block size. */ 2348 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2349 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2350 val = BGE_STATBLKSZ_FULL; 2351 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2352 } else { 2353 val = BGE_STATBLKSZ_32BYTE; 2354 bzero(sc->bge_ldata.bge_status_block, 32); 2355 } 2356 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2357 sc->bge_cdata.bge_status_map, 2358 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2359 2360 /* Turn on host coalescing state machine */ 2361 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2362 2363 /* Turn on RX BD completion state machine and enable attentions */ 2364 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2365 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2366 2367 /* Turn on RX list placement state machine */ 2368 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2369 2370 /* Turn on RX list selector state machine. */ 2371 if (!(BGE_IS_5705_PLUS(sc))) 2372 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2373 2374 /* Turn on DMA, clear stats. */ 2375 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2376 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2377 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2378 BGE_MACMODE_FRMHDR_DMA_ENB; 2379 2380 if (sc->bge_flags & BGE_FLAG_TBI) 2381 val |= BGE_PORTMODE_TBI; 2382 else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 2383 val |= BGE_PORTMODE_GMII; 2384 else 2385 val |= BGE_PORTMODE_MII; 2386 2387 /* Allow APE to send/receive frames. */ 2388 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2389 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2390 2391 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2392 DELAY(40); 2393 2394 /* Set misc. local control, enable interrupts on attentions */ 2395 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2396 2397 #ifdef notdef 2398 /* Assert GPIO pins for PHY reset */ 2399 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 2400 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 2401 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 2402 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 2403 #endif 2404 2405 /* Turn on DMA completion state machine */ 2406 if (!(BGE_IS_5705_PLUS(sc))) 2407 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2408 2409 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2410 2411 /* Enable host coalescing bug fix. */ 2412 if (BGE_IS_5755_PLUS(sc)) 2413 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2414 2415 /* Request larger DMA burst size to get better performance. */ 2416 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) 2417 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2418 2419 /* Turn on write DMA state machine */ 2420 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 2421 DELAY(40); 2422 2423 /* Turn on read DMA state machine */ 2424 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2425 2426 if (sc->bge_asicrev == BGE_ASICREV_BCM5717) 2427 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2428 2429 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2430 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2431 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2432 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2433 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2434 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2435 if (sc->bge_flags & BGE_FLAG_PCIE) 2436 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2437 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 2438 val |= BGE_RDMAMODE_TSO4_ENABLE; 2439 if (sc->bge_flags & BGE_FLAG_TSO3 || 2440 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2441 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2442 val |= BGE_RDMAMODE_TSO6_ENABLE; 2443 } 2444 2445 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 2446 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2447 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2448 BGE_RDMAMODE_H2BNC_VLAN_DET; 2449 /* 2450 * Allow multiple outstanding read requests from 2451 * non-LSO read DMA engine. 2452 */ 2453 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2454 } 2455 2456 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2457 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2458 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2459 sc->bge_asicrev == BGE_ASICREV_BCM57780 || 2460 BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) { 2461 if (sc->bge_asicrev == BGE_ASICREV_BCM5762) 2462 rdmareg = BGE_RDMA_RSRVCTRL_REG2; 2463 else 2464 rdmareg = BGE_RDMA_RSRVCTRL; 2465 dmactl = CSR_READ_4(sc, rdmareg); 2466 /* 2467 * Adjust tx margin to prevent TX data corruption and 2468 * fix internal FIFO overflow. 2469 */ 2470 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2471 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2472 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2473 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2474 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2475 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2476 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2477 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2478 } 2479 /* 2480 * Enable fix for read DMA FIFO overruns. 2481 * The fix is to limit the number of RX BDs 2482 * the hardware would fetch at a fime. 2483 */ 2484 CSR_WRITE_4(sc, rdmareg, dmactl | 2485 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2486 } 2487 2488 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) { 2489 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2490 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2491 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2492 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2493 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2494 /* 2495 * Allow 4KB burst length reads for non-LSO frames. 2496 * Enable 512B burst length reads for buffer descriptors. 2497 */ 2498 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2499 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2500 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2501 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2502 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2503 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2, 2504 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) | 2505 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2506 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2507 } 2508 2509 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 2510 DELAY(40); 2511 2512 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) { 2513 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 2514 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 2515 if ((val & 0xFFFF) > BGE_FRAMELEN) 2516 break; 2517 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 2518 break; 2519 } 2520 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 2521 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 2522 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 2523 val |= BGE_RDMA_TX_LENGTH_WA_5719; 2524 else 2525 val |= BGE_RDMA_TX_LENGTH_WA_5720; 2526 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 2527 } 2528 } 2529 2530 /* Turn on RX data completion state machine */ 2531 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2532 2533 /* Turn on RX BD initiator state machine */ 2534 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2535 2536 /* Turn on RX data and RX BD initiator state machine */ 2537 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2538 2539 /* Turn on Mbuf cluster free state machine */ 2540 if (!(BGE_IS_5705_PLUS(sc))) 2541 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2542 2543 /* Turn on send BD completion state machine */ 2544 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2545 2546 /* Turn on send data completion state machine */ 2547 val = BGE_SDCMODE_ENABLE; 2548 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 2549 val |= BGE_SDCMODE_CDELAY; 2550 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2551 2552 /* Turn on send data initiator state machine */ 2553 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) 2554 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2555 BGE_SDIMODE_HW_LSO_PRE_DMA); 2556 else 2557 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2558 2559 /* Turn on send BD initiator state machine */ 2560 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2561 2562 /* Turn on send BD selector state machine */ 2563 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2564 2565 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2566 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2567 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2568 2569 /* ack/clear link change events */ 2570 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2571 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2572 BGE_MACSTAT_LINK_CHANGED); 2573 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2574 2575 /* 2576 * Enable attention when the link has changed state for 2577 * devices that use auto polling. 2578 */ 2579 if (sc->bge_flags & BGE_FLAG_TBI) { 2580 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2581 } else { 2582 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 2583 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 2584 DELAY(80); 2585 } 2586 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2587 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 2588 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2589 BGE_EVTENB_MI_INTERRUPT); 2590 } 2591 2592 /* 2593 * Clear any pending link state attention. 2594 * Otherwise some link state change events may be lost until attention 2595 * is cleared by bge_intr() -> bge_link_upd() sequence. 2596 * It's not necessary on newer BCM chips - perhaps enabling link 2597 * state change attentions implies clearing pending attention. 2598 */ 2599 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2600 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2601 BGE_MACSTAT_LINK_CHANGED); 2602 2603 /* Enable link state change attentions. */ 2604 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2605 2606 return (0); 2607 } 2608 2609 static const struct bge_revision * 2610 bge_lookup_rev(uint32_t chipid) 2611 { 2612 const struct bge_revision *br; 2613 2614 for (br = bge_revisions; br->br_name != NULL; br++) { 2615 if (br->br_chipid == chipid) 2616 return (br); 2617 } 2618 2619 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2620 if (br->br_chipid == BGE_ASICREV(chipid)) 2621 return (br); 2622 } 2623 2624 return (NULL); 2625 } 2626 2627 static const struct bge_vendor * 2628 bge_lookup_vendor(uint16_t vid) 2629 { 2630 const struct bge_vendor *v; 2631 2632 for (v = bge_vendors; v->v_name != NULL; v++) 2633 if (v->v_id == vid) 2634 return (v); 2635 2636 return (NULL); 2637 } 2638 2639 static uint32_t 2640 bge_chipid(device_t dev) 2641 { 2642 uint32_t id; 2643 2644 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2645 BGE_PCIMISCCTL_ASICREV_SHIFT; 2646 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 2647 /* 2648 * Find the ASCI revision. Different chips use different 2649 * registers. 2650 */ 2651 switch (pci_get_device(dev)) { 2652 case BCOM_DEVICEID_BCM5717C: 2653 /* 5717 C0 seems to belong to 5720 line. */ 2654 id = BGE_CHIPID_BCM5720_A0; 2655 break; 2656 case BCOM_DEVICEID_BCM5717: 2657 case BCOM_DEVICEID_BCM5718: 2658 case BCOM_DEVICEID_BCM5719: 2659 case BCOM_DEVICEID_BCM5720: 2660 case BCOM_DEVICEID_BCM5725: 2661 case BCOM_DEVICEID_BCM5727: 2662 case BCOM_DEVICEID_BCM5762: 2663 case BCOM_DEVICEID_BCM57764: 2664 case BCOM_DEVICEID_BCM57767: 2665 case BCOM_DEVICEID_BCM57787: 2666 id = pci_read_config(dev, 2667 BGE_PCI_GEN2_PRODID_ASICREV, 4); 2668 break; 2669 case BCOM_DEVICEID_BCM57761: 2670 case BCOM_DEVICEID_BCM57762: 2671 case BCOM_DEVICEID_BCM57765: 2672 case BCOM_DEVICEID_BCM57766: 2673 case BCOM_DEVICEID_BCM57781: 2674 case BCOM_DEVICEID_BCM57782: 2675 case BCOM_DEVICEID_BCM57785: 2676 case BCOM_DEVICEID_BCM57786: 2677 case BCOM_DEVICEID_BCM57791: 2678 case BCOM_DEVICEID_BCM57795: 2679 id = pci_read_config(dev, 2680 BGE_PCI_GEN15_PRODID_ASICREV, 4); 2681 break; 2682 default: 2683 id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4); 2684 } 2685 } 2686 return (id); 2687 } 2688 2689 /* 2690 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2691 * against our list and return its name if we find a match. 2692 * 2693 * Note that since the Broadcom controller contains VPD support, we 2694 * try to get the device name string from the controller itself instead 2695 * of the compiled-in string. It guarantees we'll always announce the 2696 * right product name. We fall back to the compiled-in string when 2697 * VPD is unavailable or corrupt. 2698 */ 2699 static int 2700 bge_probe(device_t dev) 2701 { 2702 char buf[96]; 2703 char model[64]; 2704 const struct bge_revision *br; 2705 const char *pname; 2706 struct bge_softc *sc; 2707 const struct bge_type *t = bge_devs; 2708 const struct bge_vendor *v; 2709 uint32_t id; 2710 uint16_t did, vid; 2711 2712 sc = device_get_softc(dev); 2713 sc->bge_dev = dev; 2714 vid = pci_get_vendor(dev); 2715 did = pci_get_device(dev); 2716 while(t->bge_vid != 0) { 2717 if ((vid == t->bge_vid) && (did == t->bge_did)) { 2718 id = bge_chipid(dev); 2719 br = bge_lookup_rev(id); 2720 if (bge_has_eaddr(sc) && 2721 pci_get_vpd_ident(dev, &pname) == 0) 2722 snprintf(model, sizeof(model), "%s", pname); 2723 else { 2724 v = bge_lookup_vendor(vid); 2725 snprintf(model, sizeof(model), "%s %s", 2726 v != NULL ? v->v_name : "Unknown", 2727 br != NULL ? br->br_name : 2728 "NetXtreme/NetLink Ethernet Controller"); 2729 } 2730 snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x", 2731 model, br != NULL ? "" : "unknown ", id); 2732 device_set_desc_copy(dev, buf); 2733 return (BUS_PROBE_DEFAULT); 2734 } 2735 t++; 2736 } 2737 2738 return (ENXIO); 2739 } 2740 2741 static void 2742 bge_dma_free(struct bge_softc *sc) 2743 { 2744 int i; 2745 2746 /* Destroy DMA maps for RX buffers. */ 2747 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2748 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 2749 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2750 sc->bge_cdata.bge_rx_std_dmamap[i]); 2751 } 2752 if (sc->bge_cdata.bge_rx_std_sparemap) 2753 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2754 sc->bge_cdata.bge_rx_std_sparemap); 2755 2756 /* Destroy DMA maps for jumbo RX buffers. */ 2757 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2758 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 2759 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2760 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2761 } 2762 if (sc->bge_cdata.bge_rx_jumbo_sparemap) 2763 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2764 sc->bge_cdata.bge_rx_jumbo_sparemap); 2765 2766 /* Destroy DMA maps for TX buffers. */ 2767 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2768 if (sc->bge_cdata.bge_tx_dmamap[i]) 2769 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 2770 sc->bge_cdata.bge_tx_dmamap[i]); 2771 } 2772 2773 if (sc->bge_cdata.bge_rx_mtag) 2774 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 2775 if (sc->bge_cdata.bge_mtag_jumbo) 2776 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo); 2777 if (sc->bge_cdata.bge_tx_mtag) 2778 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 2779 2780 /* Destroy standard RX ring. */ 2781 if (sc->bge_ldata.bge_rx_std_ring_paddr) 2782 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 2783 sc->bge_cdata.bge_rx_std_ring_map); 2784 if (sc->bge_ldata.bge_rx_std_ring) 2785 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 2786 sc->bge_ldata.bge_rx_std_ring, 2787 sc->bge_cdata.bge_rx_std_ring_map); 2788 2789 if (sc->bge_cdata.bge_rx_std_ring_tag) 2790 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 2791 2792 /* Destroy jumbo RX ring. */ 2793 if (sc->bge_ldata.bge_rx_jumbo_ring_paddr) 2794 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2795 sc->bge_cdata.bge_rx_jumbo_ring_map); 2796 2797 if (sc->bge_ldata.bge_rx_jumbo_ring) 2798 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2799 sc->bge_ldata.bge_rx_jumbo_ring, 2800 sc->bge_cdata.bge_rx_jumbo_ring_map); 2801 2802 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 2803 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 2804 2805 /* Destroy RX return ring. */ 2806 if (sc->bge_ldata.bge_rx_return_ring_paddr) 2807 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 2808 sc->bge_cdata.bge_rx_return_ring_map); 2809 2810 if (sc->bge_ldata.bge_rx_return_ring) 2811 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 2812 sc->bge_ldata.bge_rx_return_ring, 2813 sc->bge_cdata.bge_rx_return_ring_map); 2814 2815 if (sc->bge_cdata.bge_rx_return_ring_tag) 2816 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 2817 2818 /* Destroy TX ring. */ 2819 if (sc->bge_ldata.bge_tx_ring_paddr) 2820 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 2821 sc->bge_cdata.bge_tx_ring_map); 2822 2823 if (sc->bge_ldata.bge_tx_ring) 2824 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 2825 sc->bge_ldata.bge_tx_ring, 2826 sc->bge_cdata.bge_tx_ring_map); 2827 2828 if (sc->bge_cdata.bge_tx_ring_tag) 2829 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 2830 2831 /* Destroy status block. */ 2832 if (sc->bge_ldata.bge_status_block_paddr) 2833 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 2834 sc->bge_cdata.bge_status_map); 2835 2836 if (sc->bge_ldata.bge_status_block) 2837 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2838 sc->bge_ldata.bge_status_block, 2839 sc->bge_cdata.bge_status_map); 2840 2841 if (sc->bge_cdata.bge_status_tag) 2842 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2843 2844 /* Destroy statistics block. */ 2845 if (sc->bge_ldata.bge_stats_paddr) 2846 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2847 sc->bge_cdata.bge_stats_map); 2848 2849 if (sc->bge_ldata.bge_stats) 2850 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2851 sc->bge_ldata.bge_stats, 2852 sc->bge_cdata.bge_stats_map); 2853 2854 if (sc->bge_cdata.bge_stats_tag) 2855 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2856 2857 if (sc->bge_cdata.bge_buffer_tag) 2858 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag); 2859 2860 /* Destroy the parent tag. */ 2861 if (sc->bge_cdata.bge_parent_tag) 2862 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2863 } 2864 2865 static int 2866 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment, 2867 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 2868 bus_addr_t *paddr, const char *msg) 2869 { 2870 struct bge_dmamap_arg ctx; 2871 bus_addr_t lowaddr; 2872 bus_size_t ring_end; 2873 int error; 2874 2875 lowaddr = BUS_SPACE_MAXADDR; 2876 again: 2877 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2878 alignment, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2879 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 2880 if (error != 0) { 2881 device_printf(sc->bge_dev, 2882 "could not create %s dma tag\n", msg); 2883 return (ENOMEM); 2884 } 2885 /* Allocate DMA'able memory for ring. */ 2886 error = bus_dmamem_alloc(*tag, (void **)ring, 2887 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 2888 if (error != 0) { 2889 device_printf(sc->bge_dev, 2890 "could not allocate DMA'able memory for %s\n", msg); 2891 return (ENOMEM); 2892 } 2893 /* Load the address of the ring. */ 2894 ctx.bge_busaddr = 0; 2895 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr, 2896 &ctx, BUS_DMA_NOWAIT); 2897 if (error != 0) { 2898 device_printf(sc->bge_dev, 2899 "could not load DMA'able memory for %s\n", msg); 2900 return (ENOMEM); 2901 } 2902 *paddr = ctx.bge_busaddr; 2903 ring_end = *paddr + maxsize; 2904 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0 && 2905 BGE_ADDR_HI(*paddr) != BGE_ADDR_HI(ring_end)) { 2906 /* 2907 * 4GB boundary crossed. Limit maximum allowable DMA 2908 * address space to 32bit and try again. 2909 */ 2910 bus_dmamap_unload(*tag, *map); 2911 bus_dmamem_free(*tag, *ring, *map); 2912 bus_dma_tag_destroy(*tag); 2913 if (bootverbose) 2914 device_printf(sc->bge_dev, "4GB boundary crossed, " 2915 "limit DMA address space to 32bit for %s\n", msg); 2916 *ring = NULL; 2917 *tag = NULL; 2918 *map = NULL; 2919 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2920 goto again; 2921 } 2922 return (0); 2923 } 2924 2925 static int 2926 bge_dma_alloc(struct bge_softc *sc) 2927 { 2928 bus_addr_t lowaddr; 2929 bus_size_t boundary, sbsz, rxmaxsegsz, txsegsz, txmaxsegsz; 2930 int i, error; 2931 2932 lowaddr = BUS_SPACE_MAXADDR; 2933 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0) 2934 lowaddr = BGE_DMA_MAXADDR; 2935 /* 2936 * Allocate the parent bus DMA tag appropriate for PCI. 2937 */ 2938 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2939 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2940 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2941 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2942 if (error != 0) { 2943 device_printf(sc->bge_dev, 2944 "could not allocate parent dma tag\n"); 2945 return (ENOMEM); 2946 } 2947 2948 /* Create tag for standard RX ring. */ 2949 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ, 2950 &sc->bge_cdata.bge_rx_std_ring_tag, 2951 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring, 2952 &sc->bge_cdata.bge_rx_std_ring_map, 2953 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring"); 2954 if (error) 2955 return (error); 2956 2957 /* Create tag for RX return ring. */ 2958 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc), 2959 &sc->bge_cdata.bge_rx_return_ring_tag, 2960 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring, 2961 &sc->bge_cdata.bge_rx_return_ring_map, 2962 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring"); 2963 if (error) 2964 return (error); 2965 2966 /* Create tag for TX ring. */ 2967 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ, 2968 &sc->bge_cdata.bge_tx_ring_tag, 2969 (uint8_t **)&sc->bge_ldata.bge_tx_ring, 2970 &sc->bge_cdata.bge_tx_ring_map, 2971 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring"); 2972 if (error) 2973 return (error); 2974 2975 /* 2976 * Create tag for status block. 2977 * Because we only use single Tx/Rx/Rx return ring, use 2978 * minimum status block size except BCM5700 AX/BX which 2979 * seems to want to see full status block size regardless 2980 * of configured number of ring. 2981 */ 2982 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2983 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 2984 sbsz = BGE_STATUS_BLK_SZ; 2985 else 2986 sbsz = 32; 2987 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz, 2988 &sc->bge_cdata.bge_status_tag, 2989 (uint8_t **)&sc->bge_ldata.bge_status_block, 2990 &sc->bge_cdata.bge_status_map, 2991 &sc->bge_ldata.bge_status_block_paddr, "status block"); 2992 if (error) 2993 return (error); 2994 2995 /* Create tag for statistics block. */ 2996 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ, 2997 &sc->bge_cdata.bge_stats_tag, 2998 (uint8_t **)&sc->bge_ldata.bge_stats, 2999 &sc->bge_cdata.bge_stats_map, 3000 &sc->bge_ldata.bge_stats_paddr, "statistics block"); 3001 if (error) 3002 return (error); 3003 3004 /* Create tag for jumbo RX ring. */ 3005 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3006 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ, 3007 &sc->bge_cdata.bge_rx_jumbo_ring_tag, 3008 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring, 3009 &sc->bge_cdata.bge_rx_jumbo_ring_map, 3010 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring"); 3011 if (error) 3012 return (error); 3013 } 3014 3015 /* Create parent tag for buffers. */ 3016 boundary = 0; 3017 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) { 3018 boundary = BGE_DMA_BNDRY; 3019 /* 3020 * XXX 3021 * watchdog timeout issue was observed on BCM5704 which 3022 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge). 3023 * Both limiting DMA address space to 32bits and flushing 3024 * mailbox write seem to address the issue. 3025 */ 3026 if (sc->bge_pcixcap != 0) 3027 lowaddr = BUS_SPACE_MAXADDR_32BIT; 3028 } 3029 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 3030 1, boundary, lowaddr, BUS_SPACE_MAXADDR, NULL, 3031 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 3032 0, NULL, NULL, &sc->bge_cdata.bge_buffer_tag); 3033 if (error != 0) { 3034 device_printf(sc->bge_dev, 3035 "could not allocate buffer dma tag\n"); 3036 return (ENOMEM); 3037 } 3038 /* Create tag for Tx mbufs. */ 3039 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 3040 txsegsz = BGE_TSOSEG_SZ; 3041 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header); 3042 } else { 3043 txsegsz = MCLBYTES; 3044 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW; 3045 } 3046 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 3047 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 3048 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL, 3049 &sc->bge_cdata.bge_tx_mtag); 3050 3051 if (error) { 3052 device_printf(sc->bge_dev, "could not allocate TX dma tag\n"); 3053 return (ENOMEM); 3054 } 3055 3056 /* Create tag for Rx mbufs. */ 3057 if (sc->bge_flags & BGE_FLAG_JUMBO_STD) 3058 rxmaxsegsz = MJUM9BYTES; 3059 else 3060 rxmaxsegsz = MCLBYTES; 3061 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0, 3062 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1, 3063 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag); 3064 3065 if (error) { 3066 device_printf(sc->bge_dev, "could not allocate RX dma tag\n"); 3067 return (ENOMEM); 3068 } 3069 3070 /* Create DMA maps for RX buffers. */ 3071 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3072 &sc->bge_cdata.bge_rx_std_sparemap); 3073 if (error) { 3074 device_printf(sc->bge_dev, 3075 "can't create spare DMA map for RX\n"); 3076 return (ENOMEM); 3077 } 3078 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 3079 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3080 &sc->bge_cdata.bge_rx_std_dmamap[i]); 3081 if (error) { 3082 device_printf(sc->bge_dev, 3083 "can't create DMA map for RX\n"); 3084 return (ENOMEM); 3085 } 3086 } 3087 3088 /* Create DMA maps for TX buffers. */ 3089 for (i = 0; i < BGE_TX_RING_CNT; i++) { 3090 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0, 3091 &sc->bge_cdata.bge_tx_dmamap[i]); 3092 if (error) { 3093 device_printf(sc->bge_dev, 3094 "can't create DMA map for TX\n"); 3095 return (ENOMEM); 3096 } 3097 } 3098 3099 /* Create tags for jumbo RX buffers. */ 3100 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3101 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 3102 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 3103 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 3104 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 3105 if (error) { 3106 device_printf(sc->bge_dev, 3107 "could not allocate jumbo dma tag\n"); 3108 return (ENOMEM); 3109 } 3110 /* Create DMA maps for jumbo RX buffers. */ 3111 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3112 0, &sc->bge_cdata.bge_rx_jumbo_sparemap); 3113 if (error) { 3114 device_printf(sc->bge_dev, 3115 "can't create spare DMA map for jumbo RX\n"); 3116 return (ENOMEM); 3117 } 3118 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 3119 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3120 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 3121 if (error) { 3122 device_printf(sc->bge_dev, 3123 "can't create DMA map for jumbo RX\n"); 3124 return (ENOMEM); 3125 } 3126 } 3127 } 3128 3129 return (0); 3130 } 3131 3132 /* 3133 * Return true if this device has more than one port. 3134 */ 3135 static int 3136 bge_has_multiple_ports(struct bge_softc *sc) 3137 { 3138 device_t dev = sc->bge_dev; 3139 u_int b, d, f, fscan, s; 3140 3141 d = pci_get_domain(dev); 3142 b = pci_get_bus(dev); 3143 s = pci_get_slot(dev); 3144 f = pci_get_function(dev); 3145 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 3146 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 3147 return (1); 3148 return (0); 3149 } 3150 3151 /* 3152 * Return true if MSI can be used with this device. 3153 */ 3154 static int 3155 bge_can_use_msi(struct bge_softc *sc) 3156 { 3157 int can_use_msi = 0; 3158 3159 if (sc->bge_msi == 0) 3160 return (0); 3161 3162 /* Disable MSI for polling(4). */ 3163 #ifdef DEVICE_POLLING 3164 return (0); 3165 #endif 3166 switch (sc->bge_asicrev) { 3167 case BGE_ASICREV_BCM5714_A0: 3168 case BGE_ASICREV_BCM5714: 3169 /* 3170 * Apparently, MSI doesn't work when these chips are 3171 * configured in single-port mode. 3172 */ 3173 if (bge_has_multiple_ports(sc)) 3174 can_use_msi = 1; 3175 break; 3176 case BGE_ASICREV_BCM5750: 3177 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 3178 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 3179 can_use_msi = 1; 3180 break; 3181 case BGE_ASICREV_BCM5784: 3182 /* 3183 * Prevent infinite "watchdog timeout" errors 3184 * in some MacBook Pro and make it work out-of-the-box. 3185 */ 3186 if (sc->bge_chiprev == BGE_CHIPREV_5784_AX) 3187 break; 3188 /* FALLTHROUGH */ 3189 default: 3190 if (BGE_IS_575X_PLUS(sc)) 3191 can_use_msi = 1; 3192 } 3193 return (can_use_msi); 3194 } 3195 3196 static int 3197 bge_mbox_reorder(struct bge_softc *sc) 3198 { 3199 /* Lists of PCI bridges that are known to reorder mailbox writes. */ 3200 static const struct mbox_reorder { 3201 const uint16_t vendor; 3202 const uint16_t device; 3203 const char *desc; 3204 } mbox_reorder_lists[] = { 3205 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" }, 3206 }; 3207 devclass_t pci, pcib; 3208 device_t bus, dev; 3209 int i; 3210 3211 pci = devclass_find("pci"); 3212 pcib = devclass_find("pcib"); 3213 dev = sc->bge_dev; 3214 bus = device_get_parent(dev); 3215 for (;;) { 3216 dev = device_get_parent(bus); 3217 bus = device_get_parent(dev); 3218 if (device_get_devclass(dev) != pcib) 3219 break; 3220 if (device_get_devclass(bus) != pci) 3221 break; 3222 for (i = 0; i < nitems(mbox_reorder_lists); i++) { 3223 if (pci_get_vendor(dev) == 3224 mbox_reorder_lists[i].vendor && 3225 pci_get_device(dev) == 3226 mbox_reorder_lists[i].device) { 3227 device_printf(sc->bge_dev, 3228 "enabling MBOX workaround for %s\n", 3229 mbox_reorder_lists[i].desc); 3230 return (1); 3231 } 3232 } 3233 } 3234 return (0); 3235 } 3236 3237 static void 3238 bge_devinfo(struct bge_softc *sc) 3239 { 3240 uint32_t cfg, clk; 3241 3242 device_printf(sc->bge_dev, 3243 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ", 3244 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev); 3245 if (sc->bge_flags & BGE_FLAG_PCIE) 3246 printf("PCI-E\n"); 3247 else if (sc->bge_flags & BGE_FLAG_PCIX) { 3248 printf("PCI-X "); 3249 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3250 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE) 3251 clk = 133; 3252 else { 3253 clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 3254 switch (clk) { 3255 case 0: 3256 clk = 33; 3257 break; 3258 case 2: 3259 clk = 50; 3260 break; 3261 case 4: 3262 clk = 66; 3263 break; 3264 case 6: 3265 clk = 100; 3266 break; 3267 case 7: 3268 clk = 133; 3269 break; 3270 } 3271 } 3272 printf("%u MHz\n", clk); 3273 } else { 3274 if (sc->bge_pcixcap != 0) 3275 printf("PCI on PCI-X "); 3276 else 3277 printf("PCI "); 3278 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4); 3279 if (cfg & BGE_PCISTATE_PCI_BUSSPEED) 3280 clk = 66; 3281 else 3282 clk = 33; 3283 if (cfg & BGE_PCISTATE_32BIT_BUS) 3284 printf("%u MHz; 32bit\n", clk); 3285 else 3286 printf("%u MHz; 64bit\n", clk); 3287 } 3288 } 3289 3290 static int 3291 bge_attach(device_t dev) 3292 { 3293 if_t ifp; 3294 struct bge_softc *sc; 3295 uint32_t hwcfg = 0, misccfg, pcistate; 3296 u_char eaddr[ETHER_ADDR_LEN]; 3297 int capmask, error, reg, rid, trys; 3298 3299 sc = device_get_softc(dev); 3300 sc->bge_dev = dev; 3301 3302 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 3303 NET_TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); 3304 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 3305 3306 pci_enable_busmaster(dev); 3307 3308 /* 3309 * Allocate control/status registers. 3310 */ 3311 rid = PCIR_BAR(0); 3312 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3313 RF_ACTIVE); 3314 3315 if (sc->bge_res == NULL) { 3316 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n"); 3317 error = ENXIO; 3318 goto fail; 3319 } 3320 3321 /* Save various chip information. */ 3322 sc->bge_func_addr = pci_get_function(dev); 3323 sc->bge_chipid = bge_chipid(dev); 3324 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 3325 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 3326 3327 /* Set default PHY address. */ 3328 sc->bge_phy_addr = 1; 3329 /* 3330 * PHY address mapping for various devices. 3331 * 3332 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 3333 * ---------+-------+-------+-------+-------+ 3334 * BCM57XX | 1 | X | X | X | 3335 * BCM5704 | 1 | X | 1 | X | 3336 * BCM5717 | 1 | 8 | 2 | 9 | 3337 * BCM5719 | 1 | 8 | 2 | 9 | 3338 * BCM5720 | 1 | 8 | 2 | 9 | 3339 * 3340 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 3341 * ---------+-------+-------+-------+-------+ 3342 * BCM57XX | X | X | X | X | 3343 * BCM5704 | X | X | X | X | 3344 * BCM5717 | X | X | X | X | 3345 * BCM5719 | 3 | 10 | 4 | 11 | 3346 * BCM5720 | X | X | X | X | 3347 * 3348 * Other addresses may respond but they are not 3349 * IEEE compliant PHYs and should be ignored. 3350 */ 3351 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 3352 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3353 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 3354 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 3355 if (CSR_READ_4(sc, BGE_SGDIG_STS) & 3356 BGE_SGDIGSTS_IS_SERDES) 3357 sc->bge_phy_addr = sc->bge_func_addr + 8; 3358 else 3359 sc->bge_phy_addr = sc->bge_func_addr + 1; 3360 } else { 3361 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 3362 BGE_CPMU_PHY_STRAP_IS_SERDES) 3363 sc->bge_phy_addr = sc->bge_func_addr + 8; 3364 else 3365 sc->bge_phy_addr = sc->bge_func_addr + 1; 3366 } 3367 } 3368 3369 if (bge_has_eaddr(sc)) 3370 sc->bge_flags |= BGE_FLAG_EADDR; 3371 3372 /* Save chipset family. */ 3373 switch (sc->bge_asicrev) { 3374 case BGE_ASICREV_BCM5762: 3375 case BGE_ASICREV_BCM57765: 3376 case BGE_ASICREV_BCM57766: 3377 sc->bge_flags |= BGE_FLAG_57765_PLUS; 3378 /* FALLTHROUGH */ 3379 case BGE_ASICREV_BCM5717: 3380 case BGE_ASICREV_BCM5719: 3381 case BGE_ASICREV_BCM5720: 3382 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS | 3383 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO | 3384 BGE_FLAG_JUMBO_FRAME; 3385 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3386 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 3387 /* 3388 * Enable work around for DMA engine miscalculation 3389 * of TXMBUF available space. 3390 */ 3391 sc->bge_flags |= BGE_FLAG_RDMA_BUG; 3392 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3393 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3394 /* Jumbo frame on BCM5719 A0 does not work. */ 3395 sc->bge_flags &= ~BGE_FLAG_JUMBO; 3396 } 3397 } 3398 break; 3399 case BGE_ASICREV_BCM5755: 3400 case BGE_ASICREV_BCM5761: 3401 case BGE_ASICREV_BCM5784: 3402 case BGE_ASICREV_BCM5785: 3403 case BGE_ASICREV_BCM5787: 3404 case BGE_ASICREV_BCM57780: 3405 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 3406 BGE_FLAG_5705_PLUS; 3407 break; 3408 case BGE_ASICREV_BCM5700: 3409 case BGE_ASICREV_BCM5701: 3410 case BGE_ASICREV_BCM5703: 3411 case BGE_ASICREV_BCM5704: 3412 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 3413 break; 3414 case BGE_ASICREV_BCM5714_A0: 3415 case BGE_ASICREV_BCM5780: 3416 case BGE_ASICREV_BCM5714: 3417 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD; 3418 /* FALLTHROUGH */ 3419 case BGE_ASICREV_BCM5750: 3420 case BGE_ASICREV_BCM5752: 3421 case BGE_ASICREV_BCM5906: 3422 sc->bge_flags |= BGE_FLAG_575X_PLUS; 3423 /* FALLTHROUGH */ 3424 case BGE_ASICREV_BCM5705: 3425 sc->bge_flags |= BGE_FLAG_5705_PLUS; 3426 break; 3427 } 3428 3429 /* Identify chips with APE processor. */ 3430 switch (sc->bge_asicrev) { 3431 case BGE_ASICREV_BCM5717: 3432 case BGE_ASICREV_BCM5719: 3433 case BGE_ASICREV_BCM5720: 3434 case BGE_ASICREV_BCM5761: 3435 case BGE_ASICREV_BCM5762: 3436 sc->bge_flags |= BGE_FLAG_APE; 3437 break; 3438 } 3439 3440 /* Chips with APE need BAR2 access for APE registers/memory. */ 3441 if ((sc->bge_flags & BGE_FLAG_APE) != 0) { 3442 rid = PCIR_BAR(2); 3443 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3444 RF_ACTIVE); 3445 if (sc->bge_res2 == NULL) { 3446 device_printf (sc->bge_dev, 3447 "couldn't map BAR2 memory\n"); 3448 error = ENXIO; 3449 goto fail; 3450 } 3451 3452 /* Enable APE register/memory access by host driver. */ 3453 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 3454 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3455 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3456 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3457 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4); 3458 3459 bge_ape_lock_init(sc); 3460 bge_ape_read_fw_ver(sc); 3461 } 3462 3463 /* Add SYSCTLs, requires the chipset family to be set. */ 3464 bge_add_sysctls(sc); 3465 3466 /* Identify the chips that use an CPMU. */ 3467 if (BGE_IS_5717_PLUS(sc) || 3468 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3469 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3470 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 3471 sc->bge_asicrev == BGE_ASICREV_BCM57780) 3472 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT; 3473 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0) 3474 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST; 3475 else 3476 sc->bge_mi_mode = BGE_MIMODE_BASE; 3477 /* Enable auto polling for BCM570[0-5]. */ 3478 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) 3479 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL; 3480 3481 /* 3482 * All Broadcom controllers have 4GB boundary DMA bug. 3483 * Whenever an address crosses a multiple of the 4GB boundary 3484 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 3485 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 3486 * state machine will lockup and cause the device to hang. 3487 */ 3488 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG; 3489 3490 /* BCM5755 or higher and BCM5906 have short DMA bug. */ 3491 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 3492 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG; 3493 3494 /* 3495 * BCM5719 cannot handle DMA requests for DMA segments that 3496 * have larger than 4KB in size. However the maximum DMA 3497 * segment size created in DMA tag is 4KB for TSO, so we 3498 * wouldn't encounter the issue here. 3499 */ 3500 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 3501 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG; 3502 3503 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3504 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 3505 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3506 misccfg == BGE_MISCCFG_BOARD_ID_5788M) 3507 sc->bge_flags |= BGE_FLAG_5788; 3508 } 3509 3510 capmask = BMSR_DEFCAPMASK; 3511 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 && 3512 (misccfg == 0x4000 || misccfg == 0x8000)) || 3513 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3514 pci_get_vendor(dev) == BCOM_VENDORID && 3515 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 || 3516 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 || 3517 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) || 3518 (pci_get_vendor(dev) == BCOM_VENDORID && 3519 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F || 3520 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F || 3521 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) || 3522 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 || 3523 pci_get_device(dev) == BCOM_DEVICEID_BCM57791 || 3524 pci_get_device(dev) == BCOM_DEVICEID_BCM57795 || 3525 sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3526 /* These chips are 10/100 only. */ 3527 capmask &= ~BMSR_EXTSTAT; 3528 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3529 } 3530 3531 /* 3532 * Some controllers seem to require a special firmware to use 3533 * TSO. But the firmware is not available to FreeBSD and Linux 3534 * claims that the TSO performed by the firmware is slower than 3535 * hardware based TSO. Moreover the firmware based TSO has one 3536 * known bug which can't handle TSO if Ethernet header + IP/TCP 3537 * header is greater than 80 bytes. A workaround for the TSO 3538 * bug exist but it seems it's too expensive than not using 3539 * TSO at all. Some hardwares also have the TSO bug so limit 3540 * the TSO to the controllers that are not affected TSO issues 3541 * (e.g. 5755 or higher). 3542 */ 3543 if (BGE_IS_5717_PLUS(sc)) { 3544 /* BCM5717 requires different TSO configuration. */ 3545 sc->bge_flags |= BGE_FLAG_TSO3; 3546 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3547 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3548 /* TSO on BCM5719 A0 does not work. */ 3549 sc->bge_flags &= ~BGE_FLAG_TSO3; 3550 } 3551 } else if (BGE_IS_5755_PLUS(sc)) { 3552 /* 3553 * BCM5754 and BCM5787 shares the same ASIC id so 3554 * explicit device id check is required. 3555 * Due to unknown reason TSO does not work on BCM5755M. 3556 */ 3557 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 && 3558 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M && 3559 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M) 3560 sc->bge_flags |= BGE_FLAG_TSO; 3561 } 3562 3563 /* 3564 * Check if this is a PCI-X or PCI Express device. 3565 */ 3566 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 3567 /* 3568 * Found a PCI Express capabilities register, this 3569 * must be a PCI Express device. 3570 */ 3571 sc->bge_flags |= BGE_FLAG_PCIE; 3572 sc->bge_expcap = reg; 3573 /* Extract supported maximum payload size. */ 3574 sc->bge_mps = pci_read_config(dev, sc->bge_expcap + 3575 PCIER_DEVICE_CAP, 2); 3576 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD); 3577 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3578 sc->bge_asicrev == BGE_ASICREV_BCM5720) 3579 sc->bge_expmrq = 2048; 3580 else 3581 sc->bge_expmrq = 4096; 3582 pci_set_max_read_req(dev, sc->bge_expmrq); 3583 } else { 3584 /* 3585 * Check if the device is in PCI-X Mode. 3586 * (This bit is not valid on PCI Express controllers.) 3587 */ 3588 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) 3589 sc->bge_pcixcap = reg; 3590 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 3591 BGE_PCISTATE_PCI_BUSMODE) == 0) 3592 sc->bge_flags |= BGE_FLAG_PCIX; 3593 } 3594 3595 /* 3596 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3597 * not actually a MAC controller bug but an issue with the embedded 3598 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3599 */ 3600 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX)) 3601 sc->bge_flags |= BGE_FLAG_40BIT_BUG; 3602 /* 3603 * Some PCI-X bridges are known to trigger write reordering to 3604 * the mailbox registers. Typical phenomena is watchdog timeouts 3605 * caused by out-of-order TX completions. Enable workaround for 3606 * PCI-X devices that live behind these bridges. 3607 * Note, PCI-X controllers can run in PCI mode so we can't use 3608 * BGE_FLAG_PCIX flag to detect PCI-X controllers. 3609 */ 3610 if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0) 3611 sc->bge_flags |= BGE_FLAG_MBOX_REORDER; 3612 /* 3613 * Allocate the interrupt, using MSI if possible. These devices 3614 * support 8 MSI messages, but only the first one is used in 3615 * normal operation. 3616 */ 3617 rid = 0; 3618 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) { 3619 sc->bge_msicap = reg; 3620 reg = 1; 3621 if (bge_can_use_msi(sc) && pci_alloc_msi(dev, ®) == 0) { 3622 rid = 1; 3623 sc->bge_flags |= BGE_FLAG_MSI; 3624 } 3625 } 3626 3627 /* 3628 * All controllers except BCM5700 supports tagged status but 3629 * we use tagged status only for MSI case on BCM5717. Otherwise 3630 * MSI on BCM5717 does not work. 3631 */ 3632 #ifndef DEVICE_POLLING 3633 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc)) 3634 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS; 3635 #endif 3636 3637 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3638 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 3639 3640 if (sc->bge_irq == NULL) { 3641 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 3642 error = ENXIO; 3643 goto fail; 3644 } 3645 3646 bge_devinfo(sc); 3647 3648 sc->bge_asf_mode = 0; 3649 /* No ASF if APE present. */ 3650 if ((sc->bge_flags & BGE_FLAG_APE) == 0) { 3651 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3652 BGE_SRAM_DATA_SIG_MAGIC)) { 3653 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3654 BGE_HWCFG_ASF) { 3655 sc->bge_asf_mode |= ASF_ENABLE; 3656 sc->bge_asf_mode |= ASF_STACKUP; 3657 if (BGE_IS_575X_PLUS(sc)) 3658 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3659 } 3660 } 3661 } 3662 3663 bge_stop_fw(sc); 3664 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 3665 if (bge_reset(sc)) { 3666 device_printf(sc->bge_dev, "chip reset failed\n"); 3667 error = ENXIO; 3668 goto fail; 3669 } 3670 3671 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 3672 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 3673 3674 if (bge_chipinit(sc)) { 3675 device_printf(sc->bge_dev, "chip initialization failed\n"); 3676 error = ENXIO; 3677 goto fail; 3678 } 3679 3680 error = bge_get_eaddr(sc, eaddr); 3681 if (error) { 3682 device_printf(sc->bge_dev, 3683 "failed to read station address\n"); 3684 error = ENXIO; 3685 goto fail; 3686 } 3687 3688 /* 5705 limits RX return ring to 512 entries. */ 3689 if (BGE_IS_5717_PLUS(sc)) 3690 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3691 else if (BGE_IS_5705_PLUS(sc)) 3692 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3693 else 3694 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3695 3696 if (bge_dma_alloc(sc)) { 3697 device_printf(sc->bge_dev, 3698 "failed to allocate DMA resources\n"); 3699 error = ENXIO; 3700 goto fail; 3701 } 3702 3703 /* Set default tuneable values. */ 3704 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3705 sc->bge_rx_coal_ticks = 150; 3706 sc->bge_tx_coal_ticks = 150; 3707 sc->bge_rx_max_coal_bds = 10; 3708 sc->bge_tx_max_coal_bds = 10; 3709 3710 /* Initialize checksum features to use. */ 3711 sc->bge_csum_features = BGE_CSUM_FEATURES; 3712 if (sc->bge_forced_udpcsum != 0) 3713 sc->bge_csum_features |= CSUM_UDP; 3714 3715 /* Set up ifnet structure */ 3716 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 3717 if (ifp == NULL) { 3718 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 3719 error = ENXIO; 3720 goto fail; 3721 } 3722 if_setsoftc(ifp, sc); 3723 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 3724 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 3725 if_setioctlfn(ifp, bge_ioctl); 3726 if_setstartfn(ifp, bge_start); 3727 if_setinitfn(ifp, bge_init); 3728 if_setgetcounterfn(ifp, bge_get_counter); 3729 if_setsendqlen(ifp, BGE_TX_RING_CNT - 1); 3730 if_setsendqready(ifp); 3731 if_sethwassist(ifp, sc->bge_csum_features); 3732 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 3733 IFCAP_VLAN_MTU); 3734 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) { 3735 if_sethwassistbits(ifp, CSUM_TSO, 0); 3736 if_setcapabilitiesbit(ifp, IFCAP_TSO4 | IFCAP_VLAN_HWTSO, 0); 3737 } 3738 #ifdef IFCAP_VLAN_HWCSUM 3739 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0); 3740 #endif 3741 if_setcapenable(ifp, if_getcapabilities(ifp)); 3742 #ifdef DEVICE_POLLING 3743 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 3744 #endif 3745 3746 /* 3747 * 5700 B0 chips do not support checksumming correctly due 3748 * to hardware bugs. 3749 */ 3750 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 3751 if_setcapabilitiesbit(ifp, 0, IFCAP_HWCSUM); 3752 if_setcapenablebit(ifp, 0, IFCAP_HWCSUM); 3753 if_sethwassist(ifp, 0); 3754 } 3755 3756 /* 3757 * Figure out what sort of media we have by checking the 3758 * hardware config word in the first 32k of NIC internal memory, 3759 * or fall back to examining the EEPROM if necessary. 3760 * Note: on some BCM5700 cards, this value appears to be unset. 3761 * If that's the case, we have to rely on identifying the NIC 3762 * by its PCI subsystem ID, as we do below for the SysKonnect 3763 * SK-9D41. 3764 */ 3765 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) 3766 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3767 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 3768 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3769 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 3770 sizeof(hwcfg))) { 3771 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 3772 error = ENXIO; 3773 goto fail; 3774 } 3775 hwcfg = ntohl(hwcfg); 3776 } 3777 3778 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3779 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == 3780 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3781 if (BGE_IS_5705_PLUS(sc)) { 3782 sc->bge_flags |= BGE_FLAG_MII_SERDES; 3783 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3784 } else 3785 sc->bge_flags |= BGE_FLAG_TBI; 3786 } 3787 3788 /* Set various PHY bug flags. */ 3789 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3790 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3791 sc->bge_phy_flags |= BGE_PHY_CRC_BUG; 3792 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 3793 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 3794 sc->bge_phy_flags |= BGE_PHY_ADC_BUG; 3795 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3796 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG; 3797 if (pci_get_subvendor(dev) == DELL_VENDORID) 3798 sc->bge_phy_flags |= BGE_PHY_NO_3LED; 3799 if ((BGE_IS_5705_PLUS(sc)) && 3800 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 3801 sc->bge_asicrev != BGE_ASICREV_BCM5785 && 3802 sc->bge_asicrev != BGE_ASICREV_BCM57780 && 3803 !BGE_IS_5717_PLUS(sc)) { 3804 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 3805 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3806 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3807 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 3808 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 && 3809 pci_get_device(dev) != BCOM_DEVICEID_BCM5756) 3810 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG; 3811 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M) 3812 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM; 3813 } else 3814 sc->bge_phy_flags |= BGE_PHY_BER_BUG; 3815 } 3816 3817 /* 3818 * Don't enable Ethernet@WireSpeed for the 5700 or the 3819 * 5705 A0 and A1 chips. 3820 */ 3821 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 3822 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3823 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3824 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3825 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3826 3827 if (sc->bge_flags & BGE_FLAG_TBI) { 3828 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3829 bge_ifmedia_sts); 3830 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 3831 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 3832 0, NULL); 3833 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3834 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3835 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3836 } else { 3837 /* 3838 * Do transceiver setup and tell the firmware the 3839 * driver is down so we can try to get access the 3840 * probe if ASF is running. Retry a couple of times 3841 * if we get a conflict with the ASF firmware accessing 3842 * the PHY. 3843 */ 3844 trys = 0; 3845 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3846 again: 3847 bge_asf_driver_up(sc); 3848 3849 error = mii_attach(dev, &sc->bge_miibus, ifp, 3850 (ifm_change_cb_t)bge_ifmedia_upd, 3851 (ifm_stat_cb_t)bge_ifmedia_sts, capmask, sc->bge_phy_addr, 3852 MII_OFFSET_ANY, MIIF_DOPAUSE); 3853 if (error != 0) { 3854 if (trys++ < 4) { 3855 device_printf(sc->bge_dev, "Try again\n"); 3856 bge_miibus_writereg(sc->bge_dev, 3857 sc->bge_phy_addr, MII_BMCR, BMCR_RESET); 3858 goto again; 3859 } 3860 device_printf(sc->bge_dev, "attaching PHYs failed\n"); 3861 goto fail; 3862 } 3863 3864 /* 3865 * Now tell the firmware we are going up after probing the PHY 3866 */ 3867 if (sc->bge_asf_mode & ASF_STACKUP) 3868 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3869 } 3870 3871 /* 3872 * When using the BCM5701 in PCI-X mode, data corruption has 3873 * been observed in the first few bytes of some received packets. 3874 * Aligning the packet buffer in memory eliminates the corruption. 3875 * Unfortunately, this misaligns the packet payloads. On platforms 3876 * which do not support unaligned accesses, we will realign the 3877 * payloads by copying the received packets. 3878 */ 3879 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 3880 sc->bge_flags & BGE_FLAG_PCIX) 3881 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 3882 3883 /* 3884 * Call MI attach routine. 3885 */ 3886 ether_ifattach(ifp, eaddr); 3887 3888 /* Tell upper layer we support long frames. */ 3889 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 3890 3891 /* 3892 * Hookup IRQ last. 3893 */ 3894 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) { 3895 /* Take advantage of single-shot MSI. */ 3896 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) & 3897 ~BGE_MSIMODE_ONE_SHOT_DISABLE); 3898 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK, 3899 taskqueue_thread_enqueue, &sc->bge_tq); 3900 if (sc->bge_tq == NULL) { 3901 device_printf(dev, "could not create taskqueue.\n"); 3902 ether_ifdetach(ifp); 3903 error = ENOMEM; 3904 goto fail; 3905 } 3906 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, 3907 "%s taskq", device_get_nameunit(sc->bge_dev)); 3908 if (error != 0) { 3909 device_printf(dev, "could not start threads.\n"); 3910 ether_ifdetach(ifp); 3911 goto fail; 3912 } 3913 error = bus_setup_intr(dev, sc->bge_irq, 3914 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, 3915 &sc->bge_intrhand); 3916 } else 3917 error = bus_setup_intr(dev, sc->bge_irq, 3918 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, 3919 &sc->bge_intrhand); 3920 3921 if (error) { 3922 ether_ifdetach(ifp); 3923 device_printf(sc->bge_dev, "couldn't set up irq\n"); 3924 goto fail; 3925 } 3926 3927 /* Attach driver debugnet methods. */ 3928 DEBUGNET_SET(ifp, bge); 3929 3930 fail: 3931 if (error) 3932 bge_detach(dev); 3933 return (error); 3934 } 3935 3936 static int 3937 bge_detach(device_t dev) 3938 { 3939 struct bge_softc *sc; 3940 if_t ifp; 3941 3942 sc = device_get_softc(dev); 3943 ifp = sc->bge_ifp; 3944 3945 #ifdef DEVICE_POLLING 3946 if (if_getcapenable(ifp) & IFCAP_POLLING) 3947 ether_poll_deregister(ifp); 3948 #endif 3949 3950 if (device_is_attached(dev)) { 3951 ether_ifdetach(ifp); 3952 BGE_LOCK(sc); 3953 bge_stop(sc); 3954 BGE_UNLOCK(sc); 3955 callout_drain(&sc->bge_stat_ch); 3956 } 3957 3958 if (sc->bge_tq) 3959 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); 3960 3961 if (sc->bge_flags & BGE_FLAG_TBI) 3962 ifmedia_removeall(&sc->bge_ifmedia); 3963 else if (sc->bge_miibus != NULL) { 3964 bus_generic_detach(dev); 3965 device_delete_child(dev, sc->bge_miibus); 3966 } 3967 3968 bge_release_resources(sc); 3969 3970 return (0); 3971 } 3972 3973 static void 3974 bge_release_resources(struct bge_softc *sc) 3975 { 3976 device_t dev; 3977 3978 dev = sc->bge_dev; 3979 3980 if (sc->bge_tq != NULL) 3981 taskqueue_free(sc->bge_tq); 3982 3983 if (sc->bge_intrhand != NULL) 3984 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 3985 3986 if (sc->bge_irq != NULL) { 3987 bus_release_resource(dev, SYS_RES_IRQ, 3988 rman_get_rid(sc->bge_irq), sc->bge_irq); 3989 pci_release_msi(dev); 3990 } 3991 3992 if (sc->bge_res != NULL) 3993 bus_release_resource(dev, SYS_RES_MEMORY, 3994 rman_get_rid(sc->bge_res), sc->bge_res); 3995 3996 if (sc->bge_res2 != NULL) 3997 bus_release_resource(dev, SYS_RES_MEMORY, 3998 rman_get_rid(sc->bge_res2), sc->bge_res2); 3999 4000 if (sc->bge_ifp != NULL) 4001 if_free(sc->bge_ifp); 4002 4003 bge_dma_free(sc); 4004 4005 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 4006 BGE_LOCK_DESTROY(sc); 4007 } 4008 4009 static int 4010 bge_reset(struct bge_softc *sc) 4011 { 4012 device_t dev; 4013 uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val; 4014 void (*write_op)(struct bge_softc *, int, int); 4015 uint16_t devctl; 4016 int i; 4017 4018 dev = sc->bge_dev; 4019 4020 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4021 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4022 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4023 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4024 4025 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4026 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 4027 if (sc->bge_flags & BGE_FLAG_PCIE) 4028 write_op = bge_writemem_direct; 4029 else 4030 write_op = bge_writemem_ind; 4031 } else 4032 write_op = bge_writereg_ind; 4033 4034 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && 4035 sc->bge_asicrev != BGE_ASICREV_BCM5701) { 4036 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4037 for (i = 0; i < 8000; i++) { 4038 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4039 BGE_NVRAMSWARB_GNT1) 4040 break; 4041 DELAY(20); 4042 } 4043 if (i == 8000) { 4044 if (bootverbose) 4045 device_printf(dev, "NVRAM lock timedout!\n"); 4046 } 4047 } 4048 /* Take APE lock when performing reset. */ 4049 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4050 4051 /* Save some important PCI state. */ 4052 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 4053 command = pci_read_config(dev, BGE_PCI_CMD, 4); 4054 4055 pci_write_config(dev, BGE_PCI_MISC_CTL, 4056 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4057 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 4058 4059 /* Disable fastboot on controllers that support it. */ 4060 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 4061 BGE_IS_5755_PLUS(sc)) { 4062 if (bootverbose) 4063 device_printf(dev, "Disabling fastboot\n"); 4064 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 4065 } 4066 4067 /* 4068 * Write the magic number to SRAM at offset 0xB50. 4069 * When firmware finishes its initialization it will 4070 * write ~BGE_SRAM_FW_MB_MAGIC to the same location. 4071 */ 4072 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4073 4074 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4075 4076 /* XXX: Broadcom Linux driver. */ 4077 if (sc->bge_flags & BGE_FLAG_PCIE) { 4078 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 && 4079 (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) { 4080 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 4081 CSR_WRITE_4(sc, 0x7E2C, 0x20); 4082 } 4083 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4084 /* Prevent PCIE link training during global reset */ 4085 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4086 reset |= 1 << 29; 4087 } 4088 } 4089 4090 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 4091 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 4092 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4093 val | BGE_VCPU_STATUS_DRV_RESET); 4094 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4095 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4096 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4097 } 4098 4099 /* 4100 * Set GPHY Power Down Override to leave GPHY 4101 * powered up in D0 uninitialized. 4102 */ 4103 if (BGE_IS_5705_PLUS(sc) && 4104 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0) 4105 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4106 4107 /* Issue global reset */ 4108 write_op(sc, BGE_MISC_CFG, reset); 4109 4110 if (sc->bge_flags & BGE_FLAG_PCIE) 4111 DELAY(100 * 1000); 4112 else 4113 DELAY(1000); 4114 4115 /* XXX: Broadcom Linux driver. */ 4116 if (sc->bge_flags & BGE_FLAG_PCIE) { 4117 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4118 DELAY(500000); /* wait for link training to complete */ 4119 val = pci_read_config(dev, 0xC4, 4); 4120 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 4121 } 4122 devctl = pci_read_config(dev, 4123 sc->bge_expcap + PCIER_DEVICE_CTL, 2); 4124 /* Clear enable no snoop and disable relaxed ordering. */ 4125 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE | 4126 PCIEM_CTL_NOSNOOP_ENABLE); 4127 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL, 4128 devctl, 2); 4129 pci_set_max_read_req(dev, sc->bge_expmrq); 4130 /* Clear error status. */ 4131 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA, 4132 PCIEM_STA_CORRECTABLE_ERROR | 4133 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 4134 PCIEM_STA_UNSUPPORTED_REQ, 2); 4135 } 4136 4137 /* Reset some of the PCI state that got zapped by reset. */ 4138 pci_write_config(dev, BGE_PCI_MISC_CTL, 4139 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4140 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 4141 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4142 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4143 (sc->bge_flags & BGE_FLAG_PCIX) != 0) 4144 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4145 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4146 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4147 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4148 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4149 pci_write_config(dev, BGE_PCI_PCISTATE, val, 4); 4150 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 4151 pci_write_config(dev, BGE_PCI_CMD, command, 4); 4152 /* 4153 * Disable PCI-X relaxed ordering to ensure status block update 4154 * comes first then packet buffer DMA. Otherwise driver may 4155 * read stale status block. 4156 */ 4157 if (sc->bge_flags & BGE_FLAG_PCIX) { 4158 devctl = pci_read_config(dev, 4159 sc->bge_pcixcap + PCIXR_COMMAND, 2); 4160 devctl &= ~PCIXM_COMMAND_ERO; 4161 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 4162 devctl &= ~PCIXM_COMMAND_MAX_READ; 4163 devctl |= PCIXM_COMMAND_MAX_READ_2048; 4164 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 4165 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 4166 PCIXM_COMMAND_MAX_READ); 4167 devctl |= PCIXM_COMMAND_MAX_READ_2048; 4168 } 4169 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 4170 devctl, 2); 4171 } 4172 /* Re-enable MSI, if necessary, and enable the memory arbiter. */ 4173 if (BGE_IS_5714_FAMILY(sc)) { 4174 /* This chip disables MSI on reset. */ 4175 if (sc->bge_flags & BGE_FLAG_MSI) { 4176 val = pci_read_config(dev, 4177 sc->bge_msicap + PCIR_MSI_CTRL, 2); 4178 pci_write_config(dev, 4179 sc->bge_msicap + PCIR_MSI_CTRL, 4180 val | PCIM_MSICTRL_MSI_ENABLE, 2); 4181 val = CSR_READ_4(sc, BGE_MSI_MODE); 4182 CSR_WRITE_4(sc, BGE_MSI_MODE, 4183 val | BGE_MSIMODE_ENABLE); 4184 } 4185 val = CSR_READ_4(sc, BGE_MARB_MODE); 4186 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4187 } else 4188 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4189 4190 /* Fix up byte swapping. */ 4191 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc)); 4192 4193 val = CSR_READ_4(sc, BGE_MAC_MODE); 4194 val = (val & ~mac_mode_mask) | mac_mode; 4195 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 4196 DELAY(40); 4197 4198 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4199 4200 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 4201 for (i = 0; i < BGE_TIMEOUT; i++) { 4202 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 4203 if (val & BGE_VCPU_STATUS_INIT_DONE) 4204 break; 4205 DELAY(100); 4206 } 4207 if (i == BGE_TIMEOUT) { 4208 device_printf(dev, "reset timed out\n"); 4209 return (1); 4210 } 4211 } else { 4212 /* 4213 * Poll until we see the 1's complement of the magic number. 4214 * This indicates that the firmware initialization is complete. 4215 * We expect this to fail if no chip containing the Ethernet 4216 * address is fitted though. 4217 */ 4218 for (i = 0; i < BGE_TIMEOUT; i++) { 4219 DELAY(10); 4220 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 4221 if (val == ~BGE_SRAM_FW_MB_MAGIC) 4222 break; 4223 } 4224 4225 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 4226 device_printf(dev, 4227 "firmware handshake timed out, found 0x%08x\n", 4228 val); 4229 /* BCM57765 A0 needs additional time before accessing. */ 4230 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 4231 DELAY(10 * 1000); /* XXX */ 4232 } 4233 4234 /* 4235 * The 5704 in TBI mode apparently needs some special 4236 * adjustment to insure the SERDES drive level is set 4237 * to 1.2V. 4238 */ 4239 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 4240 sc->bge_flags & BGE_FLAG_TBI) { 4241 val = CSR_READ_4(sc, BGE_SERDES_CFG); 4242 val = (val & ~0xFFF) | 0x880; 4243 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 4244 } 4245 4246 /* XXX: Broadcom Linux driver. */ 4247 if (sc->bge_flags & BGE_FLAG_PCIE && 4248 !BGE_IS_5717_PLUS(sc) && 4249 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4250 sc->bge_asicrev != BGE_ASICREV_BCM5785) { 4251 /* Enable Data FIFO protection. */ 4252 val = CSR_READ_4(sc, 0x7C00); 4253 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 4254 } 4255 4256 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) 4257 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4258 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4259 4260 return (0); 4261 } 4262 4263 static __inline void 4264 bge_rxreuse_std(struct bge_softc *sc, int i) 4265 { 4266 struct bge_rx_bd *r; 4267 4268 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 4269 r->bge_flags = BGE_RXBDFLAG_END; 4270 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i]; 4271 r->bge_idx = i; 4272 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4273 } 4274 4275 static __inline void 4276 bge_rxreuse_jumbo(struct bge_softc *sc, int i) 4277 { 4278 struct bge_extrx_bd *r; 4279 4280 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 4281 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 4282 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0]; 4283 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1]; 4284 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2]; 4285 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3]; 4286 r->bge_idx = i; 4287 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4288 } 4289 4290 /* 4291 * Frame reception handling. This is called if there's a frame 4292 * on the receive return list. 4293 * 4294 * Note: we have to be able to handle two possibilities here: 4295 * 1) the frame is from the jumbo receive ring 4296 * 2) the frame is from the standard receive ring 4297 */ 4298 4299 static int 4300 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck) 4301 { 4302 if_t ifp; 4303 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0; 4304 uint16_t rx_cons; 4305 4306 rx_cons = sc->bge_rx_saved_considx; 4307 4308 /* Nothing to do. */ 4309 if (rx_cons == rx_prod) 4310 return (rx_npkts); 4311 4312 ifp = sc->bge_ifp; 4313 4314 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 4315 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 4316 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 4317 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 4318 if (BGE_IS_JUMBO_CAPABLE(sc) && 4319 if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN + 4320 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)) 4321 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 4322 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 4323 4324 while (rx_cons != rx_prod) { 4325 struct bge_rx_bd *cur_rx; 4326 uint32_t rxidx; 4327 struct mbuf *m = NULL; 4328 uint16_t vlan_tag = 0; 4329 int have_tag = 0; 4330 4331 #ifdef DEVICE_POLLING 4332 if (if_getcapenable(ifp) & IFCAP_POLLING) { 4333 if (sc->rxcycles <= 0) 4334 break; 4335 sc->rxcycles--; 4336 } 4337 #endif 4338 4339 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons]; 4340 4341 rxidx = cur_rx->bge_idx; 4342 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4343 4344 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 4345 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4346 have_tag = 1; 4347 vlan_tag = cur_rx->bge_vlan_tag; 4348 } 4349 4350 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4351 jumbocnt++; 4352 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4353 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4354 bge_rxreuse_jumbo(sc, rxidx); 4355 continue; 4356 } 4357 if (bge_newbuf_jumbo(sc, rxidx) != 0) { 4358 bge_rxreuse_jumbo(sc, rxidx); 4359 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 4360 continue; 4361 } 4362 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4363 } else { 4364 stdcnt++; 4365 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4366 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4367 bge_rxreuse_std(sc, rxidx); 4368 continue; 4369 } 4370 if (bge_newbuf_std(sc, rxidx) != 0) { 4371 bge_rxreuse_std(sc, rxidx); 4372 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 4373 continue; 4374 } 4375 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4376 } 4377 4378 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 4379 #ifndef __NO_STRICT_ALIGNMENT 4380 /* 4381 * For architectures with strict alignment we must make sure 4382 * the payload is aligned. 4383 */ 4384 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 4385 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 4386 cur_rx->bge_len); 4387 m->m_data += ETHER_ALIGN; 4388 } 4389 #endif 4390 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4391 m->m_pkthdr.rcvif = ifp; 4392 4393 if (if_getcapenable(ifp) & IFCAP_RXCSUM) 4394 bge_rxcsum(sc, cur_rx, m); 4395 4396 /* 4397 * If we received a packet with a vlan tag, 4398 * attach that information to the packet. 4399 */ 4400 if (have_tag) { 4401 m->m_pkthdr.ether_vtag = vlan_tag; 4402 m->m_flags |= M_VLANTAG; 4403 } 4404 4405 if (holdlck != 0) { 4406 BGE_UNLOCK(sc); 4407 if_input(ifp, m); 4408 BGE_LOCK(sc); 4409 } else 4410 if_input(ifp, m); 4411 rx_npkts++; 4412 4413 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4414 return (rx_npkts); 4415 } 4416 4417 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 4418 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD); 4419 if (stdcnt > 0) 4420 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 4421 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 4422 4423 if (jumbocnt > 0) 4424 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 4425 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 4426 4427 sc->bge_rx_saved_considx = rx_cons; 4428 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4429 if (stdcnt) 4430 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std + 4431 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT); 4432 if (jumbocnt) 4433 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo + 4434 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT); 4435 #ifdef notyet 4436 /* 4437 * This register wraps very quickly under heavy packet drops. 4438 * If you need correct statistics, you can enable this check. 4439 */ 4440 if (BGE_IS_5705_PLUS(sc)) 4441 if_incierrors(ifp, CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS)); 4442 #endif 4443 return (rx_npkts); 4444 } 4445 4446 static void 4447 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4448 { 4449 4450 if (BGE_IS_5717_PLUS(sc)) { 4451 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4452 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4453 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4454 if ((cur_rx->bge_error_flag & 4455 BGE_RXERRFLAG_IP_CSUM_NOK) == 0) 4456 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4457 } 4458 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4459 m->m_pkthdr.csum_data = 4460 cur_rx->bge_tcp_udp_csum; 4461 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4462 CSUM_PSEUDO_HDR; 4463 } 4464 } 4465 } else { 4466 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4467 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4468 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 4469 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4470 } 4471 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4472 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 4473 m->m_pkthdr.csum_data = 4474 cur_rx->bge_tcp_udp_csum; 4475 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4476 CSUM_PSEUDO_HDR; 4477 } 4478 } 4479 } 4480 4481 static void 4482 bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 4483 { 4484 struct bge_tx_bd *cur_tx; 4485 if_t ifp; 4486 4487 BGE_LOCK_ASSERT(sc); 4488 4489 /* Nothing to do. */ 4490 if (sc->bge_tx_saved_considx == tx_cons) 4491 return; 4492 4493 ifp = sc->bge_ifp; 4494 4495 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 4496 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE); 4497 /* 4498 * Go through our tx ring and free mbufs for those 4499 * frames that have been sent. 4500 */ 4501 while (sc->bge_tx_saved_considx != tx_cons) { 4502 uint32_t idx; 4503 4504 idx = sc->bge_tx_saved_considx; 4505 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 4506 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4507 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 4508 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 4509 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 4510 sc->bge_cdata.bge_tx_dmamap[idx], 4511 BUS_DMASYNC_POSTWRITE); 4512 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 4513 sc->bge_cdata.bge_tx_dmamap[idx]); 4514 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 4515 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4516 } 4517 sc->bge_txcnt--; 4518 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4519 } 4520 4521 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 4522 if (sc->bge_txcnt == 0) 4523 sc->bge_timer = 0; 4524 } 4525 4526 #ifdef DEVICE_POLLING 4527 static int 4528 bge_poll(if_t ifp, enum poll_cmd cmd, int count) 4529 { 4530 struct bge_softc *sc = if_getsoftc(ifp); 4531 uint16_t rx_prod, tx_cons; 4532 uint32_t statusword; 4533 int rx_npkts = 0; 4534 4535 BGE_LOCK(sc); 4536 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 4537 BGE_UNLOCK(sc); 4538 return (rx_npkts); 4539 } 4540 4541 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4542 sc->bge_cdata.bge_status_map, 4543 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4544 /* Fetch updates from the status block. */ 4545 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4546 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4547 4548 statusword = sc->bge_ldata.bge_status_block->bge_status; 4549 /* Clear the status so the next pass only sees the changes. */ 4550 sc->bge_ldata.bge_status_block->bge_status = 0; 4551 4552 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4553 sc->bge_cdata.bge_status_map, 4554 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4555 4556 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 4557 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 4558 sc->bge_link_evt++; 4559 4560 if (cmd == POLL_AND_CHECK_STATUS) 4561 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4562 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4563 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 4564 bge_link_upd(sc); 4565 4566 sc->rxcycles = count; 4567 rx_npkts = bge_rxeof(sc, rx_prod, 1); 4568 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 4569 BGE_UNLOCK(sc); 4570 return (rx_npkts); 4571 } 4572 bge_txeof(sc, tx_cons); 4573 if (!if_sendq_empty(ifp)) 4574 bge_start_locked(ifp); 4575 4576 BGE_UNLOCK(sc); 4577 return (rx_npkts); 4578 } 4579 #endif /* DEVICE_POLLING */ 4580 4581 static int 4582 bge_msi_intr(void *arg) 4583 { 4584 struct bge_softc *sc; 4585 4586 sc = (struct bge_softc *)arg; 4587 /* 4588 * This interrupt is not shared and controller already 4589 * disabled further interrupt. 4590 */ 4591 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task); 4592 return (FILTER_HANDLED); 4593 } 4594 4595 static void 4596 bge_intr_task(void *arg, int pending) 4597 { 4598 struct bge_softc *sc; 4599 if_t ifp; 4600 uint32_t status, status_tag; 4601 uint16_t rx_prod, tx_cons; 4602 4603 sc = (struct bge_softc *)arg; 4604 ifp = sc->bge_ifp; 4605 4606 BGE_LOCK(sc); 4607 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 4608 BGE_UNLOCK(sc); 4609 return; 4610 } 4611 4612 /* Get updated status block. */ 4613 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4614 sc->bge_cdata.bge_status_map, 4615 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4616 4617 /* Save producer/consumer indices. */ 4618 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4619 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4620 status = sc->bge_ldata.bge_status_block->bge_status; 4621 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24; 4622 /* Dirty the status flag. */ 4623 sc->bge_ldata.bge_status_block->bge_status = 0; 4624 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4625 sc->bge_cdata.bge_status_map, 4626 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4627 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0) 4628 status_tag = 0; 4629 4630 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) 4631 bge_link_upd(sc); 4632 4633 /* Let controller work. */ 4634 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag); 4635 4636 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 4637 sc->bge_rx_saved_considx != rx_prod) { 4638 /* Check RX return ring producer/consumer. */ 4639 BGE_UNLOCK(sc); 4640 bge_rxeof(sc, rx_prod, 0); 4641 BGE_LOCK(sc); 4642 } 4643 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4644 /* Check TX ring producer/consumer. */ 4645 bge_txeof(sc, tx_cons); 4646 if (!if_sendq_empty(ifp)) 4647 bge_start_locked(ifp); 4648 } 4649 BGE_UNLOCK(sc); 4650 } 4651 4652 static void 4653 bge_intr(void *xsc) 4654 { 4655 struct bge_softc *sc; 4656 if_t ifp; 4657 uint32_t statusword; 4658 uint16_t rx_prod, tx_cons; 4659 4660 sc = xsc; 4661 4662 BGE_LOCK(sc); 4663 4664 ifp = sc->bge_ifp; 4665 4666 #ifdef DEVICE_POLLING 4667 if (if_getcapenable(ifp) & IFCAP_POLLING) { 4668 BGE_UNLOCK(sc); 4669 return; 4670 } 4671 #endif 4672 4673 /* 4674 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 4675 * disable interrupts by writing nonzero like we used to, since with 4676 * our current organization this just gives complications and 4677 * pessimizations for re-enabling interrupts. We used to have races 4678 * instead of the necessary complications. Disabling interrupts 4679 * would just reduce the chance of a status update while we are 4680 * running (by switching to the interrupt-mode coalescence 4681 * parameters), but this chance is already very low so it is more 4682 * efficient to get another interrupt than prevent it. 4683 * 4684 * We do the ack first to ensure another interrupt if there is a 4685 * status update after the ack. We don't check for the status 4686 * changing later because it is more efficient to get another 4687 * interrupt than prevent it, not quite as above (not checking is 4688 * a smaller optimization than not toggling the interrupt enable, 4689 * since checking doesn't involve PCI accesses and toggling require 4690 * the status check). So toggling would probably be a pessimization 4691 * even with MSI. It would only be needed for using a task queue. 4692 */ 4693 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4694 4695 /* 4696 * Do the mandatory PCI flush as well as get the link status. 4697 */ 4698 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 4699 4700 /* Make sure the descriptor ring indexes are coherent. */ 4701 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4702 sc->bge_cdata.bge_status_map, 4703 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4704 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4705 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4706 sc->bge_ldata.bge_status_block->bge_status = 0; 4707 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4708 sc->bge_cdata.bge_status_map, 4709 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4710 4711 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4712 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4713 statusword || sc->bge_link_evt) 4714 bge_link_upd(sc); 4715 4716 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4717 /* Check RX return ring producer/consumer. */ 4718 bge_rxeof(sc, rx_prod, 1); 4719 } 4720 4721 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4722 /* Check TX ring producer/consumer. */ 4723 bge_txeof(sc, tx_cons); 4724 } 4725 4726 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 4727 !if_sendq_empty(ifp)) 4728 bge_start_locked(ifp); 4729 4730 BGE_UNLOCK(sc); 4731 } 4732 4733 static void 4734 bge_asf_driver_up(struct bge_softc *sc) 4735 { 4736 if (sc->bge_asf_mode & ASF_STACKUP) { 4737 /* Send ASF heartbeat aprox. every 2s */ 4738 if (sc->bge_asf_count) 4739 sc->bge_asf_count --; 4740 else { 4741 sc->bge_asf_count = 2; 4742 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4743 BGE_FW_CMD_DRV_ALIVE); 4744 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4745 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4746 BGE_FW_HB_TIMEOUT_SEC); 4747 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 4748 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4749 BGE_RX_CPU_DRV_EVENT); 4750 } 4751 } 4752 } 4753 4754 static void 4755 bge_tick(void *xsc) 4756 { 4757 struct bge_softc *sc = xsc; 4758 struct mii_data *mii = NULL; 4759 4760 BGE_LOCK_ASSERT(sc); 4761 4762 /* Synchronize with possible callout reset/stop. */ 4763 if (callout_pending(&sc->bge_stat_ch) || 4764 !callout_active(&sc->bge_stat_ch)) 4765 return; 4766 4767 if (BGE_IS_5705_PLUS(sc)) 4768 bge_stats_update_regs(sc); 4769 else 4770 bge_stats_update(sc); 4771 4772 /* XXX Add APE heartbeat check here? */ 4773 4774 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 4775 mii = device_get_softc(sc->bge_miibus); 4776 /* 4777 * Do not touch PHY if we have link up. This could break 4778 * IPMI/ASF mode or produce extra input errors 4779 * (extra errors was reported for bcm5701 & bcm5704). 4780 */ 4781 if (!sc->bge_link) 4782 mii_tick(mii); 4783 } else { 4784 /* 4785 * Since in TBI mode auto-polling can't be used we should poll 4786 * link status manually. Here we register pending link event 4787 * and trigger interrupt. 4788 */ 4789 #ifdef DEVICE_POLLING 4790 /* In polling mode we poll link state in bge_poll(). */ 4791 if (!(if_getcapenable(sc->bge_ifp) & IFCAP_POLLING)) 4792 #endif 4793 { 4794 sc->bge_link_evt++; 4795 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 4796 sc->bge_flags & BGE_FLAG_5788) 4797 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4798 else 4799 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4800 } 4801 } 4802 4803 bge_asf_driver_up(sc); 4804 bge_watchdog(sc); 4805 4806 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 4807 } 4808 4809 static void 4810 bge_stats_update_regs(struct bge_softc *sc) 4811 { 4812 struct bge_mac_stats *stats; 4813 uint32_t val; 4814 4815 stats = &sc->bge_mac_stats; 4816 4817 stats->ifHCOutOctets += 4818 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4819 stats->etherStatsCollisions += 4820 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4821 stats->outXonSent += 4822 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4823 stats->outXoffSent += 4824 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4825 stats->dot3StatsInternalMacTransmitErrors += 4826 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4827 stats->dot3StatsSingleCollisionFrames += 4828 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4829 stats->dot3StatsMultipleCollisionFrames += 4830 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4831 stats->dot3StatsDeferredTransmissions += 4832 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4833 stats->dot3StatsExcessiveCollisions += 4834 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4835 stats->dot3StatsLateCollisions += 4836 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4837 stats->ifHCOutUcastPkts += 4838 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4839 stats->ifHCOutMulticastPkts += 4840 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4841 stats->ifHCOutBroadcastPkts += 4842 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4843 4844 stats->ifHCInOctets += 4845 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4846 stats->etherStatsFragments += 4847 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4848 stats->ifHCInUcastPkts += 4849 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4850 stats->ifHCInMulticastPkts += 4851 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4852 stats->ifHCInBroadcastPkts += 4853 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4854 stats->dot3StatsFCSErrors += 4855 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4856 stats->dot3StatsAlignmentErrors += 4857 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4858 stats->xonPauseFramesReceived += 4859 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4860 stats->xoffPauseFramesReceived += 4861 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4862 stats->macControlFramesReceived += 4863 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4864 stats->xoffStateEntered += 4865 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4866 stats->dot3StatsFramesTooLong += 4867 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4868 stats->etherStatsJabbers += 4869 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4870 stats->etherStatsUndersizePkts += 4871 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4872 4873 stats->FramesDroppedDueToFilters += 4874 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4875 stats->DmaWriteQueueFull += 4876 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4877 stats->DmaWriteHighPriQueueFull += 4878 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4879 stats->NoMoreRxBDs += 4880 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4881 /* 4882 * XXX 4883 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS 4884 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0 4885 * includes number of unwanted multicast frames. This comes 4886 * from silicon bug and known workaround to get rough(not 4887 * exact) counter is to enable interrupt on MBUF low water 4888 * attention. This can be accomplished by setting 4889 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE, 4890 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and 4891 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL. 4892 * However that change would generate more interrupts and 4893 * there are still possibilities of losing multiple frames 4894 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling. 4895 * Given that the workaround still would not get correct 4896 * counter I don't think it's worth to implement it. So 4897 * ignore reading the counter on controllers that have the 4898 * silicon bug. 4899 */ 4900 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 && 4901 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4902 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) 4903 stats->InputDiscards += 4904 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4905 stats->InputErrors += 4906 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4907 stats->RecvThresholdHit += 4908 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4909 4910 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) { 4911 /* 4912 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS 4913 * frames, it's safe to disable workaround for DMA engine's 4914 * miscalculation of TXMBUF space. 4915 */ 4916 if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts + 4917 stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) { 4918 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 4919 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 4920 val &= ~BGE_RDMA_TX_LENGTH_WA_5719; 4921 else 4922 val &= ~BGE_RDMA_TX_LENGTH_WA_5720; 4923 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 4924 sc->bge_flags &= ~BGE_FLAG_RDMA_BUG; 4925 } 4926 } 4927 } 4928 4929 static void 4930 bge_stats_clear_regs(struct bge_softc *sc) 4931 { 4932 4933 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4934 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4935 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4936 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4937 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4938 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4939 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4940 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4941 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4942 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4943 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4944 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4945 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4946 4947 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4948 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4949 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4950 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4951 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4952 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4953 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4954 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4955 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4956 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4957 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4958 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4959 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4960 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4961 4962 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4963 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4964 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4965 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4966 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4967 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4968 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4969 } 4970 4971 static void 4972 bge_stats_update(struct bge_softc *sc) 4973 { 4974 if_t ifp; 4975 bus_size_t stats; 4976 uint32_t cnt; /* current register value */ 4977 4978 ifp = sc->bge_ifp; 4979 4980 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4981 4982 #define READ_STAT(sc, stats, stat) \ 4983 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4984 4985 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 4986 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, cnt - sc->bge_tx_collisions); 4987 sc->bge_tx_collisions = cnt; 4988 4989 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo); 4990 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_nobds); 4991 sc->bge_rx_nobds = cnt; 4992 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo); 4993 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_inerrs); 4994 sc->bge_rx_inerrs = cnt; 4995 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 4996 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_discards); 4997 sc->bge_rx_discards = cnt; 4998 4999 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 5000 if_inc_counter(ifp, IFCOUNTER_OERRORS, cnt - sc->bge_tx_discards); 5001 sc->bge_tx_discards = cnt; 5002 5003 #undef READ_STAT 5004 } 5005 5006 /* 5007 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 5008 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 5009 * but when such padded frames employ the bge IP/TCP checksum offload, 5010 * the hardware checksum assist gives incorrect results (possibly 5011 * from incorporating its own padding into the UDP/TCP checksum; who knows). 5012 * If we pad such runts with zeros, the onboard checksum comes out correct. 5013 */ 5014 static __inline int 5015 bge_cksum_pad(struct mbuf *m) 5016 { 5017 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 5018 struct mbuf *last; 5019 5020 /* If there's only the packet-header and we can pad there, use it. */ 5021 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 5022 M_TRAILINGSPACE(m) >= padlen) { 5023 last = m; 5024 } else { 5025 /* 5026 * Walk packet chain to find last mbuf. We will either 5027 * pad there, or append a new mbuf and pad it. 5028 */ 5029 for (last = m; last->m_next != NULL; last = last->m_next); 5030 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 5031 /* Allocate new empty mbuf, pad it. Compact later. */ 5032 struct mbuf *n; 5033 5034 MGET(n, M_NOWAIT, MT_DATA); 5035 if (n == NULL) 5036 return (ENOBUFS); 5037 n->m_len = 0; 5038 last->m_next = n; 5039 last = n; 5040 } 5041 } 5042 5043 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 5044 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 5045 last->m_len += padlen; 5046 m->m_pkthdr.len += padlen; 5047 5048 return (0); 5049 } 5050 5051 static struct mbuf * 5052 bge_check_short_dma(struct mbuf *m) 5053 { 5054 struct mbuf *n; 5055 int found; 5056 5057 /* 5058 * If device receive two back-to-back send BDs with less than 5059 * or equal to 8 total bytes then the device may hang. The two 5060 * back-to-back send BDs must in the same frame for this failure 5061 * to occur. Scan mbuf chains and see whether two back-to-back 5062 * send BDs are there. If this is the case, allocate new mbuf 5063 * and copy the frame to workaround the silicon bug. 5064 */ 5065 for (n = m, found = 0; n != NULL; n = n->m_next) { 5066 if (n->m_len < 8) { 5067 found++; 5068 if (found > 1) 5069 break; 5070 continue; 5071 } 5072 found = 0; 5073 } 5074 5075 if (found > 1) { 5076 n = m_defrag(m, M_NOWAIT); 5077 if (n == NULL) 5078 m_freem(m); 5079 } else 5080 n = m; 5081 return (n); 5082 } 5083 5084 static struct mbuf * 5085 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss, 5086 uint16_t *flags) 5087 { 5088 struct ip *ip; 5089 struct tcphdr *tcp; 5090 struct mbuf *n; 5091 uint16_t hlen; 5092 uint32_t poff; 5093 5094 if (M_WRITABLE(m) == 0) { 5095 /* Get a writable copy. */ 5096 n = m_dup(m, M_NOWAIT); 5097 m_freem(m); 5098 if (n == NULL) 5099 return (NULL); 5100 m = n; 5101 } 5102 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip)); 5103 if (m == NULL) 5104 return (NULL); 5105 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 5106 poff = sizeof(struct ether_header) + (ip->ip_hl << 2); 5107 m = m_pullup(m, poff + sizeof(struct tcphdr)); 5108 if (m == NULL) 5109 return (NULL); 5110 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 5111 m = m_pullup(m, poff + (tcp->th_off << 2)); 5112 if (m == NULL) 5113 return (NULL); 5114 /* 5115 * It seems controller doesn't modify IP length and TCP pseudo 5116 * checksum. These checksum computed by upper stack should be 0. 5117 */ 5118 *mss = m->m_pkthdr.tso_segsz; 5119 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 5120 ip->ip_sum = 0; 5121 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2)); 5122 /* Clear pseudo checksum computed by TCP stack. */ 5123 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 5124 tcp->th_sum = 0; 5125 /* 5126 * Broadcom controllers uses different descriptor format for 5127 * TSO depending on ASIC revision. Due to TSO-capable firmware 5128 * license issue and lower performance of firmware based TSO 5129 * we only support hardware based TSO. 5130 */ 5131 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */ 5132 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2; 5133 if (sc->bge_flags & BGE_FLAG_TSO3) { 5134 /* 5135 * For BCM5717 and newer controllers, hardware based TSO 5136 * uses the 14 lower bits of the bge_mss field to store the 5137 * MSS and the upper 2 bits to store the lowest 2 bits of 5138 * the IP/TCP header length. The upper 6 bits of the header 5139 * length are stored in the bge_flags[14:10,4] field. Jumbo 5140 * frames are supported. 5141 */ 5142 *mss |= ((hlen & 0x3) << 14); 5143 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2); 5144 } else { 5145 /* 5146 * For BCM5755 and newer controllers, hardware based TSO uses 5147 * the lower 11 bits to store the MSS and the upper 5 bits to 5148 * store the IP/TCP header length. Jumbo frames are not 5149 * supported. 5150 */ 5151 *mss |= (hlen << 11); 5152 } 5153 return (m); 5154 } 5155 5156 /* 5157 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5158 * pointers to descriptors. 5159 */ 5160 static int 5161 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 5162 { 5163 bus_dma_segment_t segs[BGE_NSEG_NEW]; 5164 bus_dmamap_t map; 5165 struct bge_tx_bd *d; 5166 struct mbuf *m = *m_head; 5167 uint32_t idx = *txidx; 5168 uint16_t csum_flags, mss, vlan_tag; 5169 int nsegs, i, error; 5170 5171 csum_flags = 0; 5172 mss = 0; 5173 vlan_tag = 0; 5174 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 && 5175 m->m_next != NULL) { 5176 *m_head = bge_check_short_dma(m); 5177 if (*m_head == NULL) 5178 return (ENOBUFS); 5179 m = *m_head; 5180 } 5181 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 5182 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags); 5183 if (*m_head == NULL) 5184 return (ENOBUFS); 5185 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA | 5186 BGE_TXBDFLAG_CPU_POST_DMA; 5187 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) { 5188 if (m->m_pkthdr.csum_flags & CSUM_IP) 5189 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5190 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 5191 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5192 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 5193 (error = bge_cksum_pad(m)) != 0) { 5194 m_freem(m); 5195 *m_head = NULL; 5196 return (error); 5197 } 5198 } 5199 } 5200 5201 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) { 5202 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME && 5203 m->m_pkthdr.len > ETHER_MAX_LEN) 5204 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME; 5205 if (sc->bge_forced_collapse > 0 && 5206 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) { 5207 /* 5208 * Forcedly collapse mbuf chains to overcome hardware 5209 * limitation which only support a single outstanding 5210 * DMA read operation. 5211 */ 5212 if (sc->bge_forced_collapse == 1) 5213 m = m_defrag(m, M_NOWAIT); 5214 else 5215 m = m_collapse(m, M_NOWAIT, 5216 sc->bge_forced_collapse); 5217 if (m == NULL) 5218 m = *m_head; 5219 *m_head = m; 5220 } 5221 } 5222 5223 map = sc->bge_cdata.bge_tx_dmamap[idx]; 5224 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, 5225 &nsegs, BUS_DMA_NOWAIT); 5226 if (error == EFBIG) { 5227 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW); 5228 if (m == NULL) { 5229 m_freem(*m_head); 5230 *m_head = NULL; 5231 return (ENOBUFS); 5232 } 5233 *m_head = m; 5234 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, 5235 m, segs, &nsegs, BUS_DMA_NOWAIT); 5236 if (error) { 5237 m_freem(m); 5238 *m_head = NULL; 5239 return (error); 5240 } 5241 } else if (error != 0) 5242 return (error); 5243 5244 /* Check if we have enough free send BDs. */ 5245 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) { 5246 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 5247 return (ENOBUFS); 5248 } 5249 5250 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 5251 5252 if (m->m_flags & M_VLANTAG) { 5253 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 5254 vlan_tag = m->m_pkthdr.ether_vtag; 5255 } 5256 5257 if (sc->bge_asicrev == BGE_ASICREV_BCM5762 && 5258 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 5259 /* 5260 * 5725 family of devices corrupts TSO packets when TSO DMA 5261 * buffers cross into regions which are within MSS bytes of 5262 * a 4GB boundary. If we encounter the condition, drop the 5263 * packet. 5264 */ 5265 for (i = 0; ; i++) { 5266 d = &sc->bge_ldata.bge_tx_ring[idx]; 5267 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 5268 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 5269 d->bge_len = segs[i].ds_len; 5270 if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss < 5271 d->bge_addr.bge_addr_lo) 5272 break; 5273 d->bge_flags = csum_flags; 5274 d->bge_vlan_tag = vlan_tag; 5275 d->bge_mss = mss; 5276 if (i == nsegs - 1) 5277 break; 5278 BGE_INC(idx, BGE_TX_RING_CNT); 5279 } 5280 if (i != nsegs - 1) { 5281 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, 5282 BUS_DMASYNC_POSTWRITE); 5283 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 5284 m_freem(*m_head); 5285 *m_head = NULL; 5286 return (EIO); 5287 } 5288 } else { 5289 for (i = 0; ; i++) { 5290 d = &sc->bge_ldata.bge_tx_ring[idx]; 5291 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 5292 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 5293 d->bge_len = segs[i].ds_len; 5294 d->bge_flags = csum_flags; 5295 d->bge_vlan_tag = vlan_tag; 5296 d->bge_mss = mss; 5297 if (i == nsegs - 1) 5298 break; 5299 BGE_INC(idx, BGE_TX_RING_CNT); 5300 } 5301 } 5302 5303 /* Mark the last segment as end of packet... */ 5304 d->bge_flags |= BGE_TXBDFLAG_END; 5305 5306 /* 5307 * Insure that the map for this transmission 5308 * is placed at the array index of the last descriptor 5309 * in this chain. 5310 */ 5311 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 5312 sc->bge_cdata.bge_tx_dmamap[idx] = map; 5313 sc->bge_cdata.bge_tx_chain[idx] = m; 5314 sc->bge_txcnt += nsegs; 5315 5316 BGE_INC(idx, BGE_TX_RING_CNT); 5317 *txidx = idx; 5318 5319 return (0); 5320 } 5321 5322 /* 5323 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5324 * to the mbuf data regions directly in the transmit descriptors. 5325 */ 5326 static void 5327 bge_start_locked(if_t ifp) 5328 { 5329 struct bge_softc *sc; 5330 struct mbuf *m_head; 5331 uint32_t prodidx; 5332 int count; 5333 5334 sc = if_getsoftc(ifp); 5335 BGE_LOCK_ASSERT(sc); 5336 5337 if (!sc->bge_link || 5338 (if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 5339 IFF_DRV_RUNNING) 5340 return; 5341 5342 prodidx = sc->bge_tx_prodidx; 5343 5344 for (count = 0; !if_sendq_empty(ifp);) { 5345 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { 5346 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 5347 break; 5348 } 5349 m_head = if_dequeue(ifp); 5350 if (m_head == NULL) 5351 break; 5352 5353 /* 5354 * Pack the data into the transmit ring. If we 5355 * don't have room, set the OACTIVE flag and wait 5356 * for the NIC to drain the ring. 5357 */ 5358 if (bge_encap(sc, &m_head, &prodidx)) { 5359 if (m_head == NULL) 5360 break; 5361 if_sendq_prepend(ifp, m_head); 5362 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 5363 break; 5364 } 5365 ++count; 5366 5367 /* 5368 * If there's a BPF listener, bounce a copy of this frame 5369 * to him. 5370 */ 5371 if_bpfmtap(ifp, m_head); 5372 } 5373 5374 if (count > 0) 5375 bge_start_tx(sc, prodidx); 5376 } 5377 5378 static void 5379 bge_start_tx(struct bge_softc *sc, uint32_t prodidx) 5380 { 5381 5382 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 5383 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 5384 /* Transmit. */ 5385 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5386 /* 5700 b2 errata */ 5387 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 5388 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5389 5390 sc->bge_tx_prodidx = prodidx; 5391 5392 /* Set a timeout in case the chip goes out to lunch. */ 5393 sc->bge_timer = BGE_TX_TIMEOUT; 5394 } 5395 5396 /* 5397 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5398 * to the mbuf data regions directly in the transmit descriptors. 5399 */ 5400 static void 5401 bge_start(if_t ifp) 5402 { 5403 struct bge_softc *sc; 5404 5405 sc = if_getsoftc(ifp); 5406 BGE_LOCK(sc); 5407 bge_start_locked(ifp); 5408 BGE_UNLOCK(sc); 5409 } 5410 5411 static void 5412 bge_init_locked(struct bge_softc *sc) 5413 { 5414 if_t ifp; 5415 uint16_t *m; 5416 uint32_t mode; 5417 5418 BGE_LOCK_ASSERT(sc); 5419 5420 ifp = sc->bge_ifp; 5421 5422 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 5423 return; 5424 5425 /* Cancel pending I/O and flush buffers. */ 5426 bge_stop(sc); 5427 5428 bge_stop_fw(sc); 5429 bge_sig_pre_reset(sc, BGE_RESET_START); 5430 bge_reset(sc); 5431 bge_sig_legacy(sc, BGE_RESET_START); 5432 bge_sig_post_reset(sc, BGE_RESET_START); 5433 5434 bge_chipinit(sc); 5435 5436 /* 5437 * Init the various state machines, ring 5438 * control blocks and firmware. 5439 */ 5440 if (bge_blockinit(sc)) { 5441 device_printf(sc->bge_dev, "initialization failure\n"); 5442 return; 5443 } 5444 5445 ifp = sc->bge_ifp; 5446 5447 /* Specify MTU. */ 5448 CSR_WRITE_4(sc, BGE_RX_MTU, if_getmtu(ifp) + 5449 ETHER_HDR_LEN + ETHER_CRC_LEN + 5450 (if_getcapenable(ifp) & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 5451 5452 /* Load our MAC address. */ 5453 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 5454 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5455 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5456 5457 /* Program promiscuous mode. */ 5458 bge_setpromisc(sc); 5459 5460 /* Program multicast filter. */ 5461 bge_setmulti(sc); 5462 5463 /* Program VLAN tag stripping. */ 5464 bge_setvlan(sc); 5465 5466 /* Override UDP checksum offloading. */ 5467 if (sc->bge_forced_udpcsum == 0) 5468 sc->bge_csum_features &= ~CSUM_UDP; 5469 else 5470 sc->bge_csum_features |= CSUM_UDP; 5471 if (if_getcapabilities(ifp) & IFCAP_TXCSUM && 5472 if_getcapenable(ifp) & IFCAP_TXCSUM) { 5473 if_sethwassistbits(ifp, 0, (BGE_CSUM_FEATURES | CSUM_UDP)); 5474 if_sethwassistbits(ifp, sc->bge_csum_features, 0); 5475 } 5476 5477 /* Init RX ring. */ 5478 if (bge_init_rx_ring_std(sc) != 0) { 5479 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 5480 bge_stop(sc); 5481 return; 5482 } 5483 5484 /* 5485 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5486 * memory to insure that the chip has in fact read the first 5487 * entry of the ring. 5488 */ 5489 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5490 uint32_t v, i; 5491 for (i = 0; i < 10; i++) { 5492 DELAY(20); 5493 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5494 if (v == (MCLBYTES - ETHER_ALIGN)) 5495 break; 5496 } 5497 if (i == 10) 5498 device_printf (sc->bge_dev, 5499 "5705 A0 chip failed to load RX ring\n"); 5500 } 5501 5502 /* Init jumbo RX ring. */ 5503 if (BGE_IS_JUMBO_CAPABLE(sc) && 5504 if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN + 5505 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)) { 5506 if (bge_init_rx_ring_jumbo(sc) != 0) { 5507 device_printf(sc->bge_dev, 5508 "no memory for jumbo Rx buffers.\n"); 5509 bge_stop(sc); 5510 return; 5511 } 5512 } 5513 5514 /* Init our RX return ring index. */ 5515 sc->bge_rx_saved_considx = 0; 5516 5517 /* Init our RX/TX stat counters. */ 5518 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 5519 5520 /* Init TX ring. */ 5521 bge_init_tx_ring(sc); 5522 5523 /* Enable TX MAC state machine lockup fix. */ 5524 mode = CSR_READ_4(sc, BGE_TX_MODE); 5525 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 5526 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5527 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 5528 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 5529 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5530 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5531 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5532 } 5533 /* Turn on transmitter. */ 5534 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5535 DELAY(100); 5536 5537 /* Turn on receiver. */ 5538 mode = CSR_READ_4(sc, BGE_RX_MODE); 5539 if (BGE_IS_5755_PLUS(sc)) 5540 mode |= BGE_RXMODE_IPV6_ENABLE; 5541 if (sc->bge_asicrev == BGE_ASICREV_BCM5762) 5542 mode |= BGE_RXMODE_IPV4_FRAG_FIX; 5543 CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5544 DELAY(10); 5545 5546 /* 5547 * Set the number of good frames to receive after RX MBUF 5548 * Low Watermark has been reached. After the RX MAC receives 5549 * this number of frames, it will drop subsequent incoming 5550 * frames until the MBUF High Watermark is reached. 5551 */ 5552 if (BGE_IS_57765_PLUS(sc)) 5553 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1); 5554 else 5555 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5556 5557 /* Clear MAC statistics. */ 5558 if (BGE_IS_5705_PLUS(sc)) 5559 bge_stats_clear_regs(sc); 5560 5561 /* Tell firmware we're alive. */ 5562 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5563 5564 #ifdef DEVICE_POLLING 5565 /* Disable interrupts if we are polling. */ 5566 if (if_getcapenable(ifp) & IFCAP_POLLING) { 5567 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5568 BGE_PCIMISCCTL_MASK_PCI_INTR); 5569 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5570 } else 5571 #endif 5572 5573 /* Enable host interrupts. */ 5574 { 5575 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5576 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5577 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5578 } 5579 5580 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 5581 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 5582 5583 bge_ifmedia_upd_locked(ifp); 5584 5585 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 5586 } 5587 5588 static void 5589 bge_init(void *xsc) 5590 { 5591 struct bge_softc *sc = xsc; 5592 5593 BGE_LOCK(sc); 5594 bge_init_locked(sc); 5595 BGE_UNLOCK(sc); 5596 } 5597 5598 /* 5599 * Set media options. 5600 */ 5601 static int 5602 bge_ifmedia_upd(if_t ifp) 5603 { 5604 struct bge_softc *sc = if_getsoftc(ifp); 5605 int res; 5606 5607 BGE_LOCK(sc); 5608 res = bge_ifmedia_upd_locked(ifp); 5609 BGE_UNLOCK(sc); 5610 5611 return (res); 5612 } 5613 5614 static int 5615 bge_ifmedia_upd_locked(if_t ifp) 5616 { 5617 struct bge_softc *sc = if_getsoftc(ifp); 5618 struct mii_data *mii; 5619 struct mii_softc *miisc; 5620 struct ifmedia *ifm; 5621 5622 BGE_LOCK_ASSERT(sc); 5623 5624 ifm = &sc->bge_ifmedia; 5625 5626 /* If this is a 1000baseX NIC, enable the TBI port. */ 5627 if (sc->bge_flags & BGE_FLAG_TBI) { 5628 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5629 return (EINVAL); 5630 switch(IFM_SUBTYPE(ifm->ifm_media)) { 5631 case IFM_AUTO: 5632 /* 5633 * The BCM5704 ASIC appears to have a special 5634 * mechanism for programming the autoneg 5635 * advertisement registers in TBI mode. 5636 */ 5637 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 5638 uint32_t sgdig; 5639 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5640 if (sgdig & BGE_SGDIGSTS_DONE) { 5641 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5642 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5643 sgdig |= BGE_SGDIGCFG_AUTO | 5644 BGE_SGDIGCFG_PAUSE_CAP | 5645 BGE_SGDIGCFG_ASYM_PAUSE; 5646 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 5647 sgdig | BGE_SGDIGCFG_SEND); 5648 DELAY(5); 5649 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 5650 } 5651 } 5652 break; 5653 case IFM_1000_SX: 5654 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5655 BGE_CLRBIT(sc, BGE_MAC_MODE, 5656 BGE_MACMODE_HALF_DUPLEX); 5657 } else { 5658 BGE_SETBIT(sc, BGE_MAC_MODE, 5659 BGE_MACMODE_HALF_DUPLEX); 5660 } 5661 DELAY(40); 5662 break; 5663 default: 5664 return (EINVAL); 5665 } 5666 return (0); 5667 } 5668 5669 sc->bge_link_evt++; 5670 mii = device_get_softc(sc->bge_miibus); 5671 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 5672 PHY_RESET(miisc); 5673 mii_mediachg(mii); 5674 5675 /* 5676 * Force an interrupt so that we will call bge_link_upd 5677 * if needed and clear any pending link state attention. 5678 * Without this we are not getting any further interrupts 5679 * for link state changes and thus will not UP the link and 5680 * not be able to send in bge_start_locked. The only 5681 * way to get things working was to receive a packet and 5682 * get an RX intr. 5683 * bge_tick should help for fiber cards and we might not 5684 * need to do this here if BGE_FLAG_TBI is set but as 5685 * we poll for fiber anyway it should not harm. 5686 */ 5687 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 5688 sc->bge_flags & BGE_FLAG_5788) 5689 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5690 else 5691 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5692 5693 return (0); 5694 } 5695 5696 /* 5697 * Report current media status. 5698 */ 5699 static void 5700 bge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 5701 { 5702 struct bge_softc *sc = if_getsoftc(ifp); 5703 struct mii_data *mii; 5704 5705 BGE_LOCK(sc); 5706 5707 if ((if_getflags(ifp) & IFF_UP) == 0) { 5708 BGE_UNLOCK(sc); 5709 return; 5710 } 5711 if (sc->bge_flags & BGE_FLAG_TBI) { 5712 ifmr->ifm_status = IFM_AVALID; 5713 ifmr->ifm_active = IFM_ETHER; 5714 if (CSR_READ_4(sc, BGE_MAC_STS) & 5715 BGE_MACSTAT_TBI_PCS_SYNCHED) 5716 ifmr->ifm_status |= IFM_ACTIVE; 5717 else { 5718 ifmr->ifm_active |= IFM_NONE; 5719 BGE_UNLOCK(sc); 5720 return; 5721 } 5722 ifmr->ifm_active |= IFM_1000_SX; 5723 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5724 ifmr->ifm_active |= IFM_HDX; 5725 else 5726 ifmr->ifm_active |= IFM_FDX; 5727 BGE_UNLOCK(sc); 5728 return; 5729 } 5730 5731 mii = device_get_softc(sc->bge_miibus); 5732 mii_pollstat(mii); 5733 ifmr->ifm_active = mii->mii_media_active; 5734 ifmr->ifm_status = mii->mii_media_status; 5735 5736 BGE_UNLOCK(sc); 5737 } 5738 5739 static int 5740 bge_ioctl(if_t ifp, u_long command, caddr_t data) 5741 { 5742 struct bge_softc *sc = if_getsoftc(ifp); 5743 struct ifreq *ifr = (struct ifreq *) data; 5744 struct mii_data *mii; 5745 int flags, mask, error = 0; 5746 5747 switch (command) { 5748 case SIOCSIFMTU: 5749 if (BGE_IS_JUMBO_CAPABLE(sc) || 5750 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) { 5751 if (ifr->ifr_mtu < ETHERMIN || 5752 ifr->ifr_mtu > BGE_JUMBO_MTU) { 5753 error = EINVAL; 5754 break; 5755 } 5756 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) { 5757 error = EINVAL; 5758 break; 5759 } 5760 BGE_LOCK(sc); 5761 if (if_getmtu(ifp) != ifr->ifr_mtu) { 5762 if_setmtu(ifp, ifr->ifr_mtu); 5763 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 5764 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 5765 bge_init_locked(sc); 5766 } 5767 } 5768 BGE_UNLOCK(sc); 5769 break; 5770 case SIOCSIFFLAGS: 5771 BGE_LOCK(sc); 5772 if (if_getflags(ifp) & IFF_UP) { 5773 /* 5774 * If only the state of the PROMISC flag changed, 5775 * then just use the 'set promisc mode' command 5776 * instead of reinitializing the entire NIC. Doing 5777 * a full re-init means reloading the firmware and 5778 * waiting for it to start up, which may take a 5779 * second or two. Similarly for ALLMULTI. 5780 */ 5781 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 5782 flags = if_getflags(ifp) ^ sc->bge_if_flags; 5783 if (flags & IFF_PROMISC) 5784 bge_setpromisc(sc); 5785 if (flags & IFF_ALLMULTI) 5786 bge_setmulti(sc); 5787 } else 5788 bge_init_locked(sc); 5789 } else { 5790 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 5791 bge_stop(sc); 5792 } 5793 } 5794 sc->bge_if_flags = if_getflags(ifp); 5795 BGE_UNLOCK(sc); 5796 error = 0; 5797 break; 5798 case SIOCADDMULTI: 5799 case SIOCDELMULTI: 5800 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 5801 BGE_LOCK(sc); 5802 bge_setmulti(sc); 5803 BGE_UNLOCK(sc); 5804 error = 0; 5805 } 5806 break; 5807 case SIOCSIFMEDIA: 5808 case SIOCGIFMEDIA: 5809 if (sc->bge_flags & BGE_FLAG_TBI) { 5810 error = ifmedia_ioctl(ifp, ifr, 5811 &sc->bge_ifmedia, command); 5812 } else { 5813 mii = device_get_softc(sc->bge_miibus); 5814 error = ifmedia_ioctl(ifp, ifr, 5815 &mii->mii_media, command); 5816 } 5817 break; 5818 case SIOCSIFCAP: 5819 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 5820 #ifdef DEVICE_POLLING 5821 if (mask & IFCAP_POLLING) { 5822 if (ifr->ifr_reqcap & IFCAP_POLLING) { 5823 error = ether_poll_register(bge_poll, ifp); 5824 if (error) 5825 return (error); 5826 BGE_LOCK(sc); 5827 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5828 BGE_PCIMISCCTL_MASK_PCI_INTR); 5829 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5830 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 5831 BGE_UNLOCK(sc); 5832 } else { 5833 error = ether_poll_deregister(ifp); 5834 /* Enable interrupt even in error case */ 5835 BGE_LOCK(sc); 5836 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 5837 BGE_PCIMISCCTL_MASK_PCI_INTR); 5838 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5839 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 5840 BGE_UNLOCK(sc); 5841 } 5842 } 5843 #endif 5844 if ((mask & IFCAP_TXCSUM) != 0 && 5845 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 5846 if_togglecapenable(ifp, IFCAP_TXCSUM); 5847 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 5848 if_sethwassistbits(ifp, 5849 sc->bge_csum_features, 0); 5850 else 5851 if_sethwassistbits(ifp, 0, 5852 sc->bge_csum_features); 5853 } 5854 5855 if ((mask & IFCAP_RXCSUM) != 0 && 5856 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) 5857 if_togglecapenable(ifp, IFCAP_RXCSUM); 5858 5859 if ((mask & IFCAP_TSO4) != 0 && 5860 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 5861 if_togglecapenable(ifp, IFCAP_TSO4); 5862 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) 5863 if_sethwassistbits(ifp, CSUM_TSO, 0); 5864 else 5865 if_sethwassistbits(ifp, 0, CSUM_TSO); 5866 } 5867 5868 if (mask & IFCAP_VLAN_MTU) { 5869 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 5870 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 5871 bge_init(sc); 5872 } 5873 5874 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 5875 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 5876 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 5877 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 5878 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 5879 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 5880 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 5881 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 5882 BGE_LOCK(sc); 5883 bge_setvlan(sc); 5884 BGE_UNLOCK(sc); 5885 } 5886 #ifdef VLAN_CAPABILITIES 5887 if_vlancap(ifp); 5888 #endif 5889 break; 5890 default: 5891 error = ether_ioctl(ifp, command, data); 5892 break; 5893 } 5894 5895 return (error); 5896 } 5897 5898 static void 5899 bge_watchdog(struct bge_softc *sc) 5900 { 5901 if_t ifp; 5902 uint32_t status; 5903 5904 BGE_LOCK_ASSERT(sc); 5905 5906 if (sc->bge_timer == 0 || --sc->bge_timer) 5907 return; 5908 5909 /* If pause frames are active then don't reset the hardware. */ 5910 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 5911 status = CSR_READ_4(sc, BGE_RX_STS); 5912 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 5913 /* 5914 * If link partner has us in XOFF state then wait for 5915 * the condition to clear. 5916 */ 5917 CSR_WRITE_4(sc, BGE_RX_STS, status); 5918 sc->bge_timer = BGE_TX_TIMEOUT; 5919 return; 5920 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 5921 (status & BGE_RXSTAT_RCVD_XON) != 0) { 5922 /* 5923 * If link partner has us in XOFF state then wait for 5924 * the condition to clear. 5925 */ 5926 CSR_WRITE_4(sc, BGE_RX_STS, status); 5927 sc->bge_timer = BGE_TX_TIMEOUT; 5928 return; 5929 } 5930 /* 5931 * Any other condition is unexpected and the controller 5932 * should be reset. 5933 */ 5934 } 5935 5936 ifp = sc->bge_ifp; 5937 5938 if_printf(ifp, "watchdog timeout -- resetting\n"); 5939 5940 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 5941 bge_init_locked(sc); 5942 5943 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 5944 } 5945 5946 static void 5947 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit) 5948 { 5949 int i; 5950 5951 BGE_CLRBIT(sc, reg, bit); 5952 5953 for (i = 0; i < BGE_TIMEOUT; i++) { 5954 if ((CSR_READ_4(sc, reg) & bit) == 0) 5955 return; 5956 DELAY(100); 5957 } 5958 } 5959 5960 /* 5961 * Stop the adapter and free any mbufs allocated to the 5962 * RX and TX lists. 5963 */ 5964 static void 5965 bge_stop(struct bge_softc *sc) 5966 { 5967 if_t ifp; 5968 5969 BGE_LOCK_ASSERT(sc); 5970 5971 ifp = sc->bge_ifp; 5972 5973 callout_stop(&sc->bge_stat_ch); 5974 5975 /* Disable host interrupts. */ 5976 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5977 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5978 5979 /* 5980 * Tell firmware we're shutting down. 5981 */ 5982 bge_stop_fw(sc); 5983 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5984 5985 /* 5986 * Disable all of the receiver blocks. 5987 */ 5988 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5989 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5990 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5991 if (BGE_IS_5700_FAMILY(sc)) 5992 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5993 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5994 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5995 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5996 5997 /* 5998 * Disable all of the transmit blocks. 5999 */ 6000 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 6001 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 6002 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 6003 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 6004 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 6005 if (BGE_IS_5700_FAMILY(sc)) 6006 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 6007 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 6008 6009 /* 6010 * Shut down all of the memory managers and related 6011 * state machines. 6012 */ 6013 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 6014 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 6015 if (BGE_IS_5700_FAMILY(sc)) 6016 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 6017 6018 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 6019 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 6020 if (!(BGE_IS_5705_PLUS(sc))) { 6021 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 6022 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 6023 } 6024 /* Update MAC statistics. */ 6025 if (BGE_IS_5705_PLUS(sc)) 6026 bge_stats_update_regs(sc); 6027 6028 bge_reset(sc); 6029 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 6030 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 6031 6032 /* 6033 * Keep the ASF firmware running if up. 6034 */ 6035 if (sc->bge_asf_mode & ASF_STACKUP) 6036 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6037 else 6038 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6039 6040 /* Free the RX lists. */ 6041 bge_free_rx_ring_std(sc); 6042 6043 /* Free jumbo RX list. */ 6044 if (BGE_IS_JUMBO_CAPABLE(sc)) 6045 bge_free_rx_ring_jumbo(sc); 6046 6047 /* Free TX buffers. */ 6048 bge_free_tx_ring(sc); 6049 6050 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6051 6052 /* Clear MAC's link state (PHY may still have link UP). */ 6053 if (bootverbose && sc->bge_link) 6054 if_printf(sc->bge_ifp, "link DOWN\n"); 6055 sc->bge_link = 0; 6056 6057 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 6058 } 6059 6060 /* 6061 * Stop all chip I/O so that the kernel's probe routines don't 6062 * get confused by errant DMAs when rebooting. 6063 */ 6064 static int 6065 bge_shutdown(device_t dev) 6066 { 6067 struct bge_softc *sc; 6068 6069 sc = device_get_softc(dev); 6070 BGE_LOCK(sc); 6071 bge_stop(sc); 6072 BGE_UNLOCK(sc); 6073 6074 return (0); 6075 } 6076 6077 static int 6078 bge_suspend(device_t dev) 6079 { 6080 struct bge_softc *sc; 6081 6082 sc = device_get_softc(dev); 6083 BGE_LOCK(sc); 6084 bge_stop(sc); 6085 BGE_UNLOCK(sc); 6086 6087 return (0); 6088 } 6089 6090 static int 6091 bge_resume(device_t dev) 6092 { 6093 struct bge_softc *sc; 6094 if_t ifp; 6095 6096 sc = device_get_softc(dev); 6097 BGE_LOCK(sc); 6098 ifp = sc->bge_ifp; 6099 if (if_getflags(ifp) & IFF_UP) { 6100 bge_init_locked(sc); 6101 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 6102 bge_start_locked(ifp); 6103 } 6104 BGE_UNLOCK(sc); 6105 6106 return (0); 6107 } 6108 6109 static void 6110 bge_link_upd(struct bge_softc *sc) 6111 { 6112 struct mii_data *mii; 6113 uint32_t link, status; 6114 6115 BGE_LOCK_ASSERT(sc); 6116 6117 /* Clear 'pending link event' flag. */ 6118 sc->bge_link_evt = 0; 6119 6120 /* 6121 * Process link state changes. 6122 * Grrr. The link status word in the status block does 6123 * not work correctly on the BCM5700 rev AX and BX chips, 6124 * according to all available information. Hence, we have 6125 * to enable MII interrupts in order to properly obtain 6126 * async link changes. Unfortunately, this also means that 6127 * we have to read the MAC status register to detect link 6128 * changes, thereby adding an additional register access to 6129 * the interrupt handler. 6130 * 6131 * XXX: perhaps link state detection procedure used for 6132 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 6133 */ 6134 6135 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 6136 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 6137 status = CSR_READ_4(sc, BGE_MAC_STS); 6138 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6139 mii = device_get_softc(sc->bge_miibus); 6140 mii_pollstat(mii); 6141 if (!sc->bge_link && 6142 mii->mii_media_status & IFM_ACTIVE && 6143 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 6144 sc->bge_link++; 6145 if (bootverbose) 6146 if_printf(sc->bge_ifp, "link UP\n"); 6147 } else if (sc->bge_link && 6148 (!(mii->mii_media_status & IFM_ACTIVE) || 6149 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 6150 sc->bge_link = 0; 6151 if (bootverbose) 6152 if_printf(sc->bge_ifp, "link DOWN\n"); 6153 } 6154 6155 /* Clear the interrupt. */ 6156 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6157 BGE_EVTENB_MI_INTERRUPT); 6158 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6159 BRGPHY_MII_ISR); 6160 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6161 BRGPHY_MII_IMR, BRGPHY_INTRS); 6162 } 6163 return; 6164 } 6165 6166 if (sc->bge_flags & BGE_FLAG_TBI) { 6167 status = CSR_READ_4(sc, BGE_MAC_STS); 6168 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6169 if (!sc->bge_link) { 6170 sc->bge_link++; 6171 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 6172 BGE_CLRBIT(sc, BGE_MAC_MODE, 6173 BGE_MACMODE_TBI_SEND_CFGS); 6174 DELAY(40); 6175 } 6176 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6177 if (bootverbose) 6178 if_printf(sc->bge_ifp, "link UP\n"); 6179 if_link_state_change(sc->bge_ifp, 6180 LINK_STATE_UP); 6181 } 6182 } else if (sc->bge_link) { 6183 sc->bge_link = 0; 6184 if (bootverbose) 6185 if_printf(sc->bge_ifp, "link DOWN\n"); 6186 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 6187 } 6188 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 6189 /* 6190 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 6191 * in status word always set. Workaround this bug by reading 6192 * PHY link status directly. 6193 */ 6194 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 6195 6196 if (link != sc->bge_link || 6197 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 6198 mii = device_get_softc(sc->bge_miibus); 6199 mii_pollstat(mii); 6200 if (!sc->bge_link && 6201 mii->mii_media_status & IFM_ACTIVE && 6202 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 6203 sc->bge_link++; 6204 if (bootverbose) 6205 if_printf(sc->bge_ifp, "link UP\n"); 6206 } else if (sc->bge_link && 6207 (!(mii->mii_media_status & IFM_ACTIVE) || 6208 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 6209 sc->bge_link = 0; 6210 if (bootverbose) 6211 if_printf(sc->bge_ifp, "link DOWN\n"); 6212 } 6213 } 6214 } else { 6215 /* 6216 * For controllers that call mii_tick, we have to poll 6217 * link status. 6218 */ 6219 mii = device_get_softc(sc->bge_miibus); 6220 mii_pollstat(mii); 6221 bge_miibus_statchg(sc->bge_dev); 6222 } 6223 6224 /* Disable MAC attention when link is up. */ 6225 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 6226 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 6227 BGE_MACSTAT_LINK_CHANGED); 6228 } 6229 6230 static void 6231 bge_add_sysctls(struct bge_softc *sc) 6232 { 6233 struct sysctl_ctx_list *ctx; 6234 struct sysctl_oid_list *children; 6235 6236 ctx = device_get_sysctl_ctx(sc->bge_dev); 6237 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 6238 6239 #ifdef BGE_REGISTER_DEBUG 6240 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 6241 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 6242 bge_sysctl_debug_info, "I", "Debug Information"); 6243 6244 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 6245 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 6246 bge_sysctl_reg_read, "I", "MAC Register Read"); 6247 6248 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read", 6249 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 6250 bge_sysctl_ape_read, "I", "APE Register Read"); 6251 6252 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 6253 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 6254 bge_sysctl_mem_read, "I", "Memory Read"); 6255 6256 #endif 6257 6258 /* 6259 * A common design characteristic for many Broadcom client controllers 6260 * is that they only support a single outstanding DMA read operation 6261 * on the PCIe bus. This means that it will take twice as long to fetch 6262 * a TX frame that is split into header and payload buffers as it does 6263 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For 6264 * these controllers, coalescing buffers to reduce the number of memory 6265 * reads is effective way to get maximum performance(about 940Mbps). 6266 * Without collapsing TX buffers the maximum TCP bulk transfer 6267 * performance is about 850Mbps. However forcing coalescing mbufs 6268 * consumes a lot of CPU cycles, so leave it off by default. 6269 */ 6270 sc->bge_forced_collapse = 0; 6271 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse", 6272 CTLFLAG_RWTUN, &sc->bge_forced_collapse, 0, 6273 "Number of fragmented TX buffers of a frame allowed before " 6274 "forced collapsing"); 6275 6276 sc->bge_msi = 1; 6277 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi", 6278 CTLFLAG_RDTUN, &sc->bge_msi, 0, "Enable MSI"); 6279 6280 /* 6281 * It seems all Broadcom controllers have a bug that can generate UDP 6282 * datagrams with checksum value 0 when TX UDP checksum offloading is 6283 * enabled. Generating UDP checksum value 0 is RFC 768 violation. 6284 * Even though the probability of generating such UDP datagrams is 6285 * low, I don't want to see FreeBSD boxes to inject such datagrams 6286 * into network so disable UDP checksum offloading by default. Users 6287 * still override this behavior by setting a sysctl variable, 6288 * dev.bge.0.forced_udpcsum. 6289 */ 6290 sc->bge_forced_udpcsum = 0; 6291 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum", 6292 CTLFLAG_RWTUN, &sc->bge_forced_udpcsum, 0, 6293 "Enable UDP checksum offloading even if controller can " 6294 "generate UDP checksum value 0"); 6295 6296 if (BGE_IS_5705_PLUS(sc)) 6297 bge_add_sysctl_stats_regs(sc, ctx, children); 6298 else 6299 bge_add_sysctl_stats(sc, ctx, children); 6300 } 6301 6302 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 6303 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, \ 6304 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, \ 6305 offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", desc) 6306 6307 static void 6308 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 6309 struct sysctl_oid_list *parent) 6310 { 6311 struct sysctl_oid *tree; 6312 struct sysctl_oid_list *children, *schildren; 6313 6314 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", 6315 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE Statistics"); 6316 schildren = children = SYSCTL_CHILDREN(tree); 6317 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 6318 children, COSFramesDroppedDueToFilters, 6319 "FramesDroppedDueToFilters"); 6320 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 6321 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 6322 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 6323 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 6324 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 6325 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 6326 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 6327 children, ifInDiscards, "InputDiscards"); 6328 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 6329 children, ifInErrors, "InputErrors"); 6330 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 6331 children, nicRecvThresholdHit, "RecvThresholdHit"); 6332 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 6333 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 6334 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 6335 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 6336 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 6337 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 6338 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 6339 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 6340 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 6341 children, nicRingStatusUpdate, "RingStatusUpdate"); 6342 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 6343 children, nicInterrupts, "Interrupts"); 6344 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 6345 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 6346 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 6347 children, nicSendThresholdHit, "SendThresholdHit"); 6348 6349 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", 6350 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE RX Statistics"); 6351 children = SYSCTL_CHILDREN(tree); 6352 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 6353 children, rxstats.ifHCInOctets, "ifHCInOctets"); 6354 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 6355 children, rxstats.etherStatsFragments, "Fragments"); 6356 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 6357 children, rxstats.ifHCInUcastPkts, "UnicastPkts"); 6358 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 6359 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 6360 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 6361 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 6362 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 6363 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 6364 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 6365 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 6366 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 6367 children, rxstats.xoffPauseFramesReceived, 6368 "xoffPauseFramesReceived"); 6369 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 6370 children, rxstats.macControlFramesReceived, 6371 "ControlFramesReceived"); 6372 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 6373 children, rxstats.xoffStateEntered, "xoffStateEntered"); 6374 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 6375 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 6376 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 6377 children, rxstats.etherStatsJabbers, "Jabbers"); 6378 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 6379 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 6380 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 6381 children, rxstats.inRangeLengthError, "inRangeLengthError"); 6382 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 6383 children, rxstats.outRangeLengthError, "outRangeLengthError"); 6384 6385 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", 6386 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE TX Statistics"); 6387 children = SYSCTL_CHILDREN(tree); 6388 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 6389 children, txstats.ifHCOutOctets, "ifHCOutOctets"); 6390 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 6391 children, txstats.etherStatsCollisions, "Collisions"); 6392 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 6393 children, txstats.outXonSent, "XonSent"); 6394 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 6395 children, txstats.outXoffSent, "XoffSent"); 6396 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 6397 children, txstats.flowControlDone, "flowControlDone"); 6398 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 6399 children, txstats.dot3StatsInternalMacTransmitErrors, 6400 "InternalMacTransmitErrors"); 6401 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 6402 children, txstats.dot3StatsSingleCollisionFrames, 6403 "SingleCollisionFrames"); 6404 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 6405 children, txstats.dot3StatsMultipleCollisionFrames, 6406 "MultipleCollisionFrames"); 6407 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 6408 children, txstats.dot3StatsDeferredTransmissions, 6409 "DeferredTransmissions"); 6410 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 6411 children, txstats.dot3StatsExcessiveCollisions, 6412 "ExcessiveCollisions"); 6413 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 6414 children, txstats.dot3StatsLateCollisions, 6415 "LateCollisions"); 6416 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 6417 children, txstats.ifHCOutUcastPkts, "UnicastPkts"); 6418 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 6419 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 6420 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 6421 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 6422 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 6423 children, txstats.dot3StatsCarrierSenseErrors, 6424 "CarrierSenseErrors"); 6425 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 6426 children, txstats.ifOutDiscards, "Discards"); 6427 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 6428 children, txstats.ifOutErrors, "Errors"); 6429 } 6430 6431 #undef BGE_SYSCTL_STAT 6432 6433 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 6434 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 6435 6436 static void 6437 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 6438 struct sysctl_oid_list *parent) 6439 { 6440 struct sysctl_oid *tree; 6441 struct sysctl_oid_list *child, *schild; 6442 struct bge_mac_stats *stats; 6443 6444 stats = &sc->bge_mac_stats; 6445 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", 6446 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE Statistics"); 6447 schild = child = SYSCTL_CHILDREN(tree); 6448 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters", 6449 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters"); 6450 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull", 6451 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full"); 6452 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull", 6453 &stats->DmaWriteHighPriQueueFull, 6454 "NIC DMA Write High Priority Queue Full"); 6455 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs", 6456 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors"); 6457 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards", 6458 &stats->InputDiscards, "Discarded Input Frames"); 6459 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors", 6460 &stats->InputErrors, "Input Errors"); 6461 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit", 6462 &stats->RecvThresholdHit, "NIC Recv Threshold Hit"); 6463 6464 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", 6465 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE RX Statistics"); 6466 child = SYSCTL_CHILDREN(tree); 6467 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets", 6468 &stats->ifHCInOctets, "Inbound Octets"); 6469 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments", 6470 &stats->etherStatsFragments, "Fragments"); 6471 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 6472 &stats->ifHCInUcastPkts, "Inbound Unicast Packets"); 6473 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 6474 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets"); 6475 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 6476 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets"); 6477 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors", 6478 &stats->dot3StatsFCSErrors, "FCS Errors"); 6479 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors", 6480 &stats->dot3StatsAlignmentErrors, "Alignment Errors"); 6481 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived", 6482 &stats->xonPauseFramesReceived, "XON Pause Frames Received"); 6483 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived", 6484 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received"); 6485 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived", 6486 &stats->macControlFramesReceived, "MAC Control Frames Received"); 6487 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered", 6488 &stats->xoffStateEntered, "XOFF State Entered"); 6489 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong", 6490 &stats->dot3StatsFramesTooLong, "Frames Too Long"); 6491 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers", 6492 &stats->etherStatsJabbers, "Jabbers"); 6493 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts", 6494 &stats->etherStatsUndersizePkts, "Undersized Packets"); 6495 6496 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", 6497 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE TX Statistics"); 6498 child = SYSCTL_CHILDREN(tree); 6499 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets", 6500 &stats->ifHCOutOctets, "Outbound Octets"); 6501 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions", 6502 &stats->etherStatsCollisions, "TX Collisions"); 6503 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent", 6504 &stats->outXonSent, "XON Sent"); 6505 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent", 6506 &stats->outXoffSent, "XOFF Sent"); 6507 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors", 6508 &stats->dot3StatsInternalMacTransmitErrors, 6509 "Internal MAC TX Errors"); 6510 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames", 6511 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames"); 6512 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames", 6513 &stats->dot3StatsMultipleCollisionFrames, 6514 "Multiple Collision Frames"); 6515 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions", 6516 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions"); 6517 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions", 6518 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions"); 6519 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions", 6520 &stats->dot3StatsLateCollisions, "Late Collisions"); 6521 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 6522 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets"); 6523 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 6524 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets"); 6525 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 6526 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets"); 6527 } 6528 6529 #undef BGE_SYSCTL_STAT_ADD64 6530 6531 static int 6532 bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 6533 { 6534 struct bge_softc *sc; 6535 uint32_t result; 6536 int offset; 6537 6538 sc = (struct bge_softc *)arg1; 6539 offset = arg2; 6540 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 6541 offsetof(bge_hostaddr, bge_addr_lo)); 6542 return (sysctl_handle_int(oidp, &result, 0, req)); 6543 } 6544 6545 #ifdef BGE_REGISTER_DEBUG 6546 static int 6547 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 6548 { 6549 struct bge_softc *sc; 6550 uint16_t *sbdata; 6551 int error, result, sbsz; 6552 int i, j; 6553 6554 result = -1; 6555 error = sysctl_handle_int(oidp, &result, 0, req); 6556 if (error || (req->newptr == NULL)) 6557 return (error); 6558 6559 if (result == 1) { 6560 sc = (struct bge_softc *)arg1; 6561 6562 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 6563 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 6564 sbsz = BGE_STATUS_BLK_SZ; 6565 else 6566 sbsz = 32; 6567 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 6568 printf("Status Block:\n"); 6569 BGE_LOCK(sc); 6570 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 6571 sc->bge_cdata.bge_status_map, 6572 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6573 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) { 6574 printf("%06x:", i); 6575 for (j = 0; j < 8; j++) 6576 printf(" %04x", sbdata[i++]); 6577 printf("\n"); 6578 } 6579 6580 printf("Registers:\n"); 6581 for (i = 0x800; i < 0xA00; ) { 6582 printf("%06x:", i); 6583 for (j = 0; j < 8; j++) { 6584 printf(" %08x", CSR_READ_4(sc, i)); 6585 i += 4; 6586 } 6587 printf("\n"); 6588 } 6589 BGE_UNLOCK(sc); 6590 6591 printf("Hardware Flags:\n"); 6592 if (BGE_IS_5717_PLUS(sc)) 6593 printf(" - 5717 Plus\n"); 6594 if (BGE_IS_5755_PLUS(sc)) 6595 printf(" - 5755 Plus\n"); 6596 if (BGE_IS_575X_PLUS(sc)) 6597 printf(" - 575X Plus\n"); 6598 if (BGE_IS_5705_PLUS(sc)) 6599 printf(" - 5705 Plus\n"); 6600 if (BGE_IS_5714_FAMILY(sc)) 6601 printf(" - 5714 Family\n"); 6602 if (BGE_IS_5700_FAMILY(sc)) 6603 printf(" - 5700 Family\n"); 6604 if (sc->bge_flags & BGE_FLAG_JUMBO) 6605 printf(" - Supports Jumbo Frames\n"); 6606 if (sc->bge_flags & BGE_FLAG_PCIX) 6607 printf(" - PCI-X Bus\n"); 6608 if (sc->bge_flags & BGE_FLAG_PCIE) 6609 printf(" - PCI Express Bus\n"); 6610 if (sc->bge_phy_flags & BGE_PHY_NO_3LED) 6611 printf(" - No 3 LEDs\n"); 6612 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 6613 printf(" - RX Alignment Bug\n"); 6614 } 6615 6616 return (error); 6617 } 6618 6619 static int 6620 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 6621 { 6622 struct bge_softc *sc; 6623 int error; 6624 uint16_t result; 6625 uint32_t val; 6626 6627 result = -1; 6628 error = sysctl_handle_int(oidp, &result, 0, req); 6629 if (error || (req->newptr == NULL)) 6630 return (error); 6631 6632 if (result < 0x8000) { 6633 sc = (struct bge_softc *)arg1; 6634 val = CSR_READ_4(sc, result); 6635 printf("reg 0x%06X = 0x%08X\n", result, val); 6636 } 6637 6638 return (error); 6639 } 6640 6641 static int 6642 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS) 6643 { 6644 struct bge_softc *sc; 6645 int error; 6646 uint16_t result; 6647 uint32_t val; 6648 6649 result = -1; 6650 error = sysctl_handle_int(oidp, &result, 0, req); 6651 if (error || (req->newptr == NULL)) 6652 return (error); 6653 6654 if (result < 0x8000) { 6655 sc = (struct bge_softc *)arg1; 6656 val = APE_READ_4(sc, result); 6657 printf("reg 0x%06X = 0x%08X\n", result, val); 6658 } 6659 6660 return (error); 6661 } 6662 6663 static int 6664 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 6665 { 6666 struct bge_softc *sc; 6667 int error; 6668 uint16_t result; 6669 uint32_t val; 6670 6671 result = -1; 6672 error = sysctl_handle_int(oidp, &result, 0, req); 6673 if (error || (req->newptr == NULL)) 6674 return (error); 6675 6676 if (result < 0x8000) { 6677 sc = (struct bge_softc *)arg1; 6678 val = bge_readmem_ind(sc, result); 6679 printf("mem 0x%06X = 0x%08X\n", result, val); 6680 } 6681 6682 return (error); 6683 } 6684 #endif 6685 6686 static int 6687 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6688 { 6689 return (1); 6690 } 6691 6692 static int 6693 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6694 { 6695 uint32_t mac_addr; 6696 6697 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6698 if ((mac_addr >> 16) == 0x484b) { 6699 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6700 ether_addr[1] = (uint8_t)mac_addr; 6701 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6702 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6703 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6704 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6705 ether_addr[5] = (uint8_t)mac_addr; 6706 return (0); 6707 } 6708 return (1); 6709 } 6710 6711 static int 6712 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6713 { 6714 int mac_offset = BGE_EE_MAC_OFFSET; 6715 6716 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6717 mac_offset = BGE_EE_MAC_OFFSET_5906; 6718 6719 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6720 ETHER_ADDR_LEN)); 6721 } 6722 6723 static int 6724 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6725 { 6726 6727 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6728 return (1); 6729 6730 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6731 ETHER_ADDR_LEN)); 6732 } 6733 6734 static int 6735 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6736 { 6737 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6738 /* NOTE: Order is critical */ 6739 bge_get_eaddr_fw, 6740 bge_get_eaddr_mem, 6741 bge_get_eaddr_nvram, 6742 bge_get_eaddr_eeprom, 6743 NULL 6744 }; 6745 const bge_eaddr_fcn_t *func; 6746 6747 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6748 if ((*func)(sc, eaddr) == 0) 6749 break; 6750 } 6751 return (*func == NULL ? ENXIO : 0); 6752 } 6753 6754 static uint64_t 6755 bge_get_counter(if_t ifp, ift_counter cnt) 6756 { 6757 struct bge_softc *sc; 6758 struct bge_mac_stats *stats; 6759 6760 sc = if_getsoftc(ifp); 6761 if (!BGE_IS_5705_PLUS(sc)) 6762 return (if_get_counter_default(ifp, cnt)); 6763 stats = &sc->bge_mac_stats; 6764 6765 switch (cnt) { 6766 case IFCOUNTER_IERRORS: 6767 return (stats->NoMoreRxBDs + stats->InputDiscards + 6768 stats->InputErrors); 6769 case IFCOUNTER_COLLISIONS: 6770 return (stats->etherStatsCollisions); 6771 default: 6772 return (if_get_counter_default(ifp, cnt)); 6773 } 6774 } 6775 6776 #ifdef DEBUGNET 6777 static void 6778 bge_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 6779 { 6780 struct bge_softc *sc; 6781 6782 sc = if_getsoftc(ifp); 6783 BGE_LOCK(sc); 6784 /* 6785 * There is only one logical receive ring, but it is backed 6786 * by two actual rings, for cluster- and jumbo-sized mbufs. 6787 * Debugnet expects only one size, so if jumbo is in use, 6788 * this says we have two rings of jumbo mbufs, but that's 6789 * only a little wasteful. 6790 */ 6791 *nrxr = 2; 6792 *ncl = DEBUGNET_MAX_IN_FLIGHT; 6793 if ((sc->bge_flags & BGE_FLAG_JUMBO_STD) != 0 && 6794 (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN + 6795 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) 6796 *clsize = MJUM9BYTES; 6797 else 6798 *clsize = MCLBYTES; 6799 BGE_UNLOCK(sc); 6800 } 6801 6802 static void 6803 bge_debugnet_event(if_t ifp __unused, enum debugnet_ev event __unused) 6804 { 6805 } 6806 6807 static int 6808 bge_debugnet_transmit(if_t ifp, struct mbuf *m) 6809 { 6810 struct bge_softc *sc; 6811 uint32_t prodidx; 6812 int error; 6813 6814 sc = if_getsoftc(ifp); 6815 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6816 IFF_DRV_RUNNING) 6817 return (1); 6818 6819 prodidx = sc->bge_tx_prodidx; 6820 error = bge_encap(sc, &m, &prodidx); 6821 if (error == 0) 6822 bge_start_tx(sc, prodidx); 6823 return (error); 6824 } 6825 6826 static int 6827 bge_debugnet_poll(if_t ifp, int count) 6828 { 6829 struct bge_softc *sc; 6830 uint32_t rx_prod, tx_cons; 6831 6832 sc = if_getsoftc(ifp); 6833 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6834 IFF_DRV_RUNNING) 6835 return (1); 6836 6837 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 6838 sc->bge_cdata.bge_status_map, 6839 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6840 6841 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 6842 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 6843 6844 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 6845 sc->bge_cdata.bge_status_map, 6846 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 6847 6848 (void)bge_rxeof(sc, rx_prod, 0); 6849 bge_txeof(sc, tx_cons); 6850 return (0); 6851 } 6852 #endif /* DEBUGNET */
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