FreeBSD/Linux Kernel Cross Reference
sys/dev/bge/if_bge.c
1 /*-
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD: head/sys/dev/bge/if_bge.c 199153 2009-11-10 20:29:20Z yongari $");
36
37 /*
38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
39 *
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
45 * frames, highly configurable RX filtering, and 16 RX and TX queues
46 * (which, along with RX filter rules, can be used for QOS applications).
47 * Other features, such as TCP segmentation, may be available as part
48 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
49 * firmware images can be stored in hardware and need not be compiled
50 * into the driver.
51 *
52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
54 *
55 * The BCM5701 is a single-chip solution incorporating both the BCM5700
56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
57 * does not support external SSRAM.
58 *
59 * Broadcom also produces a variation of the BCM5700 under the "Altima"
60 * brand name, which is functionally similar but lacks PCI-X support.
61 *
62 * Without external SSRAM, you can only have at most 4 TX rings,
63 * and the use of the mini RX ring is disabled. This seems to imply
64 * that these features are simply not available on the BCM5701. As a
65 * result, this driver does not implement any support for the mini RX
66 * ring.
67 */
68
69 #ifdef HAVE_KERNEL_OPTION_HEADERS
70 #include "opt_device_polling.h"
71 #endif
72
73 #include <sys/param.h>
74 #include <sys/endian.h>
75 #include <sys/systm.h>
76 #include <sys/sockio.h>
77 #include <sys/mbuf.h>
78 #include <sys/malloc.h>
79 #include <sys/kernel.h>
80 #include <sys/module.h>
81 #include <sys/socket.h>
82 #include <sys/sysctl.h>
83
84 #include <net/if.h>
85 #include <net/if_arp.h>
86 #include <net/ethernet.h>
87 #include <net/if_dl.h>
88 #include <net/if_media.h>
89
90 #include <net/bpf.h>
91
92 #include <net/if_types.h>
93 #include <net/if_vlan_var.h>
94
95 #include <netinet/in_systm.h>
96 #include <netinet/in.h>
97 #include <netinet/ip.h>
98
99 #include <machine/bus.h>
100 #include <machine/resource.h>
101 #include <sys/bus.h>
102 #include <sys/rman.h>
103
104 #include <dev/mii/mii.h>
105 #include <dev/mii/miivar.h>
106 #include "miidevs.h"
107 #include <dev/mii/brgphyreg.h>
108
109 #ifdef __sparc64__
110 #include <dev/ofw/ofw_bus.h>
111 #include <dev/ofw/openfirm.h>
112 #include <machine/ofw_machdep.h>
113 #include <machine/ver.h>
114 #endif
115
116 #include <dev/pci/pcireg.h>
117 #include <dev/pci/pcivar.h>
118
119 #include <dev/bge/if_bgereg.h>
120
121 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
122 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
123
124 MODULE_DEPEND(bge, pci, 1, 1, 1);
125 MODULE_DEPEND(bge, ether, 1, 1, 1);
126 MODULE_DEPEND(bge, miibus, 1, 1, 1);
127
128 /* "device miibus" required. See GENERIC if you get errors here. */
129 #include "miibus_if.h"
130
131 /*
132 * Various supported device vendors/types and their names. Note: the
133 * spec seems to indicate that the hardware still has Alteon's vendor
134 * ID burned into it, though it will always be overriden by the vendor
135 * ID in the EEPROM. Just to be safe, we cover all possibilities.
136 */
137 static const struct bge_type {
138 uint16_t bge_vid;
139 uint16_t bge_did;
140 } bge_devs[] = {
141 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 },
142 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 },
143
144 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 },
145 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 },
146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 },
147
148 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 },
149
150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 },
151 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 },
152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 },
153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT },
154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X },
155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 },
156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT },
157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X },
158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C },
159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S },
160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT },
161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 },
162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F },
163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K },
164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M },
165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT },
166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C },
167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S },
168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 },
169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S },
170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 },
171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 },
172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 },
173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 },
174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 },
175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M },
176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 },
177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F },
178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M },
179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 },
180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M },
181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 },
182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F },
183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M },
184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 },
185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M },
186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 },
187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M },
188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 },
189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E },
190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S },
191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE },
192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 },
193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 },
194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S },
195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 },
196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 },
197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 },
198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F },
199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G },
200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 },
201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 },
202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F },
203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M },
204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 },
205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 },
206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 },
207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 },
208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M },
209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 },
210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M },
211 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 },
212 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 },
213 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 },
214 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 },
215
216 { SK_VENDORID, SK_DEVICEID_ALTIMA },
217
218 { TC_VENDORID, TC_DEVICEID_3C996 },
219
220 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 },
221 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 },
222 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 },
223
224 { 0, 0 }
225 };
226
227 static const struct bge_vendor {
228 uint16_t v_id;
229 const char *v_name;
230 } bge_vendors[] = {
231 { ALTEON_VENDORID, "Alteon" },
232 { ALTIMA_VENDORID, "Altima" },
233 { APPLE_VENDORID, "Apple" },
234 { BCOM_VENDORID, "Broadcom" },
235 { SK_VENDORID, "SysKonnect" },
236 { TC_VENDORID, "3Com" },
237 { FJTSU_VENDORID, "Fujitsu" },
238
239 { 0, NULL }
240 };
241
242 static const struct bge_revision {
243 uint32_t br_chipid;
244 const char *br_name;
245 } bge_revisions[] = {
246 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" },
247 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" },
248 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" },
249 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" },
250 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" },
251 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" },
252 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" },
253 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" },
254 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" },
255 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" },
256 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" },
257 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" },
258 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" },
259 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" },
260 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" },
261 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" },
262 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" },
263 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" },
264 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" },
265 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" },
266 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" },
267 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" },
268 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" },
269 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" },
270 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" },
271 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" },
272 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" },
273 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" },
274 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" },
275 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" },
276 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" },
277 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" },
278 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" },
279 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" },
280 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
281 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
282 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
283 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
284 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
285 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
286 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
287 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
288 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
289 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
290 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
291 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
292 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" },
293 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" },
294 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" },
295 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" },
296 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" },
297 /* 5754 and 5787 share the same ASIC ID */
298 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" },
299 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" },
300 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" },
301 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" },
302 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" },
303 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" },
304 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" },
305
306 { 0, NULL }
307 };
308
309 /*
310 * Some defaults for major revisions, so that newer steppings
311 * that we don't know about have a shot at working.
312 */
313 static const struct bge_revision bge_majorrevs[] = {
314 { BGE_ASICREV_BCM5700, "unknown BCM5700" },
315 { BGE_ASICREV_BCM5701, "unknown BCM5701" },
316 { BGE_ASICREV_BCM5703, "unknown BCM5703" },
317 { BGE_ASICREV_BCM5704, "unknown BCM5704" },
318 { BGE_ASICREV_BCM5705, "unknown BCM5705" },
319 { BGE_ASICREV_BCM5750, "unknown BCM5750" },
320 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
321 { BGE_ASICREV_BCM5752, "unknown BCM5752" },
322 { BGE_ASICREV_BCM5780, "unknown BCM5780" },
323 { BGE_ASICREV_BCM5714, "unknown BCM5714" },
324 { BGE_ASICREV_BCM5755, "unknown BCM5755" },
325 { BGE_ASICREV_BCM5761, "unknown BCM5761" },
326 { BGE_ASICREV_BCM5784, "unknown BCM5784" },
327 { BGE_ASICREV_BCM5785, "unknown BCM5785" },
328 /* 5754 and 5787 share the same ASIC ID */
329 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
330 { BGE_ASICREV_BCM5906, "unknown BCM5906" },
331 { BGE_ASICREV_BCM57780, "unknown BCM57780" },
332
333 { 0, NULL }
334 };
335
336 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
337 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
338 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
339 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
340 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
341 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
342
343 const struct bge_revision * bge_lookup_rev(uint32_t);
344 const struct bge_vendor * bge_lookup_vendor(uint16_t);
345
346 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
347
348 static int bge_probe(device_t);
349 static int bge_attach(device_t);
350 static int bge_detach(device_t);
351 static int bge_suspend(device_t);
352 static int bge_resume(device_t);
353 static void bge_release_resources(struct bge_softc *);
354 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
355 static int bge_dma_alloc(device_t);
356 static void bge_dma_free(struct bge_softc *);
357
358 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
359 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
360 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
361 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
362 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
363
364 static void bge_txeof(struct bge_softc *);
365 static int bge_rxeof(struct bge_softc *);
366
367 static void bge_asf_driver_up (struct bge_softc *);
368 static void bge_tick(void *);
369 static void bge_stats_update(struct bge_softc *);
370 static void bge_stats_update_regs(struct bge_softc *);
371 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
372
373 static void bge_intr(void *);
374 static void bge_start_locked(struct ifnet *);
375 static void bge_start(struct ifnet *);
376 static int bge_ioctl(struct ifnet *, u_long, caddr_t);
377 static void bge_init_locked(struct bge_softc *);
378 static void bge_init(void *);
379 static void bge_stop(struct bge_softc *);
380 static void bge_watchdog(struct bge_softc *);
381 static int bge_shutdown(device_t);
382 static int bge_ifmedia_upd_locked(struct ifnet *);
383 static int bge_ifmedia_upd(struct ifnet *);
384 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
385
386 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
387 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
388
389 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
390 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
391
392 static void bge_setpromisc(struct bge_softc *);
393 static void bge_setmulti(struct bge_softc *);
394 static void bge_setvlan(struct bge_softc *);
395
396 static int bge_newbuf_std(struct bge_softc *, int);
397 static int bge_newbuf_jumbo(struct bge_softc *, int);
398 static int bge_init_rx_ring_std(struct bge_softc *);
399 static void bge_free_rx_ring_std(struct bge_softc *);
400 static int bge_init_rx_ring_jumbo(struct bge_softc *);
401 static void bge_free_rx_ring_jumbo(struct bge_softc *);
402 static void bge_free_tx_ring(struct bge_softc *);
403 static int bge_init_tx_ring(struct bge_softc *);
404
405 static int bge_chipinit(struct bge_softc *);
406 static int bge_blockinit(struct bge_softc *);
407
408 static int bge_has_eaddr(struct bge_softc *);
409 static uint32_t bge_readmem_ind(struct bge_softc *, int);
410 static void bge_writemem_ind(struct bge_softc *, int, int);
411 static void bge_writembx(struct bge_softc *, int, int);
412 #ifdef notdef
413 static uint32_t bge_readreg_ind(struct bge_softc *, int);
414 #endif
415 static void bge_writemem_direct(struct bge_softc *, int, int);
416 static void bge_writereg_ind(struct bge_softc *, int, int);
417 static void bge_set_max_readrq(struct bge_softc *, int);
418
419 static int bge_miibus_readreg(device_t, int, int);
420 static int bge_miibus_writereg(device_t, int, int, int);
421 static void bge_miibus_statchg(device_t);
422 #ifdef DEVICE_POLLING
423 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
424 #endif
425
426 #define BGE_RESET_START 1
427 #define BGE_RESET_STOP 2
428 static void bge_sig_post_reset(struct bge_softc *, int);
429 static void bge_sig_legacy(struct bge_softc *, int);
430 static void bge_sig_pre_reset(struct bge_softc *, int);
431 static int bge_reset(struct bge_softc *);
432 static void bge_link_upd(struct bge_softc *);
433
434 /*
435 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may
436 * leak information to untrusted users. It is also known to cause alignment
437 * traps on certain architectures.
438 */
439 #ifdef BGE_REGISTER_DEBUG
440 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
441 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
442 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
443 #endif
444 static void bge_add_sysctls(struct bge_softc *);
445 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
446
447 static device_method_t bge_methods[] = {
448 /* Device interface */
449 DEVMETHOD(device_probe, bge_probe),
450 DEVMETHOD(device_attach, bge_attach),
451 DEVMETHOD(device_detach, bge_detach),
452 DEVMETHOD(device_shutdown, bge_shutdown),
453 DEVMETHOD(device_suspend, bge_suspend),
454 DEVMETHOD(device_resume, bge_resume),
455
456 /* bus interface */
457 DEVMETHOD(bus_print_child, bus_generic_print_child),
458 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
459
460 /* MII interface */
461 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
462 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
463 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
464
465 { 0, 0 }
466 };
467
468 static driver_t bge_driver = {
469 "bge",
470 bge_methods,
471 sizeof(struct bge_softc)
472 };
473
474 static devclass_t bge_devclass;
475
476 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
477 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
478
479 static int bge_allow_asf = 1;
480
481 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
482
483 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
484 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
485 "Allow ASF mode if available");
486
487 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500"
488 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2"
489 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500"
490 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3"
491 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id"
492
493 static int
494 bge_has_eaddr(struct bge_softc *sc)
495 {
496 #ifdef __sparc64__
497 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
498 device_t dev;
499 uint32_t subvendor;
500
501 dev = sc->bge_dev;
502
503 /*
504 * The on-board BGEs found in sun4u machines aren't fitted with
505 * an EEPROM which means that we have to obtain the MAC address
506 * via OFW and that some tests will always fail. We distinguish
507 * such BGEs by the subvendor ID, which also has to be obtained
508 * from OFW instead of the PCI configuration space as the latter
509 * indicates Broadcom as the subvendor of the netboot interface.
510 * For early Blade 1500 and 2500 we even have to check the OFW
511 * device path as the subvendor ID always defaults to Broadcom
512 * there.
513 */
514 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
515 &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
516 subvendor == SUN_VENDORID)
517 return (0);
518 memset(buf, 0, sizeof(buf));
519 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
520 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
521 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
522 return (0);
523 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
524 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
525 return (0);
526 }
527 #endif
528 return (1);
529 }
530
531 static uint32_t
532 bge_readmem_ind(struct bge_softc *sc, int off)
533 {
534 device_t dev;
535 uint32_t val;
536
537 dev = sc->bge_dev;
538
539 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
540 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
541 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
542 return (val);
543 }
544
545 static void
546 bge_writemem_ind(struct bge_softc *sc, int off, int val)
547 {
548 device_t dev;
549
550 dev = sc->bge_dev;
551
552 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
553 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
554 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
555 }
556
557 /*
558 * PCI Express only
559 */
560 static void
561 bge_set_max_readrq(struct bge_softc *sc, int expr_ptr)
562 {
563 device_t dev;
564 uint16_t val;
565
566 KASSERT((sc->bge_flags & BGE_FLAG_PCIE) && expr_ptr != 0,
567 ("%s: not applicable", __func__));
568
569 dev = sc->bge_dev;
570
571 val = pci_read_config(dev, expr_ptr + BGE_PCIE_DEVCTL, 2);
572 if ((val & BGE_PCIE_DEVCTL_MAX_READRQ_MASK) !=
573 BGE_PCIE_DEVCTL_MAX_READRQ_4096) {
574 if (bootverbose)
575 device_printf(dev, "adjust device control 0x%04x ",
576 val);
577 val &= ~BGE_PCIE_DEVCTL_MAX_READRQ_MASK;
578 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096;
579 pci_write_config(dev, expr_ptr + BGE_PCIE_DEVCTL, val, 2);
580 if (bootverbose)
581 printf("-> 0x%04x\n", val);
582 }
583 }
584
585 #ifdef notdef
586 static uint32_t
587 bge_readreg_ind(struct bge_softc *sc, int off)
588 {
589 device_t dev;
590
591 dev = sc->bge_dev;
592
593 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
594 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
595 }
596 #endif
597
598 static void
599 bge_writereg_ind(struct bge_softc *sc, int off, int val)
600 {
601 device_t dev;
602
603 dev = sc->bge_dev;
604
605 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
606 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
607 }
608
609 static void
610 bge_writemem_direct(struct bge_softc *sc, int off, int val)
611 {
612 CSR_WRITE_4(sc, off, val);
613 }
614
615 static void
616 bge_writembx(struct bge_softc *sc, int off, int val)
617 {
618 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
619 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
620
621 CSR_WRITE_4(sc, off, val);
622 }
623
624 /*
625 * Map a single buffer address.
626 */
627
628 static void
629 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
630 {
631 struct bge_dmamap_arg *ctx;
632
633 if (error)
634 return;
635
636 ctx = arg;
637
638 if (nseg > ctx->bge_maxsegs) {
639 ctx->bge_maxsegs = 0;
640 return;
641 }
642
643 ctx->bge_busaddr = segs->ds_addr;
644 }
645
646 static uint8_t
647 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
648 {
649 uint32_t access, byte = 0;
650 int i;
651
652 /* Lock. */
653 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
654 for (i = 0; i < 8000; i++) {
655 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
656 break;
657 DELAY(20);
658 }
659 if (i == 8000)
660 return (1);
661
662 /* Enable access. */
663 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
664 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
665
666 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
667 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
668 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
669 DELAY(10);
670 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
671 DELAY(10);
672 break;
673 }
674 }
675
676 if (i == BGE_TIMEOUT * 10) {
677 if_printf(sc->bge_ifp, "nvram read timed out\n");
678 return (1);
679 }
680
681 /* Get result. */
682 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
683
684 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
685
686 /* Disable access. */
687 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
688
689 /* Unlock. */
690 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
691 CSR_READ_4(sc, BGE_NVRAM_SWARB);
692
693 return (0);
694 }
695
696 /*
697 * Read a sequence of bytes from NVRAM.
698 */
699 static int
700 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
701 {
702 int err = 0, i;
703 uint8_t byte = 0;
704
705 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
706 return (1);
707
708 for (i = 0; i < cnt; i++) {
709 err = bge_nvram_getbyte(sc, off + i, &byte);
710 if (err)
711 break;
712 *(dest + i) = byte;
713 }
714
715 return (err ? 1 : 0);
716 }
717
718 /*
719 * Read a byte of data stored in the EEPROM at address 'addr.' The
720 * BCM570x supports both the traditional bitbang interface and an
721 * auto access interface for reading the EEPROM. We use the auto
722 * access method.
723 */
724 static uint8_t
725 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
726 {
727 int i;
728 uint32_t byte = 0;
729
730 /*
731 * Enable use of auto EEPROM access so we can avoid
732 * having to use the bitbang method.
733 */
734 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
735
736 /* Reset the EEPROM, load the clock period. */
737 CSR_WRITE_4(sc, BGE_EE_ADDR,
738 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
739 DELAY(20);
740
741 /* Issue the read EEPROM command. */
742 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
743
744 /* Wait for completion */
745 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
746 DELAY(10);
747 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
748 break;
749 }
750
751 if (i == BGE_TIMEOUT * 10) {
752 device_printf(sc->bge_dev, "EEPROM read timed out\n");
753 return (1);
754 }
755
756 /* Get result. */
757 byte = CSR_READ_4(sc, BGE_EE_DATA);
758
759 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
760
761 return (0);
762 }
763
764 /*
765 * Read a sequence of bytes from the EEPROM.
766 */
767 static int
768 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
769 {
770 int i, error = 0;
771 uint8_t byte = 0;
772
773 for (i = 0; i < cnt; i++) {
774 error = bge_eeprom_getbyte(sc, off + i, &byte);
775 if (error)
776 break;
777 *(dest + i) = byte;
778 }
779
780 return (error ? 1 : 0);
781 }
782
783 static int
784 bge_miibus_readreg(device_t dev, int phy, int reg)
785 {
786 struct bge_softc *sc;
787 uint32_t val, autopoll;
788 int i;
789
790 sc = device_get_softc(dev);
791
792 /*
793 * Broadcom's own driver always assumes the internal
794 * PHY is at GMII address 1. On some chips, the PHY responds
795 * to accesses at all addresses, which could cause us to
796 * bogusly attach the PHY 32 times at probe type. Always
797 * restricting the lookup to address 1 is simpler than
798 * trying to figure out which chips revisions should be
799 * special-cased.
800 */
801 if (phy != 1)
802 return (0);
803
804 /* Reading with autopolling on may trigger PCI errors */
805 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
806 if (autopoll & BGE_MIMODE_AUTOPOLL) {
807 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
808 DELAY(40);
809 }
810
811 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
812 BGE_MIPHY(phy) | BGE_MIREG(reg));
813
814 for (i = 0; i < BGE_TIMEOUT; i++) {
815 DELAY(10);
816 val = CSR_READ_4(sc, BGE_MI_COMM);
817 if (!(val & BGE_MICOMM_BUSY))
818 break;
819 }
820
821 if (i == BGE_TIMEOUT) {
822 device_printf(sc->bge_dev,
823 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
824 phy, reg, val);
825 val = 0;
826 goto done;
827 }
828
829 DELAY(5);
830 val = CSR_READ_4(sc, BGE_MI_COMM);
831
832 done:
833 if (autopoll & BGE_MIMODE_AUTOPOLL) {
834 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
835 DELAY(40);
836 }
837
838 if (val & BGE_MICOMM_READFAIL)
839 return (0);
840
841 return (val & 0xFFFF);
842 }
843
844 static int
845 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
846 {
847 struct bge_softc *sc;
848 uint32_t autopoll;
849 int i;
850
851 sc = device_get_softc(dev);
852
853 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
854 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
855 return(0);
856
857 /* Reading with autopolling on may trigger PCI errors */
858 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
859 if (autopoll & BGE_MIMODE_AUTOPOLL) {
860 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
861 DELAY(40);
862 }
863
864 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
865 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
866
867 for (i = 0; i < BGE_TIMEOUT; i++) {
868 DELAY(10);
869 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
870 DELAY(5);
871 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
872 break;
873 }
874 }
875
876 if (i == BGE_TIMEOUT) {
877 device_printf(sc->bge_dev,
878 "PHY write timed out (phy %d, reg %d, val %d)\n",
879 phy, reg, val);
880 return (0);
881 }
882
883 if (autopoll & BGE_MIMODE_AUTOPOLL) {
884 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
885 DELAY(40);
886 }
887
888 return (0);
889 }
890
891 static void
892 bge_miibus_statchg(device_t dev)
893 {
894 struct bge_softc *sc;
895 struct mii_data *mii;
896 sc = device_get_softc(dev);
897 mii = device_get_softc(sc->bge_miibus);
898
899 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
900 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
901 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
902 else
903 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
904
905 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
906 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
907 else
908 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
909 }
910
911 /*
912 * Intialize a standard receive ring descriptor.
913 */
914 static int
915 bge_newbuf_std(struct bge_softc *sc, int i)
916 {
917 struct mbuf *m;
918 struct bge_rx_bd *r;
919 bus_dma_segment_t segs[1];
920 bus_dmamap_t map;
921 int error, nsegs;
922
923 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
924 if (m == NULL)
925 return (ENOBUFS);
926 m->m_len = m->m_pkthdr.len = MCLBYTES;
927 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
928 m_adj(m, ETHER_ALIGN);
929
930 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
931 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
932 if (error != 0) {
933 m_freem(m);
934 return (error);
935 }
936 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
937 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
938 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
939 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
940 sc->bge_cdata.bge_rx_std_dmamap[i]);
941 }
942 map = sc->bge_cdata.bge_rx_std_dmamap[i];
943 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
944 sc->bge_cdata.bge_rx_std_sparemap = map;
945 sc->bge_cdata.bge_rx_std_chain[i] = m;
946 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
947 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
948 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
949 r->bge_flags = BGE_RXBDFLAG_END;
950 r->bge_len = segs[0].ds_len;
951 r->bge_idx = i;
952
953 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
954 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
955
956 return (0);
957 }
958
959 /*
960 * Initialize a jumbo receive ring descriptor. This allocates
961 * a jumbo buffer from the pool managed internally by the driver.
962 */
963 static int
964 bge_newbuf_jumbo(struct bge_softc *sc, int i)
965 {
966 bus_dma_segment_t segs[BGE_NSEG_JUMBO];
967 bus_dmamap_t map;
968 struct bge_extrx_bd *r;
969 struct mbuf *m;
970 int error, nsegs;
971
972 MGETHDR(m, M_DONTWAIT, MT_DATA);
973 if (m == NULL)
974 return (ENOBUFS);
975
976 m_cljget(m, M_DONTWAIT, MJUM9BYTES);
977 if (!(m->m_flags & M_EXT)) {
978 m_freem(m);
979 return (ENOBUFS);
980 }
981 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
982 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
983 m_adj(m, ETHER_ALIGN);
984
985 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
986 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
987 if (error != 0) {
988 m_freem(m);
989 return (error);
990 }
991
992 if (sc->bge_cdata.bge_rx_jumbo_chain[i] == NULL) {
993 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
994 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
995 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
996 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
997 }
998 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
999 sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1000 sc->bge_cdata.bge_rx_jumbo_sparemap;
1001 sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1002 sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1003 /*
1004 * Fill in the extended RX buffer descriptor.
1005 */
1006 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1007 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1008 r->bge_idx = i;
1009 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1010 switch (nsegs) {
1011 case 4:
1012 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1013 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1014 r->bge_len3 = segs[3].ds_len;
1015 case 3:
1016 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1017 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1018 r->bge_len2 = segs[2].ds_len;
1019 case 2:
1020 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1021 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1022 r->bge_len1 = segs[1].ds_len;
1023 case 1:
1024 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1025 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1026 r->bge_len0 = segs[0].ds_len;
1027 break;
1028 default:
1029 panic("%s: %d segments\n", __func__, nsegs);
1030 }
1031
1032 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1033 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1034
1035 return (0);
1036 }
1037
1038 /*
1039 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1040 * that's 1MB or memory, which is a lot. For now, we fill only the first
1041 * 256 ring entries and hope that our CPU is fast enough to keep up with
1042 * the NIC.
1043 */
1044 static int
1045 bge_init_rx_ring_std(struct bge_softc *sc)
1046 {
1047 int error, i;
1048
1049 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1050 sc->bge_std = 0;
1051 for (i = 0; i < BGE_SSLOTS; i++) {
1052 if ((error = bge_newbuf_std(sc, i)) != 0)
1053 return (error);
1054 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1055 };
1056
1057 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1058 sc->bge_cdata.bge_rx_std_ring_map,
1059 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1060
1061 sc->bge_std = i - 1;
1062 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1063
1064 return (0);
1065 }
1066
1067 static void
1068 bge_free_rx_ring_std(struct bge_softc *sc)
1069 {
1070 int i;
1071
1072 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1073 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1074 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1075 sc->bge_cdata.bge_rx_std_dmamap[i],
1076 BUS_DMASYNC_POSTREAD);
1077 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1078 sc->bge_cdata.bge_rx_std_dmamap[i]);
1079 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1080 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1081 }
1082 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1083 sizeof(struct bge_rx_bd));
1084 }
1085 }
1086
1087 static int
1088 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1089 {
1090 struct bge_rcb *rcb;
1091 int error, i;
1092
1093 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1094 sc->bge_jumbo = 0;
1095 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1096 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1097 return (error);
1098 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1099 };
1100
1101 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1102 sc->bge_cdata.bge_rx_jumbo_ring_map,
1103 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1104
1105 sc->bge_jumbo = i - 1;
1106
1107 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1108 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1109 BGE_RCB_FLAG_USE_EXT_RX_BD);
1110 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1111
1112 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1113
1114 return (0);
1115 }
1116
1117 static void
1118 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1119 {
1120 int i;
1121
1122 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1123 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1124 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1125 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1126 BUS_DMASYNC_POSTREAD);
1127 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1128 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1129 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1130 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1131 }
1132 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1133 sizeof(struct bge_extrx_bd));
1134 }
1135 }
1136
1137 static void
1138 bge_free_tx_ring(struct bge_softc *sc)
1139 {
1140 int i;
1141
1142 if (sc->bge_ldata.bge_tx_ring == NULL)
1143 return;
1144
1145 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1146 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1147 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1148 sc->bge_cdata.bge_tx_dmamap[i],
1149 BUS_DMASYNC_POSTWRITE);
1150 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1151 sc->bge_cdata.bge_tx_dmamap[i]);
1152 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1153 sc->bge_cdata.bge_tx_chain[i] = NULL;
1154 }
1155 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1156 sizeof(struct bge_tx_bd));
1157 }
1158 }
1159
1160 static int
1161 bge_init_tx_ring(struct bge_softc *sc)
1162 {
1163 sc->bge_txcnt = 0;
1164 sc->bge_tx_saved_considx = 0;
1165
1166 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1167 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1168 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1169
1170 /* Initialize transmit producer index for host-memory send ring. */
1171 sc->bge_tx_prodidx = 0;
1172 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1173
1174 /* 5700 b2 errata */
1175 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1176 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1177
1178 /* NIC-memory send ring not used; initialize to zero. */
1179 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1180 /* 5700 b2 errata */
1181 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1182 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1183
1184 return (0);
1185 }
1186
1187 static void
1188 bge_setpromisc(struct bge_softc *sc)
1189 {
1190 struct ifnet *ifp;
1191
1192 BGE_LOCK_ASSERT(sc);
1193
1194 ifp = sc->bge_ifp;
1195
1196 /* Enable or disable promiscuous mode as needed. */
1197 if (ifp->if_flags & IFF_PROMISC)
1198 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1199 else
1200 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1201 }
1202
1203 static void
1204 bge_setmulti(struct bge_softc *sc)
1205 {
1206 struct ifnet *ifp;
1207 struct ifmultiaddr *ifma;
1208 uint32_t hashes[4] = { 0, 0, 0, 0 };
1209 int h, i;
1210
1211 BGE_LOCK_ASSERT(sc);
1212
1213 ifp = sc->bge_ifp;
1214
1215 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1216 for (i = 0; i < 4; i++)
1217 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1218 return;
1219 }
1220
1221 /* First, zot all the existing filters. */
1222 for (i = 0; i < 4; i++)
1223 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1224
1225 /* Now program new ones. */
1226 if_maddr_rlock(ifp);
1227 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1228 if (ifma->ifma_addr->sa_family != AF_LINK)
1229 continue;
1230 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1231 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1232 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1233 }
1234 if_maddr_runlock(ifp);
1235
1236 for (i = 0; i < 4; i++)
1237 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1238 }
1239
1240 static void
1241 bge_setvlan(struct bge_softc *sc)
1242 {
1243 struct ifnet *ifp;
1244
1245 BGE_LOCK_ASSERT(sc);
1246
1247 ifp = sc->bge_ifp;
1248
1249 /* Enable or disable VLAN tag stripping as needed. */
1250 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1251 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1252 else
1253 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1254 }
1255
1256 static void
1257 bge_sig_pre_reset(sc, type)
1258 struct bge_softc *sc;
1259 int type;
1260 {
1261 /*
1262 * Some chips don't like this so only do this if ASF is enabled
1263 */
1264 if (sc->bge_asf_mode)
1265 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1266
1267 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1268 switch (type) {
1269 case BGE_RESET_START:
1270 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1271 break;
1272 case BGE_RESET_STOP:
1273 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1274 break;
1275 }
1276 }
1277 }
1278
1279 static void
1280 bge_sig_post_reset(sc, type)
1281 struct bge_softc *sc;
1282 int type;
1283 {
1284 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1285 switch (type) {
1286 case BGE_RESET_START:
1287 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001);
1288 /* START DONE */
1289 break;
1290 case BGE_RESET_STOP:
1291 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002);
1292 break;
1293 }
1294 }
1295 }
1296
1297 static void
1298 bge_sig_legacy(sc, type)
1299 struct bge_softc *sc;
1300 int type;
1301 {
1302 if (sc->bge_asf_mode) {
1303 switch (type) {
1304 case BGE_RESET_START:
1305 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1306 break;
1307 case BGE_RESET_STOP:
1308 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1309 break;
1310 }
1311 }
1312 }
1313
1314 void bge_stop_fw(struct bge_softc *);
1315 void
1316 bge_stop_fw(sc)
1317 struct bge_softc *sc;
1318 {
1319 int i;
1320
1321 if (sc->bge_asf_mode) {
1322 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE);
1323 CSR_WRITE_4(sc, BGE_CPU_EVENT,
1324 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
1325
1326 for (i = 0; i < 100; i++ ) {
1327 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14)))
1328 break;
1329 DELAY(10);
1330 }
1331 }
1332 }
1333
1334 /*
1335 * Do endian, PCI and DMA initialization.
1336 */
1337 static int
1338 bge_chipinit(struct bge_softc *sc)
1339 {
1340 uint32_t dma_rw_ctl;
1341 int i;
1342
1343 /* Set endianness before we access any non-PCI registers. */
1344 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1345
1346 /* Clear the MAC control register */
1347 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1348
1349 /*
1350 * Clear the MAC statistics block in the NIC's
1351 * internal memory.
1352 */
1353 for (i = BGE_STATS_BLOCK;
1354 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1355 BGE_MEMWIN_WRITE(sc, i, 0);
1356
1357 for (i = BGE_STATUS_BLOCK;
1358 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1359 BGE_MEMWIN_WRITE(sc, i, 0);
1360
1361 /*
1362 * Set up the PCI DMA control register.
1363 */
1364 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1365 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1366 if (sc->bge_flags & BGE_FLAG_PCIE) {
1367 /* Read watermark not used, 128 bytes for write. */
1368 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1369 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1370 if (BGE_IS_5714_FAMILY(sc)) {
1371 /* 256 bytes for read and write. */
1372 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1373 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1374 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1375 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1376 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1377 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1378 /* 1536 bytes for read, 384 bytes for write. */
1379 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1380 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1381 } else {
1382 /* 384 bytes for read and write. */
1383 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1384 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1385 0x0F;
1386 }
1387 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1388 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1389 uint32_t tmp;
1390
1391 /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1392 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1393 if (tmp == 6 || tmp == 7)
1394 dma_rw_ctl |=
1395 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1396
1397 /* Set PCI-X DMA write workaround. */
1398 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1399 }
1400 } else {
1401 /* Conventional PCI bus: 256 bytes for read and write. */
1402 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1403 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1404
1405 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1406 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1407 dma_rw_ctl |= 0x0F;
1408 }
1409 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1410 sc->bge_asicrev == BGE_ASICREV_BCM5701)
1411 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1412 BGE_PCIDMARWCTL_ASRT_ALL_BE;
1413 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1414 sc->bge_asicrev == BGE_ASICREV_BCM5704)
1415 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1416 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1417
1418 /*
1419 * Set up general mode register.
1420 */
1421 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
1422 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1423 BGE_MODECTL_TX_NO_PHDR_CSUM);
1424
1425 /*
1426 * BCM5701 B5 have a bug causing data corruption when using
1427 * 64-bit DMA reads, which can be terminated early and then
1428 * completed later as 32-bit accesses, in combination with
1429 * certain bridges.
1430 */
1431 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1432 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1433 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1434
1435 /*
1436 * Tell the firmware the driver is running
1437 */
1438 if (sc->bge_asf_mode & ASF_STACKUP)
1439 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
1440
1441 /*
1442 * Disable memory write invalidate. Apparently it is not supported
1443 * properly by these devices. Also ensure that INTx isn't disabled,
1444 * as these chips need it even when using MSI.
1445 */
1446 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1447 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4);
1448
1449 /* Set the timer prescaler (always 66Mhz) */
1450 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1451
1452 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1453 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1454 DELAY(40); /* XXX */
1455
1456 /* Put PHY into ready state */
1457 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1458 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1459 DELAY(40);
1460 }
1461
1462 return (0);
1463 }
1464
1465 static int
1466 bge_blockinit(struct bge_softc *sc)
1467 {
1468 struct bge_rcb *rcb;
1469 bus_size_t vrcb;
1470 bge_hostaddr taddr;
1471 uint32_t val;
1472 int i;
1473
1474 /*
1475 * Initialize the memory window pointer register so that
1476 * we can access the first 32K of internal NIC RAM. This will
1477 * allow us to set up the TX send ring RCBs and the RX return
1478 * ring RCBs, plus other things which live in NIC memory.
1479 */
1480 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1481
1482 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1483
1484 if (!(BGE_IS_5705_PLUS(sc))) {
1485 /* Configure mbuf memory pool */
1486 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1487 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1488 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1489 else
1490 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1491
1492 /* Configure DMA resource pool */
1493 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1494 BGE_DMA_DESCRIPTORS);
1495 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1496 }
1497
1498 /* Configure mbuf pool watermarks */
1499 if (!BGE_IS_5705_PLUS(sc)) {
1500 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1501 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1502 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1503 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1504 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1505 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1506 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1507 } else {
1508 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1509 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1510 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1511 }
1512
1513 /* Configure DMA resource watermarks */
1514 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1515 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1516
1517 /* Enable buffer manager */
1518 if (!(BGE_IS_5705_PLUS(sc))) {
1519 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1520 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN);
1521
1522 /* Poll for buffer manager start indication */
1523 for (i = 0; i < BGE_TIMEOUT; i++) {
1524 DELAY(10);
1525 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1526 break;
1527 }
1528
1529 if (i == BGE_TIMEOUT) {
1530 device_printf(sc->bge_dev,
1531 "buffer manager failed to start\n");
1532 return (ENXIO);
1533 }
1534 }
1535
1536 /* Enable flow-through queues */
1537 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1538 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1539
1540 /* Wait until queue initialization is complete */
1541 for (i = 0; i < BGE_TIMEOUT; i++) {
1542 DELAY(10);
1543 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1544 break;
1545 }
1546
1547 if (i == BGE_TIMEOUT) {
1548 device_printf(sc->bge_dev, "flow-through queue init failed\n");
1549 return (ENXIO);
1550 }
1551
1552 /* Initialize the standard RX ring control block */
1553 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1554 rcb->bge_hostaddr.bge_addr_lo =
1555 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1556 rcb->bge_hostaddr.bge_addr_hi =
1557 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1558 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1559 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1560 if (BGE_IS_5705_PLUS(sc))
1561 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1562 else
1563 rcb->bge_maxlen_flags =
1564 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1565 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1566 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1567 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1568
1569 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1570 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1571
1572 /*
1573 * Initialize the jumbo RX ring control block
1574 * We set the 'ring disabled' bit in the flags
1575 * field until we're actually ready to start
1576 * using this ring (i.e. once we set the MTU
1577 * high enough to require it).
1578 */
1579 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1580 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1581
1582 rcb->bge_hostaddr.bge_addr_lo =
1583 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1584 rcb->bge_hostaddr.bge_addr_hi =
1585 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1586 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1587 sc->bge_cdata.bge_rx_jumbo_ring_map,
1588 BUS_DMASYNC_PREREAD);
1589 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1590 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
1591 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1592 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1593 rcb->bge_hostaddr.bge_addr_hi);
1594 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1595 rcb->bge_hostaddr.bge_addr_lo);
1596
1597 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1598 rcb->bge_maxlen_flags);
1599 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1600
1601 /* Set up dummy disabled mini ring RCB */
1602 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1603 rcb->bge_maxlen_flags =
1604 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1605 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1606 rcb->bge_maxlen_flags);
1607 }
1608
1609 /*
1610 * Set the BD ring replentish thresholds. The recommended
1611 * values are 1/8th the number of descriptors allocated to
1612 * each ring.
1613 * XXX The 5754 requires a lower threshold, so it might be a
1614 * requirement of all 575x family chips. The Linux driver sets
1615 * the lower threshold for all 5705 family chips as well, but there
1616 * are reports that it might not need to be so strict.
1617 *
1618 * XXX Linux does some extra fiddling here for the 5906 parts as
1619 * well.
1620 */
1621 if (BGE_IS_5705_PLUS(sc))
1622 val = 8;
1623 else
1624 val = BGE_STD_RX_RING_CNT / 8;
1625 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1626 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1627
1628 /*
1629 * Disable all unused send rings by setting the 'ring disabled'
1630 * bit in the flags field of all the TX send ring control blocks.
1631 * These are located in NIC memory.
1632 */
1633 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1634 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1635 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1636 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1637 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1638 vrcb += sizeof(struct bge_rcb);
1639 }
1640
1641 /* Configure TX RCB 0 (we use only the first ring) */
1642 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1643 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1644 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1645 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1646 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1647 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1648 if (!(BGE_IS_5705_PLUS(sc)))
1649 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1650 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1651
1652 /* Disable all unused RX return rings */
1653 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1654 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1655 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1656 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1657 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1658 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1659 BGE_RCB_FLAG_RING_DISABLED));
1660 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1661 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1662 (i * (sizeof(uint64_t))), 0);
1663 vrcb += sizeof(struct bge_rcb);
1664 }
1665
1666 /* Initialize RX ring indexes */
1667 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1668 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1669 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1670
1671 /*
1672 * Set up RX return ring 0
1673 * Note that the NIC address for RX return rings is 0x00000000.
1674 * The return rings live entirely within the host, so the
1675 * nicaddr field in the RCB isn't used.
1676 */
1677 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1678 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1679 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1680 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1681 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1682 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1683 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1684
1685 /* Set random backoff seed for TX */
1686 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1687 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1688 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1689 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1690 BGE_TX_BACKOFF_SEED_MASK);
1691
1692 /* Set inter-packet gap */
1693 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1694
1695 /*
1696 * Specify which ring to use for packets that don't match
1697 * any RX rules.
1698 */
1699 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1700
1701 /*
1702 * Configure number of RX lists. One interrupt distribution
1703 * list, sixteen active lists, one bad frames class.
1704 */
1705 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1706
1707 /* Inialize RX list placement stats mask. */
1708 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1709 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1710
1711 /* Disable host coalescing until we get it set up */
1712 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1713
1714 /* Poll to make sure it's shut down. */
1715 for (i = 0; i < BGE_TIMEOUT; i++) {
1716 DELAY(10);
1717 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1718 break;
1719 }
1720
1721 if (i == BGE_TIMEOUT) {
1722 device_printf(sc->bge_dev,
1723 "host coalescing engine failed to idle\n");
1724 return (ENXIO);
1725 }
1726
1727 /* Set up host coalescing defaults */
1728 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1729 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1730 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1731 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1732 if (!(BGE_IS_5705_PLUS(sc))) {
1733 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1734 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1735 }
1736 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1737 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1738
1739 /* Set up address of statistics block */
1740 if (!(BGE_IS_5705_PLUS(sc))) {
1741 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1742 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1743 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1744 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1745 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1746 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1747 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1748 }
1749
1750 /* Set up address of status block */
1751 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1752 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1753 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1754 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1755 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1756 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1757
1758 /* Turn on host coalescing state machine */
1759 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1760
1761 /* Turn on RX BD completion state machine and enable attentions */
1762 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1763 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
1764
1765 /* Turn on RX list placement state machine */
1766 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1767
1768 /* Turn on RX list selector state machine. */
1769 if (!(BGE_IS_5705_PLUS(sc)))
1770 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1771
1772 /* Turn on DMA, clear stats */
1773 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB |
1774 BGE_MACMODE_RXDMA_ENB | BGE_MACMODE_RX_STATS_CLEAR |
1775 BGE_MACMODE_TX_STATS_CLEAR | BGE_MACMODE_RX_STATS_ENB |
1776 BGE_MACMODE_TX_STATS_ENB | BGE_MACMODE_FRMHDR_DMA_ENB |
1777 ((sc->bge_flags & BGE_FLAG_TBI) ?
1778 BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1779
1780 /* Set misc. local control, enable interrupts on attentions */
1781 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1782
1783 #ifdef notdef
1784 /* Assert GPIO pins for PHY reset */
1785 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
1786 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
1787 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
1788 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
1789 #endif
1790
1791 /* Turn on DMA completion state machine */
1792 if (!(BGE_IS_5705_PLUS(sc)))
1793 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1794
1795 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
1796
1797 /* Enable host coalescing bug fix. */
1798 if (BGE_IS_5755_PLUS(sc))
1799 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1800
1801 /* Turn on write DMA state machine */
1802 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1803 DELAY(40);
1804
1805 /* Turn on read DMA state machine */
1806 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1807 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1808 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1809 sc->bge_asicrev == BGE_ASICREV_BCM57780)
1810 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1811 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1812 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1813 if (sc->bge_flags & BGE_FLAG_PCIE)
1814 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1815 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1816 DELAY(40);
1817
1818 /* Turn on RX data completion state machine */
1819 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1820
1821 /* Turn on RX BD initiator state machine */
1822 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1823
1824 /* Turn on RX data and RX BD initiator state machine */
1825 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1826
1827 /* Turn on Mbuf cluster free state machine */
1828 if (!(BGE_IS_5705_PLUS(sc)))
1829 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1830
1831 /* Turn on send BD completion state machine */
1832 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1833
1834 /* Turn on send data completion state machine */
1835 val = BGE_SDCMODE_ENABLE;
1836 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1837 val |= BGE_SDCMODE_CDELAY;
1838 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1839
1840 /* Turn on send data initiator state machine */
1841 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1842
1843 /* Turn on send BD initiator state machine */
1844 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1845
1846 /* Turn on send BD selector state machine */
1847 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1848
1849 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1850 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1851 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
1852
1853 /* ack/clear link change events */
1854 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1855 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1856 BGE_MACSTAT_LINK_CHANGED);
1857 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1858
1859 /* Enable PHY auto polling (for MII/GMII only) */
1860 if (sc->bge_flags & BGE_FLAG_TBI) {
1861 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1862 } else {
1863 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16));
1864 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1865 sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
1866 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1867 BGE_EVTENB_MI_INTERRUPT);
1868 }
1869
1870 /*
1871 * Clear any pending link state attention.
1872 * Otherwise some link state change events may be lost until attention
1873 * is cleared by bge_intr() -> bge_link_upd() sequence.
1874 * It's not necessary on newer BCM chips - perhaps enabling link
1875 * state change attentions implies clearing pending attention.
1876 */
1877 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1878 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1879 BGE_MACSTAT_LINK_CHANGED);
1880
1881 /* Enable link state change attentions. */
1882 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1883
1884 return (0);
1885 }
1886
1887 const struct bge_revision *
1888 bge_lookup_rev(uint32_t chipid)
1889 {
1890 const struct bge_revision *br;
1891
1892 for (br = bge_revisions; br->br_name != NULL; br++) {
1893 if (br->br_chipid == chipid)
1894 return (br);
1895 }
1896
1897 for (br = bge_majorrevs; br->br_name != NULL; br++) {
1898 if (br->br_chipid == BGE_ASICREV(chipid))
1899 return (br);
1900 }
1901
1902 return (NULL);
1903 }
1904
1905 const struct bge_vendor *
1906 bge_lookup_vendor(uint16_t vid)
1907 {
1908 const struct bge_vendor *v;
1909
1910 for (v = bge_vendors; v->v_name != NULL; v++)
1911 if (v->v_id == vid)
1912 return (v);
1913
1914 panic("%s: unknown vendor %d", __func__, vid);
1915 return (NULL);
1916 }
1917
1918 /*
1919 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1920 * against our list and return its name if we find a match.
1921 *
1922 * Note that since the Broadcom controller contains VPD support, we
1923 * try to get the device name string from the controller itself instead
1924 * of the compiled-in string. It guarantees we'll always announce the
1925 * right product name. We fall back to the compiled-in string when
1926 * VPD is unavailable or corrupt.
1927 */
1928 static int
1929 bge_probe(device_t dev)
1930 {
1931 const struct bge_type *t = bge_devs;
1932 struct bge_softc *sc = device_get_softc(dev);
1933 uint16_t vid, did;
1934
1935 sc->bge_dev = dev;
1936 vid = pci_get_vendor(dev);
1937 did = pci_get_device(dev);
1938 while(t->bge_vid != 0) {
1939 if ((vid == t->bge_vid) && (did == t->bge_did)) {
1940 char model[64], buf[96];
1941 const struct bge_revision *br;
1942 const struct bge_vendor *v;
1943 uint32_t id;
1944
1945 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1946 BGE_PCIMISCCTL_ASICREV_SHIFT;
1947 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG)
1948 id = pci_read_config(dev,
1949 BGE_PCI_PRODID_ASICREV, 4);
1950 br = bge_lookup_rev(id);
1951 v = bge_lookup_vendor(vid);
1952 {
1953 #if __FreeBSD_version > 700024
1954 const char *pname;
1955
1956 if (bge_has_eaddr(sc) &&
1957 pci_get_vpd_ident(dev, &pname) == 0)
1958 snprintf(model, 64, "%s", pname);
1959 else
1960 #endif
1961 snprintf(model, 64, "%s %s",
1962 v->v_name,
1963 br != NULL ? br->br_name :
1964 "NetXtreme Ethernet Controller");
1965 }
1966 snprintf(buf, 96, "%s, %sASIC rev. %#08x", model,
1967 br != NULL ? "" : "unknown ", id);
1968 device_set_desc_copy(dev, buf);
1969 if (pci_get_subvendor(dev) == DELL_VENDORID)
1970 sc->bge_flags |= BGE_FLAG_NO_3LED;
1971 if (did == BCOM_DEVICEID_BCM5755M)
1972 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1973 return (0);
1974 }
1975 t++;
1976 }
1977
1978 return (ENXIO);
1979 }
1980
1981 static void
1982 bge_dma_free(struct bge_softc *sc)
1983 {
1984 int i;
1985
1986 /* Destroy DMA maps for RX buffers. */
1987 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1988 if (sc->bge_cdata.bge_rx_std_dmamap[i])
1989 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
1990 sc->bge_cdata.bge_rx_std_dmamap[i]);
1991 }
1992 if (sc->bge_cdata.bge_rx_std_sparemap)
1993 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
1994 sc->bge_cdata.bge_rx_std_sparemap);
1995
1996 /* Destroy DMA maps for jumbo RX buffers. */
1997 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1998 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
1999 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2000 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2001 }
2002 if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2003 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2004 sc->bge_cdata.bge_rx_jumbo_sparemap);
2005
2006 /* Destroy DMA maps for TX buffers. */
2007 for (i = 0; i < BGE_TX_RING_CNT; i++) {
2008 if (sc->bge_cdata.bge_tx_dmamap[i])
2009 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2010 sc->bge_cdata.bge_tx_dmamap[i]);
2011 }
2012
2013 if (sc->bge_cdata.bge_rx_mtag)
2014 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2015 if (sc->bge_cdata.bge_tx_mtag)
2016 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2017
2018
2019 /* Destroy standard RX ring. */
2020 if (sc->bge_cdata.bge_rx_std_ring_map)
2021 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2022 sc->bge_cdata.bge_rx_std_ring_map);
2023 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
2024 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2025 sc->bge_ldata.bge_rx_std_ring,
2026 sc->bge_cdata.bge_rx_std_ring_map);
2027
2028 if (sc->bge_cdata.bge_rx_std_ring_tag)
2029 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2030
2031 /* Destroy jumbo RX ring. */
2032 if (sc->bge_cdata.bge_rx_jumbo_ring_map)
2033 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2034 sc->bge_cdata.bge_rx_jumbo_ring_map);
2035
2036 if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
2037 sc->bge_ldata.bge_rx_jumbo_ring)
2038 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2039 sc->bge_ldata.bge_rx_jumbo_ring,
2040 sc->bge_cdata.bge_rx_jumbo_ring_map);
2041
2042 if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2043 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2044
2045 /* Destroy RX return ring. */
2046 if (sc->bge_cdata.bge_rx_return_ring_map)
2047 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2048 sc->bge_cdata.bge_rx_return_ring_map);
2049
2050 if (sc->bge_cdata.bge_rx_return_ring_map &&
2051 sc->bge_ldata.bge_rx_return_ring)
2052 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2053 sc->bge_ldata.bge_rx_return_ring,
2054 sc->bge_cdata.bge_rx_return_ring_map);
2055
2056 if (sc->bge_cdata.bge_rx_return_ring_tag)
2057 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2058
2059 /* Destroy TX ring. */
2060 if (sc->bge_cdata.bge_tx_ring_map)
2061 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2062 sc->bge_cdata.bge_tx_ring_map);
2063
2064 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
2065 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2066 sc->bge_ldata.bge_tx_ring,
2067 sc->bge_cdata.bge_tx_ring_map);
2068
2069 if (sc->bge_cdata.bge_tx_ring_tag)
2070 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2071
2072 /* Destroy status block. */
2073 if (sc->bge_cdata.bge_status_map)
2074 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2075 sc->bge_cdata.bge_status_map);
2076
2077 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
2078 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2079 sc->bge_ldata.bge_status_block,
2080 sc->bge_cdata.bge_status_map);
2081
2082 if (sc->bge_cdata.bge_status_tag)
2083 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2084
2085 /* Destroy statistics block. */
2086 if (sc->bge_cdata.bge_stats_map)
2087 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2088 sc->bge_cdata.bge_stats_map);
2089
2090 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2091 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2092 sc->bge_ldata.bge_stats,
2093 sc->bge_cdata.bge_stats_map);
2094
2095 if (sc->bge_cdata.bge_stats_tag)
2096 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2097
2098 /* Destroy the parent tag. */
2099 if (sc->bge_cdata.bge_parent_tag)
2100 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2101 }
2102
2103 static int
2104 bge_dma_alloc(device_t dev)
2105 {
2106 struct bge_dmamap_arg ctx;
2107 struct bge_softc *sc;
2108 int i, error;
2109
2110 sc = device_get_softc(dev);
2111
2112 /*
2113 * Allocate the parent bus DMA tag appropriate for PCI.
2114 */
2115 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2116 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2117 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2118 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2119
2120 if (error != 0) {
2121 device_printf(sc->bge_dev,
2122 "could not allocate parent dma tag\n");
2123 return (ENOMEM);
2124 }
2125
2126 /*
2127 * Create tag for Tx mbufs.
2128 */
2129 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1,
2130 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2131 NULL, MCLBYTES * BGE_NSEG_NEW, BGE_NSEG_NEW, MCLBYTES,
2132 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->bge_cdata.bge_tx_mtag);
2133
2134 if (error) {
2135 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
2136 return (ENOMEM);
2137 }
2138
2139 /*
2140 * Create tag for Rx mbufs.
2141 */
2142 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
2143 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
2144 MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
2145
2146 if (error) {
2147 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
2148 return (ENOMEM);
2149 }
2150
2151 /* Create DMA maps for RX buffers. */
2152 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2153 &sc->bge_cdata.bge_rx_std_sparemap);
2154 if (error) {
2155 device_printf(sc->bge_dev,
2156 "can't create spare DMA map for RX\n");
2157 return (ENOMEM);
2158 }
2159 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2160 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2161 &sc->bge_cdata.bge_rx_std_dmamap[i]);
2162 if (error) {
2163 device_printf(sc->bge_dev,
2164 "can't create DMA map for RX\n");
2165 return (ENOMEM);
2166 }
2167 }
2168
2169 /* Create DMA maps for TX buffers. */
2170 for (i = 0; i < BGE_TX_RING_CNT; i++) {
2171 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
2172 &sc->bge_cdata.bge_tx_dmamap[i]);
2173 if (error) {
2174 device_printf(sc->bge_dev,
2175 "can't create DMA map for TX\n");
2176 return (ENOMEM);
2177 }
2178 }
2179
2180 /* Create tag for standard RX ring. */
2181 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2182 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2183 NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0,
2184 NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag);
2185
2186 if (error) {
2187 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2188 return (ENOMEM);
2189 }
2190
2191 /* Allocate DMA'able memory for standard RX ring. */
2192 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag,
2193 (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT,
2194 &sc->bge_cdata.bge_rx_std_ring_map);
2195 if (error)
2196 return (ENOMEM);
2197
2198 bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
2199
2200 /* Load the address of the standard RX ring. */
2201 ctx.bge_maxsegs = 1;
2202 ctx.sc = sc;
2203
2204 error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag,
2205 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring,
2206 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2207
2208 if (error)
2209 return (ENOMEM);
2210
2211 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr;
2212
2213 /* Create tags for jumbo mbufs. */
2214 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2215 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2216 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2217 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
2218 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
2219 if (error) {
2220 device_printf(sc->bge_dev,
2221 "could not allocate jumbo dma tag\n");
2222 return (ENOMEM);
2223 }
2224
2225 /* Create tag for jumbo RX ring. */
2226 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2227 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2228 NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0,
2229 NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag);
2230
2231 if (error) {
2232 device_printf(sc->bge_dev,
2233 "could not allocate jumbo ring dma tag\n");
2234 return (ENOMEM);
2235 }
2236
2237 /* Allocate DMA'able memory for jumbo RX ring. */
2238 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2239 (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
2240 BUS_DMA_NOWAIT | BUS_DMA_ZERO,
2241 &sc->bge_cdata.bge_rx_jumbo_ring_map);
2242 if (error)
2243 return (ENOMEM);
2244
2245 /* Load the address of the jumbo RX ring. */
2246 ctx.bge_maxsegs = 1;
2247 ctx.sc = sc;
2248
2249 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2250 sc->bge_cdata.bge_rx_jumbo_ring_map,
2251 sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ,
2252 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2253
2254 if (error)
2255 return (ENOMEM);
2256
2257 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr;
2258
2259 /* Create DMA maps for jumbo RX buffers. */
2260 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2261 0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
2262 if (error) {
2263 device_printf(sc->bge_dev,
2264 "can't create sapre DMA map for jumbo RX\n");
2265 return (ENOMEM);
2266 }
2267 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2268 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2269 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2270 if (error) {
2271 device_printf(sc->bge_dev,
2272 "can't create DMA map for jumbo RX\n");
2273 return (ENOMEM);
2274 }
2275 }
2276
2277 }
2278
2279 /* Create tag for RX return ring. */
2280 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2281 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2282 NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0,
2283 NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag);
2284
2285 if (error) {
2286 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2287 return (ENOMEM);
2288 }
2289
2290 /* Allocate DMA'able memory for RX return ring. */
2291 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag,
2292 (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT,
2293 &sc->bge_cdata.bge_rx_return_ring_map);
2294 if (error)
2295 return (ENOMEM);
2296
2297 bzero((char *)sc->bge_ldata.bge_rx_return_ring,
2298 BGE_RX_RTN_RING_SZ(sc));
2299
2300 /* Load the address of the RX return ring. */
2301 ctx.bge_maxsegs = 1;
2302 ctx.sc = sc;
2303
2304 error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag,
2305 sc->bge_cdata.bge_rx_return_ring_map,
2306 sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc),
2307 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2308
2309 if (error)
2310 return (ENOMEM);
2311
2312 sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr;
2313
2314 /* Create tag for TX ring. */
2315 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2316 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2317 NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL,
2318 &sc->bge_cdata.bge_tx_ring_tag);
2319
2320 if (error) {
2321 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2322 return (ENOMEM);
2323 }
2324
2325 /* Allocate DMA'able memory for TX ring. */
2326 error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag,
2327 (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT,
2328 &sc->bge_cdata.bge_tx_ring_map);
2329 if (error)
2330 return (ENOMEM);
2331
2332 bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
2333
2334 /* Load the address of the TX ring. */
2335 ctx.bge_maxsegs = 1;
2336 ctx.sc = sc;
2337
2338 error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag,
2339 sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring,
2340 BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2341
2342 if (error)
2343 return (ENOMEM);
2344
2345 sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr;
2346
2347 /* Create tag for status block. */
2348 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2349 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2350 NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0,
2351 NULL, NULL, &sc->bge_cdata.bge_status_tag);
2352
2353 if (error) {
2354 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2355 return (ENOMEM);
2356 }
2357
2358 /* Allocate DMA'able memory for status block. */
2359 error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag,
2360 (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT,
2361 &sc->bge_cdata.bge_status_map);
2362 if (error)
2363 return (ENOMEM);
2364
2365 bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2366
2367 /* Load the address of the status block. */
2368 ctx.sc = sc;
2369 ctx.bge_maxsegs = 1;
2370
2371 error = bus_dmamap_load(sc->bge_cdata.bge_status_tag,
2372 sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block,
2373 BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2374
2375 if (error)
2376 return (ENOMEM);
2377
2378 sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr;
2379
2380 /* Create tag for statistics block. */
2381 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2382 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2383 NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL,
2384 &sc->bge_cdata.bge_stats_tag);
2385
2386 if (error) {
2387 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2388 return (ENOMEM);
2389 }
2390
2391 /* Allocate DMA'able memory for statistics block. */
2392 error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag,
2393 (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT,
2394 &sc->bge_cdata.bge_stats_map);
2395 if (error)
2396 return (ENOMEM);
2397
2398 bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ);
2399
2400 /* Load the address of the statstics block. */
2401 ctx.sc = sc;
2402 ctx.bge_maxsegs = 1;
2403
2404 error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag,
2405 sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats,
2406 BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2407
2408 if (error)
2409 return (ENOMEM);
2410
2411 sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr;
2412
2413 return (0);
2414 }
2415
2416 #if __FreeBSD_version > 602105
2417 /*
2418 * Return true if this device has more than one port.
2419 */
2420 static int
2421 bge_has_multiple_ports(struct bge_softc *sc)
2422 {
2423 device_t dev = sc->bge_dev;
2424 u_int b, d, f, fscan, s;
2425
2426 d = pci_get_domain(dev);
2427 b = pci_get_bus(dev);
2428 s = pci_get_slot(dev);
2429 f = pci_get_function(dev);
2430 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
2431 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
2432 return (1);
2433 return (0);
2434 }
2435
2436 /*
2437 * Return true if MSI can be used with this device.
2438 */
2439 static int
2440 bge_can_use_msi(struct bge_softc *sc)
2441 {
2442 int can_use_msi = 0;
2443
2444 switch (sc->bge_asicrev) {
2445 case BGE_ASICREV_BCM5714_A0:
2446 case BGE_ASICREV_BCM5714:
2447 /*
2448 * Apparently, MSI doesn't work when these chips are
2449 * configured in single-port mode.
2450 */
2451 if (bge_has_multiple_ports(sc))
2452 can_use_msi = 1;
2453 break;
2454 case BGE_ASICREV_BCM5750:
2455 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
2456 sc->bge_chiprev != BGE_CHIPREV_5750_BX)
2457 can_use_msi = 1;
2458 break;
2459 default:
2460 if (BGE_IS_575X_PLUS(sc))
2461 can_use_msi = 1;
2462 }
2463 return (can_use_msi);
2464 }
2465 #endif
2466
2467 static int
2468 bge_attach(device_t dev)
2469 {
2470 struct ifnet *ifp;
2471 struct bge_softc *sc;
2472 uint32_t hwcfg = 0, misccfg;
2473 u_char eaddr[ETHER_ADDR_LEN];
2474 int error, reg, rid, trys;
2475
2476 sc = device_get_softc(dev);
2477 sc->bge_dev = dev;
2478
2479 /*
2480 * Map control/status registers.
2481 */
2482 pci_enable_busmaster(dev);
2483
2484 rid = BGE_PCI_BAR0;
2485 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2486 RF_ACTIVE);
2487
2488 if (sc->bge_res == NULL) {
2489 device_printf (sc->bge_dev, "couldn't map memory\n");
2490 error = ENXIO;
2491 goto fail;
2492 }
2493
2494 /* Save various chip information. */
2495 sc->bge_chipid =
2496 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2497 BGE_PCIMISCCTL_ASICREV_SHIFT;
2498 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
2499 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV,
2500 4);
2501 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2502 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2503
2504 /*
2505 * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the
2506 * 5705 A0 and A1 chips.
2507 */
2508 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
2509 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2510 sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2511 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)
2512 sc->bge_flags |= BGE_FLAG_WIRESPEED;
2513
2514 if (bge_has_eaddr(sc))
2515 sc->bge_flags |= BGE_FLAG_EADDR;
2516
2517 /* Save chipset family. */
2518 switch (sc->bge_asicrev) {
2519 case BGE_ASICREV_BCM5755:
2520 case BGE_ASICREV_BCM5761:
2521 case BGE_ASICREV_BCM5784:
2522 case BGE_ASICREV_BCM5785:
2523 case BGE_ASICREV_BCM5787:
2524 case BGE_ASICREV_BCM57780:
2525 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2526 BGE_FLAG_5705_PLUS;
2527 break;
2528 case BGE_ASICREV_BCM5700:
2529 case BGE_ASICREV_BCM5701:
2530 case BGE_ASICREV_BCM5703:
2531 case BGE_ASICREV_BCM5704:
2532 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2533 break;
2534 case BGE_ASICREV_BCM5714_A0:
2535 case BGE_ASICREV_BCM5780:
2536 case BGE_ASICREV_BCM5714:
2537 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */;
2538 /* FALLTHROUGH */
2539 case BGE_ASICREV_BCM5750:
2540 case BGE_ASICREV_BCM5752:
2541 case BGE_ASICREV_BCM5906:
2542 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2543 /* FALLTHROUGH */
2544 case BGE_ASICREV_BCM5705:
2545 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2546 break;
2547 }
2548
2549 /* Set various bug flags. */
2550 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2551 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2552 sc->bge_flags |= BGE_FLAG_CRC_BUG;
2553 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2554 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2555 sc->bge_flags |= BGE_FLAG_ADC_BUG;
2556 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2557 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
2558 if (BGE_IS_5705_PLUS(sc) &&
2559 !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) {
2560 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2561 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2562 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2563 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2564 if (sc->bge_chipid != BGE_CHIPID_BCM5722_A0)
2565 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
2566 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
2567 sc->bge_flags |= BGE_FLAG_BER_BUG;
2568 }
2569
2570
2571 /*
2572 * We could possibly check for BCOM_DEVICEID_BCM5788 in bge_probe()
2573 * but I do not know the DEVICEID for the 5788M.
2574 */
2575 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID;
2576 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2577 misccfg == BGE_MISCCFG_BOARD_ID_5788M)
2578 sc->bge_flags |= BGE_FLAG_5788;
2579
2580 /*
2581 * Check if this is a PCI-X or PCI Express device.
2582 */
2583 #if __FreeBSD_version > 602101
2584 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
2585 /*
2586 * Found a PCI Express capabilities register, this
2587 * must be a PCI Express device.
2588 */
2589 if (reg != 0) {
2590 sc->bge_flags |= BGE_FLAG_PCIE;
2591 #else
2592 if (BGE_IS_5705_PLUS(sc)) {
2593 reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
2594 if ((reg & 0xFF) == BGE_PCIE_CAPID) {
2595 sc->bge_flags |= BGE_FLAG_PCIE;
2596 reg = BGE_PCIE_CAPID;
2597 #endif
2598 bge_set_max_readrq(sc, reg);
2599 }
2600 } else {
2601 /*
2602 * Check if the device is in PCI-X Mode.
2603 * (This bit is not valid on PCI Express controllers.)
2604 */
2605 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
2606 BGE_PCISTATE_PCI_BUSMODE) == 0)
2607 sc->bge_flags |= BGE_FLAG_PCIX;
2608 }
2609
2610 #if __FreeBSD_version > 602105
2611 {
2612 int msicount;
2613
2614 /*
2615 * Allocate the interrupt, using MSI if possible. These devices
2616 * support 8 MSI messages, but only the first one is used in
2617 * normal operation.
2618 */
2619 if (bge_can_use_msi(sc)) {
2620 msicount = pci_msi_count(dev);
2621 if (msicount > 1)
2622 msicount = 1;
2623 } else
2624 msicount = 0;
2625 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
2626 rid = 1;
2627 sc->bge_flags |= BGE_FLAG_MSI;
2628 } else
2629 rid = 0;
2630 }
2631 #else
2632 rid = 0;
2633 #endif
2634
2635 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2636 RF_SHAREABLE | RF_ACTIVE);
2637
2638 if (sc->bge_irq == NULL) {
2639 device_printf(sc->bge_dev, "couldn't map interrupt\n");
2640 error = ENXIO;
2641 goto fail;
2642 }
2643
2644 if (bootverbose)
2645 device_printf(dev,
2646 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2647 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2648 (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" :
2649 ((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI"));
2650
2651 BGE_LOCK_INIT(sc, device_get_nameunit(dev));
2652
2653 /* Try to reset the chip. */
2654 if (bge_reset(sc)) {
2655 device_printf(sc->bge_dev, "chip reset failed\n");
2656 error = ENXIO;
2657 goto fail;
2658 }
2659
2660 sc->bge_asf_mode = 0;
2661 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG)
2662 == BGE_MAGIC_NUMBER)) {
2663 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG)
2664 & BGE_HWCFG_ASF) {
2665 sc->bge_asf_mode |= ASF_ENABLE;
2666 sc->bge_asf_mode |= ASF_STACKUP;
2667 if (sc->bge_asicrev == BGE_ASICREV_BCM5750) {
2668 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
2669 }
2670 }
2671 }
2672
2673 /* Try to reset the chip again the nice way. */
2674 bge_stop_fw(sc);
2675 bge_sig_pre_reset(sc, BGE_RESET_STOP);
2676 if (bge_reset(sc)) {
2677 device_printf(sc->bge_dev, "chip reset failed\n");
2678 error = ENXIO;
2679 goto fail;
2680 }
2681
2682 bge_sig_legacy(sc, BGE_RESET_STOP);
2683 bge_sig_post_reset(sc, BGE_RESET_STOP);
2684
2685 if (bge_chipinit(sc)) {
2686 device_printf(sc->bge_dev, "chip initialization failed\n");
2687 error = ENXIO;
2688 goto fail;
2689 }
2690
2691 error = bge_get_eaddr(sc, eaddr);
2692 if (error) {
2693 device_printf(sc->bge_dev,
2694 "failed to read station address\n");
2695 error = ENXIO;
2696 goto fail;
2697 }
2698
2699 /* 5705 limits RX return ring to 512 entries. */
2700 if (BGE_IS_5705_PLUS(sc))
2701 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2702 else
2703 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2704
2705 if (bge_dma_alloc(dev)) {
2706 device_printf(sc->bge_dev,
2707 "failed to allocate DMA resources\n");
2708 error = ENXIO;
2709 goto fail;
2710 }
2711
2712 /* Set default tuneable values. */
2713 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2714 sc->bge_rx_coal_ticks = 150;
2715 sc->bge_tx_coal_ticks = 150;
2716 sc->bge_rx_max_coal_bds = 10;
2717 sc->bge_tx_max_coal_bds = 10;
2718
2719 /* Set up ifnet structure */
2720 ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
2721 if (ifp == NULL) {
2722 device_printf(sc->bge_dev, "failed to if_alloc()\n");
2723 error = ENXIO;
2724 goto fail;
2725 }
2726 ifp->if_softc = sc;
2727 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2728 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2729 ifp->if_ioctl = bge_ioctl;
2730 ifp->if_start = bge_start;
2731 ifp->if_init = bge_init;
2732 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
2733 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2734 IFQ_SET_READY(&ifp->if_snd);
2735 ifp->if_hwassist = BGE_CSUM_FEATURES;
2736 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
2737 IFCAP_VLAN_MTU;
2738 #ifdef IFCAP_VLAN_HWCSUM
2739 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
2740 #endif
2741 ifp->if_capenable = ifp->if_capabilities;
2742 #ifdef DEVICE_POLLING
2743 ifp->if_capabilities |= IFCAP_POLLING;
2744 #endif
2745
2746 /*
2747 * 5700 B0 chips do not support checksumming correctly due
2748 * to hardware bugs.
2749 */
2750 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
2751 ifp->if_capabilities &= ~IFCAP_HWCSUM;
2752 ifp->if_capenable &= ~IFCAP_HWCSUM;
2753 ifp->if_hwassist = 0;
2754 }
2755
2756 /*
2757 * Figure out what sort of media we have by checking the
2758 * hardware config word in the first 32k of NIC internal memory,
2759 * or fall back to examining the EEPROM if necessary.
2760 * Note: on some BCM5700 cards, this value appears to be unset.
2761 * If that's the case, we have to rely on identifying the NIC
2762 * by its PCI subsystem ID, as we do below for the SysKonnect
2763 * SK-9D41.
2764 */
2765 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2766 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2767 else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
2768 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
2769 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2770 sizeof(hwcfg))) {
2771 device_printf(sc->bge_dev, "failed to read EEPROM\n");
2772 error = ENXIO;
2773 goto fail;
2774 }
2775 hwcfg = ntohl(hwcfg);
2776 }
2777
2778 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2779 sc->bge_flags |= BGE_FLAG_TBI;
2780
2781 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2782 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41)
2783 sc->bge_flags |= BGE_FLAG_TBI;
2784
2785 if (sc->bge_flags & BGE_FLAG_TBI) {
2786 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
2787 bge_ifmedia_sts);
2788 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
2789 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2790 0, NULL);
2791 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
2792 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
2793 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2794 } else {
2795 /*
2796 * Do transceiver setup and tell the firmware the
2797 * driver is down so we can try to get access the
2798 * probe if ASF is running. Retry a couple of times
2799 * if we get a conflict with the ASF firmware accessing
2800 * the PHY.
2801 */
2802 trys = 0;
2803 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2804 again:
2805 bge_asf_driver_up(sc);
2806
2807 if (mii_phy_probe(dev, &sc->bge_miibus,
2808 bge_ifmedia_upd, bge_ifmedia_sts)) {
2809 if (trys++ < 4) {
2810 device_printf(sc->bge_dev, "Try again\n");
2811 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR,
2812 BMCR_RESET);
2813 goto again;
2814 }
2815
2816 device_printf(sc->bge_dev, "MII without any PHY!\n");
2817 error = ENXIO;
2818 goto fail;
2819 }
2820
2821 /*
2822 * Now tell the firmware we are going up after probing the PHY
2823 */
2824 if (sc->bge_asf_mode & ASF_STACKUP)
2825 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2826 }
2827
2828 /*
2829 * When using the BCM5701 in PCI-X mode, data corruption has
2830 * been observed in the first few bytes of some received packets.
2831 * Aligning the packet buffer in memory eliminates the corruption.
2832 * Unfortunately, this misaligns the packet payloads. On platforms
2833 * which do not support unaligned accesses, we will realign the
2834 * payloads by copying the received packets.
2835 */
2836 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2837 sc->bge_flags & BGE_FLAG_PCIX)
2838 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2839
2840 /*
2841 * Call MI attach routine.
2842 */
2843 ether_ifattach(ifp, eaddr);
2844 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
2845
2846 /* Tell upper layer we support long frames. */
2847 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2848
2849 /*
2850 * Hookup IRQ last.
2851 */
2852 #if __FreeBSD_version > 700030
2853 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
2854 NULL, bge_intr, sc, &sc->bge_intrhand);
2855 #else
2856 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
2857 bge_intr, sc, &sc->bge_intrhand);
2858 #endif
2859
2860 if (error) {
2861 bge_detach(dev);
2862 device_printf(sc->bge_dev, "couldn't set up irq\n");
2863 }
2864
2865 bge_add_sysctls(sc);
2866
2867 return (0);
2868
2869 fail:
2870 bge_release_resources(sc);
2871
2872 return (error);
2873 }
2874
2875 static int
2876 bge_detach(device_t dev)
2877 {
2878 struct bge_softc *sc;
2879 struct ifnet *ifp;
2880
2881 sc = device_get_softc(dev);
2882 ifp = sc->bge_ifp;
2883
2884 #ifdef DEVICE_POLLING
2885 if (ifp->if_capenable & IFCAP_POLLING)
2886 ether_poll_deregister(ifp);
2887 #endif
2888
2889 BGE_LOCK(sc);
2890 bge_stop(sc);
2891 bge_reset(sc);
2892 BGE_UNLOCK(sc);
2893
2894 callout_drain(&sc->bge_stat_ch);
2895
2896 ether_ifdetach(ifp);
2897
2898 if (sc->bge_flags & BGE_FLAG_TBI) {
2899 ifmedia_removeall(&sc->bge_ifmedia);
2900 } else {
2901 bus_generic_detach(dev);
2902 device_delete_child(dev, sc->bge_miibus);
2903 }
2904
2905 bge_release_resources(sc);
2906
2907 return (0);
2908 }
2909
2910 static void
2911 bge_release_resources(struct bge_softc *sc)
2912 {
2913 device_t dev;
2914
2915 dev = sc->bge_dev;
2916
2917 if (sc->bge_intrhand != NULL)
2918 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2919
2920 if (sc->bge_irq != NULL)
2921 bus_release_resource(dev, SYS_RES_IRQ,
2922 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
2923
2924 #if __FreeBSD_version > 602105
2925 if (sc->bge_flags & BGE_FLAG_MSI)
2926 pci_release_msi(dev);
2927 #endif
2928
2929 if (sc->bge_res != NULL)
2930 bus_release_resource(dev, SYS_RES_MEMORY,
2931 BGE_PCI_BAR0, sc->bge_res);
2932
2933 if (sc->bge_ifp != NULL)
2934 if_free(sc->bge_ifp);
2935
2936 bge_dma_free(sc);
2937
2938 if (mtx_initialized(&sc->bge_mtx)) /* XXX */
2939 BGE_LOCK_DESTROY(sc);
2940 }
2941
2942 static int
2943 bge_reset(struct bge_softc *sc)
2944 {
2945 device_t dev;
2946 uint32_t cachesize, command, pcistate, reset, val;
2947 void (*write_op)(struct bge_softc *, int, int);
2948 int i;
2949
2950 dev = sc->bge_dev;
2951
2952 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2953 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
2954 if (sc->bge_flags & BGE_FLAG_PCIE)
2955 write_op = bge_writemem_direct;
2956 else
2957 write_op = bge_writemem_ind;
2958 } else
2959 write_op = bge_writereg_ind;
2960
2961 /* Save some important PCI state. */
2962 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2963 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2964 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2965
2966 pci_write_config(dev, BGE_PCI_MISC_CTL,
2967 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
2968 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
2969
2970 /* Disable fastboot on controllers that support it. */
2971 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2972 BGE_IS_5755_PLUS(sc)) {
2973 if (bootverbose)
2974 device_printf(sc->bge_dev, "Disabling fastboot\n");
2975 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2976 }
2977
2978 /*
2979 * Write the magic number to SRAM at offset 0xB50.
2980 * When firmware finishes its initialization it will
2981 * write ~BGE_MAGIC_NUMBER to the same location.
2982 */
2983 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2984
2985 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
2986
2987 /* XXX: Broadcom Linux driver. */
2988 if (sc->bge_flags & BGE_FLAG_PCIE) {
2989 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */
2990 CSR_WRITE_4(sc, 0x7E2C, 0x20);
2991 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2992 /* Prevent PCIE link training during global reset */
2993 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
2994 reset |= 1 << 29;
2995 }
2996 }
2997
2998 /*
2999 * Set GPHY Power Down Override to leave GPHY
3000 * powered up in D0 uninitialized.
3001 */
3002 if (BGE_IS_5705_PLUS(sc))
3003 reset |= 0x04000000;
3004
3005 /* Issue global reset */
3006 write_op(sc, BGE_MISC_CFG, reset);
3007
3008 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3009 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3010 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
3011 val | BGE_VCPU_STATUS_DRV_RESET);
3012 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
3013 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
3014 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
3015 }
3016
3017 DELAY(1000);
3018
3019 /* XXX: Broadcom Linux driver. */
3020 if (sc->bge_flags & BGE_FLAG_PCIE) {
3021 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
3022 DELAY(500000); /* wait for link training to complete */
3023 val = pci_read_config(dev, 0xC4, 4);
3024 pci_write_config(dev, 0xC4, val | (1 << 15), 4);
3025 }
3026 /*
3027 * Set PCIE max payload size to 128 bytes and clear error
3028 * status.
3029 */
3030 pci_write_config(dev, 0xD8, 0xF5000, 4);
3031 }
3032
3033 /* Reset some of the PCI state that got zapped by reset. */
3034 pci_write_config(dev, BGE_PCI_MISC_CTL,
3035 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3036 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3037 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
3038 pci_write_config(dev, BGE_PCI_CMD, command, 4);
3039 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
3040
3041 /* Re-enable MSI, if neccesary, and enable the memory arbiter. */
3042 if (BGE_IS_5714_FAMILY(sc)) {
3043 /* This chip disables MSI on reset. */
3044 if (sc->bge_flags & BGE_FLAG_MSI) {
3045 val = pci_read_config(dev, BGE_PCI_MSI_CTL, 2);
3046 pci_write_config(dev, BGE_PCI_MSI_CTL,
3047 val | PCIM_MSICTRL_MSI_ENABLE, 2);
3048 val = CSR_READ_4(sc, BGE_MSI_MODE);
3049 CSR_WRITE_4(sc, BGE_MSI_MODE,
3050 val | BGE_MSIMODE_ENABLE);
3051 }
3052 val = CSR_READ_4(sc, BGE_MARB_MODE);
3053 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
3054 } else
3055 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3056
3057 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3058 for (i = 0; i < BGE_TIMEOUT; i++) {
3059 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3060 if (val & BGE_VCPU_STATUS_INIT_DONE)
3061 break;
3062 DELAY(100);
3063 }
3064 if (i == BGE_TIMEOUT) {
3065 device_printf(sc->bge_dev, "reset timed out\n");
3066 return (1);
3067 }
3068 } else {
3069 /*
3070 * Poll until we see the 1's complement of the magic number.
3071 * This indicates that the firmware initialization is complete.
3072 * We expect this to fail if no chip containing the Ethernet
3073 * address is fitted though.
3074 */
3075 for (i = 0; i < BGE_TIMEOUT; i++) {
3076 DELAY(10);
3077 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
3078 if (val == ~BGE_MAGIC_NUMBER)
3079 break;
3080 }
3081
3082 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
3083 device_printf(sc->bge_dev, "firmware handshake timed out, "
3084 "found 0x%08x\n", val);
3085 }
3086
3087 /*
3088 * XXX Wait for the value of the PCISTATE register to
3089 * return to its original pre-reset state. This is a
3090 * fairly good indicator of reset completion. If we don't
3091 * wait for the reset to fully complete, trying to read
3092 * from the device's non-PCI registers may yield garbage
3093 * results.
3094 */
3095 for (i = 0; i < BGE_TIMEOUT; i++) {
3096 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
3097 break;
3098 DELAY(10);
3099 }
3100
3101 if (sc->bge_flags & BGE_FLAG_PCIE) {
3102 reset = bge_readmem_ind(sc, 0x7C00);
3103 bge_writemem_ind(sc, 0x7C00, reset | (1 << 25));
3104 }
3105
3106 /* Fix up byte swapping. */
3107 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
3108 BGE_MODECTL_BYTESWAP_DATA);
3109
3110 /* Tell the ASF firmware we are up */
3111 if (sc->bge_asf_mode & ASF_STACKUP)
3112 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3113
3114 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
3115
3116 /*
3117 * The 5704 in TBI mode apparently needs some special
3118 * adjustment to insure the SERDES drive level is set
3119 * to 1.2V.
3120 */
3121 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
3122 sc->bge_flags & BGE_FLAG_TBI) {
3123 val = CSR_READ_4(sc, BGE_SERDES_CFG);
3124 val = (val & ~0xFFF) | 0x880;
3125 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
3126 }
3127
3128 /* XXX: Broadcom Linux driver. */
3129 if (sc->bge_flags & BGE_FLAG_PCIE &&
3130 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3131 val = CSR_READ_4(sc, 0x7C00);
3132 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
3133 }
3134 DELAY(10000);
3135
3136 return(0);
3137 }
3138
3139 /*
3140 * Frame reception handling. This is called if there's a frame
3141 * on the receive return list.
3142 *
3143 * Note: we have to be able to handle two possibilities here:
3144 * 1) the frame is from the jumbo receive ring
3145 * 2) the frame is from the standard receive ring
3146 */
3147
3148 static int
3149 bge_rxeof(struct bge_softc *sc)
3150 {
3151 struct ifnet *ifp;
3152 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
3153 uint16_t rx_prod, rx_cons;
3154
3155 BGE_LOCK_ASSERT(sc);
3156 rx_cons = sc->bge_rx_saved_considx;
3157 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3158
3159 /* Nothing to do. */
3160 if (rx_cons == rx_prod)
3161 return (rx_npkts);
3162
3163 ifp = sc->bge_ifp;
3164
3165 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3166 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
3167 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3168 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
3169 if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
3170 (MCLBYTES - ETHER_ALIGN))
3171 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3172 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
3173
3174 while (rx_cons != rx_prod) {
3175 struct bge_rx_bd *cur_rx;
3176 uint32_t rxidx;
3177 struct mbuf *m = NULL;
3178 uint16_t vlan_tag = 0;
3179 int have_tag = 0;
3180
3181 #ifdef DEVICE_POLLING
3182 if (ifp->if_capenable & IFCAP_POLLING) {
3183 if (sc->rxcycles <= 0)
3184 break;
3185 sc->rxcycles--;
3186 }
3187 #endif
3188
3189 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
3190
3191 rxidx = cur_rx->bge_idx;
3192 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
3193
3194 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
3195 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
3196 have_tag = 1;
3197 vlan_tag = cur_rx->bge_vlan_tag;
3198 }
3199
3200 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
3201 jumbocnt++;
3202 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
3203 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3204 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3205 continue;
3206 }
3207 if (bge_newbuf_jumbo(sc, rxidx) != 0) {
3208 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3209 ifp->if_iqdrops++;
3210 continue;
3211 }
3212 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3213 } else {
3214 stdcnt++;
3215 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3216 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3217 continue;
3218 }
3219 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
3220 if (bge_newbuf_std(sc, rxidx) != 0) {
3221 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3222 ifp->if_iqdrops++;
3223 continue;
3224 }
3225 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3226 }
3227
3228 ifp->if_ipackets++;
3229 #ifndef __NO_STRICT_ALIGNMENT
3230 /*
3231 * For architectures with strict alignment we must make sure
3232 * the payload is aligned.
3233 */
3234 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
3235 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
3236 cur_rx->bge_len);
3237 m->m_data += ETHER_ALIGN;
3238 }
3239 #endif
3240 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
3241 m->m_pkthdr.rcvif = ifp;
3242
3243 if (ifp->if_capenable & IFCAP_RXCSUM) {
3244 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3245 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3246 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
3247 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3248 }
3249 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
3250 m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
3251 m->m_pkthdr.csum_data =
3252 cur_rx->bge_tcp_udp_csum;
3253 m->m_pkthdr.csum_flags |=
3254 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
3255 }
3256 }
3257
3258 /*
3259 * If we received a packet with a vlan tag,
3260 * attach that information to the packet.
3261 */
3262 if (have_tag) {
3263 #if __FreeBSD_version > 700022
3264 m->m_pkthdr.ether_vtag = vlan_tag;
3265 m->m_flags |= M_VLANTAG;
3266 #else
3267 VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag);
3268 if (m == NULL)
3269 continue;
3270 #endif
3271 }
3272
3273 BGE_UNLOCK(sc);
3274 (*ifp->if_input)(ifp, m);
3275 BGE_LOCK(sc);
3276 rx_npkts++;
3277
3278 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
3279 return (rx_npkts);
3280 }
3281
3282 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3283 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
3284 if (stdcnt > 0)
3285 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3286 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
3287
3288 if (jumbocnt > 0)
3289 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3290 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
3291
3292 sc->bge_rx_saved_considx = rx_cons;
3293 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3294 if (stdcnt)
3295 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
3296 if (jumbocnt)
3297 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
3298 #ifdef notyet
3299 /*
3300 * This register wraps very quickly under heavy packet drops.
3301 * If you need correct statistics, you can enable this check.
3302 */
3303 if (BGE_IS_5705_PLUS(sc))
3304 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3305 #endif
3306 return (rx_npkts);
3307 }
3308
3309 static void
3310 bge_txeof(struct bge_softc *sc)
3311 {
3312 struct bge_tx_bd *cur_tx = NULL;
3313 struct ifnet *ifp;
3314
3315 BGE_LOCK_ASSERT(sc);
3316
3317 /* Nothing to do. */
3318 if (sc->bge_tx_saved_considx ==
3319 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
3320 return;
3321
3322 ifp = sc->bge_ifp;
3323
3324 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
3325 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
3326 /*
3327 * Go through our tx ring and free mbufs for those
3328 * frames that have been sent.
3329 */
3330 while (sc->bge_tx_saved_considx !=
3331 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
3332 uint32_t idx = 0;
3333
3334 idx = sc->bge_tx_saved_considx;
3335 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
3336 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
3337 ifp->if_opackets++;
3338 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
3339 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
3340 sc->bge_cdata.bge_tx_dmamap[idx],
3341 BUS_DMASYNC_POSTWRITE);
3342 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
3343 sc->bge_cdata.bge_tx_dmamap[idx]);
3344 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
3345 sc->bge_cdata.bge_tx_chain[idx] = NULL;
3346 }
3347 sc->bge_txcnt--;
3348 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
3349 }
3350
3351 if (cur_tx != NULL)
3352 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3353 if (sc->bge_txcnt == 0)
3354 sc->bge_timer = 0;
3355 }
3356
3357 #ifdef DEVICE_POLLING
3358 static int
3359 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3360 {
3361 struct bge_softc *sc = ifp->if_softc;
3362 uint32_t statusword;
3363 int rx_npkts = 0;
3364
3365 BGE_LOCK(sc);
3366 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3367 BGE_UNLOCK(sc);
3368 return (rx_npkts);
3369 }
3370
3371 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3372 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD);
3373
3374 statusword = atomic_readandclear_32(
3375 &sc->bge_ldata.bge_status_block->bge_status);
3376
3377 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3378 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD);
3379
3380 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
3381 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
3382 sc->bge_link_evt++;
3383
3384 if (cmd == POLL_AND_CHECK_STATUS)
3385 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3386 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3387 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
3388 bge_link_upd(sc);
3389
3390 sc->rxcycles = count;
3391 rx_npkts = bge_rxeof(sc);
3392 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3393 BGE_UNLOCK(sc);
3394 return (rx_npkts);
3395 }
3396 bge_txeof(sc);
3397 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3398 bge_start_locked(ifp);
3399
3400 BGE_UNLOCK(sc);
3401 return (rx_npkts);
3402 }
3403 #endif /* DEVICE_POLLING */
3404
3405 static void
3406 bge_intr(void *xsc)
3407 {
3408 struct bge_softc *sc;
3409 struct ifnet *ifp;
3410 uint32_t statusword;
3411
3412 sc = xsc;
3413
3414 BGE_LOCK(sc);
3415
3416 ifp = sc->bge_ifp;
3417
3418 #ifdef DEVICE_POLLING
3419 if (ifp->if_capenable & IFCAP_POLLING) {
3420 BGE_UNLOCK(sc);
3421 return;
3422 }
3423 #endif
3424
3425 /*
3426 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
3427 * disable interrupts by writing nonzero like we used to, since with
3428 * our current organization this just gives complications and
3429 * pessimizations for re-enabling interrupts. We used to have races
3430 * instead of the necessary complications. Disabling interrupts
3431 * would just reduce the chance of a status update while we are
3432 * running (by switching to the interrupt-mode coalescence
3433 * parameters), but this chance is already very low so it is more
3434 * efficient to get another interrupt than prevent it.
3435 *
3436 * We do the ack first to ensure another interrupt if there is a
3437 * status update after the ack. We don't check for the status
3438 * changing later because it is more efficient to get another
3439 * interrupt than prevent it, not quite as above (not checking is
3440 * a smaller optimization than not toggling the interrupt enable,
3441 * since checking doesn't involve PCI accesses and toggling require
3442 * the status check). So toggling would probably be a pessimization
3443 * even with MSI. It would only be needed for using a task queue.
3444 */
3445 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3446
3447 /*
3448 * Do the mandatory PCI flush as well as get the link status.
3449 */
3450 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
3451
3452 /* Make sure the descriptor ring indexes are coherent. */
3453 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3454 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD);
3455
3456 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3457 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3458 statusword || sc->bge_link_evt)
3459 bge_link_upd(sc);
3460
3461 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3462 /* Check RX return ring producer/consumer. */
3463 bge_rxeof(sc);
3464 }
3465
3466 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3467 /* Check TX ring producer/consumer. */
3468 bge_txeof(sc);
3469 }
3470
3471 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3472 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3473 bge_start_locked(ifp);
3474
3475 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3476 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD);
3477
3478 BGE_UNLOCK(sc);
3479 }
3480
3481 static void
3482 bge_asf_driver_up(struct bge_softc *sc)
3483 {
3484 if (sc->bge_asf_mode & ASF_STACKUP) {
3485 /* Send ASF heartbeat aprox. every 2s */
3486 if (sc->bge_asf_count)
3487 sc->bge_asf_count --;
3488 else {
3489 sc->bge_asf_count = 5;
3490 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW,
3491 BGE_FW_DRV_ALIVE);
3492 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4);
3493 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3);
3494 CSR_WRITE_4(sc, BGE_CPU_EVENT,
3495 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
3496 }
3497 }
3498 }
3499
3500 static void
3501 bge_tick(void *xsc)
3502 {
3503 struct bge_softc *sc = xsc;
3504 struct mii_data *mii = NULL;
3505
3506 BGE_LOCK_ASSERT(sc);
3507
3508 /* Synchronize with possible callout reset/stop. */
3509 if (callout_pending(&sc->bge_stat_ch) ||
3510 !callout_active(&sc->bge_stat_ch))
3511 return;
3512
3513 if (BGE_IS_5705_PLUS(sc))
3514 bge_stats_update_regs(sc);
3515 else
3516 bge_stats_update(sc);
3517
3518 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
3519 mii = device_get_softc(sc->bge_miibus);
3520 /*
3521 * Do not touch PHY if we have link up. This could break
3522 * IPMI/ASF mode or produce extra input errors
3523 * (extra errors was reported for bcm5701 & bcm5704).
3524 */
3525 if (!sc->bge_link)
3526 mii_tick(mii);
3527 } else {
3528 /*
3529 * Since in TBI mode auto-polling can't be used we should poll
3530 * link status manually. Here we register pending link event
3531 * and trigger interrupt.
3532 */
3533 #ifdef DEVICE_POLLING
3534 /* In polling mode we poll link state in bge_poll(). */
3535 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
3536 #endif
3537 {
3538 sc->bge_link_evt++;
3539 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3540 sc->bge_flags & BGE_FLAG_5788)
3541 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3542 else
3543 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3544 }
3545 }
3546
3547 bge_asf_driver_up(sc);
3548 bge_watchdog(sc);
3549
3550 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
3551 }
3552
3553 static void
3554 bge_stats_update_regs(struct bge_softc *sc)
3555 {
3556 struct ifnet *ifp;
3557
3558 ifp = sc->bge_ifp;
3559
3560 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS +
3561 offsetof(struct bge_mac_stats_regs, etherStatsCollisions));
3562
3563 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
3564 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3565 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
3566 }
3567
3568 static void
3569 bge_stats_update(struct bge_softc *sc)
3570 {
3571 struct ifnet *ifp;
3572 bus_size_t stats;
3573 uint32_t cnt; /* current register value */
3574
3575 ifp = sc->bge_ifp;
3576
3577 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3578
3579 #define READ_STAT(sc, stats, stat) \
3580 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3581
3582 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
3583 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
3584 sc->bge_tx_collisions = cnt;
3585
3586 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
3587 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
3588 sc->bge_rx_discards = cnt;
3589
3590 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
3591 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
3592 sc->bge_tx_discards = cnt;
3593
3594 #undef READ_STAT
3595 }
3596
3597 /*
3598 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
3599 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
3600 * but when such padded frames employ the bge IP/TCP checksum offload,
3601 * the hardware checksum assist gives incorrect results (possibly
3602 * from incorporating its own padding into the UDP/TCP checksum; who knows).
3603 * If we pad such runts with zeros, the onboard checksum comes out correct.
3604 */
3605 static __inline int
3606 bge_cksum_pad(struct mbuf *m)
3607 {
3608 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
3609 struct mbuf *last;
3610
3611 /* If there's only the packet-header and we can pad there, use it. */
3612 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
3613 M_TRAILINGSPACE(m) >= padlen) {
3614 last = m;
3615 } else {
3616 /*
3617 * Walk packet chain to find last mbuf. We will either
3618 * pad there, or append a new mbuf and pad it.
3619 */
3620 for (last = m; last->m_next != NULL; last = last->m_next);
3621 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
3622 /* Allocate new empty mbuf, pad it. Compact later. */
3623 struct mbuf *n;
3624
3625 MGET(n, M_DONTWAIT, MT_DATA);
3626 if (n == NULL)
3627 return (ENOBUFS);
3628 n->m_len = 0;
3629 last->m_next = n;
3630 last = n;
3631 }
3632 }
3633
3634 /* Now zero the pad area, to avoid the bge cksum-assist bug. */
3635 memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
3636 last->m_len += padlen;
3637 m->m_pkthdr.len += padlen;
3638
3639 return (0);
3640 }
3641
3642 /*
3643 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
3644 * pointers to descriptors.
3645 */
3646 static int
3647 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
3648 {
3649 bus_dma_segment_t segs[BGE_NSEG_NEW];
3650 bus_dmamap_t map;
3651 struct bge_tx_bd *d;
3652 struct mbuf *m = *m_head;
3653 uint32_t idx = *txidx;
3654 uint16_t csum_flags;
3655 int nsegs, i, error;
3656
3657 csum_flags = 0;
3658 if (m->m_pkthdr.csum_flags) {
3659 if (m->m_pkthdr.csum_flags & CSUM_IP)
3660 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3661 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
3662 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3663 if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
3664 (error = bge_cksum_pad(m)) != 0) {
3665 m_freem(m);
3666 *m_head = NULL;
3667 return (error);
3668 }
3669 }
3670 if (m->m_flags & M_LASTFRAG)
3671 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3672 else if (m->m_flags & M_FRAG)
3673 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3674 }
3675
3676 map = sc->bge_cdata.bge_tx_dmamap[idx];
3677 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
3678 &nsegs, BUS_DMA_NOWAIT);
3679 if (error == EFBIG) {
3680 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW);
3681 if (m == NULL) {
3682 m_freem(*m_head);
3683 *m_head = NULL;
3684 return (ENOBUFS);
3685 }
3686 *m_head = m;
3687 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
3688 m, segs, &nsegs, BUS_DMA_NOWAIT);
3689 if (error) {
3690 m_freem(m);
3691 *m_head = NULL;
3692 return (error);
3693 }
3694 } else if (error != 0)
3695 return (error);
3696
3697 /*
3698 * Sanity check: avoid coming within 16 descriptors
3699 * of the end of the ring.
3700 */
3701 if (nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) {
3702 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
3703 return (ENOBUFS);
3704 }
3705
3706 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3707
3708 for (i = 0; ; i++) {
3709 d = &sc->bge_ldata.bge_tx_ring[idx];
3710 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3711 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3712 d->bge_len = segs[i].ds_len;
3713 d->bge_flags = csum_flags;
3714 if (i == nsegs - 1)
3715 break;
3716 BGE_INC(idx, BGE_TX_RING_CNT);
3717 }
3718
3719 /* Mark the last segment as end of packet... */
3720 d->bge_flags |= BGE_TXBDFLAG_END;
3721
3722 /* ... and put VLAN tag into first segment. */
3723 d = &sc->bge_ldata.bge_tx_ring[*txidx];
3724 #if __FreeBSD_version > 700022
3725 if (m->m_flags & M_VLANTAG) {
3726 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3727 d->bge_vlan_tag = m->m_pkthdr.ether_vtag;
3728 } else
3729 d->bge_vlan_tag = 0;
3730 #else
3731 {
3732 struct m_tag *mtag;
3733
3734 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) {
3735 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3736 d->bge_vlan_tag = VLAN_TAG_VALUE(mtag);
3737 } else
3738 d->bge_vlan_tag = 0;
3739 }
3740 #endif
3741
3742 /*
3743 * Insure that the map for this transmission
3744 * is placed at the array index of the last descriptor
3745 * in this chain.
3746 */
3747 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
3748 sc->bge_cdata.bge_tx_dmamap[idx] = map;
3749 sc->bge_cdata.bge_tx_chain[idx] = m;
3750 sc->bge_txcnt += nsegs;
3751
3752 BGE_INC(idx, BGE_TX_RING_CNT);
3753 *txidx = idx;
3754
3755 return (0);
3756 }
3757
3758 /*
3759 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3760 * to the mbuf data regions directly in the transmit descriptors.
3761 */
3762 static void
3763 bge_start_locked(struct ifnet *ifp)
3764 {
3765 struct bge_softc *sc;
3766 struct mbuf *m_head = NULL;
3767 uint32_t prodidx;
3768 int count = 0;
3769
3770 sc = ifp->if_softc;
3771
3772 if (!sc->bge_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3773 return;
3774
3775 prodidx = sc->bge_tx_prodidx;
3776
3777 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
3778 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3779 if (m_head == NULL)
3780 break;
3781
3782 /*
3783 * XXX
3784 * The code inside the if() block is never reached since we
3785 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
3786 * requests to checksum TCP/UDP in a fragmented packet.
3787 *
3788 * XXX
3789 * safety overkill. If this is a fragmented packet chain
3790 * with delayed TCP/UDP checksums, then only encapsulate
3791 * it if we have enough descriptors to handle the entire
3792 * chain at once.
3793 * (paranoia -- may not actually be needed)
3794 */
3795 if (m_head->m_flags & M_FIRSTFRAG &&
3796 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
3797 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3798 m_head->m_pkthdr.csum_data + 16) {
3799 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3800 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3801 break;
3802 }
3803 }
3804
3805 /*
3806 * Pack the data into the transmit ring. If we
3807 * don't have room, set the OACTIVE flag and wait
3808 * for the NIC to drain the ring.
3809 */
3810 if (bge_encap(sc, &m_head, &prodidx)) {
3811 if (m_head == NULL)
3812 break;
3813 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3814 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3815 break;
3816 }
3817 ++count;
3818
3819 /*
3820 * If there's a BPF listener, bounce a copy of this frame
3821 * to him.
3822 */
3823 #ifdef ETHER_BPF_MTAP
3824 ETHER_BPF_MTAP(ifp, m_head);
3825 #else
3826 BPF_MTAP(ifp, m_head);
3827 #endif
3828 }
3829
3830 if (count == 0)
3831 /* No packets were dequeued. */
3832 return;
3833
3834 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
3835 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
3836 /* Transmit. */
3837 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3838 /* 5700 b2 errata */
3839 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
3840 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3841
3842 sc->bge_tx_prodidx = prodidx;
3843
3844 /*
3845 * Set a timeout in case the chip goes out to lunch.
3846 */
3847 sc->bge_timer = 5;
3848 }
3849
3850 /*
3851 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3852 * to the mbuf data regions directly in the transmit descriptors.
3853 */
3854 static void
3855 bge_start(struct ifnet *ifp)
3856 {
3857 struct bge_softc *sc;
3858
3859 sc = ifp->if_softc;
3860 BGE_LOCK(sc);
3861 bge_start_locked(ifp);
3862 BGE_UNLOCK(sc);
3863 }
3864
3865 static void
3866 bge_init_locked(struct bge_softc *sc)
3867 {
3868 struct ifnet *ifp;
3869 uint16_t *m;
3870
3871 BGE_LOCK_ASSERT(sc);
3872
3873 ifp = sc->bge_ifp;
3874
3875 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3876 return;
3877
3878 /* Cancel pending I/O and flush buffers. */
3879 bge_stop(sc);
3880
3881 bge_stop_fw(sc);
3882 bge_sig_pre_reset(sc, BGE_RESET_START);
3883 bge_reset(sc);
3884 bge_sig_legacy(sc, BGE_RESET_START);
3885 bge_sig_post_reset(sc, BGE_RESET_START);
3886
3887 bge_chipinit(sc);
3888
3889 /*
3890 * Init the various state machines, ring
3891 * control blocks and firmware.
3892 */
3893 if (bge_blockinit(sc)) {
3894 device_printf(sc->bge_dev, "initialization failure\n");
3895 return;
3896 }
3897
3898 ifp = sc->bge_ifp;
3899
3900 /* Specify MTU. */
3901 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3902 ETHER_HDR_LEN + ETHER_CRC_LEN +
3903 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
3904
3905 /* Load our MAC address. */
3906 m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
3907 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3908 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3909
3910 /* Program promiscuous mode. */
3911 bge_setpromisc(sc);
3912
3913 /* Program multicast filter. */
3914 bge_setmulti(sc);
3915
3916 /* Program VLAN tag stripping. */
3917 bge_setvlan(sc);
3918
3919 /* Init RX ring. */
3920 if (bge_init_rx_ring_std(sc) != 0) {
3921 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
3922 bge_stop(sc);
3923 return;
3924 }
3925
3926 /*
3927 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3928 * memory to insure that the chip has in fact read the first
3929 * entry of the ring.
3930 */
3931 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3932 uint32_t v, i;
3933 for (i = 0; i < 10; i++) {
3934 DELAY(20);
3935 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3936 if (v == (MCLBYTES - ETHER_ALIGN))
3937 break;
3938 }
3939 if (i == 10)
3940 device_printf (sc->bge_dev,
3941 "5705 A0 chip failed to load RX ring\n");
3942 }
3943
3944 /* Init jumbo RX ring. */
3945 if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
3946 (MCLBYTES - ETHER_ALIGN)) {
3947 if (bge_init_rx_ring_jumbo(sc) != 0) {
3948 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
3949 bge_stop(sc);
3950 return;
3951 }
3952 }
3953
3954 /* Init our RX return ring index. */
3955 sc->bge_rx_saved_considx = 0;
3956
3957 /* Init our RX/TX stat counters. */
3958 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
3959
3960 /* Init TX ring. */
3961 bge_init_tx_ring(sc);
3962
3963 /* Turn on transmitter. */
3964 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
3965
3966 /* Turn on receiver. */
3967 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3968
3969 /* Tell firmware we're alive. */
3970 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3971
3972 #ifdef DEVICE_POLLING
3973 /* Disable interrupts if we are polling. */
3974 if (ifp->if_capenable & IFCAP_POLLING) {
3975 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
3976 BGE_PCIMISCCTL_MASK_PCI_INTR);
3977 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3978 } else
3979 #endif
3980
3981 /* Enable host interrupts. */
3982 {
3983 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
3984 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3985 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3986 }
3987
3988 bge_ifmedia_upd_locked(ifp);
3989
3990 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3991 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3992
3993 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
3994 }
3995
3996 static void
3997 bge_init(void *xsc)
3998 {
3999 struct bge_softc *sc = xsc;
4000
4001 BGE_LOCK(sc);
4002 bge_init_locked(sc);
4003 BGE_UNLOCK(sc);
4004 }
4005
4006 /*
4007 * Set media options.
4008 */
4009 static int
4010 bge_ifmedia_upd(struct ifnet *ifp)
4011 {
4012 struct bge_softc *sc = ifp->if_softc;
4013 int res;
4014
4015 BGE_LOCK(sc);
4016 res = bge_ifmedia_upd_locked(ifp);
4017 BGE_UNLOCK(sc);
4018
4019 return (res);
4020 }
4021
4022 static int
4023 bge_ifmedia_upd_locked(struct ifnet *ifp)
4024 {
4025 struct bge_softc *sc = ifp->if_softc;
4026 struct mii_data *mii;
4027 struct mii_softc *miisc;
4028 struct ifmedia *ifm;
4029
4030 BGE_LOCK_ASSERT(sc);
4031
4032 ifm = &sc->bge_ifmedia;
4033
4034 /* If this is a 1000baseX NIC, enable the TBI port. */
4035 if (sc->bge_flags & BGE_FLAG_TBI) {
4036 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
4037 return (EINVAL);
4038 switch(IFM_SUBTYPE(ifm->ifm_media)) {
4039 case IFM_AUTO:
4040 /*
4041 * The BCM5704 ASIC appears to have a special
4042 * mechanism for programming the autoneg
4043 * advertisement registers in TBI mode.
4044 */
4045 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4046 uint32_t sgdig;
4047 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
4048 if (sgdig & BGE_SGDIGSTS_DONE) {
4049 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
4050 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
4051 sgdig |= BGE_SGDIGCFG_AUTO |
4052 BGE_SGDIGCFG_PAUSE_CAP |
4053 BGE_SGDIGCFG_ASYM_PAUSE;
4054 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
4055 sgdig | BGE_SGDIGCFG_SEND);
4056 DELAY(5);
4057 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
4058 }
4059 }
4060 break;
4061 case IFM_1000_SX:
4062 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
4063 BGE_CLRBIT(sc, BGE_MAC_MODE,
4064 BGE_MACMODE_HALF_DUPLEX);
4065 } else {
4066 BGE_SETBIT(sc, BGE_MAC_MODE,
4067 BGE_MACMODE_HALF_DUPLEX);
4068 }
4069 break;
4070 default:
4071 return (EINVAL);
4072 }
4073 return (0);
4074 }
4075
4076 sc->bge_link_evt++;
4077 mii = device_get_softc(sc->bge_miibus);
4078 if (mii->mii_instance)
4079 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4080 mii_phy_reset(miisc);
4081 mii_mediachg(mii);
4082
4083 /*
4084 * Force an interrupt so that we will call bge_link_upd
4085 * if needed and clear any pending link state attention.
4086 * Without this we are not getting any further interrupts
4087 * for link state changes and thus will not UP the link and
4088 * not be able to send in bge_start_locked. The only
4089 * way to get things working was to receive a packet and
4090 * get an RX intr.
4091 * bge_tick should help for fiber cards and we might not
4092 * need to do this here if BGE_FLAG_TBI is set but as
4093 * we poll for fiber anyway it should not harm.
4094 */
4095 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4096 sc->bge_flags & BGE_FLAG_5788)
4097 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4098 else
4099 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4100
4101 return (0);
4102 }
4103
4104 /*
4105 * Report current media status.
4106 */
4107 static void
4108 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4109 {
4110 struct bge_softc *sc = ifp->if_softc;
4111 struct mii_data *mii;
4112
4113 BGE_LOCK(sc);
4114
4115 if (sc->bge_flags & BGE_FLAG_TBI) {
4116 ifmr->ifm_status = IFM_AVALID;
4117 ifmr->ifm_active = IFM_ETHER;
4118 if (CSR_READ_4(sc, BGE_MAC_STS) &
4119 BGE_MACSTAT_TBI_PCS_SYNCHED)
4120 ifmr->ifm_status |= IFM_ACTIVE;
4121 else {
4122 ifmr->ifm_active |= IFM_NONE;
4123 BGE_UNLOCK(sc);
4124 return;
4125 }
4126 ifmr->ifm_active |= IFM_1000_SX;
4127 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
4128 ifmr->ifm_active |= IFM_HDX;
4129 else
4130 ifmr->ifm_active |= IFM_FDX;
4131 BGE_UNLOCK(sc);
4132 return;
4133 }
4134
4135 mii = device_get_softc(sc->bge_miibus);
4136 mii_pollstat(mii);
4137 ifmr->ifm_active = mii->mii_media_active;
4138 ifmr->ifm_status = mii->mii_media_status;
4139
4140 BGE_UNLOCK(sc);
4141 }
4142
4143 static int
4144 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
4145 {
4146 struct bge_softc *sc = ifp->if_softc;
4147 struct ifreq *ifr = (struct ifreq *) data;
4148 struct mii_data *mii;
4149 int flags, mask, error = 0;
4150
4151 switch (command) {
4152 case SIOCSIFMTU:
4153 if (ifr->ifr_mtu < ETHERMIN ||
4154 ((BGE_IS_JUMBO_CAPABLE(sc)) &&
4155 ifr->ifr_mtu > BGE_JUMBO_MTU) ||
4156 ((!BGE_IS_JUMBO_CAPABLE(sc)) &&
4157 ifr->ifr_mtu > ETHERMTU))
4158 error = EINVAL;
4159 else if (ifp->if_mtu != ifr->ifr_mtu) {
4160 ifp->if_mtu = ifr->ifr_mtu;
4161 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4162 bge_init(sc);
4163 }
4164 break;
4165 case SIOCSIFFLAGS:
4166 BGE_LOCK(sc);
4167 if (ifp->if_flags & IFF_UP) {
4168 /*
4169 * If only the state of the PROMISC flag changed,
4170 * then just use the 'set promisc mode' command
4171 * instead of reinitializing the entire NIC. Doing
4172 * a full re-init means reloading the firmware and
4173 * waiting for it to start up, which may take a
4174 * second or two. Similarly for ALLMULTI.
4175 */
4176 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4177 flags = ifp->if_flags ^ sc->bge_if_flags;
4178 if (flags & IFF_PROMISC)
4179 bge_setpromisc(sc);
4180 if (flags & IFF_ALLMULTI)
4181 bge_setmulti(sc);
4182 } else
4183 bge_init_locked(sc);
4184 } else {
4185 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4186 bge_stop(sc);
4187 }
4188 }
4189 sc->bge_if_flags = ifp->if_flags;
4190 BGE_UNLOCK(sc);
4191 error = 0;
4192 break;
4193 case SIOCADDMULTI:
4194 case SIOCDELMULTI:
4195 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4196 BGE_LOCK(sc);
4197 bge_setmulti(sc);
4198 BGE_UNLOCK(sc);
4199 error = 0;
4200 }
4201 break;
4202 case SIOCSIFMEDIA:
4203 case SIOCGIFMEDIA:
4204 if (sc->bge_flags & BGE_FLAG_TBI) {
4205 error = ifmedia_ioctl(ifp, ifr,
4206 &sc->bge_ifmedia, command);
4207 } else {
4208 mii = device_get_softc(sc->bge_miibus);
4209 error = ifmedia_ioctl(ifp, ifr,
4210 &mii->mii_media, command);
4211 }
4212 break;
4213 case SIOCSIFCAP:
4214 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
4215 #ifdef DEVICE_POLLING
4216 if (mask & IFCAP_POLLING) {
4217 if (ifr->ifr_reqcap & IFCAP_POLLING) {
4218 error = ether_poll_register(bge_poll, ifp);
4219 if (error)
4220 return (error);
4221 BGE_LOCK(sc);
4222 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4223 BGE_PCIMISCCTL_MASK_PCI_INTR);
4224 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4225 ifp->if_capenable |= IFCAP_POLLING;
4226 BGE_UNLOCK(sc);
4227 } else {
4228 error = ether_poll_deregister(ifp);
4229 /* Enable interrupt even in error case */
4230 BGE_LOCK(sc);
4231 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
4232 BGE_PCIMISCCTL_MASK_PCI_INTR);
4233 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4234 ifp->if_capenable &= ~IFCAP_POLLING;
4235 BGE_UNLOCK(sc);
4236 }
4237 }
4238 #endif
4239 if (mask & IFCAP_HWCSUM) {
4240 ifp->if_capenable ^= IFCAP_HWCSUM;
4241 if (IFCAP_HWCSUM & ifp->if_capenable &&
4242 IFCAP_HWCSUM & ifp->if_capabilities)
4243 ifp->if_hwassist = BGE_CSUM_FEATURES;
4244 else
4245 ifp->if_hwassist = 0;
4246 #ifdef VLAN_CAPABILITIES
4247 VLAN_CAPABILITIES(ifp);
4248 #endif
4249 }
4250
4251 if (mask & IFCAP_VLAN_MTU) {
4252 ifp->if_capenable ^= IFCAP_VLAN_MTU;
4253 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4254 bge_init(sc);
4255 }
4256
4257 if (mask & IFCAP_VLAN_HWTAGGING) {
4258 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
4259 BGE_LOCK(sc);
4260 bge_setvlan(sc);
4261 BGE_UNLOCK(sc);
4262 #ifdef VLAN_CAPABILITIES
4263 VLAN_CAPABILITIES(ifp);
4264 #endif
4265 }
4266
4267 break;
4268 default:
4269 error = ether_ioctl(ifp, command, data);
4270 break;
4271 }
4272
4273 return (error);
4274 }
4275
4276 static void
4277 bge_watchdog(struct bge_softc *sc)
4278 {
4279 struct ifnet *ifp;
4280
4281 BGE_LOCK_ASSERT(sc);
4282
4283 if (sc->bge_timer == 0 || --sc->bge_timer)
4284 return;
4285
4286 ifp = sc->bge_ifp;
4287
4288 if_printf(ifp, "watchdog timeout -- resetting\n");
4289
4290 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4291 bge_init_locked(sc);
4292
4293 ifp->if_oerrors++;
4294 }
4295
4296 /*
4297 * Stop the adapter and free any mbufs allocated to the
4298 * RX and TX lists.
4299 */
4300 static void
4301 bge_stop(struct bge_softc *sc)
4302 {
4303 struct ifnet *ifp;
4304 struct ifmedia_entry *ifm;
4305 struct mii_data *mii = NULL;
4306 int mtmp, itmp;
4307
4308 BGE_LOCK_ASSERT(sc);
4309
4310 ifp = sc->bge_ifp;
4311
4312 if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
4313 mii = device_get_softc(sc->bge_miibus);
4314
4315 callout_stop(&sc->bge_stat_ch);
4316
4317 /* Disable host interrupts. */
4318 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4319 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4320
4321 /*
4322 * Tell firmware we're shutting down.
4323 */
4324 bge_stop_fw(sc);
4325 bge_sig_pre_reset(sc, BGE_RESET_STOP);
4326
4327 /*
4328 * Disable all of the receiver blocks.
4329 */
4330 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4331 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
4332 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
4333 if (!(BGE_IS_5705_PLUS(sc)))
4334 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
4335 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
4336 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
4337 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
4338
4339 /*
4340 * Disable all of the transmit blocks.
4341 */
4342 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
4343 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
4344 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
4345 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
4346 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
4347 if (!(BGE_IS_5705_PLUS(sc)))
4348 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
4349 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
4350
4351 /*
4352 * Shut down all of the memory managers and related
4353 * state machines.
4354 */
4355 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
4356 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
4357 if (!(BGE_IS_5705_PLUS(sc)))
4358 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
4359 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
4360 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
4361 if (!(BGE_IS_5705_PLUS(sc))) {
4362 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
4363 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4364 }
4365
4366 bge_reset(sc);
4367 bge_sig_legacy(sc, BGE_RESET_STOP);
4368 bge_sig_post_reset(sc, BGE_RESET_STOP);
4369
4370 /*
4371 * Keep the ASF firmware running if up.
4372 */
4373 if (sc->bge_asf_mode & ASF_STACKUP)
4374 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4375 else
4376 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4377
4378 /* Free the RX lists. */
4379 bge_free_rx_ring_std(sc);
4380
4381 /* Free jumbo RX list. */
4382 if (BGE_IS_JUMBO_CAPABLE(sc))
4383 bge_free_rx_ring_jumbo(sc);
4384
4385 /* Free TX buffers. */
4386 bge_free_tx_ring(sc);
4387
4388 /*
4389 * Isolate/power down the PHY, but leave the media selection
4390 * unchanged so that things will be put back to normal when
4391 * we bring the interface back up.
4392 */
4393 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4394 itmp = ifp->if_flags;
4395 ifp->if_flags |= IFF_UP;
4396 /*
4397 * If we are called from bge_detach(), mii is already NULL.
4398 */
4399 if (mii != NULL) {
4400 ifm = mii->mii_media.ifm_cur;
4401 mtmp = ifm->ifm_media;
4402 ifm->ifm_media = IFM_ETHER | IFM_NONE;
4403 mii_mediachg(mii);
4404 ifm->ifm_media = mtmp;
4405 }
4406 ifp->if_flags = itmp;
4407 }
4408
4409 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
4410
4411 /* Clear MAC's link state (PHY may still have link UP). */
4412 if (bootverbose && sc->bge_link)
4413 if_printf(sc->bge_ifp, "link DOWN\n");
4414 sc->bge_link = 0;
4415
4416 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4417 }
4418
4419 /*
4420 * Stop all chip I/O so that the kernel's probe routines don't
4421 * get confused by errant DMAs when rebooting.
4422 */
4423 static int
4424 bge_shutdown(device_t dev)
4425 {
4426 struct bge_softc *sc;
4427
4428 sc = device_get_softc(dev);
4429 BGE_LOCK(sc);
4430 bge_stop(sc);
4431 bge_reset(sc);
4432 BGE_UNLOCK(sc);
4433
4434 return (0);
4435 }
4436
4437 static int
4438 bge_suspend(device_t dev)
4439 {
4440 struct bge_softc *sc;
4441
4442 sc = device_get_softc(dev);
4443 BGE_LOCK(sc);
4444 bge_stop(sc);
4445 BGE_UNLOCK(sc);
4446
4447 return (0);
4448 }
4449
4450 static int
4451 bge_resume(device_t dev)
4452 {
4453 struct bge_softc *sc;
4454 struct ifnet *ifp;
4455
4456 sc = device_get_softc(dev);
4457 BGE_LOCK(sc);
4458 ifp = sc->bge_ifp;
4459 if (ifp->if_flags & IFF_UP) {
4460 bge_init_locked(sc);
4461 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4462 bge_start_locked(ifp);
4463 }
4464 BGE_UNLOCK(sc);
4465
4466 return (0);
4467 }
4468
4469 static void
4470 bge_link_upd(struct bge_softc *sc)
4471 {
4472 struct mii_data *mii;
4473 uint32_t link, status;
4474
4475 BGE_LOCK_ASSERT(sc);
4476
4477 /* Clear 'pending link event' flag. */
4478 sc->bge_link_evt = 0;
4479
4480 /*
4481 * Process link state changes.
4482 * Grrr. The link status word in the status block does
4483 * not work correctly on the BCM5700 rev AX and BX chips,
4484 * according to all available information. Hence, we have
4485 * to enable MII interrupts in order to properly obtain
4486 * async link changes. Unfortunately, this also means that
4487 * we have to read the MAC status register to detect link
4488 * changes, thereby adding an additional register access to
4489 * the interrupt handler.
4490 *
4491 * XXX: perhaps link state detection procedure used for
4492 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
4493 */
4494
4495 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4496 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
4497 status = CSR_READ_4(sc, BGE_MAC_STS);
4498 if (status & BGE_MACSTAT_MI_INTERRUPT) {
4499 mii = device_get_softc(sc->bge_miibus);
4500 mii_pollstat(mii);
4501 if (!sc->bge_link &&
4502 mii->mii_media_status & IFM_ACTIVE &&
4503 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4504 sc->bge_link++;
4505 if (bootverbose)
4506 if_printf(sc->bge_ifp, "link UP\n");
4507 } else if (sc->bge_link &&
4508 (!(mii->mii_media_status & IFM_ACTIVE) ||
4509 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4510 sc->bge_link = 0;
4511 if (bootverbose)
4512 if_printf(sc->bge_ifp, "link DOWN\n");
4513 }
4514
4515 /* Clear the interrupt. */
4516 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
4517 BGE_EVTENB_MI_INTERRUPT);
4518 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4519 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
4520 BRGPHY_INTRS);
4521 }
4522 return;
4523 }
4524
4525 if (sc->bge_flags & BGE_FLAG_TBI) {
4526 status = CSR_READ_4(sc, BGE_MAC_STS);
4527 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4528 if (!sc->bge_link) {
4529 sc->bge_link++;
4530 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
4531 BGE_CLRBIT(sc, BGE_MAC_MODE,
4532 BGE_MACMODE_TBI_SEND_CFGS);
4533 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4534 if (bootverbose)
4535 if_printf(sc->bge_ifp, "link UP\n");
4536 if_link_state_change(sc->bge_ifp,
4537 LINK_STATE_UP);
4538 }
4539 } else if (sc->bge_link) {
4540 sc->bge_link = 0;
4541 if (bootverbose)
4542 if_printf(sc->bge_ifp, "link DOWN\n");
4543 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
4544 }
4545 } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
4546 /*
4547 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
4548 * in status word always set. Workaround this bug by reading
4549 * PHY link status directly.
4550 */
4551 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
4552
4553 if (link != sc->bge_link ||
4554 sc->bge_asicrev == BGE_ASICREV_BCM5700) {
4555 mii = device_get_softc(sc->bge_miibus);
4556 mii_pollstat(mii);
4557 if (!sc->bge_link &&
4558 mii->mii_media_status & IFM_ACTIVE &&
4559 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4560 sc->bge_link++;
4561 if (bootverbose)
4562 if_printf(sc->bge_ifp, "link UP\n");
4563 } else if (sc->bge_link &&
4564 (!(mii->mii_media_status & IFM_ACTIVE) ||
4565 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4566 sc->bge_link = 0;
4567 if (bootverbose)
4568 if_printf(sc->bge_ifp, "link DOWN\n");
4569 }
4570 }
4571 } else {
4572 /*
4573 * Discard link events for MII/GMII controllers
4574 * if MI auto-polling is disabled.
4575 */
4576 }
4577
4578 /* Clear the attention. */
4579 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4580 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4581 BGE_MACSTAT_LINK_CHANGED);
4582 }
4583
4584 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
4585 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
4586 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
4587 desc)
4588
4589 static void
4590 bge_add_sysctls(struct bge_softc *sc)
4591 {
4592 struct sysctl_ctx_list *ctx;
4593 struct sysctl_oid_list *children, *schildren;
4594 struct sysctl_oid *tree;
4595
4596 ctx = device_get_sysctl_ctx(sc->bge_dev);
4597 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
4598
4599 #ifdef BGE_REGISTER_DEBUG
4600 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
4601 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
4602 "Debug Information");
4603
4604 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
4605 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
4606 "Register Read");
4607
4608 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
4609 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
4610 "Memory Read");
4611
4612 #endif
4613
4614 if (BGE_IS_5705_PLUS(sc))
4615 return;
4616
4617 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
4618 NULL, "BGE Statistics");
4619 schildren = children = SYSCTL_CHILDREN(tree);
4620 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
4621 children, COSFramesDroppedDueToFilters,
4622 "FramesDroppedDueToFilters");
4623 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
4624 children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
4625 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
4626 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
4627 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
4628 children, nicNoMoreRxBDs, "NoMoreRxBDs");
4629 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
4630 children, ifInDiscards, "InputDiscards");
4631 BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
4632 children, ifInErrors, "InputErrors");
4633 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
4634 children, nicRecvThresholdHit, "RecvThresholdHit");
4635 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
4636 children, nicDmaReadQueueFull, "DmaReadQueueFull");
4637 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
4638 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
4639 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
4640 children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
4641 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
4642 children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
4643 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
4644 children, nicRingStatusUpdate, "RingStatusUpdate");
4645 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
4646 children, nicInterrupts, "Interrupts");
4647 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
4648 children, nicAvoidedInterrupts, "AvoidedInterrupts");
4649 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
4650 children, nicSendThresholdHit, "SendThresholdHit");
4651
4652 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
4653 NULL, "BGE RX Statistics");
4654 children = SYSCTL_CHILDREN(tree);
4655 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
4656 children, rxstats.ifHCInOctets, "Octets");
4657 BGE_SYSCTL_STAT(sc, ctx, "Fragments",
4658 children, rxstats.etherStatsFragments, "Fragments");
4659 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
4660 children, rxstats.ifHCInUcastPkts, "UcastPkts");
4661 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
4662 children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
4663 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
4664 children, rxstats.dot3StatsFCSErrors, "FCSErrors");
4665 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
4666 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
4667 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
4668 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
4669 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
4670 children, rxstats.xoffPauseFramesReceived,
4671 "xoffPauseFramesReceived");
4672 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
4673 children, rxstats.macControlFramesReceived,
4674 "ControlFramesReceived");
4675 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
4676 children, rxstats.xoffStateEntered, "xoffStateEntered");
4677 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
4678 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
4679 BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
4680 children, rxstats.etherStatsJabbers, "Jabbers");
4681 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
4682 children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
4683 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
4684 children, rxstats.inRangeLengthError, "inRangeLengthError");
4685 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
4686 children, rxstats.outRangeLengthError, "outRangeLengthError");
4687
4688 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
4689 NULL, "BGE TX Statistics");
4690 children = SYSCTL_CHILDREN(tree);
4691 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
4692 children, txstats.ifHCOutOctets, "Octets");
4693 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
4694 children, txstats.etherStatsCollisions, "Collisions");
4695 BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
4696 children, txstats.outXonSent, "XonSent");
4697 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
4698 children, txstats.outXoffSent, "XoffSent");
4699 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
4700 children, txstats.flowControlDone, "flowControlDone");
4701 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
4702 children, txstats.dot3StatsInternalMacTransmitErrors,
4703 "InternalMacTransmitErrors");
4704 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
4705 children, txstats.dot3StatsSingleCollisionFrames,
4706 "SingleCollisionFrames");
4707 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
4708 children, txstats.dot3StatsMultipleCollisionFrames,
4709 "MultipleCollisionFrames");
4710 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
4711 children, txstats.dot3StatsDeferredTransmissions,
4712 "DeferredTransmissions");
4713 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
4714 children, txstats.dot3StatsExcessiveCollisions,
4715 "ExcessiveCollisions");
4716 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
4717 children, txstats.dot3StatsLateCollisions,
4718 "LateCollisions");
4719 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
4720 children, txstats.ifHCOutUcastPkts, "UcastPkts");
4721 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
4722 children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
4723 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
4724 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
4725 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
4726 children, txstats.dot3StatsCarrierSenseErrors,
4727 "CarrierSenseErrors");
4728 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
4729 children, txstats.ifOutDiscards, "Discards");
4730 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
4731 children, txstats.ifOutErrors, "Errors");
4732 }
4733
4734 static int
4735 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
4736 {
4737 struct bge_softc *sc;
4738 uint32_t result;
4739 int offset;
4740
4741 sc = (struct bge_softc *)arg1;
4742 offset = arg2;
4743 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
4744 offsetof(bge_hostaddr, bge_addr_lo));
4745 return (sysctl_handle_int(oidp, &result, 0, req));
4746 }
4747
4748 #ifdef BGE_REGISTER_DEBUG
4749 static int
4750 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4751 {
4752 struct bge_softc *sc;
4753 uint16_t *sbdata;
4754 int error;
4755 int result;
4756 int i, j;
4757
4758 result = -1;
4759 error = sysctl_handle_int(oidp, &result, 0, req);
4760 if (error || (req->newptr == NULL))
4761 return (error);
4762
4763 if (result == 1) {
4764 sc = (struct bge_softc *)arg1;
4765
4766 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
4767 printf("Status Block:\n");
4768 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) {
4769 printf("%06x:", i);
4770 for (j = 0; j < 8; j++) {
4771 printf(" %04x", sbdata[i]);
4772 i += 4;
4773 }
4774 printf("\n");
4775 }
4776
4777 printf("Registers:\n");
4778 for (i = 0x800; i < 0xA00; ) {
4779 printf("%06x:", i);
4780 for (j = 0; j < 8; j++) {
4781 printf(" %08x", CSR_READ_4(sc, i));
4782 i += 4;
4783 }
4784 printf("\n");
4785 }
4786
4787 printf("Hardware Flags:\n");
4788 if (BGE_IS_5755_PLUS(sc))
4789 printf(" - 5755 Plus\n");
4790 if (BGE_IS_575X_PLUS(sc))
4791 printf(" - 575X Plus\n");
4792 if (BGE_IS_5705_PLUS(sc))
4793 printf(" - 5705 Plus\n");
4794 if (BGE_IS_5714_FAMILY(sc))
4795 printf(" - 5714 Family\n");
4796 if (BGE_IS_5700_FAMILY(sc))
4797 printf(" - 5700 Family\n");
4798 if (sc->bge_flags & BGE_FLAG_JUMBO)
4799 printf(" - Supports Jumbo Frames\n");
4800 if (sc->bge_flags & BGE_FLAG_PCIX)
4801 printf(" - PCI-X Bus\n");
4802 if (sc->bge_flags & BGE_FLAG_PCIE)
4803 printf(" - PCI Express Bus\n");
4804 if (sc->bge_flags & BGE_FLAG_NO_3LED)
4805 printf(" - No 3 LEDs\n");
4806 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
4807 printf(" - RX Alignment Bug\n");
4808 }
4809
4810 return (error);
4811 }
4812
4813 static int
4814 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
4815 {
4816 struct bge_softc *sc;
4817 int error;
4818 uint16_t result;
4819 uint32_t val;
4820
4821 result = -1;
4822 error = sysctl_handle_int(oidp, &result, 0, req);
4823 if (error || (req->newptr == NULL))
4824 return (error);
4825
4826 if (result < 0x8000) {
4827 sc = (struct bge_softc *)arg1;
4828 val = CSR_READ_4(sc, result);
4829 printf("reg 0x%06X = 0x%08X\n", result, val);
4830 }
4831
4832 return (error);
4833 }
4834
4835 static int
4836 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
4837 {
4838 struct bge_softc *sc;
4839 int error;
4840 uint16_t result;
4841 uint32_t val;
4842
4843 result = -1;
4844 error = sysctl_handle_int(oidp, &result, 0, req);
4845 if (error || (req->newptr == NULL))
4846 return (error);
4847
4848 if (result < 0x8000) {
4849 sc = (struct bge_softc *)arg1;
4850 val = bge_readmem_ind(sc, result);
4851 printf("mem 0x%06X = 0x%08X\n", result, val);
4852 }
4853
4854 return (error);
4855 }
4856 #endif
4857
4858 static int
4859 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
4860 {
4861
4862 if (sc->bge_flags & BGE_FLAG_EADDR)
4863 return (1);
4864
4865 #ifdef __sparc64__
4866 OF_getetheraddr(sc->bge_dev, ether_addr);
4867 return (0);
4868 #endif
4869 return (1);
4870 }
4871
4872 static int
4873 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
4874 {
4875 uint32_t mac_addr;
4876
4877 mac_addr = bge_readmem_ind(sc, 0x0c14);
4878 if ((mac_addr >> 16) == 0x484b) {
4879 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4880 ether_addr[1] = (uint8_t)mac_addr;
4881 mac_addr = bge_readmem_ind(sc, 0x0c18);
4882 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4883 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4884 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4885 ether_addr[5] = (uint8_t)mac_addr;
4886 return (0);
4887 }
4888 return (1);
4889 }
4890
4891 static int
4892 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
4893 {
4894 int mac_offset = BGE_EE_MAC_OFFSET;
4895
4896 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
4897 mac_offset = BGE_EE_MAC_OFFSET_5906;
4898
4899 return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
4900 ETHER_ADDR_LEN));
4901 }
4902
4903 static int
4904 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
4905 {
4906
4907 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
4908 return (1);
4909
4910 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4911 ETHER_ADDR_LEN));
4912 }
4913
4914 static int
4915 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
4916 {
4917 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
4918 /* NOTE: Order is critical */
4919 bge_get_eaddr_fw,
4920 bge_get_eaddr_mem,
4921 bge_get_eaddr_nvram,
4922 bge_get_eaddr_eeprom,
4923 NULL
4924 };
4925 const bge_eaddr_fcn_t *func;
4926
4927 for (func = bge_eaddr_funcs; *func != NULL; ++func) {
4928 if ((*func)(sc, eaddr) == 0)
4929 break;
4930 }
4931 return (*func == NULL ? ENXIO : 0);
4932 }
Cache object: 569c92da5b81c9c5e7ac7778d4af9760
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