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sys/dev/bge/if_bge.c
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1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: releng/5.0/sys/dev/bge/if_bge.c 108915 2003-01-08 01:38:37Z jdp $ 34 */ 35 36 /* 37 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Engineer, Wind River Systems 41 */ 42 43 /* 44 * The Broadcom BCM5700 is based on technology originally developed by 45 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 46 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 47 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 48 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 49 * frames, highly configurable RX filtering, and 16 RX and TX queues 50 * (which, along with RX filter rules, can be used for QOS applications). 51 * Other features, such as TCP segmentation, may be available as part 52 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 53 * firmware images can be stored in hardware and need not be compiled 54 * into the driver. 55 * 56 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 57 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 58 * 59 * The BCM5701 is a single-chip solution incorporating both the BCM5700 60 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 61 * does not support external SSRAM. 62 * 63 * Broadcom also produces a variation of the BCM5700 under the "Altima" 64 * brand name, which is functionally similar but lacks PCI-X support. 65 * 66 * Without external SSRAM, you can only have at most 4 TX rings, 67 * and the use of the mini RX ring is disabled. This seems to imply 68 * that these features are simply not available on the BCM5701. As a 69 * result, this driver does not implement any support for the mini RX 70 * ring. 71 */ 72 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/sockio.h> 76 #include <sys/mbuf.h> 77 #include <sys/malloc.h> 78 #include <sys/kernel.h> 79 #include <sys/socket.h> 80 #include <sys/queue.h> 81 82 #include <net/if.h> 83 #include <net/if_arp.h> 84 #include <net/ethernet.h> 85 #include <net/if_dl.h> 86 #include <net/if_media.h> 87 88 #include <net/bpf.h> 89 90 #include <net/if_types.h> 91 #include <net/if_vlan_var.h> 92 93 #include <netinet/in_systm.h> 94 #include <netinet/in.h> 95 #include <netinet/ip.h> 96 97 #include <vm/vm.h> /* for vtophys */ 98 #include <vm/pmap.h> /* for vtophys */ 99 #include <machine/clock.h> /* for DELAY */ 100 #include <machine/bus_memio.h> 101 #include <machine/bus.h> 102 #include <machine/resource.h> 103 #include <sys/bus.h> 104 #include <sys/rman.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 #include <dev/mii/miidevs.h> 109 #include <dev/mii/brgphyreg.h> 110 111 #include <pci/pcireg.h> 112 #include <pci/pcivar.h> 113 114 #include <dev/bge/if_bgereg.h> 115 116 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 117 118 MODULE_DEPEND(bge, miibus, 1, 1, 1); 119 120 /* "controller miibus0" required. See GENERIC if you get errors here. */ 121 #include "miibus_if.h" 122 123 #if !defined(lint) 124 static const char rcsid[] = 125 "$FreeBSD: releng/5.0/sys/dev/bge/if_bge.c 108915 2003-01-08 01:38:37Z jdp $"; 126 #endif 127 128 /* 129 * Various supported device vendors/types and their names. Note: the 130 * spec seems to indicate that the hardware still has Alteon's vendor 131 * ID burned into it, though it will always be overriden by the vendor 132 * ID in the EEPROM. Just to be safe, we cover all possibilities. 133 */ 134 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */ 135 136 static struct bge_type bge_devs[] = { 137 { ALT_VENDORID, ALT_DEVICEID_BCM5700, 138 "Broadcom BCM5700 Gigabit Ethernet" }, 139 { ALT_VENDORID, ALT_DEVICEID_BCM5701, 140 "Broadcom BCM5701 Gigabit Ethernet" }, 141 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700, 142 "Broadcom BCM5700 Gigabit Ethernet" }, 143 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701, 144 "Broadcom BCM5701 Gigabit Ethernet" }, 145 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X, 146 "Broadcom BCM5702X Gigabit Ethernet" }, 147 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X, 148 "Broadcom BCM5703X Gigabit Ethernet" }, 149 { SK_VENDORID, SK_DEVICEID_ALTIMA, 150 "SysKonnect Gigabit Ethernet" }, 151 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000, 152 "Altima AC1000 Gigabit Ethernet" }, 153 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100, 154 "Altima AC9100 Gigabit Ethernet" }, 155 { 0, 0, NULL } 156 }; 157 158 static int bge_probe (device_t); 159 static int bge_attach (device_t); 160 static int bge_detach (device_t); 161 static void bge_release_resources 162 (struct bge_softc *); 163 static void bge_txeof (struct bge_softc *); 164 static void bge_rxeof (struct bge_softc *); 165 166 static void bge_tick (void *); 167 static void bge_stats_update (struct bge_softc *); 168 static int bge_encap (struct bge_softc *, struct mbuf *, 169 u_int32_t *); 170 171 static void bge_intr (void *); 172 static void bge_start (struct ifnet *); 173 static int bge_ioctl (struct ifnet *, u_long, caddr_t); 174 static void bge_init (void *); 175 static void bge_stop (struct bge_softc *); 176 static void bge_watchdog (struct ifnet *); 177 static void bge_shutdown (device_t); 178 static int bge_ifmedia_upd (struct ifnet *); 179 static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 180 181 static u_int8_t bge_eeprom_getbyte (struct bge_softc *, int, u_int8_t *); 182 static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int); 183 184 static u_int32_t bge_crc (caddr_t); 185 static void bge_setmulti (struct bge_softc *); 186 187 static void bge_handle_events (struct bge_softc *); 188 static int bge_alloc_jumbo_mem (struct bge_softc *); 189 static void bge_free_jumbo_mem (struct bge_softc *); 190 static void *bge_jalloc (struct bge_softc *); 191 static void bge_jfree (void *, void *); 192 static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *); 193 static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *); 194 static int bge_init_rx_ring_std (struct bge_softc *); 195 static void bge_free_rx_ring_std (struct bge_softc *); 196 static int bge_init_rx_ring_jumbo (struct bge_softc *); 197 static void bge_free_rx_ring_jumbo (struct bge_softc *); 198 static void bge_free_tx_ring (struct bge_softc *); 199 static int bge_init_tx_ring (struct bge_softc *); 200 201 static int bge_chipinit (struct bge_softc *); 202 static int bge_blockinit (struct bge_softc *); 203 204 #ifdef notdef 205 static u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 206 static void bge_vpd_read_res (struct bge_softc *, struct vpd_res *, int); 207 static void bge_vpd_read (struct bge_softc *); 208 #endif 209 210 static u_int32_t bge_readmem_ind 211 (struct bge_softc *, int); 212 static void bge_writemem_ind (struct bge_softc *, int, int); 213 #ifdef notdef 214 static u_int32_t bge_readreg_ind 215 (struct bge_softc *, int); 216 #endif 217 static void bge_writereg_ind (struct bge_softc *, int, int); 218 219 static int bge_miibus_readreg (device_t, int, int); 220 static int bge_miibus_writereg (device_t, int, int, int); 221 static void bge_miibus_statchg (device_t); 222 223 static void bge_reset (struct bge_softc *); 224 static void bge_phy_hack (struct bge_softc *); 225 226 static device_method_t bge_methods[] = { 227 /* Device interface */ 228 DEVMETHOD(device_probe, bge_probe), 229 DEVMETHOD(device_attach, bge_attach), 230 DEVMETHOD(device_detach, bge_detach), 231 DEVMETHOD(device_shutdown, bge_shutdown), 232 233 /* bus interface */ 234 DEVMETHOD(bus_print_child, bus_generic_print_child), 235 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 236 237 /* MII interface */ 238 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 239 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 240 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 241 242 { 0, 0 } 243 }; 244 245 static driver_t bge_driver = { 246 "bge", 247 bge_methods, 248 sizeof(struct bge_softc) 249 }; 250 251 static devclass_t bge_devclass; 252 253 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0); 254 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 255 256 static u_int32_t 257 bge_readmem_ind(sc, off) 258 struct bge_softc *sc; 259 int off; 260 { 261 device_t dev; 262 263 dev = sc->bge_dev; 264 265 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 266 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 267 } 268 269 static void 270 bge_writemem_ind(sc, off, val) 271 struct bge_softc *sc; 272 int off, val; 273 { 274 device_t dev; 275 276 dev = sc->bge_dev; 277 278 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 279 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 280 281 return; 282 } 283 284 #ifdef notdef 285 static u_int32_t 286 bge_readreg_ind(sc, off) 287 struct bge_softc *sc; 288 int off; 289 { 290 device_t dev; 291 292 dev = sc->bge_dev; 293 294 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 295 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 296 } 297 #endif 298 299 static void 300 bge_writereg_ind(sc, off, val) 301 struct bge_softc *sc; 302 int off, val; 303 { 304 device_t dev; 305 306 dev = sc->bge_dev; 307 308 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 309 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 310 311 return; 312 } 313 314 #ifdef notdef 315 static u_int8_t 316 bge_vpd_readbyte(sc, addr) 317 struct bge_softc *sc; 318 int addr; 319 { 320 int i; 321 device_t dev; 322 u_int32_t val; 323 324 dev = sc->bge_dev; 325 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 326 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 327 DELAY(10); 328 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 329 break; 330 } 331 332 if (i == BGE_TIMEOUT) { 333 printf("bge%d: VPD read timed out\n", sc->bge_unit); 334 return(0); 335 } 336 337 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 338 339 return((val >> ((addr % 4) * 8)) & 0xFF); 340 } 341 342 static void 343 bge_vpd_read_res(sc, res, addr) 344 struct bge_softc *sc; 345 struct vpd_res *res; 346 int addr; 347 { 348 int i; 349 u_int8_t *ptr; 350 351 ptr = (u_int8_t *)res; 352 for (i = 0; i < sizeof(struct vpd_res); i++) 353 ptr[i] = bge_vpd_readbyte(sc, i + addr); 354 355 return; 356 } 357 358 static void 359 bge_vpd_read(sc) 360 struct bge_softc *sc; 361 { 362 int pos = 0, i; 363 struct vpd_res res; 364 365 if (sc->bge_vpd_prodname != NULL) 366 free(sc->bge_vpd_prodname, M_DEVBUF); 367 if (sc->bge_vpd_readonly != NULL) 368 free(sc->bge_vpd_readonly, M_DEVBUF); 369 sc->bge_vpd_prodname = NULL; 370 sc->bge_vpd_readonly = NULL; 371 372 bge_vpd_read_res(sc, &res, pos); 373 374 if (res.vr_id != VPD_RES_ID) { 375 printf("bge%d: bad VPD resource id: expected %x got %x\n", 376 sc->bge_unit, VPD_RES_ID, res.vr_id); 377 return; 378 } 379 380 pos += sizeof(res); 381 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 382 for (i = 0; i < res.vr_len; i++) 383 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 384 sc->bge_vpd_prodname[i] = '\0'; 385 pos += i; 386 387 bge_vpd_read_res(sc, &res, pos); 388 389 if (res.vr_id != VPD_RES_READ) { 390 printf("bge%d: bad VPD resource id: expected %x got %x\n", 391 sc->bge_unit, VPD_RES_READ, res.vr_id); 392 return; 393 } 394 395 pos += sizeof(res); 396 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 397 for (i = 0; i < res.vr_len + 1; i++) 398 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 399 400 return; 401 } 402 #endif 403 404 /* 405 * Read a byte of data stored in the EEPROM at address 'addr.' The 406 * BCM570x supports both the traditional bitbang interface and an 407 * auto access interface for reading the EEPROM. We use the auto 408 * access method. 409 */ 410 static u_int8_t 411 bge_eeprom_getbyte(sc, addr, dest) 412 struct bge_softc *sc; 413 int addr; 414 u_int8_t *dest; 415 { 416 int i; 417 u_int32_t byte = 0; 418 419 /* 420 * Enable use of auto EEPROM access so we can avoid 421 * having to use the bitbang method. 422 */ 423 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 424 425 /* Reset the EEPROM, load the clock period. */ 426 CSR_WRITE_4(sc, BGE_EE_ADDR, 427 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 428 DELAY(20); 429 430 /* Issue the read EEPROM command. */ 431 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 432 433 /* Wait for completion */ 434 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 435 DELAY(10); 436 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 437 break; 438 } 439 440 if (i == BGE_TIMEOUT) { 441 printf("bge%d: eeprom read timed out\n", sc->bge_unit); 442 return(0); 443 } 444 445 /* Get result. */ 446 byte = CSR_READ_4(sc, BGE_EE_DATA); 447 448 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 449 450 return(0); 451 } 452 453 /* 454 * Read a sequence of bytes from the EEPROM. 455 */ 456 static int 457 bge_read_eeprom(sc, dest, off, cnt) 458 struct bge_softc *sc; 459 caddr_t dest; 460 int off; 461 int cnt; 462 { 463 int err = 0, i; 464 u_int8_t byte = 0; 465 466 for (i = 0; i < cnt; i++) { 467 err = bge_eeprom_getbyte(sc, off + i, &byte); 468 if (err) 469 break; 470 *(dest + i) = byte; 471 } 472 473 return(err ? 1 : 0); 474 } 475 476 static int 477 bge_miibus_readreg(dev, phy, reg) 478 device_t dev; 479 int phy, reg; 480 { 481 struct bge_softc *sc; 482 struct ifnet *ifp; 483 u_int32_t val; 484 int i; 485 486 sc = device_get_softc(dev); 487 ifp = &sc->arpcom.ac_if; 488 489 if (phy != 1) 490 switch(sc->bge_asicrev) { 491 case BGE_ASICREV_BCM5701_B5: 492 case BGE_ASICREV_BCM5703_A2: 493 return(0); 494 } 495 496 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 497 BGE_MIPHY(phy)|BGE_MIREG(reg)); 498 499 for (i = 0; i < BGE_TIMEOUT; i++) { 500 val = CSR_READ_4(sc, BGE_MI_COMM); 501 if (!(val & BGE_MICOMM_BUSY)) 502 break; 503 } 504 505 if (i == BGE_TIMEOUT) { 506 printf("bge%d: PHY read timed out\n", sc->bge_unit); 507 return(0); 508 } 509 510 val = CSR_READ_4(sc, BGE_MI_COMM); 511 512 if (val & BGE_MICOMM_READFAIL) 513 return(0); 514 515 return(val & 0xFFFF); 516 } 517 518 static int 519 bge_miibus_writereg(dev, phy, reg, val) 520 device_t dev; 521 int phy, reg, val; 522 { 523 struct bge_softc *sc; 524 int i; 525 526 sc = device_get_softc(dev); 527 528 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 529 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 530 531 for (i = 0; i < BGE_TIMEOUT; i++) { 532 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 533 break; 534 } 535 536 if (i == BGE_TIMEOUT) { 537 printf("bge%d: PHY read timed out\n", sc->bge_unit); 538 return(0); 539 } 540 541 return(0); 542 } 543 544 static void 545 bge_miibus_statchg(dev) 546 device_t dev; 547 { 548 struct bge_softc *sc; 549 struct mii_data *mii; 550 551 sc = device_get_softc(dev); 552 mii = device_get_softc(sc->bge_miibus); 553 554 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 555 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 556 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 557 } else { 558 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 559 } 560 561 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 562 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 563 } else { 564 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 565 } 566 567 bge_phy_hack(sc); 568 569 return; 570 } 571 572 /* 573 * Handle events that have triggered interrupts. 574 */ 575 static void 576 bge_handle_events(sc) 577 struct bge_softc *sc; 578 { 579 580 return; 581 } 582 583 /* 584 * Memory management for jumbo frames. 585 */ 586 587 static int 588 bge_alloc_jumbo_mem(sc) 589 struct bge_softc *sc; 590 { 591 caddr_t ptr; 592 register int i; 593 struct bge_jpool_entry *entry; 594 595 /* Grab a big chunk o' storage. */ 596 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF, 597 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 598 599 if (sc->bge_cdata.bge_jumbo_buf == NULL) { 600 printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit); 601 return(ENOBUFS); 602 } 603 604 SLIST_INIT(&sc->bge_jfree_listhead); 605 SLIST_INIT(&sc->bge_jinuse_listhead); 606 607 /* 608 * Now divide it up into 9K pieces and save the addresses 609 * in an array. 610 */ 611 ptr = sc->bge_cdata.bge_jumbo_buf; 612 for (i = 0; i < BGE_JSLOTS; i++) { 613 sc->bge_cdata.bge_jslots[i] = ptr; 614 ptr += BGE_JLEN; 615 entry = malloc(sizeof(struct bge_jpool_entry), 616 M_DEVBUF, M_NOWAIT); 617 if (entry == NULL) { 618 contigfree(sc->bge_cdata.bge_jumbo_buf, 619 BGE_JMEM, M_DEVBUF); 620 sc->bge_cdata.bge_jumbo_buf = NULL; 621 printf("bge%d: no memory for jumbo " 622 "buffer queue!\n", sc->bge_unit); 623 return(ENOBUFS); 624 } 625 entry->slot = i; 626 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 627 entry, jpool_entries); 628 } 629 630 return(0); 631 } 632 633 static void 634 bge_free_jumbo_mem(sc) 635 struct bge_softc *sc; 636 { 637 int i; 638 struct bge_jpool_entry *entry; 639 640 for (i = 0; i < BGE_JSLOTS; i++) { 641 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 642 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 643 free(entry, M_DEVBUF); 644 } 645 646 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF); 647 648 return; 649 } 650 651 /* 652 * Allocate a jumbo buffer. 653 */ 654 static void * 655 bge_jalloc(sc) 656 struct bge_softc *sc; 657 { 658 struct bge_jpool_entry *entry; 659 660 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 661 662 if (entry == NULL) { 663 printf("bge%d: no free jumbo buffers\n", sc->bge_unit); 664 return(NULL); 665 } 666 667 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 668 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 669 return(sc->bge_cdata.bge_jslots[entry->slot]); 670 } 671 672 /* 673 * Release a jumbo buffer. 674 */ 675 static void 676 bge_jfree(buf, args) 677 void *buf; 678 void *args; 679 { 680 struct bge_jpool_entry *entry; 681 struct bge_softc *sc; 682 int i; 683 684 /* Extract the softc struct pointer. */ 685 sc = (struct bge_softc *)args; 686 687 if (sc == NULL) 688 panic("bge_jfree: can't find softc pointer!"); 689 690 /* calculate the slot this buffer belongs to */ 691 692 i = ((vm_offset_t)buf 693 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 694 695 if ((i < 0) || (i >= BGE_JSLOTS)) 696 panic("bge_jfree: asked to free buffer that we don't manage!"); 697 698 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 699 if (entry == NULL) 700 panic("bge_jfree: buffer not in use!"); 701 entry->slot = i; 702 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 703 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 704 705 return; 706 } 707 708 709 /* 710 * Intialize a standard receive ring descriptor. 711 */ 712 static int 713 bge_newbuf_std(sc, i, m) 714 struct bge_softc *sc; 715 int i; 716 struct mbuf *m; 717 { 718 struct mbuf *m_new = NULL; 719 struct bge_rx_bd *r; 720 721 if (m == NULL) { 722 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 723 if (m_new == NULL) { 724 return(ENOBUFS); 725 } 726 727 MCLGET(m_new, M_DONTWAIT); 728 if (!(m_new->m_flags & M_EXT)) { 729 m_freem(m_new); 730 return(ENOBUFS); 731 } 732 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 733 } else { 734 m_new = m; 735 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 736 m_new->m_data = m_new->m_ext.ext_buf; 737 } 738 739 if (!sc->bge_rx_alignment_bug) 740 m_adj(m_new, ETHER_ALIGN); 741 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 742 r = &sc->bge_rdata->bge_rx_std_ring[i]; 743 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t)); 744 r->bge_flags = BGE_RXBDFLAG_END; 745 r->bge_len = m_new->m_len; 746 r->bge_idx = i; 747 748 return(0); 749 } 750 751 /* 752 * Initialize a jumbo receive ring descriptor. This allocates 753 * a jumbo buffer from the pool managed internally by the driver. 754 */ 755 static int 756 bge_newbuf_jumbo(sc, i, m) 757 struct bge_softc *sc; 758 int i; 759 struct mbuf *m; 760 { 761 struct mbuf *m_new = NULL; 762 struct bge_rx_bd *r; 763 764 if (m == NULL) { 765 caddr_t *buf = NULL; 766 767 /* Allocate the mbuf. */ 768 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 769 if (m_new == NULL) { 770 return(ENOBUFS); 771 } 772 773 /* Allocate the jumbo buffer */ 774 buf = bge_jalloc(sc); 775 if (buf == NULL) { 776 m_freem(m_new); 777 printf("bge%d: jumbo allocation failed " 778 "-- packet dropped!\n", sc->bge_unit); 779 return(ENOBUFS); 780 } 781 782 /* Attach the buffer to the mbuf. */ 783 m_new->m_data = (void *) buf; 784 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 785 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree, 786 (struct bge_softc *)sc, 0, EXT_NET_DRV); 787 } else { 788 m_new = m; 789 m_new->m_data = m_new->m_ext.ext_buf; 790 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 791 } 792 793 if (!sc->bge_rx_alignment_bug) 794 m_adj(m_new, ETHER_ALIGN); 795 /* Set up the descriptor. */ 796 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 797 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 798 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t)); 799 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 800 r->bge_len = m_new->m_len; 801 r->bge_idx = i; 802 803 return(0); 804 } 805 806 /* 807 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 808 * that's 1MB or memory, which is a lot. For now, we fill only the first 809 * 256 ring entries and hope that our CPU is fast enough to keep up with 810 * the NIC. 811 */ 812 static int 813 bge_init_rx_ring_std(sc) 814 struct bge_softc *sc; 815 { 816 int i; 817 818 for (i = 0; i < BGE_SSLOTS; i++) { 819 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 820 return(ENOBUFS); 821 }; 822 823 sc->bge_std = i - 1; 824 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 825 826 return(0); 827 } 828 829 static void 830 bge_free_rx_ring_std(sc) 831 struct bge_softc *sc; 832 { 833 int i; 834 835 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 836 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 837 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 838 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 839 } 840 bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i], 841 sizeof(struct bge_rx_bd)); 842 } 843 844 return; 845 } 846 847 static int 848 bge_init_rx_ring_jumbo(sc) 849 struct bge_softc *sc; 850 { 851 int i; 852 struct bge_rcb *rcb; 853 854 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 855 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 856 return(ENOBUFS); 857 }; 858 859 sc->bge_jumbo = i - 1; 860 861 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 862 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 863 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 864 865 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 866 867 return(0); 868 } 869 870 static void 871 bge_free_rx_ring_jumbo(sc) 872 struct bge_softc *sc; 873 { 874 int i; 875 876 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 877 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 878 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 879 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 880 } 881 bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 882 sizeof(struct bge_rx_bd)); 883 } 884 885 return; 886 } 887 888 static void 889 bge_free_tx_ring(sc) 890 struct bge_softc *sc; 891 { 892 int i; 893 894 if (sc->bge_rdata->bge_tx_ring == NULL) 895 return; 896 897 for (i = 0; i < BGE_TX_RING_CNT; i++) { 898 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 899 m_freem(sc->bge_cdata.bge_tx_chain[i]); 900 sc->bge_cdata.bge_tx_chain[i] = NULL; 901 } 902 bzero((char *)&sc->bge_rdata->bge_tx_ring[i], 903 sizeof(struct bge_tx_bd)); 904 } 905 906 return; 907 } 908 909 static int 910 bge_init_tx_ring(sc) 911 struct bge_softc *sc; 912 { 913 sc->bge_txcnt = 0; 914 sc->bge_tx_saved_considx = 0; 915 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 916 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 917 918 return(0); 919 } 920 921 #define BGE_POLY 0xEDB88320 922 923 static u_int32_t 924 bge_crc(addr) 925 caddr_t addr; 926 { 927 u_int32_t idx, bit, data, crc; 928 929 /* Compute CRC for the address value. */ 930 crc = 0xFFFFFFFF; /* initial value */ 931 932 for (idx = 0; idx < 6; idx++) { 933 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 934 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 935 } 936 937 return(crc & 0x7F); 938 } 939 940 static void 941 bge_setmulti(sc) 942 struct bge_softc *sc; 943 { 944 struct ifnet *ifp; 945 struct ifmultiaddr *ifma; 946 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 947 int h, i; 948 949 ifp = &sc->arpcom.ac_if; 950 951 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 952 for (i = 0; i < 4; i++) 953 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 954 return; 955 } 956 957 /* First, zot all the existing filters. */ 958 for (i = 0; i < 4; i++) 959 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 960 961 /* Now program new ones. */ 962 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 963 if (ifma->ifma_addr->sa_family != AF_LINK) 964 continue; 965 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 966 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 967 } 968 969 for (i = 0; i < 4; i++) 970 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 971 972 return; 973 } 974 975 /* 976 * Do endian, PCI and DMA initialization. Also check the on-board ROM 977 * self-test results. 978 */ 979 static int 980 bge_chipinit(sc) 981 struct bge_softc *sc; 982 { 983 int i; 984 985 /* Set endianness before we access any non-PCI registers. */ 986 #if BYTE_ORDER == BIG_ENDIAN 987 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 988 BGE_BIGENDIAN_INIT, 4); 989 #else 990 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 991 BGE_LITTLEENDIAN_INIT, 4); 992 #endif 993 994 /* 995 * Check the 'ROM failed' bit on the RX CPU to see if 996 * self-tests passed. 997 */ 998 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 999 printf("bge%d: RX CPU self-diagnostics failed!\n", 1000 sc->bge_unit); 1001 return(ENODEV); 1002 } 1003 1004 /* Clear the MAC control register */ 1005 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1006 1007 /* 1008 * Clear the MAC statistics block in the NIC's 1009 * internal memory. 1010 */ 1011 for (i = BGE_STATS_BLOCK; 1012 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1013 BGE_MEMWIN_WRITE(sc, i, 0); 1014 1015 for (i = BGE_STATUS_BLOCK; 1016 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1017 BGE_MEMWIN_WRITE(sc, i, 0); 1018 1019 /* Set up the PCI DMA control register. */ 1020 if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 1021 BGE_PCISTATE_PCI_BUSMODE) { 1022 /* Conventional PCI bus */ 1023 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1024 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x3F000F, 4); 1025 } else { 1026 /* PCI-X bus */ 1027 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1028 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x1B000F, 4); 1029 } 1030 1031 /* 1032 * Set up general mode register. 1033 */ 1034 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 1035 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1036 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1037 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| 1038 BGE_MODECTL_RX_NO_PHDR_CSUM); 1039 1040 /* 1041 * Disable memory write invalidate. Apparently it is not supported 1042 * properly by these devices. 1043 */ 1044 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1045 1046 #ifdef __brokenalpha__ 1047 /* 1048 * Must insure that we do not cross an 8K (bytes) boundary 1049 * for DMA reads. Our highest limit is 1K bytes. This is a 1050 * restriction on some ALPHA platforms with early revision 1051 * 21174 PCI chipsets, such as the AlphaPC 164lx 1052 */ 1053 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1054 BGE_PCI_READ_BNDRY_1024BYTES, 4); 1055 #endif 1056 1057 /* Set the timer prescaler (always 66Mhz) */ 1058 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1059 1060 return(0); 1061 } 1062 1063 static int 1064 bge_blockinit(sc) 1065 struct bge_softc *sc; 1066 { 1067 struct bge_rcb *rcb; 1068 volatile struct bge_rcb *vrcb; 1069 int i; 1070 1071 /* 1072 * Initialize the memory window pointer register so that 1073 * we can access the first 32K of internal NIC RAM. This will 1074 * allow us to set up the TX send ring RCBs and the RX return 1075 * ring RCBs, plus other things which live in NIC memory. 1076 */ 1077 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1078 1079 /* Configure mbuf memory pool */ 1080 if (sc->bge_extram) { 1081 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM); 1082 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1083 } else { 1084 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1085 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1086 } 1087 1088 /* Configure DMA resource pool */ 1089 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS); 1090 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1091 1092 /* Configure mbuf pool watermarks */ 1093 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1094 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1095 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1096 1097 /* Configure DMA resource watermarks */ 1098 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1099 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1100 1101 /* Enable buffer manager */ 1102 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1103 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1104 1105 /* Poll for buffer manager start indication */ 1106 for (i = 0; i < BGE_TIMEOUT; i++) { 1107 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1108 break; 1109 DELAY(10); 1110 } 1111 1112 if (i == BGE_TIMEOUT) { 1113 printf("bge%d: buffer manager failed to start\n", 1114 sc->bge_unit); 1115 return(ENXIO); 1116 } 1117 1118 /* Enable flow-through queues */ 1119 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1120 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1121 1122 /* Wait until queue initialization is complete */ 1123 for (i = 0; i < BGE_TIMEOUT; i++) { 1124 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1125 break; 1126 DELAY(10); 1127 } 1128 1129 if (i == BGE_TIMEOUT) { 1130 printf("bge%d: flow-through queue init failed\n", 1131 sc->bge_unit); 1132 return(ENXIO); 1133 } 1134 1135 /* Initialize the standard RX ring control block */ 1136 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1137 BGE_HOSTADDR(rcb->bge_hostaddr) = 1138 vtophys(&sc->bge_rdata->bge_rx_std_ring); 1139 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1140 if (sc->bge_extram) 1141 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1142 else 1143 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1144 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1145 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1146 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1147 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1148 1149 /* 1150 * Initialize the jumbo RX ring control block 1151 * We set the 'ring disabled' bit in the flags 1152 * field until we're actually ready to start 1153 * using this ring (i.e. once we set the MTU 1154 * high enough to require it). 1155 */ 1156 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1157 BGE_HOSTADDR(rcb->bge_hostaddr) = 1158 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring); 1159 rcb->bge_maxlen_flags = 1160 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, BGE_RCB_FLAG_RING_DISABLED); 1161 if (sc->bge_extram) 1162 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1163 else 1164 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1165 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1166 rcb->bge_hostaddr.bge_addr_hi); 1167 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1168 rcb->bge_hostaddr.bge_addr_lo); 1169 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1170 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1171 1172 /* Set up dummy disabled mini ring RCB */ 1173 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1174 rcb->bge_maxlen_flags = 1175 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1176 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1177 1178 /* 1179 * Set the BD ring replentish thresholds. The recommended 1180 * values are 1/8th the number of descriptors allocated to 1181 * each ring. 1182 */ 1183 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1184 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1185 1186 /* 1187 * Disable all unused send rings by setting the 'ring disabled' 1188 * bit in the flags field of all the TX send ring control blocks. 1189 * These are located in NIC memory. 1190 */ 1191 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1192 BGE_SEND_RING_RCB); 1193 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1194 vrcb->bge_maxlen_flags = 1195 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1196 vrcb->bge_nicaddr = 0; 1197 vrcb++; 1198 } 1199 1200 /* Configure TX RCB 0 (we use only the first ring) */ 1201 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1202 BGE_SEND_RING_RCB); 1203 vrcb->bge_hostaddr.bge_addr_hi = 0; 1204 BGE_HOSTADDR(vrcb->bge_hostaddr) = 1205 vtophys(&sc->bge_rdata->bge_tx_ring); 1206 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 1207 vrcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0); 1208 1209 /* Disable all unused RX return rings */ 1210 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1211 BGE_RX_RETURN_RING_RCB); 1212 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1213 vrcb->bge_hostaddr.bge_addr_hi = 0; 1214 vrcb->bge_hostaddr.bge_addr_lo = 0; 1215 vrcb->bge_maxlen_flags = 1216 BGE_RCB_MAXLEN_FLAGS(BGE_RETURN_RING_CNT, 1217 BGE_RCB_FLAG_RING_DISABLED); 1218 vrcb->bge_nicaddr = 0; 1219 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1220 (i * (sizeof(u_int64_t))), 0); 1221 vrcb++; 1222 } 1223 1224 /* Initialize RX ring indexes */ 1225 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1226 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1227 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1228 1229 /* 1230 * Set up RX return ring 0 1231 * Note that the NIC address for RX return rings is 0x00000000. 1232 * The return rings live entirely within the host, so the 1233 * nicaddr field in the RCB isn't used. 1234 */ 1235 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1236 BGE_RX_RETURN_RING_RCB); 1237 vrcb->bge_hostaddr.bge_addr_hi = 0; 1238 BGE_HOSTADDR(vrcb->bge_hostaddr) = 1239 vtophys(&sc->bge_rdata->bge_rx_return_ring); 1240 vrcb->bge_nicaddr = 0x00000000; 1241 vrcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(BGE_RETURN_RING_CNT, 0); 1242 1243 /* Set random backoff seed for TX */ 1244 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1245 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1246 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1247 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1248 BGE_TX_BACKOFF_SEED_MASK); 1249 1250 /* Set inter-packet gap */ 1251 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1252 1253 /* 1254 * Specify which ring to use for packets that don't match 1255 * any RX rules. 1256 */ 1257 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1258 1259 /* 1260 * Configure number of RX lists. One interrupt distribution 1261 * list, sixteen active lists, one bad frames class. 1262 */ 1263 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1264 1265 /* Inialize RX list placement stats mask. */ 1266 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1267 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1268 1269 /* Disable host coalescing until we get it set up */ 1270 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1271 1272 /* Poll to make sure it's shut down. */ 1273 for (i = 0; i < BGE_TIMEOUT; i++) { 1274 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1275 break; 1276 DELAY(10); 1277 } 1278 1279 if (i == BGE_TIMEOUT) { 1280 printf("bge%d: host coalescing engine failed to idle\n", 1281 sc->bge_unit); 1282 return(ENXIO); 1283 } 1284 1285 /* Set up host coalescing defaults */ 1286 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1287 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1288 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1289 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1290 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1291 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1292 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1293 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1294 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1295 1296 /* Set up address of statistics block */ 1297 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1298 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0); 1299 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1300 vtophys(&sc->bge_rdata->bge_info.bge_stats)); 1301 1302 /* Set up address of status block */ 1303 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1304 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0); 1305 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1306 vtophys(&sc->bge_rdata->bge_status_block)); 1307 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1308 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1309 1310 /* Turn on host coalescing state machine */ 1311 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1312 1313 /* Turn on RX BD completion state machine and enable attentions */ 1314 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1315 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1316 1317 /* Turn on RX list placement state machine */ 1318 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1319 1320 /* Turn on RX list selector state machine. */ 1321 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1322 1323 /* Turn on DMA, clear stats */ 1324 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1325 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1326 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1327 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1328 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1329 1330 /* Set misc. local control, enable interrupts on attentions */ 1331 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1332 1333 #ifdef notdef 1334 /* Assert GPIO pins for PHY reset */ 1335 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1336 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1337 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1338 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1339 #endif 1340 1341 /* Turn on DMA completion state machine */ 1342 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1343 1344 /* Turn on write DMA state machine */ 1345 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1346 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1347 1348 /* Turn on read DMA state machine */ 1349 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1350 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1351 1352 /* Turn on RX data completion state machine */ 1353 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1354 1355 /* Turn on RX BD initiator state machine */ 1356 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1357 1358 /* Turn on RX data and RX BD initiator state machine */ 1359 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1360 1361 /* Turn on Mbuf cluster free state machine */ 1362 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1363 1364 /* Turn on send BD completion state machine */ 1365 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1366 1367 /* Turn on send data completion state machine */ 1368 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1369 1370 /* Turn on send data initiator state machine */ 1371 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1372 1373 /* Turn on send BD initiator state machine */ 1374 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1375 1376 /* Turn on send BD selector state machine */ 1377 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1378 1379 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1380 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1381 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1382 1383 /* init LED register */ 1384 CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000); 1385 1386 /* ack/clear link change events */ 1387 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1388 BGE_MACSTAT_CFG_CHANGED); 1389 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1390 1391 /* Enable PHY auto polling (for MII/GMII only) */ 1392 if (sc->bge_tbi) { 1393 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1394 } else { 1395 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1396 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1397 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1398 BGE_EVTENB_MI_INTERRUPT); 1399 } 1400 1401 /* Enable link state change attentions. */ 1402 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1403 1404 return(0); 1405 } 1406 1407 /* 1408 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1409 * against our list and return its name if we find a match. Note 1410 * that since the Broadcom controller contains VPD support, we 1411 * can get the device name string from the controller itself instead 1412 * of the compiled-in string. This is a little slow, but it guarantees 1413 * we'll always announce the right product name. 1414 */ 1415 static int 1416 bge_probe(dev) 1417 device_t dev; 1418 { 1419 struct bge_type *t; 1420 struct bge_softc *sc; 1421 char *descbuf; 1422 1423 t = bge_devs; 1424 1425 sc = device_get_softc(dev); 1426 bzero(sc, sizeof(struct bge_softc)); 1427 sc->bge_unit = device_get_unit(dev); 1428 sc->bge_dev = dev; 1429 1430 while(t->bge_name != NULL) { 1431 if ((pci_get_vendor(dev) == t->bge_vid) && 1432 (pci_get_device(dev) == t->bge_did)) { 1433 #ifdef notdef 1434 bge_vpd_read(sc); 1435 device_set_desc(dev, sc->bge_vpd_prodname); 1436 #endif 1437 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 1438 if (descbuf == NULL) 1439 return(ENOMEM); 1440 snprintf(descbuf, BGE_DEVDESC_MAX, 1441 "%s, ASIC rev. %#04x", t->bge_name, 1442 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16); 1443 device_set_desc_copy(dev, descbuf); 1444 free(descbuf, M_TEMP); 1445 return(0); 1446 } 1447 t++; 1448 } 1449 1450 return(ENXIO); 1451 } 1452 1453 static int 1454 bge_attach(dev) 1455 device_t dev; 1456 { 1457 int s; 1458 u_int32_t command; 1459 struct ifnet *ifp; 1460 struct bge_softc *sc; 1461 u_int32_t hwcfg = 0; 1462 u_int32_t mac_addr = 0; 1463 int unit, error = 0, rid; 1464 1465 s = splimp(); 1466 1467 sc = device_get_softc(dev); 1468 unit = device_get_unit(dev); 1469 sc->bge_dev = dev; 1470 sc->bge_unit = unit; 1471 1472 /* 1473 * Map control/status registers. 1474 */ 1475 pci_enable_busmaster(dev); 1476 pci_enable_io(dev, SYS_RES_MEMORY); 1477 command = pci_read_config(dev, PCIR_COMMAND, 4); 1478 1479 if (!(command & PCIM_CMD_MEMEN)) { 1480 printf("bge%d: failed to enable memory mapping!\n", unit); 1481 error = ENXIO; 1482 goto fail; 1483 } 1484 1485 rid = BGE_PCI_BAR0; 1486 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1487 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 1488 1489 if (sc->bge_res == NULL) { 1490 printf ("bge%d: couldn't map memory\n", unit); 1491 error = ENXIO; 1492 goto fail; 1493 } 1494 1495 sc->bge_btag = rman_get_bustag(sc->bge_res); 1496 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 1497 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 1498 1499 /* Allocate interrupt */ 1500 rid = 0; 1501 1502 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1503 RF_SHAREABLE | RF_ACTIVE); 1504 1505 if (sc->bge_irq == NULL) { 1506 printf("bge%d: couldn't map interrupt\n", unit); 1507 error = ENXIO; 1508 goto fail; 1509 } 1510 1511 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET, 1512 bge_intr, sc, &sc->bge_intrhand); 1513 1514 if (error) { 1515 bge_release_resources(sc); 1516 printf("bge%d: couldn't set up irq\n", unit); 1517 goto fail; 1518 } 1519 1520 sc->bge_unit = unit; 1521 1522 /* Try to reset the chip. */ 1523 bge_reset(sc); 1524 1525 if (bge_chipinit(sc)) { 1526 printf("bge%d: chip initialization failed\n", sc->bge_unit); 1527 bge_release_resources(sc); 1528 error = ENXIO; 1529 goto fail; 1530 } 1531 1532 /* 1533 * Get station address from the EEPROM. 1534 */ 1535 mac_addr = bge_readmem_ind(sc, 0x0c14); 1536 if ((mac_addr >> 16) == 0x484b) { 1537 sc->arpcom.ac_enaddr[0] = (u_char)(mac_addr >> 8); 1538 sc->arpcom.ac_enaddr[1] = (u_char)mac_addr; 1539 mac_addr = bge_readmem_ind(sc, 0x0c18); 1540 sc->arpcom.ac_enaddr[2] = (u_char)(mac_addr >> 24); 1541 sc->arpcom.ac_enaddr[3] = (u_char)(mac_addr >> 16); 1542 sc->arpcom.ac_enaddr[4] = (u_char)(mac_addr >> 8); 1543 sc->arpcom.ac_enaddr[5] = (u_char)mac_addr; 1544 } else if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1545 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1546 printf("bge%d: failed to read station address\n", unit); 1547 bge_release_resources(sc); 1548 error = ENXIO; 1549 goto fail; 1550 } 1551 1552 /* 1553 * A Broadcom chip was detected. Inform the world. 1554 */ 1555 printf("bge%d: Ethernet address: %6D\n", unit, 1556 sc->arpcom.ac_enaddr, ":"); 1557 1558 /* Allocate the general information block and ring buffers. */ 1559 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF, 1560 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1561 1562 if (sc->bge_rdata == NULL) { 1563 bge_release_resources(sc); 1564 error = ENXIO; 1565 printf("bge%d: no memory for list buffers!\n", sc->bge_unit); 1566 goto fail; 1567 } 1568 1569 bzero(sc->bge_rdata, sizeof(struct bge_ring_data)); 1570 1571 /* Try to allocate memory for jumbo buffers. */ 1572 if (bge_alloc_jumbo_mem(sc)) { 1573 printf("bge%d: jumbo buffer allocation " 1574 "failed\n", sc->bge_unit); 1575 bge_release_resources(sc); 1576 error = ENXIO; 1577 goto fail; 1578 } 1579 1580 /* Set default tuneable values. */ 1581 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1582 sc->bge_rx_coal_ticks = 150; 1583 sc->bge_tx_coal_ticks = 150; 1584 sc->bge_rx_max_coal_bds = 64; 1585 sc->bge_tx_max_coal_bds = 128; 1586 1587 /* Set up ifnet structure */ 1588 ifp = &sc->arpcom.ac_if; 1589 ifp->if_softc = sc; 1590 ifp->if_unit = sc->bge_unit; 1591 ifp->if_name = "bge"; 1592 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1593 ifp->if_ioctl = bge_ioctl; 1594 ifp->if_output = ether_output; 1595 ifp->if_start = bge_start; 1596 ifp->if_watchdog = bge_watchdog; 1597 ifp->if_init = bge_init; 1598 ifp->if_mtu = ETHERMTU; 1599 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1; 1600 ifp->if_hwassist = BGE_CSUM_FEATURES; 1601 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 1602 ifp->if_capenable = ifp->if_capabilities; 1603 1604 /* Save ASIC rev. */ 1605 1606 sc->bge_asicrev = 1607 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 1608 BGE_PCIMISCCTL_ASICREV; 1609 1610 /* Pretend all 5700s are the same */ 1611 if ((sc->bge_asicrev & 0xFF000000) == BGE_ASICREV_BCM5700) 1612 sc->bge_asicrev = BGE_ASICREV_BCM5700; 1613 1614 /* 1615 * Figure out what sort of media we have by checking the 1616 * hardware config word in the EEPROM. Note: on some BCM5700 1617 * cards, this value appears to be unset. If that's the 1618 * case, we have to rely on identifying the NIC by its PCI 1619 * subsystem ID, as we do below for the SysKonnect SK-9D41. 1620 */ 1621 bge_read_eeprom(sc, (caddr_t)&hwcfg, 1622 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 1623 if ((ntohl(hwcfg) & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 1624 sc->bge_tbi = 1; 1625 1626 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1627 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 1628 sc->bge_tbi = 1; 1629 1630 if (sc->bge_tbi) { 1631 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 1632 bge_ifmedia_upd, bge_ifmedia_sts); 1633 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1634 ifmedia_add(&sc->bge_ifmedia, 1635 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1636 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1637 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 1638 } else { 1639 /* 1640 * Do transceiver setup. 1641 */ 1642 if (mii_phy_probe(dev, &sc->bge_miibus, 1643 bge_ifmedia_upd, bge_ifmedia_sts)) { 1644 printf("bge%d: MII without any PHY!\n", sc->bge_unit); 1645 bge_release_resources(sc); 1646 bge_free_jumbo_mem(sc); 1647 error = ENXIO; 1648 goto fail; 1649 } 1650 } 1651 1652 /* 1653 * When using the BCM5701 in PCI-X mode, data corruption has 1654 * been observed in the first few bytes of some received packets. 1655 * Aligning the packet buffer in memory eliminates the corruption. 1656 * Unfortunately, this misaligns the packet payloads. On platforms 1657 * which do not support unaligned accesses, we will realign the 1658 * payloads by copying the received packets. 1659 */ 1660 switch (sc->bge_asicrev) { 1661 case BGE_ASICREV_BCM5701_A0: 1662 case BGE_ASICREV_BCM5701_B0: 1663 case BGE_ASICREV_BCM5701_B2: 1664 case BGE_ASICREV_BCM5701_B5: 1665 /* If in PCI-X mode, work around the alignment bug. */ 1666 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 1667 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 1668 BGE_PCISTATE_PCI_BUSSPEED) 1669 sc->bge_rx_alignment_bug = 1; 1670 break; 1671 } 1672 1673 /* 1674 * Call MI attach routine. 1675 */ 1676 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1677 callout_handle_init(&sc->bge_stat_ch); 1678 1679 fail: 1680 splx(s); 1681 1682 return(error); 1683 } 1684 1685 static int 1686 bge_detach(dev) 1687 device_t dev; 1688 { 1689 struct bge_softc *sc; 1690 struct ifnet *ifp; 1691 int s; 1692 1693 s = splimp(); 1694 1695 sc = device_get_softc(dev); 1696 ifp = &sc->arpcom.ac_if; 1697 1698 ether_ifdetach(ifp); 1699 bge_stop(sc); 1700 bge_reset(sc); 1701 1702 if (sc->bge_tbi) { 1703 ifmedia_removeall(&sc->bge_ifmedia); 1704 } else { 1705 bus_generic_detach(dev); 1706 device_delete_child(dev, sc->bge_miibus); 1707 } 1708 1709 bge_release_resources(sc); 1710 bge_free_jumbo_mem(sc); 1711 1712 splx(s); 1713 1714 return(0); 1715 } 1716 1717 static void 1718 bge_release_resources(sc) 1719 struct bge_softc *sc; 1720 { 1721 device_t dev; 1722 1723 dev = sc->bge_dev; 1724 1725 if (sc->bge_vpd_prodname != NULL) 1726 free(sc->bge_vpd_prodname, M_DEVBUF); 1727 1728 if (sc->bge_vpd_readonly != NULL) 1729 free(sc->bge_vpd_readonly, M_DEVBUF); 1730 1731 if (sc->bge_intrhand != NULL) 1732 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 1733 1734 if (sc->bge_irq != NULL) 1735 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 1736 1737 if (sc->bge_res != NULL) 1738 bus_release_resource(dev, SYS_RES_MEMORY, 1739 BGE_PCI_BAR0, sc->bge_res); 1740 1741 if (sc->bge_rdata != NULL) 1742 contigfree(sc->bge_rdata, 1743 sizeof(struct bge_ring_data), M_DEVBUF); 1744 1745 return; 1746 } 1747 1748 static void 1749 bge_reset(sc) 1750 struct bge_softc *sc; 1751 { 1752 device_t dev; 1753 u_int32_t cachesize, command, pcistate; 1754 int i, val = 0; 1755 1756 dev = sc->bge_dev; 1757 1758 /* Save some important PCI state. */ 1759 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 1760 command = pci_read_config(dev, BGE_PCI_CMD, 4); 1761 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 1762 1763 pci_write_config(dev, BGE_PCI_MISC_CTL, 1764 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1765 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1766 1767 /* Issue global reset */ 1768 bge_writereg_ind(sc, BGE_MISC_CFG, 1769 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 1770 1771 DELAY(1000); 1772 1773 /* Reset some of the PCI state that got zapped by reset */ 1774 pci_write_config(dev, BGE_PCI_MISC_CTL, 1775 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1776 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1777 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 1778 pci_write_config(dev, BGE_PCI_CMD, command, 4); 1779 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1780 1781 /* 1782 * Prevent PXE restart: write a magic number to the 1783 * general communications memory at 0xB50. 1784 */ 1785 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1786 /* 1787 * Poll the value location we just wrote until 1788 * we see the 1's complement of the magic number. 1789 * This indicates that the firmware initialization 1790 * is complete. 1791 */ 1792 for (i = 0; i < BGE_TIMEOUT; i++) { 1793 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1794 if (val == ~BGE_MAGIC_NUMBER) 1795 break; 1796 DELAY(10); 1797 } 1798 1799 if (i == BGE_TIMEOUT) { 1800 printf("bge%d: firmware handshake timed out\n", sc->bge_unit); 1801 return; 1802 } 1803 1804 /* 1805 * XXX Wait for the value of the PCISTATE register to 1806 * return to its original pre-reset state. This is a 1807 * fairly good indicator of reset completion. If we don't 1808 * wait for the reset to fully complete, trying to read 1809 * from the device's non-PCI registers may yield garbage 1810 * results. 1811 */ 1812 for (i = 0; i < BGE_TIMEOUT; i++) { 1813 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 1814 break; 1815 DELAY(10); 1816 } 1817 1818 /* Enable memory arbiter. */ 1819 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1820 1821 /* Fix up byte swapping */ 1822 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 1823 BGE_MODECTL_BYTESWAP_DATA); 1824 1825 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1826 1827 DELAY(10000); 1828 1829 return; 1830 } 1831 1832 /* 1833 * Frame reception handling. This is called if there's a frame 1834 * on the receive return list. 1835 * 1836 * Note: we have to be able to handle two possibilities here: 1837 * 1) the frame is from the jumbo recieve ring 1838 * 2) the frame is from the standard receive ring 1839 */ 1840 1841 static void 1842 bge_rxeof(sc) 1843 struct bge_softc *sc; 1844 { 1845 struct ifnet *ifp; 1846 int stdcnt = 0, jumbocnt = 0; 1847 1848 ifp = &sc->arpcom.ac_if; 1849 1850 while(sc->bge_rx_saved_considx != 1851 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 1852 struct bge_rx_bd *cur_rx; 1853 u_int32_t rxidx; 1854 struct ether_header *eh; 1855 struct mbuf *m = NULL; 1856 u_int16_t vlan_tag = 0; 1857 int have_tag = 0; 1858 1859 cur_rx = 1860 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx]; 1861 1862 rxidx = cur_rx->bge_idx; 1863 BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT); 1864 1865 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 1866 have_tag = 1; 1867 vlan_tag = cur_rx->bge_vlan_tag; 1868 } 1869 1870 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 1871 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1872 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 1873 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 1874 jumbocnt++; 1875 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1876 ifp->if_ierrors++; 1877 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1878 continue; 1879 } 1880 if (bge_newbuf_jumbo(sc, 1881 sc->bge_jumbo, NULL) == ENOBUFS) { 1882 ifp->if_ierrors++; 1883 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1884 continue; 1885 } 1886 } else { 1887 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1888 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 1889 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 1890 stdcnt++; 1891 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1892 ifp->if_ierrors++; 1893 bge_newbuf_std(sc, sc->bge_std, m); 1894 continue; 1895 } 1896 if (bge_newbuf_std(sc, sc->bge_std, 1897 NULL) == ENOBUFS) { 1898 ifp->if_ierrors++; 1899 bge_newbuf_std(sc, sc->bge_std, m); 1900 continue; 1901 } 1902 } 1903 1904 ifp->if_ipackets++; 1905 #ifndef __i386__ 1906 /* 1907 * The i386 allows unaligned accesses, but for other 1908 * platforms we must make sure the payload is aligned. 1909 */ 1910 if (sc->bge_rx_alignment_bug) { 1911 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 1912 cur_rx->bge_len); 1913 m->m_data += ETHER_ALIGN; 1914 } 1915 #endif 1916 eh = mtod(m, struct ether_header *); 1917 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 1918 m->m_pkthdr.rcvif = ifp; 1919 1920 #if 0 /* currently broken for some packets, possibly related to TCP options */ 1921 if (ifp->if_hwassist) { 1922 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1923 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 1924 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1925 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 1926 m->m_pkthdr.csum_data = 1927 cur_rx->bge_tcp_udp_csum; 1928 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1929 } 1930 } 1931 #endif 1932 1933 /* 1934 * If we received a packet with a vlan tag, 1935 * attach that information to the packet. 1936 */ 1937 if (have_tag) 1938 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue); 1939 1940 (*ifp->if_input)(ifp, m); 1941 } 1942 1943 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 1944 if (stdcnt) 1945 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1946 if (jumbocnt) 1947 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1948 1949 return; 1950 } 1951 1952 static void 1953 bge_txeof(sc) 1954 struct bge_softc *sc; 1955 { 1956 struct bge_tx_bd *cur_tx = NULL; 1957 struct ifnet *ifp; 1958 1959 ifp = &sc->arpcom.ac_if; 1960 1961 /* 1962 * Go through our tx ring and free mbufs for those 1963 * frames that have been sent. 1964 */ 1965 while (sc->bge_tx_saved_considx != 1966 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 1967 u_int32_t idx = 0; 1968 1969 idx = sc->bge_tx_saved_considx; 1970 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 1971 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 1972 ifp->if_opackets++; 1973 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 1974 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 1975 sc->bge_cdata.bge_tx_chain[idx] = NULL; 1976 } 1977 sc->bge_txcnt--; 1978 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 1979 ifp->if_timer = 0; 1980 } 1981 1982 if (cur_tx != NULL) 1983 ifp->if_flags &= ~IFF_OACTIVE; 1984 1985 return; 1986 } 1987 1988 static void 1989 bge_intr(xsc) 1990 void *xsc; 1991 { 1992 struct bge_softc *sc; 1993 struct ifnet *ifp; 1994 1995 sc = xsc; 1996 ifp = &sc->arpcom.ac_if; 1997 1998 #ifdef notdef 1999 /* Avoid this for now -- checking this register is expensive. */ 2000 /* Make sure this is really our interrupt. */ 2001 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2002 return; 2003 #endif 2004 /* Ack interrupt and stop others from occuring. */ 2005 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2006 2007 /* 2008 * Process link state changes. 2009 * Grrr. The link status word in the status block does 2010 * not work correctly on the BCM5700 rev AX and BX chips, 2011 * according to all avaibable information. Hence, we have 2012 * to enable MII interrupts in order to properly obtain 2013 * async link changes. Unfortunately, this also means that 2014 * we have to read the MAC status register to detect link 2015 * changes, thereby adding an additional register access to 2016 * the interrupt handler. 2017 */ 2018 2019 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) { 2020 u_int32_t status; 2021 2022 status = CSR_READ_4(sc, BGE_MAC_STS); 2023 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2024 sc->bge_link = 0; 2025 untimeout(bge_tick, sc, sc->bge_stat_ch); 2026 bge_tick(sc); 2027 /* Clear the interrupt */ 2028 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2029 BGE_EVTENB_MI_INTERRUPT); 2030 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 2031 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 2032 BRGPHY_INTRS); 2033 } 2034 } else { 2035 if (sc->bge_rdata->bge_status_block.bge_status & 2036 BGE_STATFLAG_LINKSTATE_CHANGED) { 2037 sc->bge_link = 0; 2038 untimeout(bge_tick, sc, sc->bge_stat_ch); 2039 bge_tick(sc); 2040 /* Clear the interrupt */ 2041 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2042 BGE_MACSTAT_CFG_CHANGED); 2043 } 2044 } 2045 2046 if (ifp->if_flags & IFF_RUNNING) { 2047 /* Check RX return ring producer/consumer */ 2048 bge_rxeof(sc); 2049 2050 /* Check TX ring producer/consumer */ 2051 bge_txeof(sc); 2052 } 2053 2054 bge_handle_events(sc); 2055 2056 /* Re-enable interrupts. */ 2057 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2058 2059 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2060 bge_start(ifp); 2061 2062 return; 2063 } 2064 2065 static void 2066 bge_tick(xsc) 2067 void *xsc; 2068 { 2069 struct bge_softc *sc; 2070 struct mii_data *mii = NULL; 2071 struct ifmedia *ifm = NULL; 2072 struct ifnet *ifp; 2073 int s; 2074 2075 sc = xsc; 2076 ifp = &sc->arpcom.ac_if; 2077 2078 s = splimp(); 2079 2080 bge_stats_update(sc); 2081 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2082 if (sc->bge_link) { 2083 splx(s); 2084 return; 2085 } 2086 2087 if (sc->bge_tbi) { 2088 ifm = &sc->bge_ifmedia; 2089 if (CSR_READ_4(sc, BGE_MAC_STS) & 2090 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2091 sc->bge_link++; 2092 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2093 printf("bge%d: gigabit link up\n", sc->bge_unit); 2094 if (ifp->if_snd.ifq_head != NULL) 2095 bge_start(ifp); 2096 } 2097 splx(s); 2098 return; 2099 } 2100 2101 mii = device_get_softc(sc->bge_miibus); 2102 mii_tick(mii); 2103 2104 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2105 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2106 sc->bge_link++; 2107 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 2108 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2109 printf("bge%d: gigabit link up\n", 2110 sc->bge_unit); 2111 if (ifp->if_snd.ifq_head != NULL) 2112 bge_start(ifp); 2113 } 2114 2115 splx(s); 2116 2117 return; 2118 } 2119 2120 static void 2121 bge_stats_update(sc) 2122 struct bge_softc *sc; 2123 { 2124 struct ifnet *ifp; 2125 struct bge_stats *stats; 2126 2127 ifp = &sc->arpcom.ac_if; 2128 2129 stats = (struct bge_stats *)(sc->bge_vhandle + 2130 BGE_MEMWIN_START + BGE_STATS_BLOCK); 2131 2132 ifp->if_collisions += 2133 (stats->dot3StatsSingleCollisionFrames.bge_addr_lo + 2134 stats->dot3StatsMultipleCollisionFrames.bge_addr_lo + 2135 stats->dot3StatsExcessiveCollisions.bge_addr_lo + 2136 stats->dot3StatsLateCollisions.bge_addr_lo) - 2137 ifp->if_collisions; 2138 2139 #ifdef notdef 2140 ifp->if_collisions += 2141 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2142 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2143 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2144 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2145 ifp->if_collisions; 2146 #endif 2147 2148 return; 2149 } 2150 2151 /* 2152 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2153 * pointers to descriptors. 2154 */ 2155 static int 2156 bge_encap(sc, m_head, txidx) 2157 struct bge_softc *sc; 2158 struct mbuf *m_head; 2159 u_int32_t *txidx; 2160 { 2161 struct bge_tx_bd *f = NULL; 2162 struct mbuf *m; 2163 u_int32_t frag, cur, cnt = 0; 2164 u_int16_t csum_flags = 0; 2165 struct m_tag *mtag; 2166 2167 m = m_head; 2168 cur = frag = *txidx; 2169 2170 if (m_head->m_pkthdr.csum_flags) { 2171 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2172 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2173 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2174 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2175 if (m_head->m_flags & M_LASTFRAG) 2176 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 2177 else if (m_head->m_flags & M_FRAG) 2178 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 2179 } 2180 2181 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m); 2182 2183 /* 2184 * Start packing the mbufs in this chain into 2185 * the fragment pointers. Stop when we run out 2186 * of fragments or hit the end of the mbuf chain. 2187 */ 2188 for (m = m_head; m != NULL; m = m->m_next) { 2189 if (m->m_len != 0) { 2190 f = &sc->bge_rdata->bge_tx_ring[frag]; 2191 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2192 break; 2193 BGE_HOSTADDR(f->bge_addr) = 2194 vtophys(mtod(m, vm_offset_t)); 2195 f->bge_len = m->m_len; 2196 f->bge_flags = csum_flags; 2197 if (mtag != NULL) { 2198 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2199 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 2200 } else { 2201 f->bge_vlan_tag = 0; 2202 } 2203 /* 2204 * Sanity check: avoid coming within 16 descriptors 2205 * of the end of the ring. 2206 */ 2207 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2208 return(ENOBUFS); 2209 cur = frag; 2210 BGE_INC(frag, BGE_TX_RING_CNT); 2211 cnt++; 2212 } 2213 } 2214 2215 if (m != NULL) 2216 return(ENOBUFS); 2217 2218 if (frag == sc->bge_tx_saved_considx) 2219 return(ENOBUFS); 2220 2221 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2222 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2223 sc->bge_txcnt += cnt; 2224 2225 *txidx = frag; 2226 2227 return(0); 2228 } 2229 2230 /* 2231 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2232 * to the mbuf data regions directly in the transmit descriptors. 2233 */ 2234 static void 2235 bge_start(ifp) 2236 struct ifnet *ifp; 2237 { 2238 struct bge_softc *sc; 2239 struct mbuf *m_head = NULL; 2240 u_int32_t prodidx = 0; 2241 2242 sc = ifp->if_softc; 2243 2244 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 2245 return; 2246 2247 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2248 2249 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2250 IF_DEQUEUE(&ifp->if_snd, m_head); 2251 if (m_head == NULL) 2252 break; 2253 2254 /* 2255 * XXX 2256 * safety overkill. If this is a fragmented packet chain 2257 * with delayed TCP/UDP checksums, then only encapsulate 2258 * it if we have enough descriptors to handle the entire 2259 * chain at once. 2260 * (paranoia -- may not actually be needed) 2261 */ 2262 if (m_head->m_flags & M_FIRSTFRAG && 2263 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2264 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2265 m_head->m_pkthdr.csum_data + 16) { 2266 IF_PREPEND(&ifp->if_snd, m_head); 2267 ifp->if_flags |= IFF_OACTIVE; 2268 break; 2269 } 2270 } 2271 2272 /* 2273 * Pack the data into the transmit ring. If we 2274 * don't have room, set the OACTIVE flag and wait 2275 * for the NIC to drain the ring. 2276 */ 2277 if (bge_encap(sc, m_head, &prodidx)) { 2278 IF_PREPEND(&ifp->if_snd, m_head); 2279 ifp->if_flags |= IFF_OACTIVE; 2280 break; 2281 } 2282 2283 /* 2284 * If there's a BPF listener, bounce a copy of this frame 2285 * to him. 2286 */ 2287 BPF_MTAP(ifp, m_head); 2288 } 2289 2290 /* Transmit */ 2291 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2292 2293 /* 2294 * Set a timeout in case the chip goes out to lunch. 2295 */ 2296 ifp->if_timer = 5; 2297 2298 return; 2299 } 2300 2301 /* 2302 * If we have a BCM5400 or BCM5401 PHY, we need to properly 2303 * program its internal DSP. Failing to do this can result in 2304 * massive packet loss at 1Gb speeds. 2305 */ 2306 static void 2307 bge_phy_hack(sc) 2308 struct bge_softc *sc; 2309 { 2310 struct bge_bcom_hack bhack[] = { 2311 { BRGPHY_MII_AUXCTL, 0x4C20 }, 2312 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 2313 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 2314 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 2315 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 2316 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2317 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 2318 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2319 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 2320 { BRGPHY_MII_DSP_ADDR_REG, 0x201F }, 2321 { BRGPHY_MII_DSP_RW_PORT, 0x0A20 }, 2322 { 0, 0 } }; 2323 u_int16_t vid, did; 2324 int i; 2325 2326 vid = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR1); 2327 did = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR2); 2328 2329 if (MII_OUI(vid, did) == MII_OUI_xxBROADCOM && 2330 (MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5400 || 2331 MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5401)) { 2332 i = 0; 2333 while(bhack[i].reg) { 2334 bge_miibus_writereg(sc->bge_dev, 1, bhack[i].reg, 2335 bhack[i].val); 2336 i++; 2337 } 2338 } 2339 2340 return; 2341 } 2342 2343 static void 2344 bge_init(xsc) 2345 void *xsc; 2346 { 2347 struct bge_softc *sc = xsc; 2348 struct ifnet *ifp; 2349 u_int16_t *m; 2350 int s; 2351 2352 s = splimp(); 2353 2354 ifp = &sc->arpcom.ac_if; 2355 2356 if (ifp->if_flags & IFF_RUNNING) { 2357 splx(s); 2358 return; 2359 } 2360 2361 /* Cancel pending I/O and flush buffers. */ 2362 bge_stop(sc); 2363 bge_reset(sc); 2364 bge_chipinit(sc); 2365 2366 /* 2367 * Init the various state machines, ring 2368 * control blocks and firmware. 2369 */ 2370 if (bge_blockinit(sc)) { 2371 printf("bge%d: initialization failure\n", sc->bge_unit); 2372 splx(s); 2373 return; 2374 } 2375 2376 ifp = &sc->arpcom.ac_if; 2377 2378 /* Specify MTU. */ 2379 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2380 ETHER_HDR_LEN + ETHER_CRC_LEN); 2381 2382 /* Load our MAC address. */ 2383 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2384 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2385 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2386 2387 /* Enable or disable promiscuous mode as needed. */ 2388 if (ifp->if_flags & IFF_PROMISC) { 2389 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2390 } else { 2391 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2392 } 2393 2394 /* Program multicast filter. */ 2395 bge_setmulti(sc); 2396 2397 /* Init RX ring. */ 2398 bge_init_rx_ring_std(sc); 2399 2400 /* Init jumbo RX ring. */ 2401 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2402 bge_init_rx_ring_jumbo(sc); 2403 2404 /* Init our RX return ring index */ 2405 sc->bge_rx_saved_considx = 0; 2406 2407 /* Init TX ring. */ 2408 bge_init_tx_ring(sc); 2409 2410 /* Turn on transmitter */ 2411 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2412 2413 /* Turn on receiver */ 2414 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2415 2416 /* Tell firmware we're alive. */ 2417 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2418 2419 /* Enable host interrupts. */ 2420 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2421 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2422 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2423 2424 bge_ifmedia_upd(ifp); 2425 2426 ifp->if_flags |= IFF_RUNNING; 2427 ifp->if_flags &= ~IFF_OACTIVE; 2428 2429 splx(s); 2430 2431 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2432 2433 return; 2434 } 2435 2436 /* 2437 * Set media options. 2438 */ 2439 static int 2440 bge_ifmedia_upd(ifp) 2441 struct ifnet *ifp; 2442 { 2443 struct bge_softc *sc; 2444 struct mii_data *mii; 2445 struct ifmedia *ifm; 2446 2447 sc = ifp->if_softc; 2448 ifm = &sc->bge_ifmedia; 2449 2450 /* If this is a 1000baseX NIC, enable the TBI port. */ 2451 if (sc->bge_tbi) { 2452 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2453 return(EINVAL); 2454 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2455 case IFM_AUTO: 2456 break; 2457 case IFM_1000_SX: 2458 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2459 BGE_CLRBIT(sc, BGE_MAC_MODE, 2460 BGE_MACMODE_HALF_DUPLEX); 2461 } else { 2462 BGE_SETBIT(sc, BGE_MAC_MODE, 2463 BGE_MACMODE_HALF_DUPLEX); 2464 } 2465 break; 2466 default: 2467 return(EINVAL); 2468 } 2469 return(0); 2470 } 2471 2472 mii = device_get_softc(sc->bge_miibus); 2473 sc->bge_link = 0; 2474 if (mii->mii_instance) { 2475 struct mii_softc *miisc; 2476 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2477 miisc = LIST_NEXT(miisc, mii_list)) 2478 mii_phy_reset(miisc); 2479 } 2480 bge_phy_hack(sc); 2481 mii_mediachg(mii); 2482 2483 return(0); 2484 } 2485 2486 /* 2487 * Report current media status. 2488 */ 2489 static void 2490 bge_ifmedia_sts(ifp, ifmr) 2491 struct ifnet *ifp; 2492 struct ifmediareq *ifmr; 2493 { 2494 struct bge_softc *sc; 2495 struct mii_data *mii; 2496 2497 sc = ifp->if_softc; 2498 2499 if (sc->bge_tbi) { 2500 ifmr->ifm_status = IFM_AVALID; 2501 ifmr->ifm_active = IFM_ETHER; 2502 if (CSR_READ_4(sc, BGE_MAC_STS) & 2503 BGE_MACSTAT_TBI_PCS_SYNCHED) 2504 ifmr->ifm_status |= IFM_ACTIVE; 2505 ifmr->ifm_active |= IFM_1000_SX; 2506 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2507 ifmr->ifm_active |= IFM_HDX; 2508 else 2509 ifmr->ifm_active |= IFM_FDX; 2510 return; 2511 } 2512 2513 mii = device_get_softc(sc->bge_miibus); 2514 mii_pollstat(mii); 2515 ifmr->ifm_active = mii->mii_media_active; 2516 ifmr->ifm_status = mii->mii_media_status; 2517 2518 return; 2519 } 2520 2521 static int 2522 bge_ioctl(ifp, command, data) 2523 struct ifnet *ifp; 2524 u_long command; 2525 caddr_t data; 2526 { 2527 struct bge_softc *sc = ifp->if_softc; 2528 struct ifreq *ifr = (struct ifreq *) data; 2529 int s, mask, error = 0; 2530 struct mii_data *mii; 2531 2532 s = splimp(); 2533 2534 switch(command) { 2535 case SIOCSIFMTU: 2536 if (ifr->ifr_mtu > BGE_JUMBO_MTU) 2537 error = EINVAL; 2538 else { 2539 ifp->if_mtu = ifr->ifr_mtu; 2540 ifp->if_flags &= ~IFF_RUNNING; 2541 bge_init(sc); 2542 } 2543 break; 2544 case SIOCSIFFLAGS: 2545 if (ifp->if_flags & IFF_UP) { 2546 /* 2547 * If only the state of the PROMISC flag changed, 2548 * then just use the 'set promisc mode' command 2549 * instead of reinitializing the entire NIC. Doing 2550 * a full re-init means reloading the firmware and 2551 * waiting for it to start up, which may take a 2552 * second or two. 2553 */ 2554 if (ifp->if_flags & IFF_RUNNING && 2555 ifp->if_flags & IFF_PROMISC && 2556 !(sc->bge_if_flags & IFF_PROMISC)) { 2557 BGE_SETBIT(sc, BGE_RX_MODE, 2558 BGE_RXMODE_RX_PROMISC); 2559 } else if (ifp->if_flags & IFF_RUNNING && 2560 !(ifp->if_flags & IFF_PROMISC) && 2561 sc->bge_if_flags & IFF_PROMISC) { 2562 BGE_CLRBIT(sc, BGE_RX_MODE, 2563 BGE_RXMODE_RX_PROMISC); 2564 } else 2565 bge_init(sc); 2566 } else { 2567 if (ifp->if_flags & IFF_RUNNING) { 2568 bge_stop(sc); 2569 } 2570 } 2571 sc->bge_if_flags = ifp->if_flags; 2572 error = 0; 2573 break; 2574 case SIOCADDMULTI: 2575 case SIOCDELMULTI: 2576 if (ifp->if_flags & IFF_RUNNING) { 2577 bge_setmulti(sc); 2578 error = 0; 2579 } 2580 break; 2581 case SIOCSIFMEDIA: 2582 case SIOCGIFMEDIA: 2583 if (sc->bge_tbi) { 2584 error = ifmedia_ioctl(ifp, ifr, 2585 &sc->bge_ifmedia, command); 2586 } else { 2587 mii = device_get_softc(sc->bge_miibus); 2588 error = ifmedia_ioctl(ifp, ifr, 2589 &mii->mii_media, command); 2590 } 2591 break; 2592 case SIOCSIFCAP: 2593 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2594 if (mask & IFCAP_HWCSUM) { 2595 if (IFCAP_HWCSUM & ifp->if_capenable) 2596 ifp->if_capenable &= ~IFCAP_HWCSUM; 2597 else 2598 ifp->if_capenable |= IFCAP_HWCSUM; 2599 } 2600 error = 0; 2601 break; 2602 default: 2603 error = ether_ioctl(ifp, command, data); 2604 break; 2605 } 2606 2607 (void)splx(s); 2608 2609 return(error); 2610 } 2611 2612 static void 2613 bge_watchdog(ifp) 2614 struct ifnet *ifp; 2615 { 2616 struct bge_softc *sc; 2617 2618 sc = ifp->if_softc; 2619 2620 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit); 2621 2622 ifp->if_flags &= ~IFF_RUNNING; 2623 bge_init(sc); 2624 2625 ifp->if_oerrors++; 2626 2627 return; 2628 } 2629 2630 /* 2631 * Stop the adapter and free any mbufs allocated to the 2632 * RX and TX lists. 2633 */ 2634 static void 2635 bge_stop(sc) 2636 struct bge_softc *sc; 2637 { 2638 struct ifnet *ifp; 2639 struct ifmedia_entry *ifm; 2640 struct mii_data *mii = NULL; 2641 int mtmp, itmp; 2642 2643 ifp = &sc->arpcom.ac_if; 2644 2645 if (!sc->bge_tbi) 2646 mii = device_get_softc(sc->bge_miibus); 2647 2648 untimeout(bge_tick, sc, sc->bge_stat_ch); 2649 2650 /* 2651 * Disable all of the receiver blocks 2652 */ 2653 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2654 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2655 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2656 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2657 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2658 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2659 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2660 2661 /* 2662 * Disable all of the transmit blocks 2663 */ 2664 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2665 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2666 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2667 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2668 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2669 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2670 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2671 2672 /* 2673 * Shut down all of the memory managers and related 2674 * state machines. 2675 */ 2676 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2677 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2678 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2679 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2680 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2681 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2682 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2683 2684 /* Disable host interrupts. */ 2685 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2686 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2687 2688 /* 2689 * Tell firmware we're shutting down. 2690 */ 2691 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2692 2693 /* Free the RX lists. */ 2694 bge_free_rx_ring_std(sc); 2695 2696 /* Free jumbo RX list. */ 2697 bge_free_rx_ring_jumbo(sc); 2698 2699 /* Free TX buffers. */ 2700 bge_free_tx_ring(sc); 2701 2702 /* 2703 * Isolate/power down the PHY, but leave the media selection 2704 * unchanged so that things will be put back to normal when 2705 * we bring the interface back up. 2706 */ 2707 if (!sc->bge_tbi) { 2708 itmp = ifp->if_flags; 2709 ifp->if_flags |= IFF_UP; 2710 ifm = mii->mii_media.ifm_cur; 2711 mtmp = ifm->ifm_media; 2712 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2713 mii_mediachg(mii); 2714 ifm->ifm_media = mtmp; 2715 ifp->if_flags = itmp; 2716 } 2717 2718 sc->bge_link = 0; 2719 2720 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2721 2722 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2723 2724 return; 2725 } 2726 2727 /* 2728 * Stop all chip I/O so that the kernel's probe routines don't 2729 * get confused by errant DMAs when rebooting. 2730 */ 2731 static void 2732 bge_shutdown(dev) 2733 device_t dev; 2734 { 2735 struct bge_softc *sc; 2736 2737 sc = device_get_softc(dev); 2738 2739 bge_stop(sc); 2740 bge_reset(sc); 2741 2742 return; 2743 }
Cache object: 23040ed640c8057f603653f4f38725af
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