Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/bge/if_bge.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 36 * 37 * The Broadcom BCM5700 is based on technology originally developed by 38 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 39 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 40 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 41 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 42 * frames, highly configurable RX filtering, and 16 RX and TX queues 43 * (which, along with RX filter rules, can be used for QOS applications). 44 * Other features, such as TCP segmentation, may be available as part 45 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 46 * firmware images can be stored in hardware and need not be compiled 47 * into the driver. 48 * 49 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 50 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 51 * 52 * The BCM5701 is a single-chip solution incorporating both the BCM5700 53 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 54 * does not support external SSRAM. 55 * 56 * Broadcom also produces a variation of the BCM5700 under the "Altima" 57 * brand name, which is functionally similar but lacks PCI-X support. 58 * 59 * Without external SSRAM, you can only have at most 4 TX rings, 60 * and the use of the mini RX ring is disabled. This seems to imply 61 * that these features are simply not available on the BCM5701. As a 62 * result, this driver does not implement any support for the mini RX 63 * ring. 64 */ 65 66 #include <sys/cdefs.h> 67 __FBSDID("$FreeBSD: releng/5.1/sys/dev/bge/if_bge.c 115200 2003-05-21 07:00:49Z ps $"); 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/sockio.h> 72 #include <sys/mbuf.h> 73 #include <sys/malloc.h> 74 #include <sys/kernel.h> 75 #include <sys/socket.h> 76 #include <sys/queue.h> 77 78 #include <net/if.h> 79 #include <net/if_arp.h> 80 #include <net/ethernet.h> 81 #include <net/if_dl.h> 82 #include <net/if_media.h> 83 84 #include <net/bpf.h> 85 86 #include <net/if_types.h> 87 #include <net/if_vlan_var.h> 88 89 #include <netinet/in_systm.h> 90 #include <netinet/in.h> 91 #include <netinet/ip.h> 92 93 #include <vm/vm.h> /* for vtophys */ 94 #include <vm/pmap.h> /* for vtophys */ 95 #include <machine/clock.h> /* for DELAY */ 96 #include <machine/bus_memio.h> 97 #include <machine/bus.h> 98 #include <machine/resource.h> 99 #include <sys/bus.h> 100 #include <sys/rman.h> 101 102 #include <dev/mii/mii.h> 103 #include <dev/mii/miivar.h> 104 #include "miidevs.h" 105 #include <dev/mii/brgphyreg.h> 106 107 #include <pci/pcireg.h> 108 #include <pci/pcivar.h> 109 110 #include <dev/bge/if_bgereg.h> 111 112 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 113 114 MODULE_DEPEND(bge, pci, 1, 1, 1); 115 MODULE_DEPEND(bge, ether, 1, 1, 1); 116 MODULE_DEPEND(bge, miibus, 1, 1, 1); 117 118 /* "controller miibus0" required. See GENERIC if you get errors here. */ 119 #include "miibus_if.h" 120 121 /* 122 * Various supported device vendors/types and their names. Note: the 123 * spec seems to indicate that the hardware still has Alteon's vendor 124 * ID burned into it, though it will always be overriden by the vendor 125 * ID in the EEPROM. Just to be safe, we cover all possibilities. 126 */ 127 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */ 128 129 static struct bge_type bge_devs[] = { 130 { ALT_VENDORID, ALT_DEVICEID_BCM5700, 131 "Broadcom BCM5700 Gigabit Ethernet" }, 132 { ALT_VENDORID, ALT_DEVICEID_BCM5701, 133 "Broadcom BCM5701 Gigabit Ethernet" }, 134 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700, 135 "Broadcom BCM5700 Gigabit Ethernet" }, 136 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701, 137 "Broadcom BCM5701 Gigabit Ethernet" }, 138 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X, 139 "Broadcom BCM5702X Gigabit Ethernet" }, 140 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X, 141 "Broadcom BCM5703X Gigabit Ethernet" }, 142 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C, 143 "Broadcom BCM5704C Dual Gigabit Ethernet" }, 144 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S, 145 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 146 { SK_VENDORID, SK_DEVICEID_ALTIMA, 147 "SysKonnect Gigabit Ethernet" }, 148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000, 149 "Altima AC1000 Gigabit Ethernet" }, 150 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100, 151 "Altima AC9100 Gigabit Ethernet" }, 152 { 0, 0, NULL } 153 }; 154 155 static int bge_probe (device_t); 156 static int bge_attach (device_t); 157 static int bge_detach (device_t); 158 static void bge_release_resources 159 (struct bge_softc *); 160 static void bge_txeof (struct bge_softc *); 161 static void bge_rxeof (struct bge_softc *); 162 163 static void bge_tick (void *); 164 static void bge_stats_update (struct bge_softc *); 165 static int bge_encap (struct bge_softc *, struct mbuf *, 166 u_int32_t *); 167 168 static void bge_intr (void *); 169 static void bge_start (struct ifnet *); 170 static int bge_ioctl (struct ifnet *, u_long, caddr_t); 171 static void bge_init (void *); 172 static void bge_stop (struct bge_softc *); 173 static void bge_watchdog (struct ifnet *); 174 static void bge_shutdown (device_t); 175 static int bge_ifmedia_upd (struct ifnet *); 176 static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 177 178 static u_int8_t bge_eeprom_getbyte (struct bge_softc *, int, u_int8_t *); 179 static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int); 180 181 static u_int32_t bge_crc (caddr_t); 182 static void bge_setmulti (struct bge_softc *); 183 184 static void bge_handle_events (struct bge_softc *); 185 static int bge_alloc_jumbo_mem (struct bge_softc *); 186 static void bge_free_jumbo_mem (struct bge_softc *); 187 static void *bge_jalloc (struct bge_softc *); 188 static void bge_jfree (void *, void *); 189 static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *); 190 static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *); 191 static int bge_init_rx_ring_std (struct bge_softc *); 192 static void bge_free_rx_ring_std (struct bge_softc *); 193 static int bge_init_rx_ring_jumbo (struct bge_softc *); 194 static void bge_free_rx_ring_jumbo (struct bge_softc *); 195 static void bge_free_tx_ring (struct bge_softc *); 196 static int bge_init_tx_ring (struct bge_softc *); 197 198 static int bge_chipinit (struct bge_softc *); 199 static int bge_blockinit (struct bge_softc *); 200 201 #ifdef notdef 202 static u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 203 static void bge_vpd_read_res (struct bge_softc *, struct vpd_res *, int); 204 static void bge_vpd_read (struct bge_softc *); 205 #endif 206 207 static u_int32_t bge_readmem_ind 208 (struct bge_softc *, int); 209 static void bge_writemem_ind (struct bge_softc *, int, int); 210 #ifdef notdef 211 static u_int32_t bge_readreg_ind 212 (struct bge_softc *, int); 213 #endif 214 static void bge_writereg_ind (struct bge_softc *, int, int); 215 216 static int bge_miibus_readreg (device_t, int, int); 217 static int bge_miibus_writereg (device_t, int, int, int); 218 static void bge_miibus_statchg (device_t); 219 220 static void bge_reset (struct bge_softc *); 221 222 static device_method_t bge_methods[] = { 223 /* Device interface */ 224 DEVMETHOD(device_probe, bge_probe), 225 DEVMETHOD(device_attach, bge_attach), 226 DEVMETHOD(device_detach, bge_detach), 227 DEVMETHOD(device_shutdown, bge_shutdown), 228 229 /* bus interface */ 230 DEVMETHOD(bus_print_child, bus_generic_print_child), 231 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 232 233 /* MII interface */ 234 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 235 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 236 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 237 238 { 0, 0 } 239 }; 240 241 static driver_t bge_driver = { 242 "bge", 243 bge_methods, 244 sizeof(struct bge_softc) 245 }; 246 247 static devclass_t bge_devclass; 248 249 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 250 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 251 252 static u_int32_t 253 bge_readmem_ind(sc, off) 254 struct bge_softc *sc; 255 int off; 256 { 257 device_t dev; 258 259 dev = sc->bge_dev; 260 261 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 262 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 263 } 264 265 static void 266 bge_writemem_ind(sc, off, val) 267 struct bge_softc *sc; 268 int off, val; 269 { 270 device_t dev; 271 272 dev = sc->bge_dev; 273 274 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 275 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 276 277 return; 278 } 279 280 #ifdef notdef 281 static u_int32_t 282 bge_readreg_ind(sc, off) 283 struct bge_softc *sc; 284 int off; 285 { 286 device_t dev; 287 288 dev = sc->bge_dev; 289 290 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 291 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 292 } 293 #endif 294 295 static void 296 bge_writereg_ind(sc, off, val) 297 struct bge_softc *sc; 298 int off, val; 299 { 300 device_t dev; 301 302 dev = sc->bge_dev; 303 304 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 305 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 306 307 return; 308 } 309 310 #ifdef notdef 311 static u_int8_t 312 bge_vpd_readbyte(sc, addr) 313 struct bge_softc *sc; 314 int addr; 315 { 316 int i; 317 device_t dev; 318 u_int32_t val; 319 320 dev = sc->bge_dev; 321 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 322 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 323 DELAY(10); 324 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 325 break; 326 } 327 328 if (i == BGE_TIMEOUT) { 329 printf("bge%d: VPD read timed out\n", sc->bge_unit); 330 return(0); 331 } 332 333 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 334 335 return((val >> ((addr % 4) * 8)) & 0xFF); 336 } 337 338 static void 339 bge_vpd_read_res(sc, res, addr) 340 struct bge_softc *sc; 341 struct vpd_res *res; 342 int addr; 343 { 344 int i; 345 u_int8_t *ptr; 346 347 ptr = (u_int8_t *)res; 348 for (i = 0; i < sizeof(struct vpd_res); i++) 349 ptr[i] = bge_vpd_readbyte(sc, i + addr); 350 351 return; 352 } 353 354 static void 355 bge_vpd_read(sc) 356 struct bge_softc *sc; 357 { 358 int pos = 0, i; 359 struct vpd_res res; 360 361 if (sc->bge_vpd_prodname != NULL) 362 free(sc->bge_vpd_prodname, M_DEVBUF); 363 if (sc->bge_vpd_readonly != NULL) 364 free(sc->bge_vpd_readonly, M_DEVBUF); 365 sc->bge_vpd_prodname = NULL; 366 sc->bge_vpd_readonly = NULL; 367 368 bge_vpd_read_res(sc, &res, pos); 369 370 if (res.vr_id != VPD_RES_ID) { 371 printf("bge%d: bad VPD resource id: expected %x got %x\n", 372 sc->bge_unit, VPD_RES_ID, res.vr_id); 373 return; 374 } 375 376 pos += sizeof(res); 377 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 378 for (i = 0; i < res.vr_len; i++) 379 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 380 sc->bge_vpd_prodname[i] = '\0'; 381 pos += i; 382 383 bge_vpd_read_res(sc, &res, pos); 384 385 if (res.vr_id != VPD_RES_READ) { 386 printf("bge%d: bad VPD resource id: expected %x got %x\n", 387 sc->bge_unit, VPD_RES_READ, res.vr_id); 388 return; 389 } 390 391 pos += sizeof(res); 392 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 393 for (i = 0; i < res.vr_len + 1; i++) 394 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 395 396 return; 397 } 398 #endif 399 400 /* 401 * Read a byte of data stored in the EEPROM at address 'addr.' The 402 * BCM570x supports both the traditional bitbang interface and an 403 * auto access interface for reading the EEPROM. We use the auto 404 * access method. 405 */ 406 static u_int8_t 407 bge_eeprom_getbyte(sc, addr, dest) 408 struct bge_softc *sc; 409 int addr; 410 u_int8_t *dest; 411 { 412 int i; 413 u_int32_t byte = 0; 414 415 /* 416 * Enable use of auto EEPROM access so we can avoid 417 * having to use the bitbang method. 418 */ 419 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 420 421 /* Reset the EEPROM, load the clock period. */ 422 CSR_WRITE_4(sc, BGE_EE_ADDR, 423 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 424 DELAY(20); 425 426 /* Issue the read EEPROM command. */ 427 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 428 429 /* Wait for completion */ 430 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 431 DELAY(10); 432 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 433 break; 434 } 435 436 if (i == BGE_TIMEOUT) { 437 printf("bge%d: eeprom read timed out\n", sc->bge_unit); 438 return(0); 439 } 440 441 /* Get result. */ 442 byte = CSR_READ_4(sc, BGE_EE_DATA); 443 444 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 445 446 return(0); 447 } 448 449 /* 450 * Read a sequence of bytes from the EEPROM. 451 */ 452 static int 453 bge_read_eeprom(sc, dest, off, cnt) 454 struct bge_softc *sc; 455 caddr_t dest; 456 int off; 457 int cnt; 458 { 459 int err = 0, i; 460 u_int8_t byte = 0; 461 462 for (i = 0; i < cnt; i++) { 463 err = bge_eeprom_getbyte(sc, off + i, &byte); 464 if (err) 465 break; 466 *(dest + i) = byte; 467 } 468 469 return(err ? 1 : 0); 470 } 471 472 static int 473 bge_miibus_readreg(dev, phy, reg) 474 device_t dev; 475 int phy, reg; 476 { 477 struct bge_softc *sc; 478 struct ifnet *ifp; 479 u_int32_t val, autopoll; 480 int i; 481 482 sc = device_get_softc(dev); 483 ifp = &sc->arpcom.ac_if; 484 485 if (phy != 1) 486 switch(sc->bge_chipid) { 487 case BGE_CHIPID_BCM5701_B5: 488 case BGE_CHIPID_BCM5703_A2: 489 case BGE_CHIPID_BCM5704_A0: 490 return(0); 491 } 492 493 /* Reading with autopolling on may trigger PCI errors */ 494 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 495 if (autopoll & BGE_MIMODE_AUTOPOLL) { 496 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 497 DELAY(40); 498 } 499 500 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 501 BGE_MIPHY(phy)|BGE_MIREG(reg)); 502 503 for (i = 0; i < BGE_TIMEOUT; i++) { 504 val = CSR_READ_4(sc, BGE_MI_COMM); 505 if (!(val & BGE_MICOMM_BUSY)) 506 break; 507 } 508 509 if (i == BGE_TIMEOUT) { 510 printf("bge%d: PHY read timed out\n", sc->bge_unit); 511 val = 0; 512 goto done; 513 } 514 515 val = CSR_READ_4(sc, BGE_MI_COMM); 516 517 done: 518 if (autopoll & BGE_MIMODE_AUTOPOLL) { 519 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 520 DELAY(40); 521 } 522 523 if (val & BGE_MICOMM_READFAIL) 524 return(0); 525 526 return(val & 0xFFFF); 527 } 528 529 static int 530 bge_miibus_writereg(dev, phy, reg, val) 531 device_t dev; 532 int phy, reg, val; 533 { 534 struct bge_softc *sc; 535 u_int32_t autopoll; 536 int i; 537 538 sc = device_get_softc(dev); 539 540 /* Reading with autopolling on may trigger PCI errors */ 541 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 542 if (autopoll & BGE_MIMODE_AUTOPOLL) { 543 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 544 DELAY(40); 545 } 546 547 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 548 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 549 550 for (i = 0; i < BGE_TIMEOUT; i++) { 551 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 552 break; 553 } 554 555 if (autopoll & BGE_MIMODE_AUTOPOLL) { 556 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 557 DELAY(40); 558 } 559 560 if (i == BGE_TIMEOUT) { 561 printf("bge%d: PHY read timed out\n", sc->bge_unit); 562 return(0); 563 } 564 565 return(0); 566 } 567 568 static void 569 bge_miibus_statchg(dev) 570 device_t dev; 571 { 572 struct bge_softc *sc; 573 struct mii_data *mii; 574 575 sc = device_get_softc(dev); 576 mii = device_get_softc(sc->bge_miibus); 577 578 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 579 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 580 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 581 } else { 582 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 583 } 584 585 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 586 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 587 } else { 588 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 589 } 590 591 return; 592 } 593 594 /* 595 * Handle events that have triggered interrupts. 596 */ 597 static void 598 bge_handle_events(sc) 599 struct bge_softc *sc; 600 { 601 602 return; 603 } 604 605 /* 606 * Memory management for jumbo frames. 607 */ 608 609 static int 610 bge_alloc_jumbo_mem(sc) 611 struct bge_softc *sc; 612 { 613 caddr_t ptr; 614 register int i; 615 struct bge_jpool_entry *entry; 616 617 /* Grab a big chunk o' storage. */ 618 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF, 619 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 620 621 if (sc->bge_cdata.bge_jumbo_buf == NULL) { 622 printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit); 623 return(ENOBUFS); 624 } 625 626 SLIST_INIT(&sc->bge_jfree_listhead); 627 SLIST_INIT(&sc->bge_jinuse_listhead); 628 629 /* 630 * Now divide it up into 9K pieces and save the addresses 631 * in an array. 632 */ 633 ptr = sc->bge_cdata.bge_jumbo_buf; 634 for (i = 0; i < BGE_JSLOTS; i++) { 635 sc->bge_cdata.bge_jslots[i] = ptr; 636 ptr += BGE_JLEN; 637 entry = malloc(sizeof(struct bge_jpool_entry), 638 M_DEVBUF, M_NOWAIT); 639 if (entry == NULL) { 640 contigfree(sc->bge_cdata.bge_jumbo_buf, 641 BGE_JMEM, M_DEVBUF); 642 sc->bge_cdata.bge_jumbo_buf = NULL; 643 printf("bge%d: no memory for jumbo " 644 "buffer queue!\n", sc->bge_unit); 645 return(ENOBUFS); 646 } 647 entry->slot = i; 648 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 649 entry, jpool_entries); 650 } 651 652 return(0); 653 } 654 655 static void 656 bge_free_jumbo_mem(sc) 657 struct bge_softc *sc; 658 { 659 int i; 660 struct bge_jpool_entry *entry; 661 662 for (i = 0; i < BGE_JSLOTS; i++) { 663 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 664 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 665 free(entry, M_DEVBUF); 666 } 667 668 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF); 669 670 return; 671 } 672 673 /* 674 * Allocate a jumbo buffer. 675 */ 676 static void * 677 bge_jalloc(sc) 678 struct bge_softc *sc; 679 { 680 struct bge_jpool_entry *entry; 681 682 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 683 684 if (entry == NULL) { 685 printf("bge%d: no free jumbo buffers\n", sc->bge_unit); 686 return(NULL); 687 } 688 689 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 690 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 691 return(sc->bge_cdata.bge_jslots[entry->slot]); 692 } 693 694 /* 695 * Release a jumbo buffer. 696 */ 697 static void 698 bge_jfree(buf, args) 699 void *buf; 700 void *args; 701 { 702 struct bge_jpool_entry *entry; 703 struct bge_softc *sc; 704 int i; 705 706 /* Extract the softc struct pointer. */ 707 sc = (struct bge_softc *)args; 708 709 if (sc == NULL) 710 panic("bge_jfree: can't find softc pointer!"); 711 712 /* calculate the slot this buffer belongs to */ 713 714 i = ((vm_offset_t)buf 715 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 716 717 if ((i < 0) || (i >= BGE_JSLOTS)) 718 panic("bge_jfree: asked to free buffer that we don't manage!"); 719 720 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 721 if (entry == NULL) 722 panic("bge_jfree: buffer not in use!"); 723 entry->slot = i; 724 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 725 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 726 727 return; 728 } 729 730 731 /* 732 * Intialize a standard receive ring descriptor. 733 */ 734 static int 735 bge_newbuf_std(sc, i, m) 736 struct bge_softc *sc; 737 int i; 738 struct mbuf *m; 739 { 740 struct mbuf *m_new = NULL; 741 struct bge_rx_bd *r; 742 743 if (m == NULL) { 744 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 745 if (m_new == NULL) { 746 return(ENOBUFS); 747 } 748 749 MCLGET(m_new, M_DONTWAIT); 750 if (!(m_new->m_flags & M_EXT)) { 751 m_freem(m_new); 752 return(ENOBUFS); 753 } 754 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 755 } else { 756 m_new = m; 757 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 758 m_new->m_data = m_new->m_ext.ext_buf; 759 } 760 761 if (!sc->bge_rx_alignment_bug) 762 m_adj(m_new, ETHER_ALIGN); 763 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 764 r = &sc->bge_rdata->bge_rx_std_ring[i]; 765 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t))); 766 r->bge_flags = BGE_RXBDFLAG_END; 767 r->bge_len = m_new->m_len; 768 r->bge_idx = i; 769 770 return(0); 771 } 772 773 /* 774 * Initialize a jumbo receive ring descriptor. This allocates 775 * a jumbo buffer from the pool managed internally by the driver. 776 */ 777 static int 778 bge_newbuf_jumbo(sc, i, m) 779 struct bge_softc *sc; 780 int i; 781 struct mbuf *m; 782 { 783 struct mbuf *m_new = NULL; 784 struct bge_rx_bd *r; 785 786 if (m == NULL) { 787 caddr_t *buf = NULL; 788 789 /* Allocate the mbuf. */ 790 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 791 if (m_new == NULL) { 792 return(ENOBUFS); 793 } 794 795 /* Allocate the jumbo buffer */ 796 buf = bge_jalloc(sc); 797 if (buf == NULL) { 798 m_freem(m_new); 799 printf("bge%d: jumbo allocation failed " 800 "-- packet dropped!\n", sc->bge_unit); 801 return(ENOBUFS); 802 } 803 804 /* Attach the buffer to the mbuf. */ 805 m_new->m_data = (void *) buf; 806 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 807 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree, 808 (struct bge_softc *)sc, 0, EXT_NET_DRV); 809 } else { 810 m_new = m; 811 m_new->m_data = m_new->m_ext.ext_buf; 812 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 813 } 814 815 if (!sc->bge_rx_alignment_bug) 816 m_adj(m_new, ETHER_ALIGN); 817 /* Set up the descriptor. */ 818 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 819 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 820 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t))); 821 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 822 r->bge_len = m_new->m_len; 823 r->bge_idx = i; 824 825 return(0); 826 } 827 828 /* 829 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 830 * that's 1MB or memory, which is a lot. For now, we fill only the first 831 * 256 ring entries and hope that our CPU is fast enough to keep up with 832 * the NIC. 833 */ 834 static int 835 bge_init_rx_ring_std(sc) 836 struct bge_softc *sc; 837 { 838 int i; 839 840 for (i = 0; i < BGE_SSLOTS; i++) { 841 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 842 return(ENOBUFS); 843 }; 844 845 sc->bge_std = i - 1; 846 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 847 848 return(0); 849 } 850 851 static void 852 bge_free_rx_ring_std(sc) 853 struct bge_softc *sc; 854 { 855 int i; 856 857 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 858 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 859 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 860 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 861 } 862 bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i], 863 sizeof(struct bge_rx_bd)); 864 } 865 866 return; 867 } 868 869 static int 870 bge_init_rx_ring_jumbo(sc) 871 struct bge_softc *sc; 872 { 873 int i; 874 struct bge_rcb *rcb; 875 876 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 877 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 878 return(ENOBUFS); 879 }; 880 881 sc->bge_jumbo = i - 1; 882 883 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 884 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 885 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 886 887 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 888 889 return(0); 890 } 891 892 static void 893 bge_free_rx_ring_jumbo(sc) 894 struct bge_softc *sc; 895 { 896 int i; 897 898 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 899 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 900 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 901 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 902 } 903 bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 904 sizeof(struct bge_rx_bd)); 905 } 906 907 return; 908 } 909 910 static void 911 bge_free_tx_ring(sc) 912 struct bge_softc *sc; 913 { 914 int i; 915 916 if (sc->bge_rdata->bge_tx_ring == NULL) 917 return; 918 919 for (i = 0; i < BGE_TX_RING_CNT; i++) { 920 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 921 m_freem(sc->bge_cdata.bge_tx_chain[i]); 922 sc->bge_cdata.bge_tx_chain[i] = NULL; 923 } 924 bzero((char *)&sc->bge_rdata->bge_tx_ring[i], 925 sizeof(struct bge_tx_bd)); 926 } 927 928 return; 929 } 930 931 static int 932 bge_init_tx_ring(sc) 933 struct bge_softc *sc; 934 { 935 sc->bge_txcnt = 0; 936 sc->bge_tx_saved_considx = 0; 937 938 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 939 /* 5700 b2 errata */ 940 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 941 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 942 943 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 944 /* 5700 b2 errata */ 945 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 946 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 947 948 return(0); 949 } 950 951 #define BGE_POLY 0xEDB88320 952 953 static u_int32_t 954 bge_crc(addr) 955 caddr_t addr; 956 { 957 u_int32_t idx, bit, data, crc; 958 959 /* Compute CRC for the address value. */ 960 crc = 0xFFFFFFFF; /* initial value */ 961 962 for (idx = 0; idx < 6; idx++) { 963 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 964 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 965 } 966 967 return(crc & 0x7F); 968 } 969 970 static void 971 bge_setmulti(sc) 972 struct bge_softc *sc; 973 { 974 struct ifnet *ifp; 975 struct ifmultiaddr *ifma; 976 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 977 int h, i; 978 979 ifp = &sc->arpcom.ac_if; 980 981 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 982 for (i = 0; i < 4; i++) 983 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 984 return; 985 } 986 987 /* First, zot all the existing filters. */ 988 for (i = 0; i < 4; i++) 989 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 990 991 /* Now program new ones. */ 992 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 993 if (ifma->ifma_addr->sa_family != AF_LINK) 994 continue; 995 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 996 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 997 } 998 999 for (i = 0; i < 4; i++) 1000 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1001 1002 return; 1003 } 1004 1005 /* 1006 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1007 * self-test results. 1008 */ 1009 static int 1010 bge_chipinit(sc) 1011 struct bge_softc *sc; 1012 { 1013 int i; 1014 u_int32_t dma_rw_ctl; 1015 1016 /* Set endianness before we access any non-PCI registers. */ 1017 #if BYTE_ORDER == BIG_ENDIAN 1018 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1019 BGE_BIGENDIAN_INIT, 4); 1020 #else 1021 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1022 BGE_LITTLEENDIAN_INIT, 4); 1023 #endif 1024 1025 /* 1026 * Check the 'ROM failed' bit on the RX CPU to see if 1027 * self-tests passed. 1028 */ 1029 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1030 printf("bge%d: RX CPU self-diagnostics failed!\n", 1031 sc->bge_unit); 1032 return(ENODEV); 1033 } 1034 1035 /* Clear the MAC control register */ 1036 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1037 1038 /* 1039 * Clear the MAC statistics block in the NIC's 1040 * internal memory. 1041 */ 1042 for (i = BGE_STATS_BLOCK; 1043 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1044 BGE_MEMWIN_WRITE(sc, i, 0); 1045 1046 for (i = BGE_STATUS_BLOCK; 1047 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1048 BGE_MEMWIN_WRITE(sc, i, 0); 1049 1050 /* Set up the PCI DMA control register. */ 1051 if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 1052 BGE_PCISTATE_PCI_BUSMODE) { 1053 /* Conventional PCI bus */ 1054 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1055 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1056 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1057 (0x0F); 1058 } else { 1059 /* PCI-X bus */ 1060 /* 1061 * The 5704 uses a different encoding of read/write 1062 * watermarks. 1063 */ 1064 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1065 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1066 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1067 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1068 else 1069 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1070 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1071 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1072 (0x0F); 1073 1074 /* 1075 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1076 * for hardware bugs. 1077 */ 1078 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1079 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1080 u_int32_t tmp; 1081 1082 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1083 if (tmp == 0x6 || tmp == 0x7) 1084 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1085 } 1086 } 1087 1088 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1089 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1090 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1091 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1092 1093 /* 1094 * Set up general mode register. 1095 */ 1096 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 1097 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1098 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1099 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| 1100 BGE_MODECTL_RX_NO_PHDR_CSUM); 1101 1102 /* 1103 * Disable memory write invalidate. Apparently it is not supported 1104 * properly by these devices. 1105 */ 1106 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1107 1108 #ifdef __brokenalpha__ 1109 /* 1110 * Must insure that we do not cross an 8K (bytes) boundary 1111 * for DMA reads. Our highest limit is 1K bytes. This is a 1112 * restriction on some ALPHA platforms with early revision 1113 * 21174 PCI chipsets, such as the AlphaPC 164lx 1114 */ 1115 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1116 BGE_PCI_READ_BNDRY_1024BYTES, 4); 1117 #endif 1118 1119 /* Set the timer prescaler (always 66Mhz) */ 1120 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1121 1122 return(0); 1123 } 1124 1125 static int 1126 bge_blockinit(sc) 1127 struct bge_softc *sc; 1128 { 1129 struct bge_rcb *rcb; 1130 volatile struct bge_rcb *vrcb; 1131 int i; 1132 1133 /* 1134 * Initialize the memory window pointer register so that 1135 * we can access the first 32K of internal NIC RAM. This will 1136 * allow us to set up the TX send ring RCBs and the RX return 1137 * ring RCBs, plus other things which live in NIC memory. 1138 */ 1139 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1140 1141 /* Configure mbuf memory pool */ 1142 if (sc->bge_extram) { 1143 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM); 1144 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1145 } else { 1146 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1147 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1148 } 1149 1150 /* Configure DMA resource pool */ 1151 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS); 1152 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1153 1154 /* Configure mbuf pool watermarks */ 1155 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1156 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1157 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1158 1159 /* Configure DMA resource watermarks */ 1160 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1161 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1162 1163 /* Enable buffer manager */ 1164 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1165 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1166 1167 /* Poll for buffer manager start indication */ 1168 for (i = 0; i < BGE_TIMEOUT; i++) { 1169 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1170 break; 1171 DELAY(10); 1172 } 1173 1174 if (i == BGE_TIMEOUT) { 1175 printf("bge%d: buffer manager failed to start\n", 1176 sc->bge_unit); 1177 return(ENXIO); 1178 } 1179 1180 /* Enable flow-through queues */ 1181 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1182 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1183 1184 /* Wait until queue initialization is complete */ 1185 for (i = 0; i < BGE_TIMEOUT; i++) { 1186 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1187 break; 1188 DELAY(10); 1189 } 1190 1191 if (i == BGE_TIMEOUT) { 1192 printf("bge%d: flow-through queue init failed\n", 1193 sc->bge_unit); 1194 return(ENXIO); 1195 } 1196 1197 /* Initialize the standard RX ring control block */ 1198 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1199 BGE_HOSTADDR(rcb->bge_hostaddr, 1200 vtophys(&sc->bge_rdata->bge_rx_std_ring)); 1201 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1202 if (sc->bge_extram) 1203 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1204 else 1205 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1206 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1207 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1208 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1209 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1210 1211 /* 1212 * Initialize the jumbo RX ring control block 1213 * We set the 'ring disabled' bit in the flags 1214 * field until we're actually ready to start 1215 * using this ring (i.e. once we set the MTU 1216 * high enough to require it). 1217 */ 1218 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1219 BGE_HOSTADDR(rcb->bge_hostaddr, 1220 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring)); 1221 rcb->bge_maxlen_flags = 1222 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, BGE_RCB_FLAG_RING_DISABLED); 1223 if (sc->bge_extram) 1224 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1225 else 1226 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1227 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1228 rcb->bge_hostaddr.bge_addr_hi); 1229 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1230 rcb->bge_hostaddr.bge_addr_lo); 1231 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1232 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1233 1234 /* Set up dummy disabled mini ring RCB */ 1235 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1236 rcb->bge_maxlen_flags = 1237 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1238 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1239 1240 /* 1241 * Set the BD ring replentish thresholds. The recommended 1242 * values are 1/8th the number of descriptors allocated to 1243 * each ring. 1244 */ 1245 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1246 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1247 1248 /* 1249 * Disable all unused send rings by setting the 'ring disabled' 1250 * bit in the flags field of all the TX send ring control blocks. 1251 * These are located in NIC memory. 1252 */ 1253 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1254 BGE_SEND_RING_RCB); 1255 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1256 vrcb->bge_maxlen_flags = 1257 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1258 vrcb->bge_nicaddr = 0; 1259 vrcb++; 1260 } 1261 1262 /* Configure TX RCB 0 (we use only the first ring) */ 1263 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1264 BGE_SEND_RING_RCB); 1265 vrcb->bge_hostaddr.bge_addr_hi = 0; 1266 BGE_HOSTADDR(vrcb->bge_hostaddr, vtophys(&sc->bge_rdata->bge_tx_ring)); 1267 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 1268 vrcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0); 1269 1270 /* Disable all unused RX return rings */ 1271 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1272 BGE_RX_RETURN_RING_RCB); 1273 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1274 vrcb->bge_hostaddr.bge_addr_hi = 0; 1275 vrcb->bge_hostaddr.bge_addr_lo = 0; 1276 vrcb->bge_maxlen_flags = 1277 BGE_RCB_MAXLEN_FLAGS(BGE_RETURN_RING_CNT, 1278 BGE_RCB_FLAG_RING_DISABLED); 1279 vrcb->bge_nicaddr = 0; 1280 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1281 (i * (sizeof(u_int64_t))), 0); 1282 vrcb++; 1283 } 1284 1285 /* Initialize RX ring indexes */ 1286 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1287 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1288 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1289 1290 /* 1291 * Set up RX return ring 0 1292 * Note that the NIC address for RX return rings is 0x00000000. 1293 * The return rings live entirely within the host, so the 1294 * nicaddr field in the RCB isn't used. 1295 */ 1296 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1297 BGE_RX_RETURN_RING_RCB); 1298 vrcb->bge_hostaddr.bge_addr_hi = 0; 1299 BGE_HOSTADDR(vrcb->bge_hostaddr, 1300 vtophys(&sc->bge_rdata->bge_rx_return_ring)); 1301 vrcb->bge_nicaddr = 0x00000000; 1302 vrcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(BGE_RETURN_RING_CNT, 0); 1303 1304 /* Set random backoff seed for TX */ 1305 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1306 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1307 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1308 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1309 BGE_TX_BACKOFF_SEED_MASK); 1310 1311 /* Set inter-packet gap */ 1312 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1313 1314 /* 1315 * Specify which ring to use for packets that don't match 1316 * any RX rules. 1317 */ 1318 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1319 1320 /* 1321 * Configure number of RX lists. One interrupt distribution 1322 * list, sixteen active lists, one bad frames class. 1323 */ 1324 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1325 1326 /* Inialize RX list placement stats mask. */ 1327 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1328 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1329 1330 /* Disable host coalescing until we get it set up */ 1331 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1332 1333 /* Poll to make sure it's shut down. */ 1334 for (i = 0; i < BGE_TIMEOUT; i++) { 1335 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1336 break; 1337 DELAY(10); 1338 } 1339 1340 if (i == BGE_TIMEOUT) { 1341 printf("bge%d: host coalescing engine failed to idle\n", 1342 sc->bge_unit); 1343 return(ENXIO); 1344 } 1345 1346 /* Set up host coalescing defaults */ 1347 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1348 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1349 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1350 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1351 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1352 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1353 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1354 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1355 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1356 1357 /* Set up address of statistics block */ 1358 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1359 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0); 1360 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1361 vtophys(&sc->bge_rdata->bge_info.bge_stats)); 1362 1363 /* Set up address of status block */ 1364 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1365 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0); 1366 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1367 vtophys(&sc->bge_rdata->bge_status_block)); 1368 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1369 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1370 1371 /* Turn on host coalescing state machine */ 1372 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1373 1374 /* Turn on RX BD completion state machine and enable attentions */ 1375 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1376 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1377 1378 /* Turn on RX list placement state machine */ 1379 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1380 1381 /* Turn on RX list selector state machine. */ 1382 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1383 1384 /* Turn on DMA, clear stats */ 1385 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1386 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1387 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1388 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1389 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1390 1391 /* Set misc. local control, enable interrupts on attentions */ 1392 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1393 1394 #ifdef notdef 1395 /* Assert GPIO pins for PHY reset */ 1396 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1397 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1398 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1399 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1400 #endif 1401 1402 /* Turn on DMA completion state machine */ 1403 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1404 1405 /* Turn on write DMA state machine */ 1406 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1407 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1408 1409 /* Turn on read DMA state machine */ 1410 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1411 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1412 1413 /* Turn on RX data completion state machine */ 1414 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1415 1416 /* Turn on RX BD initiator state machine */ 1417 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1418 1419 /* Turn on RX data and RX BD initiator state machine */ 1420 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1421 1422 /* Turn on Mbuf cluster free state machine */ 1423 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1424 1425 /* Turn on send BD completion state machine */ 1426 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1427 1428 /* Turn on send data completion state machine */ 1429 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1430 1431 /* Turn on send data initiator state machine */ 1432 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1433 1434 /* Turn on send BD initiator state machine */ 1435 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1436 1437 /* Turn on send BD selector state machine */ 1438 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1439 1440 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1441 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1442 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1443 1444 /* ack/clear link change events */ 1445 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1446 BGE_MACSTAT_CFG_CHANGED); 1447 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1448 1449 /* Enable PHY auto polling (for MII/GMII only) */ 1450 if (sc->bge_tbi) { 1451 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1452 } else { 1453 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1454 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1455 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1456 BGE_EVTENB_MI_INTERRUPT); 1457 } 1458 1459 /* Enable link state change attentions. */ 1460 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1461 1462 return(0); 1463 } 1464 1465 /* 1466 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1467 * against our list and return its name if we find a match. Note 1468 * that since the Broadcom controller contains VPD support, we 1469 * can get the device name string from the controller itself instead 1470 * of the compiled-in string. This is a little slow, but it guarantees 1471 * we'll always announce the right product name. 1472 */ 1473 static int 1474 bge_probe(dev) 1475 device_t dev; 1476 { 1477 struct bge_type *t; 1478 struct bge_softc *sc; 1479 char *descbuf; 1480 1481 t = bge_devs; 1482 1483 sc = device_get_softc(dev); 1484 bzero(sc, sizeof(struct bge_softc)); 1485 sc->bge_unit = device_get_unit(dev); 1486 sc->bge_dev = dev; 1487 1488 while(t->bge_name != NULL) { 1489 if ((pci_get_vendor(dev) == t->bge_vid) && 1490 (pci_get_device(dev) == t->bge_did)) { 1491 #ifdef notdef 1492 bge_vpd_read(sc); 1493 device_set_desc(dev, sc->bge_vpd_prodname); 1494 #endif 1495 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 1496 if (descbuf == NULL) 1497 return(ENOMEM); 1498 snprintf(descbuf, BGE_DEVDESC_MAX, 1499 "%s, ASIC rev. %#04x", t->bge_name, 1500 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16); 1501 device_set_desc_copy(dev, descbuf); 1502 free(descbuf, M_TEMP); 1503 return(0); 1504 } 1505 t++; 1506 } 1507 1508 return(ENXIO); 1509 } 1510 1511 static int 1512 bge_attach(dev) 1513 device_t dev; 1514 { 1515 int s; 1516 struct ifnet *ifp; 1517 struct bge_softc *sc; 1518 u_int32_t hwcfg = 0; 1519 u_int32_t mac_addr = 0; 1520 int unit, error = 0, rid; 1521 1522 s = splimp(); 1523 1524 sc = device_get_softc(dev); 1525 unit = device_get_unit(dev); 1526 sc->bge_dev = dev; 1527 sc->bge_unit = unit; 1528 1529 /* 1530 * Map control/status registers. 1531 */ 1532 pci_enable_busmaster(dev); 1533 1534 rid = BGE_PCI_BAR0; 1535 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1536 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 1537 1538 if (sc->bge_res == NULL) { 1539 printf ("bge%d: couldn't map memory\n", unit); 1540 error = ENXIO; 1541 goto fail; 1542 } 1543 1544 sc->bge_btag = rman_get_bustag(sc->bge_res); 1545 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 1546 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 1547 1548 /* Allocate interrupt */ 1549 rid = 0; 1550 1551 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1552 RF_SHAREABLE | RF_ACTIVE); 1553 1554 if (sc->bge_irq == NULL) { 1555 printf("bge%d: couldn't map interrupt\n", unit); 1556 error = ENXIO; 1557 goto fail; 1558 } 1559 1560 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET, 1561 bge_intr, sc, &sc->bge_intrhand); 1562 1563 if (error) { 1564 bge_release_resources(sc); 1565 printf("bge%d: couldn't set up irq\n", unit); 1566 goto fail; 1567 } 1568 1569 sc->bge_unit = unit; 1570 1571 /* Try to reset the chip. */ 1572 bge_reset(sc); 1573 1574 if (bge_chipinit(sc)) { 1575 printf("bge%d: chip initialization failed\n", sc->bge_unit); 1576 bge_release_resources(sc); 1577 error = ENXIO; 1578 goto fail; 1579 } 1580 1581 /* 1582 * Get station address from the EEPROM. 1583 */ 1584 mac_addr = bge_readmem_ind(sc, 0x0c14); 1585 if ((mac_addr >> 16) == 0x484b) { 1586 sc->arpcom.ac_enaddr[0] = (u_char)(mac_addr >> 8); 1587 sc->arpcom.ac_enaddr[1] = (u_char)mac_addr; 1588 mac_addr = bge_readmem_ind(sc, 0x0c18); 1589 sc->arpcom.ac_enaddr[2] = (u_char)(mac_addr >> 24); 1590 sc->arpcom.ac_enaddr[3] = (u_char)(mac_addr >> 16); 1591 sc->arpcom.ac_enaddr[4] = (u_char)(mac_addr >> 8); 1592 sc->arpcom.ac_enaddr[5] = (u_char)mac_addr; 1593 } else if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1594 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1595 printf("bge%d: failed to read station address\n", unit); 1596 bge_release_resources(sc); 1597 error = ENXIO; 1598 goto fail; 1599 } 1600 1601 /* 1602 * A Broadcom chip was detected. Inform the world. 1603 */ 1604 printf("bge%d: Ethernet address: %6D\n", unit, 1605 sc->arpcom.ac_enaddr, ":"); 1606 1607 /* Allocate the general information block and ring buffers. */ 1608 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF, 1609 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1610 1611 if (sc->bge_rdata == NULL) { 1612 bge_release_resources(sc); 1613 error = ENXIO; 1614 printf("bge%d: no memory for list buffers!\n", sc->bge_unit); 1615 goto fail; 1616 } 1617 1618 bzero(sc->bge_rdata, sizeof(struct bge_ring_data)); 1619 1620 /* Try to allocate memory for jumbo buffers. */ 1621 if (bge_alloc_jumbo_mem(sc)) { 1622 printf("bge%d: jumbo buffer allocation " 1623 "failed\n", sc->bge_unit); 1624 bge_release_resources(sc); 1625 error = ENXIO; 1626 goto fail; 1627 } 1628 1629 /* Set default tuneable values. */ 1630 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1631 sc->bge_rx_coal_ticks = 150; 1632 sc->bge_tx_coal_ticks = 150; 1633 sc->bge_rx_max_coal_bds = 64; 1634 sc->bge_tx_max_coal_bds = 128; 1635 1636 /* Set up ifnet structure */ 1637 ifp = &sc->arpcom.ac_if; 1638 ifp->if_softc = sc; 1639 ifp->if_unit = sc->bge_unit; 1640 ifp->if_name = "bge"; 1641 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1642 ifp->if_ioctl = bge_ioctl; 1643 ifp->if_output = ether_output; 1644 ifp->if_start = bge_start; 1645 ifp->if_watchdog = bge_watchdog; 1646 ifp->if_init = bge_init; 1647 ifp->if_mtu = ETHERMTU; 1648 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1; 1649 ifp->if_hwassist = BGE_CSUM_FEATURES; 1650 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 1651 ifp->if_capenable = ifp->if_capabilities; 1652 1653 /* Save ASIC rev. */ 1654 1655 sc->bge_chipid = 1656 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 1657 BGE_PCIMISCCTL_ASICREV; 1658 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 1659 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 1660 1661 /* 1662 * Figure out what sort of media we have by checking the 1663 * hardware config word in the first 32k of NIC internal memory, 1664 * or fall back to examining the EEPROM if necessary. 1665 * Note: on some BCM5700 cards, this value appears to be unset. 1666 * If that's the case, we have to rely on identifying the NIC 1667 * by its PCI subsystem ID, as we do below for the SysKonnect 1668 * SK-9D41. 1669 */ 1670 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 1671 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 1672 else { 1673 bge_read_eeprom(sc, (caddr_t)&hwcfg, 1674 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 1675 hwcfg = ntohl(hwcfg); 1676 } 1677 1678 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 1679 sc->bge_tbi = 1; 1680 1681 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1682 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 1683 sc->bge_tbi = 1; 1684 1685 if (sc->bge_tbi) { 1686 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 1687 bge_ifmedia_upd, bge_ifmedia_sts); 1688 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1689 ifmedia_add(&sc->bge_ifmedia, 1690 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1691 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1692 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 1693 } else { 1694 /* 1695 * Do transceiver setup. 1696 */ 1697 if (mii_phy_probe(dev, &sc->bge_miibus, 1698 bge_ifmedia_upd, bge_ifmedia_sts)) { 1699 printf("bge%d: MII without any PHY!\n", sc->bge_unit); 1700 bge_release_resources(sc); 1701 bge_free_jumbo_mem(sc); 1702 error = ENXIO; 1703 goto fail; 1704 } 1705 } 1706 1707 /* 1708 * When using the BCM5701 in PCI-X mode, data corruption has 1709 * been observed in the first few bytes of some received packets. 1710 * Aligning the packet buffer in memory eliminates the corruption. 1711 * Unfortunately, this misaligns the packet payloads. On platforms 1712 * which do not support unaligned accesses, we will realign the 1713 * payloads by copying the received packets. 1714 */ 1715 switch (sc->bge_chipid) { 1716 case BGE_CHIPID_BCM5701_A0: 1717 case BGE_CHIPID_BCM5701_B0: 1718 case BGE_CHIPID_BCM5701_B2: 1719 case BGE_CHIPID_BCM5701_B5: 1720 /* If in PCI-X mode, work around the alignment bug. */ 1721 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 1722 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 1723 BGE_PCISTATE_PCI_BUSSPEED) 1724 sc->bge_rx_alignment_bug = 1; 1725 break; 1726 } 1727 1728 /* 1729 * Call MI attach routine. 1730 */ 1731 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1732 callout_handle_init(&sc->bge_stat_ch); 1733 1734 fail: 1735 splx(s); 1736 1737 return(error); 1738 } 1739 1740 static int 1741 bge_detach(dev) 1742 device_t dev; 1743 { 1744 struct bge_softc *sc; 1745 struct ifnet *ifp; 1746 int s; 1747 1748 s = splimp(); 1749 1750 sc = device_get_softc(dev); 1751 ifp = &sc->arpcom.ac_if; 1752 1753 ether_ifdetach(ifp); 1754 bge_stop(sc); 1755 bge_reset(sc); 1756 1757 if (sc->bge_tbi) { 1758 ifmedia_removeall(&sc->bge_ifmedia); 1759 } else { 1760 bus_generic_detach(dev); 1761 device_delete_child(dev, sc->bge_miibus); 1762 } 1763 1764 bge_release_resources(sc); 1765 bge_free_jumbo_mem(sc); 1766 1767 splx(s); 1768 1769 return(0); 1770 } 1771 1772 static void 1773 bge_release_resources(sc) 1774 struct bge_softc *sc; 1775 { 1776 device_t dev; 1777 1778 dev = sc->bge_dev; 1779 1780 if (sc->bge_vpd_prodname != NULL) 1781 free(sc->bge_vpd_prodname, M_DEVBUF); 1782 1783 if (sc->bge_vpd_readonly != NULL) 1784 free(sc->bge_vpd_readonly, M_DEVBUF); 1785 1786 if (sc->bge_intrhand != NULL) 1787 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 1788 1789 if (sc->bge_irq != NULL) 1790 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 1791 1792 if (sc->bge_res != NULL) 1793 bus_release_resource(dev, SYS_RES_MEMORY, 1794 BGE_PCI_BAR0, sc->bge_res); 1795 1796 if (sc->bge_rdata != NULL) 1797 contigfree(sc->bge_rdata, 1798 sizeof(struct bge_ring_data), M_DEVBUF); 1799 1800 return; 1801 } 1802 1803 static void 1804 bge_reset(sc) 1805 struct bge_softc *sc; 1806 { 1807 device_t dev; 1808 u_int32_t cachesize, command, pcistate; 1809 int i, val = 0; 1810 1811 dev = sc->bge_dev; 1812 1813 /* Save some important PCI state. */ 1814 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 1815 command = pci_read_config(dev, BGE_PCI_CMD, 4); 1816 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 1817 1818 pci_write_config(dev, BGE_PCI_MISC_CTL, 1819 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1820 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1821 1822 /* Issue global reset */ 1823 bge_writereg_ind(sc, BGE_MISC_CFG, 1824 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 1825 1826 DELAY(1000); 1827 1828 /* Reset some of the PCI state that got zapped by reset */ 1829 pci_write_config(dev, BGE_PCI_MISC_CTL, 1830 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1831 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1832 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 1833 pci_write_config(dev, BGE_PCI_CMD, command, 4); 1834 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1835 1836 /* 1837 * Prevent PXE restart: write a magic number to the 1838 * general communications memory at 0xB50. 1839 */ 1840 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1841 /* 1842 * Poll the value location we just wrote until 1843 * we see the 1's complement of the magic number. 1844 * This indicates that the firmware initialization 1845 * is complete. 1846 */ 1847 for (i = 0; i < BGE_TIMEOUT; i++) { 1848 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1849 if (val == ~BGE_MAGIC_NUMBER) 1850 break; 1851 DELAY(10); 1852 } 1853 1854 if (i == BGE_TIMEOUT) { 1855 printf("bge%d: firmware handshake timed out\n", sc->bge_unit); 1856 return; 1857 } 1858 1859 /* 1860 * XXX Wait for the value of the PCISTATE register to 1861 * return to its original pre-reset state. This is a 1862 * fairly good indicator of reset completion. If we don't 1863 * wait for the reset to fully complete, trying to read 1864 * from the device's non-PCI registers may yield garbage 1865 * results. 1866 */ 1867 for (i = 0; i < BGE_TIMEOUT; i++) { 1868 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 1869 break; 1870 DELAY(10); 1871 } 1872 1873 /* Enable memory arbiter. */ 1874 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1875 1876 /* Fix up byte swapping */ 1877 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 1878 BGE_MODECTL_BYTESWAP_DATA); 1879 1880 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1881 1882 DELAY(10000); 1883 1884 return; 1885 } 1886 1887 /* 1888 * Frame reception handling. This is called if there's a frame 1889 * on the receive return list. 1890 * 1891 * Note: we have to be able to handle two possibilities here: 1892 * 1) the frame is from the jumbo recieve ring 1893 * 2) the frame is from the standard receive ring 1894 */ 1895 1896 static void 1897 bge_rxeof(sc) 1898 struct bge_softc *sc; 1899 { 1900 struct ifnet *ifp; 1901 int stdcnt = 0, jumbocnt = 0; 1902 1903 ifp = &sc->arpcom.ac_if; 1904 1905 while(sc->bge_rx_saved_considx != 1906 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 1907 struct bge_rx_bd *cur_rx; 1908 u_int32_t rxidx; 1909 struct ether_header *eh; 1910 struct mbuf *m = NULL; 1911 u_int16_t vlan_tag = 0; 1912 int have_tag = 0; 1913 1914 cur_rx = 1915 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx]; 1916 1917 rxidx = cur_rx->bge_idx; 1918 BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT); 1919 1920 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 1921 have_tag = 1; 1922 vlan_tag = cur_rx->bge_vlan_tag; 1923 } 1924 1925 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 1926 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1927 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 1928 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 1929 jumbocnt++; 1930 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1931 ifp->if_ierrors++; 1932 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1933 continue; 1934 } 1935 if (bge_newbuf_jumbo(sc, 1936 sc->bge_jumbo, NULL) == ENOBUFS) { 1937 ifp->if_ierrors++; 1938 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1939 continue; 1940 } 1941 } else { 1942 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1943 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 1944 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 1945 stdcnt++; 1946 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1947 ifp->if_ierrors++; 1948 bge_newbuf_std(sc, sc->bge_std, m); 1949 continue; 1950 } 1951 if (bge_newbuf_std(sc, sc->bge_std, 1952 NULL) == ENOBUFS) { 1953 ifp->if_ierrors++; 1954 bge_newbuf_std(sc, sc->bge_std, m); 1955 continue; 1956 } 1957 } 1958 1959 ifp->if_ipackets++; 1960 #ifndef __i386__ 1961 /* 1962 * The i386 allows unaligned accesses, but for other 1963 * platforms we must make sure the payload is aligned. 1964 */ 1965 if (sc->bge_rx_alignment_bug) { 1966 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 1967 cur_rx->bge_len); 1968 m->m_data += ETHER_ALIGN; 1969 } 1970 #endif 1971 eh = mtod(m, struct ether_header *); 1972 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 1973 m->m_pkthdr.rcvif = ifp; 1974 1975 #if 0 /* currently broken for some packets, possibly related to TCP options */ 1976 if (ifp->if_hwassist) { 1977 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1978 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 1979 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1980 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 1981 m->m_pkthdr.csum_data = 1982 cur_rx->bge_tcp_udp_csum; 1983 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1984 } 1985 } 1986 #endif 1987 1988 /* 1989 * If we received a packet with a vlan tag, 1990 * attach that information to the packet. 1991 */ 1992 if (have_tag) 1993 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue); 1994 1995 (*ifp->if_input)(ifp, m); 1996 } 1997 1998 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 1999 if (stdcnt) 2000 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2001 if (jumbocnt) 2002 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2003 2004 return; 2005 } 2006 2007 static void 2008 bge_txeof(sc) 2009 struct bge_softc *sc; 2010 { 2011 struct bge_tx_bd *cur_tx = NULL; 2012 struct ifnet *ifp; 2013 2014 ifp = &sc->arpcom.ac_if; 2015 2016 /* 2017 * Go through our tx ring and free mbufs for those 2018 * frames that have been sent. 2019 */ 2020 while (sc->bge_tx_saved_considx != 2021 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2022 u_int32_t idx = 0; 2023 2024 idx = sc->bge_tx_saved_considx; 2025 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2026 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2027 ifp->if_opackets++; 2028 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 2029 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 2030 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2031 } 2032 sc->bge_txcnt--; 2033 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2034 ifp->if_timer = 0; 2035 } 2036 2037 if (cur_tx != NULL) 2038 ifp->if_flags &= ~IFF_OACTIVE; 2039 2040 return; 2041 } 2042 2043 static void 2044 bge_intr(xsc) 2045 void *xsc; 2046 { 2047 struct bge_softc *sc; 2048 struct ifnet *ifp; 2049 u_int32_t statusword; 2050 2051 sc = xsc; 2052 ifp = &sc->arpcom.ac_if; 2053 statusword = 2054 atomic_readandclear_32(&sc->bge_rdata->bge_status_block.bge_status); 2055 2056 #ifdef notdef 2057 /* Avoid this for now -- checking this register is expensive. */ 2058 /* Make sure this is really our interrupt. */ 2059 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2060 return; 2061 #endif 2062 /* Ack interrupt and stop others from occuring. */ 2063 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2064 2065 /* 2066 * Process link state changes. 2067 * Grrr. The link status word in the status block does 2068 * not work correctly on the BCM5700 rev AX and BX chips, 2069 * according to all avaibable information. Hence, we have 2070 * to enable MII interrupts in order to properly obtain 2071 * async link changes. Unfortunately, this also means that 2072 * we have to read the MAC status register to detect link 2073 * changes, thereby adding an additional register access to 2074 * the interrupt handler. 2075 */ 2076 2077 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) { 2078 u_int32_t status; 2079 2080 status = CSR_READ_4(sc, BGE_MAC_STS); 2081 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2082 sc->bge_link = 0; 2083 untimeout(bge_tick, sc, sc->bge_stat_ch); 2084 bge_tick(sc); 2085 /* Clear the interrupt */ 2086 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2087 BGE_EVTENB_MI_INTERRUPT); 2088 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 2089 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 2090 BRGPHY_INTRS); 2091 } 2092 } else { 2093 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) { 2094 sc->bge_link = 0; 2095 untimeout(bge_tick, sc, sc->bge_stat_ch); 2096 bge_tick(sc); 2097 /* Clear the interrupt */ 2098 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2099 BGE_MACSTAT_CFG_CHANGED); 2100 2101 /* Force flush the status block cached by PCI bridge */ 2102 CSR_READ_4(sc, BGE_MBX_IRQ0_LO); 2103 } 2104 } 2105 2106 if (ifp->if_flags & IFF_RUNNING) { 2107 /* Check RX return ring producer/consumer */ 2108 bge_rxeof(sc); 2109 2110 /* Check TX ring producer/consumer */ 2111 bge_txeof(sc); 2112 } 2113 2114 bge_handle_events(sc); 2115 2116 /* Re-enable interrupts. */ 2117 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2118 2119 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2120 bge_start(ifp); 2121 2122 return; 2123 } 2124 2125 static void 2126 bge_tick(xsc) 2127 void *xsc; 2128 { 2129 struct bge_softc *sc; 2130 struct mii_data *mii = NULL; 2131 struct ifmedia *ifm = NULL; 2132 struct ifnet *ifp; 2133 int s; 2134 2135 sc = xsc; 2136 ifp = &sc->arpcom.ac_if; 2137 2138 s = splimp(); 2139 2140 bge_stats_update(sc); 2141 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2142 if (sc->bge_link) { 2143 splx(s); 2144 return; 2145 } 2146 2147 if (sc->bge_tbi) { 2148 ifm = &sc->bge_ifmedia; 2149 if (CSR_READ_4(sc, BGE_MAC_STS) & 2150 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2151 sc->bge_link++; 2152 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2153 printf("bge%d: gigabit link up\n", sc->bge_unit); 2154 if (ifp->if_snd.ifq_head != NULL) 2155 bge_start(ifp); 2156 } 2157 splx(s); 2158 return; 2159 } 2160 2161 mii = device_get_softc(sc->bge_miibus); 2162 mii_tick(mii); 2163 2164 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2165 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2166 sc->bge_link++; 2167 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 2168 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2169 printf("bge%d: gigabit link up\n", 2170 sc->bge_unit); 2171 if (ifp->if_snd.ifq_head != NULL) 2172 bge_start(ifp); 2173 } 2174 2175 splx(s); 2176 2177 return; 2178 } 2179 2180 static void 2181 bge_stats_update(sc) 2182 struct bge_softc *sc; 2183 { 2184 struct ifnet *ifp; 2185 struct bge_stats *stats; 2186 2187 ifp = &sc->arpcom.ac_if; 2188 2189 stats = (struct bge_stats *)(sc->bge_vhandle + 2190 BGE_MEMWIN_START + BGE_STATS_BLOCK); 2191 2192 ifp->if_collisions += 2193 (stats->dot3StatsSingleCollisionFrames.bge_addr_lo + 2194 stats->dot3StatsMultipleCollisionFrames.bge_addr_lo + 2195 stats->dot3StatsExcessiveCollisions.bge_addr_lo + 2196 stats->dot3StatsLateCollisions.bge_addr_lo) - 2197 ifp->if_collisions; 2198 2199 #ifdef notdef 2200 ifp->if_collisions += 2201 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2202 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2203 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2204 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2205 ifp->if_collisions; 2206 #endif 2207 2208 return; 2209 } 2210 2211 /* 2212 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2213 * pointers to descriptors. 2214 */ 2215 static int 2216 bge_encap(sc, m_head, txidx) 2217 struct bge_softc *sc; 2218 struct mbuf *m_head; 2219 u_int32_t *txidx; 2220 { 2221 struct bge_tx_bd *f = NULL; 2222 struct mbuf *m; 2223 u_int32_t frag, cur, cnt = 0; 2224 u_int16_t csum_flags = 0; 2225 struct m_tag *mtag; 2226 2227 m = m_head; 2228 cur = frag = *txidx; 2229 2230 if (m_head->m_pkthdr.csum_flags) { 2231 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2232 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2233 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2234 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2235 if (m_head->m_flags & M_LASTFRAG) 2236 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 2237 else if (m_head->m_flags & M_FRAG) 2238 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 2239 } 2240 2241 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m); 2242 2243 /* 2244 * Start packing the mbufs in this chain into 2245 * the fragment pointers. Stop when we run out 2246 * of fragments or hit the end of the mbuf chain. 2247 */ 2248 for (m = m_head; m != NULL; m = m->m_next) { 2249 if (m->m_len != 0) { 2250 f = &sc->bge_rdata->bge_tx_ring[frag]; 2251 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2252 break; 2253 BGE_HOSTADDR(f->bge_addr, 2254 vtophys(mtod(m, vm_offset_t))); 2255 f->bge_len = m->m_len; 2256 f->bge_flags = csum_flags; 2257 if (mtag != NULL) { 2258 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2259 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 2260 } else { 2261 f->bge_vlan_tag = 0; 2262 } 2263 /* 2264 * Sanity check: avoid coming within 16 descriptors 2265 * of the end of the ring. 2266 */ 2267 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2268 return(ENOBUFS); 2269 cur = frag; 2270 BGE_INC(frag, BGE_TX_RING_CNT); 2271 cnt++; 2272 } 2273 } 2274 2275 if (m != NULL) 2276 return(ENOBUFS); 2277 2278 if (frag == sc->bge_tx_saved_considx) 2279 return(ENOBUFS); 2280 2281 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2282 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2283 sc->bge_txcnt += cnt; 2284 2285 *txidx = frag; 2286 2287 return(0); 2288 } 2289 2290 /* 2291 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2292 * to the mbuf data regions directly in the transmit descriptors. 2293 */ 2294 static void 2295 bge_start(ifp) 2296 struct ifnet *ifp; 2297 { 2298 struct bge_softc *sc; 2299 struct mbuf *m_head = NULL; 2300 u_int32_t prodidx = 0; 2301 2302 sc = ifp->if_softc; 2303 2304 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 2305 return; 2306 2307 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2308 2309 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2310 IF_DEQUEUE(&ifp->if_snd, m_head); 2311 if (m_head == NULL) 2312 break; 2313 2314 /* 2315 * XXX 2316 * safety overkill. If this is a fragmented packet chain 2317 * with delayed TCP/UDP checksums, then only encapsulate 2318 * it if we have enough descriptors to handle the entire 2319 * chain at once. 2320 * (paranoia -- may not actually be needed) 2321 */ 2322 if (m_head->m_flags & M_FIRSTFRAG && 2323 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2324 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2325 m_head->m_pkthdr.csum_data + 16) { 2326 IF_PREPEND(&ifp->if_snd, m_head); 2327 ifp->if_flags |= IFF_OACTIVE; 2328 break; 2329 } 2330 } 2331 2332 /* 2333 * Pack the data into the transmit ring. If we 2334 * don't have room, set the OACTIVE flag and wait 2335 * for the NIC to drain the ring. 2336 */ 2337 if (bge_encap(sc, m_head, &prodidx)) { 2338 IF_PREPEND(&ifp->if_snd, m_head); 2339 ifp->if_flags |= IFF_OACTIVE; 2340 break; 2341 } 2342 2343 /* 2344 * If there's a BPF listener, bounce a copy of this frame 2345 * to him. 2346 */ 2347 BPF_MTAP(ifp, m_head); 2348 } 2349 2350 /* Transmit */ 2351 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2352 /* 5700 b2 errata */ 2353 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 2354 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2355 2356 /* 2357 * Set a timeout in case the chip goes out to lunch. 2358 */ 2359 ifp->if_timer = 5; 2360 2361 return; 2362 } 2363 2364 static void 2365 bge_init(xsc) 2366 void *xsc; 2367 { 2368 struct bge_softc *sc = xsc; 2369 struct ifnet *ifp; 2370 u_int16_t *m; 2371 int s; 2372 2373 s = splimp(); 2374 2375 ifp = &sc->arpcom.ac_if; 2376 2377 if (ifp->if_flags & IFF_RUNNING) { 2378 splx(s); 2379 return; 2380 } 2381 2382 /* Cancel pending I/O and flush buffers. */ 2383 bge_stop(sc); 2384 bge_reset(sc); 2385 bge_chipinit(sc); 2386 2387 /* 2388 * Init the various state machines, ring 2389 * control blocks and firmware. 2390 */ 2391 if (bge_blockinit(sc)) { 2392 printf("bge%d: initialization failure\n", sc->bge_unit); 2393 splx(s); 2394 return; 2395 } 2396 2397 ifp = &sc->arpcom.ac_if; 2398 2399 /* Specify MTU. */ 2400 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2401 ETHER_HDR_LEN + ETHER_CRC_LEN); 2402 2403 /* Load our MAC address. */ 2404 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2405 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2406 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2407 2408 /* Enable or disable promiscuous mode as needed. */ 2409 if (ifp->if_flags & IFF_PROMISC) { 2410 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2411 } else { 2412 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2413 } 2414 2415 /* Program multicast filter. */ 2416 bge_setmulti(sc); 2417 2418 /* Init RX ring. */ 2419 bge_init_rx_ring_std(sc); 2420 2421 /* Init jumbo RX ring. */ 2422 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2423 bge_init_rx_ring_jumbo(sc); 2424 2425 /* Init our RX return ring index */ 2426 sc->bge_rx_saved_considx = 0; 2427 2428 /* Init TX ring. */ 2429 bge_init_tx_ring(sc); 2430 2431 /* Turn on transmitter */ 2432 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2433 2434 /* Turn on receiver */ 2435 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2436 2437 /* Tell firmware we're alive. */ 2438 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2439 2440 /* Enable host interrupts. */ 2441 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2442 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2443 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2444 2445 bge_ifmedia_upd(ifp); 2446 2447 ifp->if_flags |= IFF_RUNNING; 2448 ifp->if_flags &= ~IFF_OACTIVE; 2449 2450 splx(s); 2451 2452 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2453 2454 return; 2455 } 2456 2457 /* 2458 * Set media options. 2459 */ 2460 static int 2461 bge_ifmedia_upd(ifp) 2462 struct ifnet *ifp; 2463 { 2464 struct bge_softc *sc; 2465 struct mii_data *mii; 2466 struct ifmedia *ifm; 2467 2468 sc = ifp->if_softc; 2469 ifm = &sc->bge_ifmedia; 2470 2471 /* If this is a 1000baseX NIC, enable the TBI port. */ 2472 if (sc->bge_tbi) { 2473 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2474 return(EINVAL); 2475 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2476 case IFM_AUTO: 2477 break; 2478 case IFM_1000_SX: 2479 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2480 BGE_CLRBIT(sc, BGE_MAC_MODE, 2481 BGE_MACMODE_HALF_DUPLEX); 2482 } else { 2483 BGE_SETBIT(sc, BGE_MAC_MODE, 2484 BGE_MACMODE_HALF_DUPLEX); 2485 } 2486 break; 2487 default: 2488 return(EINVAL); 2489 } 2490 return(0); 2491 } 2492 2493 mii = device_get_softc(sc->bge_miibus); 2494 sc->bge_link = 0; 2495 if (mii->mii_instance) { 2496 struct mii_softc *miisc; 2497 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2498 miisc = LIST_NEXT(miisc, mii_list)) 2499 mii_phy_reset(miisc); 2500 } 2501 mii_mediachg(mii); 2502 2503 return(0); 2504 } 2505 2506 /* 2507 * Report current media status. 2508 */ 2509 static void 2510 bge_ifmedia_sts(ifp, ifmr) 2511 struct ifnet *ifp; 2512 struct ifmediareq *ifmr; 2513 { 2514 struct bge_softc *sc; 2515 struct mii_data *mii; 2516 2517 sc = ifp->if_softc; 2518 2519 if (sc->bge_tbi) { 2520 ifmr->ifm_status = IFM_AVALID; 2521 ifmr->ifm_active = IFM_ETHER; 2522 if (CSR_READ_4(sc, BGE_MAC_STS) & 2523 BGE_MACSTAT_TBI_PCS_SYNCHED) 2524 ifmr->ifm_status |= IFM_ACTIVE; 2525 ifmr->ifm_active |= IFM_1000_SX; 2526 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2527 ifmr->ifm_active |= IFM_HDX; 2528 else 2529 ifmr->ifm_active |= IFM_FDX; 2530 return; 2531 } 2532 2533 mii = device_get_softc(sc->bge_miibus); 2534 mii_pollstat(mii); 2535 ifmr->ifm_active = mii->mii_media_active; 2536 ifmr->ifm_status = mii->mii_media_status; 2537 2538 return; 2539 } 2540 2541 static int 2542 bge_ioctl(ifp, command, data) 2543 struct ifnet *ifp; 2544 u_long command; 2545 caddr_t data; 2546 { 2547 struct bge_softc *sc = ifp->if_softc; 2548 struct ifreq *ifr = (struct ifreq *) data; 2549 int s, mask, error = 0; 2550 struct mii_data *mii; 2551 2552 s = splimp(); 2553 2554 switch(command) { 2555 case SIOCSIFMTU: 2556 if (ifr->ifr_mtu > BGE_JUMBO_MTU) 2557 error = EINVAL; 2558 else { 2559 ifp->if_mtu = ifr->ifr_mtu; 2560 ifp->if_flags &= ~IFF_RUNNING; 2561 bge_init(sc); 2562 } 2563 break; 2564 case SIOCSIFFLAGS: 2565 if (ifp->if_flags & IFF_UP) { 2566 /* 2567 * If only the state of the PROMISC flag changed, 2568 * then just use the 'set promisc mode' command 2569 * instead of reinitializing the entire NIC. Doing 2570 * a full re-init means reloading the firmware and 2571 * waiting for it to start up, which may take a 2572 * second or two. 2573 */ 2574 if (ifp->if_flags & IFF_RUNNING && 2575 ifp->if_flags & IFF_PROMISC && 2576 !(sc->bge_if_flags & IFF_PROMISC)) { 2577 BGE_SETBIT(sc, BGE_RX_MODE, 2578 BGE_RXMODE_RX_PROMISC); 2579 } else if (ifp->if_flags & IFF_RUNNING && 2580 !(ifp->if_flags & IFF_PROMISC) && 2581 sc->bge_if_flags & IFF_PROMISC) { 2582 BGE_CLRBIT(sc, BGE_RX_MODE, 2583 BGE_RXMODE_RX_PROMISC); 2584 } else 2585 bge_init(sc); 2586 } else { 2587 if (ifp->if_flags & IFF_RUNNING) { 2588 bge_stop(sc); 2589 } 2590 } 2591 sc->bge_if_flags = ifp->if_flags; 2592 error = 0; 2593 break; 2594 case SIOCADDMULTI: 2595 case SIOCDELMULTI: 2596 if (ifp->if_flags & IFF_RUNNING) { 2597 bge_setmulti(sc); 2598 error = 0; 2599 } 2600 break; 2601 case SIOCSIFMEDIA: 2602 case SIOCGIFMEDIA: 2603 if (sc->bge_tbi) { 2604 error = ifmedia_ioctl(ifp, ifr, 2605 &sc->bge_ifmedia, command); 2606 } else { 2607 mii = device_get_softc(sc->bge_miibus); 2608 error = ifmedia_ioctl(ifp, ifr, 2609 &mii->mii_media, command); 2610 } 2611 break; 2612 case SIOCSIFCAP: 2613 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2614 if (mask & IFCAP_HWCSUM) { 2615 if (IFCAP_HWCSUM & ifp->if_capenable) 2616 ifp->if_capenable &= ~IFCAP_HWCSUM; 2617 else 2618 ifp->if_capenable |= IFCAP_HWCSUM; 2619 } 2620 error = 0; 2621 break; 2622 default: 2623 error = ether_ioctl(ifp, command, data); 2624 break; 2625 } 2626 2627 (void)splx(s); 2628 2629 return(error); 2630 } 2631 2632 static void 2633 bge_watchdog(ifp) 2634 struct ifnet *ifp; 2635 { 2636 struct bge_softc *sc; 2637 2638 sc = ifp->if_softc; 2639 2640 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit); 2641 2642 ifp->if_flags &= ~IFF_RUNNING; 2643 bge_init(sc); 2644 2645 ifp->if_oerrors++; 2646 2647 return; 2648 } 2649 2650 /* 2651 * Stop the adapter and free any mbufs allocated to the 2652 * RX and TX lists. 2653 */ 2654 static void 2655 bge_stop(sc) 2656 struct bge_softc *sc; 2657 { 2658 struct ifnet *ifp; 2659 struct ifmedia_entry *ifm; 2660 struct mii_data *mii = NULL; 2661 int mtmp, itmp; 2662 2663 ifp = &sc->arpcom.ac_if; 2664 2665 if (!sc->bge_tbi) 2666 mii = device_get_softc(sc->bge_miibus); 2667 2668 untimeout(bge_tick, sc, sc->bge_stat_ch); 2669 2670 /* 2671 * Disable all of the receiver blocks 2672 */ 2673 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2674 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2675 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2676 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2677 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2678 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2679 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2680 2681 /* 2682 * Disable all of the transmit blocks 2683 */ 2684 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2685 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2686 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2687 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2688 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2689 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2690 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2691 2692 /* 2693 * Shut down all of the memory managers and related 2694 * state machines. 2695 */ 2696 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2697 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2698 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2699 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2700 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2701 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2702 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2703 2704 /* Disable host interrupts. */ 2705 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2706 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2707 2708 /* 2709 * Tell firmware we're shutting down. 2710 */ 2711 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2712 2713 /* Free the RX lists. */ 2714 bge_free_rx_ring_std(sc); 2715 2716 /* Free jumbo RX list. */ 2717 bge_free_rx_ring_jumbo(sc); 2718 2719 /* Free TX buffers. */ 2720 bge_free_tx_ring(sc); 2721 2722 /* 2723 * Isolate/power down the PHY, but leave the media selection 2724 * unchanged so that things will be put back to normal when 2725 * we bring the interface back up. 2726 */ 2727 if (!sc->bge_tbi) { 2728 itmp = ifp->if_flags; 2729 ifp->if_flags |= IFF_UP; 2730 ifm = mii->mii_media.ifm_cur; 2731 mtmp = ifm->ifm_media; 2732 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2733 mii_mediachg(mii); 2734 ifm->ifm_media = mtmp; 2735 ifp->if_flags = itmp; 2736 } 2737 2738 sc->bge_link = 0; 2739 2740 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2741 2742 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2743 2744 return; 2745 } 2746 2747 /* 2748 * Stop all chip I/O so that the kernel's probe routines don't 2749 * get confused by errant DMAs when rebooting. 2750 */ 2751 static void 2752 bge_shutdown(dev) 2753 device_t dev; 2754 { 2755 struct bge_softc *sc; 2756 2757 sc = device_get_softc(dev); 2758 2759 bge_stop(sc); 2760 bge_reset(sc); 2761 2762 return; 2763 }
Cache object: dc0f9ec486bc7914add3c2a8d1b9400b
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]