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sys/dev/bge/if_bge.c
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1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD: releng/6.4/sys/dev/bge/if_bge.c 183162 2008-09-18 22:29:05Z oleg $"); 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #ifdef HAVE_KERNEL_OPTION_HEADERS 70 #include "opt_device_polling.h" 71 #endif 72 73 #include <sys/param.h> 74 #include <sys/endian.h> 75 #include <sys/systm.h> 76 #include <sys/sockio.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/module.h> 81 #include <sys/socket.h> 82 #include <sys/sysctl.h> 83 84 #include <net/if.h> 85 #include <net/if_arp.h> 86 #include <net/ethernet.h> 87 #include <net/if_dl.h> 88 #include <net/if_media.h> 89 90 #include <net/bpf.h> 91 92 #include <net/if_types.h> 93 #include <net/if_vlan_var.h> 94 95 #include <netinet/in_systm.h> 96 #include <netinet/in.h> 97 #include <netinet/ip.h> 98 99 #include <machine/bus.h> 100 #include <machine/resource.h> 101 #include <sys/bus.h> 102 #include <sys/rman.h> 103 104 #include <dev/mii/mii.h> 105 #include <dev/mii/miivar.h> 106 #include "miidevs.h" 107 #include <dev/mii/brgphyreg.h> 108 109 #ifdef __sparc64__ 110 #include <dev/ofw/ofw_bus.h> 111 #include <dev/ofw/openfirm.h> 112 #include <machine/ofw_machdep.h> 113 #include <machine/ver.h> 114 #endif 115 116 #include <dev/pci/pcireg.h> 117 #include <dev/pci/pcivar.h> 118 119 #include <dev/bge/if_bgereg.h> 120 121 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 122 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 123 124 MODULE_DEPEND(bge, pci, 1, 1, 1); 125 MODULE_DEPEND(bge, ether, 1, 1, 1); 126 MODULE_DEPEND(bge, miibus, 1, 1, 1); 127 128 /* "device miibus" required. See GENERIC if you get errors here. */ 129 #include "miibus_if.h" 130 131 /* 132 * Various supported device vendors/types and their names. Note: the 133 * spec seems to indicate that the hardware still has Alteon's vendor 134 * ID burned into it, though it will always be overriden by the vendor 135 * ID in the EEPROM. Just to be safe, we cover all possibilities. 136 */ 137 static struct bge_type { 138 uint16_t bge_vid; 139 uint16_t bge_did; 140 } bge_devs[] = { 141 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 142 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 143 144 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 145 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 147 148 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 149 150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 151 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 201 202 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 203 204 { TC_VENDORID, TC_DEVICEID_3C996 }, 205 206 { 0, 0 } 207 }; 208 209 static const struct bge_vendor { 210 uint16_t v_id; 211 const char *v_name; 212 } bge_vendors[] = { 213 { ALTEON_VENDORID, "Alteon" }, 214 { ALTIMA_VENDORID, "Altima" }, 215 { APPLE_VENDORID, "Apple" }, 216 { BCOM_VENDORID, "Broadcom" }, 217 { SK_VENDORID, "SysKonnect" }, 218 { TC_VENDORID, "3Com" }, 219 220 { 0, NULL } 221 }; 222 223 static const struct bge_revision { 224 uint32_t br_chipid; 225 const char *br_name; 226 } bge_revisions[] = { 227 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 228 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 229 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 230 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 231 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 232 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 233 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 234 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 235 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 236 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 237 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 238 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 239 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 240 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 241 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 242 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 243 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 244 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 245 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 246 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 247 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 248 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 249 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 250 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 251 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 252 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 253 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 254 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 255 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 256 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 257 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 258 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 259 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 260 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 261 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 262 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 263 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 264 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 265 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 266 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 267 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 268 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 269 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 270 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 271 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 272 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 273 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 274 /* 5754 and 5787 share the same ASIC ID */ 275 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 276 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 277 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 278 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 279 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 280 281 { 0, NULL } 282 }; 283 284 /* 285 * Some defaults for major revisions, so that newer steppings 286 * that we don't know about have a shot at working. 287 */ 288 static const struct bge_revision bge_majorrevs[] = { 289 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 290 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 291 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 292 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 293 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 294 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 295 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 296 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 297 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 298 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 299 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 300 /* 5754 and 5787 share the same ASIC ID */ 301 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 302 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 303 304 { 0, NULL } 305 }; 306 307 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 308 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 309 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 310 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 311 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 312 313 const struct bge_revision * bge_lookup_rev(uint32_t); 314 const struct bge_vendor * bge_lookup_vendor(uint16_t); 315 316 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 317 318 static int bge_probe(device_t); 319 static int bge_attach(device_t); 320 static int bge_detach(device_t); 321 static int bge_suspend(device_t); 322 static int bge_resume(device_t); 323 static void bge_release_resources(struct bge_softc *); 324 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 325 static int bge_dma_alloc(device_t); 326 static void bge_dma_free(struct bge_softc *); 327 328 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 329 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 330 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 331 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 332 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 333 334 static void bge_txeof(struct bge_softc *); 335 static void bge_rxeof(struct bge_softc *); 336 337 static void bge_asf_driver_up (struct bge_softc *); 338 static void bge_tick(void *); 339 static void bge_stats_update(struct bge_softc *); 340 static void bge_stats_update_regs(struct bge_softc *); 341 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 342 343 static void bge_intr(void *); 344 static void bge_start_locked(struct ifnet *); 345 static void bge_start(struct ifnet *); 346 static int bge_ioctl(struct ifnet *, u_long, caddr_t); 347 static void bge_init_locked(struct bge_softc *); 348 static void bge_init(void *); 349 static void bge_stop(struct bge_softc *); 350 static void bge_watchdog(struct bge_softc *); 351 static void bge_shutdown(device_t); 352 static int bge_ifmedia_upd_locked(struct ifnet *); 353 static int bge_ifmedia_upd(struct ifnet *); 354 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 355 356 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 357 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 358 359 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 360 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 361 362 static void bge_setpromisc(struct bge_softc *); 363 static void bge_setmulti(struct bge_softc *); 364 365 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *); 366 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 367 static int bge_init_rx_ring_std(struct bge_softc *); 368 static void bge_free_rx_ring_std(struct bge_softc *); 369 static int bge_init_rx_ring_jumbo(struct bge_softc *); 370 static void bge_free_rx_ring_jumbo(struct bge_softc *); 371 static void bge_free_tx_ring(struct bge_softc *); 372 static int bge_init_tx_ring(struct bge_softc *); 373 374 static int bge_chipinit(struct bge_softc *); 375 static int bge_blockinit(struct bge_softc *); 376 377 static int bge_has_eaddr(struct bge_softc *); 378 static uint32_t bge_readmem_ind(struct bge_softc *, int); 379 static void bge_writemem_ind(struct bge_softc *, int, int); 380 static void bge_writembx(struct bge_softc *, int, int); 381 #ifdef notdef 382 static uint32_t bge_readreg_ind(struct bge_softc *, int); 383 #endif 384 static void bge_writemem_direct(struct bge_softc *, int, int); 385 static void bge_writereg_ind(struct bge_softc *, int, int); 386 387 static int bge_miibus_readreg(device_t, int, int); 388 static int bge_miibus_writereg(device_t, int, int, int); 389 static void bge_miibus_statchg(device_t); 390 #ifdef DEVICE_POLLING 391 static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 392 #endif 393 394 #define BGE_RESET_START 1 395 #define BGE_RESET_STOP 2 396 static void bge_sig_post_reset(struct bge_softc *, int); 397 static void bge_sig_legacy(struct bge_softc *, int); 398 static void bge_sig_pre_reset(struct bge_softc *, int); 399 static int bge_reset(struct bge_softc *); 400 static void bge_link_upd(struct bge_softc *); 401 402 /* 403 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 404 * leak information to untrusted users. It is also known to cause alignment 405 * traps on certain architectures. 406 */ 407 #ifdef BGE_REGISTER_DEBUG 408 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 409 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 410 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 411 #endif 412 static void bge_add_sysctls(struct bge_softc *); 413 414 static device_method_t bge_methods[] = { 415 /* Device interface */ 416 DEVMETHOD(device_probe, bge_probe), 417 DEVMETHOD(device_attach, bge_attach), 418 DEVMETHOD(device_detach, bge_detach), 419 DEVMETHOD(device_shutdown, bge_shutdown), 420 DEVMETHOD(device_suspend, bge_suspend), 421 DEVMETHOD(device_resume, bge_resume), 422 423 /* bus interface */ 424 DEVMETHOD(bus_print_child, bus_generic_print_child), 425 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 426 427 /* MII interface */ 428 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 429 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 430 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 431 432 { 0, 0 } 433 }; 434 435 static driver_t bge_driver = { 436 "bge", 437 bge_methods, 438 sizeof(struct bge_softc) 439 }; 440 441 static devclass_t bge_devclass; 442 443 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 444 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 445 446 static int bge_allow_asf = 0; 447 448 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 449 450 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 451 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, 452 "Allow ASF mode if available"); 453 454 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 455 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 456 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 457 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 458 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 459 460 static int 461 bge_has_eaddr(struct bge_softc *sc) 462 { 463 #ifdef __sparc64__ 464 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 465 device_t dev; 466 uint32_t subvendor; 467 468 dev = sc->bge_dev; 469 470 /* 471 * The on-board BGEs found in sun4u machines aren't fitted with 472 * an EEPROM which means that we have to obtain the MAC address 473 * via OFW and that some tests will always fail. We distinguish 474 * such BGEs by the subvendor ID, which also has to be obtained 475 * from OFW instead of the PCI configuration space as the latter 476 * indicates Broadcom as the subvendor of the netboot interface. 477 * For early Blade 1500 and 2500 we even have to check the OFW 478 * device path as the subvendor ID always defaults to Broadcom 479 * there. 480 */ 481 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 482 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 483 subvendor == SUN_VENDORID) 484 return (0); 485 memset(buf, 0, sizeof(buf)); 486 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 487 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 488 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 489 return (0); 490 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 491 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 492 return (0); 493 } 494 #endif 495 return (1); 496 } 497 498 static uint32_t 499 bge_readmem_ind(struct bge_softc *sc, int off) 500 { 501 device_t dev; 502 uint32_t val; 503 504 dev = sc->bge_dev; 505 506 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 507 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 508 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 509 return (val); 510 } 511 512 static void 513 bge_writemem_ind(struct bge_softc *sc, int off, int val) 514 { 515 device_t dev; 516 517 dev = sc->bge_dev; 518 519 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 520 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 521 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 522 } 523 524 #ifdef notdef 525 static uint32_t 526 bge_readreg_ind(struct bge_softc *sc, int off) 527 { 528 device_t dev; 529 530 dev = sc->bge_dev; 531 532 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 533 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 534 } 535 #endif 536 537 static void 538 bge_writereg_ind(struct bge_softc *sc, int off, int val) 539 { 540 device_t dev; 541 542 dev = sc->bge_dev; 543 544 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 545 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 546 } 547 548 static void 549 bge_writemem_direct(struct bge_softc *sc, int off, int val) 550 { 551 CSR_WRITE_4(sc, off, val); 552 } 553 554 static void 555 bge_writembx(struct bge_softc *sc, int off, int val) 556 { 557 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 558 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 559 560 CSR_WRITE_4(sc, off, val); 561 } 562 563 /* 564 * Map a single buffer address. 565 */ 566 567 static void 568 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 569 { 570 struct bge_dmamap_arg *ctx; 571 572 if (error) 573 return; 574 575 ctx = arg; 576 577 if (nseg > ctx->bge_maxsegs) { 578 ctx->bge_maxsegs = 0; 579 return; 580 } 581 582 ctx->bge_busaddr = segs->ds_addr; 583 } 584 585 static uint8_t 586 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 587 { 588 uint32_t access, byte = 0; 589 int i; 590 591 /* Lock. */ 592 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 593 for (i = 0; i < 8000; i++) { 594 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 595 break; 596 DELAY(20); 597 } 598 if (i == 8000) 599 return (1); 600 601 /* Enable access. */ 602 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 603 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 604 605 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 606 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 607 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 608 DELAY(10); 609 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 610 DELAY(10); 611 break; 612 } 613 } 614 615 if (i == BGE_TIMEOUT * 10) { 616 if_printf(sc->bge_ifp, "nvram read timed out\n"); 617 return (1); 618 } 619 620 /* Get result. */ 621 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 622 623 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 624 625 /* Disable access. */ 626 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 627 628 /* Unlock. */ 629 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 630 CSR_READ_4(sc, BGE_NVRAM_SWARB); 631 632 return (0); 633 } 634 635 /* 636 * Read a sequence of bytes from NVRAM. 637 */ 638 static int 639 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 640 { 641 int err = 0, i; 642 uint8_t byte = 0; 643 644 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 645 return (1); 646 647 for (i = 0; i < cnt; i++) { 648 err = bge_nvram_getbyte(sc, off + i, &byte); 649 if (err) 650 break; 651 *(dest + i) = byte; 652 } 653 654 return (err ? 1 : 0); 655 } 656 657 /* 658 * Read a byte of data stored in the EEPROM at address 'addr.' The 659 * BCM570x supports both the traditional bitbang interface and an 660 * auto access interface for reading the EEPROM. We use the auto 661 * access method. 662 */ 663 static uint8_t 664 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 665 { 666 int i; 667 uint32_t byte = 0; 668 669 /* 670 * Enable use of auto EEPROM access so we can avoid 671 * having to use the bitbang method. 672 */ 673 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 674 675 /* Reset the EEPROM, load the clock period. */ 676 CSR_WRITE_4(sc, BGE_EE_ADDR, 677 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 678 DELAY(20); 679 680 /* Issue the read EEPROM command. */ 681 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 682 683 /* Wait for completion */ 684 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 685 DELAY(10); 686 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 687 break; 688 } 689 690 if (i == BGE_TIMEOUT * 10) { 691 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 692 return (1); 693 } 694 695 /* Get result. */ 696 byte = CSR_READ_4(sc, BGE_EE_DATA); 697 698 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 699 700 return (0); 701 } 702 703 /* 704 * Read a sequence of bytes from the EEPROM. 705 */ 706 static int 707 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 708 { 709 int i, error = 0; 710 uint8_t byte = 0; 711 712 for (i = 0; i < cnt; i++) { 713 error = bge_eeprom_getbyte(sc, off + i, &byte); 714 if (error) 715 break; 716 *(dest + i) = byte; 717 } 718 719 return (error ? 1 : 0); 720 } 721 722 static int 723 bge_miibus_readreg(device_t dev, int phy, int reg) 724 { 725 struct bge_softc *sc; 726 uint32_t val, autopoll; 727 int i; 728 729 sc = device_get_softc(dev); 730 731 /* 732 * Broadcom's own driver always assumes the internal 733 * PHY is at GMII address 1. On some chips, the PHY responds 734 * to accesses at all addresses, which could cause us to 735 * bogusly attach the PHY 32 times at probe type. Always 736 * restricting the lookup to address 1 is simpler than 737 * trying to figure out which chips revisions should be 738 * special-cased. 739 */ 740 if (phy != 1) 741 return (0); 742 743 /* Reading with autopolling on may trigger PCI errors */ 744 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 745 if (autopoll & BGE_MIMODE_AUTOPOLL) { 746 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 747 DELAY(40); 748 } 749 750 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 751 BGE_MIPHY(phy) | BGE_MIREG(reg)); 752 753 for (i = 0; i < BGE_TIMEOUT; i++) { 754 DELAY(10); 755 val = CSR_READ_4(sc, BGE_MI_COMM); 756 if (!(val & BGE_MICOMM_BUSY)) 757 break; 758 } 759 760 if (i == BGE_TIMEOUT) { 761 device_printf(sc->bge_dev, 762 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 763 phy, reg, val); 764 val = 0; 765 goto done; 766 } 767 768 DELAY(5); 769 val = CSR_READ_4(sc, BGE_MI_COMM); 770 771 done: 772 if (autopoll & BGE_MIMODE_AUTOPOLL) { 773 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 774 DELAY(40); 775 } 776 777 if (val & BGE_MICOMM_READFAIL) 778 return (0); 779 780 return (val & 0xFFFF); 781 } 782 783 static int 784 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 785 { 786 struct bge_softc *sc; 787 uint32_t autopoll; 788 int i; 789 790 sc = device_get_softc(dev); 791 792 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 793 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 794 return(0); 795 796 /* Reading with autopolling on may trigger PCI errors */ 797 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 798 if (autopoll & BGE_MIMODE_AUTOPOLL) { 799 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 800 DELAY(40); 801 } 802 803 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 804 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 805 806 for (i = 0; i < BGE_TIMEOUT; i++) { 807 DELAY(10); 808 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 809 DELAY(5); 810 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 811 break; 812 } 813 } 814 815 if (i == BGE_TIMEOUT) { 816 device_printf(sc->bge_dev, 817 "PHY write timed out (phy %d, reg %d, val %d)\n", 818 phy, reg, val); 819 return (0); 820 } 821 822 if (autopoll & BGE_MIMODE_AUTOPOLL) { 823 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 824 DELAY(40); 825 } 826 827 828 return (0); 829 } 830 831 static void 832 bge_miibus_statchg(device_t dev) 833 { 834 struct bge_softc *sc; 835 struct mii_data *mii; 836 sc = device_get_softc(dev); 837 mii = device_get_softc(sc->bge_miibus); 838 839 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 840 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 841 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 842 else 843 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 844 845 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 846 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 847 else 848 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 849 } 850 851 /* 852 * Intialize a standard receive ring descriptor. 853 */ 854 static int 855 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m) 856 { 857 struct mbuf *m_new = NULL; 858 struct bge_rx_bd *r; 859 struct bge_dmamap_arg ctx; 860 int error; 861 862 if (m == NULL) { 863 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 864 if (m_new == NULL) 865 return (ENOBUFS); 866 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 867 } else { 868 m_new = m; 869 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 870 m_new->m_data = m_new->m_ext.ext_buf; 871 } 872 873 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 874 m_adj(m_new, ETHER_ALIGN); 875 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 876 r = &sc->bge_ldata.bge_rx_std_ring[i]; 877 ctx.bge_maxsegs = 1; 878 ctx.sc = sc; 879 error = bus_dmamap_load(sc->bge_cdata.bge_mtag, 880 sc->bge_cdata.bge_rx_std_dmamap[i], mtod(m_new, void *), 881 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 882 if (error || ctx.bge_maxsegs == 0) { 883 if (m == NULL) { 884 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 885 m_freem(m_new); 886 } 887 return (ENOMEM); 888 } 889 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_busaddr); 890 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_busaddr); 891 r->bge_flags = BGE_RXBDFLAG_END; 892 r->bge_len = m_new->m_len; 893 r->bge_idx = i; 894 895 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 896 sc->bge_cdata.bge_rx_std_dmamap[i], 897 BUS_DMASYNC_PREREAD); 898 899 return (0); 900 } 901 902 /* 903 * Initialize a jumbo receive ring descriptor. This allocates 904 * a jumbo buffer from the pool managed internally by the driver. 905 */ 906 static int 907 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 908 { 909 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 910 struct bge_extrx_bd *r; 911 struct mbuf *m_new = NULL; 912 int nsegs; 913 int error; 914 915 if (m == NULL) { 916 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 917 if (m_new == NULL) 918 return (ENOBUFS); 919 920 m_cljget(m_new, M_DONTWAIT, MJUM9BYTES); 921 if (!(m_new->m_flags & M_EXT)) { 922 m_freem(m_new); 923 return (ENOBUFS); 924 } 925 m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES; 926 } else { 927 m_new = m; 928 m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES; 929 m_new->m_data = m_new->m_ext.ext_buf; 930 } 931 932 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 933 m_adj(m_new, ETHER_ALIGN); 934 935 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 936 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 937 m_new, segs, &nsegs, BUS_DMA_NOWAIT); 938 if (error) { 939 if (m == NULL) 940 m_freem(m_new); 941 return (error); 942 } 943 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 944 945 /* 946 * Fill in the extended RX buffer descriptor. 947 */ 948 r = &sc->bge_ldata.bge_rx_jumbo_ring[i]; 949 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 950 r->bge_idx = i; 951 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 952 switch (nsegs) { 953 case 4: 954 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 955 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 956 r->bge_len3 = segs[3].ds_len; 957 case 3: 958 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 959 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 960 r->bge_len2 = segs[2].ds_len; 961 case 2: 962 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 963 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 964 r->bge_len1 = segs[1].ds_len; 965 case 1: 966 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 967 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 968 r->bge_len0 = segs[0].ds_len; 969 break; 970 default: 971 panic("%s: %d segments\n", __func__, nsegs); 972 } 973 974 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 975 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 976 BUS_DMASYNC_PREREAD); 977 978 return (0); 979 } 980 981 /* 982 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 983 * that's 1MB or memory, which is a lot. For now, we fill only the first 984 * 256 ring entries and hope that our CPU is fast enough to keep up with 985 * the NIC. 986 */ 987 static int 988 bge_init_rx_ring_std(struct bge_softc *sc) 989 { 990 int i; 991 992 for (i = 0; i < BGE_SSLOTS; i++) { 993 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 994 return (ENOBUFS); 995 }; 996 997 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 998 sc->bge_cdata.bge_rx_std_ring_map, 999 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1000 1001 sc->bge_std = i - 1; 1002 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1003 1004 return (0); 1005 } 1006 1007 static void 1008 bge_free_rx_ring_std(struct bge_softc *sc) 1009 { 1010 int i; 1011 1012 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1013 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1014 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 1015 sc->bge_cdata.bge_rx_std_dmamap[i], 1016 BUS_DMASYNC_POSTREAD); 1017 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 1018 sc->bge_cdata.bge_rx_std_dmamap[i]); 1019 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1020 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1021 } 1022 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1023 sizeof(struct bge_rx_bd)); 1024 } 1025 } 1026 1027 static int 1028 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1029 { 1030 struct bge_rcb *rcb; 1031 int i; 1032 1033 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1034 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1035 return (ENOBUFS); 1036 }; 1037 1038 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1039 sc->bge_cdata.bge_rx_jumbo_ring_map, 1040 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1041 1042 sc->bge_jumbo = i - 1; 1043 1044 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1045 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1046 BGE_RCB_FLAG_USE_EXT_RX_BD); 1047 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1048 1049 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1050 1051 return (0); 1052 } 1053 1054 static void 1055 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1056 { 1057 int i; 1058 1059 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1060 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1061 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1062 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1063 BUS_DMASYNC_POSTREAD); 1064 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1065 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1066 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1067 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1068 } 1069 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1070 sizeof(struct bge_extrx_bd)); 1071 } 1072 } 1073 1074 static void 1075 bge_free_tx_ring(struct bge_softc *sc) 1076 { 1077 int i; 1078 1079 if (sc->bge_ldata.bge_tx_ring == NULL) 1080 return; 1081 1082 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1083 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1084 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 1085 sc->bge_cdata.bge_tx_dmamap[i], 1086 BUS_DMASYNC_POSTWRITE); 1087 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 1088 sc->bge_cdata.bge_tx_dmamap[i]); 1089 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1090 sc->bge_cdata.bge_tx_chain[i] = NULL; 1091 } 1092 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1093 sizeof(struct bge_tx_bd)); 1094 } 1095 } 1096 1097 static int 1098 bge_init_tx_ring(struct bge_softc *sc) 1099 { 1100 sc->bge_txcnt = 0; 1101 sc->bge_tx_saved_considx = 0; 1102 1103 /* Initialize transmit producer index for host-memory send ring. */ 1104 sc->bge_tx_prodidx = 0; 1105 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1106 1107 /* 5700 b2 errata */ 1108 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1109 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1110 1111 /* NIC-memory send ring not used; initialize to zero. */ 1112 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1113 /* 5700 b2 errata */ 1114 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1115 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1116 1117 return (0); 1118 } 1119 1120 static void 1121 bge_setpromisc(struct bge_softc *sc) 1122 { 1123 struct ifnet *ifp; 1124 1125 BGE_LOCK_ASSERT(sc); 1126 1127 ifp = sc->bge_ifp; 1128 1129 /* Enable or disable promiscuous mode as needed. */ 1130 if (ifp->if_flags & IFF_PROMISC) 1131 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1132 else 1133 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1134 } 1135 1136 static void 1137 bge_setmulti(struct bge_softc *sc) 1138 { 1139 struct ifnet *ifp; 1140 struct ifmultiaddr *ifma; 1141 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1142 int h, i; 1143 1144 BGE_LOCK_ASSERT(sc); 1145 1146 ifp = sc->bge_ifp; 1147 1148 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1149 for (i = 0; i < 4; i++) 1150 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1151 return; 1152 } 1153 1154 /* First, zot all the existing filters. */ 1155 for (i = 0; i < 4; i++) 1156 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1157 1158 /* Now program new ones. */ 1159 IF_ADDR_LOCK(ifp); 1160 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1161 if (ifma->ifma_addr->sa_family != AF_LINK) 1162 continue; 1163 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1164 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 1165 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1166 } 1167 IF_ADDR_UNLOCK(ifp); 1168 1169 for (i = 0; i < 4; i++) 1170 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1171 } 1172 1173 static void 1174 bge_sig_pre_reset(sc, type) 1175 struct bge_softc *sc; 1176 int type; 1177 { 1178 /* 1179 * Some chips don't like this so only do this if ASF is enabled 1180 */ 1181 if (sc->bge_asf_mode) 1182 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1183 1184 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1185 switch (type) { 1186 case BGE_RESET_START: 1187 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1188 break; 1189 case BGE_RESET_STOP: 1190 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1191 break; 1192 } 1193 } 1194 } 1195 1196 static void 1197 bge_sig_post_reset(sc, type) 1198 struct bge_softc *sc; 1199 int type; 1200 { 1201 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1202 switch (type) { 1203 case BGE_RESET_START: 1204 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); 1205 /* START DONE */ 1206 break; 1207 case BGE_RESET_STOP: 1208 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); 1209 break; 1210 } 1211 } 1212 } 1213 1214 static void 1215 bge_sig_legacy(sc, type) 1216 struct bge_softc *sc; 1217 int type; 1218 { 1219 if (sc->bge_asf_mode) { 1220 switch (type) { 1221 case BGE_RESET_START: 1222 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1223 break; 1224 case BGE_RESET_STOP: 1225 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1226 break; 1227 } 1228 } 1229 } 1230 1231 void bge_stop_fw(struct bge_softc *); 1232 void 1233 bge_stop_fw(sc) 1234 struct bge_softc *sc; 1235 { 1236 int i; 1237 1238 if (sc->bge_asf_mode) { 1239 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); 1240 CSR_WRITE_4(sc, BGE_CPU_EVENT, 1241 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 1242 1243 for (i = 0; i < 100; i++ ) { 1244 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) 1245 break; 1246 DELAY(10); 1247 } 1248 } 1249 } 1250 1251 /* 1252 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1253 * self-test results. 1254 */ 1255 static int 1256 bge_chipinit(struct bge_softc *sc) 1257 { 1258 uint32_t dma_rw_ctl; 1259 int i; 1260 1261 /* Set endianness before we access any non-PCI registers. */ 1262 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4); 1263 1264 /* 1265 * Check the 'ROM failed' bit on the RX CPU to see if 1266 * self-tests passed. Skip this check when there's no 1267 * chip containing the Ethernet address fitted, since 1268 * in that case it will always fail. 1269 */ 1270 if ((sc->bge_flags & BGE_FLAG_EADDR) && 1271 CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1272 device_printf(sc->bge_dev, "RX CPU self-diagnostics failed!\n"); 1273 return (ENODEV); 1274 } 1275 1276 /* Clear the MAC control register */ 1277 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1278 1279 /* 1280 * Clear the MAC statistics block in the NIC's 1281 * internal memory. 1282 */ 1283 for (i = BGE_STATS_BLOCK; 1284 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1285 BGE_MEMWIN_WRITE(sc, i, 0); 1286 1287 for (i = BGE_STATUS_BLOCK; 1288 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1289 BGE_MEMWIN_WRITE(sc, i, 0); 1290 1291 /* Set up the PCI DMA control register. */ 1292 if (sc->bge_flags & BGE_FLAG_PCIE) { 1293 /* PCI Express bus */ 1294 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1295 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0xF) | 1296 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x2); 1297 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1298 /* PCI-X bus */ 1299 if (BGE_IS_5714_FAMILY(sc)) { 1300 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 1301 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */ 1302 /* XXX magic values, Broadcom-supplied Linux driver */ 1303 dma_rw_ctl |= (1 << 20) | (1 << 18); 1304 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) 1305 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1306 else 1307 dma_rw_ctl |= 1 << 15; 1308 1309 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1310 /* 1311 * The 5704 uses a different encoding of read/write 1312 * watermarks. 1313 */ 1314 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1315 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x7) | 1316 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x3); 1317 else 1318 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1319 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x3) | 1320 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x3) | 1321 0x0F; 1322 1323 /* 1324 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1325 * for hardware bugs. 1326 */ 1327 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1328 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1329 uint32_t tmp; 1330 1331 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1332 if (tmp == 0x6 || tmp == 0x7) 1333 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1334 } 1335 } else 1336 /* Conventional PCI bus */ 1337 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1338 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x7) | 1339 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x7) | 1340 0x0F; 1341 1342 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1343 sc->bge_asicrev == BGE_ASICREV_BCM5704 || 1344 sc->bge_asicrev == BGE_ASICREV_BCM5705) 1345 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1346 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1347 1348 /* 1349 * Set up general mode register. 1350 */ 1351 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1352 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1353 BGE_MODECTL_TX_NO_PHDR_CSUM); 1354 1355 /* 1356 * Tell the firmware the driver is running 1357 */ 1358 if (sc->bge_asf_mode & ASF_STACKUP) 1359 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 1360 1361 /* 1362 * Disable memory write invalidate. Apparently it is not supported 1363 * properly by these devices. 1364 */ 1365 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1366 1367 #ifdef __brokenalpha__ 1368 /* 1369 * Must insure that we do not cross an 8K (bytes) boundary 1370 * for DMA reads. Our highest limit is 1K bytes. This is a 1371 * restriction on some ALPHA platforms with early revision 1372 * 21174 PCI chipsets, such as the AlphaPC 164lx 1373 */ 1374 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1375 BGE_PCI_READ_BNDRY_1024BYTES, 4); 1376 #endif 1377 1378 /* Set the timer prescaler (always 66Mhz) */ 1379 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1380 1381 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1382 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1383 DELAY(40); /* XXX */ 1384 1385 /* Put PHY into ready state */ 1386 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1387 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1388 DELAY(40); 1389 } 1390 1391 return (0); 1392 } 1393 1394 static int 1395 bge_blockinit(struct bge_softc *sc) 1396 { 1397 struct bge_rcb *rcb; 1398 bus_size_t vrcb; 1399 bge_hostaddr taddr; 1400 uint32_t val; 1401 int i; 1402 1403 /* 1404 * Initialize the memory window pointer register so that 1405 * we can access the first 32K of internal NIC RAM. This will 1406 * allow us to set up the TX send ring RCBs and the RX return 1407 * ring RCBs, plus other things which live in NIC memory. 1408 */ 1409 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1410 1411 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1412 1413 if (!(BGE_IS_5705_PLUS(sc))) { 1414 /* Configure mbuf memory pool */ 1415 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1416 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1417 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1418 else 1419 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1420 1421 /* Configure DMA resource pool */ 1422 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1423 BGE_DMA_DESCRIPTORS); 1424 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1425 } 1426 1427 /* Configure mbuf pool watermarks */ 1428 if (!BGE_IS_5705_PLUS(sc)) { 1429 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1430 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1431 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1432 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1433 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1434 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1435 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1436 } else { 1437 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1438 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1439 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1440 } 1441 1442 /* Configure DMA resource watermarks */ 1443 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1444 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1445 1446 /* Enable buffer manager */ 1447 if (!(BGE_IS_5705_PLUS(sc))) { 1448 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1449 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 1450 1451 /* Poll for buffer manager start indication */ 1452 for (i = 0; i < BGE_TIMEOUT; i++) { 1453 DELAY(10); 1454 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1455 break; 1456 } 1457 1458 if (i == BGE_TIMEOUT) { 1459 device_printf(sc->bge_dev, 1460 "buffer manager failed to start\n"); 1461 return (ENXIO); 1462 } 1463 } 1464 1465 /* Enable flow-through queues */ 1466 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1467 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1468 1469 /* Wait until queue initialization is complete */ 1470 for (i = 0; i < BGE_TIMEOUT; i++) { 1471 DELAY(10); 1472 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1473 break; 1474 } 1475 1476 if (i == BGE_TIMEOUT) { 1477 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 1478 return (ENXIO); 1479 } 1480 1481 /* Initialize the standard RX ring control block */ 1482 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1483 rcb->bge_hostaddr.bge_addr_lo = 1484 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1485 rcb->bge_hostaddr.bge_addr_hi = 1486 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1487 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1488 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 1489 if (BGE_IS_5705_PLUS(sc)) 1490 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1491 else 1492 rcb->bge_maxlen_flags = 1493 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1494 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1495 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1496 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1497 1498 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1499 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1500 1501 /* 1502 * Initialize the jumbo RX ring control block 1503 * We set the 'ring disabled' bit in the flags 1504 * field until we're actually ready to start 1505 * using this ring (i.e. once we set the MTU 1506 * high enough to require it). 1507 */ 1508 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1509 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1510 1511 rcb->bge_hostaddr.bge_addr_lo = 1512 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1513 rcb->bge_hostaddr.bge_addr_hi = 1514 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1515 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1516 sc->bge_cdata.bge_rx_jumbo_ring_map, 1517 BUS_DMASYNC_PREREAD); 1518 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1519 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 1520 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1521 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1522 rcb->bge_hostaddr.bge_addr_hi); 1523 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1524 rcb->bge_hostaddr.bge_addr_lo); 1525 1526 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1527 rcb->bge_maxlen_flags); 1528 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1529 1530 /* Set up dummy disabled mini ring RCB */ 1531 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1532 rcb->bge_maxlen_flags = 1533 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1534 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1535 rcb->bge_maxlen_flags); 1536 } 1537 1538 /* 1539 * Set the BD ring replentish thresholds. The recommended 1540 * values are 1/8th the number of descriptors allocated to 1541 * each ring. 1542 * XXX The 5754 requires a lower threshold, so it might be a 1543 * requirement of all 575x family chips. The Linux driver sets 1544 * the lower threshold for all 5705 family chips as well, but there 1545 * are reports that it might not need to be so strict. 1546 * 1547 * XXX Linux does some extra fiddling here for the 5906 parts as 1548 * well. 1549 */ 1550 if (BGE_IS_5705_PLUS(sc)) 1551 val = 8; 1552 else 1553 val = BGE_STD_RX_RING_CNT / 8; 1554 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 1555 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1556 1557 /* 1558 * Disable all unused send rings by setting the 'ring disabled' 1559 * bit in the flags field of all the TX send ring control blocks. 1560 * These are located in NIC memory. 1561 */ 1562 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1563 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1564 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1565 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1566 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1567 vrcb += sizeof(struct bge_rcb); 1568 } 1569 1570 /* Configure TX RCB 0 (we use only the first ring) */ 1571 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1572 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 1573 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1574 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1575 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 1576 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1577 if (!(BGE_IS_5705_PLUS(sc))) 1578 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1579 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1580 1581 /* Disable all unused RX return rings */ 1582 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1583 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1584 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1585 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1586 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1587 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1588 BGE_RCB_FLAG_RING_DISABLED)); 1589 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1590 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1591 (i * (sizeof(uint64_t))), 0); 1592 vrcb += sizeof(struct bge_rcb); 1593 } 1594 1595 /* Initialize RX ring indexes */ 1596 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1597 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1598 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1599 1600 /* 1601 * Set up RX return ring 0 1602 * Note that the NIC address for RX return rings is 0x00000000. 1603 * The return rings live entirely within the host, so the 1604 * nicaddr field in the RCB isn't used. 1605 */ 1606 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1607 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 1608 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1609 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1610 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000); 1611 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1612 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1613 1614 /* Set random backoff seed for TX */ 1615 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1616 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 1617 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 1618 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] + 1619 BGE_TX_BACKOFF_SEED_MASK); 1620 1621 /* Set inter-packet gap */ 1622 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1623 1624 /* 1625 * Specify which ring to use for packets that don't match 1626 * any RX rules. 1627 */ 1628 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1629 1630 /* 1631 * Configure number of RX lists. One interrupt distribution 1632 * list, sixteen active lists, one bad frames class. 1633 */ 1634 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1635 1636 /* Inialize RX list placement stats mask. */ 1637 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1638 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1639 1640 /* Disable host coalescing until we get it set up */ 1641 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1642 1643 /* Poll to make sure it's shut down. */ 1644 for (i = 0; i < BGE_TIMEOUT; i++) { 1645 DELAY(10); 1646 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1647 break; 1648 } 1649 1650 if (i == BGE_TIMEOUT) { 1651 device_printf(sc->bge_dev, 1652 "host coalescing engine failed to idle\n"); 1653 return (ENXIO); 1654 } 1655 1656 /* Set up host coalescing defaults */ 1657 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1658 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1659 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1660 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1661 if (!(BGE_IS_5705_PLUS(sc))) { 1662 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1663 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1664 } 1665 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 1666 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 1667 1668 /* Set up address of statistics block */ 1669 if (!(BGE_IS_5705_PLUS(sc))) { 1670 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1671 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1672 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1673 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1674 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1675 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1676 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1677 } 1678 1679 /* Set up address of status block */ 1680 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1681 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1682 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1683 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1684 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0; 1685 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0; 1686 1687 /* Turn on host coalescing state machine */ 1688 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1689 1690 /* Turn on RX BD completion state machine and enable attentions */ 1691 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1692 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 1693 1694 /* Turn on RX list placement state machine */ 1695 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1696 1697 /* Turn on RX list selector state machine. */ 1698 if (!(BGE_IS_5705_PLUS(sc))) 1699 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1700 1701 /* Turn on DMA, clear stats */ 1702 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB | 1703 BGE_MACMODE_RXDMA_ENB | BGE_MACMODE_RX_STATS_CLEAR | 1704 BGE_MACMODE_TX_STATS_CLEAR | BGE_MACMODE_RX_STATS_ENB | 1705 BGE_MACMODE_TX_STATS_ENB | BGE_MACMODE_FRMHDR_DMA_ENB | 1706 ((sc->bge_flags & BGE_FLAG_TBI) ? 1707 BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1708 1709 /* Set misc. local control, enable interrupts on attentions */ 1710 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1711 1712 #ifdef notdef 1713 /* Assert GPIO pins for PHY reset */ 1714 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 1715 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 1716 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 1717 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 1718 #endif 1719 1720 /* Turn on DMA completion state machine */ 1721 if (!(BGE_IS_5705_PLUS(sc))) 1722 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1723 1724 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 1725 1726 /* Enable host coalescing bug fix. */ 1727 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 1728 sc->bge_asicrev == BGE_ASICREV_BCM5787) 1729 val |= 1 << 29; 1730 1731 /* Turn on write DMA state machine */ 1732 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 1733 1734 /* Turn on read DMA state machine */ 1735 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1736 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS); 1737 1738 /* Turn on RX data completion state machine */ 1739 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1740 1741 /* Turn on RX BD initiator state machine */ 1742 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1743 1744 /* Turn on RX data and RX BD initiator state machine */ 1745 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1746 1747 /* Turn on Mbuf cluster free state machine */ 1748 if (!(BGE_IS_5705_PLUS(sc))) 1749 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1750 1751 /* Turn on send BD completion state machine */ 1752 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1753 1754 /* Turn on send data completion state machine */ 1755 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1756 1757 /* Turn on send data initiator state machine */ 1758 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1759 1760 /* Turn on send BD initiator state machine */ 1761 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1762 1763 /* Turn on send BD selector state machine */ 1764 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1765 1766 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1767 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1768 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 1769 1770 /* ack/clear link change events */ 1771 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 1772 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 1773 BGE_MACSTAT_LINK_CHANGED); 1774 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1775 1776 /* Enable PHY auto polling (for MII/GMII only) */ 1777 if (sc->bge_flags & BGE_FLAG_TBI) { 1778 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1779 } else { 1780 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 1781 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1782 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 1783 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1784 BGE_EVTENB_MI_INTERRUPT); 1785 } 1786 1787 /* 1788 * Clear any pending link state attention. 1789 * Otherwise some link state change events may be lost until attention 1790 * is cleared by bge_intr() -> bge_link_upd() sequence. 1791 * It's not necessary on newer BCM chips - perhaps enabling link 1792 * state change attentions implies clearing pending attention. 1793 */ 1794 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 1795 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 1796 BGE_MACSTAT_LINK_CHANGED); 1797 1798 /* Enable link state change attentions. */ 1799 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1800 1801 return (0); 1802 } 1803 1804 const struct bge_revision * 1805 bge_lookup_rev(uint32_t chipid) 1806 { 1807 const struct bge_revision *br; 1808 1809 for (br = bge_revisions; br->br_name != NULL; br++) { 1810 if (br->br_chipid == chipid) 1811 return (br); 1812 } 1813 1814 for (br = bge_majorrevs; br->br_name != NULL; br++) { 1815 if (br->br_chipid == BGE_ASICREV(chipid)) 1816 return (br); 1817 } 1818 1819 return (NULL); 1820 } 1821 1822 const struct bge_vendor * 1823 bge_lookup_vendor(uint16_t vid) 1824 { 1825 const struct bge_vendor *v; 1826 1827 for (v = bge_vendors; v->v_name != NULL; v++) 1828 if (v->v_id == vid) 1829 return (v); 1830 1831 panic("%s: unknown vendor %d", __func__, vid); 1832 return (NULL); 1833 } 1834 1835 /* 1836 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1837 * against our list and return its name if we find a match. 1838 * 1839 * Note that since the Broadcom controller contains VPD support, we 1840 * try to get the device name string from the controller itself instead 1841 * of the compiled-in string. It guarantees we'll always announce the 1842 * right product name. We fall back to the compiled-in string when 1843 * VPD is unavailable or corrupt. 1844 */ 1845 static int 1846 bge_probe(device_t dev) 1847 { 1848 struct bge_type *t = bge_devs; 1849 struct bge_softc *sc = device_get_softc(dev); 1850 uint16_t vid, did; 1851 1852 sc->bge_dev = dev; 1853 vid = pci_get_vendor(dev); 1854 did = pci_get_device(dev); 1855 while(t->bge_vid != 0) { 1856 if ((vid == t->bge_vid) && (did == t->bge_did)) { 1857 char model[64], buf[96]; 1858 const struct bge_revision *br; 1859 const struct bge_vendor *v; 1860 uint32_t id; 1861 1862 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 1863 BGE_PCIMISCCTL_ASICREV; 1864 br = bge_lookup_rev(id); 1865 v = bge_lookup_vendor(vid); 1866 { 1867 #if __FreeBSD_version > 700024 1868 const char *pname; 1869 1870 if (pci_get_vpd_ident(dev, &pname) == 0) 1871 snprintf(model, 64, "%s", pname); 1872 else 1873 #endif 1874 snprintf(model, 64, "%s %s", 1875 v->v_name, 1876 br != NULL ? br->br_name : 1877 "NetXtreme Ethernet Controller"); 1878 } 1879 snprintf(buf, 96, "%s, %sASIC rev. %#04x", model, 1880 br != NULL ? "" : "unknown ", id >> 16); 1881 device_set_desc_copy(dev, buf); 1882 if (pci_get_subvendor(dev) == DELL_VENDORID) 1883 sc->bge_flags |= BGE_FLAG_NO_3LED; 1884 if (did == BCOM_DEVICEID_BCM5755M) 1885 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM; 1886 return (0); 1887 } 1888 t++; 1889 } 1890 1891 return (ENXIO); 1892 } 1893 1894 static void 1895 bge_dma_free(struct bge_softc *sc) 1896 { 1897 int i; 1898 1899 /* Destroy DMA maps for RX buffers. */ 1900 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1901 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 1902 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1903 sc->bge_cdata.bge_rx_std_dmamap[i]); 1904 } 1905 1906 /* Destroy DMA maps for jumbo RX buffers. */ 1907 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1908 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 1909 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 1910 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1911 } 1912 1913 /* Destroy DMA maps for TX buffers. */ 1914 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1915 if (sc->bge_cdata.bge_tx_dmamap[i]) 1916 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1917 sc->bge_cdata.bge_tx_dmamap[i]); 1918 } 1919 1920 if (sc->bge_cdata.bge_mtag) 1921 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag); 1922 1923 1924 /* Destroy standard RX ring. */ 1925 if (sc->bge_cdata.bge_rx_std_ring_map) 1926 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 1927 sc->bge_cdata.bge_rx_std_ring_map); 1928 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) 1929 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 1930 sc->bge_ldata.bge_rx_std_ring, 1931 sc->bge_cdata.bge_rx_std_ring_map); 1932 1933 if (sc->bge_cdata.bge_rx_std_ring_tag) 1934 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 1935 1936 /* Destroy jumbo RX ring. */ 1937 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 1938 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1939 sc->bge_cdata.bge_rx_jumbo_ring_map); 1940 1941 if (sc->bge_cdata.bge_rx_jumbo_ring_map && 1942 sc->bge_ldata.bge_rx_jumbo_ring) 1943 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1944 sc->bge_ldata.bge_rx_jumbo_ring, 1945 sc->bge_cdata.bge_rx_jumbo_ring_map); 1946 1947 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 1948 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 1949 1950 /* Destroy RX return ring. */ 1951 if (sc->bge_cdata.bge_rx_return_ring_map) 1952 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 1953 sc->bge_cdata.bge_rx_return_ring_map); 1954 1955 if (sc->bge_cdata.bge_rx_return_ring_map && 1956 sc->bge_ldata.bge_rx_return_ring) 1957 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 1958 sc->bge_ldata.bge_rx_return_ring, 1959 sc->bge_cdata.bge_rx_return_ring_map); 1960 1961 if (sc->bge_cdata.bge_rx_return_ring_tag) 1962 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 1963 1964 /* Destroy TX ring. */ 1965 if (sc->bge_cdata.bge_tx_ring_map) 1966 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 1967 sc->bge_cdata.bge_tx_ring_map); 1968 1969 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) 1970 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 1971 sc->bge_ldata.bge_tx_ring, 1972 sc->bge_cdata.bge_tx_ring_map); 1973 1974 if (sc->bge_cdata.bge_tx_ring_tag) 1975 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 1976 1977 /* Destroy status block. */ 1978 if (sc->bge_cdata.bge_status_map) 1979 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 1980 sc->bge_cdata.bge_status_map); 1981 1982 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) 1983 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 1984 sc->bge_ldata.bge_status_block, 1985 sc->bge_cdata.bge_status_map); 1986 1987 if (sc->bge_cdata.bge_status_tag) 1988 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 1989 1990 /* Destroy statistics block. */ 1991 if (sc->bge_cdata.bge_stats_map) 1992 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 1993 sc->bge_cdata.bge_stats_map); 1994 1995 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) 1996 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 1997 sc->bge_ldata.bge_stats, 1998 sc->bge_cdata.bge_stats_map); 1999 2000 if (sc->bge_cdata.bge_stats_tag) 2001 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2002 2003 /* Destroy the parent tag. */ 2004 if (sc->bge_cdata.bge_parent_tag) 2005 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2006 } 2007 2008 static int 2009 bge_dma_alloc(device_t dev) 2010 { 2011 struct bge_dmamap_arg ctx; 2012 struct bge_softc *sc; 2013 int i, error; 2014 2015 sc = device_get_softc(dev); 2016 2017 /* 2018 * Allocate the parent bus DMA tag appropriate for PCI. 2019 */ 2020 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2021 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2022 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2023 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2024 2025 if (error != 0) { 2026 device_printf(sc->bge_dev, 2027 "could not allocate parent dma tag\n"); 2028 return (ENOMEM); 2029 } 2030 2031 /* 2032 * Create tag for mbufs. 2033 */ 2034 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 2035 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2036 NULL, MCLBYTES * BGE_NSEG_NEW, BGE_NSEG_NEW, MCLBYTES, 2037 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->bge_cdata.bge_mtag); 2038 2039 if (error) { 2040 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2041 return (ENOMEM); 2042 } 2043 2044 /* Create DMA maps for RX buffers. */ 2045 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2046 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 2047 &sc->bge_cdata.bge_rx_std_dmamap[i]); 2048 if (error) { 2049 device_printf(sc->bge_dev, 2050 "can't create DMA map for RX\n"); 2051 return (ENOMEM); 2052 } 2053 } 2054 2055 /* Create DMA maps for TX buffers. */ 2056 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2057 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 2058 &sc->bge_cdata.bge_tx_dmamap[i]); 2059 if (error) { 2060 device_printf(sc->bge_dev, 2061 "can't create DMA map for RX\n"); 2062 return (ENOMEM); 2063 } 2064 } 2065 2066 /* Create tag for standard RX ring. */ 2067 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2068 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2069 NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0, 2070 NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag); 2071 2072 if (error) { 2073 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2074 return (ENOMEM); 2075 } 2076 2077 /* Allocate DMA'able memory for standard RX ring. */ 2078 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag, 2079 (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT, 2080 &sc->bge_cdata.bge_rx_std_ring_map); 2081 if (error) 2082 return (ENOMEM); 2083 2084 bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 2085 2086 /* Load the address of the standard RX ring. */ 2087 ctx.bge_maxsegs = 1; 2088 ctx.sc = sc; 2089 2090 error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag, 2091 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring, 2092 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2093 2094 if (error) 2095 return (ENOMEM); 2096 2097 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr; 2098 2099 /* Create tags for jumbo mbufs. */ 2100 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2101 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2102 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2103 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 2104 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 2105 if (error) { 2106 device_printf(sc->bge_dev, 2107 "could not allocate jumbo dma tag\n"); 2108 return (ENOMEM); 2109 } 2110 2111 /* Create tag for jumbo RX ring. */ 2112 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2113 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2114 NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0, 2115 NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag); 2116 2117 if (error) { 2118 device_printf(sc->bge_dev, 2119 "could not allocate jumbo ring dma tag\n"); 2120 return (ENOMEM); 2121 } 2122 2123 /* Allocate DMA'able memory for jumbo RX ring. */ 2124 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2125 (void **)&sc->bge_ldata.bge_rx_jumbo_ring, 2126 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 2127 &sc->bge_cdata.bge_rx_jumbo_ring_map); 2128 if (error) 2129 return (ENOMEM); 2130 2131 /* Load the address of the jumbo RX ring. */ 2132 ctx.bge_maxsegs = 1; 2133 ctx.sc = sc; 2134 2135 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2136 sc->bge_cdata.bge_rx_jumbo_ring_map, 2137 sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ, 2138 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2139 2140 if (error) 2141 return (ENOMEM); 2142 2143 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr; 2144 2145 /* Create DMA maps for jumbo RX buffers. */ 2146 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2147 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2148 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2149 if (error) { 2150 device_printf(sc->bge_dev, 2151 "can't create DMA map for jumbo RX\n"); 2152 return (ENOMEM); 2153 } 2154 } 2155 2156 } 2157 2158 /* Create tag for RX return ring. */ 2159 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2160 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2161 NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0, 2162 NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag); 2163 2164 if (error) { 2165 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2166 return (ENOMEM); 2167 } 2168 2169 /* Allocate DMA'able memory for RX return ring. */ 2170 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag, 2171 (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT, 2172 &sc->bge_cdata.bge_rx_return_ring_map); 2173 if (error) 2174 return (ENOMEM); 2175 2176 bzero((char *)sc->bge_ldata.bge_rx_return_ring, 2177 BGE_RX_RTN_RING_SZ(sc)); 2178 2179 /* Load the address of the RX return ring. */ 2180 ctx.bge_maxsegs = 1; 2181 ctx.sc = sc; 2182 2183 error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag, 2184 sc->bge_cdata.bge_rx_return_ring_map, 2185 sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc), 2186 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2187 2188 if (error) 2189 return (ENOMEM); 2190 2191 sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr; 2192 2193 /* Create tag for TX ring. */ 2194 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2195 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2196 NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL, 2197 &sc->bge_cdata.bge_tx_ring_tag); 2198 2199 if (error) { 2200 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2201 return (ENOMEM); 2202 } 2203 2204 /* Allocate DMA'able memory for TX ring. */ 2205 error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag, 2206 (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT, 2207 &sc->bge_cdata.bge_tx_ring_map); 2208 if (error) 2209 return (ENOMEM); 2210 2211 bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 2212 2213 /* Load the address of the TX ring. */ 2214 ctx.bge_maxsegs = 1; 2215 ctx.sc = sc; 2216 2217 error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag, 2218 sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring, 2219 BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2220 2221 if (error) 2222 return (ENOMEM); 2223 2224 sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr; 2225 2226 /* Create tag for status block. */ 2227 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2228 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2229 NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0, 2230 NULL, NULL, &sc->bge_cdata.bge_status_tag); 2231 2232 if (error) { 2233 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2234 return (ENOMEM); 2235 } 2236 2237 /* Allocate DMA'able memory for status block. */ 2238 error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag, 2239 (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT, 2240 &sc->bge_cdata.bge_status_map); 2241 if (error) 2242 return (ENOMEM); 2243 2244 bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2245 2246 /* Load the address of the status block. */ 2247 ctx.sc = sc; 2248 ctx.bge_maxsegs = 1; 2249 2250 error = bus_dmamap_load(sc->bge_cdata.bge_status_tag, 2251 sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block, 2252 BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2253 2254 if (error) 2255 return (ENOMEM); 2256 2257 sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr; 2258 2259 /* Create tag for statistics block. */ 2260 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2261 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2262 NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL, 2263 &sc->bge_cdata.bge_stats_tag); 2264 2265 if (error) { 2266 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2267 return (ENOMEM); 2268 } 2269 2270 /* Allocate DMA'able memory for statistics block. */ 2271 error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag, 2272 (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT, 2273 &sc->bge_cdata.bge_stats_map); 2274 if (error) 2275 return (ENOMEM); 2276 2277 bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ); 2278 2279 /* Load the address of the statstics block. */ 2280 ctx.sc = sc; 2281 ctx.bge_maxsegs = 1; 2282 2283 error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag, 2284 sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats, 2285 BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2286 2287 if (error) 2288 return (ENOMEM); 2289 2290 sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr; 2291 2292 return (0); 2293 } 2294 2295 #if __FreeBSD_version > 602105 2296 /* 2297 * Return true if this device has more than one port. 2298 */ 2299 static int 2300 bge_has_multiple_ports(struct bge_softc *sc) 2301 { 2302 device_t dev = sc->bge_dev; 2303 u_int b, s, f, fscan; 2304 2305 b = pci_get_bus(dev); 2306 s = pci_get_slot(dev); 2307 f = pci_get_function(dev); 2308 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 2309 if (fscan != f && pci_find_bsf(b, s, fscan) != NULL) 2310 return (1); 2311 return (0); 2312 } 2313 2314 /* 2315 * Return true if MSI can be used with this device. 2316 */ 2317 static int 2318 bge_can_use_msi(struct bge_softc *sc) 2319 { 2320 int can_use_msi = 0; 2321 2322 switch (sc->bge_asicrev) { 2323 case BGE_ASICREV_BCM5714: 2324 /* 2325 * Apparently, MSI doesn't work when this chip is configured 2326 * in single-port mode. 2327 */ 2328 if (bge_has_multiple_ports(sc)) 2329 can_use_msi = 1; 2330 break; 2331 case BGE_ASICREV_BCM5750: 2332 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 2333 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 2334 can_use_msi = 1; 2335 break; 2336 case BGE_ASICREV_BCM5752: 2337 case BGE_ASICREV_BCM5780: 2338 can_use_msi = 1; 2339 break; 2340 } 2341 return (can_use_msi); 2342 } 2343 #endif 2344 2345 static int 2346 bge_attach(device_t dev) 2347 { 2348 struct ifnet *ifp; 2349 struct bge_softc *sc; 2350 uint32_t hwcfg = 0; 2351 u_char eaddr[ETHER_ADDR_LEN]; 2352 int error, reg, rid, trys; 2353 2354 sc = device_get_softc(dev); 2355 sc->bge_dev = dev; 2356 2357 /* 2358 * Map control/status registers. 2359 */ 2360 pci_enable_busmaster(dev); 2361 2362 rid = BGE_PCI_BAR0; 2363 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2364 RF_ACTIVE | PCI_RF_DENSE); 2365 2366 if (sc->bge_res == NULL) { 2367 device_printf (sc->bge_dev, "couldn't map memory\n"); 2368 error = ENXIO; 2369 goto fail; 2370 } 2371 2372 sc->bge_btag = rman_get_bustag(sc->bge_res); 2373 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 2374 2375 /* Save ASIC rev. */ 2376 2377 sc->bge_chipid = 2378 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 2379 BGE_PCIMISCCTL_ASICREV; 2380 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2381 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2382 2383 /* 2384 * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the 2385 * 5705 A0 and A1 chips. 2386 */ 2387 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && 2388 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 2389 sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2390 sc->bge_chipid != BGE_CHIPID_BCM5705_A1) 2391 sc->bge_flags |= BGE_FLAG_WIRESPEED; 2392 2393 if (bge_has_eaddr(sc)) 2394 sc->bge_flags |= BGE_FLAG_EADDR; 2395 2396 /* Save chipset family. */ 2397 switch (sc->bge_asicrev) { 2398 case BGE_ASICREV_BCM5700: 2399 case BGE_ASICREV_BCM5701: 2400 case BGE_ASICREV_BCM5703: 2401 case BGE_ASICREV_BCM5704: 2402 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 2403 break; 2404 case BGE_ASICREV_BCM5714_A0: 2405 case BGE_ASICREV_BCM5780: 2406 case BGE_ASICREV_BCM5714: 2407 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */; 2408 /* FALLTHRU */ 2409 case BGE_ASICREV_BCM5750: 2410 case BGE_ASICREV_BCM5752: 2411 case BGE_ASICREV_BCM5755: 2412 case BGE_ASICREV_BCM5787: 2413 case BGE_ASICREV_BCM5906: 2414 sc->bge_flags |= BGE_FLAG_575X_PLUS; 2415 /* FALLTHRU */ 2416 case BGE_ASICREV_BCM5705: 2417 sc->bge_flags |= BGE_FLAG_5705_PLUS; 2418 break; 2419 } 2420 2421 /* Set various bug flags. */ 2422 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2423 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2424 sc->bge_flags |= BGE_FLAG_CRC_BUG; 2425 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 2426 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 2427 sc->bge_flags |= BGE_FLAG_ADC_BUG; 2428 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2429 sc->bge_flags |= BGE_FLAG_5704_A0_BUG; 2430 if (BGE_IS_5705_PLUS(sc) && 2431 !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) { 2432 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2433 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2434 if (sc->bge_chipid != BGE_CHIPID_BCM5722_A0) 2435 sc->bge_flags |= BGE_FLAG_JITTER_BUG; 2436 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 2437 sc->bge_flags |= BGE_FLAG_BER_BUG; 2438 } 2439 2440 /* 2441 * Check if this is a PCI-X or PCI Express device. 2442 */ 2443 #if __FreeBSD_version > 602101 2444 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 2445 /* 2446 * Found a PCI Express capabilities register, this 2447 * must be a PCI Express device. 2448 */ 2449 if (reg != 0) 2450 sc->bge_flags |= BGE_FLAG_PCIE; 2451 } else if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) { 2452 if (reg != 0) 2453 sc->bge_flags |= BGE_FLAG_PCIX; 2454 } 2455 2456 #else 2457 if (BGE_IS_5705_PLUS(sc)) { 2458 reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4); 2459 if ((reg & 0xFF) == BGE_PCIE_CAPID) 2460 sc->bge_flags |= BGE_FLAG_PCIE; 2461 } else { 2462 /* 2463 * Check if the device is in PCI-X Mode. 2464 * (This bit is not valid on PCI Express controllers.) 2465 */ 2466 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 2467 BGE_PCISTATE_PCI_BUSMODE) == 0) 2468 sc->bge_flags |= BGE_FLAG_PCIX; 2469 } 2470 #endif 2471 2472 #if __FreeBSD_version > 602105 2473 { 2474 int msicount; 2475 2476 /* 2477 * Allocate the interrupt, using MSI if possible. These devices 2478 * support 8 MSI messages, but only the first one is used in 2479 * normal operation. 2480 */ 2481 if (bge_can_use_msi(sc)) { 2482 msicount = pci_msi_count(dev); 2483 if (msicount > 1) 2484 msicount = 1; 2485 } else 2486 msicount = 0; 2487 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { 2488 rid = 1; 2489 sc->bge_flags |= BGE_FLAG_MSI; 2490 } else 2491 rid = 0; 2492 } 2493 #else 2494 rid = 0; 2495 #endif 2496 2497 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2498 RF_SHAREABLE | RF_ACTIVE); 2499 2500 if (sc->bge_irq == NULL) { 2501 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 2502 error = ENXIO; 2503 goto fail; 2504 } 2505 2506 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 2507 2508 /* Try to reset the chip. */ 2509 if (bge_reset(sc)) { 2510 device_printf(sc->bge_dev, "chip reset failed\n"); 2511 error = ENXIO; 2512 goto fail; 2513 } 2514 2515 sc->bge_asf_mode = 0; 2516 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) 2517 == BGE_MAGIC_NUMBER)) { 2518 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) 2519 & BGE_HWCFG_ASF) { 2520 sc->bge_asf_mode |= ASF_ENABLE; 2521 sc->bge_asf_mode |= ASF_STACKUP; 2522 if (sc->bge_asicrev == BGE_ASICREV_BCM5750) { 2523 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 2524 } 2525 } 2526 } 2527 2528 /* Try to reset the chip again the nice way. */ 2529 bge_stop_fw(sc); 2530 bge_sig_pre_reset(sc, BGE_RESET_STOP); 2531 if (bge_reset(sc)) { 2532 device_printf(sc->bge_dev, "chip reset failed\n"); 2533 error = ENXIO; 2534 goto fail; 2535 } 2536 2537 bge_sig_legacy(sc, BGE_RESET_STOP); 2538 bge_sig_post_reset(sc, BGE_RESET_STOP); 2539 2540 if (bge_chipinit(sc)) { 2541 device_printf(sc->bge_dev, "chip initialization failed\n"); 2542 error = ENXIO; 2543 goto fail; 2544 } 2545 2546 error = bge_get_eaddr(sc, eaddr); 2547 if (error) { 2548 device_printf(sc->bge_dev, 2549 "failed to read station address\n"); 2550 error = ENXIO; 2551 goto fail; 2552 } 2553 2554 /* 5705 limits RX return ring to 512 entries. */ 2555 if (BGE_IS_5705_PLUS(sc)) 2556 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2557 else 2558 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2559 2560 if (bge_dma_alloc(dev)) { 2561 device_printf(sc->bge_dev, 2562 "failed to allocate DMA resources\n"); 2563 error = ENXIO; 2564 goto fail; 2565 } 2566 2567 /* Set default tuneable values. */ 2568 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2569 sc->bge_rx_coal_ticks = 150; 2570 sc->bge_tx_coal_ticks = 150; 2571 sc->bge_rx_max_coal_bds = 10; 2572 sc->bge_tx_max_coal_bds = 10; 2573 2574 /* Set up ifnet structure */ 2575 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 2576 if (ifp == NULL) { 2577 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 2578 error = ENXIO; 2579 goto fail; 2580 } 2581 ifp->if_softc = sc; 2582 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2583 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2584 ifp->if_ioctl = bge_ioctl; 2585 ifp->if_start = bge_start; 2586 ifp->if_init = bge_init; 2587 ifp->if_mtu = ETHERMTU; 2588 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 2589 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 2590 IFQ_SET_READY(&ifp->if_snd); 2591 ifp->if_hwassist = BGE_CSUM_FEATURES; 2592 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 2593 IFCAP_VLAN_MTU; 2594 #ifdef IFCAP_VLAN_HWCSUM 2595 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 2596 #endif 2597 ifp->if_capenable = ifp->if_capabilities; 2598 #ifdef DEVICE_POLLING 2599 ifp->if_capabilities |= IFCAP_POLLING; 2600 #endif 2601 2602 /* 2603 * 5700 B0 chips do not support checksumming correctly due 2604 * to hardware bugs. 2605 */ 2606 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 2607 ifp->if_capabilities &= ~IFCAP_HWCSUM; 2608 ifp->if_capenable &= IFCAP_HWCSUM; 2609 ifp->if_hwassist = 0; 2610 } 2611 2612 /* 2613 * Figure out what sort of media we have by checking the 2614 * hardware config word in the first 32k of NIC internal memory, 2615 * or fall back to examining the EEPROM if necessary. 2616 * Note: on some BCM5700 cards, this value appears to be unset. 2617 * If that's the case, we have to rely on identifying the NIC 2618 * by its PCI subsystem ID, as we do below for the SysKonnect 2619 * SK-9D41. 2620 */ 2621 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 2622 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2623 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 2624 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 2625 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 2626 sizeof(hwcfg))) { 2627 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 2628 error = ENXIO; 2629 goto fail; 2630 } 2631 hwcfg = ntohl(hwcfg); 2632 } 2633 2634 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2635 sc->bge_flags |= BGE_FLAG_TBI; 2636 2637 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2638 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 2639 sc->bge_flags |= BGE_FLAG_TBI; 2640 2641 if (sc->bge_flags & BGE_FLAG_TBI) { 2642 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2643 bge_ifmedia_sts); 2644 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 2645 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 2646 0, NULL); 2647 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 2648 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 2649 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2650 } else { 2651 /* 2652 * Do transceiver setup and tell the firmware the 2653 * driver is down so we can try to get access the 2654 * probe if ASF is running. Retry a couple of times 2655 * if we get a conflict with the ASF firmware accessing 2656 * the PHY. 2657 */ 2658 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2659 again: 2660 bge_asf_driver_up(sc); 2661 2662 trys = 0; 2663 if (mii_phy_probe(dev, &sc->bge_miibus, 2664 bge_ifmedia_upd, bge_ifmedia_sts)) { 2665 if (trys++ < 4) { 2666 device_printf(sc->bge_dev, "Try again\n"); 2667 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR, 2668 BMCR_RESET); 2669 goto again; 2670 } 2671 2672 device_printf(sc->bge_dev, "MII without any PHY!\n"); 2673 error = ENXIO; 2674 goto fail; 2675 } 2676 2677 /* 2678 * Now tell the firmware we are going up after probing the PHY 2679 */ 2680 if (sc->bge_asf_mode & ASF_STACKUP) 2681 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2682 } 2683 2684 /* 2685 * When using the BCM5701 in PCI-X mode, data corruption has 2686 * been observed in the first few bytes of some received packets. 2687 * Aligning the packet buffer in memory eliminates the corruption. 2688 * Unfortunately, this misaligns the packet payloads. On platforms 2689 * which do not support unaligned accesses, we will realign the 2690 * payloads by copying the received packets. 2691 */ 2692 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 2693 sc->bge_flags & BGE_FLAG_PCIX) 2694 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 2695 2696 /* 2697 * Call MI attach routine. 2698 */ 2699 ether_ifattach(ifp, eaddr); 2700 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 2701 2702 /* 2703 * Hookup IRQ last. 2704 */ 2705 #if __FreeBSD_version > 700030 2706 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 2707 NULL, bge_intr, sc, &sc->bge_intrhand); 2708 #else 2709 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 2710 bge_intr, sc, &sc->bge_intrhand); 2711 #endif 2712 2713 if (error) { 2714 bge_detach(dev); 2715 device_printf(sc->bge_dev, "couldn't set up irq\n"); 2716 } 2717 2718 bge_add_sysctls(sc); 2719 2720 return (0); 2721 2722 fail: 2723 bge_release_resources(sc); 2724 2725 return (error); 2726 } 2727 2728 static int 2729 bge_detach(device_t dev) 2730 { 2731 struct bge_softc *sc; 2732 struct ifnet *ifp; 2733 2734 sc = device_get_softc(dev); 2735 ifp = sc->bge_ifp; 2736 2737 #ifdef DEVICE_POLLING 2738 if (ifp->if_capenable & IFCAP_POLLING) 2739 ether_poll_deregister(ifp); 2740 #endif 2741 2742 BGE_LOCK(sc); 2743 bge_stop(sc); 2744 bge_reset(sc); 2745 BGE_UNLOCK(sc); 2746 2747 callout_drain(&sc->bge_stat_ch); 2748 2749 ether_ifdetach(ifp); 2750 2751 if (sc->bge_flags & BGE_FLAG_TBI) { 2752 ifmedia_removeall(&sc->bge_ifmedia); 2753 } else { 2754 bus_generic_detach(dev); 2755 device_delete_child(dev, sc->bge_miibus); 2756 } 2757 2758 bge_release_resources(sc); 2759 2760 return (0); 2761 } 2762 2763 static void 2764 bge_release_resources(struct bge_softc *sc) 2765 { 2766 device_t dev; 2767 2768 dev = sc->bge_dev; 2769 2770 if (sc->bge_intrhand != NULL) 2771 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 2772 2773 if (sc->bge_irq != NULL) 2774 bus_release_resource(dev, SYS_RES_IRQ, 2775 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq); 2776 2777 #if __FreeBSD_version > 602105 2778 if (sc->bge_flags & BGE_FLAG_MSI) 2779 pci_release_msi(dev); 2780 #endif 2781 2782 if (sc->bge_res != NULL) 2783 bus_release_resource(dev, SYS_RES_MEMORY, 2784 BGE_PCI_BAR0, sc->bge_res); 2785 2786 if (sc->bge_ifp != NULL) 2787 if_free(sc->bge_ifp); 2788 2789 bge_dma_free(sc); 2790 2791 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 2792 BGE_LOCK_DESTROY(sc); 2793 } 2794 2795 static int 2796 bge_reset(struct bge_softc *sc) 2797 { 2798 device_t dev; 2799 uint32_t cachesize, command, pcistate, reset, val; 2800 void (*write_op)(struct bge_softc *, int, int); 2801 int i; 2802 2803 dev = sc->bge_dev; 2804 2805 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 2806 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 2807 if (sc->bge_flags & BGE_FLAG_PCIE) 2808 write_op = bge_writemem_direct; 2809 else 2810 write_op = bge_writemem_ind; 2811 } else 2812 write_op = bge_writereg_ind; 2813 2814 /* Save some important PCI state. */ 2815 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 2816 command = pci_read_config(dev, BGE_PCI_CMD, 4); 2817 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 2818 2819 pci_write_config(dev, BGE_PCI_MISC_CTL, 2820 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 2821 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 2822 2823 /* Disable fastboot on controllers that support it. */ 2824 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 2825 sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2826 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2827 if (bootverbose) 2828 device_printf(sc->bge_dev, "Disabling fastboot\n"); 2829 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 2830 } 2831 2832 /* 2833 * Write the magic number to SRAM at offset 0xB50. 2834 * When firmware finishes its initialization it will 2835 * write ~BGE_MAGIC_NUMBER to the same location. 2836 */ 2837 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2838 2839 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 2840 2841 /* XXX: Broadcom Linux driver. */ 2842 if (sc->bge_flags & BGE_FLAG_PCIE) { 2843 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 2844 CSR_WRITE_4(sc, 0x7E2C, 0x20); 2845 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2846 /* Prevent PCIE link training during global reset */ 2847 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 2848 reset |= 1 << 29; 2849 } 2850 } 2851 2852 /* 2853 * Set GPHY Power Down Override to leave GPHY 2854 * powered up in D0 uninitialized. 2855 */ 2856 if (BGE_IS_5705_PLUS(sc)) 2857 reset |= 0x04000000; 2858 2859 /* Issue global reset */ 2860 write_op(sc, BGE_MISC_CFG, reset); 2861 2862 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2863 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2864 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 2865 val | BGE_VCPU_STATUS_DRV_RESET); 2866 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 2867 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 2868 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 2869 } 2870 2871 DELAY(1000); 2872 2873 /* XXX: Broadcom Linux driver. */ 2874 if (sc->bge_flags & BGE_FLAG_PCIE) { 2875 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2876 DELAY(500000); /* wait for link training to complete */ 2877 val = pci_read_config(dev, 0xC4, 4); 2878 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 2879 } 2880 /* 2881 * Set PCIE max payload size to 128 bytes and clear error 2882 * status. 2883 */ 2884 pci_write_config(dev, 0xD8, 0xF5000, 4); 2885 } 2886 2887 /* Reset some of the PCI state that got zapped by reset. */ 2888 pci_write_config(dev, BGE_PCI_MISC_CTL, 2889 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 2890 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 2891 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 2892 pci_write_config(dev, BGE_PCI_CMD, command, 4); 2893 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2894 2895 /* Re-enable MSI, if neccesary, and enable the memory arbiter. */ 2896 if (BGE_IS_5714_FAMILY(sc)) { 2897 /* This chip disables MSI on reset. */ 2898 if (sc->bge_flags & BGE_FLAG_MSI) { 2899 val = pci_read_config(dev, BGE_PCI_MSI_CTL, 2); 2900 pci_write_config(dev, BGE_PCI_MSI_CTL, 2901 val | PCIM_MSICTRL_MSI_ENABLE, 2); 2902 val = CSR_READ_4(sc, BGE_MSI_MODE); 2903 CSR_WRITE_4(sc, BGE_MSI_MODE, 2904 val | BGE_MSIMODE_ENABLE); 2905 } 2906 val = CSR_READ_4(sc, BGE_MARB_MODE); 2907 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 2908 } else 2909 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2910 2911 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2912 for (i = 0; i < BGE_TIMEOUT; i++) { 2913 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2914 if (val & BGE_VCPU_STATUS_INIT_DONE) 2915 break; 2916 DELAY(100); 2917 } 2918 if (i == BGE_TIMEOUT) { 2919 device_printf(sc->bge_dev, "reset timed out\n"); 2920 return (1); 2921 } 2922 } else { 2923 /* 2924 * Poll until we see the 1's complement of the magic number. 2925 * This indicates that the firmware initialization is complete. 2926 * We expect this to fail if no chip containing the Ethernet 2927 * address is fitted though. 2928 */ 2929 for (i = 0; i < BGE_TIMEOUT; i++) { 2930 DELAY(10); 2931 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2932 if (val == ~BGE_MAGIC_NUMBER) 2933 break; 2934 } 2935 2936 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 2937 device_printf(sc->bge_dev, "firmware handshake timed out, " 2938 "found 0x%08x\n", val); 2939 } 2940 2941 /* 2942 * XXX Wait for the value of the PCISTATE register to 2943 * return to its original pre-reset state. This is a 2944 * fairly good indicator of reset completion. If we don't 2945 * wait for the reset to fully complete, trying to read 2946 * from the device's non-PCI registers may yield garbage 2947 * results. 2948 */ 2949 for (i = 0; i < BGE_TIMEOUT; i++) { 2950 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 2951 break; 2952 DELAY(10); 2953 } 2954 2955 if (sc->bge_flags & BGE_FLAG_PCIE) { 2956 reset = bge_readmem_ind(sc, 0x7C00); 2957 bge_writemem_ind(sc, 0x7C00, reset | (1 << 25)); 2958 } 2959 2960 /* Fix up byte swapping. */ 2961 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 2962 BGE_MODECTL_BYTESWAP_DATA); 2963 2964 /* Tell the ASF firmware we are up */ 2965 if (sc->bge_asf_mode & ASF_STACKUP) 2966 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2967 2968 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2969 2970 /* 2971 * The 5704 in TBI mode apparently needs some special 2972 * adjustment to insure the SERDES drive level is set 2973 * to 1.2V. 2974 */ 2975 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 2976 sc->bge_flags & BGE_FLAG_TBI) { 2977 val = CSR_READ_4(sc, BGE_SERDES_CFG); 2978 val = (val & ~0xFFF) | 0x880; 2979 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 2980 } 2981 2982 /* XXX: Broadcom Linux driver. */ 2983 if (sc->bge_flags & BGE_FLAG_PCIE && 2984 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2985 val = CSR_READ_4(sc, 0x7C00); 2986 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 2987 } 2988 DELAY(10000); 2989 2990 return(0); 2991 } 2992 2993 /* 2994 * Frame reception handling. This is called if there's a frame 2995 * on the receive return list. 2996 * 2997 * Note: we have to be able to handle two possibilities here: 2998 * 1) the frame is from the jumbo receive ring 2999 * 2) the frame is from the standard receive ring 3000 */ 3001 3002 static void 3003 bge_rxeof(struct bge_softc *sc) 3004 { 3005 struct ifnet *ifp; 3006 int stdcnt = 0, jumbocnt = 0; 3007 3008 BGE_LOCK_ASSERT(sc); 3009 3010 /* Nothing to do. */ 3011 if (sc->bge_rx_saved_considx == 3012 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) 3013 return; 3014 3015 ifp = sc->bge_ifp; 3016 3017 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 3018 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 3019 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3020 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD); 3021 if (BGE_IS_JUMBO_CAPABLE(sc)) 3022 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3023 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTREAD); 3024 3025 while(sc->bge_rx_saved_considx != 3026 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) { 3027 struct bge_rx_bd *cur_rx; 3028 uint32_t rxidx; 3029 struct mbuf *m = NULL; 3030 uint16_t vlan_tag = 0; 3031 int have_tag = 0; 3032 3033 #ifdef DEVICE_POLLING 3034 if (ifp->if_capenable & IFCAP_POLLING) { 3035 if (sc->rxcycles <= 0) 3036 break; 3037 sc->rxcycles--; 3038 } 3039 #endif 3040 3041 cur_rx = 3042 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx]; 3043 3044 rxidx = cur_rx->bge_idx; 3045 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 3046 3047 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3048 have_tag = 1; 3049 vlan_tag = cur_rx->bge_vlan_tag; 3050 } 3051 3052 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3053 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3054 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 3055 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx], 3056 BUS_DMASYNC_POSTREAD); 3057 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 3058 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx]); 3059 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3060 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 3061 jumbocnt++; 3062 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3063 ifp->if_ierrors++; 3064 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3065 continue; 3066 } 3067 if (bge_newbuf_jumbo(sc, 3068 sc->bge_jumbo, NULL) == ENOBUFS) { 3069 ifp->if_ierrors++; 3070 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3071 continue; 3072 } 3073 } else { 3074 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3075 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 3076 sc->bge_cdata.bge_rx_std_dmamap[rxidx], 3077 BUS_DMASYNC_POSTREAD); 3078 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 3079 sc->bge_cdata.bge_rx_std_dmamap[rxidx]); 3080 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3081 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 3082 stdcnt++; 3083 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3084 ifp->if_ierrors++; 3085 bge_newbuf_std(sc, sc->bge_std, m); 3086 continue; 3087 } 3088 if (bge_newbuf_std(sc, sc->bge_std, 3089 NULL) == ENOBUFS) { 3090 ifp->if_ierrors++; 3091 bge_newbuf_std(sc, sc->bge_std, m); 3092 continue; 3093 } 3094 } 3095 3096 ifp->if_ipackets++; 3097 #ifndef __NO_STRICT_ALIGNMENT 3098 /* 3099 * For architectures with strict alignment we must make sure 3100 * the payload is aligned. 3101 */ 3102 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 3103 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 3104 cur_rx->bge_len); 3105 m->m_data += ETHER_ALIGN; 3106 } 3107 #endif 3108 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3109 m->m_pkthdr.rcvif = ifp; 3110 3111 if (ifp->if_capenable & IFCAP_RXCSUM) { 3112 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 3113 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3114 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 3115 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3116 } 3117 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3118 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 3119 m->m_pkthdr.csum_data = 3120 cur_rx->bge_tcp_udp_csum; 3121 m->m_pkthdr.csum_flags |= 3122 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 3123 } 3124 } 3125 3126 /* 3127 * If we received a packet with a vlan tag, 3128 * attach that information to the packet. 3129 */ 3130 if (have_tag) { 3131 #if __FreeBSD_version > 700022 3132 m->m_pkthdr.ether_vtag = vlan_tag; 3133 m->m_flags |= M_VLANTAG; 3134 #else 3135 VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag); 3136 if (m == NULL) 3137 continue; 3138 #endif 3139 } 3140 3141 BGE_UNLOCK(sc); 3142 (*ifp->if_input)(ifp, m); 3143 BGE_LOCK(sc); 3144 } 3145 3146 if (stdcnt > 0) 3147 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3148 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 3149 3150 if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0) 3151 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3152 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 3153 3154 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3155 if (stdcnt) 3156 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3157 if (jumbocnt) 3158 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3159 #ifdef notyet 3160 /* 3161 * This register wraps very quickly under heavy packet drops. 3162 * If you need correct statistics, you can enable this check. 3163 */ 3164 if (BGE_IS_5705_PLUS(sc)) 3165 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3166 #endif 3167 } 3168 3169 static void 3170 bge_txeof(struct bge_softc *sc) 3171 { 3172 struct bge_tx_bd *cur_tx = NULL; 3173 struct ifnet *ifp; 3174 3175 BGE_LOCK_ASSERT(sc); 3176 3177 /* Nothing to do. */ 3178 if (sc->bge_tx_saved_considx == 3179 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) 3180 return; 3181 3182 ifp = sc->bge_ifp; 3183 3184 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 3185 sc->bge_cdata.bge_tx_ring_map, 3186 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3187 /* 3188 * Go through our tx ring and free mbufs for those 3189 * frames that have been sent. 3190 */ 3191 while (sc->bge_tx_saved_considx != 3192 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) { 3193 uint32_t idx = 0; 3194 3195 idx = sc->bge_tx_saved_considx; 3196 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 3197 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3198 ifp->if_opackets++; 3199 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 3200 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 3201 sc->bge_cdata.bge_tx_dmamap[idx], 3202 BUS_DMASYNC_POSTWRITE); 3203 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 3204 sc->bge_cdata.bge_tx_dmamap[idx]); 3205 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 3206 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3207 } 3208 sc->bge_txcnt--; 3209 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3210 } 3211 3212 if (cur_tx != NULL) 3213 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3214 if (sc->bge_txcnt == 0) 3215 sc->bge_timer = 0; 3216 } 3217 3218 #ifdef DEVICE_POLLING 3219 static void 3220 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3221 { 3222 struct bge_softc *sc = ifp->if_softc; 3223 uint32_t statusword; 3224 3225 BGE_LOCK(sc); 3226 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3227 BGE_UNLOCK(sc); 3228 return; 3229 } 3230 3231 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3232 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD); 3233 3234 statusword = atomic_readandclear_32( 3235 &sc->bge_ldata.bge_status_block->bge_status); 3236 3237 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3238 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD); 3239 3240 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 3241 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 3242 sc->bge_link_evt++; 3243 3244 if (cmd == POLL_AND_CHECK_STATUS) 3245 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3246 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3247 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 3248 bge_link_upd(sc); 3249 3250 sc->rxcycles = count; 3251 bge_rxeof(sc); 3252 bge_txeof(sc); 3253 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3254 bge_start_locked(ifp); 3255 3256 BGE_UNLOCK(sc); 3257 } 3258 #endif /* DEVICE_POLLING */ 3259 3260 static void 3261 bge_intr(void *xsc) 3262 { 3263 struct bge_softc *sc; 3264 struct ifnet *ifp; 3265 uint32_t statusword; 3266 3267 sc = xsc; 3268 3269 BGE_LOCK(sc); 3270 3271 ifp = sc->bge_ifp; 3272 3273 #ifdef DEVICE_POLLING 3274 if (ifp->if_capenable & IFCAP_POLLING) { 3275 BGE_UNLOCK(sc); 3276 return; 3277 } 3278 #endif 3279 3280 /* 3281 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 3282 * disable interrupts by writing nonzero like we used to, since with 3283 * our current organization this just gives complications and 3284 * pessimizations for re-enabling interrupts. We used to have races 3285 * instead of the necessary complications. Disabling interrupts 3286 * would just reduce the chance of a status update while we are 3287 * running (by switching to the interrupt-mode coalescence 3288 * parameters), but this chance is already very low so it is more 3289 * efficient to get another interrupt than prevent it. 3290 * 3291 * We do the ack first to ensure another interrupt if there is a 3292 * status update after the ack. We don't check for the status 3293 * changing later because it is more efficient to get another 3294 * interrupt than prevent it, not quite as above (not checking is 3295 * a smaller optimization than not toggling the interrupt enable, 3296 * since checking doesn't involve PCI accesses and toggling require 3297 * the status check). So toggling would probably be a pessimization 3298 * even with MSI. It would only be needed for using a task queue. 3299 */ 3300 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3301 3302 /* 3303 * Do the mandatory PCI flush as well as get the link status. 3304 */ 3305 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 3306 3307 /* Make sure the descriptor ring indexes are coherent. */ 3308 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3309 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD); 3310 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3311 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD); 3312 3313 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3314 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3315 statusword || sc->bge_link_evt) 3316 bge_link_upd(sc); 3317 3318 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3319 /* Check RX return ring producer/consumer. */ 3320 bge_rxeof(sc); 3321 3322 /* Check TX ring producer/consumer. */ 3323 bge_txeof(sc); 3324 } 3325 3326 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3327 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3328 bge_start_locked(ifp); 3329 3330 BGE_UNLOCK(sc); 3331 } 3332 3333 static void 3334 bge_asf_driver_up(struct bge_softc *sc) 3335 { 3336 if (sc->bge_asf_mode & ASF_STACKUP) { 3337 /* Send ASF heartbeat aprox. every 2s */ 3338 if (sc->bge_asf_count) 3339 sc->bge_asf_count --; 3340 else { 3341 sc->bge_asf_count = 5; 3342 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, 3343 BGE_FW_DRV_ALIVE); 3344 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); 3345 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); 3346 CSR_WRITE_4(sc, BGE_CPU_EVENT, 3347 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 3348 } 3349 } 3350 } 3351 3352 static void 3353 bge_tick(void *xsc) 3354 { 3355 struct bge_softc *sc = xsc; 3356 struct mii_data *mii = NULL; 3357 3358 BGE_LOCK_ASSERT(sc); 3359 3360 /* Synchronize with possible callout reset/stop. */ 3361 if (callout_pending(&sc->bge_stat_ch) || 3362 !callout_active(&sc->bge_stat_ch)) 3363 return; 3364 3365 if (BGE_IS_5705_PLUS(sc)) 3366 bge_stats_update_regs(sc); 3367 else 3368 bge_stats_update(sc); 3369 3370 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 3371 mii = device_get_softc(sc->bge_miibus); 3372 /* 3373 * Do not touch PHY if we have link up. This could break 3374 * IPMI/ASF mode or produce extra input errors 3375 * (extra errors was reported for bcm5701 & bcm5704). 3376 */ 3377 if (!sc->bge_link) 3378 mii_tick(mii); 3379 } else { 3380 /* 3381 * Since in TBI mode auto-polling can't be used we should poll 3382 * link status manually. Here we register pending link event 3383 * and trigger interrupt. 3384 */ 3385 #ifdef DEVICE_POLLING 3386 /* In polling mode we poll link state in bge_poll(). */ 3387 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 3388 #endif 3389 { 3390 sc->bge_link_evt++; 3391 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3392 } 3393 } 3394 3395 bge_asf_driver_up(sc); 3396 bge_watchdog(sc); 3397 3398 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 3399 } 3400 3401 static void 3402 bge_stats_update_regs(struct bge_softc *sc) 3403 { 3404 struct ifnet *ifp; 3405 3406 ifp = sc->bge_ifp; 3407 3408 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 3409 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 3410 3411 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3412 } 3413 3414 static void 3415 bge_stats_update(struct bge_softc *sc) 3416 { 3417 struct ifnet *ifp; 3418 bus_size_t stats; 3419 uint32_t cnt; /* current register value */ 3420 3421 ifp = sc->bge_ifp; 3422 3423 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3424 3425 #define READ_STAT(sc, stats, stat) \ 3426 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3427 3428 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 3429 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); 3430 sc->bge_tx_collisions = cnt; 3431 3432 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 3433 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); 3434 sc->bge_rx_discards = cnt; 3435 3436 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 3437 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); 3438 sc->bge_tx_discards = cnt; 3439 3440 #undef READ_STAT 3441 } 3442 3443 /* 3444 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3445 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3446 * but when such padded frames employ the bge IP/TCP checksum offload, 3447 * the hardware checksum assist gives incorrect results (possibly 3448 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3449 * If we pad such runts with zeros, the onboard checksum comes out correct. 3450 */ 3451 static __inline int 3452 bge_cksum_pad(struct mbuf *m) 3453 { 3454 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 3455 struct mbuf *last; 3456 3457 /* If there's only the packet-header and we can pad there, use it. */ 3458 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 3459 M_TRAILINGSPACE(m) >= padlen) { 3460 last = m; 3461 } else { 3462 /* 3463 * Walk packet chain to find last mbuf. We will either 3464 * pad there, or append a new mbuf and pad it. 3465 */ 3466 for (last = m; last->m_next != NULL; last = last->m_next); 3467 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 3468 /* Allocate new empty mbuf, pad it. Compact later. */ 3469 struct mbuf *n; 3470 3471 MGET(n, M_DONTWAIT, MT_DATA); 3472 if (n == NULL) 3473 return (ENOBUFS); 3474 n->m_len = 0; 3475 last->m_next = n; 3476 last = n; 3477 } 3478 } 3479 3480 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 3481 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 3482 last->m_len += padlen; 3483 m->m_pkthdr.len += padlen; 3484 3485 return (0); 3486 } 3487 3488 /* 3489 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3490 * pointers to descriptors. 3491 */ 3492 static int 3493 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 3494 { 3495 bus_dma_segment_t segs[BGE_NSEG_NEW]; 3496 bus_dmamap_t map; 3497 struct bge_tx_bd *d; 3498 struct mbuf *m = *m_head; 3499 uint32_t idx = *txidx; 3500 uint16_t csum_flags; 3501 int nsegs, i, error; 3502 3503 csum_flags = 0; 3504 if (m->m_pkthdr.csum_flags) { 3505 if (m->m_pkthdr.csum_flags & CSUM_IP) 3506 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3507 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 3508 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3509 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 3510 (error = bge_cksum_pad(m)) != 0) { 3511 m_freem(m); 3512 *m_head = NULL; 3513 return (error); 3514 } 3515 } 3516 if (m->m_flags & M_LASTFRAG) 3517 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 3518 else if (m->m_flags & M_FRAG) 3519 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 3520 } 3521 3522 map = sc->bge_cdata.bge_tx_dmamap[idx]; 3523 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, segs, 3524 &nsegs, BUS_DMA_NOWAIT); 3525 if (error == EFBIG) { 3526 m = m_defrag(m, M_DONTWAIT); 3527 if (m == NULL) { 3528 m_freem(*m_head); 3529 *m_head = NULL; 3530 return (ENOBUFS); 3531 } 3532 *m_head = m; 3533 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, 3534 segs, &nsegs, BUS_DMA_NOWAIT); 3535 if (error) { 3536 m_freem(m); 3537 *m_head = NULL; 3538 return (error); 3539 } 3540 } else if (error != 0) 3541 return (error); 3542 3543 /* 3544 * Sanity check: avoid coming within 16 descriptors 3545 * of the end of the ring. 3546 */ 3547 if (nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 3548 bus_dmamap_unload(sc->bge_cdata.bge_mtag, map); 3549 return (ENOBUFS); 3550 } 3551 3552 bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE); 3553 3554 for (i = 0; ; i++) { 3555 d = &sc->bge_ldata.bge_tx_ring[idx]; 3556 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 3557 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 3558 d->bge_len = segs[i].ds_len; 3559 d->bge_flags = csum_flags; 3560 if (i == nsegs - 1) 3561 break; 3562 BGE_INC(idx, BGE_TX_RING_CNT); 3563 } 3564 3565 /* Mark the last segment as end of packet... */ 3566 d->bge_flags |= BGE_TXBDFLAG_END; 3567 3568 /* ... and put VLAN tag into first segment. */ 3569 d = &sc->bge_ldata.bge_tx_ring[*txidx]; 3570 #if __FreeBSD_version > 700022 3571 if (m->m_flags & M_VLANTAG) { 3572 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3573 d->bge_vlan_tag = m->m_pkthdr.ether_vtag; 3574 } else 3575 d->bge_vlan_tag = 0; 3576 #else 3577 { 3578 struct m_tag *mtag; 3579 3580 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) { 3581 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3582 d->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 3583 } else 3584 d->bge_vlan_tag = 0; 3585 } 3586 #endif 3587 3588 /* 3589 * Insure that the map for this transmission 3590 * is placed at the array index of the last descriptor 3591 * in this chain. 3592 */ 3593 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 3594 sc->bge_cdata.bge_tx_dmamap[idx] = map; 3595 sc->bge_cdata.bge_tx_chain[idx] = m; 3596 sc->bge_txcnt += nsegs; 3597 3598 BGE_INC(idx, BGE_TX_RING_CNT); 3599 *txidx = idx; 3600 3601 return (0); 3602 } 3603 3604 /* 3605 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3606 * to the mbuf data regions directly in the transmit descriptors. 3607 */ 3608 static void 3609 bge_start_locked(struct ifnet *ifp) 3610 { 3611 struct bge_softc *sc; 3612 struct mbuf *m_head = NULL; 3613 uint32_t prodidx; 3614 int count = 0; 3615 3616 sc = ifp->if_softc; 3617 3618 if (!sc->bge_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3619 return; 3620 3621 prodidx = sc->bge_tx_prodidx; 3622 3623 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3624 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3625 if (m_head == NULL) 3626 break; 3627 3628 /* 3629 * XXX 3630 * The code inside the if() block is never reached since we 3631 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting 3632 * requests to checksum TCP/UDP in a fragmented packet. 3633 * 3634 * XXX 3635 * safety overkill. If this is a fragmented packet chain 3636 * with delayed TCP/UDP checksums, then only encapsulate 3637 * it if we have enough descriptors to handle the entire 3638 * chain at once. 3639 * (paranoia -- may not actually be needed) 3640 */ 3641 if (m_head->m_flags & M_FIRSTFRAG && 3642 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3643 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3644 m_head->m_pkthdr.csum_data + 16) { 3645 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3646 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3647 break; 3648 } 3649 } 3650 3651 /* 3652 * Pack the data into the transmit ring. If we 3653 * don't have room, set the OACTIVE flag and wait 3654 * for the NIC to drain the ring. 3655 */ 3656 if (bge_encap(sc, &m_head, &prodidx)) { 3657 if (m_head == NULL) 3658 break; 3659 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3660 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3661 break; 3662 } 3663 ++count; 3664 3665 /* 3666 * If there's a BPF listener, bounce a copy of this frame 3667 * to him. 3668 */ 3669 #ifdef ETHER_BPF_MTAP 3670 ETHER_BPF_MTAP(ifp, m_head); 3671 #else 3672 BPF_MTAP(ifp, m_head); 3673 #endif 3674 } 3675 3676 if (count == 0) 3677 /* No packets were dequeued. */ 3678 return; 3679 3680 /* Transmit. */ 3681 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3682 /* 5700 b2 errata */ 3683 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 3684 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3685 3686 sc->bge_tx_prodidx = prodidx; 3687 3688 /* 3689 * Set a timeout in case the chip goes out to lunch. 3690 */ 3691 sc->bge_timer = 5; 3692 } 3693 3694 /* 3695 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3696 * to the mbuf data regions directly in the transmit descriptors. 3697 */ 3698 static void 3699 bge_start(struct ifnet *ifp) 3700 { 3701 struct bge_softc *sc; 3702 3703 sc = ifp->if_softc; 3704 BGE_LOCK(sc); 3705 bge_start_locked(ifp); 3706 BGE_UNLOCK(sc); 3707 } 3708 3709 static void 3710 bge_init_locked(struct bge_softc *sc) 3711 { 3712 struct ifnet *ifp; 3713 uint16_t *m; 3714 3715 BGE_LOCK_ASSERT(sc); 3716 3717 ifp = sc->bge_ifp; 3718 3719 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3720 return; 3721 3722 /* Cancel pending I/O and flush buffers. */ 3723 bge_stop(sc); 3724 3725 bge_stop_fw(sc); 3726 bge_sig_pre_reset(sc, BGE_RESET_START); 3727 bge_reset(sc); 3728 bge_sig_legacy(sc, BGE_RESET_START); 3729 bge_sig_post_reset(sc, BGE_RESET_START); 3730 3731 bge_chipinit(sc); 3732 3733 /* 3734 * Init the various state machines, ring 3735 * control blocks and firmware. 3736 */ 3737 if (bge_blockinit(sc)) { 3738 device_printf(sc->bge_dev, "initialization failure\n"); 3739 return; 3740 } 3741 3742 ifp = sc->bge_ifp; 3743 3744 /* Specify MTU. */ 3745 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3746 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3747 3748 /* Load our MAC address. */ 3749 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 3750 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3751 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3752 3753 /* Program promiscuous mode. */ 3754 bge_setpromisc(sc); 3755 3756 /* Program multicast filter. */ 3757 bge_setmulti(sc); 3758 3759 /* Init RX ring. */ 3760 bge_init_rx_ring_std(sc); 3761 3762 /* 3763 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 3764 * memory to insure that the chip has in fact read the first 3765 * entry of the ring. 3766 */ 3767 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 3768 uint32_t v, i; 3769 for (i = 0; i < 10; i++) { 3770 DELAY(20); 3771 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 3772 if (v == (MCLBYTES - ETHER_ALIGN)) 3773 break; 3774 } 3775 if (i == 10) 3776 device_printf (sc->bge_dev, 3777 "5705 A0 chip failed to load RX ring\n"); 3778 } 3779 3780 /* Init jumbo RX ring. */ 3781 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3782 bge_init_rx_ring_jumbo(sc); 3783 3784 /* Init our RX return ring index. */ 3785 sc->bge_rx_saved_considx = 0; 3786 3787 /* Init our RX/TX stat counters. */ 3788 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 3789 3790 /* Init TX ring. */ 3791 bge_init_tx_ring(sc); 3792 3793 /* Turn on transmitter. */ 3794 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3795 3796 /* Turn on receiver. */ 3797 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3798 3799 /* Tell firmware we're alive. */ 3800 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3801 3802 #ifdef DEVICE_POLLING 3803 /* Disable interrupts if we are polling. */ 3804 if (ifp->if_capenable & IFCAP_POLLING) { 3805 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 3806 BGE_PCIMISCCTL_MASK_PCI_INTR); 3807 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3808 } else 3809 #endif 3810 3811 /* Enable host interrupts. */ 3812 { 3813 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3814 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3815 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3816 } 3817 3818 bge_ifmedia_upd_locked(ifp); 3819 3820 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3821 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3822 3823 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 3824 } 3825 3826 static void 3827 bge_init(void *xsc) 3828 { 3829 struct bge_softc *sc = xsc; 3830 3831 BGE_LOCK(sc); 3832 bge_init_locked(sc); 3833 BGE_UNLOCK(sc); 3834 } 3835 3836 /* 3837 * Set media options. 3838 */ 3839 static int 3840 bge_ifmedia_upd(struct ifnet *ifp) 3841 { 3842 struct bge_softc *sc = ifp->if_softc; 3843 int res; 3844 3845 BGE_LOCK(sc); 3846 res = bge_ifmedia_upd_locked(ifp); 3847 BGE_UNLOCK(sc); 3848 3849 return (res); 3850 } 3851 3852 static int 3853 bge_ifmedia_upd_locked(struct ifnet *ifp) 3854 { 3855 struct bge_softc *sc = ifp->if_softc; 3856 struct mii_data *mii; 3857 struct ifmedia *ifm; 3858 3859 BGE_LOCK_ASSERT(sc); 3860 3861 ifm = &sc->bge_ifmedia; 3862 3863 /* If this is a 1000baseX NIC, enable the TBI port. */ 3864 if (sc->bge_flags & BGE_FLAG_TBI) { 3865 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3866 return (EINVAL); 3867 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3868 case IFM_AUTO: 3869 /* 3870 * The BCM5704 ASIC appears to have a special 3871 * mechanism for programming the autoneg 3872 * advertisement registers in TBI mode. 3873 */ 3874 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 3875 uint32_t sgdig; 3876 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 3877 if (sgdig & BGE_SGDIGSTS_DONE) { 3878 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 3879 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 3880 sgdig |= BGE_SGDIGCFG_AUTO | 3881 BGE_SGDIGCFG_PAUSE_CAP | 3882 BGE_SGDIGCFG_ASYM_PAUSE; 3883 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 3884 sgdig | BGE_SGDIGCFG_SEND); 3885 DELAY(5); 3886 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 3887 } 3888 } 3889 break; 3890 case IFM_1000_SX: 3891 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3892 BGE_CLRBIT(sc, BGE_MAC_MODE, 3893 BGE_MACMODE_HALF_DUPLEX); 3894 } else { 3895 BGE_SETBIT(sc, BGE_MAC_MODE, 3896 BGE_MACMODE_HALF_DUPLEX); 3897 } 3898 break; 3899 default: 3900 return (EINVAL); 3901 } 3902 return (0); 3903 } 3904 3905 sc->bge_link_evt++; 3906 mii = device_get_softc(sc->bge_miibus); 3907 if (mii->mii_instance) { 3908 struct mii_softc *miisc; 3909 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 3910 miisc = LIST_NEXT(miisc, mii_list)) 3911 mii_phy_reset(miisc); 3912 } 3913 mii_mediachg(mii); 3914 3915 return (0); 3916 } 3917 3918 /* 3919 * Report current media status. 3920 */ 3921 static void 3922 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3923 { 3924 struct bge_softc *sc = ifp->if_softc; 3925 struct mii_data *mii; 3926 3927 BGE_LOCK(sc); 3928 3929 if (sc->bge_flags & BGE_FLAG_TBI) { 3930 ifmr->ifm_status = IFM_AVALID; 3931 ifmr->ifm_active = IFM_ETHER; 3932 if (CSR_READ_4(sc, BGE_MAC_STS) & 3933 BGE_MACSTAT_TBI_PCS_SYNCHED) 3934 ifmr->ifm_status |= IFM_ACTIVE; 3935 else { 3936 ifmr->ifm_active |= IFM_NONE; 3937 BGE_UNLOCK(sc); 3938 return; 3939 } 3940 ifmr->ifm_active |= IFM_1000_SX; 3941 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3942 ifmr->ifm_active |= IFM_HDX; 3943 else 3944 ifmr->ifm_active |= IFM_FDX; 3945 BGE_UNLOCK(sc); 3946 return; 3947 } 3948 3949 mii = device_get_softc(sc->bge_miibus); 3950 mii_pollstat(mii); 3951 ifmr->ifm_active = mii->mii_media_active; 3952 ifmr->ifm_status = mii->mii_media_status; 3953 3954 BGE_UNLOCK(sc); 3955 } 3956 3957 static int 3958 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3959 { 3960 struct bge_softc *sc = ifp->if_softc; 3961 struct ifreq *ifr = (struct ifreq *) data; 3962 struct mii_data *mii; 3963 int flags, mask, error = 0; 3964 3965 switch (command) { 3966 case SIOCSIFMTU: 3967 if (ifr->ifr_mtu < ETHERMIN || 3968 ((BGE_IS_JUMBO_CAPABLE(sc)) && 3969 ifr->ifr_mtu > BGE_JUMBO_MTU) || 3970 ((!BGE_IS_JUMBO_CAPABLE(sc)) && 3971 ifr->ifr_mtu > ETHERMTU)) 3972 error = EINVAL; 3973 else if (ifp->if_mtu != ifr->ifr_mtu) { 3974 ifp->if_mtu = ifr->ifr_mtu; 3975 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3976 bge_init(sc); 3977 } 3978 break; 3979 case SIOCSIFFLAGS: 3980 BGE_LOCK(sc); 3981 if (ifp->if_flags & IFF_UP) { 3982 /* 3983 * If only the state of the PROMISC flag changed, 3984 * then just use the 'set promisc mode' command 3985 * instead of reinitializing the entire NIC. Doing 3986 * a full re-init means reloading the firmware and 3987 * waiting for it to start up, which may take a 3988 * second or two. Similarly for ALLMULTI. 3989 */ 3990 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3991 flags = ifp->if_flags ^ sc->bge_if_flags; 3992 if (flags & IFF_PROMISC) 3993 bge_setpromisc(sc); 3994 if (flags & IFF_ALLMULTI) 3995 bge_setmulti(sc); 3996 } else 3997 bge_init_locked(sc); 3998 } else { 3999 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4000 bge_stop(sc); 4001 } 4002 } 4003 sc->bge_if_flags = ifp->if_flags; 4004 BGE_UNLOCK(sc); 4005 error = 0; 4006 break; 4007 case SIOCADDMULTI: 4008 case SIOCDELMULTI: 4009 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4010 BGE_LOCK(sc); 4011 bge_setmulti(sc); 4012 BGE_UNLOCK(sc); 4013 error = 0; 4014 } 4015 break; 4016 case SIOCSIFMEDIA: 4017 case SIOCGIFMEDIA: 4018 if (sc->bge_flags & BGE_FLAG_TBI) { 4019 error = ifmedia_ioctl(ifp, ifr, 4020 &sc->bge_ifmedia, command); 4021 } else { 4022 mii = device_get_softc(sc->bge_miibus); 4023 error = ifmedia_ioctl(ifp, ifr, 4024 &mii->mii_media, command); 4025 } 4026 break; 4027 case SIOCSIFCAP: 4028 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 4029 #ifdef DEVICE_POLLING 4030 if (mask & IFCAP_POLLING) { 4031 if (ifr->ifr_reqcap & IFCAP_POLLING) { 4032 error = ether_poll_register(bge_poll, ifp); 4033 if (error) 4034 return (error); 4035 BGE_LOCK(sc); 4036 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 4037 BGE_PCIMISCCTL_MASK_PCI_INTR); 4038 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4039 ifp->if_capenable |= IFCAP_POLLING; 4040 BGE_UNLOCK(sc); 4041 } else { 4042 error = ether_poll_deregister(ifp); 4043 /* Enable interrupt even in error case */ 4044 BGE_LOCK(sc); 4045 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 4046 BGE_PCIMISCCTL_MASK_PCI_INTR); 4047 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4048 ifp->if_capenable &= ~IFCAP_POLLING; 4049 BGE_UNLOCK(sc); 4050 } 4051 } 4052 #endif 4053 if (mask & IFCAP_HWCSUM) { 4054 ifp->if_capenable ^= IFCAP_HWCSUM; 4055 if (IFCAP_HWCSUM & ifp->if_capenable && 4056 IFCAP_HWCSUM & ifp->if_capabilities) 4057 ifp->if_hwassist = BGE_CSUM_FEATURES; 4058 else 4059 ifp->if_hwassist = 0; 4060 #ifdef VLAN_CAPABILITIES 4061 VLAN_CAPABILITIES(ifp); 4062 #endif 4063 } 4064 break; 4065 default: 4066 error = ether_ioctl(ifp, command, data); 4067 break; 4068 } 4069 4070 return (error); 4071 } 4072 4073 static void 4074 bge_watchdog(struct bge_softc *sc) 4075 { 4076 struct ifnet *ifp; 4077 4078 BGE_LOCK_ASSERT(sc); 4079 4080 if (sc->bge_timer == 0 || --sc->bge_timer) 4081 return; 4082 4083 ifp = sc->bge_ifp; 4084 4085 if_printf(ifp, "watchdog timeout -- resetting\n"); 4086 4087 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4088 bge_init_locked(sc); 4089 4090 ifp->if_oerrors++; 4091 } 4092 4093 /* 4094 * Stop the adapter and free any mbufs allocated to the 4095 * RX and TX lists. 4096 */ 4097 static void 4098 bge_stop(struct bge_softc *sc) 4099 { 4100 struct ifnet *ifp; 4101 struct ifmedia_entry *ifm; 4102 struct mii_data *mii = NULL; 4103 int mtmp, itmp; 4104 4105 BGE_LOCK_ASSERT(sc); 4106 4107 ifp = sc->bge_ifp; 4108 4109 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) 4110 mii = device_get_softc(sc->bge_miibus); 4111 4112 callout_stop(&sc->bge_stat_ch); 4113 4114 /* 4115 * Disable all of the receiver blocks. 4116 */ 4117 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4118 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4119 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4120 if (!(BGE_IS_5705_PLUS(sc))) 4121 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4122 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4123 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4124 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4125 4126 /* 4127 * Disable all of the transmit blocks. 4128 */ 4129 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4130 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4131 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4132 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4133 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4134 if (!(BGE_IS_5705_PLUS(sc))) 4135 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4136 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4137 4138 /* 4139 * Shut down all of the memory managers and related 4140 * state machines. 4141 */ 4142 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4143 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4144 if (!(BGE_IS_5705_PLUS(sc))) 4145 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4146 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4147 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4148 if (!(BGE_IS_5705_PLUS(sc))) { 4149 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4150 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4151 } 4152 4153 /* Disable host interrupts. */ 4154 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4155 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4156 4157 /* 4158 * Tell firmware we're shutting down. 4159 */ 4160 4161 bge_stop_fw(sc); 4162 bge_sig_pre_reset(sc, BGE_RESET_STOP); 4163 bge_reset(sc); 4164 bge_sig_legacy(sc, BGE_RESET_STOP); 4165 bge_sig_post_reset(sc, BGE_RESET_STOP); 4166 4167 /* 4168 * Keep the ASF firmware running if up. 4169 */ 4170 if (sc->bge_asf_mode & ASF_STACKUP) 4171 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4172 else 4173 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4174 4175 /* Free the RX lists. */ 4176 bge_free_rx_ring_std(sc); 4177 4178 /* Free jumbo RX list. */ 4179 if (BGE_IS_JUMBO_CAPABLE(sc)) 4180 bge_free_rx_ring_jumbo(sc); 4181 4182 /* Free TX buffers. */ 4183 bge_free_tx_ring(sc); 4184 4185 /* 4186 * Isolate/power down the PHY, but leave the media selection 4187 * unchanged so that things will be put back to normal when 4188 * we bring the interface back up. 4189 */ 4190 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 4191 itmp = ifp->if_flags; 4192 ifp->if_flags |= IFF_UP; 4193 /* 4194 * If we are called from bge_detach(), mii is already NULL. 4195 */ 4196 if (mii != NULL) { 4197 ifm = mii->mii_media.ifm_cur; 4198 mtmp = ifm->ifm_media; 4199 ifm->ifm_media = IFM_ETHER | IFM_NONE; 4200 mii_mediachg(mii); 4201 ifm->ifm_media = mtmp; 4202 } 4203 ifp->if_flags = itmp; 4204 } 4205 4206 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4207 4208 /* Clear MAC's link state (PHY may still have link UP). */ 4209 if (bootverbose && sc->bge_link) 4210 if_printf(sc->bge_ifp, "link DOWN\n"); 4211 sc->bge_link = 0; 4212 4213 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4214 } 4215 4216 /* 4217 * Stop all chip I/O so that the kernel's probe routines don't 4218 * get confused by errant DMAs when rebooting. 4219 */ 4220 static void 4221 bge_shutdown(device_t dev) 4222 { 4223 struct bge_softc *sc; 4224 4225 sc = device_get_softc(dev); 4226 4227 BGE_LOCK(sc); 4228 bge_stop(sc); 4229 bge_reset(sc); 4230 BGE_UNLOCK(sc); 4231 } 4232 4233 static int 4234 bge_suspend(device_t dev) 4235 { 4236 struct bge_softc *sc; 4237 4238 sc = device_get_softc(dev); 4239 BGE_LOCK(sc); 4240 bge_stop(sc); 4241 BGE_UNLOCK(sc); 4242 4243 return (0); 4244 } 4245 4246 static int 4247 bge_resume(device_t dev) 4248 { 4249 struct bge_softc *sc; 4250 struct ifnet *ifp; 4251 4252 sc = device_get_softc(dev); 4253 BGE_LOCK(sc); 4254 ifp = sc->bge_ifp; 4255 if (ifp->if_flags & IFF_UP) { 4256 bge_init_locked(sc); 4257 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4258 bge_start_locked(ifp); 4259 } 4260 BGE_UNLOCK(sc); 4261 4262 return (0); 4263 } 4264 4265 static void 4266 bge_link_upd(struct bge_softc *sc) 4267 { 4268 struct mii_data *mii; 4269 uint32_t link, status; 4270 4271 BGE_LOCK_ASSERT(sc); 4272 4273 /* Clear 'pending link event' flag. */ 4274 sc->bge_link_evt = 0; 4275 4276 /* 4277 * Process link state changes. 4278 * Grrr. The link status word in the status block does 4279 * not work correctly on the BCM5700 rev AX and BX chips, 4280 * according to all available information. Hence, we have 4281 * to enable MII interrupts in order to properly obtain 4282 * async link changes. Unfortunately, this also means that 4283 * we have to read the MAC status register to detect link 4284 * changes, thereby adding an additional register access to 4285 * the interrupt handler. 4286 * 4287 * XXX: perhaps link state detection procedure used for 4288 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 4289 */ 4290 4291 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4292 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 4293 status = CSR_READ_4(sc, BGE_MAC_STS); 4294 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4295 mii = device_get_softc(sc->bge_miibus); 4296 mii_pollstat(mii); 4297 if (!sc->bge_link && 4298 mii->mii_media_status & IFM_ACTIVE && 4299 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4300 sc->bge_link++; 4301 if (bootverbose) 4302 if_printf(sc->bge_ifp, "link UP\n"); 4303 } else if (sc->bge_link && 4304 (!(mii->mii_media_status & IFM_ACTIVE) || 4305 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4306 sc->bge_link = 0; 4307 if (bootverbose) 4308 if_printf(sc->bge_ifp, "link DOWN\n"); 4309 } 4310 4311 /* Clear the interrupt. */ 4312 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4313 BGE_EVTENB_MI_INTERRUPT); 4314 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4315 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4316 BRGPHY_INTRS); 4317 } 4318 return; 4319 } 4320 4321 if (sc->bge_flags & BGE_FLAG_TBI) { 4322 status = CSR_READ_4(sc, BGE_MAC_STS); 4323 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4324 if (!sc->bge_link) { 4325 sc->bge_link++; 4326 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 4327 BGE_CLRBIT(sc, BGE_MAC_MODE, 4328 BGE_MACMODE_TBI_SEND_CFGS); 4329 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4330 if (bootverbose) 4331 if_printf(sc->bge_ifp, "link UP\n"); 4332 if_link_state_change(sc->bge_ifp, 4333 LINK_STATE_UP); 4334 } 4335 } else if (sc->bge_link) { 4336 sc->bge_link = 0; 4337 if (bootverbose) 4338 if_printf(sc->bge_ifp, "link DOWN\n"); 4339 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 4340 } 4341 } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) { 4342 /* 4343 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 4344 * in status word always set. Workaround this bug by reading 4345 * PHY link status directly. 4346 */ 4347 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 4348 4349 if (link != sc->bge_link || 4350 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 4351 mii = device_get_softc(sc->bge_miibus); 4352 mii_pollstat(mii); 4353 if (!sc->bge_link && 4354 mii->mii_media_status & IFM_ACTIVE && 4355 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4356 sc->bge_link++; 4357 if (bootverbose) 4358 if_printf(sc->bge_ifp, "link UP\n"); 4359 } else if (sc->bge_link && 4360 (!(mii->mii_media_status & IFM_ACTIVE) || 4361 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4362 sc->bge_link = 0; 4363 if (bootverbose) 4364 if_printf(sc->bge_ifp, "link DOWN\n"); 4365 } 4366 } 4367 } else { 4368 /* 4369 * Discard link events for MII/GMII controllers 4370 * if MI auto-polling is disabled. 4371 */ 4372 } 4373 4374 /* Clear the attention. */ 4375 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4376 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4377 BGE_MACSTAT_LINK_CHANGED); 4378 } 4379 4380 static void 4381 bge_add_sysctls(struct bge_softc *sc) 4382 { 4383 struct sysctl_ctx_list *ctx; 4384 struct sysctl_oid_list *children; 4385 4386 ctx = device_get_sysctl_ctx(sc->bge_dev); 4387 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 4388 4389 #ifdef BGE_REGISTER_DEBUG 4390 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 4391 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 4392 "Debug Information"); 4393 4394 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 4395 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 4396 "Register Read"); 4397 4398 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 4399 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 4400 "Memory Read"); 4401 4402 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "stat_IfHcInOctets", 4403 CTLFLAG_RD, 4404 &sc->bge_ldata.bge_stats->rxstats.ifHCInOctets.bge_addr_lo, 4405 "Bytes received"); 4406 4407 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "stat_IfHcOutOctets", 4408 CTLFLAG_RD, 4409 &sc->bge_ldata.bge_stats->txstats.ifHCOutOctets.bge_addr_lo, 4410 "Bytes received"); 4411 #endif 4412 } 4413 4414 #ifdef BGE_REGISTER_DEBUG 4415 static int 4416 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4417 { 4418 struct bge_softc *sc; 4419 uint16_t *sbdata; 4420 int error; 4421 int result; 4422 int i, j; 4423 4424 result = -1; 4425 error = sysctl_handle_int(oidp, &result, 0, req); 4426 if (error || (req->newptr == NULL)) 4427 return (error); 4428 4429 if (result == 1) { 4430 sc = (struct bge_softc *)arg1; 4431 4432 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 4433 printf("Status Block:\n"); 4434 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) { 4435 printf("%06x:", i); 4436 for (j = 0; j < 8; j++) { 4437 printf(" %04x", sbdata[i]); 4438 i += 4; 4439 } 4440 printf("\n"); 4441 } 4442 4443 printf("Registers:\n"); 4444 for (i = 0x800; i < 0xA00; ) { 4445 printf("%06x:", i); 4446 for (j = 0; j < 8; j++) { 4447 printf(" %08x", CSR_READ_4(sc, i)); 4448 i += 4; 4449 } 4450 printf("\n"); 4451 } 4452 4453 printf("Hardware Flags:\n"); 4454 if (BGE_IS_575X_PLUS(sc)) 4455 printf(" - 575X Plus\n"); 4456 if (BGE_IS_5705_PLUS(sc)) 4457 printf(" - 5705 Plus\n"); 4458 if (BGE_IS_5714_FAMILY(sc)) 4459 printf(" - 5714 Family\n"); 4460 if (BGE_IS_5700_FAMILY(sc)) 4461 printf(" - 5700 Family\n"); 4462 if (sc->bge_flags & BGE_FLAG_JUMBO) 4463 printf(" - Supports Jumbo Frames\n"); 4464 if (sc->bge_flags & BGE_FLAG_PCIX) 4465 printf(" - PCI-X Bus\n"); 4466 if (sc->bge_flags & BGE_FLAG_PCIE) 4467 printf(" - PCI Express Bus\n"); 4468 if (sc->bge_flags & BGE_FLAG_NO_3LED) 4469 printf(" - No 3 LEDs\n"); 4470 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 4471 printf(" - RX Alignment Bug\n"); 4472 } 4473 4474 return (error); 4475 } 4476 4477 static int 4478 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 4479 { 4480 struct bge_softc *sc; 4481 int error; 4482 uint16_t result; 4483 uint32_t val; 4484 4485 result = -1; 4486 error = sysctl_handle_int(oidp, &result, 0, req); 4487 if (error || (req->newptr == NULL)) 4488 return (error); 4489 4490 if (result < 0x8000) { 4491 sc = (struct bge_softc *)arg1; 4492 val = CSR_READ_4(sc, result); 4493 printf("reg 0x%06X = 0x%08X\n", result, val); 4494 } 4495 4496 return (error); 4497 } 4498 4499 static int 4500 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 4501 { 4502 struct bge_softc *sc; 4503 int error; 4504 uint16_t result; 4505 uint32_t val; 4506 4507 result = -1; 4508 error = sysctl_handle_int(oidp, &result, 0, req); 4509 if (error || (req->newptr == NULL)) 4510 return (error); 4511 4512 if (result < 0x8000) { 4513 sc = (struct bge_softc *)arg1; 4514 val = bge_readmem_ind(sc, result); 4515 printf("mem 0x%06X = 0x%08X\n", result, val); 4516 } 4517 4518 return (error); 4519 } 4520 #endif 4521 4522 static int 4523 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 4524 { 4525 4526 if (sc->bge_flags & BGE_FLAG_EADDR) 4527 return (1); 4528 4529 #ifdef __sparc64__ 4530 OF_getetheraddr(sc->bge_dev, ether_addr); 4531 return (0); 4532 #endif 4533 return (1); 4534 } 4535 4536 static int 4537 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 4538 { 4539 uint32_t mac_addr; 4540 4541 mac_addr = bge_readmem_ind(sc, 0x0c14); 4542 if ((mac_addr >> 16) == 0x484b) { 4543 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4544 ether_addr[1] = (uint8_t)mac_addr; 4545 mac_addr = bge_readmem_ind(sc, 0x0c18); 4546 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4547 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4548 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4549 ether_addr[5] = (uint8_t)mac_addr; 4550 return (0); 4551 } 4552 return (1); 4553 } 4554 4555 static int 4556 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 4557 { 4558 int mac_offset = BGE_EE_MAC_OFFSET; 4559 4560 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 4561 mac_offset = BGE_EE_MAC_OFFSET_5906; 4562 4563 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 4564 ETHER_ADDR_LEN)); 4565 } 4566 4567 static int 4568 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 4569 { 4570 4571 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 4572 return (1); 4573 4574 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4575 ETHER_ADDR_LEN)); 4576 } 4577 4578 static int 4579 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 4580 { 4581 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 4582 /* NOTE: Order is critical */ 4583 bge_get_eaddr_fw, 4584 bge_get_eaddr_mem, 4585 bge_get_eaddr_nvram, 4586 bge_get_eaddr_eeprom, 4587 NULL 4588 }; 4589 const bge_eaddr_fcn_t *func; 4590 4591 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 4592 if ((*func)(sc, eaddr) == 0) 4593 break; 4594 } 4595 return (*func == NULL ? ENXIO : 0); 4596 }
Cache object: 28d026a18a74db0f0152c38d516b56d9
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